ARM: OMAP: Fix 32 kHz timer and modify GP timer to use GPT1

The dmtimer framework update broke 32 kHz timer as udelay() does not work
before system timer is started (and GPT1 should not be reset).
This also makes the GP timer use GPT1. This requires a fix in clock framework.
Signed-off-by: NTimo Teras <timo.teras@solidboot.com>
Signed-off-by: NJuha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

arch/arm/mach-omap2/clock.c

@@ -753,7 +753,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 			val = 0x2;
 		break;
 	case CM_WKUP_SEL1:
-		src_reg_addr = (u32)&CM_CLKSEL2_CORE;
+		src_reg_addr = (u32)&CM_CLKSEL_WKUP;
 		mask = 0x3;
 		if (src_clk == &func_32k_ck)
 			val = 0x0;

arch/arm/mach-omap2/timer-gp.c

@@ -61,7 +61,7 @@ static void __init omap2_gp_timer_init(void)
 	u32 tick_period;
 
 	omap_dm_timer_init();
-	gptimer = omap_dm_timer_request_specific(2);
+	gptimer = omap_dm_timer_request_specific(1);
 	BUG_ON(gptimer == NULL);
 
 	omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);

arch/arm/plat-omap/dmtimer.c

@@ -147,9 +147,10 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
 {
 	u32 l;
 
-	omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
-	omap_dm_timer_wait_for_reset(timer);
-
+	if (timer != &dm_timers[0]) {
+		omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
+		omap_dm_timer_wait_for_reset(timer);
+	}
 	omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK);
 
 	/* Set to smart-idle mode */
@@ -335,7 +336,7 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 
 	/* When the functional clock disappears, too quick writes seem to
 	 * cause an abort. */
-	udelay(50);
+	__delay(15000);
 }
 
 #endif