The sdm845 SOC ships with a CCI controller, which
has two CCI/I2C buses.
Signed-off-by: NRobert Foss <robert.foss@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200324155843.10719-4-robert.foss@linaro.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Add IPA-related nodes and definitions to "sdm845.dtsi".
Signed-off-by: NAlex Elder <elder@linaro.org>
Link: https://lore.kernel.org/r/20200313115237.10491-2-elder@linaro.org
[bjorn: Moved modem-init to cheza.dtsi]
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Add pinctrl nodes required for QUAT I2S
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Tested-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20200312143024.11059-5-srinivas.kandagatla@linaro.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Reviewed-by: NVinod Koul <vkoul@kernel.org>
Tested-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20200312143024.11059-3-srinivas.kandagatla@linaro.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Reviewed-by: NVinod Koul <vkoul@kernel.org>
Tested-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20200312143024.11059-2-srinivas.kandagatla@linaro.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

This reverts commit 9cc5ae12.

This commit:
  b303f9f0 arm64: dts: sdm845: Redefine interconnect provider DT nodes
found in the Qualcomm for-next tree removes/redefines the interconnect
provider node(s) used for IPA.  I'm not sure whether it technically
conflicts with the IPA change to "sdm845.dtsi" in for-next, but it renders
it broken.

Revert this commit in the for-next tree, with the plan to incorporate
it into the Qualcomm tree instead.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add IPA-related nodes and definitions to "sdm845.dtsi".
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add Operation State Manager (OSM) L3 interconnect provider on SDM845 SoCs.
Acked-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: NEvan Green <evgreen@chromium.org>
Signed-off-by: NSibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200227105632.15041-7-sibis@codeaurora.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Add the DT nodes for each of the Network-On-Chip interconnect
buses found on SDM845 based platform and redefine the rsc_hlos
child node as a bcm-voter device to better represent the hardware.
Reviewed-by: NEvan Green <evgreen@chromium.org>
Acked-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NDavid Dai <daidavid1@codeaurora.org>
Signed-off-by: NOdelu Kukatla <okukatla@codeaurora.org>
Signed-off-by: NSibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200209183411.17195-7-sibis@codeaurora.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Move all pmdomain and clock resources to Venus DT node. And make
possible to support dynamic core assignment on v4.
Signed-off-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Link: https://lore.kernel.org/r/20200106154929.4331-12-stanimir.varbanov@linaro.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

We're transitioning over to requiring the Qualcomm Video Clock
Controller to specify all the input clocks.  Let's add the one input
clock for the videocc for sdm845.

NOTE: Until the Linux driver for sdm845's video is updated, this clock
will not actually be used in Linux.  It will continue to use global
clock names to match things up.
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200203103049.v4.14.Id0599319487f075808baba7cba02c4c3c486dc80@changeidSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

We're transitioning over to requiring the Qualcomm GPU Clock
Controller to specify all the input clocks.  Let's add them for
sdm845.

As part of this we've decided that the xo clock should be referred to
in the bindings as "bi_tcxo".  Change the dts.

NOTE: Until the Linux driver for sdm845's gpucc is updated, these
clocks will not actually be used in Linux.  It will continue to use
global clock names to match things up.  Of course, Linux didn't use
the old "xo" clock anyway.
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200203103049.v4.8.If8596faf02408cef4bb9f52296b911eb9ba49287@changeidSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

We're transitioning over to requiring the Qualcomm Display Clock
Controller to specify all the input clocks.  Let's add them for
sdm845.

NOTES:
- Until the Linux driver for sdm845's dispcc is updated, these clocks
  will not actually be used in Linux.  It will continue to use global
  clock names to match things up.
- Although the clocks from the DP PHY are required, the DP PHY isn't
  represented in the dts yet.  Apparently the magic for this is just
  to use <0>.
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200203103049.v4.3.Ie80fa74e1774f4317d80d70d30ef4b78f16cc8df@changeidSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Cheza boards require this node to probe, so add it.
Reviewed-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: NAlexandre Courbot <acourbot@chromium.org>
Link: https://lore.kernel.org/r/20200108032623.113921-1-acourbot@chromium.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Add the second PCIe controller and the associated QHP PHY found on
SDM845.
Tested-by: NJulien Massot <jmassot@softbankrobotics.com>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191107002247.1127689-3-bjorn.andersson@linaro.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Add the GEN2 PCIe controller and PHY found on SDM845.
Tested-by: NJulien Massot <jmassot@softbankrobotics.com>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191107002247.1127689-2-bjorn.andersson@linaro.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

We want to specify per-device firmware-name, so move the zap node into
the .dts file for individual boards/devices.  This lets us get rid of
the /delete-node/ for cheza, which does not use zap.
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NRob Clark <robdclark@chromium.org>
Link: https://lore.kernel.org/r/20200112195405.1132288-5-robdclark@gmail.comSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Add the core UFS reset for sdm845
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20200106070826.147064-4-vkoul@kernel.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

This is just like commit ac00546a ("arm64: dts: qcom: sc7180:
Rename gic-its node to msi-controller") but for sdm845.  This fixes
all arm64/qcom device trees that I could find.
Reviewed-by: NRajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191216222021.1.I684f124a05a1c3f0b113c8d06d5f9da5d69b801e@changeidSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

LLCC cache-controller was renamed to system-cache-controller
to make schema pass the dt binding check. Update the device
tree node to reflect this change.
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NSai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/a2bb92de65e90768bf1d6b8c0b7fbd43cba704d2.1573814758.git.saiprakash.ranjan@codeaurora.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

PDC always-on interrupt controller can detect certain GPIOs even when
the TLMM interrupt controller is powered off. Link the PDC as TLMM's
wakeup parent.
Signed-off-by: NLina Iyer <ilina@codeaurora.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1573855915-9841-12-git-send-email-ilina@codeaurora.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: NLina Iyer <ilina@codeaurora.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1573855915-9841-11-git-send-email-ilina@codeaurora.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Register critical interrupts for each of the two tsens controllers
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Link: https://lore.kernel.org/r/c536e9cdb448bbad3441f6580fa57f1f921fb580.1573499020.git.amit.kucheria@linaro.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

This is unused on cheza.  Delete the node to get ride of the reserved-
memory section, and to avoid the driver from attempting to load a zap
shader that doesn't exist every time it powers up the GPU.

This also avoids a massive amount of dmesg spam about missing zap fw:
  msm ae00000.mdss: [drm:adreno_request_fw] *ERROR* failed to load
qcom/a630_zap.mdt: -2
  adreno 5000000.gpu: [drm:adreno_zap_shader_load] *ERROR* Unable to
load a630_zap.mdt
Signed-off-by: NRob Clark <robdclark@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Fixes: 3fdeaee9 ("arm64: dts: sdm845: Add zap shader region for GPU")
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Tested-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Register upper-lower interrupts for each of the two tsens controllers.
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Add a node describing the watchdog found in the application subsystem.
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

RPM clock controller has parent as xo, so specify that in DT node for
rpmhcc
Reviewed-by: NStephen Boyd <sboyd@kernel.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Add fastrpc compute context bank nodes to both cdsp and adsp.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Add dynamic power coefficients for the Silver and Gold CPU cores of
the Qualcomm SDM845.
Signed-off-by: NMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Reviewed-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

AOSS hosts resources that can be used to warm up the SoC.
Add nodes for these resources.
Signed-off-by: NThara Gopinath <thara.gopinath@linaro.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: NSai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Last level cache (aka. system cache) controller provides control
over the last level cache present on SDM845. This cache lies after
the memory noc, right before the DDR.
Signed-off-by: NSai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

The thermal trip points have unit name but no reg property, so we can
remove them

arch/arm64/boot/dts/qcom/sdm845.dtsi:2824.31-2828.7: Warning (unit_address_vs_reg): /thermal-zones/cpu0-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:2830.31-2834.7: Warning (unit_address_vs_reg): /thermal-zones/cpu0-thermal/trips/trip-point@1: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:2868.31-2872.7: Warning (unit_address_vs_reg): /thermal-zones/cpu1-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:2874.31-2878.7: Warning (unit_address_vs_reg): /thermal-zones/cpu1-thermal/trips/trip-point@1: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:2912.31-2916.7: Warning (unit_address_vs_reg): /thermal-zones/cpu2-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:2918.31-2922.7: Warning (unit_address_vs_reg): /thermal-zones/cpu2-thermal/trips/trip-point@1: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:2956.31-2960.7: Warning (unit_address_vs_reg): /thermal-zones/cpu3-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:2962.31-2966.7: Warning (unit_address_vs_reg): /thermal-zones/cpu3-thermal/trips/trip-point@1: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3000.31-3004.7: Warning (unit_address_vs_reg): /thermal-zones/cpu4-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3006.31-3010.7: Warning (unit_address_vs_reg): /thermal-zones/cpu4-thermal/trips/trip-point@1: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3044.31-3048.7: Warning (unit_address_vs_reg): /thermal-zones/cpu5-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3050.31-3054.7: Warning (unit_address_vs_reg): /thermal-zones/cpu5-thermal/trips/trip-point@1: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3088.31-3092.7: Warning (unit_address_vs_reg): /thermal-zones/cpu6-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3094.31-3098.7: Warning (unit_address_vs_reg): /thermal-zones/cpu6-thermal/trips/trip-point@1: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3132.31-3136.7: Warning (unit_address_vs_reg): /thermal-zones/cpu7-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3138.31-3142.7: Warning (unit_address_vs_reg): /thermal-zones/cpu7-thermal/trips/trip-point@1: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3176.32-3180.7: Warning (unit_address_vs_reg): /thermal-zones/aoss0-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3191.35-3195.7: Warning (unit_address_vs_reg): /thermal-zones/cluster0-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3211.35-3215.7: Warning (unit_address_vs_reg): /thermal-zones/cluster1-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3231.31-3235.7: Warning (unit_address_vs_reg): /thermal-zones/gpu-thermal-top/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3246.31-3250.7: Warning (unit_address_vs_reg): /thermal-zones/gpu-thermal-bottom/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3261.32-3265.7: Warning (unit_address_vs_reg): /thermal-zones/aoss1-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3276.35-3280.7: Warning (unit_address_vs_reg): /thermal-zones/q6-modem-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3291.30-3295.7: Warning (unit_address_vs_reg): /thermal-zones/mem-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3306.31-3310.7: Warning (unit_address_vs_reg): /thermal-zones/wlan-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3321.33-3325.7: Warning (unit_address_vs_reg): /thermal-zones/q6-hvx-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3336.33-3340.7: Warning (unit_address_vs_reg): /thermal-zones/camera-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3351.32-3355.7: Warning (unit_address_vs_reg): /thermal-zones/video-thermal/trips/trip-point@0: node has a unit name, but no reg property
arch/arm64/boot/dts/qcom/sdm845.dtsi:3366.32-3370.7: Warning (unit_address_vs_reg): /thermal-zones/modem-thermal/trips/trip-point@0: node has a unit name, but no reg property
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Reviewed-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

We get a warning about unnecessary properties of

arch/arm64/boot/dts/qcom/sdm845.dtsi:2211.22-2257.6: Warning (avoid_unnecessary_addr_size): /soc/mdss@ae00000/dsi@ae94000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
arch/arm64/boot/dts/qcom/sdm845.dtsi:2278.22-2324.6: Warning (avoid_unnecessary_addr_size): /soc/mdss@ae00000/dsi@ae96000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property

So, remove these properties
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Reviewed-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

We get a warning about missing unit name for soc node, so add it.

arch/arm64/boot/dts/qcom/sdm845.dtsi:623.11-2814.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Reviewed-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

This adds video nodes to sdm845 based on the examples
in the bindings.
Tested-by: NAn\355bal Lim\363n <anibal.limon@linaro.org>
Reviewed-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NMalathi Gottam <mgottam@codeaurora.org>
Co-developed-by: NAniket Masule <amasule@codeaurora.org>
Signed-off-by: NAniket Masule <amasule@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

This patch adds Q6V5 MSS remoteproc node for SDM845 SoCs.
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NSibi Sankar <sibis@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

The AOSS QMP provides a number of power domains, used for QDSS and
PIL, add the node for this.
Tested-by: NSibi Sankar <sibis@codeaurora.org>
Reviewed-by: NSibi Sankar <sibis@codeaurora.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Add device bindings for cpuidle states for cpu devices.

Cc: <mkshah@codeaurora.org>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: NEvan Green <evgreen@chromium.org>
Signed-off-by: NRaju P.L.S.S.S.N <rplsssn@codeaurora.org>
[amit: rename the idle-states to more generic names and fixups]
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Some Adreno GPU targets require a special zap shader to bring the GPU
out of secure mode. Define a region to allocate and store the zap
shader.
Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org>
[bjorn: Rebase ontop of recent reserved-memory patch]
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>