at91rm9200_devices.c 30.3 KB
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/*
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 * arch/arm/mach-at91/at91rm9200_devices.c
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 *
 *  Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
 *  Copyright (C) 2005 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */
#include <asm/mach/arch.h>
#include <asm/mach/map.h>

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#include <linux/dma-mapping.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/i2c-gpio.h>
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#include <mach/board.h>
#include <mach/at91rm9200.h>
#include <mach/at91rm9200_mc.h>
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#include <mach/at91_ramc.h>
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#include "generic.h"

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/* --------------------------------------------------------------------
 *  USB Host
 * -------------------------------------------------------------------- */

#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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static u64 ohci_dmamask = DMA_BIT_MASK(32);
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static struct at91_usbh_data usbh_data;

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static struct resource usbh_resources[] = {
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	[0] = {
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		.start	= AT91RM9200_UHP_BASE,
		.end	= AT91RM9200_UHP_BASE + SZ_1M - 1,
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		.flags	= IORESOURCE_MEM,
	},
	[1] = {
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		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
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		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device at91rm9200_usbh_device = {
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	.name		= "at91_ohci",
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	.id		= -1,
	.dev		= {
				.dma_mask		= &ohci_dmamask,
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				.coherent_dma_mask	= DMA_BIT_MASK(32),
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				.platform_data		= &usbh_data,
	},
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	.resource	= usbh_resources,
	.num_resources	= ARRAY_SIZE(usbh_resources),
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};

void __init at91_add_device_usbh(struct at91_usbh_data *data)
{
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	int i;

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	if (!data)
		return;

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	/* Enable overcurrent notification */
	for (i = 0; i < data->ports; i++) {
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		if (gpio_is_valid(data->overcurrent_pin[i]))
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			at91_set_gpio_input(data->overcurrent_pin[i], 1);
	}

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	usbh_data = *data;
	platform_device_register(&at91rm9200_usbh_device);
}
#else
void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
#endif


/* --------------------------------------------------------------------
 *  USB Device (Gadget)
 * -------------------------------------------------------------------- */

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#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
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static struct at91_udc_data udc_data;

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static struct resource udc_resources[] = {
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	[0] = {
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		.start	= AT91RM9200_BASE_UDP,
		.end	= AT91RM9200_BASE_UDP + SZ_16K - 1,
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		.flags	= IORESOURCE_MEM,
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	},
	[1] = {
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		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
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		.flags	= IORESOURCE_IRQ,
	},
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};

static struct platform_device at91rm9200_udc_device = {
	.name		= "at91_udc",
	.id		= -1,
	.dev		= {
				.platform_data		= &udc_data,
	},
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	.resource	= udc_resources,
	.num_resources	= ARRAY_SIZE(udc_resources),
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};

void __init at91_add_device_udc(struct at91_udc_data *data)
{
	if (!data)
		return;

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	if (gpio_is_valid(data->vbus_pin)) {
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		at91_set_gpio_input(data->vbus_pin, 0);
		at91_set_deglitch(data->vbus_pin, 1);
	}
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	if (gpio_is_valid(data->pullup_pin))
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		at91_set_gpio_output(data->pullup_pin, 0);

	udc_data = *data;
	platform_device_register(&at91rm9200_udc_device);
}
#else
void __init at91_add_device_udc(struct at91_udc_data *data) {}
#endif


/* --------------------------------------------------------------------
 *  Ethernet
 * -------------------------------------------------------------------- */

#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
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static u64 eth_dmamask = DMA_BIT_MASK(32);
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static struct macb_platform_data eth_data;
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static struct resource eth_resources[] = {
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	[0] = {
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		.start	= AT91RM9200_BASE_EMAC,
		.end	= AT91RM9200_BASE_EMAC + SZ_16K - 1,
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		.flags	= IORESOURCE_MEM,
	},
	[1] = {
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		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
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		.flags	= IORESOURCE_IRQ,
	},
};

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static struct platform_device at91rm9200_eth_device = {
	.name		= "at91_ether",
	.id		= -1,
	.dev		= {
				.dma_mask		= &eth_dmamask,
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				.coherent_dma_mask	= DMA_BIT_MASK(32),
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				.platform_data		= &eth_data,
	},
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	.resource	= eth_resources,
	.num_resources	= ARRAY_SIZE(eth_resources),
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};

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void __init at91_add_device_eth(struct macb_platform_data *data)
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{
	if (!data)
		return;

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	if (gpio_is_valid(data->phy_irq_pin)) {
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		at91_set_gpio_input(data->phy_irq_pin, 0);
		at91_set_deglitch(data->phy_irq_pin, 1);
	}

	/* Pins used for MII and RMII */
	at91_set_A_periph(AT91_PIN_PA16, 0);	/* EMDIO */
	at91_set_A_periph(AT91_PIN_PA15, 0);	/* EMDC */
	at91_set_A_periph(AT91_PIN_PA14, 0);	/* ERXER */
	at91_set_A_periph(AT91_PIN_PA13, 0);	/* ERX1 */
	at91_set_A_periph(AT91_PIN_PA12, 0);	/* ERX0 */
	at91_set_A_periph(AT91_PIN_PA11, 0);	/* ECRS_ECRSDV */
	at91_set_A_periph(AT91_PIN_PA10, 0);	/* ETX1 */
	at91_set_A_periph(AT91_PIN_PA9, 0);	/* ETX0 */
	at91_set_A_periph(AT91_PIN_PA8, 0);	/* ETXEN */
	at91_set_A_periph(AT91_PIN_PA7, 0);	/* ETXCK_EREFCK */

	if (!data->is_rmii) {
		at91_set_B_periph(AT91_PIN_PB19, 0);	/* ERXCK */
		at91_set_B_periph(AT91_PIN_PB18, 0);	/* ECOL */
		at91_set_B_periph(AT91_PIN_PB17, 0);	/* ERXDV */
		at91_set_B_periph(AT91_PIN_PB16, 0);	/* ERX3 */
		at91_set_B_periph(AT91_PIN_PB15, 0);	/* ERX2 */
		at91_set_B_periph(AT91_PIN_PB14, 0);	/* ETXER */
		at91_set_B_periph(AT91_PIN_PB13, 0);	/* ETX3 */
		at91_set_B_periph(AT91_PIN_PB12, 0);	/* ETX2 */
	}

	eth_data = *data;
	platform_device_register(&at91rm9200_eth_device);
}
#else
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void __init at91_add_device_eth(struct macb_platform_data *data) {}
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#endif


/* --------------------------------------------------------------------
 *  Compact Flash / PCMCIA
 * -------------------------------------------------------------------- */

#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
static struct at91_cf_data cf_data;

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#define CF_BASE		AT91_CHIPSELECT_4

static struct resource cf_resources[] = {
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	[0] = {
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		.start	= CF_BASE,
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		/* ties up CS4, CS5 and CS6 */
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		.end	= CF_BASE + (0x30000000 - 1),
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		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
	},
};

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static struct platform_device at91rm9200_cf_device = {
	.name		= "at91_cf",
	.id		= -1,
	.dev		= {
				.platform_data		= &cf_data,
	},
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	.resource	= cf_resources,
	.num_resources	= ARRAY_SIZE(cf_resources),
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};

void __init at91_add_device_cf(struct at91_cf_data *data)
{
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	unsigned int csa;

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	if (!data)
		return;

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	data->chipselect = 4;		/* can only use EBI ChipSelect 4 */

	/* CF takes over CS4, CS5, CS6 */
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	csa = at91_ramc_read(0, AT91_EBI_CSA);
	at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
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	/*
	 * Static memory controller timing adjustments.
	 * REVISIT:  these timings are in terms of MCK cycles, so
	 * when MCK changes (cpufreq etc) so must these values...
	 */
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	at91_ramc_write(0, AT91_SMC_CSR(4),
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				  AT91_SMC_ACSS_STD
				| AT91_SMC_DBW_16
				| AT91_SMC_BAT
				| AT91_SMC_WSEN
				| AT91_SMC_NWS_(32)	/* wait states */
				| AT91_SMC_RWSETUP_(6)	/* setup time */
				| AT91_SMC_RWHOLD_(4)	/* hold time */
	);

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	/* input/irq */
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	if (gpio_is_valid(data->irq_pin)) {
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		at91_set_gpio_input(data->irq_pin, 1);
		at91_set_deglitch(data->irq_pin, 1);
	}
	at91_set_gpio_input(data->det_pin, 1);
	at91_set_deglitch(data->det_pin, 1);

	/* outputs, initially off */
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	if (gpio_is_valid(data->vcc_pin))
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		at91_set_gpio_output(data->vcc_pin, 0);
	at91_set_gpio_output(data->rst_pin, 0);

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	/* force poweron defaults for these pins ... */
	at91_set_A_periph(AT91_PIN_PC9, 0);	/* A25/CFRNW */
	at91_set_A_periph(AT91_PIN_PC10, 0);	/* NCS4/CFCS */
	at91_set_A_periph(AT91_PIN_PC11, 0);	/* NCS5/CFCE1 */
	at91_set_A_periph(AT91_PIN_PC12, 0);	/* NCS6/CFCE2 */

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	/* nWAIT is _not_ a default setting */
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	at91_set_A_periph(AT91_PIN_PC6, 1);	/* nWAIT */
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	cf_data = *data;
	platform_device_register(&at91rm9200_cf_device);
}
#else
void __init at91_add_device_cf(struct at91_cf_data *data) {}
#endif


/* --------------------------------------------------------------------
 *  MMC / SD
 * -------------------------------------------------------------------- */

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#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
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static u64 mmc_dmamask = DMA_BIT_MASK(32);
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static struct mci_platform_data mmc_data;
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static struct resource mmc_resources[] = {
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	[0] = {
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		.start	= AT91RM9200_BASE_MCI,
		.end	= AT91RM9200_BASE_MCI + SZ_16K - 1,
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		.flags	= IORESOURCE_MEM,
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	},
	[1] = {
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		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
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		.flags	= IORESOURCE_IRQ,
	},
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};

static struct platform_device at91rm9200_mmc_device = {
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	.name		= "atmel_mci",
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	.id		= -1,
	.dev		= {
				.dma_mask		= &mmc_dmamask,
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				.coherent_dma_mask	= DMA_BIT_MASK(32),
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				.platform_data		= &mmc_data,
	},
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	.resource	= mmc_resources,
	.num_resources	= ARRAY_SIZE(mmc_resources),
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};

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void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
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{
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	unsigned int i;
	unsigned int slot_count = 0;

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	if (!data)
		return;

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	for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
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		if (!data->slot[i].bus_width)
			continue;
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		/* input/irq */
		if (gpio_is_valid(data->slot[i].detect_pin)) {
			at91_set_gpio_input(data->slot[i].detect_pin, 1);
			at91_set_deglitch(data->slot[i].detect_pin, 1);
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		}
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		if (gpio_is_valid(data->slot[i].wp_pin))
			at91_set_gpio_input(data->slot[i].wp_pin, 1);

		switch (i) {
		case 0:					/* slot A */
			/* CMD */
			at91_set_A_periph(AT91_PIN_PA28, 1);
			/* DAT0, maybe DAT1..DAT3 */
			at91_set_A_periph(AT91_PIN_PA29, 1);
			if (data->slot[i].bus_width == 4) {
				at91_set_B_periph(AT91_PIN_PB3, 1);
				at91_set_B_periph(AT91_PIN_PB4, 1);
				at91_set_B_periph(AT91_PIN_PB5, 1);
			}
			slot_count++;
			break;
		case 1:					/* slot B */
			/* CMD */
			at91_set_B_periph(AT91_PIN_PA8, 1);
			/* DAT0, maybe DAT1..DAT3 */
			at91_set_B_periph(AT91_PIN_PA9, 1);
			if (data->slot[i].bus_width == 4) {
				at91_set_B_periph(AT91_PIN_PA10, 1);
				at91_set_B_periph(AT91_PIN_PA11, 1);
				at91_set_B_periph(AT91_PIN_PA12, 1);
			}
			slot_count++;
			break;
		default:
			printk(KERN_ERR
			       "AT91: SD/MMC slot %d not available\n", i);
			break;
		}
		if (slot_count) {
			/* CLK */
			at91_set_A_periph(AT91_PIN_PA27, 0);

			mmc_data = *data;
			platform_device_register(&at91rm9200_mmc_device);
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		}
	}

}
#else
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void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
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#endif

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/* --------------------------------------------------------------------
 *  NAND / SmartMedia
 * -------------------------------------------------------------------- */

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#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
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static struct atmel_nand_data nand_data;
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#define NAND_BASE	AT91_CHIPSELECT_3

static struct resource nand_resources[] = {
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	{
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		.start	= NAND_BASE,
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		.end	= NAND_BASE + SZ_256M - 1,
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		.flags	= IORESOURCE_MEM,
	}
};

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static struct platform_device at91rm9200_nand_device = {
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	.name		= "atmel_nand",
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	.id		= -1,
	.dev		= {
				.platform_data	= &nand_data,
	},
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	.resource	= nand_resources,
	.num_resources	= ARRAY_SIZE(nand_resources),
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};

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void __init at91_add_device_nand(struct atmel_nand_data *data)
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{
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	unsigned int csa;

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	if (!data)
		return;

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	/* enable the address range of CS3 */
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	csa = at91_ramc_read(0, AT91_EBI_CSA);
	at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
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	/* set the bus interface characteristics */
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	at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
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		| AT91_SMC_NWS_(5)
		| AT91_SMC_TDF_(1)
		| AT91_SMC_RWSETUP_(0)	/* tDS Data Set up Time 30 - ns */
		| AT91_SMC_RWHOLD_(1)	/* tDH Data Hold Time 20 - ns */
	);

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	/* enable pin */
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	if (gpio_is_valid(data->enable_pin))
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		at91_set_gpio_output(data->enable_pin, 1);

	/* ready/busy pin */
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	if (gpio_is_valid(data->rdy_pin))
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		at91_set_gpio_input(data->rdy_pin, 1);

	/* card detect pin */
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	if (gpio_is_valid(data->det_pin))
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		at91_set_gpio_input(data->det_pin, 1);

	at91_set_A_periph(AT91_PIN_PC1, 0);		/* SMOE */
	at91_set_A_periph(AT91_PIN_PC3, 0);		/* SMWE */

	nand_data = *data;
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	platform_device_register(&at91rm9200_nand_device);
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}
#else
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void __init at91_add_device_nand(struct atmel_nand_data *data) {}
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#endif


/* --------------------------------------------------------------------
 *  TWI (i2c)
 * -------------------------------------------------------------------- */

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/*
 * Prefer the GPIO code since the TWI controller isn't robust
 * (gets overruns and underruns under load) and can only issue
 * repeated STARTs in one scenario (the driver doesn't yet handle them).
 */
#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)

static struct i2c_gpio_platform_data pdata = {
	.sda_pin		= AT91_PIN_PA25,
	.sda_is_open_drain	= 1,
	.scl_pin		= AT91_PIN_PA26,
	.scl_is_open_drain	= 1,
	.udelay			= 2,		/* ~100 kHz */
};

static struct platform_device at91rm9200_twi_device = {
	.name			= "i2c-gpio",
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	.id			= 0,
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	.dev.platform_data	= &pdata,
};

void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
{
	at91_set_GPIO_periph(AT91_PIN_PA25, 1);		/* TWD (SDA) */
	at91_set_multi_drive(AT91_PIN_PA25, 1);

	at91_set_GPIO_periph(AT91_PIN_PA26, 1);		/* TWCK (SCL) */
	at91_set_multi_drive(AT91_PIN_PA26, 1);

	i2c_register_board_info(0, devices, nr_devices);
	platform_device_register(&at91rm9200_twi_device);
}

#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
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static struct resource twi_resources[] = {
	[0] = {
		.start	= AT91RM9200_BASE_TWI,
		.end	= AT91RM9200_BASE_TWI + SZ_16K - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
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		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
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		.flags	= IORESOURCE_IRQ,
	},
};

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static struct platform_device at91rm9200_twi_device = {
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	.name		= "i2c-at91rm9200",
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	.id		= 0,
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	.resource	= twi_resources,
	.num_resources	= ARRAY_SIZE(twi_resources),
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};

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void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
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{
	/* pins used for TWI interface */
	at91_set_A_periph(AT91_PIN_PA25, 0);		/* TWD */
	at91_set_multi_drive(AT91_PIN_PA25, 1);

	at91_set_A_periph(AT91_PIN_PA26, 0);		/* TWCK */
	at91_set_multi_drive(AT91_PIN_PA26, 1);

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	i2c_register_board_info(0, devices, nr_devices);
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	platform_device_register(&at91rm9200_twi_device);
}
#else
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void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
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#endif


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/* --------------------------------------------------------------------
 *  SPI
 * -------------------------------------------------------------------- */

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#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
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static u64 spi_dmamask = DMA_BIT_MASK(32);
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static struct resource spi_resources[] = {
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	[0] = {
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		.start	= AT91RM9200_BASE_SPI,
		.end	= AT91RM9200_BASE_SPI + SZ_16K - 1,
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		.flags	= IORESOURCE_MEM,
	},
	[1] = {
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		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
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		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device at91rm9200_spi_device = {
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	.name		= "atmel_spi",
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	.id		= 0,
	.dev		= {
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				.dma_mask		= &spi_dmamask,
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				.coherent_dma_mask	= DMA_BIT_MASK(32),
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	},
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	.resource	= spi_resources,
	.num_resources	= ARRAY_SIZE(spi_resources),
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};

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static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
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void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
{
	int i;
	unsigned long cs_pin;

	at91_set_A_periph(AT91_PIN_PA0, 0);	/* MISO */
	at91_set_A_periph(AT91_PIN_PA1, 0);	/* MOSI */
	at91_set_A_periph(AT91_PIN_PA2, 0);	/* SPCK */

	/* Enable SPI chip-selects */
	for (i = 0; i < nr_devices; i++) {
		if (devices[i].controller_data)
			cs_pin = (unsigned long) devices[i].controller_data;
		else
584
			cs_pin = spi_standard_cs[devices[i].chip_select];
585

586 587 588 589 590
		if (devices[i].chip_select == 0)	/* for CS0 errata */
			at91_set_A_periph(cs_pin, 0);
		else
			at91_set_gpio_output(cs_pin, 1);

591 592 593 594 595 596 597 598 599 600 601 602 603

		/* pass chip-select pin to driver */
		devices[i].controller_data = (void *) cs_pin;
	}

	spi_register_board_info(devices, nr_devices);
	platform_device_register(&at91rm9200_spi_device);
}
#else
void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
#endif


604 605 606 607 608 609 610 611 612 613 614 615 616
/* --------------------------------------------------------------------
 *  Timer/Counter blocks
 * -------------------------------------------------------------------- */

#ifdef CONFIG_ATMEL_TCLIB

static struct resource tcb0_resources[] = {
	[0] = {
		.start	= AT91RM9200_BASE_TCB0,
		.end	= AT91RM9200_BASE_TCB0 + SZ_16K - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
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		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
619 620 621
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
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		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
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		.flags	= IORESOURCE_IRQ,
	},
	[3] = {
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		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
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		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device at91rm9200_tcb0_device = {
	.name		= "atmel_tcb",
	.id		= 0,
	.resource	= tcb0_resources,
	.num_resources	= ARRAY_SIZE(tcb0_resources),
};

static struct resource tcb1_resources[] = {
	[0] = {
		.start	= AT91RM9200_BASE_TCB1,
		.end	= AT91RM9200_BASE_TCB1 + SZ_16K - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
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		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
649 650 651
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
652 653
		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
654 655 656
		.flags	= IORESOURCE_IRQ,
	},
	[3] = {
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		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
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		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device at91rm9200_tcb1_device = {
	.name		= "atmel_tcb",
	.id		= 1,
	.resource	= tcb1_resources,
	.num_resources	= ARRAY_SIZE(tcb1_resources),
};

static void __init at91_add_device_tc(void)
{
	platform_device_register(&at91rm9200_tcb0_device);
	platform_device_register(&at91rm9200_tcb1_device);
}
#else
static void __init at91_add_device_tc(void) { }
#endif


680 681 682 683
/* --------------------------------------------------------------------
 *  RTC
 * -------------------------------------------------------------------- */

684
#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
685 686 687 688 689 690 691
static struct resource rtc_resources[] = {
	[0] = {
		.start	= AT91RM9200_BASE_RTC,
		.end	= AT91RM9200_BASE_RTC + SZ_256 - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
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		.start	= NR_IRQS_LEGACY + AT91_ID_SYS,
		.end	= NR_IRQS_LEGACY + AT91_ID_SYS,
694 695 696 697
		.flags	= IORESOURCE_IRQ,
	},
};

698 699 700
static struct platform_device at91rm9200_rtc_device = {
	.name		= "at91_rtc",
	.id		= -1,
701 702
	.resource	= rtc_resources,
	.num_resources	= ARRAY_SIZE(rtc_resources),
703 704
};

705
static void __init at91_add_device_rtc(void)
706 707 708 709
{
	platform_device_register(&at91rm9200_rtc_device);
}
#else
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static void __init at91_add_device_rtc(void) {}
#endif


/* --------------------------------------------------------------------
 *  Watchdog
 * -------------------------------------------------------------------- */

718
#if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
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static struct platform_device at91rm9200_wdt_device = {
	.name		= "at91_wdt",
	.id		= -1,
	.num_resources	= 0,
};

static void __init at91_add_device_watchdog(void)
{
	platform_device_register(&at91rm9200_wdt_device);
}
#else
static void __init at91_add_device_watchdog(void) {}
731 732 733
#endif


734 735 736 737 738 739 740 741 742 743 744 745 746 747
/* --------------------------------------------------------------------
 *  SSC -- Synchronous Serial Controller
 * -------------------------------------------------------------------- */

#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
static u64 ssc0_dmamask = DMA_BIT_MASK(32);

static struct resource ssc0_resources[] = {
	[0] = {
		.start	= AT91RM9200_BASE_SSC0,
		.end	= AT91RM9200_BASE_SSC0 + SZ_16K - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
748 749
		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device at91rm9200_ssc0_device = {
	.name	= "ssc",
	.id	= 0,
	.dev	= {
		.dma_mask		= &ssc0_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= ssc0_resources,
	.num_resources	= ARRAY_SIZE(ssc0_resources),
};

static inline void configure_ssc0_pins(unsigned pins)
{
	if (pins & ATMEL_SSC_TF)
		at91_set_A_periph(AT91_PIN_PB0, 1);
	if (pins & ATMEL_SSC_TK)
		at91_set_A_periph(AT91_PIN_PB1, 1);
	if (pins & ATMEL_SSC_TD)
		at91_set_A_periph(AT91_PIN_PB2, 1);
	if (pins & ATMEL_SSC_RD)
		at91_set_A_periph(AT91_PIN_PB3, 1);
	if (pins & ATMEL_SSC_RK)
		at91_set_A_periph(AT91_PIN_PB4, 1);
	if (pins & ATMEL_SSC_RF)
		at91_set_A_periph(AT91_PIN_PB5, 1);
}

static u64 ssc1_dmamask = DMA_BIT_MASK(32);

static struct resource ssc1_resources[] = {
	[0] = {
		.start	= AT91RM9200_BASE_SSC1,
		.end	= AT91RM9200_BASE_SSC1 + SZ_16K - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
790 791
		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
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		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device at91rm9200_ssc1_device = {
	.name	= "ssc",
	.id	= 1,
	.dev	= {
		.dma_mask		= &ssc1_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= ssc1_resources,
	.num_resources	= ARRAY_SIZE(ssc1_resources),
};

static inline void configure_ssc1_pins(unsigned pins)
{
	if (pins & ATMEL_SSC_TF)
		at91_set_A_periph(AT91_PIN_PB6, 1);
	if (pins & ATMEL_SSC_TK)
		at91_set_A_periph(AT91_PIN_PB7, 1);
	if (pins & ATMEL_SSC_TD)
		at91_set_A_periph(AT91_PIN_PB8, 1);
	if (pins & ATMEL_SSC_RD)
		at91_set_A_periph(AT91_PIN_PB9, 1);
	if (pins & ATMEL_SSC_RK)
		at91_set_A_periph(AT91_PIN_PB10, 1);
	if (pins & ATMEL_SSC_RF)
		at91_set_A_periph(AT91_PIN_PB11, 1);
}

static u64 ssc2_dmamask = DMA_BIT_MASK(32);

static struct resource ssc2_resources[] = {
	[0] = {
		.start	= AT91RM9200_BASE_SSC2,
		.end	= AT91RM9200_BASE_SSC2 + SZ_16K - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
832 833
		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
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		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device at91rm9200_ssc2_device = {
	.name	= "ssc",
	.id	= 2,
	.dev	= {
		.dma_mask		= &ssc2_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= ssc2_resources,
	.num_resources	= ARRAY_SIZE(ssc2_resources),
};

static inline void configure_ssc2_pins(unsigned pins)
{
	if (pins & ATMEL_SSC_TF)
		at91_set_A_periph(AT91_PIN_PB12, 1);
	if (pins & ATMEL_SSC_TK)
		at91_set_A_periph(AT91_PIN_PB13, 1);
	if (pins & ATMEL_SSC_TD)
		at91_set_A_periph(AT91_PIN_PB14, 1);
	if (pins & ATMEL_SSC_RD)
		at91_set_A_periph(AT91_PIN_PB15, 1);
	if (pins & ATMEL_SSC_RK)
		at91_set_A_periph(AT91_PIN_PB16, 1);
	if (pins & ATMEL_SSC_RF)
		at91_set_A_periph(AT91_PIN_PB17, 1);
}

/*
 * SSC controllers are accessed through library code, instead of any
 * kind of all-singing/all-dancing driver.  For example one could be
 * used by a particular I2S audio codec's driver, while another one
 * on the same system might be used by a custom data capture driver.
 */
void __init at91_add_device_ssc(unsigned id, unsigned pins)
{
	struct platform_device *pdev;

	/*
	 * NOTE: caller is responsible for passing information matching
	 * "pins" to whatever will be using each particular controller.
	 */
	switch (id) {
	case AT91RM9200_ID_SSC0:
		pdev = &at91rm9200_ssc0_device;
		configure_ssc0_pins(pins);
		break;
	case AT91RM9200_ID_SSC1:
		pdev = &at91rm9200_ssc1_device;
		configure_ssc1_pins(pins);
		break;
	case AT91RM9200_ID_SSC2:
		pdev = &at91rm9200_ssc2_device;
		configure_ssc2_pins(pins);
		break;
	default:
		return;
	}

	platform_device_register(pdev);
}

#else
void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
#endif


904 905 906 907
/* --------------------------------------------------------------------
 *  UART
 * -------------------------------------------------------------------- */

908
#if defined(CONFIG_SERIAL_ATMEL)
909 910
static struct resource dbgu_resources[] = {
	[0] = {
911 912
		.start	= AT91RM9200_BASE_DBGU,
		.end	= AT91RM9200_BASE_DBGU + SZ_512 - 1,
913 914 915
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
916 917
		.start	= NR_IRQS_LEGACY + AT91_ID_SYS,
		.end	= NR_IRQS_LEGACY + AT91_ID_SYS,
918 919 920 921
		.flags	= IORESOURCE_IRQ,
	},
};

922
static struct atmel_uart_data dbgu_data = {
923 924 925 926
	.use_dma_tx	= 0,
	.use_dma_rx	= 0,		/* DBGU not capable of receive DMA */
};

927 928
static u64 dbgu_dmamask = DMA_BIT_MASK(32);

929
static struct platform_device at91rm9200_dbgu_device = {
930
	.name		= "atmel_usart",
931 932
	.id		= 0,
	.dev		= {
933 934 935
				.dma_mask		= &dbgu_dmamask,
				.coherent_dma_mask	= DMA_BIT_MASK(32),
				.platform_data		= &dbgu_data,
936 937 938 939 940 941 942 943 944 945 946 947 948
	},
	.resource	= dbgu_resources,
	.num_resources	= ARRAY_SIZE(dbgu_resources),
};

static inline void configure_dbgu_pins(void)
{
	at91_set_A_periph(AT91_PIN_PA30, 0);		/* DRXD */
	at91_set_A_periph(AT91_PIN_PA31, 1);		/* DTXD */
}

static struct resource uart0_resources[] = {
	[0] = {
949 950
		.start	= AT91RM9200_BASE_US0,
		.end	= AT91RM9200_BASE_US0 + SZ_16K - 1,
951 952 953
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
954 955
		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_US0,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_US0,
956 957 958 959
		.flags	= IORESOURCE_IRQ,
	},
};

960
static struct atmel_uart_data uart0_data = {
961 962 963 964
	.use_dma_tx	= 1,
	.use_dma_rx	= 1,
};

965 966
static u64 uart0_dmamask = DMA_BIT_MASK(32);

967
static struct platform_device at91rm9200_uart0_device = {
968
	.name		= "atmel_usart",
969 970
	.id		= 1,
	.dev		= {
971 972 973
				.dma_mask		= &uart0_dmamask,
				.coherent_dma_mask	= DMA_BIT_MASK(32),
				.platform_data		= &uart0_data,
974 975 976 977 978
	},
	.resource	= uart0_resources,
	.num_resources	= ARRAY_SIZE(uart0_resources),
};

979
static inline void configure_usart0_pins(unsigned pins)
980 981 982 983
{
	at91_set_A_periph(AT91_PIN_PA17, 1);		/* TXD0 */
	at91_set_A_periph(AT91_PIN_PA18, 0);		/* RXD0 */

984 985 986 987 988 989 990 991 992 993
	if (pins & ATMEL_UART_CTS)
		at91_set_A_periph(AT91_PIN_PA20, 0);	/* CTS0 */

	if (pins & ATMEL_UART_RTS) {
		/*
		 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
		 *  We need to drive the pin manually.  Default is off (RTS is active low).
		 */
		at91_set_gpio_output(AT91_PIN_PA21, 1);
	}
994 995 996 997
}

static struct resource uart1_resources[] = {
	[0] = {
998 999
		.start	= AT91RM9200_BASE_US1,
		.end	= AT91RM9200_BASE_US1 + SZ_16K - 1,
1000 1001 1002
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
1003 1004
		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_US1,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_US1,
1005 1006 1007 1008
		.flags	= IORESOURCE_IRQ,
	},
};

1009
static struct atmel_uart_data uart1_data = {
1010 1011 1012 1013
	.use_dma_tx	= 1,
	.use_dma_rx	= 1,
};

1014 1015
static u64 uart1_dmamask = DMA_BIT_MASK(32);

1016
static struct platform_device at91rm9200_uart1_device = {
1017
	.name		= "atmel_usart",
1018 1019
	.id		= 2,
	.dev		= {
1020 1021 1022
				.dma_mask		= &uart1_dmamask,
				.coherent_dma_mask	= DMA_BIT_MASK(32),
				.platform_data		= &uart1_data,
1023 1024 1025 1026 1027
	},
	.resource	= uart1_resources,
	.num_resources	= ARRAY_SIZE(uart1_resources),
};

1028
static inline void configure_usart1_pins(unsigned pins)
1029 1030 1031
{
	at91_set_A_periph(AT91_PIN_PB20, 1);		/* TXD1 */
	at91_set_A_periph(AT91_PIN_PB21, 0);		/* RXD1 */
1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044

	if (pins & ATMEL_UART_RI)
		at91_set_A_periph(AT91_PIN_PB18, 0);	/* RI1 */
	if (pins & ATMEL_UART_DTR)
		at91_set_A_periph(AT91_PIN_PB19, 0);	/* DTR1 */
	if (pins & ATMEL_UART_DCD)
		at91_set_A_periph(AT91_PIN_PB23, 0);	/* DCD1 */
	if (pins & ATMEL_UART_CTS)
		at91_set_A_periph(AT91_PIN_PB24, 0);	/* CTS1 */
	if (pins & ATMEL_UART_DSR)
		at91_set_A_periph(AT91_PIN_PB25, 0);	/* DSR1 */
	if (pins & ATMEL_UART_RTS)
		at91_set_A_periph(AT91_PIN_PB26, 0);	/* RTS1 */
1045 1046 1047 1048
}

static struct resource uart2_resources[] = {
	[0] = {
1049 1050
		.start	= AT91RM9200_BASE_US2,
		.end	= AT91RM9200_BASE_US2 + SZ_16K - 1,
1051 1052 1053
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
1054 1055
		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_US2,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_US2,
1056 1057 1058 1059
		.flags	= IORESOURCE_IRQ,
	},
};

1060
static struct atmel_uart_data uart2_data = {
1061 1062 1063 1064
	.use_dma_tx	= 1,
	.use_dma_rx	= 1,
};

1065 1066
static u64 uart2_dmamask = DMA_BIT_MASK(32);

1067
static struct platform_device at91rm9200_uart2_device = {
1068
	.name		= "atmel_usart",
1069 1070
	.id		= 3,
	.dev		= {
1071 1072 1073
				.dma_mask		= &uart2_dmamask,
				.coherent_dma_mask	= DMA_BIT_MASK(32),
				.platform_data		= &uart2_data,
1074 1075 1076 1077 1078
	},
	.resource	= uart2_resources,
	.num_resources	= ARRAY_SIZE(uart2_resources),
};

1079
static inline void configure_usart2_pins(unsigned pins)
1080 1081 1082
{
	at91_set_A_periph(AT91_PIN_PA22, 0);		/* RXD2 */
	at91_set_A_periph(AT91_PIN_PA23, 1);		/* TXD2 */
1083 1084 1085 1086 1087

	if (pins & ATMEL_UART_CTS)
		at91_set_B_periph(AT91_PIN_PA30, 0);	/* CTS2 */
	if (pins & ATMEL_UART_RTS)
		at91_set_B_periph(AT91_PIN_PA31, 0);	/* RTS2 */
1088 1089 1090 1091
}

static struct resource uart3_resources[] = {
	[0] = {
1092 1093
		.start	= AT91RM9200_BASE_US3,
		.end	= AT91RM9200_BASE_US3 + SZ_16K - 1,
1094 1095 1096
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
1097 1098
		.start	= NR_IRQS_LEGACY + AT91RM9200_ID_US3,
		.end	= NR_IRQS_LEGACY + AT91RM9200_ID_US3,
1099 1100 1101 1102
		.flags	= IORESOURCE_IRQ,
	},
};

1103
static struct atmel_uart_data uart3_data = {
1104 1105 1106 1107
	.use_dma_tx	= 1,
	.use_dma_rx	= 1,
};

1108 1109
static u64 uart3_dmamask = DMA_BIT_MASK(32);

1110
static struct platform_device at91rm9200_uart3_device = {
1111
	.name		= "atmel_usart",
1112 1113
	.id		= 4,
	.dev		= {
1114 1115 1116
				.dma_mask		= &uart3_dmamask,
				.coherent_dma_mask	= DMA_BIT_MASK(32),
				.platform_data		= &uart3_data,
1117 1118 1119 1120 1121
	},
	.resource	= uart3_resources,
	.num_resources	= ARRAY_SIZE(uart3_resources),
};

1122
static inline void configure_usart3_pins(unsigned pins)
1123 1124 1125
{
	at91_set_B_periph(AT91_PIN_PA5, 1);		/* TXD3 */
	at91_set_B_periph(AT91_PIN_PA6, 0);		/* RXD3 */
1126 1127 1128 1129 1130

	if (pins & ATMEL_UART_CTS)
		at91_set_B_periph(AT91_PIN_PB1, 0);	/* CTS3 */
	if (pins & ATMEL_UART_RTS)
		at91_set_B_periph(AT91_PIN_PB0, 0);	/* RTS3 */
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}

1133
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];	/* the UARTs to use */
1134

1135 1136 1137
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
	struct platform_device *pdev;
1138
	struct atmel_uart_data *pdata;
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	switch (id) {
		case 0:		/* DBGU */
			pdev = &at91rm9200_dbgu_device;
			configure_dbgu_pins();
			break;
		case AT91RM9200_ID_US0:
			pdev = &at91rm9200_uart0_device;
			configure_usart0_pins(pins);
			break;
		case AT91RM9200_ID_US1:
			pdev = &at91rm9200_uart1_device;
			configure_usart1_pins(pins);
			break;
		case AT91RM9200_ID_US2:
			pdev = &at91rm9200_uart2_device;
			configure_usart2_pins(pins);
			break;
		case AT91RM9200_ID_US3:
			pdev = &at91rm9200_uart3_device;
			configure_usart3_pins(pins);
			break;
		default:
			return;
	}
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	pdata = pdev->dev.platform_data;
	pdata->num = portnr;		/* update to mapped ID */
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	if (portnr < ATMEL_MAX_UART)
		at91_uarts[portnr] = pdev;
}

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void __init at91_add_device_serial(void)
{
	int i;

1175
	for (i = 0; i < ATMEL_MAX_UART; i++) {
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		if (at91_uarts[i])
			platform_device_register(at91_uarts[i]);
	}
}
#else
1181
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1182 1183 1184 1185
void __init at91_add_device_serial(void) {}
#endif


1186
/* -------------------------------------------------------------------- */
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/*
 * These devices are always present and don't need any board-specific
 * setup.
 */
static int __init at91_add_standard_devices(void)
{
	at91_add_device_rtc();
	at91_add_device_watchdog();
1196
	at91_add_device_tc();
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	return 0;
}

arch_initcall(at91_add_standard_devices);