intel_cdclk.c 84.0 KB
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/*
 * Copyright © 2006-2017 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

24
#include <linux/time.h>
25

26
#include "intel_atomic.h"
27
#include "intel_bw.h"
28
#include "intel_cdclk.h"
29
#include "intel_de.h"
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#include "intel_display_types.h"
31
#include "intel_psr.h"
32
#include "intel_sideband.h"
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/**
 * DOC: CDCLK / RAWCLK
 *
 * The display engine uses several different clocks to do its work. There
 * are two main clocks involved that aren't directly related to the actual
 * pixel clock or any symbol/bit clock of the actual output port. These
 * are the core display clock (CDCLK) and RAWCLK.
 *
 * CDCLK clocks most of the display pipe logic, and thus its frequency
 * must be high enough to support the rate at which pixels are flowing
 * through the pipes. Downscaling must also be accounted as that increases
 * the effective pixel rate.
 *
 * On several platforms the CDCLK frequency can be changed dynamically
 * to minimize power consumption for a given display configuration.
 * Typically changes to the CDCLK frequency require all the display pipes
 * to be shut down while the frequency is being changed.
 *
 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
 * DMC will not change the active CDCLK frequency however, so that part
 * will still be performed by the driver directly.
 *
 * RAWCLK is a fixed frequency clock, often used by various auxiliary
 * blocks such as AUX CH or backlight PWM. Hence the only thing we
 * really need to know about RAWCLK is its frequency so that various
 * dividers can be programmed correctly.
 */

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static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
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				   struct intel_cdclk_config *cdclk_config)
64
{
65
	cdclk_config->cdclk = 133333;
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}

68
static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
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				   struct intel_cdclk_config *cdclk_config)
70
{
71
	cdclk_config->cdclk = 200000;
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}

74
static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
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				   struct intel_cdclk_config *cdclk_config)
76
{
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	cdclk_config->cdclk = 266667;
78 79
}

80
static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
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				   struct intel_cdclk_config *cdclk_config)
82
{
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	cdclk_config->cdclk = 333333;
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}

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static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
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				   struct intel_cdclk_config *cdclk_config)
88
{
89
	cdclk_config->cdclk = 400000;
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}

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static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
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				   struct intel_cdclk_config *cdclk_config)
94
{
95
	cdclk_config->cdclk = 450000;
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}

98
static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
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			   struct intel_cdclk_config *cdclk_config)
100
{
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	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
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	u16 hpllcc = 0;

	/*
	 * 852GM/852GMV only supports 133 MHz and the HPLLCC
	 * encoding is different :(
	 * FIXME is this the right way to detect 852GM/852GMV?
	 */
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	if (pdev->revision == 0x1) {
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		cdclk_config->cdclk = 133333;
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		return;
	}
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	pci_bus_read_config_word(pdev->bus,
				 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);

	/* Assume that the hardware is in the high speed state.  This
	 * should be the default.
	 */
	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
	case GC_CLOCK_133_200:
	case GC_CLOCK_133_200_2:
	case GC_CLOCK_100_200:
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		cdclk_config->cdclk = 200000;
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		break;
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	case GC_CLOCK_166_250:
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		cdclk_config->cdclk = 250000;
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		break;
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	case GC_CLOCK_100_133:
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		cdclk_config->cdclk = 133333;
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		break;
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	case GC_CLOCK_133_266:
	case GC_CLOCK_133_266_2:
	case GC_CLOCK_166_266:
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		cdclk_config->cdclk = 266667;
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		break;
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	}
}

140
static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
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			     struct intel_cdclk_config *cdclk_config)
142
{
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	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
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	u16 gcfgc = 0;

	pci_read_config_word(pdev, GCFGC, &gcfgc);

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	if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
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		cdclk_config->cdclk = 133333;
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		return;
	}
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	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
	case GC_DISPLAY_CLOCK_333_320_MHZ:
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		cdclk_config->cdclk = 333333;
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		break;
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	default:
	case GC_DISPLAY_CLOCK_190_200_MHZ:
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		cdclk_config->cdclk = 190000;
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		break;
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	}
}

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static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
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			     struct intel_cdclk_config *cdclk_config)
166
{
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	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
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	u16 gcfgc = 0;

	pci_read_config_word(pdev, GCFGC, &gcfgc);

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	if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
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		cdclk_config->cdclk = 133333;
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		return;
	}
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	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
	case GC_DISPLAY_CLOCK_333_320_MHZ:
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		cdclk_config->cdclk = 320000;
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		break;
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	default:
	case GC_DISPLAY_CLOCK_190_200_MHZ:
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		cdclk_config->cdclk = 200000;
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		break;
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	}
}

static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
{
	static const unsigned int blb_vco[8] = {
		[0] = 3200000,
		[1] = 4000000,
		[2] = 5333333,
		[3] = 4800000,
		[4] = 6400000,
	};
	static const unsigned int pnv_vco[8] = {
		[0] = 3200000,
		[1] = 4000000,
		[2] = 5333333,
		[3] = 4800000,
		[4] = 2666667,
	};
	static const unsigned int cl_vco[8] = {
		[0] = 3200000,
		[1] = 4000000,
		[2] = 5333333,
		[3] = 6400000,
		[4] = 3333333,
		[5] = 3566667,
		[6] = 4266667,
	};
	static const unsigned int elk_vco[8] = {
		[0] = 3200000,
		[1] = 4000000,
		[2] = 5333333,
		[3] = 4800000,
	};
	static const unsigned int ctg_vco[8] = {
		[0] = 3200000,
		[1] = 4000000,
		[2] = 5333333,
		[3] = 6400000,
		[4] = 2666667,
		[5] = 4266667,
	};
	const unsigned int *vco_table;
	unsigned int vco;
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	u8 tmp = 0;
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	/* FIXME other chipsets? */
	if (IS_GM45(dev_priv))
		vco_table = ctg_vco;
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	else if (IS_G45(dev_priv))
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		vco_table = elk_vco;
	else if (IS_I965GM(dev_priv))
		vco_table = cl_vco;
	else if (IS_PINEVIEW(dev_priv))
		vco_table = pnv_vco;
	else if (IS_G33(dev_priv))
		vco_table = blb_vco;
	else
		return 0;

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	tmp = intel_de_read(dev_priv,
			    IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
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	vco = vco_table[tmp & 0x7];
	if (vco == 0)
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		drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
			tmp);
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	else
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		drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco);
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	return vco;
}

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static void g33_get_cdclk(struct drm_i915_private *dev_priv,
259
			  struct intel_cdclk_config *cdclk_config)
260
{
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	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
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	static const u8 div_3200[] = { 12, 10,  8,  7, 5, 16 };
	static const u8 div_4000[] = { 14, 12, 10,  8, 6, 20 };
	static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
	static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
	const u8 *div_table;
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	unsigned int cdclk_sel;
268
	u16 tmp = 0;
269

270
	cdclk_config->vco = intel_hpll_vco(dev_priv);
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	pci_read_config_word(pdev, GCFGC, &tmp);

	cdclk_sel = (tmp >> 4) & 0x7;

	if (cdclk_sel >= ARRAY_SIZE(div_3200))
		goto fail;

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	switch (cdclk_config->vco) {
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	case 3200000:
		div_table = div_3200;
		break;
	case 4000000:
		div_table = div_4000;
		break;
	case 4800000:
		div_table = div_4800;
		break;
	case 5333333:
		div_table = div_5333;
		break;
	default:
		goto fail;
	}

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	cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
						div_table[cdclk_sel]);
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	return;
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fail:
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	drm_err(&dev_priv->drm,
		"Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
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		cdclk_config->vco, tmp);
	cdclk_config->cdclk = 190476;
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}

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static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
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			  struct intel_cdclk_config *cdclk_config)
309
{
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	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
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	u16 gcfgc = 0;

	pci_read_config_word(pdev, GCFGC, &gcfgc);

	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
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		cdclk_config->cdclk = 266667;
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		break;
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	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
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		cdclk_config->cdclk = 333333;
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		break;
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	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
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		cdclk_config->cdclk = 444444;
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		break;
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	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
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		cdclk_config->cdclk = 200000;
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		break;
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	default:
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		drm_err(&dev_priv->drm,
			"Unknown pnv display core clock 0x%04x\n", gcfgc);
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		fallthrough;
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	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
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		cdclk_config->cdclk = 133333;
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		break;
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	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
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		cdclk_config->cdclk = 166667;
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		break;
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	}
}

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static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
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			     struct intel_cdclk_config *cdclk_config)
343
{
344
	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
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	static const u8 div_3200[] = { 16, 10,  8 };
	static const u8 div_4000[] = { 20, 12, 10 };
	static const u8 div_5333[] = { 24, 16, 14 };
	const u8 *div_table;
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	unsigned int cdclk_sel;
350
	u16 tmp = 0;
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	cdclk_config->vco = intel_hpll_vco(dev_priv);
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	pci_read_config_word(pdev, GCFGC, &tmp);

	cdclk_sel = ((tmp >> 8) & 0x1f) - 1;

	if (cdclk_sel >= ARRAY_SIZE(div_3200))
		goto fail;

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	switch (cdclk_config->vco) {
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	case 3200000:
		div_table = div_3200;
		break;
	case 4000000:
		div_table = div_4000;
		break;
	case 5333333:
		div_table = div_5333;
		break;
	default:
		goto fail;
	}

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	cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
						div_table[cdclk_sel]);
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	return;
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fail:
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	drm_err(&dev_priv->drm,
		"Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
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		cdclk_config->vco, tmp);
	cdclk_config->cdclk = 200000;
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}

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static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
387
			   struct intel_cdclk_config *cdclk_config)
388
{
389
	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
390
	unsigned int cdclk_sel;
391
	u16 tmp = 0;
392

393
	cdclk_config->vco = intel_hpll_vco(dev_priv);
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	pci_read_config_word(pdev, GCFGC, &tmp);

	cdclk_sel = (tmp >> 12) & 0x1;

399
	switch (cdclk_config->vco) {
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	case 2666667:
	case 4000000:
	case 5333333:
403
		cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
404
		break;
405
	case 3200000:
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		cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
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		break;
408
	default:
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		drm_err(&dev_priv->drm,
			"Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
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			cdclk_config->vco, tmp);
		cdclk_config->cdclk = 222222;
413
		break;
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	}
}

417
static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
418
			  struct intel_cdclk_config *cdclk_config)
419
{
420
	u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
421
	u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
422 423

	if (lcpll & LCPLL_CD_SOURCE_FCLK)
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		cdclk_config->cdclk = 800000;
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	else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
426
		cdclk_config->cdclk = 450000;
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	else if (freq == LCPLL_CLK_FREQ_450)
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		cdclk_config->cdclk = 450000;
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	else if (IS_HSW_ULT(dev_priv))
430
		cdclk_config->cdclk = 337500;
431
	else
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		cdclk_config->cdclk = 540000;
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}

435
static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
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{
	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
		333333 : 320000;

	/*
	 * We seem to get an unstable or solid color picture at 200MHz.
	 * Not sure what's wrong. For now use 200MHz only when all pipes
	 * are off.
	 */
445
	if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
446
		return 400000;
447
	else if (min_cdclk > 266667)
448
		return freq_320;
449
	else if (min_cdclk > 0)
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		return 266667;
	else
		return 200000;
}

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static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
{
	if (IS_VALLEYVIEW(dev_priv)) {
		if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
			return 2;
		else if (cdclk >= 266667)
			return 1;
		else
			return 0;
	} else {
		/*
		 * Specs are full of misinformation, but testing on actual
		 * hardware has shown that we just need to write the desired
		 * CCK divider into the Punit register.
		 */
		return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
	}
}

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static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
475
			  struct intel_cdclk_config *cdclk_config)
476
{
477 478
	u32 val;

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	vlv_iosf_sb_get(dev_priv,
			BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));

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	cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
	cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
						CCK_DISPLAY_CLOCK_CONTROL,
						cdclk_config->vco);
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487
	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
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	vlv_iosf_sb_put(dev_priv,
			BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
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	if (IS_VALLEYVIEW(dev_priv))
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		cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
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			DSPFREQGUAR_SHIFT;
	else
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		cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
497
			DSPFREQGUAR_SHIFT_CHV;
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}

static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
{
	unsigned int credits, default_credits;

	if (IS_CHERRYVIEW(dev_priv))
		default_credits = PFI_CREDIT(12);
	else
		default_credits = PFI_CREDIT(8);

509
	if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
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		/* CHV suggested value is 31 or 63 */
		if (IS_CHERRYVIEW(dev_priv))
			credits = PFI_CREDIT_63;
		else
			credits = PFI_CREDIT(15);
	} else {
		credits = default_credits;
	}

	/*
	 * WA - write default credits before re-programming
	 * FIXME: should we also set the resend bit here?
	 */
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	intel_de_write(dev_priv, GCI_CONTROL,
		       VGA_FAST_MODE_DISABLE | default_credits);
525

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	intel_de_write(dev_priv, GCI_CONTROL,
		       VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
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	/*
	 * FIXME is this guaranteed to clear
	 * immediately or should we poll for it?
	 */
533 534
	drm_WARN_ON(&dev_priv->drm,
		    intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
535 536
}

537
static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
538
			  const struct intel_cdclk_config *cdclk_config,
539
			  enum pipe pipe)
540
{
541 542
	int cdclk = cdclk_config->cdclk;
	u32 val, cmd = cdclk_config->voltage_level;
543
	intel_wakeref_t wakeref;
544

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	switch (cdclk) {
	case 400000:
	case 333333:
	case 320000:
	case 266667:
	case 200000:
		break;
	default:
		MISSING_CASE(cdclk);
		return;
	}

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	/* There are cases where we can end up here with power domains
	 * off and a CDCLK frequency other than the minimum, like when
	 * issuing a modeset without actually changing any display after
560
	 * a system suspend.  So grab the display core domain, which covers
561 562
	 * the HW blocks needed for the following programming.
	 */
563
	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
564

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	vlv_iosf_sb_get(dev_priv,
			BIT(VLV_IOSF_SB_CCK) |
			BIT(VLV_IOSF_SB_BUNIT) |
			BIT(VLV_IOSF_SB_PUNIT));

570
	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
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	val &= ~DSPFREQGUAR_MASK;
	val |= (cmd << DSPFREQGUAR_SHIFT);
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	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
575 576
		      DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
		     50)) {
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		drm_err(&dev_priv->drm,
			"timed out waiting for CDclk change\n");
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	}

	if (cdclk == 400000) {
		u32 divider;

		divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
					    cdclk) - 1;

		/* adjust cdclk divider */
		val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
		val &= ~CCK_FREQUENCY_VALUES;
		val |= divider;
		vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);

		if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
			      CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
			     50))
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			drm_err(&dev_priv->drm,
				"timed out waiting for CDclk change\n");
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	}

	/* adjust self-refresh exit latency value */
	val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
	val &= ~0x7f;

	/*
	 * For high bandwidth configs, we set a higher latency in the bunit
	 * so that the core display fetch happens in time to avoid underruns.
	 */
	if (cdclk == 400000)
		val |= 4500 / 250; /* 4.5 usec */
	else
		val |= 3000 / 250; /* 3.0 usec */
	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);

614
	vlv_iosf_sb_put(dev_priv,
615 616 617
			BIT(VLV_IOSF_SB_CCK) |
			BIT(VLV_IOSF_SB_BUNIT) |
			BIT(VLV_IOSF_SB_PUNIT));
618 619

	intel_update_cdclk(dev_priv);
620 621

	vlv_program_pfi_credits(dev_priv);
622

623
	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
624 625
}

626
static void chv_set_cdclk(struct drm_i915_private *dev_priv,
627
			  const struct intel_cdclk_config *cdclk_config,
628
			  enum pipe pipe)
629
{
630 631
	int cdclk = cdclk_config->cdclk;
	u32 val, cmd = cdclk_config->voltage_level;
632
	intel_wakeref_t wakeref;
633 634 635 636 637 638 639 640 641 642 643 644

	switch (cdclk) {
	case 333333:
	case 320000:
	case 266667:
	case 200000:
		break;
	default:
		MISSING_CASE(cdclk);
		return;
	}

645 646 647
	/* There are cases where we can end up here with power domains
	 * off and a CDCLK frequency other than the minimum, like when
	 * issuing a modeset without actually changing any display after
648
	 * a system suspend.  So grab the display core domain, which covers
649 650
	 * the HW blocks needed for the following programming.
	 */
651
	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
652

653
	vlv_punit_get(dev_priv);
654
	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
655 656
	val &= ~DSPFREQGUAR_MASK_CHV;
	val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
657 658
	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
659 660
		      DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
		     50)) {
661 662
		drm_err(&dev_priv->drm,
			"timed out waiting for CDclk change\n");
663
	}
664 665

	vlv_punit_put(dev_priv);
666 667

	intel_update_cdclk(dev_priv);
668 669

	vlv_program_pfi_credits(dev_priv);
670

671
	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
672 673
}

674
static int bdw_calc_cdclk(int min_cdclk)
675
{
676
	if (min_cdclk > 540000)
677
		return 675000;
678
	else if (min_cdclk > 450000)
679
		return 540000;
680
	else if (min_cdclk > 337500)
681 682 683 684 685
		return 450000;
	else
		return 337500;
}

686 687 688 689 690 691 692 693 694 695 696 697 698 699 700
static u8 bdw_calc_voltage_level(int cdclk)
{
	switch (cdclk) {
	default:
	case 337500:
		return 2;
	case 450000:
		return 0;
	case 540000:
		return 1;
	case 675000:
		return 3;
	}
}

701
static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
702
			  struct intel_cdclk_config *cdclk_config)
703
{
704
	u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
705
	u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
706 707

	if (lcpll & LCPLL_CD_SOURCE_FCLK)
708
		cdclk_config->cdclk = 800000;
709
	else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
710
		cdclk_config->cdclk = 450000;
711
	else if (freq == LCPLL_CLK_FREQ_450)
712
		cdclk_config->cdclk = 450000;
713
	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
714
		cdclk_config->cdclk = 540000;
715
	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
716
		cdclk_config->cdclk = 337500;
717
	else
718
		cdclk_config->cdclk = 675000;
719 720 721 722 723

	/*
	 * Can't read this out :( Let's assume it's
	 * at least what the CDCLK frequency requires.
	 */
724 725
	cdclk_config->voltage_level =
		bdw_calc_voltage_level(cdclk_config->cdclk);
726 727
}

728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744
static u32 bdw_cdclk_freq_sel(int cdclk)
{
	switch (cdclk) {
	default:
		MISSING_CASE(cdclk);
		fallthrough;
	case 337500:
		return LCPLL_CLK_FREQ_337_5_BDW;
	case 450000:
		return LCPLL_CLK_FREQ_450;
	case 540000:
		return LCPLL_CLK_FREQ_54O_BDW;
	case 675000:
		return LCPLL_CLK_FREQ_675_BDW;
	}
}

745
static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
746
			  const struct intel_cdclk_config *cdclk_config,
747
			  enum pipe pipe)
748
{
749
	int cdclk = cdclk_config->cdclk;
750 751
	int ret;

752 753 754 755 756 757 758
	if (drm_WARN(&dev_priv->drm,
		     (intel_de_read(dev_priv, LCPLL_CTL) &
		      (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
		       LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
		       LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
		       LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
		     "trying to change cdclk frequency with cdclk not enabled\n"))
759 760 761 762 763
		return;

	ret = sandybridge_pcode_write(dev_priv,
				      BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
	if (ret) {
764 765
		drm_err(&dev_priv->drm,
			"failed to inform pcode about cdclk change\n");
766 767 768
		return;
	}

769 770
	intel_de_rmw(dev_priv, LCPLL_CTL,
		     0, LCPLL_CD_SOURCE_FCLK);
771

772 773 774 775
	/*
	 * According to the spec, it should be enough to poll for this 1 us.
	 * However, extensive testing shows that this can take longer.
	 */
776
	if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
777
			LCPLL_CD_SOURCE_FCLK_DONE, 100))
778
		drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
779

780 781
	intel_de_rmw(dev_priv, LCPLL_CTL,
		     LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));
782

783 784
	intel_de_rmw(dev_priv, LCPLL_CTL,
		     LCPLL_CD_SOURCE_FCLK, 0);
785

786 787
	if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
			 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
788
		drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
789

790
	sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
791
				cdclk_config->voltage_level);
792

793 794
	intel_de_write(dev_priv, CDCLK_FREQ,
		       DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
795 796 797 798

	intel_update_cdclk(dev_priv);
}

799
static int skl_calc_cdclk(int min_cdclk, int vco)
800 801
{
	if (vco == 8640000) {
802
		if (min_cdclk > 540000)
803
			return 617143;
804
		else if (min_cdclk > 432000)
805
			return 540000;
806
		else if (min_cdclk > 308571)
807 808 809 810
			return 432000;
		else
			return 308571;
	} else {
811
		if (min_cdclk > 540000)
812
			return 675000;
813
		else if (min_cdclk > 450000)
814
			return 540000;
815
		else if (min_cdclk > 337500)
816 817 818 819 820 821
			return 450000;
		else
			return 337500;
	}
}

822 823
static u8 skl_calc_voltage_level(int cdclk)
{
824
	if (cdclk > 540000)
825
		return 3;
826 827 828 829 830 831
	else if (cdclk > 450000)
		return 2;
	else if (cdclk > 337500)
		return 1;
	else
		return 0;
832 833
}

834
static void skl_dpll0_update(struct drm_i915_private *dev_priv,
835
			     struct intel_cdclk_config *cdclk_config)
836 837 838
{
	u32 val;

839 840
	cdclk_config->ref = 24000;
	cdclk_config->vco = 0;
841

842
	val = intel_de_read(dev_priv, LCPLL1_CTL);
843 844 845
	if ((val & LCPLL_PLL_ENABLE) == 0)
		return;

846
	if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0))
847 848
		return;

849
	val = intel_de_read(dev_priv, DPLL_CTRL1);
850

851 852 853 854 855
	if (drm_WARN_ON(&dev_priv->drm,
			(val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
				DPLL_CTRL1_SSC(SKL_DPLL0) |
				DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
			DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
856 857 858 859 860 861 862
		return;

	switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
863
		cdclk_config->vco = 8100000;
864 865 866
		break;
	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
867
		cdclk_config->vco = 8640000;
868 869 870 871 872 873 874
		break;
	default:
		MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
		break;
	}
}

875
static void skl_get_cdclk(struct drm_i915_private *dev_priv,
876
			  struct intel_cdclk_config *cdclk_config)
877 878 879
{
	u32 cdctl;

880
	skl_dpll0_update(dev_priv, cdclk_config);
881

882
	cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
883

884
	if (cdclk_config->vco == 0)
885
		goto out;
886

887
	cdctl = intel_de_read(dev_priv, CDCLK_CTL);
888

889
	if (cdclk_config->vco == 8640000) {
890 891
		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
		case CDCLK_FREQ_450_432:
892
			cdclk_config->cdclk = 432000;
893
			break;
894
		case CDCLK_FREQ_337_308:
895
			cdclk_config->cdclk = 308571;
896
			break;
897
		case CDCLK_FREQ_540:
898
			cdclk_config->cdclk = 540000;
899
			break;
900
		case CDCLK_FREQ_675_617:
901
			cdclk_config->cdclk = 617143;
902
			break;
903 904
		default:
			MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
905
			break;
906 907 908 909
		}
	} else {
		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
		case CDCLK_FREQ_450_432:
910
			cdclk_config->cdclk = 450000;
911
			break;
912
		case CDCLK_FREQ_337_308:
913
			cdclk_config->cdclk = 337500;
914
			break;
915
		case CDCLK_FREQ_540:
916
			cdclk_config->cdclk = 540000;
917
			break;
918
		case CDCLK_FREQ_675_617:
919
			cdclk_config->cdclk = 675000;
920
			break;
921 922
		default:
			MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
923
			break;
924 925
		}
	}
926 927 928 929 930 931

 out:
	/*
	 * Can't read this out :( Let's assume it's
	 * at least what the CDCLK frequency requires.
	 */
932 933
	cdclk_config->voltage_level =
		skl_calc_voltage_level(cdclk_config->cdclk);
934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952
}

/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
static int skl_cdclk_decimal(int cdclk)
{
	return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
}

static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
					int vco)
{
	bool changed = dev_priv->skl_preferred_vco_freq != vco;

	dev_priv->skl_preferred_vco_freq = vco;

	if (changed)
		intel_update_max_cdclk(dev_priv);
}

953
static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco)
954
{
955
	drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
956 957 958 959 960 961 962 963 964 965

	/*
	 * We always enable DPLL0 with the lowest link rate possible, but still
	 * taking into account the VCO required to operate the eDP panel at the
	 * desired frequency. The usual DP link rates operate with a VCO of
	 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
	 * The modeset code is responsible for the selection of the exact link
	 * rate later on, with the constraint of choosing a frequency that
	 * works with vco.
	 */
966 967 968 969 970 971 972 973
	if (vco == 8640000)
		return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0);
	else
		return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0);
}

static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
{
974 975 976 977 978 979
	intel_de_rmw(dev_priv, DPLL_CTRL1,
		     DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
		     DPLL_CTRL1_SSC(SKL_DPLL0) |
		     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
		     DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
		     skl_dpll0_link_rate(dev_priv, vco));
980
	intel_de_posting_read(dev_priv, DPLL_CTRL1);
981

982 983
	intel_de_rmw(dev_priv, LCPLL1_CTL,
		     0, LCPLL_PLL_ENABLE);
984

985
	if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
986
		drm_err(&dev_priv->drm, "DPLL0 not locked\n");
987

988
	dev_priv->cdclk.hw.vco = vco;
989 990 991 992 993 994 995

	/* We'll want to keep using the current vco from now on. */
	skl_set_preferred_cdclk_vco(dev_priv, vco);
}

static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
{
996 997 998
	intel_de_rmw(dev_priv, LCPLL1_CTL,
		     LCPLL_PLL_ENABLE, 0);

999
	if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
1000
		drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
1001

1002
	dev_priv->cdclk.hw.vco = 0;
1003 1004
}

1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027
static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
			      int cdclk, int vco)
{
	switch (cdclk) {
	default:
		drm_WARN_ON(&dev_priv->drm,
			    cdclk != dev_priv->cdclk.hw.bypass);
		drm_WARN_ON(&dev_priv->drm, vco != 0);
		fallthrough;
	case 308571:
	case 337500:
		return CDCLK_FREQ_337_308;
	case 450000:
	case 432000:
		return CDCLK_FREQ_450_432;
	case 540000:
		return CDCLK_FREQ_540;
	case 617143:
	case 675000:
		return CDCLK_FREQ_675_617;
	}
}

1028
static void skl_set_cdclk(struct drm_i915_private *dev_priv,
1029
			  const struct intel_cdclk_config *cdclk_config,
1030
			  enum pipe pipe)
1031
{
1032 1033
	int cdclk = cdclk_config->cdclk;
	int vco = cdclk_config->vco;
1034
	u32 freq_select, cdclk_ctl;
1035 1036
	int ret;

1037 1038 1039 1040 1041 1042 1043 1044
	/*
	 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
	 * unsupported on SKL. In theory this should never happen since only
	 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
	 * supported on SKL either, see the above WA. WARN whenever trying to
	 * use the corresponding VCO freq as that always leads to using the
	 * minimum 308MHz CDCLK.
	 */
1045 1046
	drm_WARN_ON_ONCE(&dev_priv->drm,
			 IS_SKYLAKE(dev_priv) && vco == 8640000);
1047

1048 1049 1050 1051 1052
	ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
				SKL_CDCLK_PREPARE_FOR_CHANGE,
				SKL_CDCLK_READY_FOR_CHANGE,
				SKL_CDCLK_READY_FOR_CHANGE, 3);
	if (ret) {
1053 1054
		drm_err(&dev_priv->drm,
			"Failed to inform PCU about cdclk change (%d)\n", ret);
1055 1056 1057
		return;
	}

1058
	freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);
1059

1060 1061
	if (dev_priv->cdclk.hw.vco != 0 &&
	    dev_priv->cdclk.hw.vco != vco)
1062 1063
		skl_dpll0_disable(dev_priv);

1064
	cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
1065 1066 1067 1068 1069

	if (dev_priv->cdclk.hw.vco != vco) {
		/* Wa Display #1183: skl,kbl,cfl */
		cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
		cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1070
		intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1071 1072 1073 1074
	}

	/* Wa Display #1183: skl,kbl,cfl */
	cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1075 1076
	intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
	intel_de_posting_read(dev_priv, CDCLK_CTL);
1077

1078
	if (dev_priv->cdclk.hw.vco != vco)
1079 1080
		skl_dpll0_enable(dev_priv, vco);

1081 1082
	/* Wa Display #1183: skl,kbl,cfl */
	cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1083
	intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1084 1085

	cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1086
	intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1087 1088 1089

	/* Wa Display #1183: skl,kbl,cfl */
	cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1090 1091
	intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
	intel_de_posting_read(dev_priv, CDCLK_CTL);
1092 1093

	/* inform PCU of the change */
1094
	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1095
				cdclk_config->voltage_level);
1096 1097 1098 1099 1100 1101

	intel_update_cdclk(dev_priv);
}

static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
1102
	u32 cdctl, expected;
1103 1104 1105 1106 1107 1108

	/*
	 * check if the pre-os initialized the display
	 * There is SWF18 scratchpad register defined which is set by the
	 * pre-os which can be used by the OS drivers to check the status
	 */
1109
	if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1110 1111 1112
		goto sanitize;

	intel_update_cdclk(dev_priv);
1113
	intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
1114

1115
	/* Is PLL enabled and locked ? */
1116
	if (dev_priv->cdclk.hw.vco == 0 ||
1117
	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1118 1119 1120 1121 1122 1123 1124 1125
		goto sanitize;

	/* DPLL okay; verify the cdclock
	 *
	 * Noticed in some instances that the freq selection is correct but
	 * decimal part is programmed wrong from BIOS where pre-os does not
	 * enable display. Verify the same as well.
	 */
1126
	cdctl = intel_de_read(dev_priv, CDCLK_CTL);
1127
	expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1128
		skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1129 1130 1131 1132 1133
	if (cdctl == expected)
		/* All well; nothing to sanitize */
		return;

sanitize:
1134
	drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
1135 1136

	/* force cdclk programming */
1137
	dev_priv->cdclk.hw.cdclk = 0;
1138
	/* force full PLL disable + enable */
1139
	dev_priv->cdclk.hw.vco = -1;
1140 1141
}

1142
static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
1143
{
1144
	struct intel_cdclk_config cdclk_config;
1145 1146 1147

	skl_sanitize_cdclk(dev_priv);

1148 1149
	if (dev_priv->cdclk.hw.cdclk != 0 &&
	    dev_priv->cdclk.hw.vco != 0) {
1150 1151 1152 1153 1154 1155
		/*
		 * Use the current vco as our initial
		 * guess as to what the preferred vco is.
		 */
		if (dev_priv->skl_preferred_vco_freq == 0)
			skl_set_preferred_cdclk_vco(dev_priv,
1156
						    dev_priv->cdclk.hw.vco);
1157 1158 1159
		return;
	}

1160
	cdclk_config = dev_priv->cdclk.hw;
1161

1162 1163 1164 1165 1166
	cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
	if (cdclk_config.vco == 0)
		cdclk_config.vco = 8100000;
	cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1167

1168
	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1169 1170
}

1171
static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
1172
{
1173
	struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
1174

1175 1176 1177
	cdclk_config.cdclk = cdclk_config.bypass;
	cdclk_config.vco = 0;
	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1178

1179
	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1180 1181
}

1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232
static const struct intel_cdclk_vals bxt_cdclk_table[] = {
	{ .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
	{ .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
	{ .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
	{ .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
	{ .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
	{}
};

static const struct intel_cdclk_vals glk_cdclk_table[] = {
	{ .refclk = 19200, .cdclk =  79200, .divider = 8, .ratio = 33 },
	{ .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
	{ .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
	{}
};

static const struct intel_cdclk_vals cnl_cdclk_table[] = {
	{ .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
	{ .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
	{ .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },

	{ .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
	{ .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
	{ .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
	{}
};

static const struct intel_cdclk_vals icl_cdclk_table[] = {
	{ .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
	{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
	{ .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
	{ .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
	{ .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
	{ .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },

	{ .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
	{ .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
	{ .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
	{ .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
	{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
	{ .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },

	{ .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio =  9 },
	{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
	{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
	{ .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
	{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
	{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
	{}
};

M
Matt Roper 已提交
1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256
static const struct intel_cdclk_vals rkl_cdclk_table[] = {
	{ .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio =  36 },
	{ .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio =  40 },
	{ .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio =  64 },
	{ .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
	{ .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
	{ .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },

	{ .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio =  30 },
	{ .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio =  32 },
	{ .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio =  52 },
	{ .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
	{ .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio =  92 },
	{ .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },

	{ .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
	{ .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
	{ .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
	{ .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
	{ .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
	{ .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
	{}
};

1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271
static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
	{ .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
	{ .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
	{ .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },

	{ .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
	{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
	{ .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },

	{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
	{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
	{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
	{}
};

1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292
static const struct intel_cdclk_vals adlp_cdclk_table[] = {
	{ .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
	{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
	{ .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
	{ .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
	{ .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },

	{ .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
	{ .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
	{ .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
	{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
	{ .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },

	{ .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
	{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
	{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
	{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
	{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
	{}
};

1293 1294 1295 1296 1297 1298 1299 1300 1301 1302
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
	const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
	int i;

	for (i = 0; table[i].refclk; i++)
		if (table[i].refclk == dev_priv->cdclk.hw.ref &&
		    table[i].cdclk >= min_cdclk)
			return table[i].cdclk;

1303 1304 1305
	drm_WARN(&dev_priv->drm, 1,
		 "Cannot satisfy minimum cdclk %d with refclk %u\n",
		 min_cdclk, dev_priv->cdclk.hw.ref);
1306
	return 0;
1307 1308
}

1309
static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1310
{
1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321
	const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
	int i;

	if (cdclk == dev_priv->cdclk.hw.bypass)
		return 0;

	for (i = 0; table[i].refclk; i++)
		if (table[i].refclk == dev_priv->cdclk.hw.ref &&
		    table[i].cdclk == cdclk)
			return dev_priv->cdclk.hw.ref * table[i].ratio;

1322 1323
	drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
		 cdclk, dev_priv->cdclk.hw.ref);
1324
	return 0;
1325 1326
}

1327 1328 1329 1330 1331
static u8 bxt_calc_voltage_level(int cdclk)
{
	return DIV_ROUND_UP(cdclk, 25000);
}

1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353
static u8 cnl_calc_voltage_level(int cdclk)
{
	if (cdclk > 336000)
		return 2;
	else if (cdclk > 168000)
		return 1;
	else
		return 0;
}

static u8 icl_calc_voltage_level(int cdclk)
{
	if (cdclk > 556800)
		return 2;
	else if (cdclk > 312000)
		return 1;
	else
		return 0;
}

static u8 ehl_calc_voltage_level(int cdclk)
{
1354 1355 1356
	if (cdclk > 326400)
		return 3;
	else if (cdclk > 312000)
1357 1358 1359 1360 1361 1362 1363
		return 2;
	else if (cdclk > 180000)
		return 1;
	else
		return 0;
}

1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375
static u8 tgl_calc_voltage_level(int cdclk)
{
	if (cdclk > 556800)
		return 3;
	else if (cdclk > 326400)
		return 2;
	else if (cdclk > 312000)
		return 1;
	else
		return 0;
}

1376
static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
1377
			       struct intel_cdclk_config *cdclk_config)
1378
{
1379
	if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1380
		cdclk_config->ref = 24000;
1381
	else
1382
		cdclk_config->ref = 19200;
1383
}
1384

1385
static void icl_readout_refclk(struct drm_i915_private *dev_priv,
1386
			       struct intel_cdclk_config *cdclk_config)
1387
{
1388
	u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1389 1390 1391 1392

	switch (dssm) {
	default:
		MISSING_CASE(dssm);
1393
		fallthrough;
1394
	case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1395
		cdclk_config->ref = 24000;
1396 1397
		break;
	case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1398
		cdclk_config->ref = 19200;
1399 1400
		break;
	case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1401
		cdclk_config->ref = 38400;
1402 1403 1404 1405 1406
		break;
	}
}

static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
1407
			       struct intel_cdclk_config *cdclk_config)
1408 1409 1410
{
	u32 val, ratio;

1411
	if (DISPLAY_VER(dev_priv) >= 11)
1412
		icl_readout_refclk(dev_priv, cdclk_config);
1413
	else if (IS_CANNONLAKE(dev_priv))
1414
		cnl_readout_refclk(dev_priv, cdclk_config);
1415
	else
1416
		cdclk_config->ref = 19200;
1417

1418
	val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
1419 1420 1421 1422 1423 1424
	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
	    (val & BXT_DE_PLL_LOCK) == 0) {
		/*
		 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
		 * setting it to zero is a way to signal that.
		 */
1425
		cdclk_config->vco = 0;
1426
		return;
1427
	}
1428

1429 1430 1431 1432
	/*
	 * CNL+ have the ratio directly in the PLL enable register, gen9lp had
	 * it in a separate PLL control register.
	 */
1433
	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
1434 1435
		ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
	else
1436
		ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1437

1438
	cdclk_config->vco = ratio * cdclk_config->ref;
1439 1440
}

1441
static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1442
			  struct intel_cdclk_config *cdclk_config)
1443 1444
{
	u32 divider;
1445
	int div;
1446

1447
	bxt_de_pll_readout(dev_priv, cdclk_config);
1448

1449
	if (DISPLAY_VER(dev_priv) >= 12)
1450
		cdclk_config->bypass = cdclk_config->ref / 2;
1451
	else if (DISPLAY_VER(dev_priv) >= 11)
1452
		cdclk_config->bypass = 50000;
1453
	else
1454
		cdclk_config->bypass = cdclk_config->ref;
1455

1456 1457
	if (cdclk_config->vco == 0) {
		cdclk_config->cdclk = cdclk_config->bypass;
1458
		goto out;
1459
	}
1460

1461
	divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477

	switch (divider) {
	case BXT_CDCLK_CD2X_DIV_SEL_1:
		div = 2;
		break;
	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
		div = 3;
		break;
	case BXT_CDCLK_CD2X_DIV_SEL_2:
		div = 4;
		break;
	case BXT_CDCLK_CD2X_DIV_SEL_4:
		div = 8;
		break;
	default:
		MISSING_CASE(divider);
1478
		return;
1479 1480
	}

1481
	cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1482 1483 1484 1485 1486 1487

 out:
	/*
	 * Can't read this out :( Let's assume it's
	 * at least what the CDCLK frequency requires.
	 */
1488 1489
	cdclk_config->voltage_level =
		dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
1490 1491 1492 1493
}

static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
{
1494
	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0);
1495 1496

	/* Timeout 200us */
1497 1498
	if (intel_de_wait_for_clear(dev_priv,
				    BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1499
		drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
1500

1501
	dev_priv->cdclk.hw.vco = 0;
1502 1503 1504 1505
}

static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
{
1506
	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1507

1508 1509
	intel_de_rmw(dev_priv, BXT_DE_PLL_CTL,
		     BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
1510

1511
	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1512 1513

	/* Timeout 200us */
1514 1515
	if (intel_de_wait_for_set(dev_priv,
				  BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1516
		drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
1517

1518
	dev_priv->cdclk.hw.vco = vco;
1519 1520
}

1521 1522
static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
{
1523 1524
	intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,
		     BXT_DE_PLL_PLL_ENABLE, 0);
1525 1526

	/* Timeout 200us */
1527 1528
	if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
		drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");
1529 1530 1531 1532 1533 1534 1535 1536 1537 1538

	dev_priv->cdclk.hw.vco = 0;
}

static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
{
	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
	u32 val;

	val = CNL_CDCLK_PLL_RATIO(ratio);
1539
	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1540 1541

	val |= BXT_DE_PLL_PLL_ENABLE;
1542
	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1543 1544

	/* Timeout 200us */
1545 1546
	if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
		drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");
1547 1548 1549 1550

	dev_priv->cdclk.hw.vco = vco;
}

1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579
static bool has_cdclk_crawl(struct drm_i915_private *i915)
{
	return INTEL_INFO(i915)->has_cdclk_crawl;
}

static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
{
	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
	u32 val;

	/* Write PLL ratio without disabling */
	val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);

	/* Submit freq change request */
	val |= BXT_DE_PLL_FREQ_REQ;
	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);

	/* Timeout 200us */
	if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
				  BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
		DRM_ERROR("timeout waiting for FREQ change request ack\n");

	val &= ~BXT_DE_PLL_FREQ_REQ;
	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);

	dev_priv->cdclk.hw.vco = vco;
}

1580 1581
static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
{
1582
	if (DISPLAY_VER(dev_priv) >= 12) {
1583 1584 1585 1586
		if (pipe == INVALID_PIPE)
			return TGL_CDCLK_CD2X_PIPE_NONE;
		else
			return TGL_CDCLK_CD2X_PIPE(pipe);
1587
	} else if (DISPLAY_VER(dev_priv) >= 11) {
1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599
		if (pipe == INVALID_PIPE)
			return ICL_CDCLK_CD2X_PIPE_NONE;
		else
			return ICL_CDCLK_CD2X_PIPE(pipe);
	} else {
		if (pipe == INVALID_PIPE)
			return BXT_CDCLK_CD2X_PIPE_NONE;
		else
			return BXT_CDCLK_CD2X_PIPE(pipe);
	}
}

1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620
static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
				  int cdclk, int vco)
{
	/* cdclk = vco / 2 / div{1,1.5,2,4} */
	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
	default:
		drm_WARN_ON(&dev_priv->drm,
			    cdclk != dev_priv->cdclk.hw.bypass);
		drm_WARN_ON(&dev_priv->drm, vco != 0);
		fallthrough;
	case 2:
		return BXT_CDCLK_CD2X_DIV_SEL_1;
	case 3:
		return BXT_CDCLK_CD2X_DIV_SEL_1_5;
	case 4:
		return BXT_CDCLK_CD2X_DIV_SEL_2;
	case 8:
		return BXT_CDCLK_CD2X_DIV_SEL_4;
	}
}

1621
static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1622
			  const struct intel_cdclk_config *cdclk_config,
1623
			  enum pipe pipe)
1624
{
1625 1626
	int cdclk = cdclk_config->cdclk;
	int vco = cdclk_config->vco;
1627
	u32 val;
1628
	int ret;
1629

1630
	/* Inform power controller of upcoming frequency change. */
1631
	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645
		ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
					SKL_CDCLK_PREPARE_FOR_CHANGE,
					SKL_CDCLK_READY_FOR_CHANGE,
					SKL_CDCLK_READY_FOR_CHANGE, 3);
	else
		/*
		 * BSpec requires us to wait up to 150usec, but that leads to
		 * timeouts; the 2ms used here is based on experiment.
		 */
		ret = sandybridge_pcode_write_timeout(dev_priv,
						      HSW_PCODE_DE_WRITE_FREQ_REQ,
						      0x80000000, 150, 2);

	if (ret) {
1646 1647 1648
		drm_err(&dev_priv->drm,
			"Failed to inform PCU about cdclk change (err %d, freq %d)\n",
			ret, cdclk);
1649 1650 1651
		return;
	}

1652 1653 1654 1655
	if (has_cdclk_crawl(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
		if (dev_priv->cdclk.hw.vco != vco)
			adlp_cdclk_pll_crawl(dev_priv, vco);
	} else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
1656 1657 1658
		if (dev_priv->cdclk.hw.vco != 0 &&
		    dev_priv->cdclk.hw.vco != vco)
			cnl_cdclk_pll_disable(dev_priv);
1659

1660 1661 1662 1663 1664 1665 1666 1667 1668 1669
		if (dev_priv->cdclk.hw.vco != vco)
			cnl_cdclk_pll_enable(dev_priv, vco);
	} else {
		if (dev_priv->cdclk.hw.vco != 0 &&
		    dev_priv->cdclk.hw.vco != vco)
			bxt_de_pll_disable(dev_priv);

		if (dev_priv->cdclk.hw.vco != vco)
			bxt_de_pll_enable(dev_priv, vco);
	}
1670

1671 1672 1673
	val = bxt_cdclk_cd2x_div_sel(dev_priv, cdclk, vco) |
		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
		skl_cdclk_decimal(cdclk);
1674

1675 1676 1677 1678
	/*
	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
	 * enable otherwise.
	 */
1679 1680
	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
	    cdclk >= 500000)
1681
		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1682
	intel_de_write(dev_priv, CDCLK_CTL, val);
1683

1684 1685 1686
	if (pipe != INVALID_PIPE)
		intel_wait_for_vblank(dev_priv, pipe);

1687
	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
1688
		ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1689
					      cdclk_config->voltage_level);
1690 1691 1692 1693 1694 1695 1696 1697 1698
	} else {
		/*
		 * The timeout isn't specified, the 2ms used here is based on
		 * experiment.
		 * FIXME: Waiting for the request completion could be delayed
		 * until the next PCODE request based on BSpec.
		 */
		ret = sandybridge_pcode_write_timeout(dev_priv,
						      HSW_PCODE_DE_WRITE_FREQ_REQ,
1699
						      cdclk_config->voltage_level,
1700 1701 1702
						      150, 2);
	}

1703
	if (ret) {
1704 1705 1706
		drm_err(&dev_priv->drm,
			"PCode CDCLK freq set failed, (err %d, freq %d)\n",
			ret, cdclk);
1707 1708 1709 1710
		return;
	}

	intel_update_cdclk(dev_priv);
1711

1712
	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
1713 1714 1715 1716
		/*
		 * Can't read out the voltage level :(
		 * Let's just assume everything is as expected.
		 */
1717
		dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level;
1718 1719 1720 1721 1722
}

static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
	u32 cdctl, expected;
1723
	int cdclk, vco;
1724 1725

	intel_update_cdclk(dev_priv);
1726
	intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
1727

1728
	if (dev_priv->cdclk.hw.vco == 0 ||
1729
	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1730 1731 1732 1733 1734 1735 1736 1737
		goto sanitize;

	/* DPLL okay; verify the cdclock
	 *
	 * Some BIOS versions leave an incorrect decimal frequency value and
	 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
	 * so sanitize this register.
	 */
1738
	cdctl = intel_de_read(dev_priv, CDCLK_CTL);
1739 1740 1741 1742 1743
	/*
	 * Let's ignore the pipe field, since BIOS could have configured the
	 * dividers both synching to an active pipe, or asynchronously
	 * (PIPE_NONE).
	 */
1744
	cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
1745

1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758
	/* Make sure this is a legal cdclk value for the platform */
	cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
	if (cdclk != dev_priv->cdclk.hw.cdclk)
		goto sanitize;

	/* Make sure the VCO is correct for the cdclk */
	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
	if (vco != dev_priv->cdclk.hw.vco)
		goto sanitize;

	expected = skl_cdclk_decimal(cdclk);

	/* Figure out what CD2X divider we should be using for this cdclk */
1759 1760 1761
	expected |= bxt_cdclk_cd2x_div_sel(dev_priv,
					   dev_priv->cdclk.hw.cdclk,
					   dev_priv->cdclk.hw.vco);
1762

1763 1764 1765 1766
	/*
	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
	 * enable otherwise.
	 */
1767 1768
	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
	    dev_priv->cdclk.hw.cdclk >= 500000)
1769 1770 1771 1772 1773 1774 1775
		expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;

	if (cdctl == expected)
		/* All well; nothing to sanitize */
		return;

sanitize:
1776
	drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
1777 1778

	/* force cdclk programming */
1779
	dev_priv->cdclk.hw.cdclk = 0;
1780 1781

	/* force full PLL disable + enable */
1782
	dev_priv->cdclk.hw.vco = -1;
1783 1784
}

1785
static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
1786
{
1787
	struct intel_cdclk_config cdclk_config;
1788 1789 1790

	bxt_sanitize_cdclk(dev_priv);

1791 1792
	if (dev_priv->cdclk.hw.cdclk != 0 &&
	    dev_priv->cdclk.hw.vco != 0)
1793 1794
		return;

1795
	cdclk_config = dev_priv->cdclk.hw;
1796

1797 1798 1799 1800 1801
	/*
	 * FIXME:
	 * - The initial CDCLK needs to be read from VBT.
	 *   Need to make this change after VBT has changes for BXT.
	 */
1802 1803 1804 1805
	cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
	cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
	cdclk_config.voltage_level =
		dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
1806

1807
	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1808 1809
}

1810
static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
1811
{
1812
	struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
1813

1814 1815 1816 1817
	cdclk_config.cdclk = cdclk_config.bypass;
	cdclk_config.vco = 0;
	cdclk_config.voltage_level =
		dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
1818

1819
	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1820 1821
}

1822
/**
1823
 * intel_cdclk_init_hw - Initialize CDCLK hardware
1824 1825 1826 1827 1828 1829 1830
 * @i915: i915 device
 *
 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
 * sanitizing the state of the hardware if needed. This is generally done only
 * during the display core initialization sequence, after which the DMC will
 * take care of turning CDCLK off/on as needed.
 */
1831
void intel_cdclk_init_hw(struct drm_i915_private *i915)
1832
{
1833
	if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
1834
		bxt_cdclk_init_hw(i915);
1835
	else if (DISPLAY_VER(i915) == 9)
1836
		skl_cdclk_init_hw(i915);
1837 1838 1839
}

/**
1840
 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
1841 1842 1843 1844 1845
 * @i915: i915 device
 *
 * Uninitialize CDCLK. This is done only during the display core
 * uninitialization sequence.
 */
1846
void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
1847
{
1848
	if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
1849
		bxt_cdclk_uninit_hw(i915);
1850
	else if (DISPLAY_VER(i915) == 9)
1851
		skl_cdclk_uninit_hw(i915);
1852 1853
}

1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875
static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
				  const struct intel_cdclk_config *a,
				  const struct intel_cdclk_config *b)
{
	int a_div, b_div;

	if (!has_cdclk_crawl(dev_priv))
		return false;

	/*
	 * The vco and cd2x divider will change independently
	 * from each, so we disallow cd2x change when crawling.
	 */
	a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
	b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);

	return a->vco != 0 && b->vco != 0 &&
		a->vco != b->vco &&
		a_div == b_div &&
		a->ref == b->ref;
}

1876
/**
1877 1878 1879 1880
 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
 *                             configurations requires a modeset on all pipes
 * @a: first CDCLK configuration
 * @b: second CDCLK configuration
1881 1882
 *
 * Returns:
1883 1884
 * True if changing between the two CDCLK configurations
 * requires all pipes to be off, false if not.
1885
 */
1886 1887
bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
			       const struct intel_cdclk_config *b)
1888
{
1889 1890 1891 1892 1893
	return a->cdclk != b->cdclk ||
		a->vco != b->vco ||
		a->ref != b->ref;
}

1894
/**
1895 1896 1897 1898 1899
 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
 *                               configurations requires only a cd2x divider update
 * @dev_priv: i915 device
 * @a: first CDCLK configuration
 * @b: second CDCLK configuration
1900 1901
 *
 * Returns:
1902 1903
 * True if changing between the two CDCLK configurations
 * can be done with just a cd2x divider update, false if not.
1904
 */
1905
static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
1906 1907
					const struct intel_cdclk_config *a,
					const struct intel_cdclk_config *b)
1908 1909
{
	/* Older hw doesn't have the capability */
1910
	if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv))
1911 1912 1913 1914 1915 1916 1917
		return false;

	return a->cdclk != b->cdclk &&
		a->vco == b->vco &&
		a->ref == b->ref;
}

1918
/**
1919 1920 1921
 * intel_cdclk_changed - Determine if two CDCLK configurations are different
 * @a: first CDCLK configuration
 * @b: second CDCLK configuration
1922 1923
 *
 * Returns:
1924
 * True if the CDCLK configurations don't match, false if they do.
1925
 */
1926 1927
static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
				const struct intel_cdclk_config *b)
1928 1929 1930
{
	return intel_cdclk_needs_modeset(a, b) ||
		a->voltage_level != b->voltage_level;
1931 1932
}

1933 1934
void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
			     const char *context)
1935
{
1936
	DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
1937 1938 1939
			 context, cdclk_config->cdclk, cdclk_config->vco,
			 cdclk_config->ref, cdclk_config->bypass,
			 cdclk_config->voltage_level);
1940 1941
}

1942
/**
1943
 * intel_set_cdclk - Push the CDCLK configuration to the hardware
1944
 * @dev_priv: i915 device
1945
 * @cdclk_config: new CDCLK configuration
1946
 * @pipe: pipe with which to synchronize the update
1947 1948 1949 1950
 *
 * Program the hardware based on the passed in CDCLK state,
 * if necessary.
 */
1951
static void intel_set_cdclk(struct drm_i915_private *dev_priv,
1952
			    const struct intel_cdclk_config *cdclk_config,
1953
			    enum pipe pipe)
1954
{
1955 1956
	struct intel_encoder *encoder;

1957
	if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
1958 1959
		return;

1960
	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))
1961 1962
		return;

1963
	intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
1964

1965 1966 1967 1968 1969 1970
	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

		intel_psr_pause(intel_dp);
	}

1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983
	/*
	 * Lock aux/gmbus while we change cdclk in case those
	 * functions use cdclk. Not all platforms/ports do,
	 * but we'll lock them all for simplicity.
	 */
	mutex_lock(&dev_priv->gmbus_mutex);
	for_each_intel_dp(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

		mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
				     &dev_priv->gmbus_mutex);
	}

1984
	dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
1985

1986 1987 1988 1989 1990 1991 1992
	for_each_intel_dp(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

		mutex_unlock(&intel_dp->aux.hw_mutex);
	}
	mutex_unlock(&dev_priv->gmbus_mutex);

1993 1994 1995 1996 1997 1998
	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

		intel_psr_resume(intel_dp);
	}

1999 2000 2001
	if (drm_WARN(&dev_priv->drm,
		     intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
		     "cdclk state doesn't match!\n")) {
2002 2003
		intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");
		intel_dump_cdclk_config(cdclk_config, "[sw state]");
2004
	}
2005 2006
}

2007
/**
2008 2009
 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
 * @state: intel atomic state
2010
 *
2011 2012
 * Program the hardware before updating the HW plane state based on the
 * new CDCLK state, if necessary.
2013 2014
 */
void
2015
intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
2016
{
2017
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2018 2019 2020 2021
	const struct intel_cdclk_state *old_cdclk_state =
		intel_atomic_get_old_cdclk_state(state);
	const struct intel_cdclk_state *new_cdclk_state =
		intel_atomic_get_new_cdclk_state(state);
2022
	enum pipe pipe = new_cdclk_state->pipe;
2023

2024 2025 2026 2027
	if (!intel_cdclk_changed(&old_cdclk_state->actual,
				 &new_cdclk_state->actual))
		return;

2028
	if (pipe == INVALID_PIPE ||
2029
	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
2030
		drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
2031

2032
		intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
2033
	}
2034 2035 2036
}

/**
2037 2038
 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
 * @state: intel atomic state
2039
 *
2040
 * Program the hardware after updating the HW plane state based on the
2041
 * new CDCLK state, if necessary.
2042 2043
 */
void
2044
intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
2045
{
2046
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2047 2048 2049 2050
	const struct intel_cdclk_state *old_cdclk_state =
		intel_atomic_get_old_cdclk_state(state);
	const struct intel_cdclk_state *new_cdclk_state =
		intel_atomic_get_new_cdclk_state(state);
2051
	enum pipe pipe = new_cdclk_state->pipe;
2052

2053 2054 2055 2056
	if (!intel_cdclk_changed(&old_cdclk_state->actual,
				 &new_cdclk_state->actual))
		return;

2057
	if (pipe != INVALID_PIPE &&
2058
	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
2059
		drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
2060

2061
		intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
2062
	}
2063 2064
}

2065
static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
2066
{
2067
	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2068 2069
	int pixel_rate = crtc_state->pixel_rate;

2070
	if (DISPLAY_VER(dev_priv) >= 10)
2071
		return DIV_ROUND_UP(pixel_rate, 2);
2072
	else if (DISPLAY_VER(dev_priv) == 9 ||
2073 2074 2075 2076
		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
		return pixel_rate;
	else if (IS_CHERRYVIEW(dev_priv))
		return DIV_ROUND_UP(pixel_rate * 100, 95);
2077 2078
	else if (crtc_state->double_wide)
		return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
2079 2080 2081 2082
	else
		return DIV_ROUND_UP(pixel_rate * 100, 90);
}

2083 2084
static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
{
2085
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2086 2087 2088 2089 2090 2091 2092 2093 2094 2095
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	struct intel_plane *plane;
	int min_cdclk = 0;

	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
		min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);

	return min_cdclk;
}

2096
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2097 2098
{
	struct drm_i915_private *dev_priv =
2099
		to_i915(crtc_state->uapi.crtc->dev);
2100 2101
	int min_cdclk;

2102
	if (!crtc_state->hw.enable)
2103 2104
		return 0;

2105
	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
2106 2107

	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2108
	if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2109
		min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2110

2111 2112 2113
	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
	 * there may be audio corruption or screen corruption." This cdclk
2114
	 * restriction for GLK is 316.8 MHz.
2115 2116 2117 2118
	 */
	if (intel_crtc_has_dp_encoder(crtc_state) &&
	    crtc_state->has_audio &&
	    crtc_state->port_clock >= 540000 &&
2119
	    crtc_state->lane_count == 4) {
2120
		if (DISPLAY_VER(dev_priv) == 10) {
2121 2122
			/* Display WA #1145: glk,cnl */
			min_cdclk = max(316800, min_cdclk);
2123
		} else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
2124 2125 2126
			/* Display WA #1144: skl,bxt */
			min_cdclk = max(432000, min_cdclk);
		}
2127
	}
2128

2129 2130
	/*
	 * According to BSpec, "The CD clock frequency must be at least twice
2131 2132
	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
	 */
2133
	if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9)
2134
		min_cdclk = max(2 * 96000, min_cdclk);
2135

2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146
	/*
	 * "For DP audio configuration, cdclk frequency shall be set to
	 *  meet the following requirements:
	 *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
	 *  270                    | 320 or higher
	 *  162                    | 200 or higher"
	 */
	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
	    intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
		min_cdclk = max(crtc_state->port_clock, min_cdclk);

2147 2148 2149 2150 2151 2152 2153 2154
	/*
	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
	 * than 320000KHz.
	 */
	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
	    IS_VALLEYVIEW(dev_priv))
		min_cdclk = max(320000, min_cdclk);

2155 2156 2157 2158 2159 2160 2161 2162 2163
	/*
	 * On Geminilake once the CDCLK gets as low as 79200
	 * picture gets unstable, despite that values are
	 * correct for DSI PLL and DE PLL.
	 */
	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
	    IS_GEMINILAKE(dev_priv))
		min_cdclk = max(158400, min_cdclk);

2164 2165 2166
	/* Account for additional needs from the planes */
	min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);

2167 2168 2169 2170 2171 2172 2173 2174 2175
	/*
	 * HACK. Currently for TGL platforms we calculate
	 * min_cdclk initially based on pixel_rate divided
	 * by 2, accounting for also plane requirements,
	 * however in some cases the lowest possible CDCLK
	 * doesn't work and causing the underruns.
	 * Explicitly stating here that this seems to be currently
	 * rather a Hack, than final solution.
	 */
2176 2177 2178 2179 2180 2181 2182 2183 2184
	if (IS_TIGERLAKE(dev_priv)) {
		/*
		 * Clamp to max_cdclk_freq in case pixel rate is higher,
		 * in order not to break an 8K, but still leave W/A at place.
		 */
		min_cdclk = max_t(int, min_cdclk,
				  min_t(int, crtc_state->pixel_rate,
					dev_priv->max_cdclk_freq));
	}
2185

2186
	if (min_cdclk > dev_priv->max_cdclk_freq) {
2187 2188 2189
		drm_dbg_kms(&dev_priv->drm,
			    "required cdclk (%d kHz) exceeds max (%d kHz)\n",
			    min_cdclk, dev_priv->max_cdclk_freq);
2190 2191 2192
		return -EINVAL;
	}

2193
	return min_cdclk;
2194 2195
}

2196
static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
2197
{
2198
	struct intel_atomic_state *state = cdclk_state->base.state;
2199 2200
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
	struct intel_bw_state *bw_state = NULL;
2201
	struct intel_crtc *crtc;
2202
	struct intel_crtc_state *crtc_state;
2203
	int min_cdclk, i;
2204
	enum pipe pipe;
2205

2206
	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2207 2208
		int ret;

2209 2210 2211 2212
		min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
		if (min_cdclk < 0)
			return min_cdclk;

2213 2214 2215 2216
		bw_state = intel_atomic_get_bw_state(state);
		if (IS_ERR(bw_state))
			return PTR_ERR(bw_state);

2217
		if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
2218 2219
			continue;

2220
		cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
2221

2222
		ret = intel_atomic_lock_global_state(&cdclk_state->base);
2223 2224
		if (ret)
			return ret;
2225
	}
2226

2227
	min_cdclk = cdclk_state->force_min_cdclk;
2228 2229
	for_each_pipe(dev_priv, pipe) {
		min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
2230

2231 2232
		if (!bw_state)
			continue;
2233 2234 2235

		min_cdclk = max(bw_state->min_cdclk, min_cdclk);
	}
2236

2237
	return min_cdclk;
2238 2239
}

2240
/*
2241 2242 2243 2244
 * Account for port clock min voltage level requirements.
 * This only really does something on CNL+ but can be
 * called on earlier platforms as well.
 *
2245 2246 2247 2248 2249 2250 2251 2252
 * Note that this functions assumes that 0 is
 * the lowest voltage value, and higher values
 * correspond to increasingly higher voltages.
 *
 * Should that relationship no longer hold on
 * future platforms this code will need to be
 * adjusted.
 */
2253
static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
2254
{
2255
	struct intel_atomic_state *state = cdclk_state->base.state;
2256 2257 2258 2259 2260 2261 2262 2263
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
	struct intel_crtc *crtc;
	struct intel_crtc_state *crtc_state;
	u8 min_voltage_level;
	int i;
	enum pipe pipe;

	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2264 2265
		int ret;

2266
		if (crtc_state->hw.enable)
2267
			min_voltage_level = crtc_state->min_voltage_level;
2268
		else
2269 2270
			min_voltage_level = 0;

2271
		if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level)
2272 2273
			continue;

2274
		cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level;
2275

2276
		ret = intel_atomic_lock_global_state(&cdclk_state->base);
2277 2278
		if (ret)
			return ret;
2279 2280 2281 2282
	}

	min_voltage_level = 0;
	for_each_pipe(dev_priv, pipe)
2283
		min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
2284 2285 2286 2287 2288
					min_voltage_level);

	return min_voltage_level;
}

2289
static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2290
{
2291
	struct intel_atomic_state *state = cdclk_state->base.state;
2292
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2293
	int min_cdclk, cdclk;
2294

2295
	min_cdclk = intel_compute_min_cdclk(cdclk_state);
2296 2297
	if (min_cdclk < 0)
		return min_cdclk;
2298

2299
	cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2300

2301 2302
	cdclk_state->logical.cdclk = cdclk;
	cdclk_state->logical.voltage_level =
2303
		vlv_calc_voltage_level(dev_priv, cdclk);
2304

2305
	if (!cdclk_state->active_pipes) {
2306
		cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2307

2308 2309
		cdclk_state->actual.cdclk = cdclk;
		cdclk_state->actual.voltage_level =
2310
			vlv_calc_voltage_level(dev_priv, cdclk);
2311
	} else {
2312
		cdclk_state->actual = cdclk_state->logical;
2313
	}
2314 2315 2316 2317

	return 0;
}

2318
static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2319
{
2320 2321
	int min_cdclk, cdclk;

2322
	min_cdclk = intel_compute_min_cdclk(cdclk_state);
2323 2324
	if (min_cdclk < 0)
		return min_cdclk;
2325 2326 2327 2328 2329

	/*
	 * FIXME should also account for plane ratio
	 * once 64bpp pixel formats are supported.
	 */
2330
	cdclk = bdw_calc_cdclk(min_cdclk);
2331

2332 2333
	cdclk_state->logical.cdclk = cdclk;
	cdclk_state->logical.voltage_level =
2334
		bdw_calc_voltage_level(cdclk);
2335

2336
	if (!cdclk_state->active_pipes) {
2337
		cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
2338

2339 2340
		cdclk_state->actual.cdclk = cdclk;
		cdclk_state->actual.voltage_level =
2341
			bdw_calc_voltage_level(cdclk);
2342
	} else {
2343
		cdclk_state->actual = cdclk_state->logical;
2344
	}
2345 2346 2347 2348

	return 0;
}

2349
static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
2350
{
2351
	struct intel_atomic_state *state = cdclk_state->base.state;
2352
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2353 2354 2355 2356
	struct intel_crtc *crtc;
	struct intel_crtc_state *crtc_state;
	int vco, i;

2357
	vco = cdclk_state->logical.vco;
2358 2359 2360
	if (!vco)
		vco = dev_priv->skl_preferred_vco_freq;

2361
	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2362
		if (!crtc_state->hw.enable)
2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385
			continue;

		if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
			continue;

		/*
		 * DPLL0 VCO may need to be adjusted to get the correct
		 * clock for eDP. This will affect cdclk as well.
		 */
		switch (crtc_state->port_clock / 2) {
		case 108000:
		case 216000:
			vco = 8640000;
			break;
		default:
			vco = 8100000;
			break;
		}
	}

	return vco;
}

2386
static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2387
{
2388 2389
	int min_cdclk, cdclk, vco;

2390
	min_cdclk = intel_compute_min_cdclk(cdclk_state);
2391 2392
	if (min_cdclk < 0)
		return min_cdclk;
2393

2394
	vco = skl_dpll0_vco(cdclk_state);
2395 2396 2397 2398 2399

	/*
	 * FIXME should also account for plane ratio
	 * once 64bpp pixel formats are supported.
	 */
2400
	cdclk = skl_calc_cdclk(min_cdclk, vco);
2401

2402 2403 2404
	cdclk_state->logical.vco = vco;
	cdclk_state->logical.cdclk = cdclk;
	cdclk_state->logical.voltage_level =
2405
		skl_calc_voltage_level(cdclk);
2406

2407
	if (!cdclk_state->active_pipes) {
2408
		cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
2409

2410 2411 2412
		cdclk_state->actual.vco = vco;
		cdclk_state->actual.cdclk = cdclk;
		cdclk_state->actual.voltage_level =
2413
			skl_calc_voltage_level(cdclk);
2414
	} else {
2415
		cdclk_state->actual = cdclk_state->logical;
2416
	}
2417 2418 2419 2420

	return 0;
}

2421
static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2422
{
2423
	struct intel_atomic_state *state = cdclk_state->base.state;
2424
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2425
	int min_cdclk, min_voltage_level, cdclk, vco;
2426

2427
	min_cdclk = intel_compute_min_cdclk(cdclk_state);
2428 2429
	if (min_cdclk < 0)
		return min_cdclk;
2430

2431
	min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
2432 2433 2434
	if (min_voltage_level < 0)
		return min_voltage_level;

2435 2436
	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2437

2438 2439 2440
	cdclk_state->logical.vco = vco;
	cdclk_state->logical.cdclk = cdclk;
	cdclk_state->logical.voltage_level =
2441 2442
		max_t(int, min_voltage_level,
		      dev_priv->display.calc_voltage_level(cdclk));
2443

2444
	if (!cdclk_state->active_pipes) {
2445
		cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2446
		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2447

2448 2449 2450
		cdclk_state->actual.vco = vco;
		cdclk_state->actual.cdclk = cdclk;
		cdclk_state->actual.voltage_level =
2451
			dev_priv->display.calc_voltage_level(cdclk);
2452
	} else {
2453
		cdclk_state->actual = cdclk_state->logical;
2454 2455 2456 2457 2458
	}

	return 0;
}

2459
static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2460 2461 2462 2463 2464 2465 2466 2467
{
	int min_cdclk;

	/*
	 * We can't change the cdclk frequency, but we still want to
	 * check that the required minimum frequency doesn't exceed
	 * the actual cdclk frequency.
	 */
2468
	min_cdclk = intel_compute_min_cdclk(cdclk_state);
2469 2470 2471 2472 2473 2474
	if (min_cdclk < 0)
		return min_cdclk;

	return 0;
}

2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525
static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
{
	struct intel_cdclk_state *cdclk_state;

	cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
	if (!cdclk_state)
		return NULL;

	cdclk_state->pipe = INVALID_PIPE;

	return &cdclk_state->base;
}

static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
				      struct intel_global_state *state)
{
	kfree(state);
}

static const struct intel_global_state_funcs intel_cdclk_funcs = {
	.atomic_duplicate_state = intel_cdclk_duplicate_state,
	.atomic_destroy_state = intel_cdclk_destroy_state,
};

struct intel_cdclk_state *
intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
{
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
	struct intel_global_state *cdclk_state;

	cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
	if (IS_ERR(cdclk_state))
		return ERR_CAST(cdclk_state);

	return to_intel_cdclk_state(cdclk_state);
}

int intel_cdclk_init(struct drm_i915_private *dev_priv)
{
	struct intel_cdclk_state *cdclk_state;

	cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
	if (!cdclk_state)
		return -ENOMEM;

	intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
				     &cdclk_state->base, &intel_cdclk_funcs);

	return 0;
}

2526 2527 2528
int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
{
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2529 2530
	const struct intel_cdclk_state *old_cdclk_state;
	struct intel_cdclk_state *new_cdclk_state;
2531
	enum pipe pipe = INVALID_PIPE;
2532 2533
	int ret;

2534 2535 2536
	new_cdclk_state = intel_atomic_get_cdclk_state(state);
	if (IS_ERR(new_cdclk_state))
		return PTR_ERR(new_cdclk_state);
2537

2538
	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
2539

2540 2541 2542
	new_cdclk_state->active_pipes =
		intel_calc_active_pipes(state, old_cdclk_state->active_pipes);

2543
	ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
2544 2545 2546
	if (ret)
		return ret;

2547 2548
	if (intel_cdclk_changed(&old_cdclk_state->actual,
				&new_cdclk_state->actual)) {
2549 2550 2551 2552
		/*
		 * Also serialize commits across all crtcs
		 * if the actual hw needs to be poked.
		 */
2553
		ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
2554 2555
		if (ret)
			return ret;
2556
	} else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
2557
		   old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk ||
2558
		   intel_cdclk_changed(&old_cdclk_state->logical,
2559
				       &new_cdclk_state->logical)) {
2560
		ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
2561
		if (ret)
2562
			return ret;
2563 2564
	} else {
		return 0;
2565 2566
	}

2567
	if (is_power_of_2(new_cdclk_state->active_pipes) &&
2568
	    intel_cdclk_can_cd2x_update(dev_priv,
2569 2570
					&old_cdclk_state->actual,
					&new_cdclk_state->actual)) {
2571 2572 2573
		struct intel_crtc *crtc;
		struct intel_crtc_state *crtc_state;

2574
		pipe = ilog2(new_cdclk_state->active_pipes);
2575
		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
2576 2577 2578 2579 2580

		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
		if (IS_ERR(crtc_state))
			return PTR_ERR(crtc_state);

2581
		if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
2582 2583 2584
			pipe = INVALID_PIPE;
	}

2585 2586 2587 2588 2589 2590
	if (intel_cdclk_can_crawl(dev_priv,
				  &old_cdclk_state->actual,
				  &new_cdclk_state->actual)) {
		drm_dbg_kms(&dev_priv->drm,
			    "Can change cdclk via crawl\n");
	} else if (pipe != INVALID_PIPE) {
2591
		new_cdclk_state->pipe = pipe;
2592

2593
		drm_dbg_kms(&dev_priv->drm,
2594
			    "Can change cdclk cd2x divider with pipe %c active\n",
2595
			    pipe_name(pipe));
2596 2597
	} else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
					     &new_cdclk_state->actual)) {
2598
		/* All pipes must be switched off while we change the cdclk. */
2599 2600 2601 2602
		ret = intel_modeset_all_pipes(state);
		if (ret)
			return ret;

2603 2604
		drm_dbg_kms(&dev_priv->drm,
			    "Modeset required for cdclk change\n");
2605 2606
	}

2607 2608
	drm_dbg_kms(&dev_priv->drm,
		    "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
2609 2610
		    new_cdclk_state->logical.cdclk,
		    new_cdclk_state->actual.cdclk);
2611 2612
	drm_dbg_kms(&dev_priv->drm,
		    "New voltage level calculated to be logical %u, actual %u\n",
2613 2614
		    new_cdclk_state->logical.voltage_level,
		    new_cdclk_state->actual.voltage_level);
2615 2616 2617 2618

	return 0;
}

2619 2620 2621 2622
static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
{
	int max_cdclk_freq = dev_priv->max_cdclk_freq;

2623
	if (DISPLAY_VER(dev_priv) >= 10)
2624
		return 2 * max_cdclk_freq;
2625
	else if (DISPLAY_VER(dev_priv) == 9 ||
2626
		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2627 2628 2629
		return max_cdclk_freq;
	else if (IS_CHERRYVIEW(dev_priv))
		return max_cdclk_freq*95/100;
2630
	else if (DISPLAY_VER(dev_priv) < 4)
2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645
		return 2*max_cdclk_freq*90/100;
	else
		return max_cdclk_freq*90/100;
}

/**
 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
 * @dev_priv: i915 device
 *
 * Determine the maximum CDCLK frequency the platform supports, and also
 * derive the maximum dot clock frequency the maximum CDCLK frequency
 * allows.
 */
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
2646
	if (IS_JSL_EHL(dev_priv)) {
2647 2648 2649 2650
		if (dev_priv->cdclk.hw.ref == 24000)
			dev_priv->max_cdclk_freq = 552000;
		else
			dev_priv->max_cdclk_freq = 556800;
2651
	} else if (DISPLAY_VER(dev_priv) >= 11) {
2652 2653 2654 2655 2656
		if (dev_priv->cdclk.hw.ref == 24000)
			dev_priv->max_cdclk_freq = 648000;
		else
			dev_priv->max_cdclk_freq = 652800;
	} else if (IS_CANNONLAKE(dev_priv)) {
2657
		dev_priv->max_cdclk_freq = 528000;
2658 2659 2660 2661
	} else if (IS_GEMINILAKE(dev_priv)) {
		dev_priv->max_cdclk_freq = 316800;
	} else if (IS_BROXTON(dev_priv)) {
		dev_priv->max_cdclk_freq = 624000;
2662
	} else if (DISPLAY_VER(dev_priv) == 9) {
2663
		u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2664 2665 2666
		int max_cdclk, vco;

		vco = dev_priv->skl_preferred_vco_freq;
2667
		drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690

		/*
		 * Use the lower (vco 8640) cdclk values as a
		 * first guess. skl_calc_cdclk() will correct it
		 * if the preferred vco is 8100 instead.
		 */
		if (limit == SKL_DFSM_CDCLK_LIMIT_675)
			max_cdclk = 617143;
		else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
			max_cdclk = 540000;
		else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
			max_cdclk = 432000;
		else
			max_cdclk = 308571;

		dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
	} else if (IS_BROADWELL(dev_priv))  {
		/*
		 * FIXME with extra cooling we can allow
		 * 540 MHz for ULX and 675 Mhz for ULT.
		 * How can we know if extra cooling is
		 * available? PCI ID, VTB, something else?
		 */
2691
		if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704
			dev_priv->max_cdclk_freq = 450000;
		else if (IS_BDW_ULX(dev_priv))
			dev_priv->max_cdclk_freq = 450000;
		else if (IS_BDW_ULT(dev_priv))
			dev_priv->max_cdclk_freq = 540000;
		else
			dev_priv->max_cdclk_freq = 675000;
	} else if (IS_CHERRYVIEW(dev_priv)) {
		dev_priv->max_cdclk_freq = 320000;
	} else if (IS_VALLEYVIEW(dev_priv)) {
		dev_priv->max_cdclk_freq = 400000;
	} else {
		/* otherwise assume cdclk is fixed */
2705
		dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2706 2707 2708 2709
	}

	dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);

2710 2711
	drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
		dev_priv->max_cdclk_freq);
2712

2713 2714
	drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
		dev_priv->max_dotclk_freq);
2715 2716 2717 2718 2719 2720 2721 2722 2723 2724
}

/**
 * intel_update_cdclk - Determine the current CDCLK frequency
 * @dev_priv: i915 device
 *
 * Determine the current CDCLK frequency.
 */
void intel_update_cdclk(struct drm_i915_private *dev_priv)
{
2725
	dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2726 2727 2728 2729 2730 2731 2732 2733

	/*
	 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
	 * Programmng [sic] note: bit[9:2] should be programmed to the number
	 * of cdclk that generates 4MHz reference clock freq which is used to
	 * generate GMBus clock. This will vary with the cdclk freq.
	 */
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2734
		intel_de_write(dev_priv, GMBUSFREQ_VLV,
V
Ville Syrjälä 已提交
2735
			       DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2736 2737
}

2738 2739 2740 2741 2742 2743
static int dg1_rawclk(struct drm_i915_private *dev_priv)
{
	/*
	 * DG1 always uses a 38.4 MHz rawclk.  The bspec tells us
	 * "Program Numerator=2, Denominator=4, Divider=37 decimal."
	 */
2744 2745
	intel_de_write(dev_priv, PCH_RAWCLK_FREQ,
		       CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
2746 2747 2748 2749

	return 38400;
}

2750 2751 2752 2753 2754
static int cnp_rawclk(struct drm_i915_private *dev_priv)
{
	u32 rawclk;
	int divider, fraction;

2755
	if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2756 2757 2758 2759 2760 2761 2762 2763 2764
		/* 24 MHz */
		divider = 24000;
		fraction = 0;
	} else {
		/* 19.2 MHz */
		divider = 19000;
		fraction = 200;
	}

2765
	rawclk = CNP_RAWCLK_DIV(divider / 1000);
2766 2767
	if (fraction) {
		int numerator = 1;
2768

2769 2770
		rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
							   fraction) - 1);
2771
		if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2772
			rawclk |= ICP_RAWCLK_NUM(numerator);
2773 2774
	}

2775
	intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk);
2776
	return divider + fraction;
2777 2778
}

2779 2780
static int pch_rawclk(struct drm_i915_private *dev_priv)
{
2781
	return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2782 2783 2784 2785 2786 2787 2788 2789 2790
}

static int vlv_hrawclk(struct drm_i915_private *dev_priv)
{
	/* RAWCLK_FREQ_VLV register updated from power well code */
	return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
				      CCK_DISPLAY_REF_CLOCK_CONTROL);
}

2791
static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
2792
{
2793
	u32 clkcfg;
2794

2795 2796 2797 2798 2799 2800 2801 2802 2803 2804
	/*
	 * hrawclock is 1/4 the FSB frequency
	 *
	 * Note that this only reads the state of the FSB
	 * straps, not the actual FSB frequency. Some BIOSen
	 * let you configure each independently. Ideally we'd
	 * read out the actual FSB frequency but sadly we
	 * don't know which registers have that information,
	 * and all the relevant docs have gone to bit heaven :(
	 */
2805 2806
	clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;

2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843
	if (IS_MOBILE(dev_priv)) {
		switch (clkcfg) {
		case CLKCFG_FSB_400:
			return 100000;
		case CLKCFG_FSB_533:
			return 133333;
		case CLKCFG_FSB_667:
			return 166667;
		case CLKCFG_FSB_800:
			return 200000;
		case CLKCFG_FSB_1067:
			return 266667;
		case CLKCFG_FSB_1333:
			return 333333;
		default:
			MISSING_CASE(clkcfg);
			return 133333;
		}
	} else {
		switch (clkcfg) {
		case CLKCFG_FSB_400_ALT:
			return 100000;
		case CLKCFG_FSB_533:
			return 133333;
		case CLKCFG_FSB_667:
			return 166667;
		case CLKCFG_FSB_800:
			return 200000;
		case CLKCFG_FSB_1067_ALT:
			return 266667;
		case CLKCFG_FSB_1333_ALT:
			return 333333;
		case CLKCFG_FSB_1600_ALT:
			return 400000;
		default:
			return 133333;
		}
2844 2845 2846 2847
	}
}

/**
2848
 * intel_read_rawclk - Determine the current RAWCLK frequency
2849 2850 2851 2852 2853
 * @dev_priv: i915 device
 *
 * Determine the current RAWCLK frequency. RAWCLK is a fixed
 * frequency clock so this needs to done only once.
 */
2854
u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
2855
{
2856 2857
	u32 freq;

2858 2859 2860
	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
		freq = dg1_rawclk(dev_priv);
	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
2861
		freq = cnp_rawclk(dev_priv);
2862
	else if (HAS_PCH_SPLIT(dev_priv))
2863
		freq = pch_rawclk(dev_priv);
2864
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2865
		freq = vlv_hrawclk(dev_priv);
2866
	else if (DISPLAY_VER(dev_priv) >= 3)
2867
		freq = i9xx_hrawclk(dev_priv);
2868 2869
	else
		/* no rawclk on other platforms, or no need to know it */
2870
		return 0;
2871

2872
	return freq;
2873 2874 2875 2876 2877 2878 2879 2880
}

/**
 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
 * @dev_priv: i915 device
 */
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
2881 2882 2883 2884 2885
	if (IS_ALDERLAKE_P(dev_priv)) {
		dev_priv->display.set_cdclk = bxt_set_cdclk;
		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
2886 2887 2888 2889 2890
		/* Wa_22011320316:adlp[a0] */
		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
			dev_priv->cdclk.table = adlp_a_step_cdclk_table;
		else
			dev_priv->cdclk.table = adlp_cdclk_table;
2891
	} else if (IS_ROCKETLAKE(dev_priv)) {
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Matt Roper 已提交
2892 2893 2894 2895 2896
		dev_priv->display.set_cdclk = bxt_set_cdclk;
		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
		dev_priv->cdclk.table = rkl_cdclk_table;
2897
	} else if (DISPLAY_VER(dev_priv) >= 12) {
2898
		dev_priv->display.set_cdclk = bxt_set_cdclk;
2899
		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2900 2901 2902
		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
		dev_priv->cdclk.table = icl_cdclk_table;
2903
	} else if (IS_JSL_EHL(dev_priv)) {
2904
		dev_priv->display.set_cdclk = bxt_set_cdclk;
2905
		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2906
		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2907 2908
		dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
		dev_priv->cdclk.table = icl_cdclk_table;
2909
	} else if (DISPLAY_VER(dev_priv) >= 11) {
2910
		dev_priv->display.set_cdclk = bxt_set_cdclk;
2911
		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2912
		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2913
		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
2914
		dev_priv->cdclk.table = icl_cdclk_table;
2915
	} else if (IS_CANNONLAKE(dev_priv)) {
2916
		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2917
		dev_priv->display.set_cdclk = bxt_set_cdclk;
2918
		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2919
		dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
2920
		dev_priv->cdclk.table = cnl_cdclk_table;
2921
	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
2922
		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2923
		dev_priv->display.set_cdclk = bxt_set_cdclk;
2924
		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2925
		dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
2926 2927 2928 2929
		if (IS_GEMINILAKE(dev_priv))
			dev_priv->cdclk.table = glk_cdclk_table;
		else
			dev_priv->cdclk.table = bxt_cdclk_table;
2930
	} else if (DISPLAY_VER(dev_priv) == 9) {
2931
		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2932
		dev_priv->display.set_cdclk = skl_set_cdclk;
2933
		dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
2934
	} else if (IS_BROADWELL(dev_priv)) {
2935
		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
2936
		dev_priv->display.set_cdclk = bdw_set_cdclk;
2937
		dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
2938
	} else if (IS_CHERRYVIEW(dev_priv)) {
2939
		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
2940
		dev_priv->display.set_cdclk = chv_set_cdclk;
2941
		dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
2942
	} else if (IS_VALLEYVIEW(dev_priv)) {
2943
		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
2944
		dev_priv->display.set_cdclk = vlv_set_cdclk;
2945
		dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
2946
	} else {
2947
		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
2948
		dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
2949 2950
	}

2951
	if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
2952
		dev_priv->display.get_cdclk = bxt_get_cdclk;
2953
	else if (DISPLAY_VER(dev_priv) == 9)
2954
		dev_priv->display.get_cdclk = skl_get_cdclk;
2955 2956 2957 2958 2959 2960
	else if (IS_BROADWELL(dev_priv))
		dev_priv->display.get_cdclk = bdw_get_cdclk;
	else if (IS_HASWELL(dev_priv))
		dev_priv->display.get_cdclk = hsw_get_cdclk;
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		dev_priv->display.get_cdclk = vlv_get_cdclk;
2961
	else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
2962
		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2963
	else if (IS_IRONLAKE(dev_priv))
2964 2965 2966
		dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
	else if (IS_GM45(dev_priv))
		dev_priv->display.get_cdclk = gm45_get_cdclk;
2967
	else if (IS_G45(dev_priv))
2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990
		dev_priv->display.get_cdclk = g33_get_cdclk;
	else if (IS_I965GM(dev_priv))
		dev_priv->display.get_cdclk = i965gm_get_cdclk;
	else if (IS_I965G(dev_priv))
		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
	else if (IS_PINEVIEW(dev_priv))
		dev_priv->display.get_cdclk = pnv_get_cdclk;
	else if (IS_G33(dev_priv))
		dev_priv->display.get_cdclk = g33_get_cdclk;
	else if (IS_I945GM(dev_priv))
		dev_priv->display.get_cdclk = i945gm_get_cdclk;
	else if (IS_I945G(dev_priv))
		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
	else if (IS_I915GM(dev_priv))
		dev_priv->display.get_cdclk = i915gm_get_cdclk;
	else if (IS_I915G(dev_priv))
		dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
	else if (IS_I865G(dev_priv))
		dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
	else if (IS_I85X(dev_priv))
		dev_priv->display.get_cdclk = i85x_get_cdclk;
	else if (IS_I845G(dev_priv))
		dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2991 2992 2993 2994 2995
	else if (IS_I830(dev_priv))
		dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;

	if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk,
		     "Unknown platform. Assuming 133 MHz CDCLK\n"))
2996 2997
		dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
}