sun7i-a20.dtsi 36.1 KB
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/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
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 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
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 *
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 *  a) This file is free software; you can redistribute it and/or
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 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
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 *     This file is distributed in the hope that it will be useful,
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 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
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 */

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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/dma/sun4i-a10.h>
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#include <dt-bindings/clock/sun7i-a20-ccu.h>
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#include <dt-bindings/reset/sun4i-a10-ccu.h>
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/ {
	interrupt-parent = <&gic>;
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	#address-cells = <1>;
	#size-cells = <1>;
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	aliases {
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		ethernet0 = &gmac;
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	};

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	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

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		framebuffer-lcd0-hdmi {
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			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
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			allwinner,pipeline = "de_be0-lcd0-hdmi";
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			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
				 <&ccu CLK_HDMI>;
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			status = "disabled";
		};
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		framebuffer-lcd0 {
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			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0";
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			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
				 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
				 <&ccu CLK_DRAM_DE_BE0>;
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			status = "disabled";
		};

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		framebuffer-lcd0-tve0 {
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			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0-tve0";
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			clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
				 <&ccu CLK_AHB_DE_BE0>,
				 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
				 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
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			status = "disabled";
		};
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	};

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	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

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		cpu0: cpu@0 {
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			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
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			clocks = <&ccu CLK_CPU>;
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			clock-latency = <244144>; /* 8 32k periods */
			operating-points = <
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				/* kHz	  uV */
				960000	1400000
				912000	1400000
				864000	1300000
				720000	1200000
				528000	1100000
				312000	1000000
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				144000	1000000
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				>;
			#cooling-cells = <2>;
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		};

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		cpu1: cpu@1 {
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			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
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			clocks = <&ccu CLK_CPU>;
			clock-latency = <244144>; /* 8 32k periods */
			operating-points = <
				/* kHz	  uV */
				960000	1400000
				912000	1400000
				864000	1300000
				720000	1200000
				528000	1100000
				312000	1000000
				144000	1000000
				>;
			#cooling-cells = <2>;
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		};
	};

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	thermal-zones {
		cpu_thermal {
			/* milliseconds */
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&rtp>;

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
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					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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				};
			};

			trips {
				cpu_alert0: cpu_alert0 {
					/* milliCelsius */
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu_crit {
					/* milliCelsius */
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

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	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
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		default-pool {
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			compatible = "shared-dma-pool";
			size = <0x6000000>;
			alloc-ranges = <0x4a000000 0x6000000>;
			reusable;
			linux,cma-default;
		};
	};

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	timer {
		compatible = "arm,armv7-timer";
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		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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	};

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	pmu {
		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
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		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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	};

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	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

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		osc24M: clk-24M {
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			#clock-cells = <0>;
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			compatible = "fixed-clock";
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			clock-frequency = <24000000>;
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			clock-output-names = "osc24M";
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		};

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		osc32k: clk-32k {
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			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
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			clock-output-names = "osc32k";
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		};
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		/*
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		 * The following two are dummy clocks, placeholders
		 * used in the gmac_tx clock. The gmac driver will
		 * choose one parent depending on the PHY interface
		 * mode, using clk_set_rate auto-reparenting.
		 *
		 * The actual TX clock rate is not controlled by the
		 * gmac_tx clock.
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		 */
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		mii_phy_tx_clk: clk-mii-phy-tx {
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			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
			clock-output-names = "mii_phy_tx";
		};

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		gmac_int_tx_clk: clk-gmac-int-tx {
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			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <125000000>;
			clock-output-names = "gmac_int_tx";
		};

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		gmac_tx_clk: clk@1c20164 {
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			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-gmac-clk";
			reg = <0x01c20164 0x4>;
			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
			clock-output-names = "gmac_tx";
		};
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	};
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	de: display-engine {
		compatible = "allwinner,sun7i-a20-display-engine";
		allwinner,pipelines = <&fe0>, <&fe1>;
		status = "disabled";
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	};

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	soc {
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		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

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		system-control@1c00000 {
			compatible = "allwinner,sun7i-a20-system-control",
				     "allwinner,sun4i-a10-system-control";
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			reg = <0x01c00000 0x30>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

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			sram_a: sram@0 {
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				compatible = "mmio-sram";
				reg = <0x00000000 0xc000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00000000 0xc000>;

				emac_sram: sram-section@8000 {
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					compatible = "allwinner,sun7i-a20-sram-a3-a4",
						     "allwinner,sun4i-a10-sram-a3-a4";
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					reg = <0x8000 0x4000>;
					status = "disabled";
				};
			};

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			sram_d: sram@10000 {
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				compatible = "mmio-sram";
				reg = <0x00010000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00010000 0x1000>;

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				otg_sram: sram-section@0 {
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					compatible = "allwinner,sun7i-a20-sram-d",
						     "allwinner,sun4i-a10-sram-d";
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					reg = <0x0000 0x1000>;
					status = "disabled";
				};
			};
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			sram_c: sram@1d00000 {
				compatible = "mmio-sram";
				reg = <0x01d00000 0xd0000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x01d00000 0xd0000>;

				ve_sram: sram-section@0 {
					compatible = "allwinner,sun7i-a20-sram-c1",
						     "allwinner,sun4i-a10-sram-c1";
					reg = <0x000000 0x80000>;
				};
			};
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		};

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		nmi_intc: interrupt-controller@1c00030 {
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			compatible = "allwinner,sun7i-a20-sc-nmi";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x01c00030 0x0c>;
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			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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		};

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		dma: dma-controller@1c02000 {
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			compatible = "allwinner,sun4i-a10-dma";
			reg = <0x01c02000 0x1000>;
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			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_DMA>;
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			#dma-cells = <2>;
		};

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		nfc: nand@1c03000 {
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			compatible = "allwinner,sun4i-a10-nand";
			reg = <0x01c03000 0x1000>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
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			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 3>;
			dma-names = "rxtx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

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		spi0: spi@1c05000 {
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			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c05000 0x1000>;
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			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
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			clock-names = "ahb", "mod";
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			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
			       <&dma SUN4I_DMA_DEDICATED 26>;
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			dma-names = "rx", "tx";
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			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
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			num-cs = <4>;
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		};

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		spi1: spi@1c06000 {
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			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c06000 0x1000>;
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			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
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			clock-names = "ahb", "mod";
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			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
			       <&dma SUN4I_DMA_DEDICATED 8>;
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			dma-names = "rx", "tx";
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			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
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			num-cs = <1>;
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		};

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		emac: ethernet@1c0b000 {
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			compatible = "allwinner,sun4i-a10-emac";
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			reg = <0x01c0b000 0x1000>;
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			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_EMAC>;
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			allwinner,sram = <&emac_sram 1>;
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			status = "disabled";
		};

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		mdio: mdio@1c0b080 {
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			compatible = "allwinner,sun4i-a10-mdio";
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			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

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		tcon0: lcd-controller@1c0c000 {
			compatible = "allwinner,sun7i-a20-tcon";
			reg = <0x01c0c000 0x1000>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&ccu RST_TCON0>;
			reset-names = "lcd";
			clocks = <&ccu CLK_AHB_LCD0>,
				 <&ccu CLK_TCON0_CH0>,
				 <&ccu CLK_TCON0_CH1>;
			clock-names = "ahb",
				      "tcon-ch0",
				      "tcon-ch1";
			clock-output-names = "tcon0-pixel-clock";
			dmas = <&dma SUN4I_DMA_DEDICATED 14>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				tcon0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					tcon0_in_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_out_tcon0>;
					};

					tcon0_in_be1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&be1_out_tcon0>;
					};
				};

				tcon0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					tcon0_out_hdmi: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&hdmi_in_tcon0>;
						allwinner,tcon-channel = <1>;
					};
				};
			};
		};

		tcon1: lcd-controller@1c0d000 {
			compatible = "allwinner,sun7i-a20-tcon";
			reg = <0x01c0d000 0x1000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&ccu RST_TCON1>;
			reset-names = "lcd";
			clocks = <&ccu CLK_AHB_LCD1>,
				 <&ccu CLK_TCON1_CH0>,
				 <&ccu CLK_TCON1_CH1>;
			clock-names = "ahb",
				      "tcon-ch0",
				      "tcon-ch1";
			clock-output-names = "tcon1-pixel-clock";
			dmas = <&dma SUN4I_DMA_DEDICATED 15>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				tcon1_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					tcon1_in_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_out_tcon1>;
					};

					tcon1_in_be1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&be1_out_tcon1>;
					};
				};

				tcon1_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					tcon1_out_hdmi: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&hdmi_in_tcon1>;
						allwinner,tcon-channel = <1>;
					};
				};
			};
		};

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		video-codec@1c0e000 {
			compatible = "allwinner,sun7i-a20-video-engine";
			reg = <0x01c0e000 0x1000>;
			clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
				 <&ccu CLK_DRAM_VE>;
			clock-names = "ahb", "mod", "ram";
			resets = <&ccu RST_VE>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
			allwinner,sram = <&ve_sram 1>;
		};

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		mmc0: mmc@1c0f000 {
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			compatible = "allwinner,sun7i-a20-mmc";
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			reg = <0x01c0f000 0x1000>;
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			clocks = <&ccu CLK_AHB_MMC0>,
				 <&ccu CLK_MMC0>,
				 <&ccu CLK_MMC0_OUTPUT>,
				 <&ccu CLK_MMC0_SAMPLE>;
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			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
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			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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			status = "disabled";
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			#address-cells = <1>;
			#size-cells = <0>;
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		};

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		mmc1: mmc@1c10000 {
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			compatible = "allwinner,sun7i-a20-mmc";
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			reg = <0x01c10000 0x1000>;
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			clocks = <&ccu CLK_AHB_MMC1>,
				 <&ccu CLK_MMC1>,
				 <&ccu CLK_MMC1_OUTPUT>,
				 <&ccu CLK_MMC1_SAMPLE>;
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			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
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			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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			status = "disabled";
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			#address-cells = <1>;
			#size-cells = <0>;
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		};

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		mmc2: mmc@1c11000 {
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			compatible = "allwinner,sun7i-a20-mmc";
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			reg = <0x01c11000 0x1000>;
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			clocks = <&ccu CLK_AHB_MMC2>,
				 <&ccu CLK_MMC2>,
				 <&ccu CLK_MMC2_OUTPUT>,
				 <&ccu CLK_MMC2_SAMPLE>;
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			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
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			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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			status = "disabled";
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			#address-cells = <1>;
			#size-cells = <0>;
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		};

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		mmc3: mmc@1c12000 {
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			compatible = "allwinner,sun7i-a20-mmc";
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			reg = <0x01c12000 0x1000>;
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			clocks = <&ccu CLK_AHB_MMC3>,
				 <&ccu CLK_MMC3>,
				 <&ccu CLK_MMC3_OUTPUT>,
				 <&ccu CLK_MMC3_SAMPLE>;
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			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
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			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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			status = "disabled";
569 570
			#address-cells = <1>;
			#size-cells = <0>;
571 572
		};

573
		usb_otg: usb@1c13000 {
574 575
			compatible = "allwinner,sun4i-a10-musb";
			reg = <0x01c13000 0x0400>;
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576
			clocks = <&ccu CLK_AHB_OTG>;
577 578 579 580 581 582 583 584 585
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mc";
			phys = <&usbphy 0>;
			phy-names = "usb";
			extcon = <&usbphy 0>;
			allwinner,sram = <&otg_sram 1>;
			status = "disabled";
		};

586
		usbphy: phy@1c13400 {
587 588 589 590
			#phy-cells = <1>;
			compatible = "allwinner,sun7i-a20-usb-phy";
			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
			reg-names = "phy_ctrl", "pmu1", "pmu2";
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591
			clocks = <&ccu CLK_USB_PHY>;
592
			clock-names = "usb_phy";
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593 594 595
			resets = <&ccu RST_USB_PHY0>,
				 <&ccu RST_USB_PHY1>,
				 <&ccu RST_USB_PHY2>;
596
			reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
597 598 599
			status = "disabled";
		};

600
		ehci0: usb@1c14000 {
601 602
			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
			reg = <0x01c14000 0x100>;
603
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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604
			clocks = <&ccu CLK_AHB_EHCI0>;
605 606 607 608 609
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

610
		ohci0: usb@1c14400 {
611 612
			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
			reg = <0x01c14400 0x100>;
613
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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614
			clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
615 616 617 618 619
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

620
		crypto: crypto-engine@1c15000 {
621 622
			compatible = "allwinner,sun7i-a20-crypto",
				     "allwinner,sun4i-a10-crypto";
623 624
			reg = <0x01c15000 0x1000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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625
			clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
626 627 628
			clock-names = "ahb", "mod";
		};

629 630 631 632 633 634
		hdmi: hdmi@1c16000 {
			compatible = "allwinner,sun7i-a20-hdmi",
				     "allwinner,sun5i-a10s-hdmi";
			reg = <0x01c16000 0x1000>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
635 636
				 <&ccu CLK_PLL_VIDEO0_2X>,
				 <&ccu CLK_PLL_VIDEO1_2X>;
637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671
			clock-names = "ahb", "mod", "pll-0", "pll-1";
			dmas = <&dma SUN4I_DMA_NORMAL 16>,
			       <&dma SUN4I_DMA_NORMAL 16>,
			       <&dma SUN4I_DMA_DEDICATED 24>;
			dma-names = "ddc-tx", "ddc-rx", "audio-tx";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				hdmi_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					hdmi_in_tcon0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&tcon0_out_hdmi>;
					};

					hdmi_in_tcon1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&tcon1_out_hdmi>;
					};
				};

				hdmi_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;
				};
			};
		};

672
		spi2: spi@1c17000 {
673 674
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c17000 0x1000>;
675
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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676
			clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
677
			clock-names = "ahb", "mod";
678 679
			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
			       <&dma SUN4I_DMA_DEDICATED 28>;
680
			dma-names = "rx", "tx";
681 682 683
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
684
			num-cs = <1>;
685 686
		};

687
		ahci: sata@1c18000 {
688 689
			compatible = "allwinner,sun4i-a10-ahci";
			reg = <0x01c18000 0x1000>;
690
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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691
			clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
692 693 694
			status = "disabled";
		};

695
		ehci1: usb@1c1c000 {
696 697
			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
			reg = <0x01c1c000 0x100>;
698
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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699
			clocks = <&ccu CLK_AHB_EHCI1>;
700 701 702 703 704
			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

705
		ohci1: usb@1c1c400 {
706 707
			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
			reg = <0x01c1c400 0x100>;
708
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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709
			clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
710 711 712 713 714
			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

715
		spi3: spi@1c1f000 {
716 717
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c1f000 0x1000>;
718
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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719
			clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
720
			clock-names = "ahb", "mod";
721 722
			dmas = <&dma SUN4I_DMA_DEDICATED 31>,
			       <&dma SUN4I_DMA_DEDICATED 30>;
723
			dma-names = "rx", "tx";
724
			status = "disabled";
725 726
			#address-cells = <1>;
			#size-cells = <0>;
727
			num-cs = <1>;
728 729
		};

730
		ccu: clock@1c20000 {
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731 732 733 734 735 736 737 738
			compatible = "allwinner,sun7i-a20-ccu";
			reg = <0x01c20000 0x400>;
			clocks = <&osc24M>, <&osc32k>;
			clock-names = "hosc", "losc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

739
		pio: pinctrl@1c20800 {
740 741
			compatible = "allwinner,sun7i-a20-pinctrl";
			reg = <0x01c20800 0x400>;
742
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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743
			clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
744
			clock-names = "apb", "hosc", "losc";
745 746
			gpio-controller;
			interrupt-controller;
747
			#interrupt-cells = <3>;
748
			#gpio-cells = <3>;
749

750
			can_ph_pins: can-ph-pins {
751 752 753 754
				pins = "PH20", "PH21";
				function = "can";
			};

755
			clk_out_a_pin: clk-out-a-pin {
756 757
				pins = "PI12";
				function = "clk_out_a";
758 759
			};

760
			clk_out_b_pin: clk-out-b-pin {
761 762
				pins = "PI13";
				function = "clk_out_b";
763 764
			};

765
			emac_pa_pins: emac-pa-pins {
766 767 768 769 770 771
				pins = "PA0", "PA1", "PA2",
				       "PA3", "PA4", "PA5", "PA6",
				       "PA7", "PA8", "PA9", "PA10",
				       "PA11", "PA12", "PA13", "PA14",
				       "PA15", "PA16";
				function = "emac";
772 773
			};

774
			gmac_mii_pins: gmac-mii-pins {
775 776 777 778 779 780
				pins = "PA0", "PA1", "PA2",
				       "PA3", "PA4", "PA5", "PA6",
				       "PA7", "PA8", "PA9", "PA10",
				       "PA11", "PA12", "PA13", "PA14",
				       "PA15", "PA16";
				function = "gmac";
781 782
			};

783
			gmac_rgmii_pins: gmac-rgmii-pins {
784 785 786 787 788 789
				pins = "PA0", "PA1", "PA2",
				       "PA3", "PA4", "PA5", "PA6",
				        "PA7", "PA8", "PA10",
				       "PA11", "PA12", "PA13",
				       "PA15", "PA16";
				function = "gmac";
790 791 792 793
				/*
				 * data lines in RGMII mode use DDR mode
				 * and need a higher signal drive strength
				 */
794
				drive-strength = <40>;
795 796
			};

797
			i2c0_pins: i2c0-pins {
798 799
				pins = "PB0", "PB1";
				function = "i2c0";
800 801
			};

802
			i2c1_pins: i2c1-pins {
803 804
				pins = "PB18", "PB19";
				function = "i2c1";
805 806
			};

807
			i2c2_pins: i2c2-pins {
808 809
				pins = "PB20", "PB21";
				function = "i2c2";
810 811
			};

812
			i2c3_pins: i2c3-pins {
813 814
				pins = "PI0", "PI1";
				function = "i2c3";
815 816
			};

817
			ir0_rx_pin: ir0-rx-pin {
818 819
				pins = "PB4";
				function = "ir0";
820 821
			};

822
			ir0_tx_pin: ir0-tx-pin {
823 824
				pins = "PB3";
				function = "ir0";
825
			};
826

827
			ir1_rx_pin: ir1-rx-pin {
828 829
				pins = "PB23";
				function = "ir1";
830 831
			};

832
			ir1_tx_pin: ir1-tx-pin {
833 834
				pins = "PB22";
				function = "ir1";
835 836
			};

837
			mmc0_pins: mmc0-pins {
838 839 840 841
				pins = "PF0", "PF1", "PF2",
				       "PF3", "PF4", "PF5";
				function = "mmc0";
				drive-strength = <30>;
842
				bias-pull-up;
843 844
			};

845
			mmc2_pins: mmc2-pins {
846 847 848 849 850
				pins = "PC6", "PC7", "PC8",
				       "PC9", "PC10", "PC11";
				function = "mmc2";
				drive-strength = <30>;
				bias-pull-up;
851 852
			};

853
			mmc3_pins: mmc3-pins {
854 855 856 857
				pins = "PI4", "PI5", "PI6",
				       "PI7", "PI8", "PI9";
				function = "mmc3";
				drive-strength = <30>;
858
				bias-pull-up;
859 860
			};

861
			ps2_0_pins: ps2-0-pins {
862 863
				pins = "PI20", "PI21";
				function = "ps2";
864
			};
865

866
			ps2_1_ph_pins: ps2-1-ph-pins {
867 868
				pins = "PH12", "PH13";
				function = "ps2";
869 870
			};

871
			pwm0_pin: pwm0-pin {
872 873
				pins = "PB2";
				function = "pwm";
874
			};
875

876
			pwm1_pin: pwm1-pin {
877 878
				pins = "PI3";
				function = "pwm";
879 880
			};

881
			spdif_tx_pin: spdif-tx-pin {
882 883 884
				pins = "PB13";
				function = "spdif";
				bias-pull-up;
885
			};
886

887
			spi0_pi_pins: spi0-pi-pins {
888 889
				pins = "PI11", "PI12", "PI13";
				function = "spi0";
890 891
			};

892
			spi0_cs0_pi_pin: spi0-cs0-pi-pin {
893 894
				pins = "PI10";
				function = "spi0";
895 896
			};

897
			spi0_cs1_pi_pin: spi0-cs1-pi-pin {
898 899
				pins = "PI14";
				function = "spi0";
900 901
			};

902
			spi1_pi_pins: spi1-pi-pins {
903 904
				pins = "PI17", "PI18", "PI19";
				function = "spi1";
905 906
			};

907
			spi1_cs0_pi_pin: spi1-cs0-pi-pin {
908 909
				pins = "PI16";
				function = "spi1";
910 911
			};

912 913
			spi2_pb_pins: spi2-pb-pins {
				pins = "PB15", "PB16", "PB17";
914
				function = "spi2";
915 916
			};

917 918
			spi2_cs0_pb_pin: spi2-cs0-pb-pin {
				pins = "PB14";
919
				function = "spi2";
920 921
			};

922 923
			spi2_pc_pins: spi2-pc-pins {
				pins = "PC20", "PC21", "PC22";
924
				function = "spi2";
925 926
			};

927 928
			spi2_cs0_pc_pin: spi2-cs0-pc-pin {
				pins = "PC19";
929
				function = "spi2";
930
			};
931

932
			uart0_pb_pins: uart0-pb-pins {
933 934
				pins = "PB22", "PB23";
				function = "uart0";
935 936
			};

937
			uart2_pi_pins: uart2-pi-pins {
938 939 940 941 942 943
				pins = "PI18", "PI19";
				function = "uart2";
			};

			uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
				pins = "PI16", "PI17";
944
				function = "uart2";
945
			};
946

947
			uart3_pg_pins: uart3-pg-pins {
948 949 950 951 952 953
				pins = "PG6", "PG7";
				function = "uart3";
			};

			uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
				pins = "PG8", "PG9";
954
				function = "uart3";
955 956
			};

957
			uart3_ph_pins: uart3-ph-pins {
958 959
				pins = "PH0", "PH1";
				function = "uart3";
960 961
			};

962
			uart4_pg_pins: uart4-pg-pins {
963 964
				pins = "PG10", "PG11";
				function = "uart4";
965 966
			};

967
			uart4_ph_pins: uart4-ph-pins {
968 969
				pins = "PH4", "PH5";
				function = "uart4";
970
			};
971

972
			uart5_pi_pins: uart5-pi-pins {
973 974
				pins = "PI10", "PI11";
				function = "uart5";
975 976
			};

977
			uart6_pi_pins: uart6-pi-pins {
978 979
				pins = "PI12", "PI13";
				function = "uart6";
980
			};
981

982
			uart7_pi_pins: uart7-pi-pins {
983 984
				pins = "PI20", "PI21";
				function = "uart7";
985
			};
986 987
		};

988
		timer@1c20c00 {
989
			compatible = "allwinner,sun4i-a10-timer";
990
			reg = <0x01c20c00 0x90>;
991 992 993 994 995 996
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
997 998 999
			clocks = <&osc24M>;
		};

1000
		wdt: watchdog@1c20c90 {
1001
			compatible = "allwinner,sun4i-a10-wdt";
1002 1003 1004
			reg = <0x01c20c90 0x10>;
		};

1005
		rtc: rtc@1c20d00 {
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1006 1007
			compatible = "allwinner,sun7i-a20-rtc";
			reg = <0x01c20d00 0x20>;
1008
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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1009 1010
		};

1011
		pwm: pwm@1c20e00 {
1012 1013 1014 1015 1016 1017 1018
			compatible = "allwinner,sun7i-a20-pwm";
			reg = <0x01c20e00 0xc>;
			clocks = <&osc24M>;
			#pwm-cells = <3>;
			status = "disabled";
		};

1019
		spdif: spdif@1c21000 {
1020 1021 1022 1023
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun4i-a10-spdif";
			reg = <0x01c21000 0x400>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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1024
			clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
1025 1026 1027 1028 1029 1030 1031
			clock-names = "apb", "spdif";
			dmas = <&dma SUN4I_DMA_NORMAL 2>,
			       <&dma SUN4I_DMA_NORMAL 2>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

1032
		ir0: ir@1c21800 {
1033
			compatible = "allwinner,sun4i-a10-ir";
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1034
			clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1035
			clock-names = "apb", "ir";
1036
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1037 1038 1039 1040
			reg = <0x01c21800 0x40>;
			status = "disabled";
		};

1041
		ir1: ir@1c21c00 {
1042
			compatible = "allwinner,sun4i-a10-ir";
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1043
			clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1044
			clock-names = "apb", "ir";
1045
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1046 1047 1048 1049
			reg = <0x01c21c00 0x40>;
			status = "disabled";
		};

1050
		i2s1: i2s@1c22000 {
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1051 1052 1053 1054
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun4i-a10-i2s";
			reg = <0x01c22000 0x400>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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1055
			clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
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1056 1057 1058 1059 1060 1061 1062
			clock-names = "apb", "mod";
			dmas = <&dma SUN4I_DMA_NORMAL 4>,
			       <&dma SUN4I_DMA_NORMAL 4>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

1063
		i2s0: i2s@1c22400 {
M
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1064 1065 1066 1067
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun4i-a10-i2s";
			reg = <0x01c22400 0x400>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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1068
			clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
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1069 1070 1071 1072 1073 1074 1075
			clock-names = "apb", "mod";
			dmas = <&dma SUN4I_DMA_NORMAL 3>,
			       <&dma SUN4I_DMA_NORMAL 3>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

1076
		lradc: lradc@1c22800 {
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1077 1078
			compatible = "allwinner,sun4i-a10-lradc-keys";
			reg = <0x01c22800 0x100>;
1079
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
H
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1080 1081 1082
			status = "disabled";
		};

1083
		codec: codec@1c22c00 {
1084 1085 1086 1087
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun7i-a20-codec";
			reg = <0x01c22c00 0x40>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
P
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1088
			clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1089 1090 1091 1092 1093 1094 1095
			clock-names = "apb", "codec";
			dmas = <&dma SUN4I_DMA_NORMAL 19>,
			       <&dma SUN4I_DMA_NORMAL 19>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

1096
		sid: eeprom@1c23800 {
1097 1098 1099 1100
			compatible = "allwinner,sun7i-a20-sid";
			reg = <0x01c23800 0x200>;
		};

1101
		i2s2: i2s@1c24400 {
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1102 1103 1104 1105
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun4i-a10-i2s";
			reg = <0x01c24400 0x400>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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1106
			clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
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1107 1108 1109 1110 1111 1112 1113
			clock-names = "apb", "mod";
			dmas = <&dma SUN4I_DMA_NORMAL 6>,
			       <&dma SUN4I_DMA_NORMAL 6>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

1114
		rtp: rtp@1c25000 {
1115
			compatible = "allwinner,sun5i-a13-ts";
1116
			reg = <0x01c25000 0x100>;
1117
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1118
			#thermal-sensor-cells = <0>;
1119 1120
		};

1121
		uart0: serial@1c28000 {
1122 1123
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
1124
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1125 1126
			reg-shift = <2>;
			reg-io-width = <4>;
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1127
			clocks = <&ccu CLK_APB1_UART0>;
1128 1129 1130
			status = "disabled";
		};

1131
		uart1: serial@1c28400 {
1132 1133
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
1134
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1135 1136
			reg-shift = <2>;
			reg-io-width = <4>;
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1137
			clocks = <&ccu CLK_APB1_UART1>;
1138 1139 1140
			status = "disabled";
		};

1141
		uart2: serial@1c28800 {
1142 1143
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
1144
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1145 1146
			reg-shift = <2>;
			reg-io-width = <4>;
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1147
			clocks = <&ccu CLK_APB1_UART2>;
1148 1149 1150
			status = "disabled";
		};

1151
		uart3: serial@1c28c00 {
1152 1153
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
1154
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1155 1156
			reg-shift = <2>;
			reg-io-width = <4>;
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1157
			clocks = <&ccu CLK_APB1_UART3>;
1158 1159 1160
			status = "disabled";
		};

1161
		uart4: serial@1c29000 {
1162 1163
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
1164
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1165 1166
			reg-shift = <2>;
			reg-io-width = <4>;
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1167
			clocks = <&ccu CLK_APB1_UART4>;
1168 1169 1170
			status = "disabled";
		};

1171
		uart5: serial@1c29400 {
1172 1173
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
1174
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1175 1176
			reg-shift = <2>;
			reg-io-width = <4>;
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			clocks = <&ccu CLK_APB1_UART5>;
1178 1179 1180
			status = "disabled";
		};

1181
		uart6: serial@1c29800 {
1182 1183
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29800 0x400>;
1184
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1185 1186
			reg-shift = <2>;
			reg-io-width = <4>;
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			clocks = <&ccu CLK_APB1_UART6>;
1188 1189 1190
			status = "disabled";
		};

1191
		uart7: serial@1c29c00 {
1192 1193
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29c00 0x400>;
1194
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1195 1196
			reg-shift = <2>;
			reg-io-width = <4>;
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			clocks = <&ccu CLK_APB1_UART7>;
1198 1199 1200
			status = "disabled";
		};

1201
		ps20: ps2@1c2a000 {
1202 1203 1204
			compatible = "allwinner,sun4i-a10-ps2";
			reg = <0x01c2a000 0x400>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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1205
			clocks = <&ccu CLK_APB1_PS20>;
1206 1207 1208
			status = "disabled";
		};

1209
		ps21: ps2@1c2a400 {
1210 1211 1212
			compatible = "allwinner,sun4i-a10-ps2";
			reg = <0x01c2a400 0x400>;
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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1213
			clocks = <&ccu CLK_APB1_PS21>;
1214 1215 1216
			status = "disabled";
		};

1217
		i2c0: i2c@1c2ac00 {
1218 1219
			compatible = "allwinner,sun7i-a20-i2c",
				     "allwinner,sun4i-a10-i2c";
1220
			reg = <0x01c2ac00 0x400>;
1221
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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1222
			clocks = <&ccu CLK_APB1_I2C0>;
1223
			status = "disabled";
1224 1225
			#address-cells = <1>;
			#size-cells = <0>;
1226 1227
		};

1228
		i2c1: i2c@1c2b000 {
1229 1230
			compatible = "allwinner,sun7i-a20-i2c",
				     "allwinner,sun4i-a10-i2c";
1231
			reg = <0x01c2b000 0x400>;
1232
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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1233
			clocks = <&ccu CLK_APB1_I2C1>;
1234
			status = "disabled";
1235 1236
			#address-cells = <1>;
			#size-cells = <0>;
1237 1238
		};

1239
		i2c2: i2c@1c2b400 {
1240 1241
			compatible = "allwinner,sun7i-a20-i2c",
				     "allwinner,sun4i-a10-i2c";
1242
			reg = <0x01c2b400 0x400>;
1243
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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1244
			clocks = <&ccu CLK_APB1_I2C2>;
1245
			status = "disabled";
1246 1247
			#address-cells = <1>;
			#size-cells = <0>;
1248 1249
		};

1250
		i2c3: i2c@1c2b800 {
1251 1252
			compatible = "allwinner,sun7i-a20-i2c",
				     "allwinner,sun4i-a10-i2c";
1253
			reg = <0x01c2b800 0x400>;
1254
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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1255
			clocks = <&ccu CLK_APB1_I2C3>;
1256
			status = "disabled";
1257 1258
			#address-cells = <1>;
			#size-cells = <0>;
1259 1260
		};

1261
		can0: can@1c2bc00 {
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1262 1263 1264 1265
			compatible = "allwinner,sun7i-a20-can",
				     "allwinner,sun4i-a10-can";
			reg = <0x01c2bc00 0x400>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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1266
			clocks = <&ccu CLK_APB1_CAN>;
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1267 1268 1269
			status = "disabled";
		};

1270
		i2c4: i2c@1c2c000 {
1271 1272
			compatible = "allwinner,sun7i-a20-i2c",
				     "allwinner,sun4i-a10-i2c";
1273
			reg = <0x01c2c000 0x400>;
1274
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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1275
			clocks = <&ccu CLK_APB1_I2C4>;
1276
			status = "disabled";
1277 1278
			#address-cells = <1>;
			#size-cells = <0>;
1279 1280
		};

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1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305
		mali: gpu@1c40000 {
			compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
			reg = <0x01c40000 0x10000>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gp",
					  "gpmmu",
					  "pp0",
					  "ppmmu0",
					  "pp1",
					  "ppmmu1",
					  "pmu";
			clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
			clock-names = "bus", "core";
			resets = <&ccu RST_GPU>;

			assigned-clocks = <&ccu CLK_GPU>;
			assigned-clock-rates = <384000000>;
		};

1306
		gmac: ethernet@1c50000 {
1307 1308
			compatible = "allwinner,sun7i-a20-gmac";
			reg = <0x01c50000 0x10000>;
1309
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1310
			interrupt-names = "macirq";
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			clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1312 1313 1314 1315 1316 1317 1318 1319 1320
			clock-names = "stmmaceth", "allwinner_gmac_tx";
			snps,pbl = <2>;
			snps,fixed-burst;
			snps,force_sf_dma_mode;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

1321
		hstimer@1c60000 {
1322 1323
			compatible = "allwinner,sun7i-a20-hstimer";
			reg = <0x01c60000 0x1000>;
1324 1325 1326 1327
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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1328
			clocks = <&ccu CLK_AHB_HSTIMER>;
1329 1330
		};

1331
		gic: interrupt-controller@1c81000 {
1332
			compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1333
			reg = <0x01c81000 0x1000>,
1334
			      <0x01c82000 0x2000>,
1335 1336 1337 1338
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
1339
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1340
		};
1341

1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442
		fe0: display-frontend@1e00000 {
			compatible = "allwinner,sun7i-a20-display-frontend";
			reg = <0x01e00000 0x20000>;
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
				 <&ccu CLK_DRAM_DE_FE0>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&ccu RST_DE_FE0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				fe0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					fe0_out_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_in_fe0>;
					};

					fe0_out_be1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&be1_in_fe0>;
					};
				};
			};
		};

		fe1: display-frontend@1e20000 {
			compatible = "allwinner,sun7i-a20-display-frontend";
			reg = <0x01e20000 0x20000>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
				 <&ccu CLK_DRAM_DE_FE1>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&ccu RST_DE_FE1>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				fe1_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					fe1_out_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_in_fe1>;
					};

					fe1_out_be1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&be1_in_fe1>;
					};
				};
			};
		};

		be1: display-backend@1e40000 {
			compatible = "allwinner,sun7i-a20-display-backend";
			reg = <0x01e40000 0x10000>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
				 <&ccu CLK_DRAM_DE_BE1>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&ccu RST_DE_BE1>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				be1_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					be1_in_fe0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&fe0_out_be1>;
					};

					be1_in_fe1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&fe1_out_be1>;
					};
				};

				be1_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					be1_out_tcon0: endpoint@0 {
						reg = <0>;
1443
						remote-endpoint = <&tcon0_in_be1>;
1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500
					};

					be1_out_tcon1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&tcon1_in_be1>;
					};
				};
			};
		};

		be0: display-backend@1e60000 {
			compatible = "allwinner,sun7i-a20-display-backend";
			reg = <0x01e60000 0x10000>;
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
				 <&ccu CLK_DRAM_DE_BE0>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&ccu RST_DE_BE0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				be0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					be0_in_fe0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&fe0_out_be0>;
					};

					be0_in_fe1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&fe1_out_be0>;
					};
				};

				be0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					be0_out_tcon0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&tcon0_in_be0>;
					};

					be0_out_tcon1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&tcon1_in_be0>;
					};
				};
			};
		};
1501 1502
	};
};