ata_piix.c 46.6 KB
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/*
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 *    ata_piix.c - Intel PATA/SATA controllers
 *
 *    Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 *    		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *
 *	Copyright 2003-2005 Red Hat Inc
 *	Copyright 2003-2005 Jeff Garzik
 *
 *
 *	Copyright header from piix.c:
 *
 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
 *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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 *  Copyright (C) 2003 Red Hat Inc
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 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available at http://developer.intel.com/
 *
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 * Documentation
 *	Publically available from Intel web site. Errata documentation
 * is also publically available. As an aide to anyone hacking on this
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 * driver the list of errata that are relevant is below, going back to
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 * PIIX4. Older device documentation is now a bit tricky to find.
 *
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 * The chipsets all follow very much the same design. The original Triton
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 * series chipsets do _not_ support independant device timings, but this
 * is fixed in Triton II. With the odd mobile exception the chips then
 * change little except in gaining more modes until SATA arrives. This
 * driver supports only the chips with independant timing (that is those
 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
 * for the early chip drivers.
 *
 * Errata of note:
 *
 * Unfixable
 *	PIIX4    errata #9	- Only on ultra obscure hw
 *	ICH3	 errata #13     - Not observed to affect real hw
 *				  by Intel
 *
 * Things we must deal with
 *	PIIX4	errata #10	- BM IDE hang with non UDMA
 *				  (must stop/start dma to recover)
 *	440MX   errata #15	- As PIIX4 errata #10
 *	PIIX4	errata #15	- Must not read control registers
 * 				  during a PIO transfer
 *	440MX   errata #13	- As PIIX4 errata #15
 *	ICH2	errata #21	- DMA mode 0 doesn't work right
 *	ICH0/1  errata #55	- As ICH2 errata #21
 *	ICH2	spec c #9	- Extra operations needed to handle
 *				  drive hotswap [NOT YET SUPPORTED]
 *	ICH2    spec c #20	- IDE PRD must not cross a 64K boundary
 *				  and must be dword aligned
 *	ICH2    spec c #24	- UDMA mode 4,5 t85/86 should be 6ns not 3.3
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 *	ICH7	errata #16	- MWDMA1 timings are incorrect
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 *
 * Should have been BIOS fixed:
 *	450NX:	errata #19	- DMA hangs on old 450NX
 *	450NX:  errata #20	- DMA hangs on old 450NX
 *	450NX:  errata #25	- Corruption with DMA on old 450NX
 *	ICH3    errata #15      - IDE deadlock under high load
 *				  (BIOS must set dev 31 fn 0 bit 23)
 *	ICH3	errata #18	- Don't use native mode
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 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/gfp.h>
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#include <scsi/scsi_host.h>
#include <linux/libata.h>
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#include <linux/dmi.h>
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#define DRV_NAME	"ata_piix"
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#define DRV_VERSION	"2.13"
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enum {
	PIIX_IOCFG		= 0x54, /* IDE I/O configuration register */
	ICH5_PMR		= 0x90, /* port mapping register */
	ICH5_PCS		= 0x92,	/* port control and status */
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	PIIX_SIDPR_BAR		= 5,
	PIIX_SIDPR_LEN		= 16,
	PIIX_SIDPR_IDX		= 0,
	PIIX_SIDPR_DATA		= 4,
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	PIIX_FLAG_CHECKINTR	= (1 << 28), /* make sure PCI INTx enabled */
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	PIIX_FLAG_SIDPR		= (1 << 29), /* SATA idx/data pair regs */
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	PIIX_PATA_FLAGS		= ATA_FLAG_SLAVE_POSS,
	PIIX_SATA_FLAGS		= ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
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	PIIX_80C_PRI		= (1 << 5) | (1 << 4),
	PIIX_80C_SEC		= (1 << 7) | (1 << 6),

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	/* constants for mapping table */
	P0			= 0,  /* port 0 */
	P1			= 1,  /* port 1 */
	P2			= 2,  /* port 2 */
	P3			= 3,  /* port 3 */
	IDE			= -1, /* IDE */
	NA			= -2, /* not avaliable */
	RV			= -3, /* reserved */

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	PIIX_AHCI_DEVICE	= 6,
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	/* host->flags bits */
	PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
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};

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enum piix_controller_ids {
	/* controller IDs */
	piix_pata_mwdma,	/* PIIX3 MWDMA only */
	piix_pata_33,		/* PIIX4 at 33Mhz */
	ich_pata_33,		/* ICH up to UDMA 33 only */
	ich_pata_66,		/* ICH up to 66 Mhz */
	ich_pata_100,		/* ICH up to UDMA 100 */
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	ich_pata_100_nomwdma1,	/* ICH up to UDMA 100 but with no MWDMA1*/
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	ich5_sata,
	ich6_sata,
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	ich6m_sata,
	ich8_sata,
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	ich8_2port_sata,
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	ich8m_apple_sata,	/* locks up on second port enable */
	tolapai_sata,
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	piix_pata_vmw,			/* PIIX4 for VMware, spurious DMA_ERR */
};

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struct piix_map_db {
	const u32 mask;
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	const u16 port_enable;
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	const int map[][4];
};

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struct piix_host_priv {
	const int *map;
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	u32 saved_iocfg;
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	void __iomem *sidpr;
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};

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static int piix_init_one(struct pci_dev *pdev,
			 const struct pci_device_id *ent);
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static void piix_remove_one(struct pci_dev *pdev);
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static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
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static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
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static int ich_pata_cable_detect(struct ata_port *ap);
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static u8 piix_vmw_bmdma_status(struct ata_port *ap);
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static int piix_sidpr_scr_read(struct ata_link *link,
			       unsigned int reg, u32 *val);
static int piix_sidpr_scr_write(struct ata_link *link,
				unsigned int reg, u32 val);
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static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
			      unsigned hints);
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static bool piix_irq_check(struct ata_port *ap);
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#ifdef CONFIG_PM
static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
static int piix_pci_device_resume(struct pci_dev *pdev);
#endif
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static unsigned int in_module_init = 1;

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static const struct pci_device_id piix_pci_tbl[] = {
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	/* Intel PIIX3 for the 430HX etc */
	{ 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
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	/* VMware ICH4 */
	{ 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
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	/* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
	/* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
	{ 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
	/* Intel PIIX4 */
	{ 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
	/* Intel PIIX4 */
	{ 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
	/* Intel PIIX */
	{ 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
	/* Intel ICH (i810, i815, i840) UDMA 66*/
	{ 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
	/* Intel ICH0 : UDMA 33*/
	{ 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
	/* Intel ICH2M */
	{ 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
	{ 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/*  Intel ICH3M */
	{ 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/* Intel ICH3 (E7500/1) UDMA 100 */
	{ 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
	{ 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	{ 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/* Intel ICH5 */
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	{ 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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	/* C-ICH (i810E2) */
	{ 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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	/* ESB (855GME/875P + 6300ESB) UDMA 100  */
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	{ 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/* ICH6 (and 6) (i915) UDMA 100 */
	{ 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
	/* ICH7/7-R (i945, i975) UDMA 100*/
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	{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
	{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
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	/* ICH8 Mobile PATA Controller */
	{ 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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	/* SATA ports */
	
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	/* 82801EB (ICH5) */
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	{ 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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	/* 82801EB (ICH5) */
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	{ 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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	/* 6300ESB (ICH5 variant with broken PCS present bits) */
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	{ 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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	/* 6300ESB pretending RAID */
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	{ 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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	/* 82801FB/FW (ICH6/ICH6W) */
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	{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
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	/* 82801FR/FRW (ICH6R/ICH6RW) */
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	{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
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	/* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
	 * Attach iff the controller is in IDE mode. */
	{ 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
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	  PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
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	/* 82801GB/GR/GH (ICH7, identical to ICH6) */
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	{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
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	/* 2801GBM/GHM (ICH7M, identical to ICH6M) */
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	{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
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	/* Enterprise Southbridge 2 (631xESB/632xESB) */
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	{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
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	/* SATA Controller 1 IDE (ICH8) */
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	{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
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	/* SATA Controller 2 IDE (ICH8) */
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	{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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	/* Mobile SATA Controller IDE (ICH8M), Apple */
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	{ 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
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	{ 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
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	{ 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
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	/* Mobile SATA Controller IDE (ICH8M) */
	{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
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	/* SATA Controller IDE (ICH9) */
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	{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
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	/* SATA Controller IDE (ICH9) */
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	{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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	/* SATA Controller IDE (ICH9) */
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	{ 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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	/* SATA Controller IDE (ICH9M) */
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	{ 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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	/* SATA Controller IDE (ICH9M) */
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	{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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	/* SATA Controller IDE (ICH9M) */
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	{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
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	/* SATA Controller IDE (Tolapai) */
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	{ 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
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	/* SATA Controller IDE (ICH10) */
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	{ 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
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	/* SATA Controller IDE (ICH10) */
	{ 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
	/* SATA Controller IDE (ICH10) */
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	{ 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
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	/* SATA Controller IDE (ICH10) */
	{ 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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	/* SATA Controller IDE (PCH) */
	{ 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
	/* SATA Controller IDE (PCH) */
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	{ 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
	/* SATA Controller IDE (PCH) */
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	{ 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
	/* SATA Controller IDE (PCH) */
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	{ 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
	/* SATA Controller IDE (PCH) */
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	{ 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
	/* SATA Controller IDE (PCH) */
	{ 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
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	/* SATA Controller IDE (CPT) */
	{ 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
	/* SATA Controller IDE (CPT) */
	{ 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
	/* SATA Controller IDE (CPT) */
	{ 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
	/* SATA Controller IDE (CPT) */
	{ 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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	/* SATA Controller IDE (PBG) */
	{ 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
	/* SATA Controller IDE (PBG) */
	{ 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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	{ }	/* terminate list */
};

static struct pci_driver piix_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= piix_pci_tbl,
	.probe			= piix_init_one,
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	.remove			= piix_remove_one,
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#ifdef CONFIG_PM
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	.suspend		= piix_pci_device_suspend,
	.resume			= piix_pci_device_resume,
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#endif
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};

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static struct scsi_host_template piix_sht = {
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	ATA_BMDMA_SHT(DRV_NAME),
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};

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static struct ata_port_operations piix_sata_ops = {
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	.inherits		= &ata_bmdma32_port_ops,
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	.sff_irq_check		= piix_irq_check,
};

static struct ata_port_operations piix_pata_ops = {
	.inherits		= &piix_sata_ops,
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	.cable_detect		= ata_cable_40wire,
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	.set_piomode		= piix_set_piomode,
	.set_dmamode		= piix_set_dmamode,
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	.prereset		= piix_pata_prereset,
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};

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static struct ata_port_operations piix_vmw_ops = {
	.inherits		= &piix_pata_ops,
	.bmdma_status		= piix_vmw_bmdma_status,
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};

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static struct ata_port_operations ich_pata_ops = {
	.inherits		= &piix_pata_ops,
	.cable_detect		= ich_pata_cable_detect,
	.set_dmamode		= ich_set_dmamode,
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};

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static struct device_attribute *piix_sidpr_shost_attrs[] = {
	&dev_attr_link_power_management_policy,
	NULL
};

static struct scsi_host_template piix_sidpr_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
	.shost_attrs		= piix_sidpr_shost_attrs,
};

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static struct ata_port_operations piix_sidpr_sata_ops = {
	.inherits		= &piix_sata_ops,
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	.hardreset		= sata_std_hardreset,
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	.scr_read		= piix_sidpr_scr_read,
	.scr_write		= piix_sidpr_scr_write,
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	.set_lpm		= piix_sidpr_set_lpm,
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};

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static const struct piix_map_db ich5_map_db = {
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	.mask = 0x7,
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	.port_enable = 0x3,
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	.map = {
		/* PM   PS   SM   SS       MAP  */
		{  P0,  NA,  P1,  NA }, /* 000b */
		{  P1,  NA,  P0,  NA }, /* 001b */
		{  RV,  RV,  RV,  RV },
		{  RV,  RV,  RV,  RV },
		{  P0,  P1, IDE, IDE }, /* 100b */
		{  P1,  P0, IDE, IDE }, /* 101b */
		{ IDE, IDE,  P0,  P1 }, /* 110b */
		{ IDE, IDE,  P1,  P0 }, /* 111b */
	},
};

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static const struct piix_map_db ich6_map_db = {
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	.mask = 0x3,
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	.port_enable = 0xf,
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	.map = {
		/* PM   PS   SM   SS       MAP */
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		{  P0,  P2,  P1,  P3 }, /* 00b */
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		{ IDE, IDE,  P1,  P3 }, /* 01b */
		{  P0,  P2, IDE, IDE }, /* 10b */
		{  RV,  RV,  RV,  RV },
	},
};

398
static const struct piix_map_db ich6m_map_db = {
399
	.mask = 0x3,
400
	.port_enable = 0x5,
401 402

	/* Map 01b isn't specified in the doc but some notebooks use
403 404
	 * it anyway.  MAP 01b have been spotted on both ICH6M and
	 * ICH7M.
405 406 407
	 */
	.map = {
		/* PM   PS   SM   SS       MAP */
408
		{  P0,  P2,  NA,  NA }, /* 00b */
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		{ IDE, IDE,  P1,  P3 }, /* 01b */
		{  P0,  P2, IDE, IDE }, /* 10b */
		{  RV,  RV,  RV,  RV },
	},
};

415 416
static const struct piix_map_db ich8_map_db = {
	.mask = 0x3,
417
	.port_enable = 0xf,
418 419
	.map = {
		/* PM   PS   SM   SS       MAP */
420
		{  P0,  P2,  P1,  P3 }, /* 00b (hardwired when in AHCI) */
421
		{  RV,  RV,  RV,  RV },
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		{  P0,  P2, IDE, IDE }, /* 10b (IDE mode) */
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		{  RV,  RV,  RV,  RV },
	},
};

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static const struct piix_map_db ich8_2port_map_db = {
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	.mask = 0x3,
	.port_enable = 0x3,
	.map = {
		/* PM   PS   SM   SS       MAP */
		{  P0,  NA,  P1,  NA }, /* 00b */
		{  RV,  RV,  RV,  RV }, /* 01b */
		{  RV,  RV,  RV,  RV }, /* 10b */
		{  RV,  RV,  RV,  RV },
	},
437 438
};

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static const struct piix_map_db ich8m_apple_map_db = {
	.mask = 0x3,
	.port_enable = 0x1,
	.map = {
		/* PM   PS   SM   SS       MAP */
		{  P0,  NA,  NA,  NA }, /* 00b */
		{  RV,  RV,  RV,  RV },
		{  P0,  P2, IDE, IDE }, /* 10b */
		{  RV,  RV,  RV,  RV },
	},
};

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static const struct piix_map_db tolapai_map_db = {
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	.mask = 0x3,
	.port_enable = 0x3,
	.map = {
		/* PM   PS   SM   SS       MAP */
		{  P0,  NA,  P1,  NA }, /* 00b */
		{  RV,  RV,  RV,  RV }, /* 01b */
		{  RV,  RV,  RV,  RV }, /* 10b */
		{  RV,  RV,  RV,  RV },
	},
};

463 464 465
static const struct piix_map_db *piix_map_db_table[] = {
	[ich5_sata]		= &ich5_map_db,
	[ich6_sata]		= &ich6_map_db,
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	[ich6m_sata]		= &ich6m_map_db,
	[ich8_sata]		= &ich8_map_db,
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	[ich8_2port_sata]	= &ich8_2port_map_db,
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	[ich8m_apple_sata]	= &ich8m_apple_map_db,
	[tolapai_sata]		= &tolapai_map_db,
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};

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static struct ata_port_info piix_port_info[] = {
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	[piix_pata_mwdma] = 	/* PIIX3 MWDMA only */
	{
		.flags		= PIIX_PATA_FLAGS,
477 478
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
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		.port_ops	= &piix_pata_ops,
	},

482
	[piix_pata_33] =	/* PIIX4 at 33MHz */
483
	{
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		.flags		= PIIX_PATA_FLAGS,
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		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
		.udma_mask	= ATA_UDMA2,
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		.port_ops	= &piix_pata_ops,
	},

491
	[ich_pata_33] = 	/* ICH0 - ICH at 33Mhz*/
492
	{
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		.flags		= PIIX_PATA_FLAGS,
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		.pio_mask 	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok  */
		.udma_mask	= ATA_UDMA2,
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		.port_ops	= &ich_pata_ops,
	},
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	[ich_pata_66] = 	/* ICH controllers up to 66MHz */
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	{
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		.flags		= PIIX_PATA_FLAGS,
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		.pio_mask 	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
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		.udma_mask	= ATA_UDMA4,
		.port_ops	= &ich_pata_ops,
	},
508

509
	[ich_pata_100] =
510
	{
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		.flags		= PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
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		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA12_ONLY,
		.udma_mask	= ATA_UDMA5,
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		.port_ops	= &ich_pata_ops,
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	},

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	[ich_pata_100_nomwdma1] =
	{
		.flags		= PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2_ONLY,
		.udma_mask	= ATA_UDMA5,
		.port_ops	= &ich_pata_ops,
	},

527
	[ich5_sata] =
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	{
529
		.flags		= PIIX_SATA_FLAGS,
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		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
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		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &piix_sata_ops,
	},

536
	[ich6_sata] =
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	{
538
		.flags		= PIIX_SATA_FLAGS,
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		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
541
		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &piix_sata_ops,
	},

545
	[ich6m_sata] =
546
	{
547
		.flags		= PIIX_SATA_FLAGS,
548 549
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
550
		.udma_mask	= ATA_UDMA6,
551 552
		.port_ops	= &piix_sata_ops,
	},
553

554
	[ich8_sata] =
555
	{
556
		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
557 558
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
559
		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &piix_sata_ops,
	},
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	[ich8_2port_sata] =
564
	{
565
		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
566 567
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
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		.udma_mask	= ATA_UDMA6,
		.port_ops	= &piix_sata_ops,
	},
571

572
	[tolapai_sata] =
573
	{
574
		.flags		= PIIX_SATA_FLAGS,
575 576
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
577 578 579
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &piix_sata_ops,
	},
580

581
	[ich8m_apple_sata] =
582
	{
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		.flags		= PIIX_SATA_FLAGS,
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		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
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		.udma_mask	= ATA_UDMA6,
		.port_ops	= &piix_sata_ops,
	},

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	[piix_pata_vmw] =
	{
		.flags		= PIIX_PATA_FLAGS,
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		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
		.udma_mask	= ATA_UDMA2,
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		.port_ops	= &piix_vmw_ops,
	},

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};

static struct pci_bits piix_enable_bits[] = {
	{ 0x41U, 1U, 0x80UL, 0x80UL },	/* port 0 */
	{ 0x43U, 1U, 0x80UL, 0x80UL },	/* port 1 */
};

MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
MODULE_VERSION(DRV_VERSION);

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struct ich_laptop {
	u16 device;
	u16 subvendor;
	u16 subdevice;
};

/*
 *	List of laptops that use short cables rather than 80 wire
 */

static const struct ich_laptop ich_laptop[] = {
	/* devid, subvendor, subdev */
	{ 0x27DF, 0x0005, 0x0280 },	/* ICH7 on Acer 5602WLMi */
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	{ 0x27DF, 0x1025, 0x0102 },	/* ICH7 on Acer 5602aWLMi */
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	{ 0x27DF, 0x1025, 0x0110 },	/* ICH7 on Acer 3682WLMi */
627
	{ 0x27DF, 0x1028, 0x02b0 },	/* ICH7 on unknown Dell */
628
	{ 0x27DF, 0x1043, 0x1267 },	/* ICH7 on Asus W5F */
629
	{ 0x27DF, 0x103C, 0x30A1 },	/* ICH7 on HP Compaq nc2400 */
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	{ 0x27DF, 0x103C, 0x361a },	/* ICH7 on unknown HP  */
631
	{ 0x27DF, 0x1071, 0xD221 },	/* ICH7 on Hercules EC-900 */
632
	{ 0x27DF, 0x152D, 0x0778 },	/* ICH7 on unknown Intel */
633
	{ 0x24CA, 0x1025, 0x0061 },	/* ICH4 on ACER Aspire 2023WLMi */
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	{ 0x24CA, 0x1025, 0x003d },	/* ICH4 on ACER TM290 */
	{ 0x266F, 0x1025, 0x0066 },	/* ICH6 on ACER Aspire 1694WLMi */
636
	{ 0x2653, 0x1043, 0x82D8 },	/* ICH6M on Asus Eee 701 */
637
	{ 0x27df, 0x104d, 0x900e },	/* ICH7 on Sony TZ-90 */
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	/* end marker */
	{ 0, }
};

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/**
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 *	ich_pata_cable_detect - Probe host controller cable detect info
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 *	@ap: Port for which cable detect info is desired
 *
 *	Read 80c cable indicator from ATA PCI device's PCI config
 *	register.  This register is normally set by firmware (BIOS).
 *
 *	LOCKING:
 *	None (inherited from caller).
 */
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static int ich_pata_cable_detect(struct ata_port *ap)
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{
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	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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	struct piix_host_priv *hpriv = ap->host->private_data;
657
	const struct ich_laptop *lap = &ich_laptop[0];
658
	u8 mask;
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	/* Check for specials - Acer Aspire 5602WLMi */
	while (lap->device) {
		if (lap->device == pdev->device &&
		    lap->subvendor == pdev->subsystem_vendor &&
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		    lap->subdevice == pdev->subsystem_device)
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			return ATA_CBL_PATA40_SHORT;
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667 668 669
		lap++;
	}

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	/* check BIOS cable detect results */
671
	mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
672
	if ((hpriv->saved_iocfg & mask) == 0)
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		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
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}

/**
678
 *	piix_pata_prereset - prereset for PATA host controller
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 *	@link: Target link
680
 *	@deadline: deadline jiffies for the operation
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 *
682 683 684
 *	LOCKING:
 *	None (inherited from caller).
 */
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static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
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{
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	struct ata_port *ap = link->ap;
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	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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690 691
	if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
		return -ENOENT;
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	return ata_sff_prereset(link, deadline);
693 694
}

695 696
static DEFINE_SPINLOCK(piix_lock);

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/**
 *	piix_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: um
 *
 *	Set PIO mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

708
static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
711 712
	unsigned long flags;
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
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	unsigned int is_slave	= (adev->devno != 0);
714
	unsigned int master_port= ap->port_no ? 0x42 : 0x40;
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	unsigned int slave_port	= 0x44;
	u16 master_data;
	u8 slave_data;
718 719
	u8 udma_enable;
	int control = 0;
720

721 722 723 724
	/*
	 *	See Intel Document 298600-004 for the timing programing rules
	 *	for ICH controllers.
	 */
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	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

733 734 735 736 737
	if (pio >= 2)
		control |= 1;	/* TIME1 enable */
	if (ata_pio_need_iordy(adev))
		control |= 2;	/* IE enable */

738
	/* Intel specifies that the PPE functionality is for disk only */
739 740 741
	if (adev->class == ATA_DEV_ATA)
		control |= 4;	/* PPE enable */

742 743
	spin_lock_irqsave(&piix_lock, flags);

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	/* PIO configuration clears DTE unconditionally.  It will be
	 * programmed in set_dmamode which is guaranteed to be called
	 * after set_piomode if any DMA mode is available.
	 */
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	pci_read_config_word(dev, master_port, &master_data);
	if (is_slave) {
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		/* clear TIME1|IE1|PPE1|DTE1 */
		master_data &= 0xff0f;
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		/* Enable SITRE (separate slave timing register) */
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		master_data |= 0x4000;
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		/* enable PPE1, IE1 and TIME1 as needed */
		master_data |= (control << 4);
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		pci_read_config_byte(dev, slave_port, &slave_data);
757
		slave_data &= (ap->port_no ? 0x0f : 0xf0);
758
		/* Load the timing nibble for this slave */
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		slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
						<< (ap->port_no ? 4 : 0);
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	} else {
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		/* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
		master_data &= 0xccf0;
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		/* Enable PPE, IE and TIME as appropriate */
		master_data |= control;
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		/* load ISP and RCT */
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		master_data |=
			(timings[pio][0] << 12) |
			(timings[pio][1] << 8);
	}
	pci_write_config_word(dev, master_port, master_data);
	if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
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	/* Ensure the UDMA bit is off - it will be turned back on if
	   UDMA is selected */
777

778 779 780 781 782
	if (ap->udma_mask) {
		pci_read_config_byte(dev, 0x48, &udma_enable);
		udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
		pci_write_config_byte(dev, 0x48, udma_enable);
	}
783 784

	spin_unlock_irqrestore(&piix_lock, flags);
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}

/**
788
 *	do_pata_set_dmamode - Initialize host controller PATA PIO timings
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 *	@ap: Port whose timings we are configuring
790
 *	@adev: Drive in question
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 *	@isich: set if the chip is an ICH device
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 *
 *	Set UDMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

799
static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
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{
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	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
802
	unsigned long flags;
803 804 805 806
	u8 master_port		= ap->port_no ? 0x42 : 0x40;
	u16 master_data;
	u8 speed		= adev->dma_mode;
	int devid		= adev->devno + 2 * ap->port_no;
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	u8 udma_enable		= 0;
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	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

816 817
	spin_lock_irqsave(&piix_lock, flags);

818
	pci_read_config_word(dev, master_port, &master_data);
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	if (ap->udma_mask)
		pci_read_config_byte(dev, 0x48, &udma_enable);
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	if (speed >= XFER_UDMA_0) {
823 824 825 826
		unsigned int udma = adev->dma_mode - XFER_UDMA_0;
		u16 udma_timing;
		u16 ideconf;
		int u_clock, u_speed;
827

828
		/*
829
		 * UDMA is handled by a combination of clock switching and
830 831
		 * selection of dividers
		 *
832
		 * Handy rule: Odd modes are UDMATIMx 01, even are 02
833
		 *	       except UDMA0 which is 00
834 835 836 837 838 839 840 841
		 */
		u_speed = min(2 - (udma & 1), udma);
		if (udma == 5)
			u_clock = 0x1000;	/* 100Mhz */
		else if (udma > 2)
			u_clock = 1;		/* 66Mhz */
		else
			u_clock = 0;		/* 33Mhz */
842

843
		udma_enable |= (1 << devid);
844

845 846 847 848 849 850
		/* Load the CT/RP selection */
		pci_read_config_word(dev, 0x4A, &udma_timing);
		udma_timing &= ~(3 << (4 * devid));
		udma_timing |= u_speed << (4 * devid);
		pci_write_config_word(dev, 0x4A, udma_timing);

851
		if (isich) {
852 853 854 855 856 857 858
			/* Select a 33/66/100Mhz clock */
			pci_read_config_word(dev, 0x54, &ideconf);
			ideconf &= ~(0x1001 << devid);
			ideconf |= u_clock << devid;
			/* For ICH or later we should set bit 10 for better
			   performance (WR_PingPong_En) */
			pci_write_config_word(dev, 0x54, ideconf);
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		}
	} else {
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		/*
		 * MWDMA is driven by the PIO timings. We must also enable
		 * IORDY unconditionally along with TIME1. PPE has already
		 * been set when the PIO timing was set.
		 */
		unsigned int mwdma	= adev->dma_mode - XFER_MW_DMA_0;
		unsigned int control;
		u8 slave_data;
		const unsigned int needed_pio[3] = {
			XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
		};
		int pio = needed_pio[mwdma] - XFER_PIO_0;
873

874
		control = 3;	/* IORDY|TIME1 */
875

876 877
		/* If the drive MWDMA is faster than it can do PIO then
		   we must force PIO into PIO0 */
878

879 880 881 882 883 884 885 886
		if (adev->pio_mode < needed_pio[mwdma])
			/* Enable DMA timing only */
			control |= 8;	/* PIO cycles in PIO0 */

		if (adev->devno) {	/* Slave */
			master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
			master_data |= control << 4;
			pci_read_config_byte(dev, 0x44, &slave_data);
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			slave_data &= (ap->port_no ? 0x0f : 0xf0);
888 889 890 891
			/* Load the matching timing */
			slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
			pci_write_config_byte(dev, 0x44, slave_data);
		} else { 	/* Master */
892
			master_data &= 0xCCF4;	/* Mask out IORDY|TIME1|DMAONLY
893 894 895 896 897 898
						   and master timing bits */
			master_data |= control;
			master_data |=
				(timings[pio][0] << 12) |
				(timings[pio][1] << 8);
		}
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900
		if (ap->udma_mask)
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			udma_enable &= ~(1 << devid);
902 903

		pci_write_config_word(dev, master_port, master_data);
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	}
905 906 907
	/* Don't scribble on 0x48 if the controller does not support UDMA */
	if (ap->udma_mask)
		pci_write_config_byte(dev, 0x48, udma_enable);
908 909

	spin_unlock_irqrestore(&piix_lock, flags);
910 911 912 913 914 915 916 917 918 919 920 921 922
}

/**
 *	piix_set_dmamode - Initialize host controller PATA DMA timings
 *	@ap: Port whose timings we are configuring
 *	@adev: um
 *
 *	Set MW/UDMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

923
static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
924 925 926 927 928 929 930 931 932 933 934 935 936 937 938
{
	do_pata_set_dmamode(ap, adev, 0);
}

/**
 *	ich_set_dmamode - Initialize host controller PATA DMA timings
 *	@ap: Port whose timings we are configuring
 *	@adev: um
 *
 *	Set MW/UDMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

939
static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
940 941
{
	do_pata_set_dmamode(ap, adev, 1);
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}

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/*
 * Serial ATA Index/Data Pair Superset Registers access
 *
 * Beginning from ICH8, there's a sane way to access SCRs using index
948 949 950
 * and data register pair located at BAR5 which means that we have
 * separate SCRs for master and slave.  This is handled using libata
 * slave_link facility.
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 */
static const int piix_sidx_map[] = {
	[SCR_STATUS]	= 0,
	[SCR_ERROR]	= 2,
	[SCR_CONTROL]	= 1,
};

958
static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
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{
960
	struct ata_port *ap = link->ap;
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	struct piix_host_priv *hpriv = ap->host->private_data;

963
	iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
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964 965 966
		  hpriv->sidpr + PIIX_SIDPR_IDX);
}

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static int piix_sidpr_scr_read(struct ata_link *link,
			       unsigned int reg, u32 *val)
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{
970
	struct piix_host_priv *hpriv = link->ap->host->private_data;
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	if (reg >= ARRAY_SIZE(piix_sidx_map))
		return -EINVAL;

975 976
	piix_sidpr_sel(link, reg);
	*val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
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	return 0;
}

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static int piix_sidpr_scr_write(struct ata_link *link,
				unsigned int reg, u32 val)
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{
983
	struct piix_host_priv *hpriv = link->ap->host->private_data;
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985 986 987
	if (reg >= ARRAY_SIZE(piix_sidx_map))
		return -EINVAL;

988 989
	piix_sidpr_sel(link, reg);
	iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
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	return 0;
}

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static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
			      unsigned hints)
{
	return sata_link_scr_lpm(link, policy, false);
}

999 1000 1001 1002 1003 1004 1005 1006
static bool piix_irq_check(struct ata_port *ap)
{
	if (unlikely(!ap->ioaddr.bmdma_addr))
		return false;

	return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
}

1007
#ifdef CONFIG_PM
1008 1009
static int piix_broken_suspend(void)
{
1010
	static const struct dmi_system_id sysids[] = {
1011 1012 1013 1014 1015 1016 1017
		{
			.ident = "TECRA M3",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
			},
		},
1018 1019 1020 1021 1022 1023 1024
		{
			.ident = "TECRA M3",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
			},
		},
1025 1026 1027 1028 1029 1030 1031
		{
			.ident = "TECRA M4",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
			},
		},
1032 1033 1034 1035 1036 1037 1038
		{
			.ident = "TECRA M4",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
			},
		},
1039 1040 1041 1042 1043 1044
		{
			.ident = "TECRA M5",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
			},
1045
		},
1046 1047 1048 1049 1050 1051 1052
		{
			.ident = "TECRA M6",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
			},
		},
1053 1054 1055 1056 1057 1058 1059
		{
			.ident = "TECRA M7",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
			},
		},
1060 1061 1062 1063 1064 1065 1066
		{
			.ident = "TECRA A8",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
			},
		},
1067 1068 1069 1070 1071 1072 1073
		{
			.ident = "Satellite R20",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
			},
		},
1074 1075 1076 1077 1078 1079 1080
		{
			.ident = "Satellite R25",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
			},
		},
1081 1082 1083 1084 1085 1086 1087
		{
			.ident = "Satellite U200",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
			},
		},
1088 1089 1090 1091 1092 1093 1094
		{
			.ident = "Satellite U200",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
			},
		},
1095 1096 1097 1098 1099 1100 1101
		{
			.ident = "Satellite Pro U200",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
			},
		},
1102 1103 1104 1105 1106 1107
		{
			.ident = "Satellite U205",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
			},
1108
		},
1109 1110 1111 1112 1113 1114 1115
		{
			.ident = "SATELLITE U205",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
			},
		},
1116 1117 1118 1119 1120 1121
		{
			.ident = "Portege M500",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
				DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
			},
1122
		},
1123 1124 1125 1126 1127 1128 1129
		{
			.ident = "VGN-BX297XP",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
				DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
			},
		},
1130 1131

		{ }	/* terminate list */
1132
	};
1133 1134 1135 1136
	static const char *oemstrs[] = {
		"Tecra M3,",
	};
	int i;
1137 1138 1139 1140

	if (dmi_check_system(sysids))
		return 1;

1141 1142 1143 1144
	for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
		if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
			return 1;

1145 1146 1147 1148 1149 1150
	/* TECRA M4 sometimes forgets its identify and reports bogus
	 * DMI information.  As the bogus information is a bit
	 * generic, match as many entries as possible.  This manual
	 * matching is necessary because dmi_system_id.matches is
	 * limited to four entries.
	 */
1151 1152 1153 1154 1155 1156 1157
	if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
	    dmi_match(DMI_PRODUCT_NAME, "000000") &&
	    dmi_match(DMI_PRODUCT_VERSION, "000000") &&
	    dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
	    dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
	    dmi_match(DMI_BOARD_NAME, "Portable PC") &&
	    dmi_match(DMI_BOARD_VERSION, "Version A0"))
1158 1159
		return 1;

1160 1161
	return 0;
}
1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177

static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	unsigned long flags;
	int rc = 0;

	rc = ata_host_suspend(host, mesg);
	if (rc)
		return rc;

	/* Some braindamaged ACPI suspend implementations expect the
	 * controller to be awake on entry; otherwise, it burns cpu
	 * cycles and power trying to do something to the sleeping
	 * beauty.
	 */
1178
	if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212
		pci_save_state(pdev);

		/* mark its power state as "unknown", since we don't
		 * know if e.g. the BIOS will change its device state
		 * when we suspend.
		 */
		if (pdev->current_state == PCI_D0)
			pdev->current_state = PCI_UNKNOWN;

		/* tell resume that it's waking up from broken suspend */
		spin_lock_irqsave(&host->lock, flags);
		host->flags |= PIIX_HOST_BROKEN_SUSPEND;
		spin_unlock_irqrestore(&host->lock, flags);
	} else
		ata_pci_device_do_suspend(pdev, mesg);

	return 0;
}

static int piix_pci_device_resume(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	unsigned long flags;
	int rc;

	if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
		spin_lock_irqsave(&host->lock, flags);
		host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
		spin_unlock_irqrestore(&host->lock, flags);

		pci_set_power_state(pdev, PCI_D0);
		pci_restore_state(pdev);

		/* PCI device wasn't disabled during suspend.  Use
1213 1214
		 * pci_reenable_device() to avoid affecting the enable
		 * count.
1215
		 */
1216
		rc = pci_reenable_device(pdev);
1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229
		if (rc)
			dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
				   "device after resume (%d)\n", rc);
	} else
		rc = ata_pci_device_do_resume(pdev);

	if (rc == 0)
		ata_host_resume(host);

	return rc;
}
#endif

1230 1231 1232 1233 1234
static u8 piix_vmw_bmdma_status(struct ata_port *ap)
{
	return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
}

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#define AHCI_PCI_BAR 5
#define AHCI_GLOBAL_CTL 0x04
#define AHCI_ENABLE (1 << 31)
static int piix_disable_ahci(struct pci_dev *pdev)
{
1240
	void __iomem *mmio;
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1241 1242 1243 1244 1245 1246 1247
	u32 tmp;
	int rc = 0;

	/* BUG: pci_enable_device has not yet been called.  This
	 * works because this device is usually set up by BIOS.
	 */

1248 1249
	if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
	    !pci_resource_len(pdev, AHCI_PCI_BAR))
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1250
		return 0;
1251

1252
	mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
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1253 1254
	if (!mmio)
		return -ENOMEM;
1255

1256
	tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
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1257 1258
	if (tmp & AHCI_ENABLE) {
		tmp &= ~AHCI_ENABLE;
1259
		iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
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1260

1261
		tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
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1262 1263 1264
		if (tmp & AHCI_ENABLE)
			rc = -EIO;
	}
1265

1266
	pci_iounmap(pdev, mmio);
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1267 1268 1269
	return rc;
}

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/**
 *	piix_check_450nx_errata	-	Check for problem 450NX setup
1272
 *	@ata_dev: the PCI device to check
1273
 *
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1274 1275 1276 1277 1278 1279 1280 1281 1282
 *	Check for the present of 450NX errata #19 and errata #25. If
 *	they are found return an error code so we can turn off DMA
 */

static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
{
	struct pci_dev *pdev = NULL;
	u16 cfg;
	int no_piix_dma = 0;
1283

1284
	while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
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1285 1286 1287 1288
		/* Look for 450NX PXB. Check for problem configurations
		   A PCI quirk checks bit 6 already */
		pci_read_config_word(pdev, 0x41, &cfg);
		/* Only on the original revision: IDE DMA can hang */
1289
		if (pdev->revision == 0x00)
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1290 1291
			no_piix_dma = 1;
		/* On all revisions below 5 PXB bus lock must be disabled for IDE */
1292
		else if (cfg & (1<<14) && pdev->revision < 5)
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1293 1294
			no_piix_dma = 2;
	}
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1295
	if (no_piix_dma)
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1296
		dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
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1297
	if (no_piix_dma == 2)
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1298 1299
		dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
	return no_piix_dma;
1300
}
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1302
static void __devinit piix_init_pcs(struct ata_host *host,
1303 1304
				    const struct piix_map_db *map_db)
{
1305
	struct pci_dev *pdev = to_pci_dev(host->dev);
1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318
	u16 pcs, new_pcs;

	pci_read_config_word(pdev, ICH5_PCS, &pcs);

	new_pcs = pcs | map_db->port_enable;

	if (new_pcs != pcs) {
		DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
		pci_write_config_word(pdev, ICH5_PCS, new_pcs);
		msleep(150);
	}
}

1319 1320 1321
static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
					       struct ata_port_info *pinfo,
					       const struct piix_map_db *map_db)
1322
{
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	const int *map;
1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344
	int i, invalid_map = 0;
	u8 map_value;

	pci_read_config_byte(pdev, ICH5_PMR, &map_value);

	map = map_db->map[map_value & map_db->mask];

	dev_printk(KERN_INFO, &pdev->dev, "MAP [");
	for (i = 0; i < 4; i++) {
		switch (map[i]) {
		case RV:
			invalid_map = 1;
			printk(" XX");
			break;

		case NA:
			printk(" --");
			break;

		case IDE:
			WARN_ON((i & 1) || map[i + 1] != IDE);
1345
			pinfo[i / 2] = piix_port_info[ich_pata_100];
1346 1347 1348 1349 1350 1351 1352
			i++;
			printk(" IDE IDE");
			break;

		default:
			printk(" P%d", map[i]);
			if (i & 1)
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				pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1354 1355 1356 1357 1358 1359 1360 1361 1362
			break;
		}
	}
	printk(" ]\n");

	if (invalid_map)
		dev_printk(KERN_ERR, &pdev->dev,
			   "invalid MAP value %u\n", map_value);

1363
	return map;
1364 1365
}

1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398
static bool piix_no_sidpr(struct ata_host *host)
{
	struct pci_dev *pdev = to_pci_dev(host->dev);

	/*
	 * Samsung DB-P70 only has three ATA ports exposed and
	 * curiously the unconnected first port reports link online
	 * while not responding to SRST protocol causing excessive
	 * detection delay.
	 *
	 * Unfortunately, the system doesn't carry enough DMI
	 * information to identify the machine but does have subsystem
	 * vendor and device set.  As it's unclear whether the
	 * subsystem vendor/device is used only for this specific
	 * board, the port can't be disabled solely with the
	 * information; however, turning off SIDPR access works around
	 * the problem.  Turn it off.
	 *
	 * This problem is reported in bnc#441240.
	 *
	 * https://bugzilla.novell.com/show_bug.cgi?id=441420
	 */
	if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
	    pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
	    pdev->subsystem_device == 0xb049) {
		dev_printk(KERN_WARNING, host->dev,
			   "Samsung DB-P70 detected, disabling SIDPR\n");
		return true;
	}

	return false;
}

1399
static int __devinit piix_init_sidpr(struct ata_host *host)
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{
	struct pci_dev *pdev = to_pci_dev(host->dev);
	struct piix_host_priv *hpriv = host->private_data;
1403
	struct ata_link *link0 = &host->ports[0]->link;
1404
	u32 scontrol;
1405
	int i, rc;
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	/* check for availability */
	for (i = 0; i < 4; i++)
		if (hpriv->map[i] == IDE)
1410
			return 0;
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1412 1413 1414 1415
	/* is it blacklisted? */
	if (piix_no_sidpr(host))
		return 0;

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	if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1417
		return 0;
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	if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
	    pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
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		return 0;
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	if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
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		return 0;
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	hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1427 1428 1429 1430 1431

	/* SCR access via SIDPR doesn't work on some configurations.
	 * Give it a test drive by inhibiting power save modes which
	 * we'll do anyway.
	 */
1432
	piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1433 1434 1435 1436 1437 1438 1439

	/* if IPM is already 3, SCR access is probably working.  Don't
	 * un-inhibit power save modes as BIOS might have inhibited
	 * them for a reason.
	 */
	if ((scontrol & 0xf00) != 0x300) {
		scontrol |= 0x300;
1440 1441
		piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
		piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1442 1443 1444 1445

		if ((scontrol & 0xf00) != 0x300) {
			dev_printk(KERN_INFO, host->dev, "SCR access via "
				   "SIDPR is available but doesn't work\n");
1446
			return 0;
1447 1448 1449
		}
	}

1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463
	/* okay, SCRs available, set ops and ask libata for slave_link */
	for (i = 0; i < 2; i++) {
		struct ata_port *ap = host->ports[i];

		ap->ops = &piix_sidpr_sata_ops;

		if (ap->flags & ATA_FLAG_SLAVE_POSS) {
			rc = ata_slave_link_init(ap);
			if (rc)
				return rc;
		}
	}

	return 0;
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}

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static void piix_iocfg_bit18_quirk(struct ata_host *host)
1467
{
1468
	static const struct dmi_system_id sysids[] = {
1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479
		{
			/* Clevo M570U sets IOCFG bit 18 if the cdrom
			 * isn't used to boot the system which
			 * disables the channel.
			 */
			.ident = "M570U",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
				DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
			},
		},
1480 1481

		{ }	/* terminate list */
1482
	};
1483 1484
	struct pci_dev *pdev = to_pci_dev(host->dev);
	struct piix_host_priv *hpriv = host->private_data;
1485 1486 1487 1488 1489 1490 1491 1492

	if (!dmi_check_system(sysids))
		return;

	/* The datasheet says that bit 18 is NOOP but certain systems
	 * seem to use it to disable a channel.  Clear the bit on the
	 * affected systems.
	 */
1493
	if (hpriv->saved_iocfg & (1 << 18)) {
1494 1495
		dev_printk(KERN_INFO, &pdev->dev,
			   "applying IOCFG bit18 quirk\n");
1496 1497
		pci_write_config_dword(pdev, PIIX_IOCFG,
				       hpriv->saved_iocfg & ~(1 << 18));
1498 1499 1500
	}
}

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static bool piix_broken_system_poweroff(struct pci_dev *pdev)
{
	static const struct dmi_system_id broken_systems[] = {
		{
			.ident = "HP Compaq 2510p",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
				DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
			},
			/* PCI slot number of the controller */
			.driver_data = (void *)0x1FUL,
		},
1513 1514 1515 1516 1517 1518 1519 1520 1521
		{
			.ident = "HP Compaq nc6000",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
				DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
			},
			/* PCI slot number of the controller */
			.driver_data = (void *)0x1FUL,
		},
1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535

		{ }	/* terminate list */
	};
	const struct dmi_system_id *dmi = dmi_first_match(broken_systems);

	if (dmi) {
		unsigned long slot = (unsigned long)dmi->driver_data;
		/* apply the quirk only to on-board controllers */
		return slot == PCI_SLOT(pdev->devfn);
	}

	return false;
}

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/**
 *	piix_init_one - Register PIIX ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in piix_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.  We probe for combined mode (sigh),
 *	and then hand over control to libata, for it to do the rest.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

1551 1552
static int __devinit piix_init_one(struct pci_dev *pdev,
				   const struct pci_device_id *ent)
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{
	static int printed_version;
1555
	struct device *dev = &pdev->dev;
1556
	struct ata_port_info port_info[2];
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	const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
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	struct scsi_host_template *sht = &piix_sht;
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	unsigned long port_flags;
1560 1561 1562
	struct ata_host *host;
	struct piix_host_priv *hpriv;
	int rc;
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	if (!printed_version++)
1565 1566
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "version " DRV_VERSION "\n");
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1568 1569
	/* no hotplugging support for later devices (FIXME) */
	if (!in_module_init && ent->driver_data >= ich5_sata)
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		return -ENODEV;

1572 1573 1574 1575 1576 1577 1578 1579
	if (piix_broken_system_poweroff(pdev)) {
		piix_port_info[ent->driver_data].flags |=
				ATA_FLAG_NO_POWEROFF_SPINDOWN |
					ATA_FLAG_NO_HIBERNATE_SPINDOWN;
		dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
				"on poweroff and hibernation\n");
	}

1580 1581 1582 1583 1584 1585 1586 1587 1588 1589
	port_info[0] = piix_port_info[ent->driver_data];
	port_info[1] = piix_port_info[ent->driver_data];

	port_flags = port_info[0].flags;

	/* enable device and prepare host */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

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	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
	if (!hpriv)
		return -ENOMEM;

	/* Save IOCFG, this will be used for cable detection, quirk
	 * detection and restoration on detach.  This is necessary
	 * because some ACPI implementations mess up cable related
	 * bits on _STM.  Reported on kernel bz#11879.
	 */
	pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);

1601 1602 1603 1604 1605
	/* ICH6R may be driven by either ata_piix or ahci driver
	 * regardless of BIOS configuration.  Make sure AHCI mode is
	 * off.
	 */
	if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1606
		rc = piix_disable_ahci(pdev);
1607 1608 1609 1610
		if (rc)
			return rc;
	}

1611 1612 1613 1614
	/* SATA map init can change port_info, do it before prepping host */
	if (port_flags & ATA_FLAG_SATA)
		hpriv->map = piix_init_sata_map(pdev, port_info,
					piix_map_db_table[ent->driver_data]);
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	rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1617 1618 1619
	if (rc)
		return rc;
	host->private_data = hpriv;
1620

1621
	/* initialize controller */
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	if (port_flags & ATA_FLAG_SATA) {
1623
		piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1624 1625 1626
		rc = piix_init_sidpr(host);
		if (rc)
			return rc;
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		if (host->ports[0]->ops == &piix_sidpr_sata_ops)
			sht = &piix_sidpr_sht;
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	}
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1631
	/* apply IOCFG bit18 quirk */
1632
	piix_iocfg_bit18_quirk(host);
1633

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	/* On ICH5, some BIOSen disable the interrupt using the
	 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
	 * On ICH6, this bit has the same effect, but only when
	 * MSI is disabled (and it is disabled, as we don't use
	 * message-signalled interrupts currently).
	 */
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	if (port_flags & PIIX_FLAG_CHECKINTR)
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		pci_intx(pdev, 1);
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	if (piix_check_450nx_errata(pdev)) {
		/* This writes into the master table but it does not
		   really matter for this errata as we will apply it to
		   all the PIIX devices on the board */
1647 1648 1649 1650
		host->ports[0]->mwdma_mask = 0;
		host->ports[0]->udma_mask = 0;
		host->ports[1]->mwdma_mask = 0;
		host->ports[1]->udma_mask = 0;
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	}
1652
	host->flags |= ATA_HOST_PARALLEL_SCAN;
1653 1654

	pci_set_master(pdev);
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	return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
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}

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static void piix_remove_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	struct piix_host_priv *hpriv = host->private_data;

	pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);

	ata_pci_remove_one(pdev);
}

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static int __init piix_init(void)
{
	int rc;

1672 1673
	DPRINTK("pci_register_driver\n");
	rc = pci_register_driver(&piix_pci_driver);
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	if (rc)
		return rc;

	in_module_init = 0;

	DPRINTK("done\n");
	return 0;
}

static void __exit piix_exit(void)
{
	pci_unregister_driver(&piix_pci_driver);
}

module_init(piix_init);
module_exit(piix_exit);