bnx2.c 189.5 KB
Newer Older
1 2
/* bnx2.c: Broadcom NX2 network driver.
 *
M
Michael Chan 已提交
3
 * Copyright (c) 2004-2008 Broadcom Corporation
4 5 6 7 8 9 10 11
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation.
 *
 * Written by: Michael Chan  (mchan@broadcom.com)
 */

M
Michael Chan 已提交
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

#include <linux/module.h>
#include <linux/moduleparam.h>

#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/dma-mapping.h>
J
Jiri Slaby 已提交
29
#include <linux/bitops.h>
M
Michael Chan 已提交
30 31 32 33
#include <asm/io.h>
#include <asm/irq.h>
#include <linux/delay.h>
#include <asm/byteorder.h>
M
Michael Chan 已提交
34
#include <asm/page.h>
M
Michael Chan 已提交
35 36 37 38 39 40 41 42
#include <linux/time.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#ifdef NETIF_F_HW_VLAN_TX
#include <linux/if_vlan.h>
#define BCM_VLAN 1
#endif
#include <net/ip.h>
43
#include <net/tcp.h>
M
Michael Chan 已提交
44 45 46 47
#include <net/checksum.h>
#include <linux/workqueue.h>
#include <linux/crc32.h>
#include <linux/prefetch.h>
48
#include <linux/cache.h>
49
#include <linux/zlib.h>
M
Michael Chan 已提交
50

51 52
#include "bnx2.h"
#include "bnx2_fw.h"
M
Michael Chan 已提交
53
#include "bnx2_fw2.h"
54

55
#define FW_BUF_SIZE		0x10000
D
Denys Vlasenko 已提交
56

57 58
#define DRV_MODULE_NAME		"bnx2"
#define PFX DRV_MODULE_NAME	": "
59 60
#define DRV_MODULE_VERSION	"1.7.7"
#define DRV_MODULE_RELDATE	"June 17, 2008"
61 62 63 64 65 66

#define RUN_AT(x) (jiffies + (x))

/* Time in jiffies before concluding the transmitter is hung. */
#define TX_TIMEOUT  (5*HZ)

A
Andrew Morton 已提交
67
static char version[] __devinitdata =
68 69 70
	"Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";

MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
71
MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709 Driver");
72 73 74 75 76 77 78 79 80 81 82 83 84 85
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_MODULE_VERSION);

static int disable_msi = 0;

module_param(disable_msi, int, 0);
MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");

typedef enum {
	BCM5706 = 0,
	NC370T,
	NC370I,
	BCM5706S,
	NC370F,
M
Michael Chan 已提交
86 87
	BCM5708,
	BCM5708S,
M
Michael Chan 已提交
88
	BCM5709,
89
	BCM5709S,
M
Michael Chan 已提交
90
	BCM5716,
91 92 93
} board_t;

/* indexed by board_t, above */
A
Andrew Morton 已提交
94
static struct {
95 96 97 98 99 100 101
	char *name;
} board_info[] __devinitdata = {
	{ "Broadcom NetXtreme II BCM5706 1000Base-T" },
	{ "HP NC370T Multifunction Gigabit Server Adapter" },
	{ "HP NC370i Multifunction Gigabit Server Adapter" },
	{ "Broadcom NetXtreme II BCM5706 1000Base-SX" },
	{ "HP NC370F Multifunction Gigabit Server Adapter" },
M
Michael Chan 已提交
102 103
	{ "Broadcom NetXtreme II BCM5708 1000Base-T" },
	{ "Broadcom NetXtreme II BCM5708 1000Base-SX" },
M
Michael Chan 已提交
104
	{ "Broadcom NetXtreme II BCM5709 1000Base-T" },
105
	{ "Broadcom NetXtreme II BCM5709 1000Base-SX" },
M
Michael Chan 已提交
106
	{ "Broadcom NetXtreme II BCM5716 1000Base-T" },
107 108
	};

M
Michael Chan 已提交
109
static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
110 111 112 113 114 115
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
	  PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
	  PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
M
Michael Chan 已提交
116 117
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
118 119 120 121
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
	  PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
M
Michael Chan 已提交
122 123
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
M
Michael Chan 已提交
124 125
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
126 127
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
M
Michael Chan 已提交
128 129
	{ PCI_VENDOR_ID_BROADCOM, 0x163b,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
130 131 132 133 134
	{ 0, }
};

static struct flash_spec flash_table[] =
{
M
Michael Chan 已提交
135 136
#define BUFFERED_FLAGS		(BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
#define NONBUFFERED_FLAGS	(BNX2_NV_WREN)
137
	/* Slow EEPROM */
138
	{0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
M
Michael Chan 已提交
139
	 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
140 141
	 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
	 "EEPROM - slow"},
142 143
	/* Expansion entry 0001 */
	{0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
M
Michael Chan 已提交
144
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
145 146
	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 0001"},
147 148
	/* Saifun SA25F010 (non-buffered flash) */
	/* strap, cfg1, & write1 need updates */
149
	{0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
M
Michael Chan 已提交
150
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
151 152 153 154
	 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
	 "Non-buffered flash (128kB)"},
	/* Saifun SA25F020 (non-buffered flash) */
	/* strap, cfg1, & write1 need updates */
155
	{0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
M
Michael Chan 已提交
156
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
157 158
	 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
	 "Non-buffered flash (256kB)"},
159 160
	/* Expansion entry 0100 */
	{0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
M
Michael Chan 已提交
161
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
162 163 164
	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 0100"},
	/* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
165
	{0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
M
Michael Chan 已提交
166
	 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
167 168 169 170
	 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
	 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
	/* Entry 0110: ST M45PE20 (non-buffered flash)*/
	{0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
M
Michael Chan 已提交
171
	 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
172 173 174 175 176
	 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
	 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
	/* Saifun SA25F005 (non-buffered flash) */
	/* strap, cfg1, & write1 need updates */
	{0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
M
Michael Chan 已提交
177
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
178 179 180 181
	 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
	 "Non-buffered flash (64kB)"},
	/* Fast EEPROM */
	{0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
M
Michael Chan 已提交
182
	 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
183 184 185 186
	 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
	 "EEPROM - fast"},
	/* Expansion entry 1001 */
	{0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
M
Michael Chan 已提交
187
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
188 189 190 191
	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1001"},
	/* Expansion entry 1010 */
	{0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
M
Michael Chan 已提交
192
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
193 194 195 196
	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1010"},
	/* ATMEL AT45DB011B (buffered flash) */
	{0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
M
Michael Chan 已提交
197
	 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
198 199 200 201
	 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
	 "Buffered flash (128kB)"},
	/* Expansion entry 1100 */
	{0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
M
Michael Chan 已提交
202
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
203 204 205 206
	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1100"},
	/* Expansion entry 1101 */
	{0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
M
Michael Chan 已提交
207
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
208 209 210 211
	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1101"},
	/* Ateml Expansion entry 1110 */
	{0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
M
Michael Chan 已提交
212
	 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
213 214 215 216
	 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1110 (Atmel)"},
	/* ATMEL AT45DB021B (buffered flash) */
	{0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
M
Michael Chan 已提交
217
	 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
218 219
	 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
	 "Buffered flash (256kB)"},
220 221
};

M
Michael Chan 已提交
222 223 224 225 226 227 228 229 230
static struct flash_spec flash_5709 = {
	.flags		= BNX2_NV_BUFFERED,
	.page_bits	= BCM5709_FLASH_PAGE_BITS,
	.page_size	= BCM5709_FLASH_PAGE_SIZE,
	.addr_mask	= BCM5709_FLASH_BYTE_ADDR_MASK,
	.total_size	= BUFFERED_FLASH_TOTAL_SIZE*2,
	.name		= "5709 Buffered flash (256kB)",
};

231 232
MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);

233
static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
M
Michael Chan 已提交
234
{
M
Michael Chan 已提交
235
	u32 diff;
M
Michael Chan 已提交
236

M
Michael Chan 已提交
237
	smp_mb();
M
Michael Chan 已提交
238 239 240 241

	/* The ring uses 256 indices for 255 entries, one of them
	 * needs to be skipped.
	 */
242
	diff = txr->tx_prod - txr->tx_cons;
M
Michael Chan 已提交
243 244 245 246 247
	if (unlikely(diff >= TX_DESC_CNT)) {
		diff &= 0xffff;
		if (diff == TX_DESC_CNT)
			diff = MAX_TX_DESC_CNT;
	}
M
Michael Chan 已提交
248 249 250
	return (bp->tx_ring_size - diff);
}

251 252 253
static u32
bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
{
M
Michael Chan 已提交
254 255 256
	u32 val;

	spin_lock_bh(&bp->indirect_lock);
257
	REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
M
Michael Chan 已提交
258 259 260
	val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
	spin_unlock_bh(&bp->indirect_lock);
	return val;
261 262 263 264 265
}

static void
bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
{
M
Michael Chan 已提交
266
	spin_lock_bh(&bp->indirect_lock);
267 268
	REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
	REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
M
Michael Chan 已提交
269
	spin_unlock_bh(&bp->indirect_lock);
270 271
}

272 273 274 275 276 277 278 279 280 281 282 283
static void
bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
{
	bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
}

static u32
bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
{
	return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
}

284 285 286 287
static void
bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
{
	offset += cid_addr;
M
Michael Chan 已提交
288
	spin_lock_bh(&bp->indirect_lock);
M
Michael Chan 已提交
289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		int i;

		REG_WR(bp, BNX2_CTX_CTX_DATA, val);
		REG_WR(bp, BNX2_CTX_CTX_CTRL,
		       offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
		for (i = 0; i < 5; i++) {
			u32 val;
			val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
			if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
				break;
			udelay(5);
		}
	} else {
		REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
		REG_WR(bp, BNX2_CTX_DATA, val);
	}
M
Michael Chan 已提交
306
	spin_unlock_bh(&bp->indirect_lock);
307 308 309 310 311 312 313 314
}

static int
bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
{
	u32 val1;
	int i, ret;

315
	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352
		val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
		val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;

		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
		REG_RD(bp, BNX2_EMAC_MDIO_MODE);

		udelay(40);
	}

	val1 = (bp->phy_addr << 21) | (reg << 16) |
		BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
		BNX2_EMAC_MDIO_COMM_START_BUSY;
	REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);

	for (i = 0; i < 50; i++) {
		udelay(10);

		val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
		if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
			udelay(5);

			val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
			val1 &= BNX2_EMAC_MDIO_COMM_DATA;

			break;
		}
	}

	if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
		*val = 0x0;
		ret = -EBUSY;
	}
	else {
		*val = val1;
		ret = 0;
	}

353
	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371
		val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
		val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;

		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
		REG_RD(bp, BNX2_EMAC_MDIO_MODE);

		udelay(40);
	}

	return ret;
}

static int
bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
{
	u32 val1;
	int i, ret;

372
	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
373 374 375 376 377 378 379 380 381 382 383 384 385
		val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
		val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;

		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
		REG_RD(bp, BNX2_EMAC_MDIO_MODE);

		udelay(40);
	}

	val1 = (bp->phy_addr << 21) | (reg << 16) | val |
		BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
		BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
	REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
386

387 388 389 390 391 392 393 394 395 396 397 398 399 400 401
	for (i = 0; i < 50; i++) {
		udelay(10);

		val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
		if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
			udelay(5);
			break;
		}
	}

	if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
        	ret = -EBUSY;
	else
		ret = 0;

402
	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
403 404 405 406 407 408 409 410 411 412 413 414 415 416 417
		val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
		val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;

		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
		REG_RD(bp, BNX2_EMAC_MDIO_MODE);

		udelay(40);
	}

	return ret;
}

static void
bnx2_disable_int(struct bnx2 *bp)
{
418 419 420 421 422 423 424 425
	int i;
	struct bnx2_napi *bnapi;

	for (i = 0; i < bp->irq_nvecs; i++) {
		bnapi = &bp->bnx2_napi[i];
		REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
		       BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
	}
426 427 428 429 430 431
	REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
}

static void
bnx2_enable_int(struct bnx2 *bp)
{
432 433
	int i;
	struct bnx2_napi *bnapi;
434

435 436
	for (i = 0; i < bp->irq_nvecs; i++) {
		bnapi = &bp->bnx2_napi[i];
437

438 439 440 441
		REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
		       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
		       BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
		       bnapi->last_status_idx);
442

443 444 445 446
		REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
		       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
		       bnapi->last_status_idx);
	}
M
Michael Chan 已提交
447
	REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
448 449 450 451 452
}

static void
bnx2_disable_int_sync(struct bnx2 *bp)
{
453 454
	int i;

455 456
	atomic_inc(&bp->intr_sem);
	bnx2_disable_int(bp);
457 458
	for (i = 0; i < bp->irq_nvecs; i++)
		synchronize_irq(bp->irq_tbl[i].vector);
459 460
}

461 462 463
static void
bnx2_napi_disable(struct bnx2 *bp)
{
464 465 466 467
	int i;

	for (i = 0; i < bp->irq_nvecs; i++)
		napi_disable(&bp->bnx2_napi[i].napi);
468 469 470 471 472
}

static void
bnx2_napi_enable(struct bnx2 *bp)
{
473 474 475 476
	int i;

	for (i = 0; i < bp->irq_nvecs; i++)
		napi_enable(&bp->bnx2_napi[i].napi);
477 478
}

479 480 481 482 483
static void
bnx2_netif_stop(struct bnx2 *bp)
{
	bnx2_disable_int_sync(bp);
	if (netif_running(bp->dev)) {
484
		bnx2_napi_disable(bp);
485 486 487 488 489 490 491 492 493 494 495
		netif_tx_disable(bp->dev);
		bp->dev->trans_start = jiffies;	/* prevent tx timeout */
	}
}

static void
bnx2_netif_start(struct bnx2 *bp)
{
	if (atomic_dec_and_test(&bp->intr_sem)) {
		if (netif_running(bp->dev)) {
			netif_wake_queue(bp->dev);
496
			bnx2_napi_enable(bp);
497 498 499 500 501
			bnx2_enable_int(bp);
		}
	}
}

502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521
static void
bnx2_free_tx_mem(struct bnx2 *bp)
{
	int i;

	for (i = 0; i < bp->num_tx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;

		if (txr->tx_desc_ring) {
			pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
					    txr->tx_desc_ring,
					    txr->tx_desc_mapping);
			txr->tx_desc_ring = NULL;
		}
		kfree(txr->tx_buf_ring);
		txr->tx_buf_ring = NULL;
	}
}

522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555
static void
bnx2_free_rx_mem(struct bnx2 *bp)
{
	int i;

	for (i = 0; i < bp->num_rx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
		int j;

		for (j = 0; j < bp->rx_max_ring; j++) {
			if (rxr->rx_desc_ring[j])
				pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
						    rxr->rx_desc_ring[j],
						    rxr->rx_desc_mapping[j]);
			rxr->rx_desc_ring[j] = NULL;
		}
		if (rxr->rx_buf_ring)
			vfree(rxr->rx_buf_ring);
		rxr->rx_buf_ring = NULL;

		for (j = 0; j < bp->rx_max_pg_ring; j++) {
			if (rxr->rx_pg_desc_ring[j])
				pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
						    rxr->rx_pg_desc_ring[i],
						    rxr->rx_pg_desc_mapping[i]);
			rxr->rx_pg_desc_ring[i] = NULL;
		}
		if (rxr->rx_pg_ring)
			vfree(rxr->rx_pg_ring);
		rxr->rx_pg_ring = NULL;
	}
}

556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577
static int
bnx2_alloc_tx_mem(struct bnx2 *bp)
{
	int i;

	for (i = 0; i < bp->num_tx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;

		txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
		if (txr->tx_buf_ring == NULL)
			return -ENOMEM;

		txr->tx_desc_ring =
			pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
					     &txr->tx_desc_mapping);
		if (txr->tx_desc_ring == NULL)
			return -ENOMEM;
	}
	return 0;
}

578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626
static int
bnx2_alloc_rx_mem(struct bnx2 *bp)
{
	int i;

	for (i = 0; i < bp->num_rx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
		int j;

		rxr->rx_buf_ring =
			vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
		if (rxr->rx_buf_ring == NULL)
			return -ENOMEM;

		memset(rxr->rx_buf_ring, 0,
		       SW_RXBD_RING_SIZE * bp->rx_max_ring);

		for (j = 0; j < bp->rx_max_ring; j++) {
			rxr->rx_desc_ring[j] =
				pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
						     &rxr->rx_desc_mapping[j]);
			if (rxr->rx_desc_ring[j] == NULL)
				return -ENOMEM;

		}

		if (bp->rx_pg_ring_size) {
			rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
						  bp->rx_max_pg_ring);
			if (rxr->rx_pg_ring == NULL)
				return -ENOMEM;

			memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
			       bp->rx_max_pg_ring);
		}

		for (j = 0; j < bp->rx_max_pg_ring; j++) {
			rxr->rx_pg_desc_ring[j] =
				pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
						&rxr->rx_pg_desc_mapping[j]);
			if (rxr->rx_pg_desc_ring[j] == NULL)
				return -ENOMEM;

		}
	}
	return 0;
}

627 628 629
static void
bnx2_free_mem(struct bnx2 *bp)
{
630
	int i;
631
	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
632

633
	bnx2_free_tx_mem(bp);
634
	bnx2_free_rx_mem(bp);
635

M
Michael Chan 已提交
636 637 638 639 640 641 642 643
	for (i = 0; i < bp->ctx_pages; i++) {
		if (bp->ctx_blk[i]) {
			pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
					    bp->ctx_blk[i],
					    bp->ctx_blk_mapping[i]);
			bp->ctx_blk[i] = NULL;
		}
	}
644
	if (bnapi->status_blk.msi) {
645
		pci_free_consistent(bp->pdev, bp->status_stats_size,
646 647 648
				    bnapi->status_blk.msi,
				    bp->status_blk_mapping);
		bnapi->status_blk.msi = NULL;
649
		bp->stats_blk = NULL;
650 651 652 653 654 655
	}
}

static int
bnx2_alloc_mem(struct bnx2 *bp)
{
656
	int i, status_blk_size, err;
657 658
	struct bnx2_napi *bnapi;
	void *status_blk;
659

660 661
	/* Combine status and statistics blocks into one allocation. */
	status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
662
	if (bp->flags & BNX2_FLAG_MSIX_CAP)
663 664
		status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
						 BNX2_SBLK_MSIX_ALIGN_SIZE);
665 666 667
	bp->status_stats_size = status_blk_size +
				sizeof(struct statistics_block);

668 669 670
	status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
					  &bp->status_blk_mapping);
	if (status_blk == NULL)
671 672
		goto alloc_mem_err;

673
	memset(status_blk, 0, bp->status_stats_size);
674

675 676 677 678 679 680
	bnapi = &bp->bnx2_napi[0];
	bnapi->status_blk.msi = status_blk;
	bnapi->hw_tx_cons_ptr =
		&bnapi->status_blk.msi->status_tx_quick_consumer_index0;
	bnapi->hw_rx_cons_ptr =
		&bnapi->status_blk.msi->status_rx_quick_consumer_index0;
681
	if (bp->flags & BNX2_FLAG_MSIX_CAP) {
682
		for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
683 684 685
			struct status_block_msix *sblk;

			bnapi = &bp->bnx2_napi[i];
686

687 688 689 690 691 692 693
			sblk = (void *) (status_blk +
					 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
			bnapi->status_blk.msix = sblk;
			bnapi->hw_tx_cons_ptr =
				&sblk->status_tx_quick_consumer_index;
			bnapi->hw_rx_cons_ptr =
				&sblk->status_rx_quick_consumer_index;
694 695 696
			bnapi->int_num = i << 24;
		}
	}
697

698
	bp->stats_blk = status_blk + status_blk_size;
699

700
	bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
701

M
Michael Chan 已提交
702 703 704 705 706 707 708 709 710 711 712 713
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
		if (bp->ctx_pages == 0)
			bp->ctx_pages = 1;
		for (i = 0; i < bp->ctx_pages; i++) {
			bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
						BCM_PAGE_SIZE,
						&bp->ctx_blk_mapping[i]);
			if (bp->ctx_blk[i] == NULL)
				goto alloc_mem_err;
		}
	}
714

715 716 717 718
	err = bnx2_alloc_rx_mem(bp);
	if (err)
		goto alloc_mem_err;

719 720 721 722
	err = bnx2_alloc_tx_mem(bp);
	if (err)
		goto alloc_mem_err;

723 724 725 726 727 728 729
	return 0;

alloc_mem_err:
	bnx2_free_mem(bp);
	return -ENOMEM;
}

730 731 732 733 734
static void
bnx2_report_fw_link(struct bnx2 *bp)
{
	u32 fw_link_status = 0;

735
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
736 737
		return;

738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772
	if (bp->link_up) {
		u32 bmsr;

		switch (bp->line_speed) {
		case SPEED_10:
			if (bp->duplex == DUPLEX_HALF)
				fw_link_status = BNX2_LINK_STATUS_10HALF;
			else
				fw_link_status = BNX2_LINK_STATUS_10FULL;
			break;
		case SPEED_100:
			if (bp->duplex == DUPLEX_HALF)
				fw_link_status = BNX2_LINK_STATUS_100HALF;
			else
				fw_link_status = BNX2_LINK_STATUS_100FULL;
			break;
		case SPEED_1000:
			if (bp->duplex == DUPLEX_HALF)
				fw_link_status = BNX2_LINK_STATUS_1000HALF;
			else
				fw_link_status = BNX2_LINK_STATUS_1000FULL;
			break;
		case SPEED_2500:
			if (bp->duplex == DUPLEX_HALF)
				fw_link_status = BNX2_LINK_STATUS_2500HALF;
			else
				fw_link_status = BNX2_LINK_STATUS_2500FULL;
			break;
		}

		fw_link_status |= BNX2_LINK_STATUS_LINK_UP;

		if (bp->autoneg) {
			fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;

773 774
			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
775 776

			if (!(bmsr & BMSR_ANEGCOMPLETE) ||
777
			    bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
778 779 780 781 782 783 784 785
				fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
			else
				fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
		}
	}
	else
		fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;

786
	bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
787 788
}

M
Michael Chan 已提交
789 790 791 792
static char *
bnx2_xceiver_str(struct bnx2 *bp)
{
	return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
793
		((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
M
Michael Chan 已提交
794 795 796
		 "Copper"));
}

797 798 799 800 801
static void
bnx2_report_link(struct bnx2 *bp)
{
	if (bp->link_up) {
		netif_carrier_on(bp->dev);
M
Michael Chan 已提交
802 803
		printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
		       bnx2_xceiver_str(bp));
804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826

		printk("%d Mbps ", bp->line_speed);

		if (bp->duplex == DUPLEX_FULL)
			printk("full duplex");
		else
			printk("half duplex");

		if (bp->flow_ctrl) {
			if (bp->flow_ctrl & FLOW_CTRL_RX) {
				printk(", receive ");
				if (bp->flow_ctrl & FLOW_CTRL_TX)
					printk("& transmit ");
			}
			else {
				printk(", transmit ");
			}
			printk("flow control ON");
		}
		printk("\n");
	}
	else {
		netif_carrier_off(bp->dev);
M
Michael Chan 已提交
827 828
		printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
		       bnx2_xceiver_str(bp));
829
	}
830 831

	bnx2_report_fw_link(bp);
832 833 834 835 836 837 838 839
}

static void
bnx2_resolve_flow_ctrl(struct bnx2 *bp)
{
	u32 local_adv, remote_adv;

	bp->flow_ctrl = 0;
840
	if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
841 842 843 844 845 846 847 848 849 850 851 852
		(AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {

		if (bp->duplex == DUPLEX_FULL) {
			bp->flow_ctrl = bp->req_flow_ctrl;
		}
		return;
	}

	if (bp->duplex != DUPLEX_FULL) {
		return;
	}

853
	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
M
Michael Chan 已提交
854 855 856 857 858 859 860 861 862 863 864
	    (CHIP_NUM(bp) == CHIP_NUM_5708)) {
		u32 val;

		bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
		if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
			bp->flow_ctrl |= FLOW_CTRL_TX;
		if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
			bp->flow_ctrl |= FLOW_CTRL_RX;
		return;
	}

865 866
	bnx2_read_phy(bp, bp->mii_adv, &local_adv);
	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
867

868
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909
		u32 new_local_adv = 0;
		u32 new_remote_adv = 0;

		if (local_adv & ADVERTISE_1000XPAUSE)
			new_local_adv |= ADVERTISE_PAUSE_CAP;
		if (local_adv & ADVERTISE_1000XPSE_ASYM)
			new_local_adv |= ADVERTISE_PAUSE_ASYM;
		if (remote_adv & ADVERTISE_1000XPAUSE)
			new_remote_adv |= ADVERTISE_PAUSE_CAP;
		if (remote_adv & ADVERTISE_1000XPSE_ASYM)
			new_remote_adv |= ADVERTISE_PAUSE_ASYM;

		local_adv = new_local_adv;
		remote_adv = new_remote_adv;
	}

	/* See Table 28B-3 of 802.3ab-1999 spec. */
	if (local_adv & ADVERTISE_PAUSE_CAP) {
		if(local_adv & ADVERTISE_PAUSE_ASYM) {
	                if (remote_adv & ADVERTISE_PAUSE_CAP) {
				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
			}
			else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
				bp->flow_ctrl = FLOW_CTRL_RX;
			}
		}
		else {
			if (remote_adv & ADVERTISE_PAUSE_CAP) {
				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
			}
		}
	}
	else if (local_adv & ADVERTISE_PAUSE_ASYM) {
		if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
			(remote_adv & ADVERTISE_PAUSE_ASYM)) {

			bp->flow_ctrl = FLOW_CTRL_TX;
		}
	}
}

910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948
static int
bnx2_5709s_linkup(struct bnx2 *bp)
{
	u32 val, speed;

	bp->link_up = 1;

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
	bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);

	if ((bp->autoneg & AUTONEG_SPEED) == 0) {
		bp->line_speed = bp->req_line_speed;
		bp->duplex = bp->req_duplex;
		return 0;
	}
	speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
	switch (speed) {
		case MII_BNX2_GP_TOP_AN_SPEED_10:
			bp->line_speed = SPEED_10;
			break;
		case MII_BNX2_GP_TOP_AN_SPEED_100:
			bp->line_speed = SPEED_100;
			break;
		case MII_BNX2_GP_TOP_AN_SPEED_1G:
		case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
			bp->line_speed = SPEED_1000;
			break;
		case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
			bp->line_speed = SPEED_2500;
			break;
	}
	if (val & MII_BNX2_GP_TOP_AN_FD)
		bp->duplex = DUPLEX_FULL;
	else
		bp->duplex = DUPLEX_HALF;
	return 0;
}

949
static int
M
Michael Chan 已提交
950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979
bnx2_5708s_linkup(struct bnx2 *bp)
{
	u32 val;

	bp->link_up = 1;
	bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
	switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
		case BCM5708S_1000X_STAT1_SPEED_10:
			bp->line_speed = SPEED_10;
			break;
		case BCM5708S_1000X_STAT1_SPEED_100:
			bp->line_speed = SPEED_100;
			break;
		case BCM5708S_1000X_STAT1_SPEED_1G:
			bp->line_speed = SPEED_1000;
			break;
		case BCM5708S_1000X_STAT1_SPEED_2G5:
			bp->line_speed = SPEED_2500;
			break;
	}
	if (val & BCM5708S_1000X_STAT1_FD)
		bp->duplex = DUPLEX_FULL;
	else
		bp->duplex = DUPLEX_HALF;

	return 0;
}

static int
bnx2_5706s_linkup(struct bnx2 *bp)
980 981 982 983 984 985
{
	u32 bmcr, local_adv, remote_adv, common;

	bp->link_up = 1;
	bp->line_speed = SPEED_1000;

986
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
987 988 989 990 991 992 993 994 995 996 997
	if (bmcr & BMCR_FULLDPLX) {
		bp->duplex = DUPLEX_FULL;
	}
	else {
		bp->duplex = DUPLEX_HALF;
	}

	if (!(bmcr & BMCR_ANENABLE)) {
		return 0;
	}

998 999
	bnx2_read_phy(bp, bp->mii_adv, &local_adv);
	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019

	common = local_adv & remote_adv;
	if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {

		if (common & ADVERTISE_1000XFULL) {
			bp->duplex = DUPLEX_FULL;
		}
		else {
			bp->duplex = DUPLEX_HALF;
		}
	}

	return 0;
}

static int
bnx2_copper_linkup(struct bnx2 *bp)
{
	u32 bmcr;

1020
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036
	if (bmcr & BMCR_ANENABLE) {
		u32 local_adv, remote_adv, common;

		bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
		bnx2_read_phy(bp, MII_STAT1000, &remote_adv);

		common = local_adv & (remote_adv >> 2);
		if (common & ADVERTISE_1000FULL) {
			bp->line_speed = SPEED_1000;
			bp->duplex = DUPLEX_FULL;
		}
		else if (common & ADVERTISE_1000HALF) {
			bp->line_speed = SPEED_1000;
			bp->duplex = DUPLEX_HALF;
		}
		else {
1037 1038
			bnx2_read_phy(bp, bp->mii_adv, &local_adv);
			bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080

			common = local_adv & remote_adv;
			if (common & ADVERTISE_100FULL) {
				bp->line_speed = SPEED_100;
				bp->duplex = DUPLEX_FULL;
			}
			else if (common & ADVERTISE_100HALF) {
				bp->line_speed = SPEED_100;
				bp->duplex = DUPLEX_HALF;
			}
			else if (common & ADVERTISE_10FULL) {
				bp->line_speed = SPEED_10;
				bp->duplex = DUPLEX_FULL;
			}
			else if (common & ADVERTISE_10HALF) {
				bp->line_speed = SPEED_10;
				bp->duplex = DUPLEX_HALF;
			}
			else {
				bp->line_speed = 0;
				bp->link_up = 0;
			}
		}
	}
	else {
		if (bmcr & BMCR_SPEED100) {
			bp->line_speed = SPEED_100;
		}
		else {
			bp->line_speed = SPEED_10;
		}
		if (bmcr & BMCR_FULLDPLX) {
			bp->duplex = DUPLEX_FULL;
		}
		else {
			bp->duplex = DUPLEX_HALF;
		}
	}

	return 0;
}

1081
static void
1082
bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1083
{
1084
	u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116

	val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
	val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
	val |= 0x02 << 8;

	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		u32 lo_water, hi_water;

		if (bp->flow_ctrl & FLOW_CTRL_TX)
			lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
		else
			lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
		if (lo_water >= bp->rx_ring_size)
			lo_water = 0;

		hi_water = bp->rx_ring_size / 4;

		if (hi_water <= lo_water)
			lo_water = 0;

		hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
		lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;

		if (hi_water > 0xf)
			hi_water = 0xf;
		else if (hi_water == 0)
			lo_water = 0;
		val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
	}
	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
}

1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129
static void
bnx2_init_all_rx_contexts(struct bnx2 *bp)
{
	int i;
	u32 cid;

	for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
		if (i == 1)
			cid = RX_RSS_CID;
		bnx2_init_rx_context(bp, cid);
	}
}

1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144
static int
bnx2_set_mac_link(struct bnx2 *bp)
{
	u32 val;

	REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
	if (bp->link_up && (bp->line_speed == SPEED_1000) &&
		(bp->duplex == DUPLEX_HALF)) {
		REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
	}

	/* Configure the EMAC mode register. */
	val = REG_RD(bp, BNX2_EMAC_MODE);

	val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
M
Michael Chan 已提交
1145
		BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
M
Michael Chan 已提交
1146
		BNX2_EMAC_MODE_25G_MODE);
1147 1148

	if (bp->link_up) {
M
Michael Chan 已提交
1149 1150
		switch (bp->line_speed) {
			case SPEED_10:
M
Michael Chan 已提交
1151 1152
				if (CHIP_NUM(bp) != CHIP_NUM_5706) {
					val |= BNX2_EMAC_MODE_PORT_MII_10M;
M
Michael Chan 已提交
1153 1154 1155 1156 1157 1158 1159
					break;
				}
				/* fall through */
			case SPEED_100:
				val |= BNX2_EMAC_MODE_PORT_MII;
				break;
			case SPEED_2500:
M
Michael Chan 已提交
1160
				val |= BNX2_EMAC_MODE_25G_MODE;
M
Michael Chan 已提交
1161 1162 1163 1164 1165
				/* fall through */
			case SPEED_1000:
				val |= BNX2_EMAC_MODE_PORT_GMII;
				break;
		}
1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193
	}
	else {
		val |= BNX2_EMAC_MODE_PORT_GMII;
	}

	/* Set the MAC to operate in the appropriate duplex mode. */
	if (bp->duplex == DUPLEX_HALF)
		val |= BNX2_EMAC_MODE_HALF_DUPLEX;
	REG_WR(bp, BNX2_EMAC_MODE, val);

	/* Enable/disable rx PAUSE. */
	bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;

	if (bp->flow_ctrl & FLOW_CTRL_RX)
		bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
	REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);

	/* Enable/disable tx PAUSE. */
	val = REG_RD(bp, BNX2_EMAC_TX_MODE);
	val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;

	if (bp->flow_ctrl & FLOW_CTRL_TX)
		val |= BNX2_EMAC_TX_MODE_FLOW_EN;
	REG_WR(bp, BNX2_EMAC_TX_MODE, val);

	/* Acknowledge the interrupt. */
	REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);

1194
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
1195
		bnx2_init_all_rx_contexts(bp);
1196

1197 1198 1199
	return 0;
}

1200 1201 1202
static void
bnx2_enable_bmsr1(struct bnx2 *bp)
{
1203
	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1204 1205 1206 1207 1208 1209 1210 1211
	    (CHIP_NUM(bp) == CHIP_NUM_5709))
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_GP_STATUS);
}

static void
bnx2_disable_bmsr1(struct bnx2 *bp)
{
1212
	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1213 1214 1215 1216 1217
	    (CHIP_NUM(bp) == CHIP_NUM_5709))
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
}

1218 1219 1220 1221 1222 1223
static int
bnx2_test_and_enable_2g5(struct bnx2 *bp)
{
	u32 up1;
	int ret = 1;

1224
	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1225 1226 1227 1228 1229
		return 0;

	if (bp->autoneg & AUTONEG_SPEED)
		bp->advertising |= ADVERTISED_2500baseX_Full;

1230 1231 1232
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);

1233 1234 1235 1236 1237 1238 1239
	bnx2_read_phy(bp, bp->mii_up1, &up1);
	if (!(up1 & BCM5708S_UP1_2G5)) {
		up1 |= BCM5708S_UP1_2G5;
		bnx2_write_phy(bp, bp->mii_up1, up1);
		ret = 0;
	}

1240 1241 1242 1243
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);

1244 1245 1246 1247 1248 1249 1250 1251 1252
	return ret;
}

static int
bnx2_test_and_disable_2g5(struct bnx2 *bp)
{
	u32 up1;
	int ret = 0;

1253
	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1254 1255
		return 0;

1256 1257 1258
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);

1259 1260 1261 1262 1263 1264 1265
	bnx2_read_phy(bp, bp->mii_up1, &up1);
	if (up1 & BCM5708S_UP1_2G5) {
		up1 &= ~BCM5708S_UP1_2G5;
		bnx2_write_phy(bp, bp->mii_up1, up1);
		ret = 1;
	}

1266 1267 1268 1269
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);

1270 1271 1272 1273 1274 1275 1276 1277
	return ret;
}

static void
bnx2_enable_forced_2g5(struct bnx2 *bp)
{
	u32 bmcr;

1278
	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1279 1280
		return;

1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		u32 val;

		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_SERDES_DIG);
		bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
		val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
		val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
		bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);

		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);

	} else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
		bmcr |= BCM5708S_BMCR_FORCE_2500;
	}

	if (bp->autoneg & AUTONEG_SPEED) {
		bmcr &= ~BMCR_ANENABLE;
		if (bp->req_duplex == DUPLEX_FULL)
			bmcr |= BMCR_FULLDPLX;
	}
	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
}

static void
bnx2_disable_forced_2g5(struct bnx2 *bp)
{
	u32 bmcr;

1313
	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1314 1315
		return;

1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		u32 val;

		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_SERDES_DIG);
		bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
		val &= ~MII_BNX2_SD_MISC1_FORCE;
		bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);

		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);

	} else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1330 1331 1332 1333 1334 1335 1336 1337 1338
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
		bmcr &= ~BCM5708S_BMCR_FORCE_2500;
	}

	if (bp->autoneg & AUTONEG_SPEED)
		bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
}

1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351
static void
bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
{
	u32 val;

	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
	if (start)
		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
	else
		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
}

1352 1353 1354 1355 1356 1357
static int
bnx2_set_link(struct bnx2 *bp)
{
	u32 bmsr;
	u8 link_up;

M
Michael Chan 已提交
1358
	if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1359 1360 1361 1362
		bp->link_up = 1;
		return 0;
	}

1363
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1364 1365
		return 0;

1366 1367
	link_up = bp->link_up;

1368 1369 1370 1371
	bnx2_enable_bmsr1(bp);
	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
	bnx2_disable_bmsr1(bp);
1372

1373
	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1374
	    (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1375
		u32 val, an_dbg;
1376

1377
		if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1378
			bnx2_5706s_force_link_dn(bp, 0);
1379
			bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1380
		}
1381
		val = REG_RD(bp, BNX2_EMAC_STATUS);
1382 1383 1384 1385 1386 1387 1388

		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);

		if ((val & BNX2_EMAC_STATUS_LINK) &&
		    !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1389 1390 1391 1392 1393 1394 1395 1396
			bmsr |= BMSR_LSTATUS;
		else
			bmsr &= ~BMSR_LSTATUS;
	}

	if (bmsr & BMSR_LSTATUS) {
		bp->link_up = 1;

1397
		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
M
Michael Chan 已提交
1398 1399 1400 1401
			if (CHIP_NUM(bp) == CHIP_NUM_5706)
				bnx2_5706s_linkup(bp);
			else if (CHIP_NUM(bp) == CHIP_NUM_5708)
				bnx2_5708s_linkup(bp);
1402 1403
			else if (CHIP_NUM(bp) == CHIP_NUM_5709)
				bnx2_5709s_linkup(bp);
1404 1405 1406 1407 1408 1409 1410
		}
		else {
			bnx2_copper_linkup(bp);
		}
		bnx2_resolve_flow_ctrl(bp);
	}
	else {
1411
		if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1412 1413
		    (bp->autoneg & AUTONEG_SPEED))
			bnx2_disable_forced_2g5(bp);
1414

1415
		if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1416 1417 1418 1419 1420 1421
			u32 bmcr;

			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
			bmcr |= BMCR_ANENABLE;
			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);

1422
			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1423
		}
1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441
		bp->link_up = 0;
	}

	if (bp->link_up != link_up) {
		bnx2_report_link(bp);
	}

	bnx2_set_mac_link(bp);

	return 0;
}

static int
bnx2_reset_phy(struct bnx2 *bp)
{
	int i;
	u32 reg;

1442
        bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1443 1444 1445 1446 1447

#define PHY_RESET_MAX_WAIT 100
	for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
		udelay(10);

1448
		bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467
		if (!(reg & BMCR_RESET)) {
			udelay(20);
			break;
		}
	}
	if (i == PHY_RESET_MAX_WAIT) {
		return -EBUSY;
	}
	return 0;
}

static u32
bnx2_phy_get_pause_adv(struct bnx2 *bp)
{
	u32 adv = 0;

	if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
		(FLOW_CTRL_RX | FLOW_CTRL_TX)) {

1468
		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1469 1470 1471 1472 1473 1474 1475
			adv = ADVERTISE_1000XPAUSE;
		}
		else {
			adv = ADVERTISE_PAUSE_CAP;
		}
	}
	else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1476
		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1477 1478 1479 1480 1481 1482 1483
			adv = ADVERTISE_1000XPSE_ASYM;
		}
		else {
			adv = ADVERTISE_PAUSE_ASYM;
		}
	}
	else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1484
		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1485 1486 1487 1488 1489 1490 1491 1492 1493
			adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
		}
		else {
			adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
		}
	}
	return adv;
}

1494
static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1495

1496
static int
1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536
bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
{
	u32 speed_arg = 0, pause_adv;

	pause_adv = bnx2_phy_get_pause_adv(bp);

	if (bp->autoneg & AUTONEG_SPEED) {
		speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
		if (bp->advertising & ADVERTISED_10baseT_Half)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
		if (bp->advertising & ADVERTISED_10baseT_Full)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
		if (bp->advertising & ADVERTISED_100baseT_Half)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
		if (bp->advertising & ADVERTISED_100baseT_Full)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
		if (bp->advertising & ADVERTISED_1000baseT_Full)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
		if (bp->advertising & ADVERTISED_2500baseX_Full)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
	} else {
		if (bp->req_line_speed == SPEED_2500)
			speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
		else if (bp->req_line_speed == SPEED_1000)
			speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
		else if (bp->req_line_speed == SPEED_100) {
			if (bp->req_duplex == DUPLEX_FULL)
				speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
			else
				speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
		} else if (bp->req_line_speed == SPEED_10) {
			if (bp->req_duplex == DUPLEX_FULL)
				speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
			else
				speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
		}
	}

	if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
		speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1537
	if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1538 1539 1540 1541 1542 1543
		speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;

	if (port == PORT_TP)
		speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
			     BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;

1544
	bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1545 1546

	spin_unlock_bh(&bp->phy_lock);
1547
	bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1548 1549 1550 1551 1552 1553 1554
	spin_lock_bh(&bp->phy_lock);

	return 0;
}

static int
bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1555
{
1556
	u32 adv, bmcr;
1557 1558
	u32 new_adv = 0;

1559
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1560 1561
		return (bnx2_setup_remote_phy(bp, port));

1562 1563
	if (!(bp->autoneg & AUTONEG_SPEED)) {
		u32 new_bmcr;
M
Michael Chan 已提交
1564 1565
		int force_link_down = 0;

1566 1567 1568 1569 1570 1571 1572
		if (bp->req_line_speed == SPEED_2500) {
			if (!bnx2_test_and_enable_2g5(bp))
				force_link_down = 1;
		} else if (bp->req_line_speed == SPEED_1000) {
			if (bnx2_test_and_disable_2g5(bp))
				force_link_down = 1;
		}
1573
		bnx2_read_phy(bp, bp->mii_adv, &adv);
M
Michael Chan 已提交
1574 1575
		adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);

1576
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1577
		new_bmcr = bmcr & ~BMCR_ANENABLE;
M
Michael Chan 已提交
1578
		new_bmcr |= BMCR_SPEED1000;
1579

1580 1581 1582 1583 1584 1585 1586 1587 1588
		if (CHIP_NUM(bp) == CHIP_NUM_5709) {
			if (bp->req_line_speed == SPEED_2500)
				bnx2_enable_forced_2g5(bp);
			else if (bp->req_line_speed == SPEED_1000) {
				bnx2_disable_forced_2g5(bp);
				new_bmcr &= ~0x2000;
			}

		} else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1589 1590 1591 1592
			if (bp->req_line_speed == SPEED_2500)
				new_bmcr |= BCM5708S_BMCR_FORCE_2500;
			else
				new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
M
Michael Chan 已提交
1593 1594
		}

1595
		if (bp->req_duplex == DUPLEX_FULL) {
M
Michael Chan 已提交
1596
			adv |= ADVERTISE_1000XFULL;
1597 1598 1599
			new_bmcr |= BMCR_FULLDPLX;
		}
		else {
M
Michael Chan 已提交
1600
			adv |= ADVERTISE_1000XHALF;
1601 1602
			new_bmcr &= ~BMCR_FULLDPLX;
		}
M
Michael Chan 已提交
1603
		if ((new_bmcr != bmcr) || (force_link_down)) {
1604 1605
			/* Force a link down visible on the other side */
			if (bp->link_up) {
1606
				bnx2_write_phy(bp, bp->mii_adv, adv &
M
Michael Chan 已提交
1607 1608
					       ~(ADVERTISE_1000XFULL |
						 ADVERTISE_1000XHALF));
1609
				bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1610 1611 1612 1613
					BMCR_ANRESTART | BMCR_ANENABLE);

				bp->link_up = 0;
				netif_carrier_off(bp->dev);
1614
				bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
M
Michael Chan 已提交
1615
				bnx2_report_link(bp);
1616
			}
1617 1618
			bnx2_write_phy(bp, bp->mii_adv, adv);
			bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1619 1620 1621
		} else {
			bnx2_resolve_flow_ctrl(bp);
			bnx2_set_mac_link(bp);
1622 1623 1624 1625
		}
		return 0;
	}

1626
	bnx2_test_and_enable_2g5(bp);
M
Michael Chan 已提交
1627

1628 1629 1630 1631 1632
	if (bp->advertising & ADVERTISED_1000baseT_Full)
		new_adv |= ADVERTISE_1000XFULL;

	new_adv |= bnx2_phy_get_pause_adv(bp);

1633 1634
	bnx2_read_phy(bp, bp->mii_adv, &adv);
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1635 1636 1637 1638 1639

	bp->serdes_an_pending = 0;
	if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
		/* Force a link down visible on the other side */
		if (bp->link_up) {
1640
			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
M
Michael Chan 已提交
1641 1642 1643
			spin_unlock_bh(&bp->phy_lock);
			msleep(20);
			spin_lock_bh(&bp->phy_lock);
1644 1645
		}

1646 1647
		bnx2_write_phy(bp, bp->mii_adv, new_adv);
		bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1648
			BMCR_ANENABLE);
1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659
		/* Speed up link-up time when the link partner
		 * does not autonegotiate which is very common
		 * in blade servers. Some blade servers use
		 * IPMI for kerboard input and it's important
		 * to minimize link disruptions. Autoneg. involves
		 * exchanging base pages plus 3 next pages and
		 * normally completes in about 120 msec.
		 */
		bp->current_interval = SERDES_AN_TIMEOUT;
		bp->serdes_an_pending = 1;
		mod_timer(&bp->timer, jiffies + bp->current_interval);
1660 1661 1662
	} else {
		bnx2_resolve_flow_ctrl(bp);
		bnx2_set_mac_link(bp);
1663 1664 1665 1666 1667 1668
	}

	return 0;
}

#define ETHTOOL_ALL_FIBRE_SPEED						\
1669
	(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?			\
1670 1671
		(ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
		(ADVERTISED_1000baseT_Full)
1672 1673 1674 1675 1676 1677 1678 1679

#define ETHTOOL_ALL_COPPER_SPEED					\
	(ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |		\
	ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |		\
	ADVERTISED_1000baseT_Full)

#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
	ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1680

1681 1682
#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)

1683 1684 1685 1686 1687 1688
static void
bnx2_set_default_remote_link(struct bnx2 *bp)
{
	u32 link;

	if (bp->phy_port == PORT_TP)
1689
		link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1690
	else
1691
		link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729

	if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
		bp->req_line_speed = 0;
		bp->autoneg |= AUTONEG_SPEED;
		bp->advertising = ADVERTISED_Autoneg;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
			bp->advertising |= ADVERTISED_10baseT_Half;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
			bp->advertising |= ADVERTISED_10baseT_Full;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
			bp->advertising |= ADVERTISED_100baseT_Half;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
			bp->advertising |= ADVERTISED_100baseT_Full;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
			bp->advertising |= ADVERTISED_1000baseT_Full;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
			bp->advertising |= ADVERTISED_2500baseX_Full;
	} else {
		bp->autoneg = 0;
		bp->advertising = 0;
		bp->req_duplex = DUPLEX_FULL;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
			bp->req_line_speed = SPEED_10;
			if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
				bp->req_duplex = DUPLEX_HALF;
		}
		if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
			bp->req_line_speed = SPEED_100;
			if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
				bp->req_duplex = DUPLEX_HALF;
		}
		if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
			bp->req_line_speed = SPEED_1000;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
			bp->req_line_speed = SPEED_2500;
	}
}

1730 1731 1732
static void
bnx2_set_default_link(struct bnx2 *bp)
{
1733 1734 1735 1736
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
		bnx2_set_default_remote_link(bp);
		return;
	}
1737

1738 1739
	bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
	bp->req_line_speed = 0;
1740
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1741 1742 1743 1744
		u32 reg;

		bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;

1745
		reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1746 1747 1748 1749 1750 1751 1752 1753 1754 1755
		reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
		if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
			bp->autoneg = 0;
			bp->req_line_speed = bp->line_speed = SPEED_1000;
			bp->req_duplex = DUPLEX_FULL;
		}
	} else
		bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
}

M
Michael Chan 已提交
1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769
static void
bnx2_send_heart_beat(struct bnx2 *bp)
{
	u32 msg;
	u32 addr;

	spin_lock(&bp->indirect_lock);
	msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
	addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
	REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
	REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
	spin_unlock(&bp->indirect_lock);
}

1770 1771 1772 1773 1774 1775 1776
static void
bnx2_remote_phy_event(struct bnx2 *bp)
{
	u32 msg;
	u8 link_up = bp->link_up;
	u8 old_port;

1777
	msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1778

M
Michael Chan 已提交
1779 1780 1781 1782 1783
	if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
		bnx2_send_heart_beat(bp);

	msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;

1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851
	if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
		bp->link_up = 0;
	else {
		u32 speed;

		bp->link_up = 1;
		speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
		bp->duplex = DUPLEX_FULL;
		switch (speed) {
			case BNX2_LINK_STATUS_10HALF:
				bp->duplex = DUPLEX_HALF;
			case BNX2_LINK_STATUS_10FULL:
				bp->line_speed = SPEED_10;
				break;
			case BNX2_LINK_STATUS_100HALF:
				bp->duplex = DUPLEX_HALF;
			case BNX2_LINK_STATUS_100BASE_T4:
			case BNX2_LINK_STATUS_100FULL:
				bp->line_speed = SPEED_100;
				break;
			case BNX2_LINK_STATUS_1000HALF:
				bp->duplex = DUPLEX_HALF;
			case BNX2_LINK_STATUS_1000FULL:
				bp->line_speed = SPEED_1000;
				break;
			case BNX2_LINK_STATUS_2500HALF:
				bp->duplex = DUPLEX_HALF;
			case BNX2_LINK_STATUS_2500FULL:
				bp->line_speed = SPEED_2500;
				break;
			default:
				bp->line_speed = 0;
				break;
		}

		bp->flow_ctrl = 0;
		if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
		    (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
			if (bp->duplex == DUPLEX_FULL)
				bp->flow_ctrl = bp->req_flow_ctrl;
		} else {
			if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
				bp->flow_ctrl |= FLOW_CTRL_TX;
			if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
				bp->flow_ctrl |= FLOW_CTRL_RX;
		}

		old_port = bp->phy_port;
		if (msg & BNX2_LINK_STATUS_SERDES_LINK)
			bp->phy_port = PORT_FIBRE;
		else
			bp->phy_port = PORT_TP;

		if (old_port != bp->phy_port)
			bnx2_set_default_link(bp);

	}
	if (bp->link_up != link_up)
		bnx2_report_link(bp);

	bnx2_set_mac_link(bp);
}

static int
bnx2_set_remote_link(struct bnx2 *bp)
{
	u32 evt_code;

1852
	evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1853 1854 1855 1856 1857 1858
	switch (evt_code) {
		case BNX2_FW_EVT_CODE_LINK_EVENT:
			bnx2_remote_phy_event(bp);
			break;
		case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
		default:
M
Michael Chan 已提交
1859
			bnx2_send_heart_beat(bp);
1860 1861 1862 1863 1864
			break;
	}
	return 0;
}

1865 1866 1867 1868 1869 1870
static int
bnx2_setup_copper_phy(struct bnx2 *bp)
{
	u32 bmcr;
	u32 new_bmcr;

1871
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1872 1873 1874 1875 1876 1877

	if (bp->autoneg & AUTONEG_SPEED) {
		u32 adv_reg, adv1000_reg;
		u32 new_adv_reg = 0;
		u32 new_adv1000_reg = 0;

1878
		bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894
		adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
			ADVERTISE_PAUSE_ASYM);

		bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
		adv1000_reg &= PHY_ALL_1000_SPEED;

		if (bp->advertising & ADVERTISED_10baseT_Half)
			new_adv_reg |= ADVERTISE_10HALF;
		if (bp->advertising & ADVERTISED_10baseT_Full)
			new_adv_reg |= ADVERTISE_10FULL;
		if (bp->advertising & ADVERTISED_100baseT_Half)
			new_adv_reg |= ADVERTISE_100HALF;
		if (bp->advertising & ADVERTISED_100baseT_Full)
			new_adv_reg |= ADVERTISE_100FULL;
		if (bp->advertising & ADVERTISED_1000baseT_Full)
			new_adv1000_reg |= ADVERTISE_1000FULL;
1895

1896 1897 1898 1899 1900 1901 1902 1903
		new_adv_reg |= ADVERTISE_CSMA;

		new_adv_reg |= bnx2_phy_get_pause_adv(bp);

		if ((adv1000_reg != new_adv1000_reg) ||
			(adv_reg != new_adv_reg) ||
			((bmcr & BMCR_ANENABLE) == 0)) {

1904
			bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1905
			bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1906
			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928
				BMCR_ANENABLE);
		}
		else if (bp->link_up) {
			/* Flow ctrl may have changed from auto to forced */
			/* or vice-versa. */

			bnx2_resolve_flow_ctrl(bp);
			bnx2_set_mac_link(bp);
		}
		return 0;
	}

	new_bmcr = 0;
	if (bp->req_line_speed == SPEED_100) {
		new_bmcr |= BMCR_SPEED100;
	}
	if (bp->req_duplex == DUPLEX_FULL) {
		new_bmcr |= BMCR_FULLDPLX;
	}
	if (new_bmcr != bmcr) {
		u32 bmsr;

1929 1930
		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1931

1932 1933
		if (bmsr & BMSR_LSTATUS) {
			/* Force link down */
1934
			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1935 1936 1937 1938
			spin_unlock_bh(&bp->phy_lock);
			msleep(50);
			spin_lock_bh(&bp->phy_lock);

1939 1940
			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1941 1942
		}

1943
		bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954

		/* Normally, the new speed is setup after the link has
		 * gone down and up again. In some cases, link will not go
		 * down so we need to set up the new speed here.
		 */
		if (bmsr & BMSR_LSTATUS) {
			bp->line_speed = bp->req_line_speed;
			bp->duplex = bp->req_duplex;
			bnx2_resolve_flow_ctrl(bp);
			bnx2_set_mac_link(bp);
		}
1955 1956 1957
	} else {
		bnx2_resolve_flow_ctrl(bp);
		bnx2_set_mac_link(bp);
1958 1959 1960 1961 1962
	}
	return 0;
}

static int
1963
bnx2_setup_phy(struct bnx2 *bp, u8 port)
1964 1965 1966 1967
{
	if (bp->loopback == MAC_LOOPBACK)
		return 0;

1968
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1969
		return (bnx2_setup_serdes_phy(bp, port));
1970 1971 1972 1973 1974 1975
	}
	else {
		return (bnx2_setup_copper_phy(bp));
	}
}

1976
static int
1977
bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991
{
	u32 val;

	bp->mii_bmcr = MII_BMCR + 0x10;
	bp->mii_bmsr = MII_BMSR + 0x10;
	bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
	bp->mii_adv = MII_ADVERTISE + 0x10;
	bp->mii_lpa = MII_LPA + 0x10;
	bp->mii_up1 = MII_BNX2_OVER1G_UP1;

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
	bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1992 1993
	if (reset_phy)
		bnx2_reset_phy(bp);
1994 1995 1996 1997 1998 1999 2000 2001 2002 2003

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);

	bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
	val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
	val |= MII_BNX2_SD_1000XCTL1_FIBER;
	bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
	bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2004
	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025
		val |= BCM5708S_UP1_2G5;
	else
		val &= ~BCM5708S_UP1_2G5;
	bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
	bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
	val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
	bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);

	val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
	      MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
	bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);

	return 0;
}

2026
static int
2027
bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
M
Michael Chan 已提交
2028 2029 2030
{
	u32 val;

2031 2032
	if (reset_phy)
		bnx2_reset_phy(bp);
2033 2034 2035

	bp->mii_up1 = BCM5708S_UP1;

M
Michael Chan 已提交
2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047
	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
	bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);

	bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
	val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
	bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);

	bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
	val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
	bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);

2048
	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
M
Michael Chan 已提交
2049 2050 2051 2052 2053 2054
		bnx2_read_phy(bp, BCM5708S_UP1, &val);
		val |= BCM5708S_UP1_2G5;
		bnx2_write_phy(bp, BCM5708S_UP1, val);
	}

	if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
M
Michael Chan 已提交
2055 2056
	    (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
	    (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
M
Michael Chan 已提交
2057 2058 2059 2060 2061 2062 2063 2064 2065
		/* increase tx signal amplitude */
		bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
			       BCM5708S_BLK_ADDR_TX_MISC);
		bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
		val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
		bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
		bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
	}

2066
	val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
M
Michael Chan 已提交
2067 2068 2069 2070 2071
	      BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;

	if (val) {
		u32 is_backplane;

2072
		is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
M
Michael Chan 已提交
2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084
		if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
				       BCM5708S_BLK_ADDR_TX_MISC);
			bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
				       BCM5708S_BLK_ADDR_DIG);
		}
	}
	return 0;
}

static int
2085
bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2086
{
2087 2088
	if (reset_phy)
		bnx2_reset_phy(bp);
2089

2090
	bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2091

M
Michael Chan 已提交
2092 2093
	if (CHIP_NUM(bp) == CHIP_NUM_5706)
        	REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122

	if (bp->dev->mtu > 1500) {
		u32 val;

		/* Set extended packet length bit */
		bnx2_write_phy(bp, 0x18, 0x7);
		bnx2_read_phy(bp, 0x18, &val);
		bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);

		bnx2_write_phy(bp, 0x1c, 0x6c00);
		bnx2_read_phy(bp, 0x1c, &val);
		bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
	}
	else {
		u32 val;

		bnx2_write_phy(bp, 0x18, 0x7);
		bnx2_read_phy(bp, 0x18, &val);
		bnx2_write_phy(bp, 0x18, val & ~0x4007);

		bnx2_write_phy(bp, 0x1c, 0x6c00);
		bnx2_read_phy(bp, 0x1c, &val);
		bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
	}

	return 0;
}

static int
2123
bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2124
{
M
Michael Chan 已提交
2125 2126
	u32 val;

2127 2128
	if (reset_phy)
		bnx2_reset_phy(bp);
2129

2130
	if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2131 2132 2133 2134 2135 2136 2137 2138 2139 2140
		bnx2_write_phy(bp, 0x18, 0x0c00);
		bnx2_write_phy(bp, 0x17, 0x000a);
		bnx2_write_phy(bp, 0x15, 0x310b);
		bnx2_write_phy(bp, 0x17, 0x201f);
		bnx2_write_phy(bp, 0x15, 0x9506);
		bnx2_write_phy(bp, 0x17, 0x401f);
		bnx2_write_phy(bp, 0x15, 0x14e2);
		bnx2_write_phy(bp, 0x18, 0x0400);
	}

2141
	if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2142 2143 2144 2145 2146 2147 2148
		bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
			       MII_BNX2_DSP_EXPAND_REG | 0x8);
		bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
		val &= ~(1 << 8);
		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
	}

2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166
	if (bp->dev->mtu > 1500) {
		/* Set extended packet length bit */
		bnx2_write_phy(bp, 0x18, 0x7);
		bnx2_read_phy(bp, 0x18, &val);
		bnx2_write_phy(bp, 0x18, val | 0x4000);

		bnx2_read_phy(bp, 0x10, &val);
		bnx2_write_phy(bp, 0x10, val | 0x1);
	}
	else {
		bnx2_write_phy(bp, 0x18, 0x7);
		bnx2_read_phy(bp, 0x18, &val);
		bnx2_write_phy(bp, 0x18, val & ~0x4007);

		bnx2_read_phy(bp, 0x10, &val);
		bnx2_write_phy(bp, 0x10, val & ~0x1);
	}

M
Michael Chan 已提交
2167 2168 2169 2170
	/* ethernet@wirespeed */
	bnx2_write_phy(bp, 0x18, 0x7007);
	bnx2_read_phy(bp, 0x18, &val);
	bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2171 2172 2173 2174 2175
	return 0;
}


static int
2176
bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2177 2178 2179 2180
{
	u32 val;
	int rc = 0;

2181 2182
	bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
	bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2183

2184 2185
	bp->mii_bmcr = MII_BMCR;
	bp->mii_bmsr = MII_BMSR;
2186
	bp->mii_bmsr1 = MII_BMSR;
2187 2188 2189
	bp->mii_adv = MII_ADVERTISE;
	bp->mii_lpa = MII_LPA;

2190 2191
        REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);

2192
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2193 2194
		goto setup_phy;

2195 2196 2197 2198 2199
	bnx2_read_phy(bp, MII_PHYSID1, &val);
	bp->phy_id = val << 16;
	bnx2_read_phy(bp, MII_PHYSID2, &val);
	bp->phy_id |= val & 0xffff;

2200
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
M
Michael Chan 已提交
2201
		if (CHIP_NUM(bp) == CHIP_NUM_5706)
2202
			rc = bnx2_init_5706s_phy(bp, reset_phy);
M
Michael Chan 已提交
2203
		else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2204
			rc = bnx2_init_5708s_phy(bp, reset_phy);
2205
		else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2206
			rc = bnx2_init_5709s_phy(bp, reset_phy);
2207 2208
	}
	else {
2209
		rc = bnx2_init_copper_phy(bp, reset_phy);
2210 2211
	}

2212 2213 2214
setup_phy:
	if (!rc)
		rc = bnx2_setup_phy(bp, bp->phy_port);
2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231

	return rc;
}

static int
bnx2_set_mac_loopback(struct bnx2 *bp)
{
	u32 mac_mode;

	mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
	mac_mode &= ~BNX2_EMAC_MODE_PORT;
	mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
	REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
	bp->link_up = 1;
	return 0;
}

M
Michael Chan 已提交
2232 2233 2234 2235 2236 2237 2238 2239 2240
static int bnx2_test_link(struct bnx2 *);

static int
bnx2_set_phy_loopback(struct bnx2 *bp)
{
	u32 mac_mode;
	int rc, i;

	spin_lock_bh(&bp->phy_lock);
2241
	rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
M
Michael Chan 已提交
2242 2243 2244 2245 2246 2247 2248 2249
			    BMCR_SPEED1000);
	spin_unlock_bh(&bp->phy_lock);
	if (rc)
		return rc;

	for (i = 0; i < 10; i++) {
		if (bnx2_test_link(bp) == 0)
			break;
M
Michael Chan 已提交
2250
		msleep(100);
M
Michael Chan 已提交
2251 2252 2253 2254 2255
	}

	mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
	mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
		      BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
M
Michael Chan 已提交
2256
		      BNX2_EMAC_MODE_25G_MODE);
M
Michael Chan 已提交
2257 2258 2259 2260 2261 2262 2263

	mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
	REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
	bp->link_up = 1;
	return 0;
}

2264
static int
2265
bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2266 2267 2268 2269 2270 2271 2272
{
	int i;
	u32 val;

	bp->fw_wr_seq++;
	msg_data |= bp->fw_wr_seq;

2273
	bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2274

2275 2276 2277
	if (!ack)
		return 0;

2278
	/* wait for an acknowledgement. */
2279 2280
	for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
		msleep(10);
2281

2282
		val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2283 2284 2285 2286

		if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
			break;
	}
2287 2288
	if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
		return 0;
2289 2290

	/* If we timed out, inform the firmware that this is the case. */
2291 2292 2293 2294
	if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
		if (!silent)
			printk(KERN_ERR PFX "fw sync timeout, reset code = "
					    "%x\n", msg_data);
2295 2296 2297 2298

		msg_data &= ~BNX2_DRV_MSG_CODE;
		msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;

2299
		bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2300 2301 2302 2303

		return -EBUSY;
	}

2304 2305 2306
	if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
		return -EIO;

2307 2308 2309
	return 0;
}

M
Michael Chan 已提交
2310 2311 2312 2313 2314 2315 2316 2317 2318
static int
bnx2_init_5709_context(struct bnx2 *bp)
{
	int i, ret = 0;
	u32 val;

	val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
	val |= (BCM_PAGE_BITS - 8) << 16;
	REG_WR(bp, BNX2_CTX_COMMAND, val);
2319 2320 2321 2322 2323 2324 2325 2326 2327
	for (i = 0; i < 10; i++) {
		val = REG_RD(bp, BNX2_CTX_COMMAND);
		if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
			break;
		udelay(2);
	}
	if (val & BNX2_CTX_COMMAND_MEM_INIT)
		return -EBUSY;

M
Michael Chan 已提交
2328 2329 2330
	for (i = 0; i < bp->ctx_pages; i++) {
		int j;

2331 2332 2333 2334 2335
		if (bp->ctx_blk[i])
			memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
		else
			return -ENOMEM;

M
Michael Chan 已提交
2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357
		REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
		       (bp->ctx_blk_mapping[i] & 0xffffffff) |
		       BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
		REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
		       (u64) bp->ctx_blk_mapping[i] >> 32);
		REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
		       BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
		for (j = 0; j < 10; j++) {

			val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
			if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
				break;
			udelay(5);
		}
		if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
			ret = -EBUSY;
			break;
		}
	}
	return ret;
}

2358 2359 2360 2361 2362 2363 2364 2365
static void
bnx2_init_context(struct bnx2 *bp)
{
	u32 vcid;

	vcid = 96;
	while (vcid) {
		u32 vcid_addr, pcid_addr, offset;
2366
		int i;
2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386

		vcid--;

		if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
			u32 new_vcid;

			vcid_addr = GET_PCID_ADDR(vcid);
			if (vcid & 0x8) {
				new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
			}
			else {
				new_vcid = vcid;
			}
			pcid_addr = GET_PCID_ADDR(new_vcid);
		}
		else {
	    		vcid_addr = GET_CID_ADDR(vcid);
			pcid_addr = vcid_addr;
		}

2387 2388 2389
		for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
			vcid_addr += (i << PHY_CTX_SHIFT);
			pcid_addr += (i << PHY_CTX_SHIFT);
2390

2391
			REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2392
			REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2393

2394 2395
			/* Zero out the context. */
			for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
M
Michael Chan 已提交
2396
				bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2397
		}
2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420
	}
}

static int
bnx2_alloc_bad_rbuf(struct bnx2 *bp)
{
	u16 *good_mbuf;
	u32 good_mbuf_cnt;
	u32 val;

	good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
	if (good_mbuf == NULL) {
		printk(KERN_ERR PFX "Failed to allocate memory in "
				    "bnx2_alloc_bad_rbuf\n");
		return -ENOMEM;
	}

	REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
		BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);

	good_mbuf_cnt = 0;

	/* Allocate a bunch of mbufs and save the good ones in an array. */
2421
	val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2422
	while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2423 2424
		bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
				BNX2_RBUF_COMMAND_ALLOC_REQ);
2425

2426
		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2427 2428 2429 2430 2431 2432 2433 2434 2435

		val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;

		/* The addresses with Bit 9 set are bad memory blocks. */
		if (!(val & (1 << 9))) {
			good_mbuf[good_mbuf_cnt] = (u16) val;
			good_mbuf_cnt++;
		}

2436
		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2437 2438 2439 2440 2441 2442 2443 2444 2445 2446
	}

	/* Free the good ones back to the mbuf pool thus discarding
	 * all the bad ones. */
	while (good_mbuf_cnt) {
		good_mbuf_cnt--;

		val = good_mbuf[good_mbuf_cnt];
		val = (val << 9) | val | 1;

2447
		bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2448 2449 2450 2451 2452 2453
	}
	kfree(good_mbuf);
	return 0;
}

static void
2454
bnx2_set_mac_addr(struct bnx2 *bp)
2455 2456 2457 2458 2459 2460 2461 2462
{
	u32 val;
	u8 *mac_addr = bp->dev->dev_addr;

	val = (mac_addr[0] << 8) | mac_addr[1];

	REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);

2463
	val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2464 2465 2466 2467 2468
		(mac_addr[4] << 8) | mac_addr[5];

	REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
}

2469
static inline int
2470
bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2471 2472
{
	dma_addr_t mapping;
2473
	struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2474
	struct rx_bd *rxbd =
2475
		&rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489
	struct page *page = alloc_page(GFP_ATOMIC);

	if (!page)
		return -ENOMEM;
	mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
			       PCI_DMA_FROMDEVICE);
	rx_pg->page = page;
	pci_unmap_addr_set(rx_pg, mapping, mapping);
	rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
	rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
	return 0;
}

static void
2490
bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2491
{
2492
	struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504
	struct page *page = rx_pg->page;

	if (!page)
		return;

	pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
		       PCI_DMA_FROMDEVICE);

	__free_page(page);
	rx_pg->page = NULL;
}

2505
static inline int
2506
bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2507 2508
{
	struct sk_buff *skb;
2509
	struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2510
	dma_addr_t mapping;
2511
	struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2512 2513
	unsigned long align;

2514
	skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2515 2516 2517 2518
	if (skb == NULL) {
		return -ENOMEM;
	}

M
Michael Chan 已提交
2519 2520
	if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
		skb_reserve(skb, BNX2_RX_ALIGN - align);
2521 2522 2523 2524 2525 2526 2527 2528 2529 2530

	mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
		PCI_DMA_FROMDEVICE);

	rx_buf->skb = skb;
	pci_unmap_addr_set(rx_buf, mapping, mapping);

	rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
	rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;

2531
	rxr->rx_prod_bseq += bp->rx_buf_use_size;
2532 2533 2534 2535

	return 0;
}

2536
static int
2537
bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2538
{
2539
	struct status_block *sblk = bnapi->status_blk.msi;
2540
	u32 new_link_state, old_link_state;
2541
	int is_set = 1;
2542

2543 2544
	new_link_state = sblk->status_attn_bits & event;
	old_link_state = sblk->status_attn_bits_ack & event;
2545
	if (new_link_state != old_link_state) {
2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556
		if (new_link_state)
			REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
		else
			REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
	} else
		is_set = 0;

	return is_set;
}

static void
2557
bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2558
{
M
Michael Chan 已提交
2559 2560 2561
	spin_lock(&bp->phy_lock);

	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2562
		bnx2_set_link(bp);
2563
	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2564 2565
		bnx2_set_remote_link(bp);

M
Michael Chan 已提交
2566 2567
	spin_unlock(&bp->phy_lock);

2568 2569
}

2570
static inline u16
2571
bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2572 2573 2574
{
	u16 cons;

2575 2576 2577
	/* Tell compiler that status block fields can change. */
	barrier();
	cons = *bnapi->hw_tx_cons_ptr;
2578 2579 2580 2581 2582
	if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
		cons++;
	return cons;
}

M
Michael Chan 已提交
2583 2584
static int
bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2585
{
2586
	struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2587
	u16 hw_cons, sw_cons, sw_ring_cons;
M
Michael Chan 已提交
2588
	int tx_pkt = 0;
2589

2590
	hw_cons = bnx2_get_hw_tx_cons(bnapi);
2591
	sw_cons = txr->tx_cons;
2592 2593 2594 2595 2596 2597 2598 2599

	while (sw_cons != hw_cons) {
		struct sw_bd *tx_buf;
		struct sk_buff *skb;
		int i, last;

		sw_ring_cons = TX_RING_IDX(sw_cons);

2600
		tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2601
		skb = tx_buf->skb;
A
Arjan van de Ven 已提交
2602

2603
		/* partial BD completions possible with TSO packets */
H
Herbert Xu 已提交
2604
		if (skb_is_gso(skb)) {
2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617
			u16 last_idx, last_ring_idx;

			last_idx = sw_cons +
				skb_shinfo(skb)->nr_frags + 1;
			last_ring_idx = sw_ring_cons +
				skb_shinfo(skb)->nr_frags + 1;
			if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
				last_idx++;
			}
			if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
				break;
			}
		}
A
Arjan van de Ven 已提交
2618

2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629
		pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
			skb_headlen(skb), PCI_DMA_TODEVICE);

		tx_buf->skb = NULL;
		last = skb_shinfo(skb)->nr_frags;

		for (i = 0; i < last; i++) {
			sw_cons = NEXT_TX_BD(sw_cons);

			pci_unmap_page(bp->pdev,
				pci_unmap_addr(
2630
					&txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2631 2632 2633 2634 2635 2636 2637
				       	mapping),
				skb_shinfo(skb)->frags[i].size,
				PCI_DMA_TODEVICE);
		}

		sw_cons = NEXT_TX_BD(sw_cons);

2638
		dev_kfree_skb(skb);
M
Michael Chan 已提交
2639 2640 2641
		tx_pkt++;
		if (tx_pkt == budget)
			break;
2642

2643
		hw_cons = bnx2_get_hw_tx_cons(bnapi);
2644 2645
	}

2646 2647
	txr->hw_tx_cons = hw_cons;
	txr->tx_cons = sw_cons;
M
Michael Chan 已提交
2648 2649 2650 2651 2652 2653
	/* Need to make the tx_cons update visible to bnx2_start_xmit()
	 * before checking for netif_queue_stopped().  Without the
	 * memory barrier, there is a small possibility that bnx2_start_xmit()
	 * will miss it and cause the queue to be stopped forever.
	 */
	smp_mb();
2654

M
Michael Chan 已提交
2655
	if (unlikely(netif_queue_stopped(bp->dev)) &&
2656
		     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
M
Michael Chan 已提交
2657
		netif_tx_lock(bp->dev);
2658
		if ((netif_queue_stopped(bp->dev)) &&
2659
		    (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2660
			netif_wake_queue(bp->dev);
M
Michael Chan 已提交
2661
		netif_tx_unlock(bp->dev);
2662
	}
M
Michael Chan 已提交
2663
	return tx_pkt;
2664 2665
}

2666
static void
2667
bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2668
			struct sk_buff *skb, int count)
2669 2670 2671 2672 2673
{
	struct sw_pg *cons_rx_pg, *prod_rx_pg;
	struct rx_bd *cons_bd, *prod_bd;
	dma_addr_t mapping;
	int i;
2674 2675
	u16 hw_prod = rxr->rx_pg_prod, prod;
	u16 cons = rxr->rx_pg_cons;
2676 2677 2678 2679

	for (i = 0; i < count; i++) {
		prod = RX_PG_RING_IDX(hw_prod);

2680 2681 2682 2683
		prod_rx_pg = &rxr->rx_pg_ring[prod];
		cons_rx_pg = &rxr->rx_pg_ring[cons];
		cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
		prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711

		if (i == 0 && skb) {
			struct page *page;
			struct skb_shared_info *shinfo;

			shinfo = skb_shinfo(skb);
			shinfo->nr_frags--;
			page = shinfo->frags[shinfo->nr_frags].page;
			shinfo->frags[shinfo->nr_frags].page = NULL;
			mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
					       PCI_DMA_FROMDEVICE);
			cons_rx_pg->page = page;
			pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
			dev_kfree_skb(skb);
		}
		if (prod != cons) {
			prod_rx_pg->page = cons_rx_pg->page;
			cons_rx_pg->page = NULL;
			pci_unmap_addr_set(prod_rx_pg, mapping,
				pci_unmap_addr(cons_rx_pg, mapping));

			prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
			prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;

		}
		cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
		hw_prod = NEXT_RX_BD(hw_prod);
	}
2712 2713
	rxr->rx_pg_prod = hw_prod;
	rxr->rx_pg_cons = cons;
2714 2715
}

2716
static inline void
2717 2718
bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
		  struct sk_buff *skb, u16 cons, u16 prod)
2719
{
2720 2721 2722
	struct sw_bd *cons_rx_buf, *prod_rx_buf;
	struct rx_bd *cons_bd, *prod_bd;

2723 2724
	cons_rx_buf = &rxr->rx_buf_ring[cons];
	prod_rx_buf = &rxr->rx_buf_ring[prod];
2725 2726 2727

	pci_dma_sync_single_for_device(bp->pdev,
		pci_unmap_addr(cons_rx_buf, mapping),
2728
		BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2729

2730
	rxr->rx_prod_bseq += bp->rx_buf_use_size;
2731

2732
	prod_rx_buf->skb = skb;
2733

2734 2735
	if (cons == prod)
		return;
2736

2737 2738 2739
	pci_unmap_addr_set(prod_rx_buf, mapping,
			pci_unmap_addr(cons_rx_buf, mapping));

2740 2741
	cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
	prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2742 2743
	prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
	prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2744 2745
}

2746
static int
2747
bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2748 2749
	    unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
	    u32 ring_idx)
2750 2751 2752 2753
{
	int err;
	u16 prod = ring_idx & 0xffff;

2754
	err = bnx2_alloc_rx_skb(bp, rxr, prod);
2755
	if (unlikely(err)) {
2756
		bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2757 2758 2759 2760
		if (hdr_len) {
			unsigned int raw_len = len + 4;
			int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;

2761
			bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2762
		}
2763 2764 2765
		return err;
	}

2766
	skb_reserve(skb, BNX2_RX_OFFSET);
2767 2768 2769
	pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
			 PCI_DMA_FROMDEVICE);

2770 2771 2772 2773 2774 2775
	if (hdr_len == 0) {
		skb_put(skb, len);
		return 0;
	} else {
		unsigned int i, frag_len, frag_size, pages;
		struct sw_pg *rx_pg;
2776 2777
		u16 pg_cons = rxr->rx_pg_cons;
		u16 pg_prod = rxr->rx_pg_prod;
2778 2779 2780 2781 2782 2783 2784 2785 2786 2787

		frag_size = len + 4 - hdr_len;
		pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
		skb_put(skb, hdr_len);

		for (i = 0; i < pages; i++) {
			frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
			if (unlikely(frag_len <= 4)) {
				unsigned int tail = 4 - frag_len;

2788 2789 2790
				rxr->rx_pg_cons = pg_cons;
				rxr->rx_pg_prod = pg_prod;
				bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2791
							pages - i);
2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803
				skb->len -= tail;
				if (i == 0) {
					skb->tail -= tail;
				} else {
					skb_frag_t *frag =
						&skb_shinfo(skb)->frags[i - 1];
					frag->size -= tail;
					skb->data_len -= tail;
					skb->truesize -= tail;
				}
				return 0;
			}
2804
			rx_pg = &rxr->rx_pg_ring[pg_cons];
2805 2806 2807 2808 2809 2810 2811 2812 2813 2814

			pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
				       PAGE_SIZE, PCI_DMA_FROMDEVICE);

			if (i == pages - 1)
				frag_len -= 4;

			skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
			rx_pg->page = NULL;

2815 2816
			err = bnx2_alloc_rx_page(bp, rxr,
						 RX_PG_RING_IDX(pg_prod));
2817
			if (unlikely(err)) {
2818 2819 2820
				rxr->rx_pg_cons = pg_cons;
				rxr->rx_pg_prod = pg_prod;
				bnx2_reuse_rx_skb_pages(bp, rxr, skb,
2821
							pages - i);
2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832
				return err;
			}

			frag_size -= frag_len;
			skb->data_len += frag_len;
			skb->truesize += frag_len;
			skb->len += frag_len;

			pg_prod = NEXT_RX_BD(pg_prod);
			pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
		}
2833 2834
		rxr->rx_pg_prod = pg_prod;
		rxr->rx_pg_cons = pg_cons;
2835
	}
2836 2837 2838
	return 0;
}

M
Michael Chan 已提交
2839
static inline u16
2840
bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
M
Michael Chan 已提交
2841
{
2842 2843
	u16 cons;

2844 2845 2846
	/* Tell compiler that status block fields can change. */
	barrier();
	cons = *bnapi->hw_rx_cons_ptr;
M
Michael Chan 已提交
2847 2848 2849 2850 2851
	if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
		cons++;
	return cons;
}

2852
static int
2853
bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2854
{
2855
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2856 2857
	u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
	struct l2_fhdr *rx_hdr;
2858
	int rx_pkt = 0, pg_ring_used = 0;
2859

2860
	hw_cons = bnx2_get_hw_rx_cons(bnapi);
2861 2862
	sw_cons = rxr->rx_cons;
	sw_prod = rxr->rx_prod;
2863 2864 2865 2866 2867 2868

	/* Memory barrier necessary as speculative reads of the rx
	 * buffer can be ahead of the index in the status block
	 */
	rmb();
	while (sw_cons != hw_cons) {
2869
		unsigned int len, hdr_len;
2870
		u32 status;
2871 2872
		struct sw_bd *rx_buf;
		struct sk_buff *skb;
2873
		dma_addr_t dma_addr;
2874 2875 2876 2877

		sw_ring_cons = RX_RING_IDX(sw_cons);
		sw_ring_prod = RX_RING_IDX(sw_prod);

2878
		rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
2879
		skb = rx_buf->skb;
2880 2881 2882 2883 2884 2885

		rx_buf->skb = NULL;

		dma_addr = pci_unmap_addr(rx_buf, mapping);

		pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2886 2887
			BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
			PCI_DMA_FROMDEVICE);
2888 2889

		rx_hdr = (struct l2_fhdr *) skb->data;
2890
		len = rx_hdr->l2_fhdr_pkt_len;
2891

2892
		if ((status = rx_hdr->l2_fhdr_status) &
2893 2894 2895 2896 2897 2898
			(L2_FHDR_ERRORS_BAD_CRC |
			L2_FHDR_ERRORS_PHY_DECODE |
			L2_FHDR_ERRORS_ALIGNMENT |
			L2_FHDR_ERRORS_TOO_SHORT |
			L2_FHDR_ERRORS_GIANT_FRAME)) {

2899
			bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2900
					  sw_ring_prod);
2901
			goto next_rx;
2902
		}
2903 2904 2905 2906 2907 2908 2909 2910 2911 2912
		hdr_len = 0;
		if (status & L2_FHDR_STATUS_SPLIT) {
			hdr_len = rx_hdr->l2_fhdr_ip_xsum;
			pg_ring_used = 1;
		} else if (len > bp->rx_jumbo_thresh) {
			hdr_len = bp->rx_jumbo_thresh;
			pg_ring_used = 1;
		}

		len -= 4;
2913

2914
		if (len <= bp->rx_copy_thresh) {
2915 2916
			struct sk_buff *new_skb;

2917
			new_skb = netdev_alloc_skb(bp->dev, len + 2);
2918
			if (new_skb == NULL) {
2919
				bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2920 2921 2922
						  sw_ring_prod);
				goto next_rx;
			}
2923 2924

			/* aligned copy */
2925 2926
			skb_copy_from_linear_data_offset(skb,
							 BNX2_RX_OFFSET - 2,
2927
				      new_skb->data, len + 2);
2928 2929 2930
			skb_reserve(new_skb, 2);
			skb_put(new_skb, len);

2931
			bnx2_reuse_rx_skb(bp, rxr, skb,
2932 2933 2934
				sw_ring_cons, sw_ring_prod);

			skb = new_skb;
2935
		} else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
2936
			   dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2937 2938 2939 2940 2941
			goto next_rx;

		skb->protocol = eth_type_trans(skb, bp->dev);

		if ((len > (bp->dev->mtu + ETH_HLEN)) &&
A
Alexey Dobriyan 已提交
2942
			(ntohs(skb->protocol) != 0x8100)) {
2943

2944
			dev_kfree_skb(skb);
2945 2946 2947 2948 2949 2950 2951 2952 2953
			goto next_rx;

		}

		skb->ip_summed = CHECKSUM_NONE;
		if (bp->rx_csum &&
			(status & (L2_FHDR_STATUS_TCP_SEGMENT |
			L2_FHDR_STATUS_UDP_DATAGRAM))) {

2954 2955
			if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
					      L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2956 2957 2958 2959
				skb->ip_summed = CHECKSUM_UNNECESSARY;
		}

#ifdef BCM_VLAN
A
Al Viro 已提交
2960
		if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && bp->vlgrp) {
2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976
			vlan_hwaccel_receive_skb(skb, bp->vlgrp,
				rx_hdr->l2_fhdr_vlan_tag);
		}
		else
#endif
			netif_receive_skb(skb);

		bp->dev->last_rx = jiffies;
		rx_pkt++;

next_rx:
		sw_cons = NEXT_RX_BD(sw_cons);
		sw_prod = NEXT_RX_BD(sw_prod);

		if ((rx_pkt == budget))
			break;
M
Michael Chan 已提交
2977 2978 2979

		/* Refresh hw_cons to see if there is new work */
		if (sw_cons == hw_cons) {
2980
			hw_cons = bnx2_get_hw_rx_cons(bnapi);
M
Michael Chan 已提交
2981 2982
			rmb();
		}
2983
	}
2984 2985
	rxr->rx_cons = sw_cons;
	rxr->rx_prod = sw_prod;
2986

2987
	if (pg_ring_used)
2988
		REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
2989

2990
	REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
2991

2992
	REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003

	mmiowb();

	return rx_pkt;

}

/* MSI ISR - The only difference between this and the INTx ISR
 * is that the MSI interrupt is always serviced.
 */
static irqreturn_t
3004
bnx2_msi(int irq, void *dev_instance)
3005
{
3006 3007 3008
	struct bnx2_napi *bnapi = dev_instance;
	struct bnx2 *bp = bnapi->bp;
	struct net_device *dev = bp->dev;
3009

3010
	prefetch(bnapi->status_blk.msi);
3011 3012 3013 3014 3015
	REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
		BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
		BNX2_PCICFG_INT_ACK_CMD_MASK_INT);

	/* Return here if interrupt is disabled. */
3016 3017
	if (unlikely(atomic_read(&bp->intr_sem) != 0))
		return IRQ_HANDLED;
3018

3019
	netif_rx_schedule(dev, &bnapi->napi);
3020

3021
	return IRQ_HANDLED;
3022 3023
}

3024 3025 3026
static irqreturn_t
bnx2_msi_1shot(int irq, void *dev_instance)
{
3027 3028 3029
	struct bnx2_napi *bnapi = dev_instance;
	struct bnx2 *bp = bnapi->bp;
	struct net_device *dev = bp->dev;
3030

3031
	prefetch(bnapi->status_blk.msi);
3032 3033 3034 3035 3036

	/* Return here if interrupt is disabled. */
	if (unlikely(atomic_read(&bp->intr_sem) != 0))
		return IRQ_HANDLED;

3037
	netif_rx_schedule(dev, &bnapi->napi);
3038 3039 3040 3041

	return IRQ_HANDLED;
}

3042
static irqreturn_t
3043
bnx2_interrupt(int irq, void *dev_instance)
3044
{
3045 3046 3047
	struct bnx2_napi *bnapi = dev_instance;
	struct bnx2 *bp = bnapi->bp;
	struct net_device *dev = bp->dev;
3048
	struct status_block *sblk = bnapi->status_blk.msi;
3049 3050 3051 3052 3053 3054 3055

	/* When using INTx, it is possible for the interrupt to arrive
	 * at the CPU before the status block posted prior to the
	 * interrupt. Reading a register will flush the status block.
	 * When using MSI, the MSI message will always complete after
	 * the status block write.
	 */
3056
	if ((sblk->status_idx == bnapi->last_status_idx) &&
3057 3058
	    (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
	     BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3059
		return IRQ_NONE;
3060 3061 3062 3063 3064

	REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
		BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
		BNX2_PCICFG_INT_ACK_CMD_MASK_INT);

3065 3066 3067 3068 3069
	/* Read back to deassert IRQ immediately to avoid too many
	 * spurious interrupts.
	 */
	REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);

3070
	/* Return here if interrupt is shared and is disabled. */
3071 3072
	if (unlikely(atomic_read(&bp->intr_sem) != 0))
		return IRQ_HANDLED;
3073

3074 3075 3076
	if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
		bnapi->last_status_idx = sblk->status_idx;
		__netif_rx_schedule(dev, &bnapi->napi);
3077
	}
3078

3079
	return IRQ_HANDLED;
3080 3081
}

M
Michael Chan 已提交
3082
static inline int
3083
bnx2_has_fast_work(struct bnx2_napi *bnapi)
M
Michael Chan 已提交
3084
{
3085
	struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3086
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
M
Michael Chan 已提交
3087

3088
	if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3089
	    (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
M
Michael Chan 已提交
3090
		return 1;
3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103
	return 0;
}

#define STATUS_ATTN_EVENTS	(STATUS_ATTN_BITS_LINK_STATE | \
				 STATUS_ATTN_BITS_TIMER_ABORT)

static inline int
bnx2_has_work(struct bnx2_napi *bnapi)
{
	struct status_block *sblk = bnapi->status_blk.msi;

	if (bnx2_has_fast_work(bnapi))
		return 1;
M
Michael Chan 已提交
3104

3105 3106
	if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
	    (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
M
Michael Chan 已提交
3107 3108 3109 3110 3111
		return 1;

	return 0;
}

3112
static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3113
{
3114
	struct status_block *sblk = bnapi->status_blk.msi;
3115 3116
	u32 status_attn_bits = sblk->status_attn_bits;
	u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3117

3118 3119
	if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
	    (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3120

3121
		bnx2_phy_int(bp, bnapi);
M
Michael Chan 已提交
3122 3123 3124 3125 3126 3127 3128

		/* This is needed to take care of transient status
		 * during link changes.
		 */
		REG_WR(bp, BNX2_HC_COMMAND,
		       bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
		REG_RD(bp, BNX2_HC_COMMAND);
3129
	}
3130 3131 3132 3133 3134 3135 3136
}

static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
			  int work_done, int budget)
{
	struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3137

3138
	if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
M
Michael Chan 已提交
3139
		bnx2_tx_int(bp, bnapi, 0);
3140

3141
	if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3142
		work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3143

3144 3145 3146
	return work_done;
}

3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173
static int bnx2_poll_msix(struct napi_struct *napi, int budget)
{
	struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
	struct bnx2 *bp = bnapi->bp;
	int work_done = 0;
	struct status_block_msix *sblk = bnapi->status_blk.msix;

	while (1) {
		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
		if (unlikely(work_done >= budget))
			break;

		bnapi->last_status_idx = sblk->status_idx;
		/* status idx must be read before checking for more work. */
		rmb();
		if (likely(!bnx2_has_fast_work(bnapi))) {

			netif_rx_complete(bp->dev, napi);
			REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
			       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
			       bnapi->last_status_idx);
			break;
		}
	}
	return work_done;
}

3174 3175
static int bnx2_poll(struct napi_struct *napi, int budget)
{
3176 3177
	struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
	struct bnx2 *bp = bnapi->bp;
3178
	int work_done = 0;
3179
	struct status_block *sblk = bnapi->status_blk.msi;
3180 3181

	while (1) {
3182 3183
		bnx2_poll_link(bp, bnapi);

3184
		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
M
Michael Chan 已提交
3185

3186 3187 3188
		if (unlikely(work_done >= budget))
			break;

3189
		/* bnapi->last_status_idx is used below to tell the hw how
M
Michael Chan 已提交
3190 3191 3192
		 * much work has been processed, so we must read it before
		 * checking for more work.
		 */
3193
		bnapi->last_status_idx = sblk->status_idx;
M
Michael Chan 已提交
3194
		rmb();
3195
		if (likely(!bnx2_has_work(bnapi))) {
3196
			netif_rx_complete(bp->dev, napi);
3197
			if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3198 3199
				REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
				       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3200
				       bnapi->last_status_idx);
M
Michael Chan 已提交
3201
				break;
3202
			}
3203 3204
			REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
			       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3205
			       BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3206
			       bnapi->last_status_idx);
3207

3208 3209
			REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
			       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3210
			       bnapi->last_status_idx);
3211 3212
			break;
		}
3213 3214
	}

3215
	return work_done;
3216 3217
}

H
Herbert Xu 已提交
3218
/* Called with rtnl_lock from vlan functions and also netif_tx_lock
3219 3220 3221 3222 3223
 * from set_multicast.
 */
static void
bnx2_set_rx_mode(struct net_device *dev)
{
M
Michael Chan 已提交
3224
	struct bnx2 *bp = netdev_priv(dev);
3225 3226 3227
	u32 rx_mode, sort_mode;
	int i;

3228
	spin_lock_bh(&bp->phy_lock);
3229 3230 3231 3232 3233

	rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
				  BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
	sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
#ifdef BCM_VLAN
3234
	if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE))
3235 3236
		rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
#else
3237
	if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
M
Michael Chan 已提交
3238
		rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3239 3240 3241 3242
#endif
	if (dev->flags & IFF_PROMISC) {
		/* Promiscuous mode. */
		rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
M
Michael Chan 已提交
3243 3244
		sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
			     BNX2_RPM_SORT_USER0_PROM_VLAN;
3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289
	}
	else if (dev->flags & IFF_ALLMULTI) {
		for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
			REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
			       0xffffffff);
        	}
		sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
	}
	else {
		/* Accept one or more multicast(s). */
		struct dev_mc_list *mclist;
		u32 mc_filter[NUM_MC_HASH_REGISTERS];
		u32 regidx;
		u32 bit;
		u32 crc;

		memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);

		for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
		     i++, mclist = mclist->next) {

			crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
			bit = crc & 0xff;
			regidx = (bit & 0xe0) >> 5;
			bit &= 0x1f;
			mc_filter[regidx] |= (1 << bit);
		}

		for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
			REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
			       mc_filter[i]);
		}

		sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
	}

	if (rx_mode != bp->rx_mode) {
		bp->rx_mode = rx_mode;
		REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
	}

	REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
	REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
	REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);

3290
	spin_unlock_bh(&bp->phy_lock);
3291 3292 3293
}

static void
A
Al Viro 已提交
3294
load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3295 3296 3297 3298 3299
	u32 rv2p_proc)
{
	int i;
	u32 val;

3300 3301 3302 3303 3304 3305
	if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
		val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
		val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
		val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
		rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
	}
3306 3307

	for (i = 0; i < rv2p_code_len; i += 8) {
A
Al Viro 已提交
3308
		REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3309
		rv2p_code++;
A
Al Viro 已提交
3310
		REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331
		rv2p_code++;

		if (rv2p_proc == RV2P_PROC1) {
			val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
			REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
		}
		else {
			val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
			REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
		}
	}

	/* Reset the processor, un-stall is done later. */
	if (rv2p_proc == RV2P_PROC1) {
		REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
	}
	else {
		REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
	}
}

3332
static int
3333
load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
3334 3335 3336
{
	u32 offset;
	u32 val;
3337
	int rc;
3338 3339

	/* Halt the CPU. */
3340
	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3341
	val |= cpu_reg->mode_value_halt;
3342 3343
	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3344 3345 3346

	/* Load the Text area. */
	offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3347
	if (fw->gz_text) {
3348 3349
		int j;

M
Michael Chan 已提交
3350 3351 3352
		rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
				       fw->gz_text_len);
		if (rc < 0)
D
Denys Vlasenko 已提交
3353
			return rc;
M
Michael Chan 已提交
3354

3355
		for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3356
			bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3357 3358 3359 3360 3361 3362 3363 3364 3365
	        }
	}

	/* Load the Data area. */
	offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
	if (fw->data) {
		int j;

		for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3366
			bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3367 3368 3369 3370 3371
		}
	}

	/* Load the SBSS area. */
	offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
M
Michael Chan 已提交
3372
	if (fw->sbss_len) {
3373 3374 3375
		int j;

		for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3376
			bnx2_reg_wr_ind(bp, offset, 0);
3377 3378 3379 3380 3381
		}
	}

	/* Load the BSS area. */
	offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
M
Michael Chan 已提交
3382
	if (fw->bss_len) {
3383 3384 3385
		int j;

		for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3386
			bnx2_reg_wr_ind(bp, offset, 0);
3387 3388 3389 3390 3391 3392 3393 3394 3395 3396
		}
	}

	/* Load the Read-Only area. */
	offset = cpu_reg->spad_base +
		(fw->rodata_addr - cpu_reg->mips_view_base);
	if (fw->rodata) {
		int j;

		for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3397
			bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3398 3399 3400 3401
		}
	}

	/* Clear the pre-fetch instruction. */
3402 3403
	bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
	bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3404 3405

	/* Start the CPU. */
3406
	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3407
	val &= ~cpu_reg->mode_value_halt;
3408 3409
	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3410 3411

	return 0;
3412 3413
}

3414
static int
3415 3416
bnx2_init_cpus(struct bnx2 *bp)
{
3417
	struct fw_info *fw;
3418 3419
	int rc, rv2p_len;
	void *text, *rv2p;
3420 3421

	/* Initialize the RV2P processor. */
D
Denys Vlasenko 已提交
3422 3423 3424
	text = vmalloc(FW_BUF_SIZE);
	if (!text)
		return -ENOMEM;
3425 3426 3427 3428 3429 3430 3431 3432
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		rv2p = bnx2_xi_rv2p_proc1;
		rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
	} else {
		rv2p = bnx2_rv2p_proc1;
		rv2p_len = sizeof(bnx2_rv2p_proc1);
	}
	rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
M
Michael Chan 已提交
3433
	if (rc < 0)
3434
		goto init_cpu_err;
M
Michael Chan 已提交
3435

D
Denys Vlasenko 已提交
3436
	load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3437

3438 3439 3440 3441 3442 3443 3444 3445
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		rv2p = bnx2_xi_rv2p_proc2;
		rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
	} else {
		rv2p = bnx2_rv2p_proc2;
		rv2p_len = sizeof(bnx2_rv2p_proc2);
	}
	rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
M
Michael Chan 已提交
3446
	if (rc < 0)
3447
		goto init_cpu_err;
M
Michael Chan 已提交
3448

D
Denys Vlasenko 已提交
3449
	load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3450 3451

	/* Initialize the RX Processor. */
M
Michael Chan 已提交
3452 3453 3454 3455
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		fw = &bnx2_rxp_fw_09;
	else
		fw = &bnx2_rxp_fw_06;
3456

M
Michael Chan 已提交
3457
	fw->text = text;
3458
	rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
3459 3460 3461
	if (rc)
		goto init_cpu_err;

3462
	/* Initialize the TX Processor. */
M
Michael Chan 已提交
3463 3464 3465 3466
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		fw = &bnx2_txp_fw_09;
	else
		fw = &bnx2_txp_fw_06;
3467

M
Michael Chan 已提交
3468
	fw->text = text;
3469
	rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
3470 3471 3472
	if (rc)
		goto init_cpu_err;

3473
	/* Initialize the TX Patch-up Processor. */
M
Michael Chan 已提交
3474 3475 3476 3477
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		fw = &bnx2_tpat_fw_09;
	else
		fw = &bnx2_tpat_fw_06;
3478

M
Michael Chan 已提交
3479
	fw->text = text;
3480
	rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
3481 3482 3483
	if (rc)
		goto init_cpu_err;

3484
	/* Initialize the Completion Processor. */
M
Michael Chan 已提交
3485 3486 3487 3488
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		fw = &bnx2_com_fw_09;
	else
		fw = &bnx2_com_fw_06;
3489

M
Michael Chan 已提交
3490
	fw->text = text;
3491
	rc = load_cpu_fw(bp, &cpu_reg_com, fw);
3492 3493 3494
	if (rc)
		goto init_cpu_err;

M
Michael Chan 已提交
3495
	/* Initialize the Command Processor. */
3496
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
M
Michael Chan 已提交
3497
		fw = &bnx2_cp_fw_09;
3498 3499 3500 3501
	else
		fw = &bnx2_cp_fw_06;

	fw->text = text;
3502
	rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
3503

3504
init_cpu_err:
M
Michael Chan 已提交
3505
	vfree(text);
3506
	return rc;
3507 3508 3509
}

static int
3510
bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3511 3512 3513 3514 3515 3516
{
	u16 pmcsr;

	pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);

	switch (state) {
3517
	case PCI_D0: {
3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537
		u32 val;

		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
			(pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
			PCI_PM_CTRL_PME_STATUS);

		if (pmcsr & PCI_PM_CTRL_STATE_MASK)
			/* delay required during transition out of D3hot */
			msleep(20);

		val = REG_RD(bp, BNX2_EMAC_MODE);
		val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
		val &= ~BNX2_EMAC_MODE_MPKT;
		REG_WR(bp, BNX2_EMAC_MODE, val);

		val = REG_RD(bp, BNX2_RPM_CONFIG);
		val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
		REG_WR(bp, BNX2_RPM_CONFIG, val);
		break;
	}
3538
	case PCI_D3hot: {
3539 3540 3541 3542 3543 3544 3545 3546 3547 3548
		int i;
		u32 val, wol_msg;

		if (bp->wol) {
			u32 advertising;
			u8 autoneg;

			autoneg = bp->autoneg;
			advertising = bp->advertising;

M
Michael Chan 已提交
3549 3550 3551 3552 3553 3554 3555 3556
			if (bp->phy_port == PORT_TP) {
				bp->autoneg = AUTONEG_SPEED;
				bp->advertising = ADVERTISED_10baseT_Half |
					ADVERTISED_10baseT_Full |
					ADVERTISED_100baseT_Half |
					ADVERTISED_100baseT_Full |
					ADVERTISED_Autoneg;
			}
3557

M
Michael Chan 已提交
3558 3559 3560
			spin_lock_bh(&bp->phy_lock);
			bnx2_setup_phy(bp, bp->phy_port);
			spin_unlock_bh(&bp->phy_lock);
3561 3562 3563 3564 3565 3566 3567 3568 3569 3570

			bp->autoneg = autoneg;
			bp->advertising = advertising;

			bnx2_set_mac_addr(bp);

			val = REG_RD(bp, BNX2_EMAC_MODE);

			/* Enable port mode. */
			val &= ~BNX2_EMAC_MODE_PORT;
M
Michael Chan 已提交
3571
			val |= BNX2_EMAC_MODE_MPKT_RCVD |
3572 3573
			       BNX2_EMAC_MODE_ACPI_RCVD |
			       BNX2_EMAC_MODE_MPKT;
M
Michael Chan 已提交
3574 3575 3576 3577 3578 3579 3580
			if (bp->phy_port == PORT_TP)
				val |= BNX2_EMAC_MODE_PORT_MII;
			else {
				val |= BNX2_EMAC_MODE_PORT_GMII;
				if (bp->line_speed == SPEED_2500)
					val |= BNX2_EMAC_MODE_25G_MODE;
			}
3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614

			REG_WR(bp, BNX2_EMAC_MODE, val);

			/* receive all multicast */
			for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
				REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
				       0xffffffff);
			}
			REG_WR(bp, BNX2_EMAC_RX_MODE,
			       BNX2_EMAC_RX_MODE_SORT_MODE);

			val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
			      BNX2_RPM_SORT_USER0_MC_EN;
			REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
			REG_WR(bp, BNX2_RPM_SORT_USER0, val);
			REG_WR(bp, BNX2_RPM_SORT_USER0, val |
			       BNX2_RPM_SORT_USER0_ENA);

			/* Need to enable EMAC and RPM for WOL. */
			REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
			       BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
			       BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
			       BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);

			val = REG_RD(bp, BNX2_RPM_CONFIG);
			val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
			REG_WR(bp, BNX2_RPM_CONFIG, val);

			wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
		}
		else {
			wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
		}

3615
		if (!(bp->flags & BNX2_FLAG_NO_WOL))
3616 3617
			bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
				     1, 0);
3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700

		pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
		if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
		    (CHIP_ID(bp) == CHIP_ID_5706_A1)) {

			if (bp->wol)
				pmcsr |= 3;
		}
		else {
			pmcsr |= 3;
		}
		if (bp->wol) {
			pmcsr |= PCI_PM_CTRL_PME_ENABLE;
		}
		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
				      pmcsr);

		/* No more memory access after this point until
		 * device is brought back to D0.
		 */
		udelay(50);
		break;
	}
	default:
		return -EINVAL;
	}
	return 0;
}

static int
bnx2_acquire_nvram_lock(struct bnx2 *bp)
{
	u32 val;
	int j;

	/* Request access to the flash interface. */
	REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		val = REG_RD(bp, BNX2_NVM_SW_ARB);
		if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
			break;

		udelay(5);
	}

	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}

static int
bnx2_release_nvram_lock(struct bnx2 *bp)
{
	int j;
	u32 val;

	/* Relinquish nvram interface. */
	REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);

	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		val = REG_RD(bp, BNX2_NVM_SW_ARB);
		if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
			break;

		udelay(5);
	}

	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}


static int
bnx2_enable_nvram_write(struct bnx2 *bp)
{
	u32 val;

	val = REG_RD(bp, BNX2_MISC_CFG);
	REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);

M
Michael Chan 已提交
3701
	if (bp->flash_info->flags & BNX2_NV_WREN) {
3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738
		int j;

		REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
		REG_WR(bp, BNX2_NVM_COMMAND,
		       BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);

		for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
			udelay(5);

			val = REG_RD(bp, BNX2_NVM_COMMAND);
			if (val & BNX2_NVM_COMMAND_DONE)
				break;
		}

		if (j >= NVRAM_TIMEOUT_COUNT)
			return -EBUSY;
	}
	return 0;
}

static void
bnx2_disable_nvram_write(struct bnx2 *bp)
{
	u32 val;

	val = REG_RD(bp, BNX2_MISC_CFG);
	REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
}


static void
bnx2_enable_nvram_access(struct bnx2 *bp)
{
	u32 val;

	val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
	/* Enable both bits, even on read. */
3739
	REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3740 3741 3742 3743 3744 3745 3746 3747 3748 3749
	       val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
}

static void
bnx2_disable_nvram_access(struct bnx2 *bp)
{
	u32 val;

	val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
	/* Disable both bits, even after read. */
3750
	REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3751 3752 3753 3754 3755 3756 3757 3758 3759 3760
		val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
			BNX2_NVM_ACCESS_ENABLE_WR_EN));
}

static int
bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
{
	u32 cmd;
	int j;

M
Michael Chan 已提交
3761
	if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803
		/* Buffered flash, no erase needed */
		return 0;

	/* Build an erase command */
	cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
	      BNX2_NVM_COMMAND_DOIT;

	/* Need to clear DONE bit separately. */
	REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);

	/* Address of the NVRAM to read from. */
	REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);

	/* Issue an erase command. */
	REG_WR(bp, BNX2_NVM_COMMAND, cmd);

	/* Wait for completion. */
	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		u32 val;

		udelay(5);

		val = REG_RD(bp, BNX2_NVM_COMMAND);
		if (val & BNX2_NVM_COMMAND_DONE)
			break;
	}

	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}

static int
bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
{
	u32 cmd;
	int j;

	/* Build the command word. */
	cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;

M
Michael Chan 已提交
3804 3805
	/* Calculate an offset of a buffered flash, not needed for 5709. */
	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827
		offset = ((offset / bp->flash_info->page_size) <<
			   bp->flash_info->page_bits) +
			  (offset % bp->flash_info->page_size);
	}

	/* Need to clear DONE bit separately. */
	REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);

	/* Address of the NVRAM to read from. */
	REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);

	/* Issue a read command. */
	REG_WR(bp, BNX2_NVM_COMMAND, cmd);

	/* Wait for completion. */
	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		u32 val;

		udelay(5);

		val = REG_RD(bp, BNX2_NVM_COMMAND);
		if (val & BNX2_NVM_COMMAND_DONE) {
A
Al Viro 已提交
3828 3829
			__be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
			memcpy(ret_val, &v, 4);
3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842
			break;
		}
	}
	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}


static int
bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
{
A
Al Viro 已提交
3843 3844
	u32 cmd;
	__be32 val32;
3845 3846 3847 3848 3849
	int j;

	/* Build the command word. */
	cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;

M
Michael Chan 已提交
3850 3851
	/* Calculate an offset of a buffered flash, not needed for 5709. */
	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862
		offset = ((offset / bp->flash_info->page_size) <<
			  bp->flash_info->page_bits) +
			 (offset % bp->flash_info->page_size);
	}

	/* Need to clear DONE bit separately. */
	REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);

	memcpy(&val32, val, 4);

	/* Write the data. */
A
Al Viro 已提交
3863
	REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887

	/* Address of the NVRAM to write to. */
	REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);

	/* Issue the write command. */
	REG_WR(bp, BNX2_NVM_COMMAND, cmd);

	/* Wait for completion. */
	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		udelay(5);

		if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
			break;
	}
	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}

static int
bnx2_init_nvram(struct bnx2 *bp)
{
	u32 val;
M
Michael Chan 已提交
3888
	int j, entry_count, rc = 0;
3889 3890
	struct flash_spec *flash;

M
Michael Chan 已提交
3891 3892 3893 3894 3895
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		bp->flash_info = &flash_5709;
		goto get_flash_size;
	}

3896 3897 3898
	/* Determine the selected interface. */
	val = REG_RD(bp, BNX2_NVM_CFG1);

3899
	entry_count = ARRAY_SIZE(flash_table);
3900 3901 3902 3903 3904

	if (val & 0x40000000) {

		/* Flash interface has been reconfigured */
		for (j = 0, flash = &flash_table[0]; j < entry_count;
3905 3906 3907
		     j++, flash++) {
			if ((val & FLASH_BACKUP_STRAP_MASK) ==
			    (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3908 3909 3910 3911 3912 3913
				bp->flash_info = flash;
				break;
			}
		}
	}
	else {
3914
		u32 mask;
3915 3916
		/* Not yet been reconfigured */

3917 3918 3919 3920 3921
		if (val & (1 << 23))
			mask = FLASH_BACKUP_STRAP_MASK;
		else
			mask = FLASH_STRAP_MASK;

3922 3923 3924
		for (j = 0, flash = &flash_table[0]; j < entry_count;
			j++, flash++) {

3925
			if ((val & mask) == (flash->strapping & mask)) {
3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951
				bp->flash_info = flash;

				/* Request access to the flash interface. */
				if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
					return rc;

				/* Enable access to flash interface */
				bnx2_enable_nvram_access(bp);

				/* Reconfigure the flash interface */
				REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
				REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
				REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
				REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);

				/* Disable access to flash interface */
				bnx2_disable_nvram_access(bp);
				bnx2_release_nvram_lock(bp);

				break;
			}
		}
	} /* if (val & 0x40000000) */

	if (j == entry_count) {
		bp->flash_info = NULL;
3952
		printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
M
Michael Chan 已提交
3953
		return -ENODEV;
3954 3955
	}

M
Michael Chan 已提交
3956
get_flash_size:
3957
	val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
M
Michael Chan 已提交
3958 3959 3960 3961 3962 3963
	val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
	if (val)
		bp->flash_size = val;
	else
		bp->flash_size = bp->flash_info->total_size;

3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081
	return rc;
}

static int
bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
		int buf_size)
{
	int rc = 0;
	u32 cmd_flags, offset32, len32, extra;

	if (buf_size == 0)
		return 0;

	/* Request access to the flash interface. */
	if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
		return rc;

	/* Enable access to flash interface */
	bnx2_enable_nvram_access(bp);

	len32 = buf_size;
	offset32 = offset;
	extra = 0;

	cmd_flags = 0;

	if (offset32 & 3) {
		u8 buf[4];
		u32 pre_len;

		offset32 &= ~3;
		pre_len = 4 - (offset & 3);

		if (pre_len >= len32) {
			pre_len = len32;
			cmd_flags = BNX2_NVM_COMMAND_FIRST |
				    BNX2_NVM_COMMAND_LAST;
		}
		else {
			cmd_flags = BNX2_NVM_COMMAND_FIRST;
		}

		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);

		if (rc)
			return rc;

		memcpy(ret_buf, buf + (offset & 3), pre_len);

		offset32 += 4;
		ret_buf += pre_len;
		len32 -= pre_len;
	}
	if (len32 & 3) {
		extra = 4 - (len32 & 3);
		len32 = (len32 + 4) & ~3;
	}

	if (len32 == 4) {
		u8 buf[4];

		if (cmd_flags)
			cmd_flags = BNX2_NVM_COMMAND_LAST;
		else
			cmd_flags = BNX2_NVM_COMMAND_FIRST |
				    BNX2_NVM_COMMAND_LAST;

		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);

		memcpy(ret_buf, buf, 4 - extra);
	}
	else if (len32 > 0) {
		u8 buf[4];

		/* Read the first word. */
		if (cmd_flags)
			cmd_flags = 0;
		else
			cmd_flags = BNX2_NVM_COMMAND_FIRST;

		rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);

		/* Advance to the next dword. */
		offset32 += 4;
		ret_buf += 4;
		len32 -= 4;

		while (len32 > 4 && rc == 0) {
			rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);

			/* Advance to the next dword. */
			offset32 += 4;
			ret_buf += 4;
			len32 -= 4;
		}

		if (rc)
			return rc;

		cmd_flags = BNX2_NVM_COMMAND_LAST;
		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);

		memcpy(ret_buf, buf, 4 - extra);
	}

	/* Disable access to flash interface */
	bnx2_disable_nvram_access(bp);

	bnx2_release_nvram_lock(bp);

	return rc;
}

static int
bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
		int buf_size)
{
	u32 written, offset32, len32;
4082
	u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4083 4084 4085 4086 4087 4088 4089 4090 4091 4092
	int rc = 0;
	int align_start, align_end;

	buf = data_buf;
	offset32 = offset;
	len32 = buf_size;
	align_start = align_end = 0;

	if ((align_start = (offset32 & 3))) {
		offset32 &= ~3;
M
Michael Chan 已提交
4093 4094 4095
		len32 += align_start;
		if (len32 < 4)
			len32 = 4;
4096 4097 4098 4099 4100
		if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
			return rc;
	}

	if (len32 & 3) {
M
Michael Chan 已提交
4101 4102 4103 4104
		align_end = 4 - (len32 & 3);
		len32 += align_end;
		if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
			return rc;
4105 4106 4107
	}

	if (align_start || align_end) {
4108 4109
		align_buf = kmalloc(len32, GFP_KERNEL);
		if (align_buf == NULL)
4110 4111
			return -ENOMEM;
		if (align_start) {
4112
			memcpy(align_buf, start, 4);
4113 4114
		}
		if (align_end) {
4115
			memcpy(align_buf + len32 - 4, end, 4);
4116
		}
4117 4118
		memcpy(align_buf + align_start, data_buf, buf_size);
		buf = align_buf;
4119 4120
	}

M
Michael Chan 已提交
4121
	if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4122 4123 4124 4125 4126 4127 4128
		flash_buffer = kmalloc(264, GFP_KERNEL);
		if (flash_buffer == NULL) {
			rc = -ENOMEM;
			goto nvram_write_end;
		}
	}

4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142
	written = 0;
	while ((written < len32) && (rc == 0)) {
		u32 page_start, page_end, data_start, data_end;
		u32 addr, cmd_flags;
		int i;

	        /* Find the page_start addr */
		page_start = offset32 + written;
		page_start -= (page_start % bp->flash_info->page_size);
		/* Find the page_end addr */
		page_end = page_start + bp->flash_info->page_size;
		/* Find the data_start addr */
		data_start = (written == 0) ? offset32 : page_start;
		/* Find the data_end addr */
4143
		data_end = (page_end > offset32 + len32) ?
4144 4145 4146 4147 4148 4149 4150 4151 4152 4153
			(offset32 + len32) : page_end;

		/* Request access to the flash interface. */
		if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
			goto nvram_write_end;

		/* Enable access to flash interface */
		bnx2_enable_nvram_access(bp);

		cmd_flags = BNX2_NVM_COMMAND_FIRST;
M
Michael Chan 已提交
4154
		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4155 4156 4157 4158 4159 4160 4161 4162 4163
			int j;

			/* Read the whole page into the buffer
			 * (non-buffer flash only) */
			for (j = 0; j < bp->flash_info->page_size; j += 4) {
				if (j == (bp->flash_info->page_size - 4)) {
					cmd_flags |= BNX2_NVM_COMMAND_LAST;
				}
				rc = bnx2_nvram_read_dword(bp,
4164 4165
					page_start + j,
					&flash_buffer[j],
4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181
					cmd_flags);

				if (rc)
					goto nvram_write_end;

				cmd_flags = 0;
			}
		}

		/* Enable writes to flash interface (unlock write-protect) */
		if ((rc = bnx2_enable_nvram_write(bp)) != 0)
			goto nvram_write_end;

		/* Loop to write back the buffer data from page_start to
		 * data_start */
		i = 0;
M
Michael Chan 已提交
4182
		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
M
Michael Chan 已提交
4183 4184 4185 4186 4187 4188 4189
			/* Erase the page */
			if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
				goto nvram_write_end;

			/* Re-enable the write again for the actual write */
			bnx2_enable_nvram_write(bp);

4190 4191
			for (addr = page_start; addr < data_start;
				addr += 4, i += 4) {
4192

4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203
				rc = bnx2_nvram_write_dword(bp, addr,
					&flash_buffer[i], cmd_flags);

				if (rc != 0)
					goto nvram_write_end;

				cmd_flags = 0;
			}
		}

		/* Loop to write the new data from data_start to data_end */
4204
		for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4205
			if ((addr == page_end - 4) ||
M
Michael Chan 已提交
4206
				((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222
				 (addr == data_end - 4))) {

				cmd_flags |= BNX2_NVM_COMMAND_LAST;
			}
			rc = bnx2_nvram_write_dword(bp, addr, buf,
				cmd_flags);

			if (rc != 0)
				goto nvram_write_end;

			cmd_flags = 0;
			buf += 4;
		}

		/* Loop to write back the buffer data from data_end
		 * to page_end */
M
Michael Chan 已提交
4223
		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4224 4225
			for (addr = data_end; addr < page_end;
				addr += 4, i += 4) {
4226

4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251
				if (addr == page_end-4) {
					cmd_flags = BNX2_NVM_COMMAND_LAST;
                		}
				rc = bnx2_nvram_write_dword(bp, addr,
					&flash_buffer[i], cmd_flags);

				if (rc != 0)
					goto nvram_write_end;

				cmd_flags = 0;
			}
		}

		/* Disable writes to flash interface (lock write-protect) */
		bnx2_disable_nvram_write(bp);

		/* Disable access to flash interface */
		bnx2_disable_nvram_access(bp);
		bnx2_release_nvram_lock(bp);

		/* Increment written */
		written += data_end - data_start;
	}

nvram_write_end:
4252 4253
	kfree(flash_buffer);
	kfree(align_buf);
4254 4255 4256
	return rc;
}

4257 4258 4259 4260 4261
static void
bnx2_init_remote_phy(struct bnx2 *bp)
{
	u32 val;

4262 4263
	bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
	if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES))
4264 4265
		return;

4266
	val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4267 4268 4269 4270
	if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
		return;

	if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
4271
		bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4272

4273
		val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4274 4275 4276 4277
		if (val & BNX2_LINK_STATUS_SERDES_LINK)
			bp->phy_port = PORT_FIBRE;
		else
			bp->phy_port = PORT_TP;
4278 4279 4280 4281 4282 4283

		if (netif_running(bp->dev)) {
			u32 sig;

			sig = BNX2_DRV_ACK_CAP_SIGNATURE |
			      BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4284
			bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4285
		}
4286 4287 4288
	}
}

4289 4290 4291 4292 4293 4294 4295 4296 4297
static void
bnx2_setup_msix_tbl(struct bnx2 *bp)
{
	REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);

	REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
	REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
}

4298 4299 4300 4301 4302
static int
bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
{
	u32 val;
	int i, rc = 0;
4303
	u8 old_port;
4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314

	/* Wait for the current PCI transaction to complete before
	 * issuing a reset. */
	REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
	       BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
	       BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
	       BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
	       BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
	val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
	udelay(5);

4315
	/* Wait for the firmware to tell us it is ok to issue a reset. */
4316
	bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4317

4318 4319
	/* Deposit a driver reset signature so the firmware knows that
	 * this is a soft reset. */
4320 4321
	bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
		      BNX2_DRV_RESET_SIGNATURE_MAGIC);
4322 4323 4324 4325 4326

	/* Do a dummy read to force the chip to complete all current transaction
	 * before we issue a reset. */
	val = REG_RD(bp, BNX2_MISC_ID);

4327 4328 4329 4330
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
		REG_RD(bp, BNX2_MISC_COMMAND);
		udelay(5);
4331

4332 4333
		val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
		      BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4334

4335
		pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4336

4337 4338 4339 4340 4341 4342 4343 4344
	} else {
		val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
		      BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
		      BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;

		/* Chip reset. */
		REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);

4345 4346 4347 4348
		/* Reading back any register after chip reset will hang the
		 * bus on 5706 A0 and A1.  The msleep below provides plenty
		 * of margin for write posting.
		 */
4349
		if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
A
Arjan van de Ven 已提交
4350 4351
		    (CHIP_ID(bp) == CHIP_ID_5706_A1))
			msleep(20);
4352

4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366
		/* Reset takes approximate 30 usec */
		for (i = 0; i < 10; i++) {
			val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
			if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
				    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
				break;
			udelay(10);
		}

		if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
			   BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
			printk(KERN_ERR PFX "Chip reset did not complete\n");
			return -EBUSY;
		}
4367 4368 4369 4370 4371 4372 4373 4374 4375 4376
	}

	/* Make sure byte swapping is properly configured. */
	val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
	if (val != 0x01020304) {
		printk(KERN_ERR PFX "Chip not in correct endian mode\n");
		return -ENODEV;
	}

	/* Wait for the firmware to finish its initialization. */
4377
	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4378 4379
	if (rc)
		return rc;
4380

4381
	spin_lock_bh(&bp->phy_lock);
4382
	old_port = bp->phy_port;
4383
	bnx2_init_remote_phy(bp);
4384 4385
	if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
	    old_port != bp->phy_port)
4386 4387 4388
		bnx2_set_default_remote_link(bp);
	spin_unlock_bh(&bp->phy_lock);

4389 4390 4391 4392 4393 4394 4395 4396 4397
	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
		/* Adjust the voltage regular to two steps lower.  The default
		 * of this register is 0x0000000e. */
		REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);

		/* Remove bad rbuf memory from the free pool. */
		rc = bnx2_alloc_bad_rbuf(bp);
	}

4398
	if (bp->flags & BNX2_FLAG_USING_MSIX)
4399 4400
		bnx2_setup_msix_tbl(bp);

4401 4402 4403 4404 4405 4406 4407
	return rc;
}

static int
bnx2_init_chip(struct bnx2 *bp)
{
	u32 val;
4408
	int rc, i;
4409 4410 4411 4412 4413 4414 4415

	/* Make sure the interrupt is not active. */
	REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);

	val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
	      BNX2_DMA_CONFIG_DATA_WORD_SWAP |
#ifdef __BIG_ENDIAN
4416
	      BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4417
#endif
4418
	      BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4419 4420 4421 4422 4423
	      DMA_READ_CHANS << 12 |
	      DMA_WRITE_CHANS << 16;

	val |= (0x2 << 20) | (1 << 11);

4424
	if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4425 4426 4427
		val |= (1 << 23);

	if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4428
	    (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4429 4430 4431 4432 4433 4434 4435 4436 4437 4438
		val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;

	REG_WR(bp, BNX2_DMA_CONFIG, val);

	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
		val = REG_RD(bp, BNX2_TDMA_CONFIG);
		val |= BNX2_TDMA_CONFIG_ONE_DMA;
		REG_WR(bp, BNX2_TDMA_CONFIG, val);
	}

4439
	if (bp->flags & BNX2_FLAG_PCIX) {
4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454
		u16 val16;

		pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
				     &val16);
		pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
				      val16 & ~PCI_X_CMD_ERO);
	}

	REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
	       BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
	       BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
	       BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);

	/* Initialize context mapping and zero out the quick contexts.  The
	 * context block must have already been enabled. */
4455 4456 4457 4458 4459
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		rc = bnx2_init_5709_context(bp);
		if (rc)
			return rc;
	} else
M
Michael Chan 已提交
4460
		bnx2_init_context(bp);
4461

4462 4463 4464
	if ((rc = bnx2_init_cpus(bp)) != 0)
		return rc;

4465 4466 4467 4468 4469 4470 4471
	bnx2_init_nvram(bp);

	bnx2_set_mac_addr(bp);

	val = REG_RD(bp, BNX2_MQ_CONFIG);
	val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
	val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4472 4473 4474
	if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
		val |= BNX2_MQ_CONFIG_HALT_DIS;

4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503
	REG_WR(bp, BNX2_MQ_CONFIG, val);

	val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
	REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
	REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);

	val = (BCM_PAGE_BITS - 8) << 24;
	REG_WR(bp, BNX2_RV2P_CONFIG, val);

	/* Configure page size. */
	val = REG_RD(bp, BNX2_TBDR_CONFIG);
	val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
	val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
	REG_WR(bp, BNX2_TBDR_CONFIG, val);

	val = bp->mac_addr[0] +
	      (bp->mac_addr[1] << 8) +
	      (bp->mac_addr[2] << 16) +
	      bp->mac_addr[3] +
	      (bp->mac_addr[4] << 8) +
	      (bp->mac_addr[5] << 16);
	REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);

	/* Program the MTU.  Also include 4 bytes for CRC32. */
	val = bp->dev->mtu + ETH_HLEN + 4;
	if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
		val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
	REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);

4504 4505 4506
	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
		bp->bnx2_napi[i].last_status_idx = 0;

4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520
	bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;

	/* Set up how to generate a link change interrupt. */
	REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);

	REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
	       (u64) bp->status_blk_mapping & 0xffffffff);
	REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);

	REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
	       (u64) bp->stats_blk_mapping & 0xffffffff);
	REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
	       (u64) bp->stats_blk_mapping >> 32);

4521
	REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539
	       (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);

	REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
	       (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);

	REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
	       (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);

	REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);

	REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);

	REG_WR(bp, BNX2_HC_COM_TICKS,
	       (bp->com_ticks_int << 16) | bp->com_ticks);

	REG_WR(bp, BNX2_HC_CMD_TICKS,
	       (bp->cmd_ticks_int << 16) | bp->cmd_ticks);

4540 4541 4542
	if (CHIP_NUM(bp) == CHIP_NUM_5708)
		REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
	else
4543
		REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4544 4545 4546
	REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */

	if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4547
		val = BNX2_HC_CONFIG_COLLECT_STATS;
4548
	else {
4549 4550
		val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
		      BNX2_HC_CONFIG_COLLECT_STATS;
4551 4552
	}

M
Michael Chan 已提交
4553
	if (bp->irq_nvecs > 1) {
4554 4555 4556
		REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
		       BNX2_HC_MSIX_BIT_VECTOR_VAL);

M
Michael Chan 已提交
4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568
		val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
	}

	if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
		val |= BNX2_HC_CONFIG_ONE_SHOT;

	REG_WR(bp, BNX2_HC_CONFIG, val);

	for (i = 1; i < bp->irq_nvecs; i++) {
		u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
			   BNX2_HC_SB_CONFIG_1;

4569
		REG_WR(bp, base,
4570
			BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
M
Michael Chan 已提交
4571
			BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4572 4573
			BNX2_HC_SB_CONFIG_1_ONE_SHOT);

4574
		REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4575 4576 4577
			(bp->tx_quick_cons_trip_int << 16) |
			 bp->tx_quick_cons_trip);

4578
		REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4579 4580
			(bp->tx_ticks_int << 16) | bp->tx_ticks);

M
Michael Chan 已提交
4581 4582 4583
		REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
		       (bp->rx_quick_cons_trip_int << 16) |
			bp->rx_quick_cons_trip);
4584

M
Michael Chan 已提交
4585 4586 4587
		REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
			(bp->rx_ticks_int << 16) | bp->rx_ticks);
	}
4588

4589 4590 4591
	/* Clear internal stats counters. */
	REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);

4592
	REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4593 4594 4595 4596

	/* Initialize the receive filter. */
	bnx2_set_rx_mode(bp->dev);

M
Michael Chan 已提交
4597 4598 4599 4600 4601
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
		val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
		REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
	}
4602
	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4603
			  1, 0);
4604

M
Michael Chan 已提交
4605
	REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4606 4607 4608 4609
	REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);

	udelay(20);

M
Michael Chan 已提交
4610 4611
	bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);

4612
	return rc;
4613 4614
}

4615 4616 4617 4618
static void
bnx2_clear_ring_states(struct bnx2 *bp)
{
	struct bnx2_napi *bnapi;
4619
	struct bnx2_tx_ring_info *txr;
4620
	struct bnx2_rx_ring_info *rxr;
4621 4622 4623 4624
	int i;

	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
		bnapi = &bp->bnx2_napi[i];
4625
		txr = &bnapi->tx_ring;
4626
		rxr = &bnapi->rx_ring;
4627

4628 4629
		txr->tx_cons = 0;
		txr->hw_tx_cons = 0;
4630 4631 4632 4633 4634
		rxr->rx_prod_bseq = 0;
		rxr->rx_prod = 0;
		rxr->rx_cons = 0;
		rxr->rx_pg_prod = 0;
		rxr->rx_pg_cons = 0;
4635 4636 4637
	}
}

M
Michael Chan 已提交
4638
static void
4639
bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
M
Michael Chan 已提交
4640 4641
{
	u32 val, offset0, offset1, offset2, offset3;
M
Michael Chan 已提交
4642
	u32 cid_addr = GET_CID_ADDR(cid);
M
Michael Chan 已提交
4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655

	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		offset0 = BNX2_L2CTX_TYPE_XI;
		offset1 = BNX2_L2CTX_CMD_TYPE_XI;
		offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
		offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
	} else {
		offset0 = BNX2_L2CTX_TYPE;
		offset1 = BNX2_L2CTX_CMD_TYPE;
		offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
		offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
	}
	val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
M
Michael Chan 已提交
4656
	bnx2_ctx_wr(bp, cid_addr, offset0, val);
M
Michael Chan 已提交
4657 4658

	val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
M
Michael Chan 已提交
4659
	bnx2_ctx_wr(bp, cid_addr, offset1, val);
M
Michael Chan 已提交
4660

4661
	val = (u64) txr->tx_desc_mapping >> 32;
M
Michael Chan 已提交
4662
	bnx2_ctx_wr(bp, cid_addr, offset2, val);
M
Michael Chan 已提交
4663

4664
	val = (u64) txr->tx_desc_mapping & 0xffffffff;
M
Michael Chan 已提交
4665
	bnx2_ctx_wr(bp, cid_addr, offset3, val);
M
Michael Chan 已提交
4666
}
4667 4668

static void
4669
bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
4670 4671
{
	struct tx_bd *txbd;
4672 4673
	u32 cid = TX_CID;
	struct bnx2_napi *bnapi;
4674
	struct bnx2_tx_ring_info *txr;
4675

4676 4677 4678 4679 4680 4681 4682
	bnapi = &bp->bnx2_napi[ring_num];
	txr = &bnapi->tx_ring;

	if (ring_num == 0)
		cid = TX_CID;
	else
		cid = TX_TSS_CID + ring_num - 1;
4683

M
Michael Chan 已提交
4684 4685
	bp->tx_wake_thresh = bp->tx_ring_size / 2;

4686
	txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
4687

4688 4689
	txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
	txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
4690

4691 4692
	txr->tx_prod = 0;
	txr->tx_prod_bseq = 0;
4693

4694 4695
	txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
	txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4696

4697
	bnx2_init_tx_context(bp, cid, txr);
4698 4699 4700
}

static void
4701 4702
bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
		     int num_rings)
4703 4704
{
	int i;
4705
	struct rx_bd *rxbd;
4706

4707
	for (i = 0; i < num_rings; i++) {
4708
		int j;
4709

4710
		rxbd = &rx_ring[i][0];
4711
		for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4712
			rxbd->rx_bd_len = buf_size;
4713 4714
			rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
		}
4715
		if (i == (num_rings - 1))
4716 4717 4718
			j = 0;
		else
			j = i + 1;
4719 4720
		rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
		rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4721
	}
4722 4723 4724
}

static void
4725
bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
4726 4727 4728
{
	int i;
	u16 prod, ring_prod;
4729 4730 4731 4732 4733 4734 4735 4736 4737 4738
	u32 cid, rx_cid_addr, val;
	struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;

	if (ring_num == 0)
		cid = RX_CID;
	else
		cid = RX_RSS_CID + ring_num - 1;

	rx_cid_addr = GET_CID_ADDR(cid);
4739

4740
	bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
4741 4742
			     bp->rx_buf_use_size, bp->rx_max_ring);

4743
	bnx2_init_rx_context(bp, cid);
4744 4745 4746 4747 4748 4749

	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
		REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
	}

M
Michael Chan 已提交
4750
	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4751
	if (bp->rx_pg_ring_size) {
4752 4753
		bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
				     rxr->rx_pg_desc_mapping,
4754 4755
				     PAGE_SIZE, bp->rx_max_pg_ring);
		val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
M
Michael Chan 已提交
4756 4757
		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
M
Michael Chan 已提交
4758
		       BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
4759

4760
		val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
M
Michael Chan 已提交
4761
		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4762

4763
		val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
M
Michael Chan 已提交
4764
		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4765 4766 4767 4768

		if (CHIP_NUM(bp) == CHIP_NUM_5709)
			REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
	}
4769

4770
	val = (u64) rxr->rx_desc_mapping[0] >> 32;
M
Michael Chan 已提交
4771
	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4772

4773
	val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
M
Michael Chan 已提交
4774
	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4775

4776
	ring_prod = prod = rxr->rx_pg_prod;
4777
	for (i = 0; i < bp->rx_pg_ring_size; i++) {
4778
		if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
4779 4780 4781 4782
			break;
		prod = NEXT_RX_BD(prod);
		ring_prod = RX_PG_RING_IDX(prod);
	}
4783
	rxr->rx_pg_prod = prod;
4784

4785
	ring_prod = prod = rxr->rx_prod;
4786
	for (i = 0; i < bp->rx_ring_size; i++) {
4787
		if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
4788 4789 4790 4791
			break;
		prod = NEXT_RX_BD(prod);
		ring_prod = RX_RING_IDX(prod);
	}
4792
	rxr->rx_prod = prod;
4793

4794 4795 4796
	rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
	rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
	rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
4797

4798 4799 4800 4801
	REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
	REG_WR16(bp, rxr->rx_bidx_addr, prod);

	REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
4802 4803
}

4804 4805 4806 4807
static void
bnx2_init_all_rings(struct bnx2 *bp)
{
	int i;
M
Michael Chan 已提交
4808
	u32 val;
4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819

	bnx2_clear_ring_states(bp);

	REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
	for (i = 0; i < bp->num_tx_rings; i++)
		bnx2_init_tx_ring(bp, i);

	if (bp->num_tx_rings > 1)
		REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
		       (TX_TSS_CID << 7));

M
Michael Chan 已提交
4820 4821 4822
	REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
	bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);

4823 4824
	for (i = 0; i < bp->num_rx_rings; i++)
		bnx2_init_rx_ring(bp, i);
M
Michael Chan 已提交
4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846

	if (bp->num_rx_rings > 1) {
		u32 tbl_32;
		u8 *tbl = (u8 *) &tbl_32;

		bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
				BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);

		for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
			tbl[i % 4] = i % (bp->num_rx_rings - 1);
			if ((i % 4) == 3)
				bnx2_reg_wr_ind(bp,
						BNX2_RXP_SCRATCH_RSS_TBL + i,
						cpu_to_be32(tbl_32));
		}

		val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
		      BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;

		REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);

	}
4847 4848
}

4849
static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4850
{
4851
	u32 max, num_rings = 1;
4852

4853 4854
	while (ring_size > MAX_RX_DESC_CNT) {
		ring_size -= MAX_RX_DESC_CNT;
4855 4856 4857
		num_rings++;
	}
	/* round to next power of 2 */
4858
	max = max_size;
4859 4860 4861 4862 4863 4864
	while ((max & num_rings) == 0)
		max >>= 1;

	if (num_rings != max)
		max <<= 1;

4865 4866 4867 4868 4869 4870
	return max;
}

static void
bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
{
M
Michael Chan 已提交
4871
	u32 rx_size, rx_space, jumbo_size;
4872 4873

	/* 8 for CRC and VLAN */
4874
	rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
4875

M
Michael Chan 已提交
4876 4877 4878
	rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
		sizeof(struct skb_shared_info);

4879
	bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
4880 4881 4882
	bp->rx_pg_ring_size = 0;
	bp->rx_max_pg_ring = 0;
	bp->rx_max_pg_ring_idx = 0;
4883
	if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
M
Michael Chan 已提交
4884 4885 4886 4887 4888 4889 4890 4891 4892 4893
		int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;

		jumbo_size = size * pages;
		if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
			jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;

		bp->rx_pg_ring_size = jumbo_size;
		bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
							MAX_RX_PG_RINGS);
		bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4894
		rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
M
Michael Chan 已提交
4895 4896
		bp->rx_copy_thresh = 0;
	}
4897 4898 4899 4900

	bp->rx_buf_use_size = rx_size;
	/* hw alignment */
	bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4901
	bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
4902 4903
	bp->rx_ring_size = size;
	bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4904 4905 4906
	bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
}

4907 4908 4909 4910 4911
static void
bnx2_free_tx_skbs(struct bnx2 *bp)
{
	int i;

4912 4913 4914 4915
	for (i = 0; i < bp->num_tx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
		int j;
4916

4917
		if (txr->tx_buf_ring == NULL)
4918 4919
			continue;

4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931
		for (j = 0; j < TX_DESC_CNT; ) {
			struct sw_bd *tx_buf = &txr->tx_buf_ring[j];
			struct sk_buff *skb = tx_buf->skb;
			int k, last;

			if (skb == NULL) {
				j++;
				continue;
			}

			pci_unmap_single(bp->pdev,
					 pci_unmap_addr(tx_buf, mapping),
4932 4933
			skb_headlen(skb), PCI_DMA_TODEVICE);

4934
			tx_buf->skb = NULL;
4935

4936 4937 4938 4939 4940 4941 4942 4943 4944 4945
			last = skb_shinfo(skb)->nr_frags;
			for (k = 0; k < last; k++) {
				tx_buf = &txr->tx_buf_ring[j + k + 1];
				pci_unmap_page(bp->pdev,
					pci_unmap_addr(tx_buf, mapping),
					skb_shinfo(skb)->frags[j].size,
					PCI_DMA_TODEVICE);
			}
			dev_kfree_skb(skb);
			j += k + 1;
4946 4947 4948 4949 4950 4951 4952 4953 4954
		}
	}
}

static void
bnx2_free_rx_skbs(struct bnx2 *bp)
{
	int i;

4955 4956 4957 4958
	for (i = 0; i < bp->num_rx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
		int j;
4959

4960 4961
		if (rxr->rx_buf_ring == NULL)
			return;
4962

4963 4964 4965
		for (j = 0; j < bp->rx_max_ring_idx; j++) {
			struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
			struct sk_buff *skb = rx_buf->skb;
4966

4967 4968
			if (skb == NULL)
				continue;
4969

4970 4971 4972 4973
			pci_unmap_single(bp->pdev,
					 pci_unmap_addr(rx_buf, mapping),
					 bp->rx_buf_use_size,
					 PCI_DMA_FROMDEVICE);
4974

4975 4976 4977 4978 4979 4980
			rx_buf->skb = NULL;

			dev_kfree_skb(skb);
		}
		for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
			bnx2_free_rx_page(bp, rxr, j);
4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000
	}
}

static void
bnx2_free_skbs(struct bnx2 *bp)
{
	bnx2_free_tx_skbs(bp);
	bnx2_free_rx_skbs(bp);
}

static int
bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
{
	int rc;

	rc = bnx2_reset_chip(bp, reset_code);
	bnx2_free_skbs(bp);
	if (rc)
		return rc;

5001 5002 5003
	if ((rc = bnx2_init_chip(bp)) != 0)
		return rc;

5004
	bnx2_init_all_rings(bp);
5005 5006 5007 5008
	return 0;
}

static int
5009
bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5010 5011 5012 5013 5014 5015
{
	int rc;

	if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
		return rc;

M
Michael Chan 已提交
5016
	spin_lock_bh(&bp->phy_lock);
5017
	bnx2_init_phy(bp, reset_phy);
5018
	bnx2_set_link(bp);
5019 5020
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
		bnx2_remote_phy_event(bp);
5021
	spin_unlock_bh(&bp->phy_lock);
5022 5023 5024 5025 5026 5027 5028
	return 0;
}

static int
bnx2_test_registers(struct bnx2 *bp)
{
	int ret;
5029
	int i, is_5709;
5030
	static const struct {
5031 5032
		u16   offset;
		u16   flags;
5033
#define BNX2_FL_NOT_5709	1
5034 5035 5036 5037 5038 5039 5040
		u32   rw_mask;
		u32   ro_mask;
	} reg_tbl[] = {
		{ 0x006c, 0, 0x00000000, 0x0000003f },
		{ 0x0090, 0, 0xffffffff, 0x00000000 },
		{ 0x0094, 0, 0x00000000, 0x00000000 },

5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060
		{ 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
		{ 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
		{ 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
		{ 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
		{ 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
		{ 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },

		{ 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
		{ 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
		{ 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
		{ 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },

		{ 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
		{ 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
		{ 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
5061 5062

		{ 0x1000, 0, 0x00000000, 0x00000001 },
M
Michael Chan 已提交
5063
		{ 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5064 5065 5066 5067

		{ 0x1408, 0, 0x01c00800, 0x00000000 },
		{ 0x149c, 0, 0x8000ffff, 0x00000000 },
		{ 0x14a8, 0, 0x00000000, 0x000001ff },
M
Michael Chan 已提交
5068
		{ 0x14ac, 0, 0x0fffffff, 0x10000000 },
5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116 5117 5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145
		{ 0x14b0, 0, 0x00000002, 0x00000001 },
		{ 0x14b8, 0, 0x00000000, 0x00000000 },
		{ 0x14c0, 0, 0x00000000, 0x00000009 },
		{ 0x14c4, 0, 0x00003fff, 0x00000000 },
		{ 0x14cc, 0, 0x00000000, 0x00000001 },
		{ 0x14d0, 0, 0xffffffff, 0x00000000 },

		{ 0x1800, 0, 0x00000000, 0x00000001 },
		{ 0x1804, 0, 0x00000000, 0x00000003 },

		{ 0x2800, 0, 0x00000000, 0x00000001 },
		{ 0x2804, 0, 0x00000000, 0x00003f01 },
		{ 0x2808, 0, 0x0f3f3f03, 0x00000000 },
		{ 0x2810, 0, 0xffff0000, 0x00000000 },
		{ 0x2814, 0, 0xffff0000, 0x00000000 },
		{ 0x2818, 0, 0xffff0000, 0x00000000 },
		{ 0x281c, 0, 0xffff0000, 0x00000000 },
		{ 0x2834, 0, 0xffffffff, 0x00000000 },
		{ 0x2840, 0, 0x00000000, 0xffffffff },
		{ 0x2844, 0, 0x00000000, 0xffffffff },
		{ 0x2848, 0, 0xffffffff, 0x00000000 },
		{ 0x284c, 0, 0xf800f800, 0x07ff07ff },

		{ 0x2c00, 0, 0x00000000, 0x00000011 },
		{ 0x2c04, 0, 0x00000000, 0x00030007 },

		{ 0x3c00, 0, 0x00000000, 0x00000001 },
		{ 0x3c04, 0, 0x00000000, 0x00070000 },
		{ 0x3c08, 0, 0x00007f71, 0x07f00000 },
		{ 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
		{ 0x3c10, 0, 0xffffffff, 0x00000000 },
		{ 0x3c14, 0, 0x00000000, 0xffffffff },
		{ 0x3c18, 0, 0x00000000, 0xffffffff },
		{ 0x3c1c, 0, 0xfffff000, 0x00000000 },
		{ 0x3c20, 0, 0xffffff00, 0x00000000 },

		{ 0x5004, 0, 0x00000000, 0x0000007f },
		{ 0x5008, 0, 0x0f0007ff, 0x00000000 },

		{ 0x5c00, 0, 0x00000000, 0x00000001 },
		{ 0x5c04, 0, 0x00000000, 0x0003000f },
		{ 0x5c08, 0, 0x00000003, 0x00000000 },
		{ 0x5c0c, 0, 0x0000fff8, 0x00000000 },
		{ 0x5c10, 0, 0x00000000, 0xffffffff },
		{ 0x5c80, 0, 0x00000000, 0x0f7113f1 },
		{ 0x5c84, 0, 0x00000000, 0x0000f333 },
		{ 0x5c88, 0, 0x00000000, 0x00077373 },
		{ 0x5c8c, 0, 0x00000000, 0x0007f737 },

		{ 0x6808, 0, 0x0000ff7f, 0x00000000 },
		{ 0x680c, 0, 0xffffffff, 0x00000000 },
		{ 0x6810, 0, 0xffffffff, 0x00000000 },
		{ 0x6814, 0, 0xffffffff, 0x00000000 },
		{ 0x6818, 0, 0xffffffff, 0x00000000 },
		{ 0x681c, 0, 0xffffffff, 0x00000000 },
		{ 0x6820, 0, 0x00ff00ff, 0x00000000 },
		{ 0x6824, 0, 0x00ff00ff, 0x00000000 },
		{ 0x6828, 0, 0x00ff00ff, 0x00000000 },
		{ 0x682c, 0, 0x03ff03ff, 0x00000000 },
		{ 0x6830, 0, 0x03ff03ff, 0x00000000 },
		{ 0x6834, 0, 0x03ff03ff, 0x00000000 },
		{ 0x6838, 0, 0x03ff03ff, 0x00000000 },
		{ 0x683c, 0, 0x0000ffff, 0x00000000 },
		{ 0x6840, 0, 0x00000ff0, 0x00000000 },
		{ 0x6844, 0, 0x00ffff00, 0x00000000 },
		{ 0x684c, 0, 0xffffffff, 0x00000000 },
		{ 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
		{ 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
		{ 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
		{ 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
		{ 0x6908, 0, 0x00000000, 0x0001ff0f },
		{ 0x690c, 0, 0x00000000, 0x0ffe00f0 },

		{ 0xffff, 0, 0x00000000, 0x00000000 },
	};

	ret = 0;
5146 5147 5148 5149
	is_5709 = 0;
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		is_5709 = 1;

5150 5151
	for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
		u32 offset, rw_mask, ro_mask, save_val, val;
5152 5153 5154 5155
		u16 flags = reg_tbl[i].flags;

		if (is_5709 && (flags & BNX2_FL_NOT_5709))
			continue;
5156 5157 5158 5159 5160

		offset = (u32) reg_tbl[i].offset;
		rw_mask = reg_tbl[i].rw_mask;
		ro_mask = reg_tbl[i].ro_mask;

5161
		save_val = readl(bp->regview + offset);
5162

5163
		writel(0, bp->regview + offset);
5164

5165
		val = readl(bp->regview + offset);
5166 5167 5168 5169 5170 5171 5172 5173
		if ((val & rw_mask) != 0) {
			goto reg_test_err;
		}

		if ((val & ro_mask) != (save_val & ro_mask)) {
			goto reg_test_err;
		}

5174
		writel(0xffffffff, bp->regview + offset);
5175

5176
		val = readl(bp->regview + offset);
5177 5178 5179 5180 5181 5182 5183 5184
		if ((val & rw_mask) != rw_mask) {
			goto reg_test_err;
		}

		if ((val & ro_mask) != (save_val & ro_mask)) {
			goto reg_test_err;
		}

5185
		writel(save_val, bp->regview + offset);
5186 5187 5188
		continue;

reg_test_err:
5189
		writel(save_val, bp->regview + offset);
5190 5191 5192 5193 5194 5195 5196 5197 5198
		ret = -ENODEV;
		break;
	}
	return ret;
}

static int
bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
{
5199
	static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5200 5201 5202 5203 5204 5205 5206 5207
		0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
	int i;

	for (i = 0; i < sizeof(test_pattern) / 4; i++) {
		u32 offset;

		for (offset = 0; offset < size; offset += 4) {

5208
			bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5209

5210
			if (bnx2_reg_rd_ind(bp, start + offset) !=
5211 5212 5213 5214 5215 5216 5217 5218 5219 5220 5221 5222 5223
				test_pattern[i]) {
				return -ENODEV;
			}
		}
	}
	return 0;
}

static int
bnx2_test_memory(struct bnx2 *bp)
{
	int ret = 0;
	int i;
5224
	static struct mem_entry {
5225 5226
		u32   offset;
		u32   len;
5227
	} mem_tbl_5706[] = {
5228
		{ 0x60000,  0x4000 },
M
Michael Chan 已提交
5229
		{ 0xa0000,  0x3000 },
5230 5231 5232 5233 5234
		{ 0xe0000,  0x4000 },
		{ 0x120000, 0x4000 },
		{ 0x1a0000, 0x4000 },
		{ 0x160000, 0x4000 },
		{ 0xffffffff, 0    },
5235 5236 5237 5238 5239 5240 5241 5242
	},
	mem_tbl_5709[] = {
		{ 0x60000,  0x4000 },
		{ 0xa0000,  0x3000 },
		{ 0xe0000,  0x4000 },
		{ 0x120000, 0x4000 },
		{ 0x1a0000, 0x4000 },
		{ 0xffffffff, 0    },
5243
	};
5244 5245 5246 5247 5248 5249
	struct mem_entry *mem_tbl;

	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		mem_tbl = mem_tbl_5709;
	else
		mem_tbl = mem_tbl_5706;
5250 5251 5252 5253 5254 5255 5256

	for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
		if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
			mem_tbl[i].len)) != 0) {
			return ret;
		}
	}
5257

5258 5259 5260
	return ret;
}

M
Michael Chan 已提交
5261 5262 5263
#define BNX2_MAC_LOOPBACK	0
#define BNX2_PHY_LOOPBACK	1

5264
static int
M
Michael Chan 已提交
5265
bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5266 5267 5268 5269
{
	unsigned int pkt_size, num_pkts, i;
	struct sk_buff *skb, *rx_skb;
	unsigned char *packet;
M
Michael Chan 已提交
5270
	u16 rx_start_idx, rx_idx;
5271 5272 5273 5274 5275
	dma_addr_t map;
	struct tx_bd *txbd;
	struct sw_bd *rx_buf;
	struct l2_fhdr *rx_hdr;
	int ret = -ENODEV;
5276
	struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5277
	struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5278
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5279 5280

	tx_napi = bnapi;
5281

5282
	txr = &tx_napi->tx_ring;
5283
	rxr = &bnapi->rx_ring;
M
Michael Chan 已提交
5284 5285 5286 5287 5288
	if (loopback_mode == BNX2_MAC_LOOPBACK) {
		bp->loopback = MAC_LOOPBACK;
		bnx2_set_mac_loopback(bp);
	}
	else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5289
		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5290 5291
			return 0;

M
Michael Chan 已提交
5292
		bp->loopback = PHY_LOOPBACK;
M
Michael Chan 已提交
5293 5294 5295 5296
		bnx2_set_phy_loopback(bp);
	}
	else
		return -EINVAL;
5297

M
Michael Chan 已提交
5298
	pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5299
	skb = netdev_alloc_skb(bp->dev, pkt_size);
5300 5301
	if (!skb)
		return -ENOMEM;
5302
	packet = skb_put(skb, pkt_size);
M
Michael Chan 已提交
5303
	memcpy(packet, bp->dev->dev_addr, 6);
5304 5305 5306 5307 5308 5309 5310
	memset(packet + 6, 0x0, 8);
	for (i = 14; i < pkt_size; i++)
		packet[i] = (unsigned char) (i & 0xff);

	map = pci_map_single(bp->pdev, skb->data, pkt_size,
		PCI_DMA_TODEVICE);

M
Michael Chan 已提交
5311 5312 5313
	REG_WR(bp, BNX2_HC_COMMAND,
	       bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);

5314 5315 5316
	REG_RD(bp, BNX2_HC_COMMAND);

	udelay(5);
5317
	rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5318 5319 5320

	num_pkts = 0;

5321
	txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5322 5323 5324 5325 5326 5327 5328

	txbd->tx_bd_haddr_hi = (u64) map >> 32;
	txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
	txbd->tx_bd_mss_nbytes = pkt_size;
	txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;

	num_pkts++;
5329 5330
	txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
	txr->tx_prod_bseq += pkt_size;
5331

5332 5333
	REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
	REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5334 5335 5336

	udelay(100);

M
Michael Chan 已提交
5337 5338 5339
	REG_WR(bp, BNX2_HC_COMMAND,
	       bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);

5340 5341 5342 5343 5344
	REG_RD(bp, BNX2_HC_COMMAND);

	udelay(5);

	pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5345
	dev_kfree_skb(skb);
5346

5347
	if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5348 5349
		goto loopback_test_done;

5350
	rx_idx = bnx2_get_hw_rx_cons(bnapi);
5351 5352 5353 5354
	if (rx_idx != rx_start_idx + num_pkts) {
		goto loopback_test_done;
	}

5355
	rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5356 5357 5358
	rx_skb = rx_buf->skb;

	rx_hdr = (struct l2_fhdr *) rx_skb->data;
5359
	skb_reserve(rx_skb, BNX2_RX_OFFSET);
5360 5361 5362 5363 5364

	pci_dma_sync_single_for_cpu(bp->pdev,
		pci_unmap_addr(rx_buf, mapping),
		bp->rx_buf_size, PCI_DMA_FROMDEVICE);

5365
	if (rx_hdr->l2_fhdr_status &
5366 5367 5368 5369 5370 5371 5372 5373 5374 5375 5376 5377 5378 5379 5380 5381 5382 5383 5384 5385 5386 5387 5388 5389 5390 5391
		(L2_FHDR_ERRORS_BAD_CRC |
		L2_FHDR_ERRORS_PHY_DECODE |
		L2_FHDR_ERRORS_ALIGNMENT |
		L2_FHDR_ERRORS_TOO_SHORT |
		L2_FHDR_ERRORS_GIANT_FRAME)) {

		goto loopback_test_done;
	}

	if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
		goto loopback_test_done;
	}

	for (i = 14; i < pkt_size; i++) {
		if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
			goto loopback_test_done;
		}
	}

	ret = 0;

loopback_test_done:
	bp->loopback = 0;
	return ret;
}

M
Michael Chan 已提交
5392 5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406
#define BNX2_MAC_LOOPBACK_FAILED	1
#define BNX2_PHY_LOOPBACK_FAILED	2
#define BNX2_LOOPBACK_FAILED		(BNX2_MAC_LOOPBACK_FAILED |	\
					 BNX2_PHY_LOOPBACK_FAILED)

static int
bnx2_test_loopback(struct bnx2 *bp)
{
	int rc = 0;

	if (!netif_running(bp->dev))
		return BNX2_LOOPBACK_FAILED;

	bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
	spin_lock_bh(&bp->phy_lock);
5407
	bnx2_init_phy(bp, 1);
M
Michael Chan 已提交
5408 5409 5410 5411 5412 5413 5414 5415
	spin_unlock_bh(&bp->phy_lock);
	if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
		rc |= BNX2_MAC_LOOPBACK_FAILED;
	if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
		rc |= BNX2_PHY_LOOPBACK_FAILED;
	return rc;
}

5416 5417 5418 5419 5420 5421
#define NVRAM_SIZE 0x200
#define CRC32_RESIDUAL 0xdebb20e3

static int
bnx2_test_nvram(struct bnx2 *bp)
{
A
Al Viro 已提交
5422
	__be32 buf[NVRAM_SIZE / 4];
5423 5424 5425 5426 5427 5428 5429 5430 5431 5432 5433 5434 5435 5436 5437 5438 5439 5440 5441 5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455 5456 5457 5458
	u8 *data = (u8 *) buf;
	int rc = 0;
	u32 magic, csum;

	if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
		goto test_nvram_done;

        magic = be32_to_cpu(buf[0]);
	if (magic != 0x669955aa) {
		rc = -ENODEV;
		goto test_nvram_done;
	}

	if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
		goto test_nvram_done;

	csum = ether_crc_le(0x100, data);
	if (csum != CRC32_RESIDUAL) {
		rc = -ENODEV;
		goto test_nvram_done;
	}

	csum = ether_crc_le(0x100, data + 0x100);
	if (csum != CRC32_RESIDUAL) {
		rc = -ENODEV;
	}

test_nvram_done:
	return rc;
}

static int
bnx2_test_link(struct bnx2 *bp)
{
	u32 bmsr;

5459
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5460 5461 5462 5463
		if (bp->link_up)
			return 0;
		return -ENODEV;
	}
5464
	spin_lock_bh(&bp->phy_lock);
5465 5466 5467 5468
	bnx2_enable_bmsr1(bp);
	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
	bnx2_disable_bmsr1(bp);
5469
	spin_unlock_bh(&bp->phy_lock);
5470

5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488
	if (bmsr & BMSR_LSTATUS) {
		return 0;
	}
	return -ENODEV;
}

static int
bnx2_test_intr(struct bnx2 *bp)
{
	int i;
	u16 status_idx;

	if (!netif_running(bp->dev))
		return -ENODEV;

	status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;

	/* This register is not touched during run-time. */
M
Michael Chan 已提交
5489
	REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506
	REG_RD(bp, BNX2_HC_COMMAND);

	for (i = 0; i < 10; i++) {
		if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
			status_idx) {

			break;
		}

		msleep_interruptible(10);
	}
	if (i < 10)
		return 0;

	return -ENODEV;
}

5507
/* Determining link for parallel detection. */
5508 5509 5510 5511 5512
static int
bnx2_5706_serdes_has_link(struct bnx2 *bp)
{
	u32 mode_ctl, an_dbg, exp;

5513 5514 5515
	if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
		return 0;

5516 5517 5518 5519 5520 5521 5522 5523 5524 5525
	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);

	if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
		return 0;

	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);

5526
	if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537 5538
		return 0;

	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);

	if (exp & MII_EXPAND_REG1_RUDI_C)	/* receiving CONFIG */
		return 0;

	return 1;
}

5539
static void
5540
bnx2_5706_serdes_timer(struct bnx2 *bp)
5541
{
5542 5543
	int check_link = 1;

5544
	spin_lock(&bp->phy_lock);
5545
	if (bp->serdes_an_pending) {
5546
		bp->serdes_an_pending--;
5547 5548
		check_link = 0;
	} else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5549
		u32 bmcr;
5550

5551
		bp->current_interval = bp->timer_interval;
M
Michael Chan 已提交
5552

5553
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5554

5555
		if (bmcr & BMCR_ANENABLE) {
5556
			if (bnx2_5706_serdes_has_link(bp)) {
5557 5558
				bmcr &= ~BMCR_ANENABLE;
				bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5559
				bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5560
				bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5561
			}
5562
		}
5563 5564
	}
	else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5565
		 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5566
		u32 phy2;
5567

5568 5569 5570 5571
		bnx2_write_phy(bp, 0x17, 0x0f01);
		bnx2_read_phy(bp, 0x15, &phy2);
		if (phy2 & 0x20) {
			u32 bmcr;
M
Michael Chan 已提交
5572

5573
			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5574
			bmcr |= BMCR_ANENABLE;
5575
			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5576

5577
			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5578 5579 5580
		}
	} else
		bp->current_interval = bp->timer_interval;
5581

5582
	if (check_link) {
5583 5584 5585 5586 5587 5588
		u32 val;

		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);

5589 5590 5591 5592 5593 5594 5595 5596
		if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
			if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
				bnx2_5706s_force_link_dn(bp, 1);
				bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
			} else
				bnx2_set_link(bp);
		} else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
			bnx2_set_link(bp);
5597
	}
5598 5599
	spin_unlock(&bp->phy_lock);
}
5600

5601 5602 5603
static void
bnx2_5708_serdes_timer(struct bnx2 *bp)
{
5604
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5605 5606
		return;

5607
	if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5608 5609 5610
		bp->serdes_an_pending = 0;
		return;
	}
5611

5612 5613 5614 5615 5616
	spin_lock(&bp->phy_lock);
	if (bp->serdes_an_pending)
		bp->serdes_an_pending--;
	else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
		u32 bmcr;
5617

5618
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5619
		if (bmcr & BMCR_ANENABLE) {
5620
			bnx2_enable_forced_2g5(bp);
5621 5622
			bp->current_interval = SERDES_FORCED_TIMEOUT;
		} else {
5623
			bnx2_disable_forced_2g5(bp);
5624 5625
			bp->serdes_an_pending = 2;
			bp->current_interval = bp->timer_interval;
5626 5627
		}

5628 5629
	} else
		bp->current_interval = bp->timer_interval;
5630

5631 5632 5633
	spin_unlock(&bp->phy_lock);
}

5634 5635 5636 5637
static void
bnx2_timer(unsigned long data)
{
	struct bnx2 *bp = (struct bnx2 *) data;
5638

5639 5640
	if (!netif_running(bp->dev))
		return;
5641

5642 5643
	if (atomic_read(&bp->intr_sem) != 0)
		goto bnx2_restart_timer;
5644

M
Michael Chan 已提交
5645
	bnx2_send_heart_beat(bp);
5646

5647 5648
	bp->stats_blk->stat_FwRxDrop =
		bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5649

5650 5651 5652 5653 5654
	/* workaround occasional corrupted counters */
	if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
		REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
					    BNX2_HC_COMMAND_STATS_NOW);

5655
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5656 5657
		if (CHIP_NUM(bp) == CHIP_NUM_5706)
			bnx2_5706_serdes_timer(bp);
5658
		else
5659
			bnx2_5708_serdes_timer(bp);
5660 5661 5662
	}

bnx2_restart_timer:
M
Michael Chan 已提交
5663
	mod_timer(&bp->timer, jiffies + bp->current_interval);
5664 5665
}

5666 5667 5668
static int
bnx2_request_irq(struct bnx2 *bp)
{
5669
	unsigned long flags;
5670 5671
	struct bnx2_irq *irq;
	int rc = 0, i;
5672

5673
	if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5674 5675 5676
		flags = 0;
	else
		flags = IRQF_SHARED;
5677 5678 5679

	for (i = 0; i < bp->irq_nvecs; i++) {
		irq = &bp->irq_tbl[i];
5680
		rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5681
				 &bp->bnx2_napi[i]);
5682 5683 5684 5685
		if (rc)
			break;
		irq->requested = 1;
	}
5686 5687 5688 5689 5690 5691
	return rc;
}

static void
bnx2_free_irq(struct bnx2 *bp)
{
5692 5693
	struct bnx2_irq *irq;
	int i;
5694

5695 5696 5697
	for (i = 0; i < bp->irq_nvecs; i++) {
		irq = &bp->irq_tbl[i];
		if (irq->requested)
5698
			free_irq(irq->vector, &bp->bnx2_napi[i]);
5699
		irq->requested = 0;
5700
	}
5701
	if (bp->flags & BNX2_FLAG_USING_MSI)
5702
		pci_disable_msi(bp->pdev);
5703
	else if (bp->flags & BNX2_FLAG_USING_MSIX)
5704 5705
		pci_disable_msix(bp->pdev);

5706
	bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5707 5708 5709
}

static void
M
Michael Chan 已提交
5710
bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
5711
{
M
Michael Chan 已提交
5712 5713 5714
	int i, rc;
	struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];

5715 5716 5717 5718
	bnx2_setup_msix_tbl(bp);
	REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
	REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
	REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
M
Michael Chan 已提交
5719 5720 5721 5722

	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
		msix_ent[i].entry = i;
		msix_ent[i].vector = 0;
5723 5724

		strcpy(bp->irq_tbl[i].name, bp->dev->name);
5725
		bp->irq_tbl[i].handler = bnx2_msi_1shot;
M
Michael Chan 已提交
5726 5727 5728 5729 5730 5731
	}

	rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
	if (rc != 0)
		return;

M
Michael Chan 已提交
5732
	bp->irq_nvecs = msix_vecs;
5733
	bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
M
Michael Chan 已提交
5734 5735
	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
		bp->irq_tbl[i].vector = msix_ent[i].vector;
5736 5737 5738 5739 5740
}

static void
bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
{
M
Michael Chan 已提交
5741 5742 5743
	int cpus = num_online_cpus();
	int msix_vecs = min(cpus + 1, RX_MAX_RSS_RINGS);

5744 5745
	bp->irq_tbl[0].handler = bnx2_interrupt;
	strcpy(bp->irq_tbl[0].name, bp->dev->name);
5746 5747 5748
	bp->irq_nvecs = 1;
	bp->irq_tbl[0].vector = bp->pdev->irq;

M
Michael Chan 已提交
5749 5750
	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
		bnx2_enable_msix(bp, msix_vecs);
5751

5752 5753
	if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
	    !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5754
		if (pci_enable_msi(bp->pdev) == 0) {
5755
			bp->flags |= BNX2_FLAG_USING_MSI;
5756
			if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5757
				bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5758 5759 5760
				bp->irq_tbl[0].handler = bnx2_msi_1shot;
			} else
				bp->irq_tbl[0].handler = bnx2_msi;
5761 5762

			bp->irq_tbl[0].vector = bp->pdev->irq;
5763 5764
		}
	}
5765
	bp->num_tx_rings = 1;
M
Michael Chan 已提交
5766
	bp->num_rx_rings = bp->irq_nvecs;
5767 5768
}

5769 5770 5771 5772
/* Called with rtnl_lock */
static int
bnx2_open(struct net_device *dev)
{
M
Michael Chan 已提交
5773
	struct bnx2 *bp = netdev_priv(dev);
5774 5775
	int rc;

5776 5777
	netif_carrier_off(dev);

5778
	bnx2_set_power_state(bp, PCI_D0);
5779 5780
	bnx2_disable_int(bp);

5781 5782
	bnx2_setup_int_mode(bp, disable_msi);
	bnx2_napi_enable(bp);
5783
	rc = bnx2_alloc_mem(bp);
5784 5785
	if (rc)
		goto open_err;
5786

5787
	rc = bnx2_request_irq(bp);
5788 5789
	if (rc)
		goto open_err;
5790

5791
	rc = bnx2_init_nic(bp, 1);
5792 5793
	if (rc)
		goto open_err;
5794

M
Michael Chan 已提交
5795
	mod_timer(&bp->timer, jiffies + bp->current_interval);
5796 5797 5798 5799 5800

	atomic_set(&bp->intr_sem, 0);

	bnx2_enable_int(bp);

5801
	if (bp->flags & BNX2_FLAG_USING_MSI) {
5802 5803 5804 5805 5806 5807 5808 5809 5810 5811 5812
		/* Test MSI to make sure it is working
		 * If MSI test fails, go back to INTx mode
		 */
		if (bnx2_test_intr(bp) != 0) {
			printk(KERN_WARNING PFX "%s: No interrupt was generated"
			       " using MSI, switching to INTx mode. Please"
			       " report this failure to the PCI maintainer"
			       " and include system chipset information.\n",
			       bp->dev->name);

			bnx2_disable_int(bp);
5813
			bnx2_free_irq(bp);
5814

5815 5816
			bnx2_setup_int_mode(bp, 1);

5817
			rc = bnx2_init_nic(bp, 0);
5818

5819 5820 5821
			if (!rc)
				rc = bnx2_request_irq(bp);

5822 5823
			if (rc) {
				del_timer_sync(&bp->timer);
5824
				goto open_err;
5825 5826 5827 5828
			}
			bnx2_enable_int(bp);
		}
	}
5829
	if (bp->flags & BNX2_FLAG_USING_MSI)
5830
		printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5831
	else if (bp->flags & BNX2_FLAG_USING_MSIX)
M
Michael Chan 已提交
5832
		printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5833 5834 5835 5836

	netif_start_queue(dev);

	return 0;
5837 5838 5839 5840 5841 5842 5843

open_err:
	bnx2_napi_disable(bp);
	bnx2_free_skbs(bp);
	bnx2_free_irq(bp);
	bnx2_free_mem(bp);
	return rc;
5844 5845 5846
}

static void
D
David Howells 已提交
5847
bnx2_reset_task(struct work_struct *work)
5848
{
D
David Howells 已提交
5849
	struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5850

5851 5852 5853
	if (!netif_running(bp->dev))
		return;

5854 5855
	bnx2_netif_stop(bp);

5856
	bnx2_init_nic(bp, 1);
5857 5858 5859 5860 5861 5862 5863 5864

	atomic_set(&bp->intr_sem, 1);
	bnx2_netif_start(bp);
}

static void
bnx2_tx_timeout(struct net_device *dev)
{
M
Michael Chan 已提交
5865
	struct bnx2 *bp = netdev_priv(dev);
5866 5867 5868 5869 5870 5871 5872 5873 5874 5875

	/* This allows the netif to be shutdown gracefully before resetting */
	schedule_work(&bp->reset_task);
}

#ifdef BCM_VLAN
/* Called with rtnl_lock */
static void
bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
{
M
Michael Chan 已提交
5876
	struct bnx2 *bp = netdev_priv(dev);
5877 5878 5879 5880 5881 5882 5883 5884 5885 5886

	bnx2_netif_stop(bp);

	bp->vlgrp = vlgrp;
	bnx2_set_rx_mode(dev);

	bnx2_netif_start(bp);
}
#endif

H
Herbert Xu 已提交
5887
/* Called with netif_tx_lock.
M
Michael Chan 已提交
5888 5889
 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
 * netif_wake_queue().
5890 5891 5892 5893
 */
static int
bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
M
Michael Chan 已提交
5894
	struct bnx2 *bp = netdev_priv(dev);
5895 5896 5897 5898 5899 5900
	dma_addr_t mapping;
	struct tx_bd *txbd;
	struct sw_bd *tx_buf;
	u32 len, vlan_tag_flags, last_frag, mss;
	u16 prod, ring_prod;
	int i;
5901 5902
	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
	struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5903

5904
	if (unlikely(bnx2_tx_avail(bp, txr) <
5905
	    (skb_shinfo(skb)->nr_frags + 1))) {
5906 5907 5908 5909 5910 5911 5912
		netif_stop_queue(dev);
		printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
			dev->name);

		return NETDEV_TX_BUSY;
	}
	len = skb_headlen(skb);
5913
	prod = txr->tx_prod;
5914 5915 5916
	ring_prod = TX_RING_IDX(prod);

	vlan_tag_flags = 0;
5917
	if (skb->ip_summed == CHECKSUM_PARTIAL) {
5918 5919 5920
		vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
	}

A
Al Viro 已提交
5921
	if (bp->vlgrp && vlan_tx_tag_present(skb)) {
5922 5923 5924
		vlan_tag_flags |=
			(TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
	}
5925
	if ((mss = skb_shinfo(skb)->gso_size)) {
5926
		u32 tcp_opt_len, ip_tcp_len;
5927
		struct iphdr *iph;
5928 5929 5930

		vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;

5931 5932 5933 5934 5935
		tcp_opt_len = tcp_optlen(skb);

		if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
			u32 tcp_off = skb_transport_offset(skb) -
				      sizeof(struct ipv6hdr) - ETH_HLEN;
5936

5937 5938 5939 5940 5941 5942 5943 5944 5945 5946 5947 5948 5949 5950 5951 5952 5953 5954
			vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
					  TX_BD_FLAGS_SW_FLAGS;
			if (likely(tcp_off == 0))
				vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
			else {
				tcp_off >>= 3;
				vlan_tag_flags |= ((tcp_off & 0x3) <<
						   TX_BD_FLAGS_TCP6_OFF0_SHL) |
						  ((tcp_off & 0x10) <<
						   TX_BD_FLAGS_TCP6_OFF4_SHL);
				mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
			}
		} else {
			if (skb_header_cloned(skb) &&
			    pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
				dev_kfree_skb(skb);
				return NETDEV_TX_OK;
			}
5955

5956 5957 5958 5959 5960 5961 5962 5963 5964 5965 5966 5967 5968
			ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);

			iph = ip_hdr(skb);
			iph->check = 0;
			iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
			tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
								 iph->daddr, 0,
								 IPPROTO_TCP,
								 0);
			if (tcp_opt_len || (iph->ihl > 5)) {
				vlan_tag_flags |= ((iph->ihl - 5) +
						   (tcp_opt_len >> 2)) << 8;
			}
5969
		}
5970
	} else
5971 5972 5973
		mss = 0;

	mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5974

5975
	tx_buf = &txr->tx_buf_ring[ring_prod];
5976 5977 5978
	tx_buf->skb = skb;
	pci_unmap_addr_set(tx_buf, mapping, mapping);

5979
	txbd = &txr->tx_desc_ring[ring_prod];
5980 5981 5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992

	txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
	txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
	txbd->tx_bd_mss_nbytes = len | (mss << 16);
	txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;

	last_frag = skb_shinfo(skb)->nr_frags;

	for (i = 0; i < last_frag; i++) {
		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

		prod = NEXT_TX_BD(prod);
		ring_prod = TX_RING_IDX(prod);
5993
		txbd = &txr->tx_desc_ring[ring_prod];
5994 5995 5996 5997

		len = frag->size;
		mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
			len, PCI_DMA_TODEVICE);
5998
		pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod],
5999 6000 6001 6002 6003 6004 6005 6006 6007 6008 6009
				mapping, mapping);

		txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
		txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
		txbd->tx_bd_mss_nbytes = len | (mss << 16);
		txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;

	}
	txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;

	prod = NEXT_TX_BD(prod);
6010
	txr->tx_prod_bseq += skb->len;
6011

6012 6013
	REG_WR16(bp, txr->tx_bidx_addr, prod);
	REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6014 6015 6016

	mmiowb();

6017
	txr->tx_prod = prod;
6018 6019
	dev->trans_start = jiffies;

6020
	if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
M
Michael Chan 已提交
6021
		netif_stop_queue(dev);
6022
		if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
M
Michael Chan 已提交
6023
			netif_wake_queue(dev);
6024 6025 6026 6027 6028 6029 6030 6031 6032
	}

	return NETDEV_TX_OK;
}

/* Called with rtnl_lock */
static int
bnx2_close(struct net_device *dev)
{
M
Michael Chan 已提交
6033
	struct bnx2 *bp = netdev_priv(dev);
6034 6035
	u32 reset_code;

6036
	cancel_work_sync(&bp->reset_task);
6037

6038
	bnx2_disable_int_sync(bp);
6039
	bnx2_napi_disable(bp);
6040
	del_timer_sync(&bp->timer);
6041
	if (bp->flags & BNX2_FLAG_NO_WOL)
6042
		reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
M
Michael Chan 已提交
6043
	else if (bp->wol)
6044 6045 6046 6047
		reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
	else
		reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
	bnx2_reset_chip(bp, reset_code);
6048
	bnx2_free_irq(bp);
6049 6050 6051 6052
	bnx2_free_skbs(bp);
	bnx2_free_mem(bp);
	bp->link_up = 0;
	netif_carrier_off(bp->dev);
6053
	bnx2_set_power_state(bp, PCI_D3hot);
6054 6055 6056 6057 6058 6059 6060 6061 6062 6063 6064 6065 6066 6067 6068 6069 6070 6071 6072
	return 0;
}

#define GET_NET_STATS64(ctr)					\
	(unsigned long) ((unsigned long) (ctr##_hi) << 32) +	\
	(unsigned long) (ctr##_lo)

#define GET_NET_STATS32(ctr)		\
	(ctr##_lo)

#if (BITS_PER_LONG == 64)
#define GET_NET_STATS	GET_NET_STATS64
#else
#define GET_NET_STATS	GET_NET_STATS32
#endif

static struct net_device_stats *
bnx2_get_stats(struct net_device *dev)
{
M
Michael Chan 已提交
6073
	struct bnx2 *bp = netdev_priv(dev);
6074 6075 6076 6077 6078 6079 6080 6081 6082 6083 6084 6085 6086 6087 6088 6089 6090 6091 6092 6093 6094 6095
	struct statistics_block *stats_blk = bp->stats_blk;
	struct net_device_stats *net_stats = &bp->net_stats;

	if (bp->stats_blk == NULL) {
		return net_stats;
	}
	net_stats->rx_packets =
		GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
		GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
		GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);

	net_stats->tx_packets =
		GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
		GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
		GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);

	net_stats->rx_bytes =
		GET_NET_STATS(stats_blk->stat_IfHCInOctets);

	net_stats->tx_bytes =
		GET_NET_STATS(stats_blk->stat_IfHCOutOctets);

6096
	net_stats->multicast =
6097 6098
		GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);

6099
	net_stats->collisions =
6100 6101
		(unsigned long) stats_blk->stat_EtherStatsCollisions;

6102
	net_stats->rx_length_errors =
6103 6104 6105
		(unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
		stats_blk->stat_EtherStatsOverrsizePkts);

6106
	net_stats->rx_over_errors =
6107 6108
		(unsigned long) stats_blk->stat_IfInMBUFDiscards;

6109
	net_stats->rx_frame_errors =
6110 6111
		(unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;

6112
	net_stats->rx_crc_errors =
6113 6114 6115 6116 6117 6118 6119 6120 6121 6122
		(unsigned long) stats_blk->stat_Dot3StatsFCSErrors;

	net_stats->rx_errors = net_stats->rx_length_errors +
		net_stats->rx_over_errors + net_stats->rx_frame_errors +
		net_stats->rx_crc_errors;

	net_stats->tx_aborted_errors =
    		(unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
		stats_blk->stat_Dot3StatsLateCollisions);

M
Michael Chan 已提交
6123 6124
	if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
	    (CHIP_ID(bp) == CHIP_ID_5708_A0))
6125 6126 6127 6128 6129 6130 6131 6132
		net_stats->tx_carrier_errors = 0;
	else {
		net_stats->tx_carrier_errors =
			(unsigned long)
			stats_blk->stat_Dot3StatsCarrierSenseErrors;
	}

	net_stats->tx_errors =
6133
    		(unsigned long)
6134 6135 6136 6137 6138
		stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
		+
		net_stats->tx_aborted_errors +
		net_stats->tx_carrier_errors;

M
Michael Chan 已提交
6139 6140 6141 6142
	net_stats->rx_missed_errors =
		(unsigned long) (stats_blk->stat_IfInMBUFDiscards +
		stats_blk->stat_FwRxDrop);

6143 6144 6145 6146 6147 6148 6149 6150
	return net_stats;
}

/* All ethtool functions called with rtnl_lock */

static int
bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
M
Michael Chan 已提交
6151
	struct bnx2 *bp = netdev_priv(dev);
6152
	int support_serdes = 0, support_copper = 0;
6153 6154

	cmd->supported = SUPPORTED_Autoneg;
6155
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6156 6157 6158 6159 6160 6161 6162 6163
		support_serdes = 1;
		support_copper = 1;
	} else if (bp->phy_port == PORT_FIBRE)
		support_serdes = 1;
	else
		support_copper = 1;

	if (support_serdes) {
6164 6165
		cmd->supported |= SUPPORTED_1000baseT_Full |
			SUPPORTED_FIBRE;
6166
		if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6167
			cmd->supported |= SUPPORTED_2500baseX_Full;
6168 6169

	}
6170
	if (support_copper) {
6171 6172 6173 6174 6175 6176 6177 6178 6179
		cmd->supported |= SUPPORTED_10baseT_Half |
			SUPPORTED_10baseT_Full |
			SUPPORTED_100baseT_Half |
			SUPPORTED_100baseT_Full |
			SUPPORTED_1000baseT_Full |
			SUPPORTED_TP;

	}

6180 6181
	spin_lock_bh(&bp->phy_lock);
	cmd->port = bp->phy_port;
6182 6183 6184 6185 6186 6187 6188 6189 6190 6191 6192 6193 6194 6195 6196 6197 6198
	cmd->advertising = bp->advertising;

	if (bp->autoneg & AUTONEG_SPEED) {
		cmd->autoneg = AUTONEG_ENABLE;
	}
	else {
		cmd->autoneg = AUTONEG_DISABLE;
	}

	if (netif_carrier_ok(dev)) {
		cmd->speed = bp->line_speed;
		cmd->duplex = bp->duplex;
	}
	else {
		cmd->speed = -1;
		cmd->duplex = -1;
	}
6199
	spin_unlock_bh(&bp->phy_lock);
6200 6201 6202 6203 6204 6205

	cmd->transceiver = XCVR_INTERNAL;
	cmd->phy_address = bp->phy_addr;

	return 0;
}
6206

6207 6208 6209
static int
bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
M
Michael Chan 已提交
6210
	struct bnx2 *bp = netdev_priv(dev);
6211 6212 6213 6214
	u8 autoneg = bp->autoneg;
	u8 req_duplex = bp->req_duplex;
	u16 req_line_speed = bp->req_line_speed;
	u32 advertising = bp->advertising;
6215 6216 6217 6218 6219 6220 6221
	int err = -EINVAL;

	spin_lock_bh(&bp->phy_lock);

	if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
		goto err_out_unlock;

6222 6223
	if (cmd->port != bp->phy_port &&
	    !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6224
		goto err_out_unlock;
6225

6226 6227 6228 6229 6230 6231
	/* If device is down, we can store the settings only if the user
	 * is setting the currently active port.
	 */
	if (!netif_running(dev) && cmd->port != bp->phy_port)
		goto err_out_unlock;

6232 6233 6234
	if (cmd->autoneg == AUTONEG_ENABLE) {
		autoneg |= AUTONEG_SPEED;

6235
		cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6236 6237 6238 6239 6240 6241 6242

		/* allow advertising 1 speed */
		if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
			(cmd->advertising == ADVERTISED_10baseT_Full) ||
			(cmd->advertising == ADVERTISED_100baseT_Half) ||
			(cmd->advertising == ADVERTISED_100baseT_Full)) {

6243 6244
			if (cmd->port == PORT_FIBRE)
				goto err_out_unlock;
6245 6246 6247

			advertising = cmd->advertising;

6248
		} else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6249
			if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6250 6251 6252
			    (cmd->port == PORT_TP))
				goto err_out_unlock;
		} else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6253
			advertising = cmd->advertising;
6254 6255
		else if (cmd->advertising == ADVERTISED_1000baseT_Half)
			goto err_out_unlock;
6256
		else {
6257
			if (cmd->port == PORT_FIBRE)
6258
				advertising = ETHTOOL_ALL_FIBRE_SPEED;
6259
			else
6260 6261 6262 6263 6264
				advertising = ETHTOOL_ALL_COPPER_SPEED;
		}
		advertising |= ADVERTISED_Autoneg;
	}
	else {
6265
		if (cmd->port == PORT_FIBRE) {
M
Michael Chan 已提交
6266 6267 6268
			if ((cmd->speed != SPEED_1000 &&
			     cmd->speed != SPEED_2500) ||
			    (cmd->duplex != DUPLEX_FULL))
6269
				goto err_out_unlock;
M
Michael Chan 已提交
6270 6271

			if (cmd->speed == SPEED_2500 &&
6272
			    !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6273
				goto err_out_unlock;
6274
		}
6275 6276 6277
		else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
			goto err_out_unlock;

6278 6279 6280 6281 6282 6283 6284 6285 6286 6287 6288
		autoneg &= ~AUTONEG_SPEED;
		req_line_speed = cmd->speed;
		req_duplex = cmd->duplex;
		advertising = 0;
	}

	bp->autoneg = autoneg;
	bp->advertising = advertising;
	bp->req_line_speed = req_line_speed;
	bp->req_duplex = req_duplex;

6289 6290 6291 6292 6293 6294
	err = 0;
	/* If device is down, the new settings will be picked up when it is
	 * brought up.
	 */
	if (netif_running(dev))
		err = bnx2_setup_phy(bp, cmd->port);
6295

6296
err_out_unlock:
6297
	spin_unlock_bh(&bp->phy_lock);
6298

6299
	return err;
6300 6301 6302 6303 6304
}

static void
bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
M
Michael Chan 已提交
6305
	struct bnx2 *bp = netdev_priv(dev);
6306 6307 6308 6309

	strcpy(info->driver, DRV_MODULE_NAME);
	strcpy(info->version, DRV_MODULE_VERSION);
	strcpy(info->bus_info, pci_name(bp->pdev));
6310
	strcpy(info->fw_version, bp->fw_version);
6311 6312
}

M
Michael Chan 已提交
6313 6314 6315 6316 6317 6318 6319 6320 6321 6322 6323 6324 6325 6326 6327 6328 6329 6330 6331 6332 6333 6334 6335 6336 6337 6338 6339 6340 6341 6342 6343 6344 6345 6346 6347 6348 6349 6350 6351 6352 6353 6354 6355 6356 6357 6358 6359 6360 6361 6362 6363 6364 6365 6366 6367 6368 6369 6370
#define BNX2_REGDUMP_LEN		(32 * 1024)

static int
bnx2_get_regs_len(struct net_device *dev)
{
	return BNX2_REGDUMP_LEN;
}

static void
bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
{
	u32 *p = _p, i, offset;
	u8 *orig_p = _p;
	struct bnx2 *bp = netdev_priv(dev);
	u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
				 0x0800, 0x0880, 0x0c00, 0x0c10,
				 0x0c30, 0x0d08, 0x1000, 0x101c,
				 0x1040, 0x1048, 0x1080, 0x10a4,
				 0x1400, 0x1490, 0x1498, 0x14f0,
				 0x1500, 0x155c, 0x1580, 0x15dc,
				 0x1600, 0x1658, 0x1680, 0x16d8,
				 0x1800, 0x1820, 0x1840, 0x1854,
				 0x1880, 0x1894, 0x1900, 0x1984,
				 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
				 0x1c80, 0x1c94, 0x1d00, 0x1d84,
				 0x2000, 0x2030, 0x23c0, 0x2400,
				 0x2800, 0x2820, 0x2830, 0x2850,
				 0x2b40, 0x2c10, 0x2fc0, 0x3058,
				 0x3c00, 0x3c94, 0x4000, 0x4010,
				 0x4080, 0x4090, 0x43c0, 0x4458,
				 0x4c00, 0x4c18, 0x4c40, 0x4c54,
				 0x4fc0, 0x5010, 0x53c0, 0x5444,
				 0x5c00, 0x5c18, 0x5c80, 0x5c90,
				 0x5fc0, 0x6000, 0x6400, 0x6428,
				 0x6800, 0x6848, 0x684c, 0x6860,
				 0x6888, 0x6910, 0x8000 };

	regs->version = 0;

	memset(p, 0, BNX2_REGDUMP_LEN);

	if (!netif_running(bp->dev))
		return;

	i = 0;
	offset = reg_boundaries[0];
	p += offset;
	while (offset < BNX2_REGDUMP_LEN) {
		*p++ = REG_RD(bp, offset);
		offset += 4;
		if (offset == reg_boundaries[i + 1]) {
			offset = reg_boundaries[i + 2];
			p = (u32 *) (orig_p + offset);
			i += 2;
		}
	}
}

6371 6372 6373
static void
bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
M
Michael Chan 已提交
6374
	struct bnx2 *bp = netdev_priv(dev);
6375

6376
	if (bp->flags & BNX2_FLAG_NO_WOL) {
6377 6378 6379 6380 6381 6382 6383 6384 6385 6386 6387 6388 6389 6390 6391 6392
		wol->supported = 0;
		wol->wolopts = 0;
	}
	else {
		wol->supported = WAKE_MAGIC;
		if (bp->wol)
			wol->wolopts = WAKE_MAGIC;
		else
			wol->wolopts = 0;
	}
	memset(&wol->sopass, 0, sizeof(wol->sopass));
}

static int
bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
M
Michael Chan 已提交
6393
	struct bnx2 *bp = netdev_priv(dev);
6394 6395 6396 6397 6398

	if (wol->wolopts & ~WAKE_MAGIC)
		return -EINVAL;

	if (wol->wolopts & WAKE_MAGIC) {
6399
		if (bp->flags & BNX2_FLAG_NO_WOL)
6400 6401 6402 6403 6404 6405 6406 6407 6408 6409 6410 6411 6412
			return -EINVAL;

		bp->wol = 1;
	}
	else {
		bp->wol = 0;
	}
	return 0;
}

static int
bnx2_nway_reset(struct net_device *dev)
{
M
Michael Chan 已提交
6413
	struct bnx2 *bp = netdev_priv(dev);
6414 6415 6416 6417 6418 6419
	u32 bmcr;

	if (!(bp->autoneg & AUTONEG_SPEED)) {
		return -EINVAL;
	}

6420
	spin_lock_bh(&bp->phy_lock);
6421

6422
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6423 6424 6425 6426 6427 6428 6429
		int rc;

		rc = bnx2_setup_remote_phy(bp, bp->phy_port);
		spin_unlock_bh(&bp->phy_lock);
		return rc;
	}

6430
	/* Force a link down visible on the other side */
6431
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6432
		bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6433
		spin_unlock_bh(&bp->phy_lock);
6434 6435 6436

		msleep(20);

6437
		spin_lock_bh(&bp->phy_lock);
6438 6439 6440 6441

		bp->current_interval = SERDES_AN_TIMEOUT;
		bp->serdes_an_pending = 1;
		mod_timer(&bp->timer, jiffies + bp->current_interval);
6442 6443
	}

6444
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6445
	bmcr &= ~BMCR_LOOPBACK;
6446
	bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6447

6448
	spin_unlock_bh(&bp->phy_lock);
6449 6450 6451 6452 6453 6454 6455

	return 0;
}

static int
bnx2_get_eeprom_len(struct net_device *dev)
{
M
Michael Chan 已提交
6456
	struct bnx2 *bp = netdev_priv(dev);
6457

M
Michael Chan 已提交
6458
	if (bp->flash_info == NULL)
6459 6460
		return 0;

M
Michael Chan 已提交
6461
	return (int) bp->flash_size;
6462 6463 6464 6465 6466 6467
}

static int
bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
		u8 *eebuf)
{
M
Michael Chan 已提交
6468
	struct bnx2 *bp = netdev_priv(dev);
6469 6470
	int rc;

6471
	/* parameters already validated in ethtool_get_eeprom */
6472 6473 6474 6475 6476 6477 6478 6479 6480 6481

	rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);

	return rc;
}

static int
bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
		u8 *eebuf)
{
M
Michael Chan 已提交
6482
	struct bnx2 *bp = netdev_priv(dev);
6483 6484
	int rc;

6485
	/* parameters already validated in ethtool_set_eeprom */
6486 6487 6488 6489 6490 6491 6492 6493 6494

	rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);

	return rc;
}

static int
bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
{
M
Michael Chan 已提交
6495
	struct bnx2 *bp = netdev_priv(dev);
6496 6497 6498 6499 6500 6501 6502 6503 6504 6505 6506 6507 6508 6509 6510 6511 6512 6513 6514 6515 6516

	memset(coal, 0, sizeof(struct ethtool_coalesce));

	coal->rx_coalesce_usecs = bp->rx_ticks;
	coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
	coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
	coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;

	coal->tx_coalesce_usecs = bp->tx_ticks;
	coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
	coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
	coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;

	coal->stats_block_coalesce_usecs = bp->stats_ticks;

	return 0;
}

static int
bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
{
M
Michael Chan 已提交
6517
	struct bnx2 *bp = netdev_priv(dev);
6518 6519 6520 6521

	bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
	if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;

6522
	bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6523 6524 6525 6526 6527 6528 6529 6530 6531 6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542 6543 6544 6545
	if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;

	bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
	if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;

	bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
	if (bp->rx_quick_cons_trip_int > 0xff)
		bp->rx_quick_cons_trip_int = 0xff;

	bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
	if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;

	bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
	if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;

	bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
	if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;

	bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
	if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
		0xff;

	bp->stats_ticks = coal->stats_block_coalesce_usecs;
6546 6547 6548 6549
	if (CHIP_NUM(bp) == CHIP_NUM_5708) {
		if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
			bp->stats_ticks = USEC_PER_SEC;
	}
6550 6551 6552
	if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
		bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
	bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6553 6554 6555

	if (netif_running(bp->dev)) {
		bnx2_netif_stop(bp);
6556
		bnx2_init_nic(bp, 0);
6557 6558 6559 6560 6561 6562 6563 6564 6565
		bnx2_netif_start(bp);
	}

	return 0;
}

static void
bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
{
M
Michael Chan 已提交
6566
	struct bnx2 *bp = netdev_priv(dev);
6567

6568
	ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6569
	ering->rx_mini_max_pending = 0;
6570
	ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6571 6572 6573

	ering->rx_pending = bp->rx_ring_size;
	ering->rx_mini_pending = 0;
6574
	ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6575 6576 6577 6578 6579 6580

	ering->tx_max_pending = MAX_TX_DESC_CNT;
	ering->tx_pending = bp->tx_ring_size;
}

static int
6581
bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6582
{
6583 6584 6585 6586 6587 6588 6589
	if (netif_running(bp->dev)) {
		bnx2_netif_stop(bp);
		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
		bnx2_free_skbs(bp);
		bnx2_free_mem(bp);
	}

6590 6591
	bnx2_set_rx_ring_size(bp, rx);
	bp->tx_ring_size = tx;
6592 6593

	if (netif_running(bp->dev)) {
6594 6595 6596 6597 6598
		int rc;

		rc = bnx2_alloc_mem(bp);
		if (rc)
			return rc;
6599
		bnx2_init_nic(bp, 0);
6600 6601 6602 6603 6604
		bnx2_netif_start(bp);
	}
	return 0;
}

6605 6606 6607 6608 6609 6610 6611 6612 6613 6614 6615 6616 6617 6618 6619 6620
static int
bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
{
	struct bnx2 *bp = netdev_priv(dev);
	int rc;

	if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
		(ering->tx_pending > MAX_TX_DESC_CNT) ||
		(ering->tx_pending <= MAX_SKB_FRAGS)) {

		return -EINVAL;
	}
	rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
	return rc;
}

6621 6622 6623
static void
bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
{
M
Michael Chan 已提交
6624
	struct bnx2 *bp = netdev_priv(dev);
6625 6626 6627 6628 6629 6630 6631 6632 6633

	epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
	epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
	epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
}

static int
bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
{
M
Michael Chan 已提交
6634
	struct bnx2 *bp = netdev_priv(dev);
6635 6636 6637 6638 6639 6640 6641 6642 6643 6644 6645 6646 6647 6648

	bp->req_flow_ctrl = 0;
	if (epause->rx_pause)
		bp->req_flow_ctrl |= FLOW_CTRL_RX;
	if (epause->tx_pause)
		bp->req_flow_ctrl |= FLOW_CTRL_TX;

	if (epause->autoneg) {
		bp->autoneg |= AUTONEG_FLOW_CTRL;
	}
	else {
		bp->autoneg &= ~AUTONEG_FLOW_CTRL;
	}

6649
	spin_lock_bh(&bp->phy_lock);
6650

6651
	bnx2_setup_phy(bp, bp->phy_port);
6652

6653
	spin_unlock_bh(&bp->phy_lock);
6654 6655 6656 6657 6658 6659 6660

	return 0;
}

static u32
bnx2_get_rx_csum(struct net_device *dev)
{
M
Michael Chan 已提交
6661
	struct bnx2 *bp = netdev_priv(dev);
6662 6663 6664 6665 6666 6667 6668

	return bp->rx_csum;
}

static int
bnx2_set_rx_csum(struct net_device *dev, u32 data)
{
M
Michael Chan 已提交
6669
	struct bnx2 *bp = netdev_priv(dev);
6670 6671 6672 6673 6674

	bp->rx_csum = data;
	return 0;
}

M
Michael Chan 已提交
6675 6676 6677
static int
bnx2_set_tso(struct net_device *dev, u32 data)
{
6678 6679 6680
	struct bnx2 *bp = netdev_priv(dev);

	if (data) {
M
Michael Chan 已提交
6681
		dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6682 6683 6684 6685 6686
		if (CHIP_NUM(bp) == CHIP_NUM_5709)
			dev->features |= NETIF_F_TSO6;
	} else
		dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
				   NETIF_F_TSO_ECN);
M
Michael Chan 已提交
6687 6688 6689
	return 0;
}

M
Michael Chan 已提交
6690
#define BNX2_NUM_STATS 46
6691

6692
static struct {
6693 6694 6695 6696 6697 6698 6699 6700 6701 6702 6703 6704 6705 6706 6707 6708 6709 6710 6711 6712 6713 6714 6715 6716 6717 6718 6719 6720 6721 6722 6723 6724 6725 6726 6727 6728 6729 6730 6731 6732 6733 6734 6735 6736 6737 6738 6739
	char string[ETH_GSTRING_LEN];
} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
	{ "rx_bytes" },
	{ "rx_error_bytes" },
	{ "tx_bytes" },
	{ "tx_error_bytes" },
	{ "rx_ucast_packets" },
	{ "rx_mcast_packets" },
	{ "rx_bcast_packets" },
	{ "tx_ucast_packets" },
	{ "tx_mcast_packets" },
	{ "tx_bcast_packets" },
	{ "tx_mac_errors" },
	{ "tx_carrier_errors" },
	{ "rx_crc_errors" },
	{ "rx_align_errors" },
	{ "tx_single_collisions" },
	{ "tx_multi_collisions" },
	{ "tx_deferred" },
	{ "tx_excess_collisions" },
	{ "tx_late_collisions" },
	{ "tx_total_collisions" },
	{ "rx_fragments" },
	{ "rx_jabbers" },
	{ "rx_undersize_packets" },
	{ "rx_oversize_packets" },
	{ "rx_64_byte_packets" },
	{ "rx_65_to_127_byte_packets" },
	{ "rx_128_to_255_byte_packets" },
	{ "rx_256_to_511_byte_packets" },
	{ "rx_512_to_1023_byte_packets" },
	{ "rx_1024_to_1522_byte_packets" },
	{ "rx_1523_to_9022_byte_packets" },
	{ "tx_64_byte_packets" },
	{ "tx_65_to_127_byte_packets" },
	{ "tx_128_to_255_byte_packets" },
	{ "tx_256_to_511_byte_packets" },
	{ "tx_512_to_1023_byte_packets" },
	{ "tx_1024_to_1522_byte_packets" },
	{ "tx_1523_to_9022_byte_packets" },
	{ "rx_xon_frames" },
	{ "rx_xoff_frames" },
	{ "tx_xon_frames" },
	{ "tx_xoff_frames" },
	{ "rx_mac_ctrl_frames" },
	{ "rx_filtered_packets" },
	{ "rx_discards" },
M
Michael Chan 已提交
6740
	{ "rx_fw_discards" },
6741 6742 6743 6744
};

#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)

6745
static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6746 6747 6748 6749 6750 6751 6752 6753 6754 6755 6756
    STATS_OFFSET32(stat_IfHCInOctets_hi),
    STATS_OFFSET32(stat_IfHCInBadOctets_hi),
    STATS_OFFSET32(stat_IfHCOutOctets_hi),
    STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
    STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
    STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
    STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
    STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
    STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
    STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
    STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6757 6758 6759 6760 6761 6762 6763 6764 6765 6766 6767 6768 6769 6770 6771 6772 6773 6774 6775 6776 6777 6778 6779 6780 6781 6782 6783 6784 6785 6786 6787 6788 6789 6790
    STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
    STATS_OFFSET32(stat_Dot3StatsFCSErrors),
    STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
    STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
    STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
    STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
    STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
    STATS_OFFSET32(stat_Dot3StatsLateCollisions),
    STATS_OFFSET32(stat_EtherStatsCollisions),
    STATS_OFFSET32(stat_EtherStatsFragments),
    STATS_OFFSET32(stat_EtherStatsJabbers),
    STATS_OFFSET32(stat_EtherStatsUndersizePkts),
    STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
    STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
    STATS_OFFSET32(stat_XonPauseFramesReceived),
    STATS_OFFSET32(stat_XoffPauseFramesReceived),
    STATS_OFFSET32(stat_OutXonSent),
    STATS_OFFSET32(stat_OutXoffSent),
    STATS_OFFSET32(stat_MacControlFramesReceived),
    STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
    STATS_OFFSET32(stat_IfInMBUFDiscards),
M
Michael Chan 已提交
6791
    STATS_OFFSET32(stat_FwRxDrop),
6792 6793 6794 6795
};

/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
 * skipped because of errata.
6796
 */
6797
static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6798 6799 6800 6801
	8,0,8,8,8,8,8,8,8,8,
	4,0,4,4,4,4,4,4,4,4,
	4,4,4,4,4,4,4,4,4,4,
	4,4,4,4,4,4,4,4,4,4,
M
Michael Chan 已提交
6802
	4,4,4,4,4,4,
6803 6804
};

M
Michael Chan 已提交
6805 6806 6807 6808 6809
static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
	8,0,8,8,8,8,8,8,8,8,
	4,4,4,4,4,4,4,4,4,4,
	4,4,4,4,4,4,4,4,4,4,
	4,4,4,4,4,4,4,4,4,4,
M
Michael Chan 已提交
6810
	4,4,4,4,4,4,
M
Michael Chan 已提交
6811 6812
};

6813 6814
#define BNX2_NUM_TESTS 6

6815
static struct {
6816 6817 6818 6819 6820 6821 6822 6823 6824 6825 6826
	char string[ETH_GSTRING_LEN];
} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
	{ "register_test (offline)" },
	{ "memory_test (offline)" },
	{ "loopback_test (offline)" },
	{ "nvram_test (online)" },
	{ "interrupt_test (online)" },
	{ "link_test (online)" },
};

static int
6827
bnx2_get_sset_count(struct net_device *dev, int sset)
6828
{
6829 6830 6831 6832 6833 6834 6835 6836
	switch (sset) {
	case ETH_SS_TEST:
		return BNX2_NUM_TESTS;
	case ETH_SS_STATS:
		return BNX2_NUM_STATS;
	default:
		return -EOPNOTSUPP;
	}
6837 6838 6839 6840 6841
}

static void
bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
{
M
Michael Chan 已提交
6842
	struct bnx2 *bp = netdev_priv(dev);
6843 6844 6845

	memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
	if (etest->flags & ETH_TEST_FL_OFFLINE) {
M
Michael Chan 已提交
6846 6847
		int i;

6848 6849 6850 6851 6852 6853 6854 6855 6856 6857 6858 6859
		bnx2_netif_stop(bp);
		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
		bnx2_free_skbs(bp);

		if (bnx2_test_registers(bp) != 0) {
			buf[0] = 1;
			etest->flags |= ETH_TEST_FL_FAILED;
		}
		if (bnx2_test_memory(bp) != 0) {
			buf[1] = 1;
			etest->flags |= ETH_TEST_FL_FAILED;
		}
M
Michael Chan 已提交
6860
		if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6861 6862 6863 6864 6865 6866
			etest->flags |= ETH_TEST_FL_FAILED;

		if (!netif_running(bp->dev)) {
			bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
		}
		else {
6867
			bnx2_init_nic(bp, 1);
6868 6869 6870 6871
			bnx2_netif_start(bp);
		}

		/* wait for link up */
M
Michael Chan 已提交
6872 6873 6874 6875 6876
		for (i = 0; i < 7; i++) {
			if (bp->link_up)
				break;
			msleep_interruptible(1000);
		}
6877 6878 6879 6880 6881 6882 6883 6884 6885 6886 6887 6888 6889 6890 6891 6892 6893 6894 6895 6896 6897 6898 6899 6900 6901 6902 6903 6904 6905 6906 6907 6908 6909 6910 6911 6912 6913
	}

	if (bnx2_test_nvram(bp) != 0) {
		buf[3] = 1;
		etest->flags |= ETH_TEST_FL_FAILED;
	}
	if (bnx2_test_intr(bp) != 0) {
		buf[4] = 1;
		etest->flags |= ETH_TEST_FL_FAILED;
	}

	if (bnx2_test_link(bp) != 0) {
		buf[5] = 1;
		etest->flags |= ETH_TEST_FL_FAILED;

	}
}

static void
bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
{
	switch (stringset) {
	case ETH_SS_STATS:
		memcpy(buf, bnx2_stats_str_arr,
			sizeof(bnx2_stats_str_arr));
		break;
	case ETH_SS_TEST:
		memcpy(buf, bnx2_tests_str_arr,
			sizeof(bnx2_tests_str_arr));
		break;
	}
}

static void
bnx2_get_ethtool_stats(struct net_device *dev,
		struct ethtool_stats *stats, u64 *buf)
{
M
Michael Chan 已提交
6914
	struct bnx2 *bp = netdev_priv(dev);
6915 6916
	int i;
	u32 *hw_stats = (u32 *) bp->stats_blk;
6917
	u8 *stats_len_arr = NULL;
6918 6919 6920 6921 6922 6923

	if (hw_stats == NULL) {
		memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
		return;
	}

M
Michael Chan 已提交
6924 6925 6926 6927
	if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
	    (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
	    (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
	    (CHIP_ID(bp) == CHIP_ID_5708_A0))
6928
		stats_len_arr = bnx2_5706_stats_len_arr;
M
Michael Chan 已提交
6929 6930
	else
		stats_len_arr = bnx2_5708_stats_len_arr;
6931 6932 6933 6934 6935 6936 6937 6938 6939 6940 6941 6942 6943 6944 6945 6946 6947 6948 6949 6950 6951 6952 6953

	for (i = 0; i < BNX2_NUM_STATS; i++) {
		if (stats_len_arr[i] == 0) {
			/* skip this counter */
			buf[i] = 0;
			continue;
		}
		if (stats_len_arr[i] == 4) {
			/* 4-byte counter */
			buf[i] = (u64)
				*(hw_stats + bnx2_stats_offset_arr[i]);
			continue;
		}
		/* 8-byte counter */
		buf[i] = (((u64) *(hw_stats +
					bnx2_stats_offset_arr[i])) << 32) +
				*(hw_stats + bnx2_stats_offset_arr[i] + 1);
	}
}

static int
bnx2_phys_id(struct net_device *dev, u32 data)
{
M
Michael Chan 已提交
6954
	struct bnx2 *bp = netdev_priv(dev);
6955 6956 6957 6958 6959 6960 6961 6962 6963 6964 6965 6966 6967 6968 6969 6970 6971 6972 6973 6974 6975 6976 6977 6978 6979 6980 6981 6982 6983 6984
	int i;
	u32 save;

	if (data == 0)
		data = 2;

	save = REG_RD(bp, BNX2_MISC_CFG);
	REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);

	for (i = 0; i < (data * 2); i++) {
		if ((i % 2) == 0) {
			REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
		}
		else {
			REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
				BNX2_EMAC_LED_1000MB_OVERRIDE |
				BNX2_EMAC_LED_100MB_OVERRIDE |
				BNX2_EMAC_LED_10MB_OVERRIDE |
				BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
				BNX2_EMAC_LED_TRAFFIC);
		}
		msleep_interruptible(500);
		if (signal_pending(current))
			break;
	}
	REG_WR(bp, BNX2_EMAC_LED, 0);
	REG_WR(bp, BNX2_MISC_CFG, save);
	return 0;
}

6985 6986 6987 6988 6989 6990
static int
bnx2_set_tx_csum(struct net_device *dev, u32 data)
{
	struct bnx2 *bp = netdev_priv(dev);

	if (CHIP_NUM(bp) == CHIP_NUM_5709)
6991
		return (ethtool_op_set_tx_ipv6_csum(dev, data));
6992 6993 6994 6995
	else
		return (ethtool_op_set_tx_csum(dev, data));
}

6996
static const struct ethtool_ops bnx2_ethtool_ops = {
6997 6998 6999
	.get_settings		= bnx2_get_settings,
	.set_settings		= bnx2_set_settings,
	.get_drvinfo		= bnx2_get_drvinfo,
M
Michael Chan 已提交
7000 7001
	.get_regs_len		= bnx2_get_regs_len,
	.get_regs		= bnx2_get_regs,
7002 7003 7004 7005 7006 7007 7008 7009 7010 7011 7012 7013 7014 7015 7016
	.get_wol		= bnx2_get_wol,
	.set_wol		= bnx2_set_wol,
	.nway_reset		= bnx2_nway_reset,
	.get_link		= ethtool_op_get_link,
	.get_eeprom_len		= bnx2_get_eeprom_len,
	.get_eeprom		= bnx2_get_eeprom,
	.set_eeprom		= bnx2_set_eeprom,
	.get_coalesce		= bnx2_get_coalesce,
	.set_coalesce		= bnx2_set_coalesce,
	.get_ringparam		= bnx2_get_ringparam,
	.set_ringparam		= bnx2_set_ringparam,
	.get_pauseparam		= bnx2_get_pauseparam,
	.set_pauseparam		= bnx2_set_pauseparam,
	.get_rx_csum		= bnx2_get_rx_csum,
	.set_rx_csum		= bnx2_set_rx_csum,
7017
	.set_tx_csum		= bnx2_set_tx_csum,
7018
	.set_sg			= ethtool_op_set_sg,
M
Michael Chan 已提交
7019
	.set_tso		= bnx2_set_tso,
7020 7021 7022 7023
	.self_test		= bnx2_self_test,
	.get_strings		= bnx2_get_strings,
	.phys_id		= bnx2_phys_id,
	.get_ethtool_stats	= bnx2_get_ethtool_stats,
7024
	.get_sset_count		= bnx2_get_sset_count,
7025 7026 7027 7028 7029 7030
};

/* Called with rtnl_lock */
static int
bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
7031
	struct mii_ioctl_data *data = if_mii(ifr);
M
Michael Chan 已提交
7032
	struct bnx2 *bp = netdev_priv(dev);
7033 7034 7035 7036 7037 7038 7039 7040 7041 7042
	int err;

	switch(cmd) {
	case SIOCGMIIPHY:
		data->phy_id = bp->phy_addr;

		/* fallthru */
	case SIOCGMIIREG: {
		u32 mii_regval;

7043
		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7044 7045
			return -EOPNOTSUPP;

7046 7047 7048
		if (!netif_running(dev))
			return -EAGAIN;

7049
		spin_lock_bh(&bp->phy_lock);
7050
		err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7051
		spin_unlock_bh(&bp->phy_lock);
7052 7053 7054 7055 7056 7057 7058 7059 7060 7061

		data->val_out = mii_regval;

		return err;
	}

	case SIOCSMIIREG:
		if (!capable(CAP_NET_ADMIN))
			return -EPERM;

7062
		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7063 7064
			return -EOPNOTSUPP;

7065 7066 7067
		if (!netif_running(dev))
			return -EAGAIN;

7068
		spin_lock_bh(&bp->phy_lock);
7069
		err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7070
		spin_unlock_bh(&bp->phy_lock);
7071 7072 7073 7074 7075 7076 7077 7078 7079 7080 7081 7082 7083 7084 7085

		return err;

	default:
		/* do nothing */
		break;
	}
	return -EOPNOTSUPP;
}

/* Called with rtnl_lock */
static int
bnx2_change_mac_addr(struct net_device *dev, void *p)
{
	struct sockaddr *addr = p;
M
Michael Chan 已提交
7086
	struct bnx2 *bp = netdev_priv(dev);
7087

7088 7089 7090
	if (!is_valid_ether_addr(addr->sa_data))
		return -EINVAL;

7091 7092 7093 7094 7095 7096 7097 7098 7099 7100 7101
	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
	if (netif_running(dev))
		bnx2_set_mac_addr(bp);

	return 0;
}

/* Called with rtnl_lock */
static int
bnx2_change_mtu(struct net_device *dev, int new_mtu)
{
M
Michael Chan 已提交
7102
	struct bnx2 *bp = netdev_priv(dev);
7103 7104 7105 7106 7107 7108

	if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
		((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
		return -EINVAL;

	dev->mtu = new_mtu;
7109
	return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7110 7111 7112 7113 7114 7115
}

#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
static void
poll_bnx2(struct net_device *dev)
{
M
Michael Chan 已提交
7116
	struct bnx2 *bp = netdev_priv(dev);
7117 7118

	disable_irq(bp->pdev->irq);
7119
	bnx2_interrupt(bp->pdev->irq, dev);
7120 7121 7122 7123
	enable_irq(bp->pdev->irq);
}
#endif

7124 7125 7126 7127 7128 7129 7130 7131 7132 7133
static void __devinit
bnx2_get_5709_media(struct bnx2 *bp)
{
	u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
	u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
	u32 strap;

	if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
		return;
	else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7134
		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7135 7136 7137 7138 7139 7140 7141 7142 7143 7144 7145 7146 7147
		return;
	}

	if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
		strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
	else
		strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;

	if (PCI_FUNC(bp->pdev->devfn) == 0) {
		switch (strap) {
		case 0x4:
		case 0x5:
		case 0x6:
7148
			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7149 7150 7151 7152 7153 7154 7155
			return;
		}
	} else {
		switch (strap) {
		case 0x1:
		case 0x2:
		case 0x4:
7156
			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7157 7158 7159 7160 7161
			return;
		}
	}
}

7162 7163 7164 7165 7166 7167 7168 7169 7170
static void __devinit
bnx2_get_pci_speed(struct bnx2 *bp)
{
	u32 reg;

	reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
	if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
		u32 clkreg;

7171
		bp->flags |= BNX2_FLAG_PCIX;
7172 7173 7174 7175 7176 7177 7178 7179 7180 7181 7182 7183 7184 7185 7186 7187 7188 7189 7190 7191 7192 7193 7194 7195 7196 7197 7198 7199 7200 7201 7202 7203 7204 7205 7206 7207 7208 7209

		clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);

		clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
		switch (clkreg) {
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
			bp->bus_speed_mhz = 133;
			break;

		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
			bp->bus_speed_mhz = 100;
			break;

		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
			bp->bus_speed_mhz = 66;
			break;

		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
			bp->bus_speed_mhz = 50;
			break;

		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
			bp->bus_speed_mhz = 33;
			break;
		}
	}
	else {
		if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
			bp->bus_speed_mhz = 66;
		else
			bp->bus_speed_mhz = 33;
	}

	if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7210
		bp->flags |= BNX2_FLAG_PCI_32BIT;
7211 7212 7213

}

7214 7215 7216 7217 7218
static int __devinit
bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
{
	struct bnx2 *bp;
	unsigned long mem_len;
7219
	int rc, i, j;
7220
	u32 reg;
7221
	u64 dma_mask, persist_dma_mask;
7222 7223

	SET_NETDEV_DEV(dev, &pdev->dev);
M
Michael Chan 已提交
7224
	bp = netdev_priv(dev);
7225 7226 7227 7228 7229 7230 7231

	bp->flags = 0;
	bp->phy_flags = 0;

	/* enable device (incl. PCI PM wakeup), and bus-mastering */
	rc = pci_enable_device(pdev);
	if (rc) {
7232
		dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7233 7234 7235 7236
		goto err_out;
	}

	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7237
		dev_err(&pdev->dev,
7238
			"Cannot find PCI device base address, aborting.\n");
7239 7240 7241 7242 7243 7244
		rc = -ENODEV;
		goto err_out_disable;
	}

	rc = pci_request_regions(pdev, DRV_MODULE_NAME);
	if (rc) {
7245
		dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7246 7247 7248 7249
		goto err_out_disable;
	}

	pci_set_master(pdev);
W
Wendy Xiong 已提交
7250
	pci_save_state(pdev);
7251 7252 7253

	bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
	if (bp->pm_cap == 0) {
7254
		dev_err(&pdev->dev,
7255
			"Cannot find power management capability, aborting.\n");
7256 7257 7258 7259 7260 7261 7262 7263
		rc = -EIO;
		goto err_out_release;
	}

	bp->dev = dev;
	bp->pdev = pdev;

	spin_lock_init(&bp->phy_lock);
M
Michael Chan 已提交
7264
	spin_lock_init(&bp->indirect_lock);
D
David Howells 已提交
7265
	INIT_WORK(&bp->reset_task, bnx2_reset_task);
7266 7267

	dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
M
Michael Chan 已提交
7268
	mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
7269 7270 7271 7272 7273 7274
	dev->mem_end = dev->mem_start + mem_len;
	dev->irq = pdev->irq;

	bp->regview = ioremap_nocache(dev->base_addr, mem_len);

	if (!bp->regview) {
7275
		dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7276 7277 7278 7279 7280 7281 7282 7283 7284 7285 7286 7287
		rc = -ENOMEM;
		goto err_out_release;
	}

	/* Configure byte swap and enable write to the reg_window registers.
	 * Rely on CPU to do target byte swapping on big endian systems
	 * The chip's target access swapping will not swap all accesses
	 */
	pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
			       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
			       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);

7288
	bnx2_set_power_state(bp, PCI_D0);
7289 7290 7291

	bp->chip_id = REG_RD(bp, BNX2_MISC_ID);

7292 7293 7294 7295 7296 7297 7298
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
			dev_err(&pdev->dev,
				"Cannot find PCIE capability, aborting.\n");
			rc = -EIO;
			goto err_out_unmap;
		}
7299
		bp->flags |= BNX2_FLAG_PCIE;
7300
		if (CHIP_REV(bp) == CHIP_REV_Ax)
7301
			bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7302
	} else {
M
Michael Chan 已提交
7303 7304 7305 7306 7307 7308 7309 7310 7311
		bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
		if (bp->pcix_cap == 0) {
			dev_err(&pdev->dev,
				"Cannot find PCIX capability, aborting.\n");
			rc = -EIO;
			goto err_out_unmap;
		}
	}

7312 7313
	if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
		if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7314
			bp->flags |= BNX2_FLAG_MSIX_CAP;
7315 7316
	}

7317 7318
	if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
		if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7319
			bp->flags |= BNX2_FLAG_MSI_CAP;
7320 7321
	}

7322 7323 7324 7325 7326 7327 7328 7329 7330 7331 7332 7333 7334 7335 7336 7337 7338 7339 7340 7341
	/* 5708 cannot support DMA addresses > 40-bit.  */
	if (CHIP_NUM(bp) == CHIP_NUM_5708)
		persist_dma_mask = dma_mask = DMA_40BIT_MASK;
	else
		persist_dma_mask = dma_mask = DMA_64BIT_MASK;

	/* Configure DMA attributes. */
	if (pci_set_dma_mask(pdev, dma_mask) == 0) {
		dev->features |= NETIF_F_HIGHDMA;
		rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
		if (rc) {
			dev_err(&pdev->dev,
				"pci_set_consistent_dma_mask failed, aborting.\n");
			goto err_out_unmap;
		}
	} else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
		dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
		goto err_out_unmap;
	}

7342
	if (!(bp->flags & BNX2_FLAG_PCIE))
7343
		bnx2_get_pci_speed(bp);
7344 7345 7346 7347 7348 7349 7350 7351

	/* 5706A0 may falsely detect SERR and PERR. */
	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
		reg = REG_RD(bp, PCI_COMMAND);
		reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
		REG_WR(bp, PCI_COMMAND, reg);
	}
	else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7352
		!(bp->flags & BNX2_FLAG_PCIX)) {
7353

7354
		dev_err(&pdev->dev,
7355
			"5706 A1 can only be used in a PCIX bus, aborting.\n");
7356 7357 7358 7359 7360
		goto err_out_unmap;
	}

	bnx2_init_nvram(bp);

7361
	reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7362 7363

	if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7364 7365 7366
	    BNX2_SHM_HDR_SIGNATURE_SIG) {
		u32 off = PCI_FUNC(pdev->devfn) << 2;

7367
		bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7368
	} else
7369 7370
		bp->shmem_base = HOST_VIEW_SHMEM_BASE;

7371 7372 7373
	/* Get the permanent MAC address.  First we need to make sure the
	 * firmware is actually running.
	 */
7374
	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7375 7376 7377

	if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
	    BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7378
		dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7379 7380 7381 7382
		rc = -ENODEV;
		goto err_out_unmap;
	}

7383
	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7384 7385 7386 7387 7388 7389 7390 7391 7392 7393 7394 7395 7396
	for (i = 0, j = 0; i < 3; i++) {
		u8 num, k, skip0;

		num = (u8) (reg >> (24 - (i * 8)));
		for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
			if (num >= k || !skip0 || k == 1) {
				bp->fw_version[j++] = (num / k) + '0';
				skip0 = 0;
			}
		}
		if (i != 2)
			bp->fw_version[j++] = '.';
	}
7397
	reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
M
Michael Chan 已提交
7398 7399 7400 7401
	if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
		bp->wol = 1;

	if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7402
		bp->flags |= BNX2_FLAG_ASF_ENABLE;
7403 7404

		for (i = 0; i < 30; i++) {
7405
			reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7406 7407 7408 7409 7410
			if (reg & BNX2_CONDITION_MFW_RUN_MASK)
				break;
			msleep(10);
		}
	}
7411
	reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7412 7413 7414 7415
	reg &= BNX2_CONDITION_MFW_RUN_MASK;
	if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
	    reg != BNX2_CONDITION_MFW_RUN_NONE) {
		int i;
7416
		u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7417 7418 7419

		bp->fw_version[j++] = ' ';
		for (i = 0; i < 3; i++) {
7420
			reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7421 7422 7423 7424 7425
			reg = swab32(reg);
			memcpy(&bp->fw_version[j], &reg, 4);
			j += 4;
		}
	}
7426

7427
	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7428 7429 7430
	bp->mac_addr[0] = (u8) (reg >> 8);
	bp->mac_addr[1] = (u8) reg;

7431
	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7432 7433 7434 7435 7436 7437
	bp->mac_addr[2] = (u8) (reg >> 24);
	bp->mac_addr[3] = (u8) (reg >> 16);
	bp->mac_addr[4] = (u8) (reg >> 8);
	bp->mac_addr[5] = (u8) reg;

	bp->tx_ring_size = MAX_TX_DESC_CNT;
7438
	bnx2_set_rx_ring_size(bp, 255);
7439 7440 7441 7442 7443 7444 7445

	bp->rx_csum = 1;

	bp->tx_quick_cons_trip_int = 20;
	bp->tx_quick_cons_trip = 20;
	bp->tx_ticks_int = 80;
	bp->tx_ticks = 80;
7446

7447 7448 7449 7450 7451
	bp->rx_quick_cons_trip_int = 6;
	bp->rx_quick_cons_trip = 6;
	bp->rx_ticks_int = 18;
	bp->rx_ticks = 18;

7452
	bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7453 7454

	bp->timer_interval =  HZ;
M
Michael Chan 已提交
7455
	bp->current_interval =  HZ;
7456

M
Michael Chan 已提交
7457 7458
	bp->phy_addr = 1;

7459
	/* Disable WOL support if we are running on a SERDES chip. */
7460 7461 7462
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_get_5709_media(bp);
	else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7463
		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
M
Michael Chan 已提交
7464

7465
	bp->phy_port = PORT_TP;
7466
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7467
		bp->phy_port = PORT_FIBRE;
7468
		reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
M
Michael Chan 已提交
7469
		if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7470
			bp->flags |= BNX2_FLAG_NO_WOL;
M
Michael Chan 已提交
7471 7472
			bp->wol = 0;
		}
7473 7474 7475 7476 7477 7478 7479 7480 7481
		if (CHIP_NUM(bp) == CHIP_NUM_5706) {
			/* Don't do parallel detect on this board because of
			 * some board problems.  The link will not go down
			 * if we do parallel detect.
			 */
			if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
			    pdev->subsystem_device == 0x310c)
				bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
		} else {
M
Michael Chan 已提交
7482 7483
			bp->phy_addr = 2;
			if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7484
				bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
M
Michael Chan 已提交
7485
		}
7486 7487
		bnx2_init_remote_phy(bp);

7488 7489
	} else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
		   CHIP_NUM(bp) == CHIP_NUM_5708)
7490
		bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7491 7492 7493
	else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
		 (CHIP_REV(bp) == CHIP_REV_Ax ||
		  CHIP_REV(bp) == CHIP_REV_Bx))
7494
		bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7495

7496 7497
	if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
	    (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
M
Michael Chan 已提交
7498
	    (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
7499
		bp->flags |= BNX2_FLAG_NO_WOL;
M
Michael Chan 已提交
7500 7501
		bp->wol = 0;
	}
M
Michael Chan 已提交
7502

7503 7504 7505 7506 7507 7508 7509 7510 7511 7512 7513 7514
	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
		bp->tx_quick_cons_trip_int =
			bp->tx_quick_cons_trip;
		bp->tx_ticks_int = bp->tx_ticks;
		bp->rx_quick_cons_trip_int =
			bp->rx_quick_cons_trip;
		bp->rx_ticks_int = bp->rx_ticks;
		bp->comp_prod_trip_int = bp->comp_prod_trip;
		bp->com_ticks_int = bp->com_ticks;
		bp->cmd_ticks_int = bp->cmd_ticks;
	}

7515 7516 7517 7518 7519 7520 7521 7522
	/* Disable MSI on 5706 if AMD 8132 bridge is found.
	 *
	 * MSI is defined to be 32-bit write.  The 5706 does 64-bit MSI writes
	 * with byte enables disabled on the unused 32-bit word.  This is legal
	 * but causes problems on the AMD 8132 which will eventually stop
	 * responding after a while.
	 *
	 * AMD believes this incompatibility is unique to the 5706, and
7523
	 * prefers to locally disable MSI rather than globally disabling it.
7524 7525 7526 7527 7528 7529 7530 7531
	 */
	if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
		struct pci_dev *amd_8132 = NULL;

		while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
						  PCI_DEVICE_ID_AMD_8132_BRIDGE,
						  amd_8132))) {

7532 7533
			if (amd_8132->revision >= 0x10 &&
			    amd_8132->revision <= 0x13) {
7534 7535 7536 7537 7538 7539 7540
				disable_msi = 1;
				pci_dev_put(amd_8132);
				break;
			}
		}
	}

7541
	bnx2_set_default_link(bp);
7542 7543
	bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;

M
Michael Chan 已提交
7544 7545 7546 7547 7548
	init_timer(&bp->timer);
	bp->timer.expires = RUN_AT(bp->timer_interval);
	bp->timer.data = (unsigned long) bp;
	bp->timer.function = bnx2_timer;

7549 7550 7551 7552 7553
	return 0;

err_out_unmap:
	if (bp->regview) {
		iounmap(bp->regview);
7554
		bp->regview = NULL;
7555 7556 7557 7558 7559 7560 7561 7562 7563 7564 7565 7566 7567
	}

err_out_release:
	pci_release_regions(pdev);

err_out_disable:
	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);

err_out:
	return rc;
}

7568 7569 7570 7571 7572
static char * __devinit
bnx2_bus_string(struct bnx2 *bp, char *str)
{
	char *s = str;

7573
	if (bp->flags & BNX2_FLAG_PCIE) {
7574 7575 7576
		s += sprintf(s, "PCI Express");
	} else {
		s += sprintf(s, "PCI");
7577
		if (bp->flags & BNX2_FLAG_PCIX)
7578
			s += sprintf(s, "-X");
7579
		if (bp->flags & BNX2_FLAG_PCI_32BIT)
7580 7581 7582 7583 7584 7585 7586 7587
			s += sprintf(s, " 32-bit");
		else
			s += sprintf(s, " 64-bit");
		s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
	}
	return str;
}

M
Michael Chan 已提交
7588
static void __devinit
7589 7590
bnx2_init_napi(struct bnx2 *bp)
{
7591
	int i;
7592

7593
	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7594 7595 7596 7597 7598 7599
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		int (*poll)(struct napi_struct *, int);

		if (i == 0)
			poll = bnx2_poll;
		else
7600
			poll = bnx2_poll_msix;
7601 7602

		netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
7603 7604
		bnapi->bp = bp;
	}
7605 7606
}

7607 7608 7609 7610 7611 7612
static int __devinit
bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int version_printed = 0;
	struct net_device *dev = NULL;
	struct bnx2 *bp;
7613
	int rc;
7614
	char str[40];
7615
	DECLARE_MAC_BUF(mac);
7616 7617 7618 7619 7620 7621 7622 7623 7624 7625 7626 7627 7628 7629 7630 7631 7632 7633 7634 7635 7636 7637 7638 7639 7640 7641 7642 7643 7644 7645 7646

	if (version_printed++ == 0)
		printk(KERN_INFO "%s", version);

	/* dev zeroed in init_etherdev */
	dev = alloc_etherdev(sizeof(*bp));

	if (!dev)
		return -ENOMEM;

	rc = bnx2_init_board(pdev, dev);
	if (rc < 0) {
		free_netdev(dev);
		return rc;
	}

	dev->open = bnx2_open;
	dev->hard_start_xmit = bnx2_start_xmit;
	dev->stop = bnx2_close;
	dev->get_stats = bnx2_get_stats;
	dev->set_multicast_list = bnx2_set_rx_mode;
	dev->do_ioctl = bnx2_ioctl;
	dev->set_mac_address = bnx2_change_mac_addr;
	dev->change_mtu = bnx2_change_mtu;
	dev->tx_timeout = bnx2_tx_timeout;
	dev->watchdog_timeo = TX_TIMEOUT;
#ifdef BCM_VLAN
	dev->vlan_rx_register = bnx2_vlan_rx_register;
#endif
	dev->ethtool_ops = &bnx2_ethtool_ops;

M
Michael Chan 已提交
7647
	bp = netdev_priv(dev);
7648
	bnx2_init_napi(bp);
7649 7650 7651 7652 7653

#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
	dev->poll_controller = poll_bnx2;
#endif

7654 7655 7656 7657 7658 7659
	pci_set_drvdata(pdev, dev);

	memcpy(dev->dev_addr, bp->mac_addr, 6);
	memcpy(dev->perm_addr, bp->mac_addr, 6);
	bp->name = board_info[ent->driver_data].name;

7660
	dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7661
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
7662 7663
		dev->features |= NETIF_F_IPV6_CSUM;

7664 7665 7666 7667
#ifdef BCM_VLAN
	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
#endif
	dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7668 7669
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		dev->features |= NETIF_F_TSO6;
7670

7671
	if ((rc = register_netdev(dev))) {
7672
		dev_err(&pdev->dev, "Cannot register net device\n");
7673 7674 7675 7676 7677 7678 7679 7680 7681
		if (bp->regview)
			iounmap(bp->regview);
		pci_release_regions(pdev);
		pci_disable_device(pdev);
		pci_set_drvdata(pdev, NULL);
		free_netdev(dev);
		return rc;
	}

7682
	printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7683
		"IRQ %d, node addr %s\n",
7684 7685 7686 7687
		dev->name,
		bp->name,
		((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
		((CHIP_ID(bp) & 0x0ff0) >> 4),
7688
		bnx2_bus_string(bp, str),
7689
		dev->base_addr,
7690
		bp->pdev->irq, print_mac(mac, dev->dev_addr));
7691 7692 7693 7694 7695 7696 7697 7698

	return 0;
}

static void __devexit
bnx2_remove_one(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
M
Michael Chan 已提交
7699
	struct bnx2 *bp = netdev_priv(dev);
7700

7701 7702
	flush_scheduled_work();

7703 7704 7705 7706 7707 7708 7709 7710 7711 7712 7713 7714
	unregister_netdev(dev);

	if (bp->regview)
		iounmap(bp->regview);

	free_netdev(dev);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);
}

static int
7715
bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7716 7717
{
	struct net_device *dev = pci_get_drvdata(pdev);
M
Michael Chan 已提交
7718
	struct bnx2 *bp = netdev_priv(dev);
7719 7720
	u32 reset_code;

7721 7722 7723 7724 7725
	/* PCI register 4 needs to be saved whether netif_running() or not.
	 * MSI address and data need to be saved if using MSI and
	 * netif_running().
	 */
	pci_save_state(pdev);
7726 7727 7728
	if (!netif_running(dev))
		return 0;

M
Michael Chan 已提交
7729
	flush_scheduled_work();
7730 7731 7732
	bnx2_netif_stop(bp);
	netif_device_detach(dev);
	del_timer_sync(&bp->timer);
7733
	if (bp->flags & BNX2_FLAG_NO_WOL)
7734
		reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
M
Michael Chan 已提交
7735
	else if (bp->wol)
7736 7737 7738 7739 7740
		reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
	else
		reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
	bnx2_reset_chip(bp, reset_code);
	bnx2_free_skbs(bp);
7741
	bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7742 7743 7744 7745 7746 7747 7748
	return 0;
}

static int
bnx2_resume(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
M
Michael Chan 已提交
7749
	struct bnx2 *bp = netdev_priv(dev);
7750

7751
	pci_restore_state(pdev);
7752 7753 7754
	if (!netif_running(dev))
		return 0;

7755
	bnx2_set_power_state(bp, PCI_D0);
7756
	netif_device_attach(dev);
7757
	bnx2_init_nic(bp, 1);
7758 7759 7760 7761
	bnx2_netif_start(bp);
	return 0;
}

W
Wendy Xiong 已提交
7762 7763 7764 7765 7766 7767 7768 7769 7770 7771 7772 7773 7774 7775 7776 7777 7778 7779 7780 7781 7782 7783 7784 7785 7786 7787 7788 7789 7790 7791 7792 7793 7794 7795 7796 7797 7798 7799 7800 7801 7802 7803 7804 7805 7806 7807 7808 7809 7810 7811 7812 7813 7814 7815 7816 7817 7818 7819 7820 7821 7822 7823 7824 7825 7826 7827 7828 7829 7830 7831 7832 7833 7834 7835 7836 7837 7838 7839 7840 7841 7842 7843 7844 7845 7846 7847
/**
 * bnx2_io_error_detected - called when PCI error is detected
 * @pdev: Pointer to PCI device
 * @state: The current pci connection state
 *
 * This function is called after a PCI bus error affecting
 * this device has been detected.
 */
static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
					       pci_channel_state_t state)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct bnx2 *bp = netdev_priv(dev);

	rtnl_lock();
	netif_device_detach(dev);

	if (netif_running(dev)) {
		bnx2_netif_stop(bp);
		del_timer_sync(&bp->timer);
		bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
	}

	pci_disable_device(pdev);
	rtnl_unlock();

	/* Request a slot slot reset. */
	return PCI_ERS_RESULT_NEED_RESET;
}

/**
 * bnx2_io_slot_reset - called after the pci bus has been reset.
 * @pdev: Pointer to PCI device
 *
 * Restart the card from scratch, as if from a cold-boot.
 */
static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct bnx2 *bp = netdev_priv(dev);

	rtnl_lock();
	if (pci_enable_device(pdev)) {
		dev_err(&pdev->dev,
			"Cannot re-enable PCI device after reset.\n");
		rtnl_unlock();
		return PCI_ERS_RESULT_DISCONNECT;
	}
	pci_set_master(pdev);
	pci_restore_state(pdev);

	if (netif_running(dev)) {
		bnx2_set_power_state(bp, PCI_D0);
		bnx2_init_nic(bp, 1);
	}

	rtnl_unlock();
	return PCI_ERS_RESULT_RECOVERED;
}

/**
 * bnx2_io_resume - called when traffic can start flowing again.
 * @pdev: Pointer to PCI device
 *
 * This callback is called when the error recovery driver tells us that
 * its OK to resume normal operation.
 */
static void bnx2_io_resume(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct bnx2 *bp = netdev_priv(dev);

	rtnl_lock();
	if (netif_running(dev))
		bnx2_netif_start(bp);

	netif_device_attach(dev);
	rtnl_unlock();
}

static struct pci_error_handlers bnx2_err_handler = {
	.error_detected	= bnx2_io_error_detected,
	.slot_reset	= bnx2_io_slot_reset,
	.resume		= bnx2_io_resume,
};

7848
static struct pci_driver bnx2_pci_driver = {
7849 7850 7851 7852 7853 7854
	.name		= DRV_MODULE_NAME,
	.id_table	= bnx2_pci_tbl,
	.probe		= bnx2_init_one,
	.remove		= __devexit_p(bnx2_remove_one),
	.suspend	= bnx2_suspend,
	.resume		= bnx2_resume,
W
Wendy Xiong 已提交
7855
	.err_handler	= &bnx2_err_handler,
7856 7857 7858 7859
};

static int __init bnx2_init(void)
{
7860
	return pci_register_driver(&bnx2_pci_driver);
7861 7862 7863 7864 7865 7866 7867 7868 7869 7870 7871 7872
}

static void __exit bnx2_cleanup(void)
{
	pci_unregister_driver(&bnx2_pci_driver);
}

module_init(bnx2_init);
module_exit(bnx2_cleanup);