mlx5_ifc.h 218.3 KB
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/*
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 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
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 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
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*/
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#ifndef MLX5_IFC_H
#define MLX5_IFC_H

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#include "mlx5_ifc_fpga.h"

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enum {
	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
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	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
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	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
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};

enum {
	MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
	MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
};

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enum {
	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
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	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
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	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
};

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enum {
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	MLX5_SHARED_RESOURCE_UID = 0xffff,
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};

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enum {
	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
	MLX5_CMD_OP_INIT_HCA                      = 0x102,
	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
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	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
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	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
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	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
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	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
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	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
	MLX5_CMD_OP_GEN_EQE                       = 0x304,
	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
	MLX5_CMD_OP_CREATE_QP                     = 0x500,
	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
	MLX5_CMD_OP_2ERR_QP                       = 0x507,
	MLX5_CMD_OP_2RST_QP                       = 0x50a,
	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
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	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
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	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
	MLX5_CMD_OP_ARM_RQ                        = 0x703,
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	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
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	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
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	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
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	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
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	MLX5_CMD_OP_QUERY_HOST_PARAMS             = 0x740,
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	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
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	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
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	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
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	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
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	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
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	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
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	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
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	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
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	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
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	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
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	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
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	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
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	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
	MLX5_CMD_OP_NOP                           = 0x80d,
	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
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	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
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	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
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	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
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	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
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	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
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	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
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	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
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	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
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	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
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	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
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	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
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	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
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	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
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	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
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	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
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	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
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	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
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	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
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	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
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	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
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	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
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	MLX5_CMD_OP_MAX
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};

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/* Valid range for general commands that don't work over an object */
enum {
	MLX5_CMD_OP_GENERAL_START = 0xb00,
	MLX5_CMD_OP_GENERAL_END = 0xd00,
};

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struct mlx5_ifc_flow_table_fields_supported_bits {
	u8         outer_dmac[0x1];
	u8         outer_smac[0x1];
	u8         outer_ether_type[0x1];
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	u8         outer_ip_version[0x1];
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	u8         outer_first_prio[0x1];
	u8         outer_first_cfi[0x1];
	u8         outer_first_vid[0x1];
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	u8         outer_ipv4_ttl[0x1];
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	u8         outer_second_prio[0x1];
	u8         outer_second_cfi[0x1];
	u8         outer_second_vid[0x1];
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	u8         reserved_at_b[0x1];
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	u8         outer_sip[0x1];
	u8         outer_dip[0x1];
	u8         outer_frag[0x1];
	u8         outer_ip_protocol[0x1];
	u8         outer_ip_ecn[0x1];
	u8         outer_ip_dscp[0x1];
	u8         outer_udp_sport[0x1];
	u8         outer_udp_dport[0x1];
	u8         outer_tcp_sport[0x1];
	u8         outer_tcp_dport[0x1];
	u8         outer_tcp_flags[0x1];
	u8         outer_gre_protocol[0x1];
	u8         outer_gre_key[0x1];
	u8         outer_vxlan_vni[0x1];
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	u8         reserved_at_1a[0x5];
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	u8         source_eswitch_port[0x1];

	u8         inner_dmac[0x1];
	u8         inner_smac[0x1];
	u8         inner_ether_type[0x1];
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	u8         inner_ip_version[0x1];
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	u8         inner_first_prio[0x1];
	u8         inner_first_cfi[0x1];
	u8         inner_first_vid[0x1];
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	u8         reserved_at_27[0x1];
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	u8         inner_second_prio[0x1];
	u8         inner_second_cfi[0x1];
	u8         inner_second_vid[0x1];
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	u8         reserved_at_2b[0x1];
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	u8         inner_sip[0x1];
	u8         inner_dip[0x1];
	u8         inner_frag[0x1];
	u8         inner_ip_protocol[0x1];
	u8         inner_ip_ecn[0x1];
	u8         inner_ip_dscp[0x1];
	u8         inner_udp_sport[0x1];
	u8         inner_udp_dport[0x1];
	u8         inner_tcp_sport[0x1];
	u8         inner_tcp_dport[0x1];
	u8         inner_tcp_flags[0x1];
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	u8         reserved_at_37[0x9];
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	u8         reserved_at_40[0x5];
	u8         outer_first_mpls_over_udp[0x4];
	u8         outer_first_mpls_over_gre[0x4];
	u8         inner_first_mpls[0x4];
	u8         outer_first_mpls[0x4];
	u8         reserved_at_55[0x2];
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	u8	   outer_esp_spi[0x1];
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	u8         reserved_at_58[0x2];
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	u8         bth_dst_qp[0x1];
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	u8         reserved_at_5b[0x25];
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};

struct mlx5_ifc_flow_table_prop_layout_bits {
	u8         ft_support[0x1];
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	u8         reserved_at_1[0x1];
	u8         flow_counter[0x1];
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	u8	   flow_modify_en[0x1];
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	u8         modify_root[0x1];
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	u8         identified_miss_table_mode[0x1];
	u8         flow_table_modify[0x1];
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	u8         reformat[0x1];
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	u8         decap[0x1];
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	u8         reserved_at_9[0x1];
	u8         pop_vlan[0x1];
	u8         push_vlan[0x1];
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	u8         reserved_at_c[0x1];
	u8         pop_vlan_2[0x1];
	u8         push_vlan_2[0x1];
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	u8	   reformat_and_vlan_action[0x1];
	u8	   reserved_at_10[0x2];
	u8	   reformat_l3_tunnel_to_l2[0x1];
	u8	   reformat_l2_to_l3_tunnel[0x1];
	u8	   reformat_and_modify_action[0x1];
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	u8         reserved_at_15[0xb];
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	u8         reserved_at_20[0x2];
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	u8         log_max_ft_size[0x6];
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	u8         log_max_modify_header_context[0x8];
	u8         max_modify_header_actions[0x8];
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	u8         max_ft_level[0x8];

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	u8         reserved_at_40[0x20];
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	u8         reserved_at_60[0x18];
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	u8         log_max_ft_num[0x8];

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	u8         reserved_at_80[0x18];
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	u8         log_max_destination[0x8];

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	u8         log_max_flow_counter[0x8];
	u8         reserved_at_a8[0x10];
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	u8         log_max_flow[0x8];

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	u8         reserved_at_c0[0x40];
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	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;

	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
};

struct mlx5_ifc_odp_per_transport_service_cap_bits {
	u8         send[0x1];
	u8         receive[0x1];
	u8         write[0x1];
	u8         read[0x1];
395
	u8         atomic[0x1];
396
	u8         srq_receive[0x1];
397
	u8         reserved_at_6[0x1a];
398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415
};

struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
	u8         smac_47_16[0x20];

	u8         smac_15_0[0x10];
	u8         ethertype[0x10];

	u8         dmac_47_16[0x20];

	u8         dmac_15_0[0x10];
	u8         first_prio[0x3];
	u8         first_cfi[0x1];
	u8         first_vid[0xc];

	u8         ip_protocol[0x8];
	u8         ip_dscp[0x6];
	u8         ip_ecn[0x2];
416 417
	u8         cvlan_tag[0x1];
	u8         svlan_tag[0x1];
418
	u8         frag[0x1];
419
	u8         ip_version[0x4];
420 421 422 423 424
	u8         tcp_flags[0x9];

	u8         tcp_sport[0x10];
	u8         tcp_dport[0x10];

425 426
	u8         reserved_at_c0[0x18];
	u8         ttl_hoplimit[0x8];
427 428 429 430

	u8         udp_sport[0x10];
	u8         udp_dport[0x10];

431
	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
432

433
	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
434 435
};

436 437 438 439 440 441 442 443 444 445
struct mlx5_ifc_nvgre_key_bits {
	u8 hi[0x18];
	u8 lo[0x8];
};

union mlx5_ifc_gre_key_bits {
	struct mlx5_ifc_nvgre_key_bits nvgre;
	u8 key[0x20];
};

446
struct mlx5_ifc_fte_match_set_misc_bits {
447 448
	u8         reserved_at_0[0x8];
	u8         source_sqn[0x18];
449

450
	u8         source_eswitch_owner_vhca_id[0x10];
451 452 453 454 455 456 457 458 459
	u8         source_port[0x10];

	u8         outer_second_prio[0x3];
	u8         outer_second_cfi[0x1];
	u8         outer_second_vid[0xc];
	u8         inner_second_prio[0x3];
	u8         inner_second_cfi[0x1];
	u8         inner_second_vid[0xc];

460 461 462 463 464
	u8         outer_second_cvlan_tag[0x1];
	u8         inner_second_cvlan_tag[0x1];
	u8         outer_second_svlan_tag[0x1];
	u8         inner_second_svlan_tag[0x1];
	u8         reserved_at_64[0xc];
465 466
	u8         gre_protocol[0x10];

467
	union mlx5_ifc_gre_key_bits gre_key;
468 469

	u8         vxlan_vni[0x18];
470
	u8         reserved_at_b8[0x8];
471

472
	u8         reserved_at_c0[0x20];
473

474
	u8         reserved_at_e0[0xc];
475 476
	u8         outer_ipv6_flow_label[0x14];

477
	u8         reserved_at_100[0xc];
478 479
	u8         inner_ipv6_flow_label[0x14];

480 481
	u8         reserved_at_120[0x28];
	u8         bth_dst_qp[0x18];
482 483 484
	u8	   reserved_at_160[0x20];
	u8	   outer_esp_spi[0x20];
	u8         reserved_at_1a0[0x60];
485 486
};

487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509
struct mlx5_ifc_fte_match_mpls_bits {
	u8         mpls_label[0x14];
	u8         mpls_exp[0x3];
	u8         mpls_s_bos[0x1];
	u8         mpls_ttl[0x8];
};

struct mlx5_ifc_fte_match_set_misc2_bits {
	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;

	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;

	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;

	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;

	u8         reserved_at_80[0x100];

	u8         metadata_reg_a[0x20];

	u8         reserved_at_1a0[0x60];
};

510 511 512 513
struct mlx5_ifc_cmd_pas_bits {
	u8         pa_h[0x20];

	u8         pa_l[0x14];
514
	u8         reserved_at_34[0xc];
515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538
};

struct mlx5_ifc_uint64_bits {
	u8         hi[0x20];

	u8         lo[0x20];
};

enum {
	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
};

struct mlx5_ifc_ads_bits {
	u8         fl[0x1];
	u8         free_ar[0x1];
539
	u8         reserved_at_2[0xe];
540 541
	u8         pkey_index[0x10];

542
	u8         reserved_at_20[0x8];
543 544 545 546 547
	u8         grh[0x1];
	u8         mlid[0x7];
	u8         rlid[0x10];

	u8         ack_timeout[0x5];
548
	u8         reserved_at_45[0x3];
549
	u8         src_addr_index[0x8];
550
	u8         reserved_at_50[0x4];
551 552 553
	u8         stat_rate[0x4];
	u8         hop_limit[0x8];

554
	u8         reserved_at_60[0x4];
555 556 557 558 559
	u8         tclass[0x8];
	u8         flow_label[0x14];

	u8         rgid_rip[16][0x8];

560
	u8         reserved_at_100[0x4];
561 562
	u8         f_dscp[0x1];
	u8         f_ecn[0x1];
563
	u8         reserved_at_106[0x1];
564 565 566 567 568 569 570 571
	u8         f_eth_prio[0x1];
	u8         ecn[0x2];
	u8         dscp[0x6];
	u8         udp_sport[0x10];

	u8         dei_cfi[0x1];
	u8         eth_prio[0x3];
	u8         sl[0x4];
572
	u8         vhca_port_num[0x8];
573 574 575 576 577 578
	u8         rmac_47_32[0x10];

	u8         rmac_31_0[0x20];
};

struct mlx5_ifc_flow_table_nic_cap_bits {
579
	u8         nic_rx_multi_path_tirs[0x1];
580 581
	u8         nic_rx_multi_path_tirs_fts[0x1];
	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
582 583 584 585 586 587 588
	u8	   reserved_at_3[0x1d];
	u8	   encap_general_header[0x1];
	u8	   reserved_at_21[0xa];
	u8	   log_max_packet_reformat_context[0x5];
	u8	   reserved_at_30[0x6];
	u8	   max_encap_header_size[0xa];
	u8	   reserved_at_40[0x1c0];
589 590 591

	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;

592
	u8         reserved_at_400[0x200];
593 594 595 596 597

	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;

	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;

598
	u8         reserved_at_a00[0x200];
599 600 601

	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;

602
	u8         reserved_at_e00[0x7200];
603 604
};

605
struct mlx5_ifc_flow_table_eswitch_cap_bits {
606
	u8      reserved_at_0[0x1a];
607
	u8      multi_fdb_encap[0x1];
608 609 610 611 612
	u8      reserved_at_1b[0x1];
	u8      fdb_multi_path_to_table[0x1];
	u8      reserved_at_1d[0x3];

	u8      reserved_at_20[0x1e0];
613 614 615 616 617 618 619

	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;

	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;

	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;

620
	u8      reserved_at_800[0x7800];
621 622
};

623 624 625 626 627
enum {
	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
};

628 629 630 631 632 633
struct mlx5_ifc_e_switch_cap_bits {
	u8         vport_svlan_strip[0x1];
	u8         vport_cvlan_strip[0x1];
	u8         vport_svlan_insert[0x1];
	u8         vport_cvlan_insert_if_not_exist[0x1];
	u8         vport_cvlan_insert_overwrite[0x1];
634 635
	u8         reserved_at_5[0x17];
	u8         counter_eswitch_affinity[0x1];
636
	u8         merged_eswitch[0x1];
637 638
	u8         nic_vport_node_guid_modify[0x1];
	u8         nic_vport_port_guid_modify[0x1];
639

640 641
	u8         vxlan_encap_decap[0x1];
	u8         nvgre_encap_decap[0x1];
642 643 644
	u8         reserved_at_22[0x1];
	u8         log_max_fdb_encap_uplink[0x5];
	u8         reserved_at_21[0x3];
645
	u8         log_max_packet_reformat_context[0x5];
646 647 648 649 650
	u8         reserved_2b[0x6];
	u8         max_encap_header_size[0xa];

	u8         reserved_40[0x7c0];

651 652
};

653 654
struct mlx5_ifc_qos_cap_bits {
	u8         packet_pacing[0x1];
655
	u8         esw_scheduling[0x1];
656 657
	u8         esw_bw_share[0x1];
	u8         esw_rate_limit[0x1];
658 659 660 661
	u8         reserved_at_4[0x1];
	u8         packet_pacing_burst_bound[0x1];
	u8         packet_pacing_typical_size[0x1];
	u8         reserved_at_7[0x19];
662 663 664

	u8         reserved_at_20[0x20];

665
	u8         packet_pacing_max_rate[0x20];
666

667
	u8         packet_pacing_min_rate[0x20];
668 669

	u8         reserved_at_80[0x10];
670
	u8         packet_pacing_rate_table_size[0x10];
671 672 673 674 675 676 677 678 679 680

	u8         esw_element_type[0x10];
	u8         esw_tsar_type[0x10];

	u8         reserved_at_c0[0x10];
	u8         max_qos_para_vport[0x10];

	u8         max_tsar_bw_share[0x20];

	u8         reserved_at_100[0x700];
681 682
};

683 684 685 686 687 688 689 690 691 692
struct mlx5_ifc_debug_cap_bits {
	u8         reserved_at_0[0x20];

	u8         reserved_at_20[0x2];
	u8         stall_detect[0x1];
	u8         reserved_at_23[0x1d];

	u8         reserved_at_40[0x7c0];
};

693 694 695 696 697 698
struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
	u8         csum_cap[0x1];
	u8         vlan_cap[0x1];
	u8         lro_cap[0x1];
	u8         lro_psh_flag[0x1];
	u8         lro_time_stamp[0x1];
699 700
	u8         reserved_at_5[0x2];
	u8         wqe_vlan_insert[0x1];
701
	u8         self_lb_en_modifiable[0x1];
702
	u8         reserved_at_9[0x2];
703
	u8         max_lso_cap[0x5];
704
	u8         multi_pkt_send_wqe[0x2];
705
	u8	   wqe_inline_mode[0x2];
706
	u8         rss_ind_tbl_cap[0x4];
707 708
	u8         reg_umr_sq[0x1];
	u8         scatter_fcs[0x1];
709
	u8         enhanced_multi_pkt_send_wqe[0x1];
710
	u8         tunnel_lso_const_out_ip_id[0x1];
711
	u8         reserved_at_1c[0x2];
712
	u8         tunnel_stateless_gre[0x1];
713 714
	u8         tunnel_stateless_vxlan[0x1];

715 716 717
	u8         swp[0x1];
	u8         swp_csum[0x1];
	u8         swp_lso[0x1];
718 719 720
	u8         reserved_at_23[0xd];
	u8         max_vxlan_udp_ports[0x8];
	u8         reserved_at_38[0x6];
721 722
	u8         max_geneve_opt_len[0x1];
	u8         tunnel_stateless_geneve_rx[0x1];
723

724
	u8         reserved_at_40[0x10];
725 726
	u8         lro_min_mss_size[0x10];

727
	u8         reserved_at_60[0x120];
728 729 730

	u8         lro_timer_supported_periods[4][0x20];

731
	u8         reserved_at_200[0x600];
732 733 734 735
};

struct mlx5_ifc_roce_cap_bits {
	u8         roce_apm[0x1];
736
	u8         reserved_at_1[0x1f];
737

738
	u8         reserved_at_20[0x60];
739

740
	u8         reserved_at_80[0xc];
741
	u8         l3_type[0x4];
742
	u8         reserved_at_90[0x8];
743 744
	u8         roce_version[0x8];

745
	u8         reserved_at_a0[0x10];
746 747 748 749 750
	u8         r_roce_dest_udp_port[0x10];

	u8         r_roce_max_src_udp_port[0x10];
	u8         r_roce_min_src_udp_port[0x10];

751
	u8         reserved_at_e0[0x10];
752 753
	u8         roce_address_table_size[0x10];

754
	u8         reserved_at_100[0x700];
755 756
};

757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774
struct mlx5_ifc_device_mem_cap_bits {
	u8         memic[0x1];
	u8         reserved_at_1[0x1f];

	u8         reserved_at_20[0xb];
	u8         log_min_memic_alloc_size[0x5];
	u8         reserved_at_30[0x8];
	u8	   log_max_memic_addr_alignment[0x8];

	u8         memic_bar_start_addr[0x40];

	u8         memic_bar_size[0x20];

	u8         max_memic_size[0x20];

	u8         reserved_at_c0[0x740];
};

775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799
enum {
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
};

enum {
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
};

struct mlx5_ifc_atomic_caps_bits {
800
	u8         reserved_at_0[0x40];
801

802
	u8         atomic_req_8B_endianness_mode[0x2];
803
	u8         reserved_at_42[0x4];
804
	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
805

806
	u8         reserved_at_47[0x19];
807

808
	u8         reserved_at_60[0x20];
809

810
	u8         reserved_at_80[0x10];
811
	u8         atomic_operations[0x10];
812

813
	u8         reserved_at_a0[0x10];
814 815
	u8         atomic_size_qp[0x10];

816
	u8         reserved_at_c0[0x10];
817 818
	u8         atomic_size_dc[0x10];

819
	u8         reserved_at_e0[0x720];
820 821 822
};

struct mlx5_ifc_odp_cap_bits {
823
	u8         reserved_at_0[0x40];
824 825

	u8         sig[0x1];
826
	u8         reserved_at_41[0x1f];
827

828
	u8         reserved_at_60[0x20];
829 830 831 832 833 834 835

	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;

	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;

	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;

836 837 838
	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;

	u8         reserved_at_100[0x700];
839 840
};

841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864
struct mlx5_ifc_calc_op {
	u8        reserved_at_0[0x10];
	u8        reserved_at_10[0x9];
	u8        op_swap_endianness[0x1];
	u8        op_min[0x1];
	u8        op_xor[0x1];
	u8        op_or[0x1];
	u8        op_and[0x1];
	u8        op_max[0x1];
	u8        op_add[0x1];
};

struct mlx5_ifc_vector_calc_cap_bits {
	u8         calc_matrix[0x1];
	u8         reserved_at_1[0x1f];
	u8         reserved_at_20[0x8];
	u8         max_vec_count[0x8];
	u8         reserved_at_30[0xd];
	u8         max_chunk_size[0x3];
	struct mlx5_ifc_calc_op calc0;
	struct mlx5_ifc_calc_op calc1;
	struct mlx5_ifc_calc_op calc2;
	struct mlx5_ifc_calc_op calc3;

865
	u8         reserved_at_c0[0x720];
866 867
};

868 869 870
enum {
	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
	MLX5_WQ_TYPE_CYCLIC       = 0x1,
871
	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
872
	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910
};

enum {
	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
};

enum {
	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
};

enum {
	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
};

enum {
	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
};

enum {
	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
};

enum {
	MLX5_CAP_PORT_TYPE_IB  = 0x0,
	MLX5_CAP_PORT_TYPE_ETH = 0x1,
911 912
};

913 914 915 916 917 918
enum {
	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
};

919 920 921 922
enum {
	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
};

923
struct mlx5_ifc_cmd_hca_cap_bits {
924 925 926 927
	u8         reserved_at_0[0x30];
	u8         vhca_id[0x10];

	u8         reserved_at_40[0x40];
928 929 930

	u8         log_max_srq_sz[0x8];
	u8         log_max_qp_sz[0x8];
931
	u8         reserved_at_90[0xb];
932 933
	u8         log_max_qp[0x5];

934
	u8         reserved_at_a0[0xb];
935
	u8         log_max_srq[0x5];
936
	u8         reserved_at_b0[0x10];
937

938
	u8         reserved_at_c0[0x8];
939
	u8         log_max_cq_sz[0x8];
940
	u8         reserved_at_d0[0xb];
941 942 943
	u8         log_max_cq[0x5];

	u8         log_max_eq_sz[0x8];
944
	u8         reserved_at_e8[0x2];
945
	u8         log_max_mkey[0x6];
946 947
	u8         reserved_at_f0[0x8];
	u8         dump_fill_mkey[0x1];
948 949
	u8         reserved_at_f9[0x2];
	u8         fast_teardown[0x1];
950 951 952
	u8         log_max_eq[0x4];

	u8         max_indirection[0x8];
953
	u8         fixed_buffer_size[0x1];
954
	u8         log_max_mrw_sz[0x7];
955 956
	u8         force_teardown[0x1];
	u8         reserved_at_111[0x1];
957
	u8         log_max_bsf_list_size[0x6];
958 959
	u8         umr_extended_translation_offset[0x1];
	u8         null_mkey[0x1];
960 961
	u8         log_max_klm_list_size[0x6];

962
	u8         reserved_at_120[0xa];
963
	u8         log_max_ra_req_dc[0x6];
964
	u8         reserved_at_130[0xa];
965 966
	u8         log_max_ra_res_dc[0x6];

967
	u8         reserved_at_140[0xa];
968
	u8         log_max_ra_req_qp[0x6];
969
	u8         reserved_at_150[0xa];
970 971
	u8         log_max_ra_res_qp[0x6];

972
	u8         end_pad[0x1];
973 974
	u8         cc_query_allowed[0x1];
	u8         cc_modify_allowed[0x1];
975 976
	u8         start_pad[0x1];
	u8         cache_line_128byte[0x1];
977 978
	u8         reserved_at_165[0xa];
	u8         qcam_reg[0x1];
979
	u8         gid_table_size[0x10];
980

981 982
	u8         out_of_seq_cnt[0x1];
	u8         vport_counters[0x1];
983
	u8         retransmission_q_counters[0x1];
984
	u8         debug[0x1];
985
	u8         modify_rq_counter_set_id[0x1];
986
	u8         rq_delay_drop[0x1];
987 988 989
	u8         max_qp_cnt[0xa];
	u8         pkey_table_size[0x10];

990 991 992 993
	u8         vport_group_manager[0x1];
	u8         vhca_group_manager[0x1];
	u8         ib_virt[0x1];
	u8         eth_virt[0x1];
994
	u8         vnic_env_queue_counters[0x1];
995 996
	u8         ets[0x1];
	u8         nic_flow_table[0x1];
997
	u8         eswitch_manager[0x1];
998
	u8         device_memory[0x1];
999 1000
	u8         mcam_reg[0x1];
	u8         pcam_reg[0x1];
1001
	u8         local_ca_ack_delay[0x5];
1002
	u8         port_module_event[0x1];
1003
	u8         enhanced_error_q_counters[0x1];
1004
	u8         ports_check[0x1];
1005
	u8         reserved_at_1b3[0x1];
1006 1007
	u8         disable_link_up[0x1];
	u8         beacon_led[0x1];
1008
	u8         port_type[0x2];
1009 1010
	u8         num_ports[0x8];

1011 1012 1013
	u8         reserved_at_1c0[0x1];
	u8         pps[0x1];
	u8         pps_modify[0x1];
1014
	u8         log_max_msg[0x5];
1015
	u8         reserved_at_1c8[0x4];
1016
	u8         max_tc[0x4];
1017
	u8         temp_warn_event[0x1];
1018
	u8         dcbx[0x1];
1019 1020
	u8         general_notification_event[0x1];
	u8         reserved_at_1d3[0x2];
1021
	u8         fpga[0x1];
1022 1023
	u8         rol_s[0x1];
	u8         rol_g[0x1];
1024
	u8         reserved_at_1d8[0x1];
1025 1026 1027 1028 1029 1030 1031
	u8         wol_s[0x1];
	u8         wol_g[0x1];
	u8         wol_a[0x1];
	u8         wol_b[0x1];
	u8         wol_m[0x1];
	u8         wol_u[0x1];
	u8         wol_p[0x1];
1032 1033

	u8         stat_rate_support[0x10];
1034
	u8         reserved_at_1f0[0xc];
1035
	u8         cqe_version[0x4];
1036

1037
	u8         compact_address_vector[0x1];
1038
	u8         striding_rq[0x1];
1039 1040
	u8         reserved_at_202[0x1];
	u8         ipoib_enhanced_offloads[0x1];
1041
	u8         ipoib_basic_offloads[0x1];
1042 1043 1044 1045 1046
	u8         reserved_at_205[0x1];
	u8         repeated_block_disabled[0x1];
	u8         umr_modify_entity_size_disabled[0x1];
	u8         umr_modify_atomic_disabled[0x1];
	u8         umr_indirect_mkey_disabled[0x1];
1047
	u8         umr_fence[0x2];
1048 1049
	u8         dc_req_scat_data_cqe[0x1];
	u8         reserved_at_20d[0x2];
1050
	u8         drain_sigerr[0x1];
1051 1052
	u8         cmdif_checksum[0x2];
	u8         sigerr_cqe[0x1];
1053
	u8         reserved_at_213[0x1];
1054 1055
	u8         wq_signature[0x1];
	u8         sctr_data_cqe[0x1];
1056
	u8         reserved_at_216[0x1];
1057 1058 1059
	u8         sho[0x1];
	u8         tph[0x1];
	u8         rf[0x1];
1060
	u8         dct[0x1];
1061
	u8         qos[0x1];
1062
	u8         eth_net_offloads[0x1];
1063 1064
	u8         roce[0x1];
	u8         atomic[0x1];
1065
	u8         reserved_at_21f[0x1];
1066 1067 1068 1069

	u8         cq_oi[0x1];
	u8         cq_resize[0x1];
	u8         cq_moderation[0x1];
1070
	u8         reserved_at_223[0x3];
1071
	u8         cq_eq_remap[0x1];
1072 1073
	u8         pg[0x1];
	u8         block_lb_mc[0x1];
1074
	u8         reserved_at_229[0x1];
1075
	u8         scqe_break_moderation[0x1];
1076
	u8         cq_period_start_from_cqe[0x1];
1077
	u8         cd[0x1];
1078
	u8         reserved_at_22d[0x1];
1079
	u8         apm[0x1];
1080
	u8         vector_calc[0x1];
1081
	u8         umr_ptr_rlky[0x1];
1082
	u8	   imaicl[0x1];
1083 1084
	u8	   qp_packet_based[0x1];
	u8         reserved_at_233[0x3];
1085 1086
	u8         qkv[0x1];
	u8         pkv[0x1];
1087 1088
	u8         set_deth_sqpn[0x1];
	u8         reserved_at_239[0x3];
1089 1090 1091 1092 1093
	u8         xrc[0x1];
	u8         ud[0x1];
	u8         uc[0x1];
	u8         rc[0x1];

1094 1095
	u8         uar_4k[0x1];
	u8         reserved_at_241[0x9];
1096
	u8         uar_sz[0x6];
1097
	u8         reserved_at_250[0x8];
1098 1099 1100
	u8         log_pg_sz[0x8];

	u8         bf[0x1];
1101
	u8         driver_version[0x1];
1102
	u8         pad_tx_eth_packet[0x1];
1103
	u8         reserved_at_263[0x8];
1104
	u8         log_bf_reg_size[0x5];
1105 1106 1107 1108

	u8         reserved_at_270[0xb];
	u8         lag_master[0x1];
	u8         num_lag_ports[0x4];
1109

1110
	u8         reserved_at_280[0x10];
1111 1112
	u8         max_wqe_sz_sq[0x10];

1113
	u8         reserved_at_2a0[0x10];
1114 1115
	u8         max_wqe_sz_rq[0x10];

1116
	u8         max_flow_counter_31_16[0x10];
1117 1118
	u8         max_wqe_sz_sq_dc[0x10];

1119
	u8         reserved_at_2e0[0x7];
1120 1121
	u8         max_qp_mcg[0x19];

1122
	u8         reserved_at_300[0x18];
1123 1124
	u8         log_max_mcg[0x8];

1125
	u8         reserved_at_320[0x3];
1126
	u8         log_max_transport_domain[0x5];
1127
	u8         reserved_at_328[0x3];
1128
	u8         log_max_pd[0x5];
1129
	u8         reserved_at_330[0xb];
1130 1131
	u8         log_max_xrcd[0x5];

1132
	u8         nic_receive_steering_discard[0x1];
1133 1134 1135
	u8         receive_discard_vport_down[0x1];
	u8         transmit_discard_vport_down[0x1];
	u8         reserved_at_343[0x5];
1136
	u8         log_max_flow_counter_bulk[0x8];
1137
	u8         max_flow_counter_15_0[0x10];
1138

1139

1140
	u8         reserved_at_360[0x3];
1141
	u8         log_max_rq[0x5];
1142
	u8         reserved_at_368[0x3];
1143
	u8         log_max_sq[0x5];
1144
	u8         reserved_at_370[0x3];
1145
	u8         log_max_tir[0x5];
1146
	u8         reserved_at_378[0x3];
1147 1148
	u8         log_max_tis[0x5];

1149
	u8         basic_cyclic_rcv_wqe[0x1];
1150
	u8         reserved_at_381[0x2];
1151
	u8         log_max_rmp[0x5];
1152
	u8         reserved_at_388[0x3];
1153
	u8         log_max_rqt[0x5];
1154
	u8         reserved_at_390[0x3];
1155
	u8         log_max_rqt_size[0x5];
1156
	u8         reserved_at_398[0x3];
1157 1158
	u8         log_max_tis_per_sq[0x5];

1159 1160
	u8         ext_stride_num_range[0x1];
	u8         reserved_at_3a1[0x2];
1161
	u8         log_max_stride_sz_rq[0x5];
1162
	u8         reserved_at_3a8[0x3];
1163
	u8         log_min_stride_sz_rq[0x5];
1164
	u8         reserved_at_3b0[0x3];
1165
	u8         log_max_stride_sz_sq[0x5];
1166
	u8         reserved_at_3b8[0x3];
1167 1168
	u8         log_min_stride_sz_sq[0x5];

1169 1170 1171 1172 1173
	u8         hairpin[0x1];
	u8         reserved_at_3c1[0x2];
	u8         log_max_hairpin_queues[0x5];
	u8         reserved_at_3c8[0x3];
	u8         log_max_hairpin_wq_data_sz[0x5];
1174 1175 1176
	u8         reserved_at_3d0[0x3];
	u8         log_max_hairpin_num_packets[0x5];
	u8         reserved_at_3d8[0x3];
1177 1178
	u8         log_max_wq_sz[0x5];

1179
	u8         nic_vport_change_event[0x1];
1180 1181
	u8         disable_local_lb_uc[0x1];
	u8         disable_local_lb_mc[0x1];
1182 1183
	u8         log_min_hairpin_wq_data_sz[0x5];
	u8         reserved_at_3e8[0x3];
1184
	u8         log_max_vlan_list[0x5];
1185
	u8         reserved_at_3f0[0x3];
1186
	u8         log_max_current_mc_list[0x5];
1187
	u8         reserved_at_3f8[0x3];
1188 1189
	u8         log_max_current_uc_list[0x5];

1190 1191
	u8         general_obj_types[0x40];

1192 1193
	u8         reserved_at_440[0x20];

1194 1195 1196 1197
	u8         reserved_at_460[0x3];
	u8         log_max_uctx[0x5];
	u8         reserved_at_468[0x3];
	u8         log_max_umem[0x5];
1198
	u8         max_num_eqs[0x10];
1199

1200
	u8         reserved_at_480[0x3];
1201
	u8         log_max_l2_table[0x5];
1202
	u8         reserved_at_488[0x8];
1203 1204
	u8         log_uar_page_sz[0x10];

1205
	u8         reserved_at_4a0[0x20];
1206
	u8         device_frequency_mhz[0x20];
1207
	u8         device_frequency_khz[0x20];
1208

1209 1210
	u8         reserved_at_500[0x20];
	u8	   num_of_uars_per_page[0x20];
1211

1212 1213
	u8         flex_parser_protocols[0x20];
	u8         reserved_at_560[0x20];
1214

1215 1216
	u8         reserved_at_580[0x3c];
	u8         mini_cqe_resp_stride_index[0x1];
1217 1218
	u8         cqe_128_always[0x1];
	u8         cqe_compression_128[0x1];
1219
	u8         cqe_compression[0x1];
1220

1221 1222
	u8         cqe_compression_timeout[0x10];
	u8         cqe_compression_max_num[0x10];
1223

1224 1225 1226 1227 1228
	u8         reserved_at_5e0[0x10];
	u8         tag_matching[0x1];
	u8         rndv_offload_rc[0x1];
	u8         rndv_offload_dc[0x1];
	u8         log_tag_matching_list_sz[0x5];
1229
	u8         reserved_at_5f8[0x3];
1230 1231
	u8         log_max_xrq[0x5];

1232 1233 1234 1235 1236
	u8	   affiliate_nic_vport_criteria[0x8];
	u8	   native_port_num[0x8];
	u8	   num_vhca_ports[0x8];
	u8	   reserved_at_618[0x6];
	u8	   sw_owner_id[0x1];
1237 1238
	u8         reserved_at_61f[0x1];

1239 1240 1241 1242 1243 1244 1245
	u8         max_num_of_monitor_counters[0x10];
	u8         num_ppcnt_monitor_counters[0x10];

	u8         reserved_at_640[0x10];
	u8         num_q_monitor_counters[0x10];

	u8         reserved_at_660[0x40];
1246 1247 1248 1249

	u8         uctx_cap[0x20];

	u8	   reserved_at_6c0[0x140];
1250 1251
};

1252 1253 1254 1255
enum mlx5_flow_destination_type {
	MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
	MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1256

1257
	MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1258
	MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1259
	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1260
};
1261

1262 1263 1264
struct mlx5_ifc_dest_format_struct_bits {
	u8         destination_type[0x8];
	u8         destination_id[0x18];
1265

1266
	u8         destination_eswitch_owner_vhca_id_valid[0x1];
1267 1268
	u8         packet_reformat[0x1];
	u8         reserved_at_22[0xe];
1269
	u8         destination_eswitch_owner_vhca_id[0x10];
1270 1271
};

1272
struct mlx5_ifc_flow_counter_list_bits {
1273
	u8         flow_counter_id[0x20];
1274 1275 1276 1277

	u8         reserved_at_20[0x20];
};

1278 1279 1280 1281 1282 1283 1284 1285
struct mlx5_ifc_extended_dest_format_bits {
	struct mlx5_ifc_dest_format_struct_bits destination_entry;

	u8         packet_reformat_id[0x20];

	u8         reserved_at_60[0x20];
};

1286 1287 1288 1289 1290 1291
union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
	struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
	u8         reserved_at_0[0x40];
};

1292 1293 1294 1295 1296 1297
struct mlx5_ifc_fte_match_param_bits {
	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;

	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;

	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1298

1299 1300 1301
	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;

	u8         reserved_at_800[0x800];
1302 1303
};

1304 1305 1306 1307 1308 1309 1310
enum {
	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
};
1311

1312 1313 1314 1315 1316
struct mlx5_ifc_rx_hash_field_select_bits {
	u8         l3_prot_type[0x1];
	u8         l4_prot_type[0x1];
	u8         selected_fields[0x1e];
};
1317

1318 1319 1320
enum {
	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1321 1322
};

1323 1324 1325 1326 1327 1328 1329 1330 1331 1332
enum {
	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
};

struct mlx5_ifc_wq_bits {
	u8         wq_type[0x4];
	u8         wq_signature[0x1];
	u8         end_padding_mode[0x2];
	u8         cd_slave[0x1];
1333
	u8         reserved_at_8[0x18];
1334

1335 1336
	u8         hds_skip_first_sge[0x1];
	u8         log2_hds_buf_size[0x3];
1337
	u8         reserved_at_24[0x7];
1338 1339
	u8         page_offset[0x5];
	u8         lwm[0x10];
1340

1341
	u8         reserved_at_40[0x8];
1342 1343
	u8         pd[0x18];

1344
	u8         reserved_at_60[0x8];
1345 1346 1347 1348 1349 1350 1351 1352
	u8         uar_page[0x18];

	u8         dbr_addr[0x40];

	u8         hw_counter[0x20];

	u8         sw_counter[0x20];

1353
	u8         reserved_at_100[0xc];
1354
	u8         log_wq_stride[0x4];
1355
	u8         reserved_at_110[0x3];
1356
	u8         log_wq_pg_sz[0x5];
1357
	u8         reserved_at_118[0x3];
1358 1359
	u8         log_wq_sz[0x5];

1360 1361 1362
	u8         dbr_umem_valid[0x1];
	u8         wq_umem_valid[0x1];
	u8         reserved_at_122[0x1];
1363 1364
	u8         log_hairpin_num_packets[0x5];
	u8         reserved_at_128[0x3];
1365 1366
	u8         log_hairpin_data_sz[0x5];

1367 1368
	u8         reserved_at_130[0x4];
	u8         log_wqe_num_of_strides[0x4];
1369 1370 1371 1372 1373
	u8         two_byte_shift_en[0x1];
	u8         reserved_at_139[0x4];
	u8         log_wqe_stride_size[0x3];

	u8         reserved_at_140[0x4c0];
1374

1375
	struct mlx5_ifc_cmd_pas_bits pas[0];
1376 1377
};

1378
struct mlx5_ifc_rq_num_bits {
1379
	u8         reserved_at_0[0x8];
1380 1381
	u8         rq_num[0x18];
};
1382

1383
struct mlx5_ifc_mac_address_layout_bits {
1384
	u8         reserved_at_0[0x10];
1385
	u8         mac_addr_47_32[0x10];
1386

1387 1388 1389
	u8         mac_addr_31_0[0x20];
};

1390
struct mlx5_ifc_vlan_layout_bits {
1391
	u8         reserved_at_0[0x14];
1392 1393
	u8         vlan[0x0c];

1394
	u8         reserved_at_20[0x20];
1395 1396
};

1397
struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1398
	u8         reserved_at_0[0xa0];
1399 1400 1401

	u8         min_time_between_cnps[0x20];

1402
	u8         reserved_at_c0[0x12];
1403
	u8         cnp_dscp[0x6];
1404 1405
	u8         reserved_at_d8[0x4];
	u8         cnp_prio_mode[0x1];
1406 1407
	u8         cnp_802p_prio[0x3];

1408
	u8         reserved_at_e0[0x720];
1409 1410 1411
};

struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1412
	u8         reserved_at_0[0x60];
1413

1414
	u8         reserved_at_60[0x4];
1415
	u8         clamp_tgt_rate[0x1];
1416
	u8         reserved_at_65[0x3];
1417
	u8         clamp_tgt_rate_after_time_inc[0x1];
1418
	u8         reserved_at_69[0x17];
1419

1420
	u8         reserved_at_80[0x20];
1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439

	u8         rpg_time_reset[0x20];

	u8         rpg_byte_reset[0x20];

	u8         rpg_threshold[0x20];

	u8         rpg_max_rate[0x20];

	u8         rpg_ai_rate[0x20];

	u8         rpg_hai_rate[0x20];

	u8         rpg_gd[0x20];

	u8         rpg_min_dec_fac[0x20];

	u8         rpg_min_rate[0x20];

1440
	u8         reserved_at_1c0[0xe0];
1441 1442 1443 1444 1445 1446 1447 1448 1449

	u8         rate_to_set_on_first_cnp[0x20];

	u8         dce_tcp_g[0x20];

	u8         dce_tcp_rtt[0x20];

	u8         rate_reduce_monitor_period[0x20];

1450
	u8         reserved_at_320[0x20];
1451 1452 1453

	u8         initial_alpha_value[0x20];

1454
	u8         reserved_at_360[0x4a0];
1455 1456 1457
};

struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1458
	u8         reserved_at_0[0x80];
1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479

	u8         rppp_max_rps[0x20];

	u8         rpg_time_reset[0x20];

	u8         rpg_byte_reset[0x20];

	u8         rpg_threshold[0x20];

	u8         rpg_max_rate[0x20];

	u8         rpg_ai_rate[0x20];

	u8         rpg_hai_rate[0x20];

	u8         rpg_gd[0x20];

	u8         rpg_min_dec_fac[0x20];

	u8         rpg_min_rate[0x20];

1480
	u8         reserved_at_1c0[0x640];
1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629
};

enum {
	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
};

struct mlx5_ifc_resize_field_select_bits {
	u8         resize_field_select[0x20];
};

enum {
	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
};

struct mlx5_ifc_modify_field_select_bits {
	u8         modify_field_select[0x20];
};

struct mlx5_ifc_field_select_r_roce_np_bits {
	u8         field_select_r_roce_np[0x20];
};

struct mlx5_ifc_field_select_r_roce_rp_bits {
	u8         field_select_r_roce_rp[0x20];
};

enum {
	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
};

struct mlx5_ifc_field_select_802_1qau_rp_bits {
	u8         field_select_8021qaurp[0x20];
};

struct mlx5_ifc_phys_layer_cntrs_bits {
	u8         time_since_last_clear_high[0x20];

	u8         time_since_last_clear_low[0x20];

	u8         symbol_errors_high[0x20];

	u8         symbol_errors_low[0x20];

	u8         sync_headers_errors_high[0x20];

	u8         sync_headers_errors_low[0x20];

	u8         edpl_bip_errors_lane0_high[0x20];

	u8         edpl_bip_errors_lane0_low[0x20];

	u8         edpl_bip_errors_lane1_high[0x20];

	u8         edpl_bip_errors_lane1_low[0x20];

	u8         edpl_bip_errors_lane2_high[0x20];

	u8         edpl_bip_errors_lane2_low[0x20];

	u8         edpl_bip_errors_lane3_high[0x20];

	u8         edpl_bip_errors_lane3_low[0x20];

	u8         fc_fec_corrected_blocks_lane0_high[0x20];

	u8         fc_fec_corrected_blocks_lane0_low[0x20];

	u8         fc_fec_corrected_blocks_lane1_high[0x20];

	u8         fc_fec_corrected_blocks_lane1_low[0x20];

	u8         fc_fec_corrected_blocks_lane2_high[0x20];

	u8         fc_fec_corrected_blocks_lane2_low[0x20];

	u8         fc_fec_corrected_blocks_lane3_high[0x20];

	u8         fc_fec_corrected_blocks_lane3_low[0x20];

	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];

	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];

	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];

	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];

	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];

	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];

	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];

	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];

	u8         rs_fec_corrected_blocks_high[0x20];

	u8         rs_fec_corrected_blocks_low[0x20];

	u8         rs_fec_uncorrectable_blocks_high[0x20];

	u8         rs_fec_uncorrectable_blocks_low[0x20];

	u8         rs_fec_no_errors_blocks_high[0x20];

	u8         rs_fec_no_errors_blocks_low[0x20];

	u8         rs_fec_single_error_blocks_high[0x20];

	u8         rs_fec_single_error_blocks_low[0x20];

	u8         rs_fec_corrected_symbols_total_high[0x20];

	u8         rs_fec_corrected_symbols_total_low[0x20];

	u8         rs_fec_corrected_symbols_lane0_high[0x20];

	u8         rs_fec_corrected_symbols_lane0_low[0x20];

	u8         rs_fec_corrected_symbols_lane1_high[0x20];

	u8         rs_fec_corrected_symbols_lane1_low[0x20];

	u8         rs_fec_corrected_symbols_lane2_high[0x20];

	u8         rs_fec_corrected_symbols_lane2_low[0x20];

	u8         rs_fec_corrected_symbols_lane3_high[0x20];

	u8         rs_fec_corrected_symbols_lane3_low[0x20];

	u8         link_down_events[0x20];

	u8         successful_recovery_events[0x20];

1630
	u8         reserved_at_640[0x180];
1631 1632
};

1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668
struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
	u8         time_since_last_clear_high[0x20];

	u8         time_since_last_clear_low[0x20];

	u8         phy_received_bits_high[0x20];

	u8         phy_received_bits_low[0x20];

	u8         phy_symbol_errors_high[0x20];

	u8         phy_symbol_errors_low[0x20];

	u8         phy_corrected_bits_high[0x20];

	u8         phy_corrected_bits_low[0x20];

	u8         phy_corrected_bits_lane0_high[0x20];

	u8         phy_corrected_bits_lane0_low[0x20];

	u8         phy_corrected_bits_lane1_high[0x20];

	u8         phy_corrected_bits_lane1_low[0x20];

	u8         phy_corrected_bits_lane2_high[0x20];

	u8         phy_corrected_bits_lane2_low[0x20];

	u8         phy_corrected_bits_lane3_high[0x20];

	u8         phy_corrected_bits_lane3_low[0x20];

	u8         reserved_at_200[0x5c0];
};

1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695
struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
	u8	   symbol_error_counter[0x10];

	u8         link_error_recovery_counter[0x8];

	u8         link_downed_counter[0x8];

	u8         port_rcv_errors[0x10];

	u8         port_rcv_remote_physical_errors[0x10];

	u8         port_rcv_switch_relay_errors[0x10];

	u8         port_xmit_discards[0x10];

	u8         port_xmit_constraint_errors[0x8];

	u8         port_rcv_constraint_errors[0x8];

	u8         reserved_at_70[0x8];

	u8         link_overrun_errors[0x8];

	u8	   reserved_at_80[0x10];

	u8         vl_15_dropped[0x10];

1696 1697 1698
	u8	   reserved_at_a0[0x80];

	u8         port_xmit_wait[0x20];
1699 1700
};

1701 1702 1703 1704 1705
struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
	u8         transmit_queue_high[0x20];

	u8         transmit_queue_low[0x20];

1706
	u8         reserved_at_40[0x780];
1707 1708 1709 1710 1711 1712 1713
};

struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
	u8         rx_octets_high[0x20];

	u8         rx_octets_low[0x20];

1714
	u8         reserved_at_40[0xc0];
1715 1716 1717 1718 1719 1720 1721 1722 1723

	u8         rx_frames_high[0x20];

	u8         rx_frames_low[0x20];

	u8         tx_octets_high[0x20];

	u8         tx_octets_low[0x20];

1724
	u8         reserved_at_180[0xc0];
1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749

	u8         tx_frames_high[0x20];

	u8         tx_frames_low[0x20];

	u8         rx_pause_high[0x20];

	u8         rx_pause_low[0x20];

	u8         rx_pause_duration_high[0x20];

	u8         rx_pause_duration_low[0x20];

	u8         tx_pause_high[0x20];

	u8         tx_pause_low[0x20];

	u8         tx_pause_duration_high[0x20];

	u8         tx_pause_duration_low[0x20];

	u8         rx_pause_transition_high[0x20];

	u8         rx_pause_transition_low[0x20];

1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760
	u8         reserved_at_3c0[0x40];

	u8         device_stall_minor_watermark_cnt_high[0x20];

	u8         device_stall_minor_watermark_cnt_low[0x20];

	u8         device_stall_critical_watermark_cnt_high[0x20];

	u8         device_stall_critical_watermark_cnt_low[0x20];

	u8         reserved_at_480[0x340];
1761 1762 1763 1764 1765 1766 1767
};

struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
	u8         port_transmit_wait_high[0x20];

	u8         port_transmit_wait_low[0x20];

1768 1769 1770 1771 1772 1773 1774 1775 1776 1777
	u8         reserved_at_40[0x100];

	u8         rx_buffer_almost_full_high[0x20];

	u8         rx_buffer_almost_full_low[0x20];

	u8         rx_buffer_full_high[0x20];

	u8         rx_buffer_full_low[0x20];

1778 1779 1780 1781 1782
	u8         rx_icrc_encapsulated_high[0x20];

	u8         rx_icrc_encapsulated_low[0x20];

	u8         reserved_at_200[0x5c0];
1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849
};

struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
	u8         dot3stats_alignment_errors_high[0x20];

	u8         dot3stats_alignment_errors_low[0x20];

	u8         dot3stats_fcs_errors_high[0x20];

	u8         dot3stats_fcs_errors_low[0x20];

	u8         dot3stats_single_collision_frames_high[0x20];

	u8         dot3stats_single_collision_frames_low[0x20];

	u8         dot3stats_multiple_collision_frames_high[0x20];

	u8         dot3stats_multiple_collision_frames_low[0x20];

	u8         dot3stats_sqe_test_errors_high[0x20];

	u8         dot3stats_sqe_test_errors_low[0x20];

	u8         dot3stats_deferred_transmissions_high[0x20];

	u8         dot3stats_deferred_transmissions_low[0x20];

	u8         dot3stats_late_collisions_high[0x20];

	u8         dot3stats_late_collisions_low[0x20];

	u8         dot3stats_excessive_collisions_high[0x20];

	u8         dot3stats_excessive_collisions_low[0x20];

	u8         dot3stats_internal_mac_transmit_errors_high[0x20];

	u8         dot3stats_internal_mac_transmit_errors_low[0x20];

	u8         dot3stats_carrier_sense_errors_high[0x20];

	u8         dot3stats_carrier_sense_errors_low[0x20];

	u8         dot3stats_frame_too_longs_high[0x20];

	u8         dot3stats_frame_too_longs_low[0x20];

	u8         dot3stats_internal_mac_receive_errors_high[0x20];

	u8         dot3stats_internal_mac_receive_errors_low[0x20];

	u8         dot3stats_symbol_errors_high[0x20];

	u8         dot3stats_symbol_errors_low[0x20];

	u8         dot3control_in_unknown_opcodes_high[0x20];

	u8         dot3control_in_unknown_opcodes_low[0x20];

	u8         dot3in_pause_frames_high[0x20];

	u8         dot3in_pause_frames_low[0x20];

	u8         dot3out_pause_frames_high[0x20];

	u8         dot3out_pause_frames_low[0x20];

1850
	u8         reserved_at_400[0x3c0];
1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937
};

struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
	u8         ether_stats_drop_events_high[0x20];

	u8         ether_stats_drop_events_low[0x20];

	u8         ether_stats_octets_high[0x20];

	u8         ether_stats_octets_low[0x20];

	u8         ether_stats_pkts_high[0x20];

	u8         ether_stats_pkts_low[0x20];

	u8         ether_stats_broadcast_pkts_high[0x20];

	u8         ether_stats_broadcast_pkts_low[0x20];

	u8         ether_stats_multicast_pkts_high[0x20];

	u8         ether_stats_multicast_pkts_low[0x20];

	u8         ether_stats_crc_align_errors_high[0x20];

	u8         ether_stats_crc_align_errors_low[0x20];

	u8         ether_stats_undersize_pkts_high[0x20];

	u8         ether_stats_undersize_pkts_low[0x20];

	u8         ether_stats_oversize_pkts_high[0x20];

	u8         ether_stats_oversize_pkts_low[0x20];

	u8         ether_stats_fragments_high[0x20];

	u8         ether_stats_fragments_low[0x20];

	u8         ether_stats_jabbers_high[0x20];

	u8         ether_stats_jabbers_low[0x20];

	u8         ether_stats_collisions_high[0x20];

	u8         ether_stats_collisions_low[0x20];

	u8         ether_stats_pkts64octets_high[0x20];

	u8         ether_stats_pkts64octets_low[0x20];

	u8         ether_stats_pkts65to127octets_high[0x20];

	u8         ether_stats_pkts65to127octets_low[0x20];

	u8         ether_stats_pkts128to255octets_high[0x20];

	u8         ether_stats_pkts128to255octets_low[0x20];

	u8         ether_stats_pkts256to511octets_high[0x20];

	u8         ether_stats_pkts256to511octets_low[0x20];

	u8         ether_stats_pkts512to1023octets_high[0x20];

	u8         ether_stats_pkts512to1023octets_low[0x20];

	u8         ether_stats_pkts1024to1518octets_high[0x20];

	u8         ether_stats_pkts1024to1518octets_low[0x20];

	u8         ether_stats_pkts1519to2047octets_high[0x20];

	u8         ether_stats_pkts1519to2047octets_low[0x20];

	u8         ether_stats_pkts2048to4095octets_high[0x20];

	u8         ether_stats_pkts2048to4095octets_low[0x20];

	u8         ether_stats_pkts4096to8191octets_high[0x20];

	u8         ether_stats_pkts4096to8191octets_low[0x20];

	u8         ether_stats_pkts8192to10239octets_high[0x20];

	u8         ether_stats_pkts8192to10239octets_low[0x20];

1938
	u8         reserved_at_540[0x280];
1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993
};

struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
	u8         if_in_octets_high[0x20];

	u8         if_in_octets_low[0x20];

	u8         if_in_ucast_pkts_high[0x20];

	u8         if_in_ucast_pkts_low[0x20];

	u8         if_in_discards_high[0x20];

	u8         if_in_discards_low[0x20];

	u8         if_in_errors_high[0x20];

	u8         if_in_errors_low[0x20];

	u8         if_in_unknown_protos_high[0x20];

	u8         if_in_unknown_protos_low[0x20];

	u8         if_out_octets_high[0x20];

	u8         if_out_octets_low[0x20];

	u8         if_out_ucast_pkts_high[0x20];

	u8         if_out_ucast_pkts_low[0x20];

	u8         if_out_discards_high[0x20];

	u8         if_out_discards_low[0x20];

	u8         if_out_errors_high[0x20];

	u8         if_out_errors_low[0x20];

	u8         if_in_multicast_pkts_high[0x20];

	u8         if_in_multicast_pkts_low[0x20];

	u8         if_in_broadcast_pkts_high[0x20];

	u8         if_in_broadcast_pkts_low[0x20];

	u8         if_out_multicast_pkts_high[0x20];

	u8         if_out_multicast_pkts_low[0x20];

	u8         if_out_broadcast_pkts_high[0x20];

	u8         if_out_broadcast_pkts_low[0x20];

1994
	u8         reserved_at_340[0x480];
1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073
};

struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
	u8         a_frames_transmitted_ok_high[0x20];

	u8         a_frames_transmitted_ok_low[0x20];

	u8         a_frames_received_ok_high[0x20];

	u8         a_frames_received_ok_low[0x20];

	u8         a_frame_check_sequence_errors_high[0x20];

	u8         a_frame_check_sequence_errors_low[0x20];

	u8         a_alignment_errors_high[0x20];

	u8         a_alignment_errors_low[0x20];

	u8         a_octets_transmitted_ok_high[0x20];

	u8         a_octets_transmitted_ok_low[0x20];

	u8         a_octets_received_ok_high[0x20];

	u8         a_octets_received_ok_low[0x20];

	u8         a_multicast_frames_xmitted_ok_high[0x20];

	u8         a_multicast_frames_xmitted_ok_low[0x20];

	u8         a_broadcast_frames_xmitted_ok_high[0x20];

	u8         a_broadcast_frames_xmitted_ok_low[0x20];

	u8         a_multicast_frames_received_ok_high[0x20];

	u8         a_multicast_frames_received_ok_low[0x20];

	u8         a_broadcast_frames_received_ok_high[0x20];

	u8         a_broadcast_frames_received_ok_low[0x20];

	u8         a_in_range_length_errors_high[0x20];

	u8         a_in_range_length_errors_low[0x20];

	u8         a_out_of_range_length_field_high[0x20];

	u8         a_out_of_range_length_field_low[0x20];

	u8         a_frame_too_long_errors_high[0x20];

	u8         a_frame_too_long_errors_low[0x20];

	u8         a_symbol_error_during_carrier_high[0x20];

	u8         a_symbol_error_during_carrier_low[0x20];

	u8         a_mac_control_frames_transmitted_high[0x20];

	u8         a_mac_control_frames_transmitted_low[0x20];

	u8         a_mac_control_frames_received_high[0x20];

	u8         a_mac_control_frames_received_low[0x20];

	u8         a_unsupported_opcodes_received_high[0x20];

	u8         a_unsupported_opcodes_received_low[0x20];

	u8         a_pause_mac_ctrl_frames_received_high[0x20];

	u8         a_pause_mac_ctrl_frames_received_low[0x20];

	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];

	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];

2074
	u8         reserved_at_4c0[0x300];
2075 2076
};

2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097
struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
	u8         life_time_counter_high[0x20];

	u8         life_time_counter_low[0x20];

	u8         rx_errors[0x20];

	u8         tx_errors[0x20];

	u8         l0_to_recovery_eieos[0x20];

	u8         l0_to_recovery_ts[0x20];

	u8         l0_to_recovery_framing[0x20];

	u8         l0_to_recovery_retrain[0x20];

	u8         crc_error_dllp[0x20];

	u8         crc_error_tlp[0x20];

2098 2099 2100
	u8         tx_overflow_buffer_pkt_high[0x20];

	u8         tx_overflow_buffer_pkt_low[0x20];
2101 2102 2103 2104 2105 2106 2107 2108 2109 2110

	u8         outbound_stalled_reads[0x20];

	u8         outbound_stalled_writes[0x20];

	u8         outbound_stalled_reads_events[0x20];

	u8         outbound_stalled_writes_events[0x20];

	u8         reserved_at_200[0x5c0];
2111 2112
};

2113 2114 2115
struct mlx5_ifc_cmd_inter_comp_event_bits {
	u8         command_completion_vector[0x20];

2116
	u8         reserved_at_20[0xc0];
2117 2118 2119
};

struct mlx5_ifc_stall_vl_event_bits {
2120
	u8         reserved_at_0[0x18];
2121
	u8         port_num[0x1];
2122
	u8         reserved_at_19[0x3];
2123 2124
	u8         vl[0x4];

2125
	u8         reserved_at_20[0xa0];
2126 2127 2128 2129
};

struct mlx5_ifc_db_bf_congestion_event_bits {
	u8         event_subtype[0x8];
2130
	u8         reserved_at_8[0x8];
2131
	u8         congestion_level[0x8];
2132
	u8         reserved_at_18[0x8];
2133

2134
	u8         reserved_at_20[0xa0];
2135 2136 2137
};

struct mlx5_ifc_gpio_event_bits {
2138
	u8         reserved_at_0[0x60];
2139 2140 2141 2142 2143

	u8         gpio_event_hi[0x20];

	u8         gpio_event_lo[0x20];

2144
	u8         reserved_at_a0[0x40];
2145 2146 2147
};

struct mlx5_ifc_port_state_change_event_bits {
2148
	u8         reserved_at_0[0x40];
2149 2150

	u8         port_num[0x4];
2151
	u8         reserved_at_44[0x1c];
2152

2153
	u8         reserved_at_60[0x80];
2154 2155 2156
};

struct mlx5_ifc_dropped_packet_logged_bits {
2157
	u8         reserved_at_0[0xe0];
2158 2159 2160 2161 2162 2163 2164 2165
};

enum {
	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
};

struct mlx5_ifc_cq_error_bits {
2166
	u8         reserved_at_0[0x8];
2167 2168
	u8         cqn[0x18];

2169
	u8         reserved_at_20[0x20];
2170

2171
	u8         reserved_at_40[0x18];
2172 2173
	u8         syndrome[0x8];

2174
	u8         reserved_at_60[0x80];
2175 2176 2177 2178 2179 2180 2181
};

struct mlx5_ifc_rdma_page_fault_event_bits {
	u8         bytes_committed[0x20];

	u8         r_key[0x20];

2182
	u8         reserved_at_40[0x10];
2183 2184 2185 2186 2187 2188
	u8         packet_len[0x10];

	u8         rdma_op_len[0x20];

	u8         rdma_va[0x40];

2189
	u8         reserved_at_c0[0x5];
2190 2191 2192 2193 2194 2195 2196 2197 2198
	u8         rdma[0x1];
	u8         write[0x1];
	u8         requestor[0x1];
	u8         qp_number[0x18];
};

struct mlx5_ifc_wqe_associated_page_fault_event_bits {
	u8         bytes_committed[0x20];

2199
	u8         reserved_at_20[0x10];
2200 2201
	u8         wqe_index[0x10];

2202
	u8         reserved_at_40[0x10];
2203 2204
	u8         len[0x10];

2205
	u8         reserved_at_60[0x60];
2206

2207
	u8         reserved_at_c0[0x5];
2208 2209 2210 2211 2212 2213 2214
	u8         rdma[0x1];
	u8         write_read[0x1];
	u8         requestor[0x1];
	u8         qpn[0x18];
};

struct mlx5_ifc_qp_events_bits {
2215
	u8         reserved_at_0[0xa0];
2216 2217

	u8         type[0x8];
2218
	u8         reserved_at_a8[0x18];
2219

2220
	u8         reserved_at_c0[0x8];
2221 2222 2223 2224
	u8         qpn_rqn_sqn[0x18];
};

struct mlx5_ifc_dct_events_bits {
2225
	u8         reserved_at_0[0xc0];
2226

2227
	u8         reserved_at_c0[0x8];
2228 2229 2230 2231
	u8         dct_number[0x18];
};

struct mlx5_ifc_comp_event_bits {
2232
	u8         reserved_at_0[0xc0];
2233

2234
	u8         reserved_at_c0[0x8];
2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267
	u8         cq_number[0x18];
};

enum {
	MLX5_QPC_STATE_RST        = 0x0,
	MLX5_QPC_STATE_INIT       = 0x1,
	MLX5_QPC_STATE_RTR        = 0x2,
	MLX5_QPC_STATE_RTS        = 0x3,
	MLX5_QPC_STATE_SQER       = 0x4,
	MLX5_QPC_STATE_ERR        = 0x6,
	MLX5_QPC_STATE_SQD        = 0x7,
	MLX5_QPC_STATE_SUSPENDED  = 0x9,
};

enum {
	MLX5_QPC_ST_RC            = 0x0,
	MLX5_QPC_ST_UC            = 0x1,
	MLX5_QPC_ST_UD            = 0x2,
	MLX5_QPC_ST_XRC           = 0x3,
	MLX5_QPC_ST_DCI           = 0x5,
	MLX5_QPC_ST_QP0           = 0x7,
	MLX5_QPC_ST_QP1           = 0x8,
	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
	MLX5_QPC_ST_REG_UMR       = 0xc,
};

enum {
	MLX5_QPC_PM_STATE_ARMED     = 0x0,
	MLX5_QPC_PM_STATE_REARM     = 0x1,
	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
};

2268 2269 2270 2271
enum {
	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
};

2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310
enum {
	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
};

enum {
	MLX5_QPC_MTU_256_BYTES        = 0x1,
	MLX5_QPC_MTU_512_BYTES        = 0x2,
	MLX5_QPC_MTU_1K_BYTES         = 0x3,
	MLX5_QPC_MTU_2K_BYTES         = 0x4,
	MLX5_QPC_MTU_4K_BYTES         = 0x5,
	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
};

enum {
	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
};

enum {
	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
};

enum {
	MLX5_QPC_CS_RES_DISABLE    = 0x0,
	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
};

struct mlx5_ifc_qpc_bits {
	u8         state[0x4];
2311
	u8         lag_tx_port_affinity[0x4];
2312
	u8         st[0x8];
2313
	u8         reserved_at_10[0x3];
2314
	u8         pm_state[0x2];
2315 2316
	u8         reserved_at_15[0x1];
	u8         req_e2e_credit_mode[0x2];
2317
	u8         offload_type[0x4];
2318
	u8         end_padding_mode[0x2];
2319
	u8         reserved_at_1e[0x2];
2320 2321 2322 2323 2324

	u8         wq_signature[0x1];
	u8         block_lb_mc[0x1];
	u8         atomic_like_write_en[0x1];
	u8         latency_sensitive[0x1];
2325
	u8         reserved_at_24[0x1];
2326
	u8         drain_sigerr[0x1];
2327
	u8         reserved_at_26[0x2];
2328 2329 2330 2331
	u8         pd[0x18];

	u8         mtu[0x3];
	u8         log_msg_max[0x5];
2332
	u8         reserved_at_48[0x1];
2333 2334 2335 2336
	u8         log_rq_size[0x4];
	u8         log_rq_stride[0x3];
	u8         no_sq[0x1];
	u8         log_sq_size[0x4];
2337
	u8         reserved_at_55[0x6];
2338
	u8         rlky[0x1];
2339
	u8         ulp_stateless_offload_mode[0x4];
2340 2341 2342 2343

	u8         counter_set_id[0x8];
	u8         uar_page[0x18];

2344
	u8         reserved_at_80[0x8];
2345 2346
	u8         user_index[0x18];

2347
	u8         reserved_at_a0[0x3];
2348 2349 2350 2351 2352 2353 2354 2355
	u8         log_page_size[0x5];
	u8         remote_qpn[0x18];

	struct mlx5_ifc_ads_bits primary_address_path;

	struct mlx5_ifc_ads_bits secondary_address_path;

	u8         log_ack_req_freq[0x4];
2356
	u8         reserved_at_384[0x4];
2357
	u8         log_sra_max[0x3];
2358
	u8         reserved_at_38b[0x2];
2359 2360
	u8         retry_count[0x3];
	u8         rnr_retry[0x3];
2361
	u8         reserved_at_393[0x1];
2362 2363 2364
	u8         fre[0x1];
	u8         cur_rnr_retry[0x3];
	u8         cur_retry_count[0x3];
2365
	u8         reserved_at_39b[0x5];
2366

2367
	u8         reserved_at_3a0[0x20];
2368

2369
	u8         reserved_at_3c0[0x8];
2370 2371
	u8         next_send_psn[0x18];

2372
	u8         reserved_at_3e0[0x8];
2373 2374
	u8         cqn_snd[0x18];

2375 2376 2377 2378
	u8         reserved_at_400[0x8];
	u8         deth_sqpn[0x18];

	u8         reserved_at_420[0x20];
2379

2380
	u8         reserved_at_440[0x8];
2381 2382
	u8         last_acked_psn[0x18];

2383
	u8         reserved_at_460[0x8];
2384 2385
	u8         ssn[0x18];

2386
	u8         reserved_at_480[0x8];
2387
	u8         log_rra_max[0x3];
2388
	u8         reserved_at_48b[0x1];
2389 2390 2391 2392
	u8         atomic_mode[0x4];
	u8         rre[0x1];
	u8         rwe[0x1];
	u8         rae[0x1];
2393
	u8         reserved_at_493[0x1];
2394
	u8         page_offset[0x6];
2395
	u8         reserved_at_49a[0x3];
2396 2397 2398 2399
	u8         cd_slave_receive[0x1];
	u8         cd_slave_send[0x1];
	u8         cd_master[0x1];

2400
	u8         reserved_at_4a0[0x3];
2401 2402 2403
	u8         min_rnr_nak[0x5];
	u8         next_rcv_psn[0x18];

2404
	u8         reserved_at_4c0[0x8];
2405 2406
	u8         xrcd[0x18];

2407
	u8         reserved_at_4e0[0x8];
2408 2409 2410 2411 2412 2413
	u8         cqn_rcv[0x18];

	u8         dbr_addr[0x40];

	u8         q_key[0x20];

2414
	u8         reserved_at_560[0x5];
2415
	u8         rq_type[0x3];
2416
	u8         srqn_rmpn_xrqn[0x18];
2417

2418
	u8         reserved_at_580[0x8];
2419 2420 2421 2422 2423 2424 2425 2426 2427
	u8         rmsn[0x18];

	u8         hw_sq_wqebb_counter[0x10];
	u8         sw_sq_wqebb_counter[0x10];

	u8         hw_rq_counter[0x20];

	u8         sw_rq_counter[0x20];

2428
	u8         reserved_at_600[0x20];
2429

2430
	u8         reserved_at_620[0xf];
2431 2432 2433 2434 2435 2436
	u8         cgs[0x1];
	u8         cs_req[0x8];
	u8         cs_res[0x8];

	u8         dc_access_key[0x40];

2437 2438 2439 2440
	u8         reserved_at_680[0x3];
	u8         dbr_umem_valid[0x1];

	u8         reserved_at_684[0xbc];
2441 2442 2443 2444 2445
};

struct mlx5_ifc_roce_addr_layout_bits {
	u8         source_l3_address[16][0x8];

2446
	u8         reserved_at_80[0x3];
2447 2448 2449 2450 2451 2452
	u8         vlan_valid[0x1];
	u8         vlan_id[0xc];
	u8         source_mac_47_32[0x10];

	u8         source_mac_31_0[0x20];

2453
	u8         reserved_at_c0[0x14];
2454 2455 2456
	u8         roce_l3_type[0x4];
	u8         roce_version[0x8];

2457
	u8         reserved_at_e0[0x20];
2458 2459 2460 2461 2462 2463 2464 2465 2466
};

union mlx5_ifc_hca_cap_union_bits {
	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
	struct mlx5_ifc_odp_cap_bits odp_cap;
	struct mlx5_ifc_atomic_caps_bits atomic_caps;
	struct mlx5_ifc_roce_cap_bits roce_cap;
	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2467
	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2468
	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2469
	struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2470
	struct mlx5_ifc_qos_cap_bits qos_cap;
2471
	struct mlx5_ifc_fpga_cap_bits fpga_cap;
2472
	u8         reserved_at_0[0x8000];
2473 2474 2475 2476 2477 2478
};

enum {
	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2479
	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2480
	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2481
	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2482
	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2483 2484
	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2485 2486
	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2487 2488 2489 2490 2491 2492 2493
};

struct mlx5_ifc_vlan_bits {
	u8         ethtype[0x10];
	u8         prio[0x3];
	u8         cfi[0x1];
	u8         vid[0xc];
2494 2495 2496
};

struct mlx5_ifc_flow_context_bits {
2497
	struct mlx5_ifc_vlan_bits push_vlan;
2498 2499 2500

	u8         group_id[0x20];

2501
	u8         reserved_at_40[0x8];
2502 2503
	u8         flow_tag[0x18];

2504
	u8         reserved_at_60[0x10];
2505 2506
	u8         action[0x10];

2507 2508
	u8         extended_destination[0x1];
	u8         reserved_at_80[0x7];
2509 2510
	u8         destination_list_size[0x18];

2511 2512 2513
	u8         reserved_at_a0[0x8];
	u8         flow_counter_list_size[0x18];

2514
	u8         packet_reformat_id[0x20];
2515

2516 2517
	u8         modify_header_id[0x20];

2518 2519 2520
	struct mlx5_ifc_vlan_bits push_vlan_2;

	u8         reserved_at_120[0xe0];
2521 2522 2523

	struct mlx5_ifc_fte_match_param_bits match_value;

2524
	u8         reserved_at_1200[0x600];
2525

2526
	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2527 2528 2529 2530 2531 2532 2533 2534 2535 2536
};

enum {
	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
};

struct mlx5_ifc_xrc_srqc_bits {
	u8         state[0x4];
	u8         log_xrc_srq_size[0x4];
2537
	u8         reserved_at_8[0x18];
2538 2539 2540

	u8         wq_signature[0x1];
	u8         cont_srq[0x1];
2541
	u8         reserved_at_22[0x1];
2542 2543 2544 2545 2546 2547
	u8         rlky[0x1];
	u8         basic_cyclic_rcv_wqe[0x1];
	u8         log_rq_stride[0x3];
	u8         xrcd[0x18];

	u8         page_offset[0x6];
2548 2549
	u8         reserved_at_46[0x1];
	u8         dbr_umem_valid[0x1];
2550 2551
	u8         cqn[0x18];

2552
	u8         reserved_at_60[0x20];
2553 2554

	u8         user_index_equal_xrc_srqn[0x1];
2555
	u8         reserved_at_81[0x1];
2556 2557 2558
	u8         log_page_size[0x6];
	u8         user_index[0x18];

2559
	u8         reserved_at_a0[0x20];
2560

2561
	u8         reserved_at_c0[0x8];
2562 2563 2564 2565 2566
	u8         pd[0x18];

	u8         lwm[0x10];
	u8         wqe_cnt[0x10];

2567
	u8         reserved_at_100[0x40];
2568 2569 2570 2571

	u8         db_record_addr_h[0x20];

	u8         db_record_addr_l[0x1e];
2572
	u8         reserved_at_17e[0x2];
2573

2574
	u8         reserved_at_180[0x80];
2575 2576
};

2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594
struct mlx5_ifc_vnic_diagnostic_statistics_bits {
	u8         counter_error_queues[0x20];

	u8         total_error_queues[0x20];

	u8         send_queue_priority_update_flow[0x20];

	u8         reserved_at_60[0x20];

	u8         nic_receive_steering_discard[0x40];

	u8         receive_discard_vport_down[0x40];

	u8         transmit_discard_vport_down[0x40];

	u8         reserved_at_140[0xec0];
};

2595 2596 2597 2598 2599 2600 2601
struct mlx5_ifc_traffic_counter_bits {
	u8         packets[0x40];

	u8         octets[0x40];
};

struct mlx5_ifc_tisc_bits {
2602 2603 2604 2605 2606
	u8         strict_lag_tx_port_affinity[0x1];
	u8         reserved_at_1[0x3];
	u8         lag_tx_port_affinity[0x04];

	u8         reserved_at_8[0x4];
2607
	u8         prio[0x4];
2608
	u8         reserved_at_10[0x10];
2609

2610
	u8         reserved_at_20[0x100];
2611

2612
	u8         reserved_at_120[0x8];
2613 2614
	u8         transport_domain[0x18];

2615 2616 2617
	u8         reserved_at_140[0x8];
	u8         underlay_qpn[0x18];
	u8         reserved_at_160[0x3a0];
2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630
};

enum {
	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
};

enum {
	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
};

enum {
2631 2632 2633
	MLX5_RX_HASH_FN_NONE           = 0x0,
	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2634 2635 2636
};

enum {
2637 2638
	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2639 2640 2641
};

struct mlx5_ifc_tirc_bits {
2642
	u8         reserved_at_0[0x20];
2643 2644

	u8         disp_type[0x4];
2645
	u8         reserved_at_24[0x1c];
2646

2647
	u8         reserved_at_40[0x40];
2648

2649
	u8         reserved_at_80[0x4];
2650 2651 2652 2653
	u8         lro_timeout_period_usecs[0x10];
	u8         lro_enable_mask[0x4];
	u8         lro_max_ip_payload_size[0x8];

2654
	u8         reserved_at_a0[0x40];
2655

2656
	u8         reserved_at_e0[0x8];
2657 2658 2659
	u8         inline_rqn[0x18];

	u8         rx_hash_symmetric[0x1];
2660
	u8         reserved_at_101[0x1];
2661
	u8         tunneled_offload_en[0x1];
2662
	u8         reserved_at_103[0x5];
2663 2664 2665
	u8         indirect_table[0x18];

	u8         rx_hash_fn[0x4];
2666
	u8         reserved_at_124[0x2];
2667 2668 2669 2670 2671 2672 2673 2674 2675
	u8         self_lb_block[0x2];
	u8         transport_domain[0x18];

	u8         rx_hash_toeplitz_key[10][0x20];

	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;

	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;

2676
	u8         reserved_at_2c0[0x4c0];
2677 2678 2679 2680 2681 2682 2683 2684 2685 2686
};

enum {
	MLX5_SRQC_STATE_GOOD   = 0x0,
	MLX5_SRQC_STATE_ERROR  = 0x1,
};

struct mlx5_ifc_srqc_bits {
	u8         state[0x4];
	u8         log_srq_size[0x4];
2687
	u8         reserved_at_8[0x18];
2688 2689 2690

	u8         wq_signature[0x1];
	u8         cont_srq[0x1];
2691
	u8         reserved_at_22[0x1];
2692
	u8         rlky[0x1];
2693
	u8         reserved_at_24[0x1];
2694 2695 2696 2697
	u8         log_rq_stride[0x3];
	u8         xrcd[0x18];

	u8         page_offset[0x6];
2698
	u8         reserved_at_46[0x2];
2699 2700
	u8         cqn[0x18];

2701
	u8         reserved_at_60[0x20];
2702

2703
	u8         reserved_at_80[0x2];
2704
	u8         log_page_size[0x6];
2705
	u8         reserved_at_88[0x18];
2706

2707
	u8         reserved_at_a0[0x20];
2708

2709
	u8         reserved_at_c0[0x8];
2710 2711 2712 2713 2714
	u8         pd[0x18];

	u8         lwm[0x10];
	u8         wqe_cnt[0x10];

2715
	u8         reserved_at_100[0x40];
2716

2717
	u8         dbr_addr[0x40];
2718

2719
	u8         reserved_at_180[0x80];
2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732
};

enum {
	MLX5_SQC_STATE_RST  = 0x0,
	MLX5_SQC_STATE_RDY  = 0x1,
	MLX5_SQC_STATE_ERR  = 0x3,
};

struct mlx5_ifc_sqc_bits {
	u8         rlky[0x1];
	u8         cd_master[0x1];
	u8         fre[0x1];
	u8         flush_in_error_en[0x1];
2733
	u8         allow_multi_pkt_send_wqe[0x1];
2734
	u8	   min_wqe_inline_mode[0x3];
2735
	u8         state[0x4];
2736
	u8         reg_umr[0x1];
2737
	u8         allow_swp[0x1];
2738 2739
	u8         hairpin[0x1];
	u8         reserved_at_f[0x11];
2740

2741
	u8         reserved_at_20[0x8];
2742 2743
	u8         user_index[0x18];

2744
	u8         reserved_at_40[0x8];
2745 2746
	u8         cqn[0x18];

2747 2748 2749 2750 2751 2752 2753
	u8         reserved_at_60[0x8];
	u8         hairpin_peer_rq[0x18];

	u8         reserved_at_80[0x10];
	u8         hairpin_peer_vhca[0x10];

	u8         reserved_at_a0[0x50];
2754

2755
	u8         packet_pacing_rate_limit_index[0x10];
2756
	u8         tis_lst_sz[0x10];
2757
	u8         reserved_at_110[0x10];
2758

2759
	u8         reserved_at_120[0x40];
2760

2761
	u8         reserved_at_160[0x8];
2762 2763 2764 2765 2766
	u8         tis_num_0[0x18];

	struct mlx5_ifc_wq_bits wq;
};

2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790
enum {
	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
};

struct mlx5_ifc_scheduling_context_bits {
	u8         element_type[0x8];
	u8         reserved_at_8[0x18];

	u8         element_attributes[0x20];

	u8         parent_element_id[0x20];

	u8         reserved_at_60[0x40];

	u8         bw_share[0x20];

	u8         max_average_bw[0x20];

	u8         reserved_at_e0[0x120];
};

2791
struct mlx5_ifc_rqtc_bits {
2792
	u8         reserved_at_0[0xa0];
2793

2794
	u8         reserved_at_a0[0x10];
2795 2796
	u8         rqt_max_size[0x10];

2797
	u8         reserved_at_c0[0x10];
2798 2799
	u8         rqt_actual_size[0x10];

2800
	u8         reserved_at_e0[0x6a0];
2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817

	struct mlx5_ifc_rq_num_bits rq_num[0];
};

enum {
	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
};

enum {
	MLX5_RQC_STATE_RST  = 0x0,
	MLX5_RQC_STATE_RDY  = 0x1,
	MLX5_RQC_STATE_ERR  = 0x3,
};

struct mlx5_ifc_rqc_bits {
	u8         rlky[0x1];
2818
	u8	   delay_drop_en[0x1];
2819
	u8         scatter_fcs[0x1];
2820 2821 2822
	u8         vsd[0x1];
	u8         mem_rq_type[0x4];
	u8         state[0x4];
2823
	u8         reserved_at_c[0x1];
2824
	u8         flush_in_error_en[0x1];
2825 2826
	u8         hairpin[0x1];
	u8         reserved_at_f[0x11];
2827

2828
	u8         reserved_at_20[0x8];
2829 2830
	u8         user_index[0x18];

2831
	u8         reserved_at_40[0x8];
2832 2833 2834
	u8         cqn[0x18];

	u8         counter_set_id[0x8];
2835
	u8         reserved_at_68[0x18];
2836

2837
	u8         reserved_at_80[0x8];
2838 2839
	u8         rmpn[0x18];

2840 2841 2842 2843 2844 2845 2846
	u8         reserved_at_a0[0x8];
	u8         hairpin_peer_sq[0x18];

	u8         reserved_at_c0[0x10];
	u8         hairpin_peer_vhca[0x10];

	u8         reserved_at_e0[0xa0];
2847 2848 2849 2850 2851 2852 2853 2854 2855 2856

	struct mlx5_ifc_wq_bits wq;
};

enum {
	MLX5_RMPC_STATE_RDY  = 0x1,
	MLX5_RMPC_STATE_ERR  = 0x3,
};

struct mlx5_ifc_rmpc_bits {
2857
	u8         reserved_at_0[0x8];
2858
	u8         state[0x4];
2859
	u8         reserved_at_c[0x14];
2860 2861

	u8         basic_cyclic_rcv_wqe[0x1];
2862
	u8         reserved_at_21[0x1f];
2863

2864
	u8         reserved_at_40[0x140];
2865 2866 2867 2868 2869

	struct mlx5_ifc_wq_bits wq;
};

struct mlx5_ifc_nic_vport_context_bits {
2870 2871
	u8         reserved_at_0[0x5];
	u8         min_wqe_inline_mode[0x3];
2872 2873 2874
	u8         reserved_at_8[0x15];
	u8         disable_mc_local_lb[0x1];
	u8         disable_uc_local_lb[0x1];
2875 2876
	u8         roce_en[0x1];

2877
	u8         arm_change_event[0x1];
2878
	u8         reserved_at_21[0x1a];
2879 2880 2881 2882 2883
	u8         event_on_mtu[0x1];
	u8         event_on_promisc_change[0x1];
	u8         event_on_vlan_change[0x1];
	u8         event_on_mc_address_change[0x1];
	u8         event_on_uc_address_change[0x1];
2884

2885 2886 2887 2888 2889 2890
	u8         reserved_at_40[0xc];

	u8	   affiliation_criteria[0x4];
	u8	   affiliated_vhca_id[0x10];

	u8	   reserved_at_60[0xd0];
2891 2892 2893

	u8         mtu[0x10];

2894 2895 2896 2897
	u8         system_image_guid[0x40];
	u8         port_guid[0x40];
	u8         node_guid[0x40];

2898
	u8         reserved_at_200[0x140];
2899
	u8         qkey_violation_counter[0x10];
2900
	u8         reserved_at_350[0x430];
2901 2902 2903 2904

	u8         promisc_uc[0x1];
	u8         promisc_mc[0x1];
	u8         promisc_all[0x1];
2905
	u8         reserved_at_783[0x2];
2906
	u8         allowed_list_type[0x3];
2907
	u8         reserved_at_788[0xc];
2908 2909 2910 2911
	u8         allowed_list_size[0xc];

	struct mlx5_ifc_mac_address_layout_bits permanent_address;

2912
	u8         reserved_at_7e0[0x20];
2913 2914 2915 2916 2917 2918 2919 2920

	u8         current_uc_mac_address[0][0x40];
};

enum {
	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2921
	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2922
	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2923 2924 2925
};

struct mlx5_ifc_mkc_bits {
2926
	u8         reserved_at_0[0x1];
2927
	u8         free[0x1];
2928 2929 2930 2931 2932
	u8         reserved_at_2[0x1];
	u8         access_mode_4_2[0x3];
	u8         reserved_at_6[0x7];
	u8         relaxed_ordering_write[0x1];
	u8         reserved_at_e[0x1];
2933 2934 2935 2936 2937 2938 2939
	u8         small_fence_on_rdma_read_response[0x1];
	u8         umr_en[0x1];
	u8         a[0x1];
	u8         rw[0x1];
	u8         rr[0x1];
	u8         lw[0x1];
	u8         lr[0x1];
2940
	u8         access_mode_1_0[0x2];
2941
	u8         reserved_at_18[0x8];
2942 2943 2944 2945

	u8         qpn[0x18];
	u8         mkey_7_0[0x8];

2946
	u8         reserved_at_40[0x20];
2947 2948 2949 2950

	u8         length64[0x1];
	u8         bsf_en[0x1];
	u8         sync_umr[0x1];
2951
	u8         reserved_at_63[0x2];
2952
	u8         expected_sigerr_count[0x1];
2953
	u8         reserved_at_66[0x1];
2954 2955 2956 2957 2958 2959 2960 2961 2962
	u8         en_rinval[0x1];
	u8         pd[0x18];

	u8         start_addr[0x40];

	u8         len[0x40];

	u8         bsf_octword_size[0x20];

2963
	u8         reserved_at_120[0x80];
2964 2965 2966

	u8         translations_octword_size[0x20];

2967
	u8         reserved_at_1c0[0x1b];
2968 2969
	u8         log_page_size[0x5];

2970
	u8         reserved_at_1e0[0x20];
2971 2972 2973
};

struct mlx5_ifc_pkey_bits {
2974
	u8         reserved_at_0[0x10];
2975 2976 2977 2978 2979 2980 2981 2982 2983 2984
	u8         pkey[0x10];
};

struct mlx5_ifc_array128_auto_bits {
	u8         array128_auto[16][0x8];
};

struct mlx5_ifc_hca_vport_context_bits {
	u8         field_select[0x20];

2985
	u8         reserved_at_20[0xe0];
2986 2987 2988 2989 2990

	u8         sm_virt_aware[0x1];
	u8         has_smi[0x1];
	u8         has_raw[0x1];
	u8         grh_required[0x1];
2991
	u8         reserved_at_104[0xc];
2992 2993 2994
	u8         port_physical_state[0x4];
	u8         vport_state_policy[0x4];
	u8         port_state[0x4];
2995 2996
	u8         vport_state[0x4];

2997
	u8         reserved_at_120[0x20];
2998 2999

	u8         system_image_guid[0x40];
3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012

	u8         port_guid[0x40];

	u8         node_guid[0x40];

	u8         cap_mask1[0x20];

	u8         cap_mask1_field_select[0x20];

	u8         cap_mask2[0x20];

	u8         cap_mask2_field_select[0x20];

3013
	u8         reserved_at_280[0x80];
3014 3015

	u8         lid[0x10];
3016
	u8         reserved_at_310[0x4];
3017 3018 3019 3020 3021 3022
	u8         init_type_reply[0x4];
	u8         lmc[0x3];
	u8         subnet_timeout[0x5];

	u8         sm_lid[0x10];
	u8         sm_sl[0x4];
3023
	u8         reserved_at_334[0xc];
3024 3025 3026 3027

	u8         qkey_violation_counter[0x10];
	u8         pkey_violation_counter[0x10];

3028
	u8         reserved_at_360[0xca0];
3029 3030
};

3031
struct mlx5_ifc_esw_vport_context_bits {
3032
	u8         reserved_at_0[0x3];
3033 3034 3035 3036
	u8         vport_svlan_strip[0x1];
	u8         vport_cvlan_strip[0x1];
	u8         vport_svlan_insert[0x1];
	u8         vport_cvlan_insert[0x2];
3037
	u8         reserved_at_8[0x18];
3038

3039
	u8         reserved_at_20[0x20];
3040 3041 3042 3043 3044 3045 3046 3047

	u8         svlan_cfi[0x1];
	u8         svlan_pcp[0x3];
	u8         svlan_id[0xc];
	u8         cvlan_cfi[0x1];
	u8         cvlan_pcp[0x3];
	u8         cvlan_id[0xc];

3048
	u8         reserved_at_60[0x7a0];
3049 3050
};

3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062
enum {
	MLX5_EQC_STATUS_OK                = 0x0,
	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
};

enum {
	MLX5_EQC_ST_ARMED  = 0x9,
	MLX5_EQC_ST_FIRED  = 0xa,
};

struct mlx5_ifc_eqc_bits {
	u8         status[0x4];
3063
	u8         reserved_at_4[0x9];
3064 3065
	u8         ec[0x1];
	u8         oi[0x1];
3066
	u8         reserved_at_f[0x5];
3067
	u8         st[0x4];
3068
	u8         reserved_at_18[0x8];
3069

3070
	u8         reserved_at_20[0x20];
3071

3072
	u8         reserved_at_40[0x14];
3073
	u8         page_offset[0x6];
3074
	u8         reserved_at_5a[0x6];
3075

3076
	u8         reserved_at_60[0x3];
3077 3078 3079
	u8         log_eq_size[0x5];
	u8         uar_page[0x18];

3080
	u8         reserved_at_80[0x20];
3081

3082
	u8         reserved_at_a0[0x18];
3083 3084
	u8         intr[0x8];

3085
	u8         reserved_at_c0[0x3];
3086
	u8         log_page_size[0x5];
3087
	u8         reserved_at_c8[0x18];
3088

3089
	u8         reserved_at_e0[0x60];
3090

3091
	u8         reserved_at_140[0x8];
3092 3093
	u8         consumer_counter[0x18];

3094
	u8         reserved_at_160[0x8];
3095 3096
	u8         producer_counter[0x18];

3097
	u8         reserved_at_180[0x80];
3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120
};

enum {
	MLX5_DCTC_STATE_ACTIVE    = 0x0,
	MLX5_DCTC_STATE_DRAINING  = 0x1,
	MLX5_DCTC_STATE_DRAINED   = 0x2,
};

enum {
	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
	MLX5_DCTC_CS_RES_NA         = 0x1,
	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
};

enum {
	MLX5_DCTC_MTU_256_BYTES  = 0x1,
	MLX5_DCTC_MTU_512_BYTES  = 0x2,
	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
};

struct mlx5_ifc_dctc_bits {
3121
	u8         reserved_at_0[0x4];
3122
	u8         state[0x4];
3123
	u8         reserved_at_8[0x18];
3124

3125
	u8         reserved_at_20[0x8];
3126 3127
	u8         user_index[0x18];

3128
	u8         reserved_at_40[0x8];
3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139
	u8         cqn[0x18];

	u8         counter_set_id[0x8];
	u8         atomic_mode[0x4];
	u8         rre[0x1];
	u8         rwe[0x1];
	u8         rae[0x1];
	u8         atomic_like_write_en[0x1];
	u8         latency_sensitive[0x1];
	u8         rlky[0x1];
	u8         free_ar[0x1];
3140
	u8         reserved_at_73[0xd];
3141

3142
	u8         reserved_at_80[0x8];
3143
	u8         cs_res[0x8];
3144
	u8         reserved_at_90[0x3];
3145
	u8         min_rnr_nak[0x5];
3146
	u8         reserved_at_98[0x8];
3147

3148
	u8         reserved_at_a0[0x8];
3149
	u8         srqn_xrqn[0x18];
3150

3151
	u8         reserved_at_c0[0x8];
3152 3153 3154
	u8         pd[0x18];

	u8         tclass[0x8];
3155
	u8         reserved_at_e8[0x4];
3156 3157 3158 3159
	u8         flow_label[0x14];

	u8         dc_access_key[0x40];

3160
	u8         reserved_at_140[0x5];
3161 3162 3163 3164
	u8         mtu[0x3];
	u8         port[0x8];
	u8         pkey_index[0x10];

3165
	u8         reserved_at_160[0x8];
3166
	u8         my_addr_index[0x8];
3167
	u8         reserved_at_170[0x8];
3168 3169 3170 3171
	u8         hop_limit[0x8];

	u8         dc_access_key_violation_count[0x20];

3172
	u8         reserved_at_1a0[0x14];
3173 3174 3175 3176 3177
	u8         dei_cfi[0x1];
	u8         eth_prio[0x3];
	u8         ecn[0x2];
	u8         dscp[0x6];

3178
	u8         reserved_at_1c0[0x40];
3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197
};

enum {
	MLX5_CQC_STATUS_OK             = 0x0,
	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
};

enum {
	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
};

enum {
	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
	MLX5_CQC_ST_FIRED                                 = 0xa,
};

3198 3199 3200
enum {
	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3201
	MLX5_CQ_PERIOD_NUM_MODES
3202 3203
};

3204 3205
struct mlx5_ifc_cqc_bits {
	u8         status[0x4];
3206 3207 3208
	u8         reserved_at_4[0x2];
	u8         dbr_umem_valid[0x1];
	u8         reserved_at_7[0x1];
3209 3210
	u8         cqe_sz[0x3];
	u8         cc[0x1];
3211
	u8         reserved_at_c[0x1];
3212 3213
	u8         scqe_break_moderation_en[0x1];
	u8         oi[0x1];
3214 3215
	u8         cq_period_mode[0x2];
	u8         cqe_comp_en[0x1];
3216 3217
	u8         mini_cqe_res_format[0x2];
	u8         st[0x4];
3218
	u8         reserved_at_18[0x8];
3219

3220
	u8         reserved_at_20[0x20];
3221

3222
	u8         reserved_at_40[0x14];
3223
	u8         page_offset[0x6];
3224
	u8         reserved_at_5a[0x6];
3225

3226
	u8         reserved_at_60[0x3];
3227 3228 3229
	u8         log_cq_size[0x5];
	u8         uar_page[0x18];

3230
	u8         reserved_at_80[0x4];
3231 3232 3233
	u8         cq_period[0xc];
	u8         cq_max_count[0x10];

3234
	u8         reserved_at_a0[0x18];
3235 3236
	u8         c_eqn[0x8];

3237
	u8         reserved_at_c0[0x3];
3238
	u8         log_page_size[0x5];
3239
	u8         reserved_at_c8[0x18];
3240

3241
	u8         reserved_at_e0[0x20];
3242

3243
	u8         reserved_at_100[0x8];
3244 3245
	u8         last_notified_index[0x18];

3246
	u8         reserved_at_120[0x8];
3247 3248
	u8         last_solicit_index[0x18];

3249
	u8         reserved_at_140[0x8];
3250 3251
	u8         consumer_counter[0x18];

3252
	u8         reserved_at_160[0x8];
3253 3254
	u8         producer_counter[0x18];

3255
	u8         reserved_at_180[0x40];
3256 3257 3258 3259 3260 3261 3262 3263

	u8         dbr_addr[0x40];
};

union mlx5_ifc_cong_control_roce_ecn_auto_bits {
	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3264
	u8         reserved_at_0[0x800];
3265 3266 3267
};

struct mlx5_ifc_query_adapter_param_block_bits {
3268
	u8         reserved_at_0[0xc0];
3269

3270
	u8         reserved_at_c0[0x8];
3271 3272
	u8         ieee_vendor_id[0x18];

3273
	u8         reserved_at_e0[0x10];
3274 3275 3276 3277 3278 3279 3280
	u8         vsd_vendor_id[0x10];

	u8         vsd[208][0x8];

	u8         vsd_contd_psid[16][0x8];
};

3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323
enum {
	MLX5_XRQC_STATE_GOOD   = 0x0,
	MLX5_XRQC_STATE_ERROR  = 0x1,
};

enum {
	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
};

enum {
	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
};

struct mlx5_ifc_tag_matching_topology_context_bits {
	u8         log_matching_list_sz[0x4];
	u8         reserved_at_4[0xc];
	u8         append_next_index[0x10];

	u8         sw_phase_cnt[0x10];
	u8         hw_phase_cnt[0x10];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_xrqc_bits {
	u8         state[0x4];
	u8         rlkey[0x1];
	u8         reserved_at_5[0xf];
	u8         topology[0x4];
	u8         reserved_at_18[0x4];
	u8         offload[0x4];

	u8         reserved_at_20[0x8];
	u8         user_index[0x18];

	u8         reserved_at_40[0x8];
	u8         cqn[0x18];

	u8         reserved_at_60[0xa0];

	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;

3324
	u8         reserved_at_180[0x280];
3325 3326 3327 3328

	struct mlx5_ifc_wq_bits wq;
};

3329 3330 3331
union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
	struct mlx5_ifc_modify_field_select_bits modify_field_select;
	struct mlx5_ifc_resize_field_select_bits resize_field_select;
3332
	u8         reserved_at_0[0x20];
3333 3334 3335 3336 3337 3338
};

union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3339
	u8         reserved_at_0[0x20];
3340 3341 3342 3343 3344 3345 3346 3347 3348 3349
};

union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
	struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3350
	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3351
	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3352
	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3353
	u8         reserved_at_0[0x7c0];
3354 3355
};

3356 3357 3358 3359 3360
union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
	u8         reserved_at_0[0x7c0];
};

3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373
union mlx5_ifc_event_auto_bits {
	struct mlx5_ifc_comp_event_bits comp_event;
	struct mlx5_ifc_dct_events_bits dct_events;
	struct mlx5_ifc_qp_events_bits qp_events;
	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
	struct mlx5_ifc_cq_error_bits cq_error;
	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
	struct mlx5_ifc_gpio_event_bits gpio_event;
	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3374
	u8         reserved_at_0[0xe0];
3375 3376 3377
};

struct mlx5_ifc_health_buffer_bits {
3378
	u8         reserved_at_0[0x100];
3379 3380 3381 3382 3383

	u8         assert_existptr[0x20];

	u8         assert_callra[0x20];

3384
	u8         reserved_at_140[0x40];
3385 3386 3387 3388 3389

	u8         fw_version[0x20];

	u8         hw_id[0x20];

3390
	u8         reserved_at_1c0[0x20];
3391 3392 3393 3394 3395 3396 3397 3398

	u8         irisc_index[0x8];
	u8         synd[0x8];
	u8         ext_synd[0x10];
};

struct mlx5_ifc_register_loopback_control_bits {
	u8         no_lb[0x1];
3399
	u8         reserved_at_1[0x7];
3400
	u8         port[0x8];
3401
	u8         reserved_at_10[0x10];
3402

3403
	u8         reserved_at_20[0x60];
3404 3405
};

3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428
struct mlx5_ifc_vport_tc_element_bits {
	u8         traffic_class[0x4];
	u8         reserved_at_4[0xc];
	u8         vport_number[0x10];
};

struct mlx5_ifc_vport_element_bits {
	u8         reserved_at_0[0x10];
	u8         vport_number[0x10];
};

enum {
	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
};

struct mlx5_ifc_tsar_element_bits {
	u8         reserved_at_0[0x8];
	u8         tsar_type[0x8];
	u8         reserved_at_10[0x10];
};

3429 3430 3431 3432 3433
enum {
	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
};

3434 3435
struct mlx5_ifc_teardown_hca_out_bits {
	u8         status[0x8];
3436
	u8         reserved_at_8[0x18];
3437 3438 3439

	u8         syndrome[0x20];

3440 3441
	u8         reserved_at_40[0x3f];

3442
	u8         state[0x1];
3443 3444 3445 3446
};

enum {
	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3447
	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3448
	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3449 3450 3451 3452
};

struct mlx5_ifc_teardown_hca_in_bits {
	u8         opcode[0x10];
3453
	u8         reserved_at_10[0x10];
3454

3455
	u8         reserved_at_20[0x10];
3456 3457
	u8         op_mod[0x10];

3458
	u8         reserved_at_40[0x10];
3459 3460
	u8         profile[0x10];

3461
	u8         reserved_at_60[0x20];
3462 3463 3464 3465
};

struct mlx5_ifc_sqerr2rts_qp_out_bits {
	u8         status[0x8];
3466
	u8         reserved_at_8[0x18];
3467 3468 3469

	u8         syndrome[0x20];

3470
	u8         reserved_at_40[0x40];
3471 3472 3473 3474
};

struct mlx5_ifc_sqerr2rts_qp_in_bits {
	u8         opcode[0x10];
3475
	u8         uid[0x10];
3476

3477
	u8         reserved_at_20[0x10];
3478 3479
	u8         op_mod[0x10];

3480
	u8         reserved_at_40[0x8];
3481 3482
	u8         qpn[0x18];

3483
	u8         reserved_at_60[0x20];
3484 3485 3486

	u8         opt_param_mask[0x20];

3487
	u8         reserved_at_a0[0x20];
3488 3489 3490

	struct mlx5_ifc_qpc_bits qpc;

3491
	u8         reserved_at_800[0x80];
3492 3493 3494 3495
};

struct mlx5_ifc_sqd2rts_qp_out_bits {
	u8         status[0x8];
3496
	u8         reserved_at_8[0x18];
3497 3498 3499

	u8         syndrome[0x20];

3500
	u8         reserved_at_40[0x40];
3501 3502 3503 3504
};

struct mlx5_ifc_sqd2rts_qp_in_bits {
	u8         opcode[0x10];
3505
	u8         uid[0x10];
3506

3507
	u8         reserved_at_20[0x10];
3508 3509
	u8         op_mod[0x10];

3510
	u8         reserved_at_40[0x8];
3511 3512
	u8         qpn[0x18];

3513
	u8         reserved_at_60[0x20];
3514 3515 3516

	u8         opt_param_mask[0x20];

3517
	u8         reserved_at_a0[0x20];
3518 3519 3520

	struct mlx5_ifc_qpc_bits qpc;

3521
	u8         reserved_at_800[0x80];
3522 3523 3524 3525
};

struct mlx5_ifc_set_roce_address_out_bits {
	u8         status[0x8];
3526
	u8         reserved_at_8[0x18];
3527 3528 3529

	u8         syndrome[0x20];

3530
	u8         reserved_at_40[0x40];
3531 3532 3533 3534
};

struct mlx5_ifc_set_roce_address_in_bits {
	u8         opcode[0x10];
3535
	u8         reserved_at_10[0x10];
3536

3537
	u8         reserved_at_20[0x10];
3538 3539 3540
	u8         op_mod[0x10];

	u8         roce_address_index[0x10];
3541 3542
	u8         reserved_at_50[0xc];
	u8	   vhca_port_num[0x4];
3543

3544
	u8         reserved_at_60[0x20];
3545 3546 3547 3548 3549 3550

	struct mlx5_ifc_roce_addr_layout_bits roce_address;
};

struct mlx5_ifc_set_mad_demux_out_bits {
	u8         status[0x8];
3551
	u8         reserved_at_8[0x18];
3552 3553 3554

	u8         syndrome[0x20];

3555
	u8         reserved_at_40[0x40];
3556 3557 3558 3559 3560 3561 3562 3563 3564
};

enum {
	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
};

struct mlx5_ifc_set_mad_demux_in_bits {
	u8         opcode[0x10];
3565
	u8         reserved_at_10[0x10];
3566

3567
	u8         reserved_at_20[0x10];
3568 3569
	u8         op_mod[0x10];

3570
	u8         reserved_at_40[0x20];
3571

3572
	u8         reserved_at_60[0x6];
3573
	u8         demux_mode[0x2];
3574
	u8         reserved_at_68[0x18];
3575 3576 3577 3578
};

struct mlx5_ifc_set_l2_table_entry_out_bits {
	u8         status[0x8];
3579
	u8         reserved_at_8[0x18];
3580 3581 3582

	u8         syndrome[0x20];

3583
	u8         reserved_at_40[0x40];
3584 3585 3586 3587
};

struct mlx5_ifc_set_l2_table_entry_in_bits {
	u8         opcode[0x10];
3588
	u8         reserved_at_10[0x10];
3589

3590
	u8         reserved_at_20[0x10];
3591 3592
	u8         op_mod[0x10];

3593
	u8         reserved_at_40[0x60];
3594

3595
	u8         reserved_at_a0[0x8];
3596 3597
	u8         table_index[0x18];

3598
	u8         reserved_at_c0[0x20];
3599

3600
	u8         reserved_at_e0[0x13];
3601 3602 3603 3604 3605
	u8         vlan_valid[0x1];
	u8         vlan[0xc];

	struct mlx5_ifc_mac_address_layout_bits mac_address;

3606
	u8         reserved_at_140[0xc0];
3607 3608 3609 3610
};

struct mlx5_ifc_set_issi_out_bits {
	u8         status[0x8];
3611
	u8         reserved_at_8[0x18];
3612 3613 3614

	u8         syndrome[0x20];

3615
	u8         reserved_at_40[0x40];
3616 3617 3618 3619
};

struct mlx5_ifc_set_issi_in_bits {
	u8         opcode[0x10];
3620
	u8         reserved_at_10[0x10];
3621

3622
	u8         reserved_at_20[0x10];
3623 3624
	u8         op_mod[0x10];

3625
	u8         reserved_at_40[0x10];
3626 3627
	u8         current_issi[0x10];

3628
	u8         reserved_at_60[0x20];
3629 3630 3631 3632
};

struct mlx5_ifc_set_hca_cap_out_bits {
	u8         status[0x8];
3633
	u8         reserved_at_8[0x18];
3634 3635 3636

	u8         syndrome[0x20];

3637
	u8         reserved_at_40[0x40];
3638 3639 3640 3641
};

struct mlx5_ifc_set_hca_cap_in_bits {
	u8         opcode[0x10];
3642
	u8         reserved_at_10[0x10];
3643

3644
	u8         reserved_at_20[0x10];
3645 3646
	u8         op_mod[0x10];

3647
	u8         reserved_at_40[0x40];
3648 3649 3650 3651

	union mlx5_ifc_hca_cap_union_bits capability;
};

3652 3653 3654 3655 3656 3657 3658
enum {
	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
};

3659 3660
struct mlx5_ifc_set_fte_out_bits {
	u8         status[0x8];
3661
	u8         reserved_at_8[0x18];
3662 3663 3664

	u8         syndrome[0x20];

3665
	u8         reserved_at_40[0x40];
3666 3667 3668 3669
};

struct mlx5_ifc_set_fte_in_bits {
	u8         opcode[0x10];
3670
	u8         reserved_at_10[0x10];
3671

3672
	u8         reserved_at_20[0x10];
3673 3674
	u8         op_mod[0x10];

3675 3676 3677 3678 3679
	u8         other_vport[0x1];
	u8         reserved_at_41[0xf];
	u8         vport_number[0x10];

	u8         reserved_at_60[0x20];
3680 3681

	u8         table_type[0x8];
3682
	u8         reserved_at_88[0x18];
3683

3684
	u8         reserved_at_a0[0x8];
3685 3686
	u8         table_id[0x18];

3687
	u8         reserved_at_c0[0x18];
3688 3689
	u8         modify_enable_mask[0x8];

3690
	u8         reserved_at_e0[0x20];
3691 3692 3693

	u8         flow_index[0x20];

3694
	u8         reserved_at_120[0xe0];
3695 3696 3697 3698 3699 3700

	struct mlx5_ifc_flow_context_bits flow_context;
};

struct mlx5_ifc_rts2rts_qp_out_bits {
	u8         status[0x8];
3701
	u8         reserved_at_8[0x18];
3702 3703 3704

	u8         syndrome[0x20];

3705
	u8         reserved_at_40[0x40];
3706 3707 3708 3709
};

struct mlx5_ifc_rts2rts_qp_in_bits {
	u8         opcode[0x10];
3710
	u8         uid[0x10];
3711

3712
	u8         reserved_at_20[0x10];
3713 3714
	u8         op_mod[0x10];

3715
	u8         reserved_at_40[0x8];
3716 3717
	u8         qpn[0x18];

3718
	u8         reserved_at_60[0x20];
3719 3720 3721

	u8         opt_param_mask[0x20];

3722
	u8         reserved_at_a0[0x20];
3723 3724 3725

	struct mlx5_ifc_qpc_bits qpc;

3726
	u8         reserved_at_800[0x80];
3727 3728 3729 3730
};

struct mlx5_ifc_rtr2rts_qp_out_bits {
	u8         status[0x8];
3731
	u8         reserved_at_8[0x18];
3732 3733 3734

	u8         syndrome[0x20];

3735
	u8         reserved_at_40[0x40];
3736 3737 3738 3739
};

struct mlx5_ifc_rtr2rts_qp_in_bits {
	u8         opcode[0x10];
3740
	u8         uid[0x10];
3741

3742
	u8         reserved_at_20[0x10];
3743 3744
	u8         op_mod[0x10];

3745
	u8         reserved_at_40[0x8];
3746 3747
	u8         qpn[0x18];

3748
	u8         reserved_at_60[0x20];
3749 3750 3751

	u8         opt_param_mask[0x20];

3752
	u8         reserved_at_a0[0x20];
3753 3754 3755

	struct mlx5_ifc_qpc_bits qpc;

3756
	u8         reserved_at_800[0x80];
3757 3758 3759 3760
};

struct mlx5_ifc_rst2init_qp_out_bits {
	u8         status[0x8];
3761
	u8         reserved_at_8[0x18];
3762 3763 3764

	u8         syndrome[0x20];

3765
	u8         reserved_at_40[0x40];
3766 3767 3768 3769
};

struct mlx5_ifc_rst2init_qp_in_bits {
	u8         opcode[0x10];
3770
	u8         uid[0x10];
3771

3772
	u8         reserved_at_20[0x10];
3773 3774
	u8         op_mod[0x10];

3775
	u8         reserved_at_40[0x8];
3776 3777
	u8         qpn[0x18];

3778
	u8         reserved_at_60[0x20];
3779 3780 3781

	u8         opt_param_mask[0x20];

3782
	u8         reserved_at_a0[0x20];
3783 3784 3785

	struct mlx5_ifc_qpc_bits qpc;

3786
	u8         reserved_at_800[0x80];
3787 3788
};

3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812
struct mlx5_ifc_query_xrq_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];

	struct mlx5_ifc_xrqc_bits xrq_context;
};

struct mlx5_ifc_query_xrq_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x8];
	u8         xrqn[0x18];

	u8         reserved_at_60[0x20];
};

3813 3814
struct mlx5_ifc_query_xrc_srq_out_bits {
	u8         status[0x8];
3815
	u8         reserved_at_8[0x18];
3816 3817 3818

	u8         syndrome[0x20];

3819
	u8         reserved_at_40[0x40];
3820 3821 3822

	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;

3823
	u8         reserved_at_280[0x600];
3824 3825 3826 3827 3828 3829

	u8         pas[0][0x40];
};

struct mlx5_ifc_query_xrc_srq_in_bits {
	u8         opcode[0x10];
3830
	u8         reserved_at_10[0x10];
3831

3832
	u8         reserved_at_20[0x10];
3833 3834
	u8         op_mod[0x10];

3835
	u8         reserved_at_40[0x8];
3836 3837
	u8         xrc_srqn[0x18];

3838
	u8         reserved_at_60[0x20];
3839 3840 3841 3842 3843 3844 3845 3846 3847
};

enum {
	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
};

struct mlx5_ifc_query_vport_state_out_bits {
	u8         status[0x8];
3848
	u8         reserved_at_8[0x18];
3849 3850 3851

	u8         syndrome[0x20];

3852
	u8         reserved_at_40[0x20];
3853

3854
	u8         reserved_at_60[0x18];
3855 3856 3857 3858 3859
	u8         admin_state[0x4];
	u8         state[0x4];
};

enum {
3860 3861
	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
3862 3863
};

3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890
struct mlx5_ifc_arm_monitor_counter_in_bits {
	u8         opcode[0x10];
	u8         uid[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x20];

	u8         reserved_at_60[0x20];
};

struct mlx5_ifc_arm_monitor_counter_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

enum {
	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
};

enum mlx5_monitor_counter_ppcnt {
3891 3892 3893 3894 3895 3896
	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
3897 3898 3899
};

enum {
3900
	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940
};

struct mlx5_ifc_monitor_counter_output_bits {
	u8         reserved_at_0[0x4];
	u8         type[0x4];
	u8         reserved_at_8[0x8];
	u8         counter[0x10];

	u8         counter_group_id[0x20];
};

#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)

struct mlx5_ifc_set_monitor_counter_in_bits {
	u8         opcode[0x10];
	u8         uid[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x10];
	u8         num_of_counters[0x10];

	u8         reserved_at_60[0x20];

	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
};

struct mlx5_ifc_set_monitor_counter_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

3941 3942
struct mlx5_ifc_query_vport_state_in_bits {
	u8         opcode[0x10];
3943
	u8         reserved_at_10[0x10];
3944

3945
	u8         reserved_at_20[0x10];
3946 3947 3948
	u8         op_mod[0x10];

	u8         other_vport[0x1];
3949
	u8         reserved_at_41[0xf];
3950 3951
	u8         vport_number[0x10];

3952
	u8         reserved_at_60[0x20];
3953 3954
};

3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983
struct mlx5_ifc_query_vnic_env_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];

	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
};

enum {
	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
};

struct mlx5_ifc_query_vnic_env_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         other_vport[0x1];
	u8         reserved_at_41[0xf];
	u8         vport_number[0x10];

	u8         reserved_at_60[0x20];
};

3984 3985
struct mlx5_ifc_query_vport_counter_out_bits {
	u8         status[0x8];
3986
	u8         reserved_at_8[0x18];
3987 3988 3989

	u8         syndrome[0x20];

3990
	u8         reserved_at_40[0x40];
3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015

	struct mlx5_ifc_traffic_counter_bits received_errors;

	struct mlx5_ifc_traffic_counter_bits transmit_errors;

	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;

	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;

	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;

	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;

	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;

	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;

	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;

	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;

	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;

	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;

4016
	u8         reserved_at_680[0xa00];
4017 4018 4019 4020 4021 4022 4023 4024
};

enum {
	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
};

struct mlx5_ifc_query_vport_counter_in_bits {
	u8         opcode[0x10];
4025
	u8         reserved_at_10[0x10];
4026

4027
	u8         reserved_at_20[0x10];
4028 4029 4030
	u8         op_mod[0x10];

	u8         other_vport[0x1];
4031 4032
	u8         reserved_at_41[0xb];
	u8	   port_num[0x4];
4033 4034
	u8         vport_number[0x10];

4035
	u8         reserved_at_60[0x60];
4036 4037

	u8         clear[0x1];
4038
	u8         reserved_at_c1[0x1f];
4039

4040
	u8         reserved_at_e0[0x20];
4041 4042 4043 4044
};

struct mlx5_ifc_query_tis_out_bits {
	u8         status[0x8];
4045
	u8         reserved_at_8[0x18];
4046 4047 4048

	u8         syndrome[0x20];

4049
	u8         reserved_at_40[0x40];
4050 4051 4052 4053 4054 4055

	struct mlx5_ifc_tisc_bits tis_context;
};

struct mlx5_ifc_query_tis_in_bits {
	u8         opcode[0x10];
4056
	u8         reserved_at_10[0x10];
4057

4058
	u8         reserved_at_20[0x10];
4059 4060
	u8         op_mod[0x10];

4061
	u8         reserved_at_40[0x8];
4062 4063
	u8         tisn[0x18];

4064
	u8         reserved_at_60[0x20];
4065 4066 4067 4068
};

struct mlx5_ifc_query_tir_out_bits {
	u8         status[0x8];
4069
	u8         reserved_at_8[0x18];
4070 4071 4072

	u8         syndrome[0x20];

4073
	u8         reserved_at_40[0xc0];
4074 4075 4076 4077 4078 4079

	struct mlx5_ifc_tirc_bits tir_context;
};

struct mlx5_ifc_query_tir_in_bits {
	u8         opcode[0x10];
4080
	u8         reserved_at_10[0x10];
4081

4082
	u8         reserved_at_20[0x10];
4083 4084
	u8         op_mod[0x10];

4085
	u8         reserved_at_40[0x8];
4086 4087
	u8         tirn[0x18];

4088
	u8         reserved_at_60[0x20];
4089 4090 4091 4092
};

struct mlx5_ifc_query_srq_out_bits {
	u8         status[0x8];
4093
	u8         reserved_at_8[0x18];
4094 4095 4096

	u8         syndrome[0x20];

4097
	u8         reserved_at_40[0x40];
4098 4099 4100

	struct mlx5_ifc_srqc_bits srq_context_entry;

4101
	u8         reserved_at_280[0x600];
4102 4103 4104 4105 4106 4107

	u8         pas[0][0x40];
};

struct mlx5_ifc_query_srq_in_bits {
	u8         opcode[0x10];
4108
	u8         reserved_at_10[0x10];
4109

4110
	u8         reserved_at_20[0x10];
4111 4112
	u8         op_mod[0x10];

4113
	u8         reserved_at_40[0x8];
4114 4115
	u8         srqn[0x18];

4116
	u8         reserved_at_60[0x20];
4117 4118 4119 4120
};

struct mlx5_ifc_query_sq_out_bits {
	u8         status[0x8];
4121
	u8         reserved_at_8[0x18];
4122 4123 4124

	u8         syndrome[0x20];

4125
	u8         reserved_at_40[0xc0];
4126 4127 4128 4129 4130 4131

	struct mlx5_ifc_sqc_bits sq_context;
};

struct mlx5_ifc_query_sq_in_bits {
	u8         opcode[0x10];
4132
	u8         reserved_at_10[0x10];
4133

4134
	u8         reserved_at_20[0x10];
4135 4136
	u8         op_mod[0x10];

4137
	u8         reserved_at_40[0x8];
4138 4139
	u8         sqn[0x18];

4140
	u8         reserved_at_60[0x20];
4141 4142 4143 4144
};

struct mlx5_ifc_query_special_contexts_out_bits {
	u8         status[0x8];
4145
	u8         reserved_at_8[0x18];
4146 4147 4148

	u8         syndrome[0x20];

4149
	u8         dump_fill_mkey[0x20];
4150 4151

	u8         resd_lkey[0x20];
4152 4153 4154 4155

	u8         null_mkey[0x20];

	u8         reserved_at_a0[0x60];
4156 4157 4158 4159
};

struct mlx5_ifc_query_special_contexts_in_bits {
	u8         opcode[0x10];
4160
	u8         reserved_at_10[0x10];
4161

4162
	u8         reserved_at_20[0x10];
4163 4164
	u8         op_mod[0x10];

4165
	u8         reserved_at_40[0x40];
4166 4167
};

4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200
struct mlx5_ifc_query_scheduling_element_out_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0xc0];

	struct mlx5_ifc_scheduling_context_bits scheduling_context;

	u8         reserved_at_300[0x100];
};

enum {
	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
};

struct mlx5_ifc_query_scheduling_element_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         scheduling_hierarchy[0x8];
	u8         reserved_at_48[0x18];

	u8         scheduling_element_id[0x20];

	u8         reserved_at_80[0x180];
};

4201 4202
struct mlx5_ifc_query_rqt_out_bits {
	u8         status[0x8];
4203
	u8         reserved_at_8[0x18];
4204 4205 4206

	u8         syndrome[0x20];

4207
	u8         reserved_at_40[0xc0];
4208 4209 4210 4211 4212 4213

	struct mlx5_ifc_rqtc_bits rqt_context;
};

struct mlx5_ifc_query_rqt_in_bits {
	u8         opcode[0x10];
4214
	u8         reserved_at_10[0x10];
4215

4216
	u8         reserved_at_20[0x10];
4217 4218
	u8         op_mod[0x10];

4219
	u8         reserved_at_40[0x8];
4220 4221
	u8         rqtn[0x18];

4222
	u8         reserved_at_60[0x20];
4223 4224 4225 4226
};

struct mlx5_ifc_query_rq_out_bits {
	u8         status[0x8];
4227
	u8         reserved_at_8[0x18];
4228 4229 4230

	u8         syndrome[0x20];

4231
	u8         reserved_at_40[0xc0];
4232 4233 4234 4235 4236 4237

	struct mlx5_ifc_rqc_bits rq_context;
};

struct mlx5_ifc_query_rq_in_bits {
	u8         opcode[0x10];
4238
	u8         reserved_at_10[0x10];
4239

4240
	u8         reserved_at_20[0x10];
4241 4242
	u8         op_mod[0x10];

4243
	u8         reserved_at_40[0x8];
4244 4245
	u8         rqn[0x18];

4246
	u8         reserved_at_60[0x20];
4247 4248 4249 4250
};

struct mlx5_ifc_query_roce_address_out_bits {
	u8         status[0x8];
4251
	u8         reserved_at_8[0x18];
4252 4253 4254

	u8         syndrome[0x20];

4255
	u8         reserved_at_40[0x40];
4256 4257 4258 4259 4260 4261

	struct mlx5_ifc_roce_addr_layout_bits roce_address;
};

struct mlx5_ifc_query_roce_address_in_bits {
	u8         opcode[0x10];
4262
	u8         reserved_at_10[0x10];
4263

4264
	u8         reserved_at_20[0x10];
4265 4266 4267
	u8         op_mod[0x10];

	u8         roce_address_index[0x10];
4268 4269
	u8         reserved_at_50[0xc];
	u8	   vhca_port_num[0x4];
4270

4271
	u8         reserved_at_60[0x20];
4272 4273 4274 4275
};

struct mlx5_ifc_query_rmp_out_bits {
	u8         status[0x8];
4276
	u8         reserved_at_8[0x18];
4277 4278 4279

	u8         syndrome[0x20];

4280
	u8         reserved_at_40[0xc0];
4281 4282 4283 4284 4285 4286

	struct mlx5_ifc_rmpc_bits rmp_context;
};

struct mlx5_ifc_query_rmp_in_bits {
	u8         opcode[0x10];
4287
	u8         reserved_at_10[0x10];
4288

4289
	u8         reserved_at_20[0x10];
4290 4291
	u8         op_mod[0x10];

4292
	u8         reserved_at_40[0x8];
4293 4294
	u8         rmpn[0x18];

4295
	u8         reserved_at_60[0x20];
4296 4297 4298 4299
};

struct mlx5_ifc_query_qp_out_bits {
	u8         status[0x8];
4300
	u8         reserved_at_8[0x18];
4301 4302 4303

	u8         syndrome[0x20];

4304
	u8         reserved_at_40[0x40];
4305 4306 4307

	u8         opt_param_mask[0x20];

4308
	u8         reserved_at_a0[0x20];
4309 4310 4311

	struct mlx5_ifc_qpc_bits qpc;

4312
	u8         reserved_at_800[0x80];
4313 4314 4315 4316 4317 4318

	u8         pas[0][0x40];
};

struct mlx5_ifc_query_qp_in_bits {
	u8         opcode[0x10];
4319
	u8         reserved_at_10[0x10];
4320

4321
	u8         reserved_at_20[0x10];
4322 4323
	u8         op_mod[0x10];

4324
	u8         reserved_at_40[0x8];
4325 4326
	u8         qpn[0x18];

4327
	u8         reserved_at_60[0x20];
4328 4329 4330 4331
};

struct mlx5_ifc_query_q_counter_out_bits {
	u8         status[0x8];
4332
	u8         reserved_at_8[0x18];
4333 4334 4335

	u8         syndrome[0x20];

4336
	u8         reserved_at_40[0x40];
4337 4338 4339

	u8         rx_write_requests[0x20];

4340
	u8         reserved_at_a0[0x20];
4341 4342 4343

	u8         rx_read_requests[0x20];

4344
	u8         reserved_at_e0[0x20];
4345 4346 4347

	u8         rx_atomic_requests[0x20];

4348
	u8         reserved_at_120[0x20];
4349 4350 4351

	u8         rx_dct_connect[0x20];

4352
	u8         reserved_at_160[0x20];
4353 4354 4355

	u8         out_of_buffer[0x20];

4356
	u8         reserved_at_1a0[0x20];
4357 4358 4359

	u8         out_of_sequence[0x20];

4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379
	u8         reserved_at_1e0[0x20];

	u8         duplicate_request[0x20];

	u8         reserved_at_220[0x20];

	u8         rnr_nak_retry_err[0x20];

	u8         reserved_at_260[0x20];

	u8         packet_seq_err[0x20];

	u8         reserved_at_2a0[0x20];

	u8         implied_nak_seq_err[0x20];

	u8         reserved_at_2e0[0x20];

	u8         local_ack_timeout_err[0x20];

4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420
	u8         reserved_at_320[0xa0];

	u8         resp_local_length_error[0x20];

	u8         req_local_length_error[0x20];

	u8         resp_local_qp_error[0x20];

	u8         local_operation_error[0x20];

	u8         resp_local_protection[0x20];

	u8         req_local_protection[0x20];

	u8         resp_cqe_error[0x20];

	u8         req_cqe_error[0x20];

	u8         req_mw_binding[0x20];

	u8         req_bad_response[0x20];

	u8         req_remote_invalid_request[0x20];

	u8         resp_remote_invalid_request[0x20];

	u8         req_remote_access_errors[0x20];

	u8	   resp_remote_access_errors[0x20];

	u8         req_remote_operation_errors[0x20];

	u8         req_transport_retries_exceeded[0x20];

	u8         cq_overflow[0x20];

	u8         resp_cqe_flush_error[0x20];

	u8         req_cqe_flush_error[0x20];

	u8         reserved_at_620[0x1e0];
4421 4422 4423 4424
};

struct mlx5_ifc_query_q_counter_in_bits {
	u8         opcode[0x10];
4425
	u8         reserved_at_10[0x10];
4426

4427
	u8         reserved_at_20[0x10];
4428 4429
	u8         op_mod[0x10];

4430
	u8         reserved_at_40[0x80];
4431 4432

	u8         clear[0x1];
4433
	u8         reserved_at_c1[0x1f];
4434

4435
	u8         reserved_at_e0[0x18];
4436 4437 4438 4439 4440
	u8         counter_set_id[0x8];
};

struct mlx5_ifc_query_pages_out_bits {
	u8         status[0x8];
4441
	u8         reserved_at_8[0x18];
4442 4443 4444

	u8         syndrome[0x20];

4445 4446
	u8         embedded_cpu_function[0x1];
	u8         reserved_at_41[0xf];
4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459
	u8         function_id[0x10];

	u8         num_pages[0x20];
};

enum {
	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
};

struct mlx5_ifc_query_pages_in_bits {
	u8         opcode[0x10];
4460
	u8         reserved_at_10[0x10];
4461

4462
	u8         reserved_at_20[0x10];
4463 4464
	u8         op_mod[0x10];

4465 4466
	u8         embedded_cpu_function[0x1];
	u8         reserved_at_41[0xf];
4467 4468
	u8         function_id[0x10];

4469
	u8         reserved_at_60[0x20];
4470 4471 4472 4473
};

struct mlx5_ifc_query_nic_vport_context_out_bits {
	u8         status[0x8];
4474
	u8         reserved_at_8[0x18];
4475 4476 4477

	u8         syndrome[0x20];

4478
	u8         reserved_at_40[0x40];
4479 4480 4481 4482 4483 4484

	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
};

struct mlx5_ifc_query_nic_vport_context_in_bits {
	u8         opcode[0x10];
4485
	u8         reserved_at_10[0x10];
4486

4487
	u8         reserved_at_20[0x10];
4488 4489 4490
	u8         op_mod[0x10];

	u8         other_vport[0x1];
4491
	u8         reserved_at_41[0xf];
4492 4493
	u8         vport_number[0x10];

4494
	u8         reserved_at_60[0x5];
4495
	u8         allowed_list_type[0x3];
4496
	u8         reserved_at_68[0x18];
4497 4498 4499 4500
};

struct mlx5_ifc_query_mkey_out_bits {
	u8         status[0x8];
4501
	u8         reserved_at_8[0x18];
4502 4503 4504

	u8         syndrome[0x20];

4505
	u8         reserved_at_40[0x40];
4506 4507 4508

	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;

4509
	u8         reserved_at_280[0x600];
4510 4511 4512 4513 4514 4515 4516 4517

	u8         bsf0_klm0_pas_mtt0_1[16][0x8];

	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
};

struct mlx5_ifc_query_mkey_in_bits {
	u8         opcode[0x10];
4518
	u8         reserved_at_10[0x10];
4519

4520
	u8         reserved_at_20[0x10];
4521 4522
	u8         op_mod[0x10];

4523
	u8         reserved_at_40[0x8];
4524 4525 4526
	u8         mkey_index[0x18];

	u8         pg_access[0x1];
4527
	u8         reserved_at_61[0x1f];
4528 4529 4530 4531
};

struct mlx5_ifc_query_mad_demux_out_bits {
	u8         status[0x8];
4532
	u8         reserved_at_8[0x18];
4533 4534 4535

	u8         syndrome[0x20];

4536
	u8         reserved_at_40[0x40];
4537 4538 4539 4540 4541 4542

	u8         mad_dumux_parameters_block[0x20];
};

struct mlx5_ifc_query_mad_demux_in_bits {
	u8         opcode[0x10];
4543
	u8         reserved_at_10[0x10];
4544

4545
	u8         reserved_at_20[0x10];
4546 4547
	u8         op_mod[0x10];

4548
	u8         reserved_at_40[0x40];
4549 4550 4551 4552
};

struct mlx5_ifc_query_l2_table_entry_out_bits {
	u8         status[0x8];
4553
	u8         reserved_at_8[0x18];
4554 4555 4556

	u8         syndrome[0x20];

4557
	u8         reserved_at_40[0xa0];
4558

4559
	u8         reserved_at_e0[0x13];
4560 4561 4562 4563 4564
	u8         vlan_valid[0x1];
	u8         vlan[0xc];

	struct mlx5_ifc_mac_address_layout_bits mac_address;

4565
	u8         reserved_at_140[0xc0];
4566 4567 4568 4569
};

struct mlx5_ifc_query_l2_table_entry_in_bits {
	u8         opcode[0x10];
4570
	u8         reserved_at_10[0x10];
4571

4572
	u8         reserved_at_20[0x10];
4573 4574
	u8         op_mod[0x10];

4575
	u8         reserved_at_40[0x60];
4576

4577
	u8         reserved_at_a0[0x8];
4578 4579
	u8         table_index[0x18];

4580
	u8         reserved_at_c0[0x140];
4581 4582 4583 4584
};

struct mlx5_ifc_query_issi_out_bits {
	u8         status[0x8];
4585
	u8         reserved_at_8[0x18];
4586 4587 4588

	u8         syndrome[0x20];

4589
	u8         reserved_at_40[0x10];
4590 4591
	u8         current_issi[0x10];

4592
	u8         reserved_at_60[0xa0];
4593

4594
	u8         reserved_at_100[76][0x8];
4595 4596 4597 4598 4599
	u8         supported_issi_dw0[0x20];
};

struct mlx5_ifc_query_issi_in_bits {
	u8         opcode[0x10];
4600
	u8         reserved_at_10[0x10];
4601

4602
	u8         reserved_at_20[0x10];
4603 4604
	u8         op_mod[0x10];

4605
	u8         reserved_at_40[0x40];
4606 4607
};

4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626
struct mlx5_ifc_set_driver_version_out_bits {
	u8         status[0x8];
	u8         reserved_0[0x18];

	u8         syndrome[0x20];
	u8         reserved_1[0x40];
};

struct mlx5_ifc_set_driver_version_in_bits {
	u8         opcode[0x10];
	u8         reserved_0[0x10];

	u8         reserved_1[0x10];
	u8         op_mod[0x10];

	u8         reserved_2[0x40];
	u8         driver_version[64][0x8];
};

4627 4628
struct mlx5_ifc_query_hca_vport_pkey_out_bits {
	u8         status[0x8];
4629
	u8         reserved_at_8[0x18];
4630 4631 4632

	u8         syndrome[0x20];

4633
	u8         reserved_at_40[0x40];
4634 4635 4636 4637 4638 4639

	struct mlx5_ifc_pkey_bits pkey[0];
};

struct mlx5_ifc_query_hca_vport_pkey_in_bits {
	u8         opcode[0x10];
4640
	u8         reserved_at_10[0x10];
4641

4642
	u8         reserved_at_20[0x10];
4643 4644 4645
	u8         op_mod[0x10];

	u8         other_vport[0x1];
4646
	u8         reserved_at_41[0xb];
4647
	u8         port_num[0x4];
4648 4649
	u8         vport_number[0x10];

4650
	u8         reserved_at_60[0x10];
4651 4652 4653
	u8         pkey_index[0x10];
};

4654 4655 4656 4657 4658 4659
enum {
	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
};

4660 4661
struct mlx5_ifc_query_hca_vport_gid_out_bits {
	u8         status[0x8];
4662
	u8         reserved_at_8[0x18];
4663 4664 4665

	u8         syndrome[0x20];

4666
	u8         reserved_at_40[0x20];
4667 4668

	u8         gids_num[0x10];
4669
	u8         reserved_at_70[0x10];
4670 4671 4672 4673 4674 4675

	struct mlx5_ifc_array128_auto_bits gid[0];
};

struct mlx5_ifc_query_hca_vport_gid_in_bits {
	u8         opcode[0x10];
4676
	u8         reserved_at_10[0x10];
4677

4678
	u8         reserved_at_20[0x10];
4679 4680 4681
	u8         op_mod[0x10];

	u8         other_vport[0x1];
4682
	u8         reserved_at_41[0xb];
4683
	u8         port_num[0x4];
4684 4685
	u8         vport_number[0x10];

4686
	u8         reserved_at_60[0x10];
4687 4688 4689 4690 4691
	u8         gid_index[0x10];
};

struct mlx5_ifc_query_hca_vport_context_out_bits {
	u8         status[0x8];
4692
	u8         reserved_at_8[0x18];
4693 4694 4695

	u8         syndrome[0x20];

4696
	u8         reserved_at_40[0x40];
4697 4698 4699 4700 4701 4702

	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
};

struct mlx5_ifc_query_hca_vport_context_in_bits {
	u8         opcode[0x10];
4703
	u8         reserved_at_10[0x10];
4704

4705
	u8         reserved_at_20[0x10];
4706 4707 4708
	u8         op_mod[0x10];

	u8         other_vport[0x1];
4709
	u8         reserved_at_41[0xb];
4710
	u8         port_num[0x4];
4711 4712
	u8         vport_number[0x10];

4713
	u8         reserved_at_60[0x20];
4714 4715 4716 4717
};

struct mlx5_ifc_query_hca_cap_out_bits {
	u8         status[0x8];
4718
	u8         reserved_at_8[0x18];
4719 4720 4721

	u8         syndrome[0x20];

4722
	u8         reserved_at_40[0x40];
4723 4724 4725 4726 4727 4728

	union mlx5_ifc_hca_cap_union_bits capability;
};

struct mlx5_ifc_query_hca_cap_in_bits {
	u8         opcode[0x10];
4729
	u8         reserved_at_10[0x10];
4730

4731
	u8         reserved_at_20[0x10];
4732 4733
	u8         op_mod[0x10];

4734
	u8         reserved_at_40[0x40];
4735 4736 4737 4738
};

struct mlx5_ifc_query_flow_table_out_bits {
	u8         status[0x8];
4739
	u8         reserved_at_8[0x18];
4740 4741 4742

	u8         syndrome[0x20];

4743
	u8         reserved_at_40[0x80];
4744

4745
	u8         reserved_at_c0[0x8];
4746
	u8         level[0x8];
4747
	u8         reserved_at_d0[0x8];
4748 4749
	u8         log_size[0x8];

4750
	u8         reserved_at_e0[0x120];
4751 4752 4753 4754
};

struct mlx5_ifc_query_flow_table_in_bits {
	u8         opcode[0x10];
4755
	u8         reserved_at_10[0x10];
4756

4757
	u8         reserved_at_20[0x10];
4758 4759
	u8         op_mod[0x10];

4760
	u8         reserved_at_40[0x40];
4761 4762

	u8         table_type[0x8];
4763
	u8         reserved_at_88[0x18];
4764

4765
	u8         reserved_at_a0[0x8];
4766 4767
	u8         table_id[0x18];

4768
	u8         reserved_at_c0[0x140];
4769 4770 4771 4772
};

struct mlx5_ifc_query_fte_out_bits {
	u8         status[0x8];
4773
	u8         reserved_at_8[0x18];
4774 4775 4776

	u8         syndrome[0x20];

4777
	u8         reserved_at_40[0x1c0];
4778 4779 4780 4781 4782 4783

	struct mlx5_ifc_flow_context_bits flow_context;
};

struct mlx5_ifc_query_fte_in_bits {
	u8         opcode[0x10];
4784
	u8         reserved_at_10[0x10];
4785

4786
	u8         reserved_at_20[0x10];
4787 4788
	u8         op_mod[0x10];

4789
	u8         reserved_at_40[0x40];
4790 4791

	u8         table_type[0x8];
4792
	u8         reserved_at_88[0x18];
4793

4794
	u8         reserved_at_a0[0x8];
4795 4796
	u8         table_id[0x18];

4797
	u8         reserved_at_c0[0x40];
4798 4799 4800

	u8         flow_index[0x20];

4801
	u8         reserved_at_120[0xe0];
4802 4803 4804 4805 4806 4807
};

enum {
	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4808
	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
4809 4810 4811 4812
};

struct mlx5_ifc_query_flow_group_out_bits {
	u8         status[0x8];
4813
	u8         reserved_at_8[0x18];
4814 4815 4816

	u8         syndrome[0x20];

4817
	u8         reserved_at_40[0xa0];
4818 4819 4820

	u8         start_flow_index[0x20];

4821
	u8         reserved_at_100[0x20];
4822 4823 4824

	u8         end_flow_index[0x20];

4825
	u8         reserved_at_140[0xa0];
4826

4827
	u8         reserved_at_1e0[0x18];
4828 4829 4830 4831
	u8         match_criteria_enable[0x8];

	struct mlx5_ifc_fte_match_param_bits match_criteria;

4832
	u8         reserved_at_1200[0xe00];
4833 4834 4835 4836
};

struct mlx5_ifc_query_flow_group_in_bits {
	u8         opcode[0x10];
4837
	u8         reserved_at_10[0x10];
4838

4839
	u8         reserved_at_20[0x10];
4840 4841
	u8         op_mod[0x10];

4842
	u8         reserved_at_40[0x40];
4843 4844

	u8         table_type[0x8];
4845
	u8         reserved_at_88[0x18];
4846

4847
	u8         reserved_at_a0[0x8];
4848 4849 4850 4851
	u8         table_id[0x18];

	u8         group_id[0x20];

4852
	u8         reserved_at_e0[0x120];
4853 4854
};

4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878
struct mlx5_ifc_query_flow_counter_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];

	struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
};

struct mlx5_ifc_query_flow_counter_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x80];

	u8         clear[0x1];
	u8         reserved_at_c1[0xf];
	u8         num_of_counters[0x10];

4879
	u8         flow_counter_id[0x20];
4880 4881
};

4882 4883
struct mlx5_ifc_query_esw_vport_context_out_bits {
	u8         status[0x8];
4884
	u8         reserved_at_8[0x18];
4885 4886 4887

	u8         syndrome[0x20];

4888
	u8         reserved_at_40[0x40];
4889 4890 4891 4892 4893 4894

	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
};

struct mlx5_ifc_query_esw_vport_context_in_bits {
	u8         opcode[0x10];
4895
	u8         reserved_at_10[0x10];
4896

4897
	u8         reserved_at_20[0x10];
4898 4899 4900
	u8         op_mod[0x10];

	u8         other_vport[0x1];
4901
	u8         reserved_at_41[0xf];
4902 4903
	u8         vport_number[0x10];

4904
	u8         reserved_at_60[0x20];
4905 4906 4907 4908
};

struct mlx5_ifc_modify_esw_vport_context_out_bits {
	u8         status[0x8];
4909
	u8         reserved_at_8[0x18];
4910 4911 4912

	u8         syndrome[0x20];

4913
	u8         reserved_at_40[0x40];
4914 4915 4916
};

struct mlx5_ifc_esw_vport_context_fields_select_bits {
4917
	u8         reserved_at_0[0x1c];
4918 4919 4920 4921 4922 4923 4924 4925
	u8         vport_cvlan_insert[0x1];
	u8         vport_svlan_insert[0x1];
	u8         vport_cvlan_strip[0x1];
	u8         vport_svlan_strip[0x1];
};

struct mlx5_ifc_modify_esw_vport_context_in_bits {
	u8         opcode[0x10];
4926
	u8         reserved_at_10[0x10];
4927

4928
	u8         reserved_at_20[0x10];
4929 4930 4931
	u8         op_mod[0x10];

	u8         other_vport[0x1];
4932
	u8         reserved_at_41[0xf];
4933 4934 4935 4936 4937 4938 4939
	u8         vport_number[0x10];

	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;

	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
};

4940 4941
struct mlx5_ifc_query_eq_out_bits {
	u8         status[0x8];
4942
	u8         reserved_at_8[0x18];
4943 4944 4945

	u8         syndrome[0x20];

4946
	u8         reserved_at_40[0x40];
4947 4948 4949

	struct mlx5_ifc_eqc_bits eq_context_entry;

4950
	u8         reserved_at_280[0x40];
4951 4952 4953

	u8         event_bitmask[0x40];

4954
	u8         reserved_at_300[0x580];
4955 4956 4957 4958 4959 4960

	u8         pas[0][0x40];
};

struct mlx5_ifc_query_eq_in_bits {
	u8         opcode[0x10];
4961
	u8         reserved_at_10[0x10];
4962

4963
	u8         reserved_at_20[0x10];
4964 4965
	u8         op_mod[0x10];

4966
	u8         reserved_at_40[0x18];
4967 4968
	u8         eq_number[0x8];

4969
	u8         reserved_at_60[0x20];
4970 4971
};

4972
struct mlx5_ifc_packet_reformat_context_in_bits {
4973
	u8         reserved_at_0[0x5];
4974
	u8         reformat_type[0x3];
4975
	u8         reserved_at_8[0xe];
4976
	u8         reformat_data_size[0xa];
4977 4978

	u8         reserved_at_20[0x10];
4979
	u8         reformat_data[2][0x8];
4980

4981
	u8         more_reformat_data[0][0x8];
4982 4983
};

4984
struct mlx5_ifc_query_packet_reformat_context_out_bits {
4985 4986 4987 4988 4989 4990 4991
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0xa0];

4992
	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
4993 4994
};

4995
struct mlx5_ifc_query_packet_reformat_context_in_bits {
4996 4997 4998 4999 5000 5001
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

5002
	u8         packet_reformat_id[0x20];
5003 5004 5005 5006

	u8         reserved_at_60[0xa0];
};

5007
struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5008 5009 5010 5011 5012
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

5013
	u8         packet_reformat_id[0x20];
5014 5015 5016 5017

	u8         reserved_at_60[0x20];
};

5018
enum {
5019 5020
	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5021 5022 5023
	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5024 5025
};

5026
struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5027 5028 5029 5030 5031 5032 5033 5034
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0xa0];

5035
	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5036 5037
};

5038
struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5039 5040 5041 5042 5043 5044 5045 5046
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

5047
struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5048 5049 5050 5051 5052 5053
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_20[0x10];
	u8         op_mod[0x10];

5054
	u8         packet_reformat_id[0x20];
5055 5056 5057 5058

	u8         reserved_60[0x20];
};

5059 5060 5061 5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111
struct mlx5_ifc_set_action_in_bits {
	u8         action_type[0x4];
	u8         field[0xc];
	u8         reserved_at_10[0x3];
	u8         offset[0x5];
	u8         reserved_at_18[0x3];
	u8         length[0x5];

	u8         data[0x20];
};

struct mlx5_ifc_add_action_in_bits {
	u8         action_type[0x4];
	u8         field[0xc];
	u8         reserved_at_10[0x10];

	u8         data[0x20];
};

union mlx5_ifc_set_action_in_add_action_in_auto_bits {
	struct mlx5_ifc_set_action_in_bits set_action_in;
	struct mlx5_ifc_add_action_in_bits add_action_in;
	u8         reserved_at_0[0x40];
};

enum {
	MLX5_ACTION_TYPE_SET   = 0x1,
	MLX5_ACTION_TYPE_ADD   = 0x2,
};

enum {
	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5112
	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5113 5114 5115 5116 5117 5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145 5146 5147 5148 5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160 5161 5162
};

struct mlx5_ifc_alloc_modify_header_context_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         modify_header_id[0x20];

	u8         reserved_at_60[0x20];
};

struct mlx5_ifc_alloc_modify_header_context_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x20];

	u8         table_type[0x8];
	u8         reserved_at_68[0x10];
	u8         num_of_actions[0x8];

	union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
};

struct mlx5_ifc_dealloc_modify_header_context_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_dealloc_modify_header_context_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         modify_header_id[0x20];

	u8         reserved_at_60[0x20];
};

5163 5164
struct mlx5_ifc_query_dct_out_bits {
	u8         status[0x8];
5165
	u8         reserved_at_8[0x18];
5166 5167 5168

	u8         syndrome[0x20];

5169
	u8         reserved_at_40[0x40];
5170 5171 5172

	struct mlx5_ifc_dctc_bits dct_context_entry;

5173
	u8         reserved_at_280[0x180];
5174 5175 5176 5177
};

struct mlx5_ifc_query_dct_in_bits {
	u8         opcode[0x10];
5178
	u8         reserved_at_10[0x10];
5179

5180
	u8         reserved_at_20[0x10];
5181 5182
	u8         op_mod[0x10];

5183
	u8         reserved_at_40[0x8];
5184 5185
	u8         dctn[0x18];

5186
	u8         reserved_at_60[0x20];
5187 5188 5189 5190
};

struct mlx5_ifc_query_cq_out_bits {
	u8         status[0x8];
5191
	u8         reserved_at_8[0x18];
5192 5193 5194

	u8         syndrome[0x20];

5195
	u8         reserved_at_40[0x40];
5196 5197 5198

	struct mlx5_ifc_cqc_bits cq_context;

5199
	u8         reserved_at_280[0x600];
5200 5201 5202 5203 5204 5205

	u8         pas[0][0x40];
};

struct mlx5_ifc_query_cq_in_bits {
	u8         opcode[0x10];
5206
	u8         reserved_at_10[0x10];
5207

5208
	u8         reserved_at_20[0x10];
5209 5210
	u8         op_mod[0x10];

5211
	u8         reserved_at_40[0x8];
5212 5213
	u8         cqn[0x18];

5214
	u8         reserved_at_60[0x20];
5215 5216 5217 5218
};

struct mlx5_ifc_query_cong_status_out_bits {
	u8         status[0x8];
5219
	u8         reserved_at_8[0x18];
5220 5221 5222

	u8         syndrome[0x20];

5223
	u8         reserved_at_40[0x20];
5224 5225 5226

	u8         enable[0x1];
	u8         tag_enable[0x1];
5227
	u8         reserved_at_62[0x1e];
5228 5229 5230 5231
};

struct mlx5_ifc_query_cong_status_in_bits {
	u8         opcode[0x10];
5232
	u8         reserved_at_10[0x10];
5233

5234
	u8         reserved_at_20[0x10];
5235 5236
	u8         op_mod[0x10];

5237
	u8         reserved_at_40[0x18];
5238 5239 5240
	u8         priority[0x4];
	u8         cong_protocol[0x4];

5241
	u8         reserved_at_60[0x20];
5242 5243 5244 5245
};

struct mlx5_ifc_query_cong_statistics_out_bits {
	u8         status[0x8];
5246
	u8         reserved_at_8[0x18];
5247 5248 5249

	u8         syndrome[0x20];

5250
	u8         reserved_at_40[0x40];
5251

5252
	u8         rp_cur_flows[0x20];
5253 5254 5255

	u8         sum_flows[0x20];

5256
	u8         rp_cnp_ignored_high[0x20];
5257

5258
	u8         rp_cnp_ignored_low[0x20];
5259

5260
	u8         rp_cnp_handled_high[0x20];
5261

5262
	u8         rp_cnp_handled_low[0x20];
5263

5264
	u8         reserved_at_140[0x100];
5265 5266 5267 5268 5269 5270 5271

	u8         time_stamp_high[0x20];

	u8         time_stamp_low[0x20];

	u8         accumulators_period[0x20];

5272
	u8         np_ecn_marked_roce_packets_high[0x20];
5273

5274
	u8         np_ecn_marked_roce_packets_low[0x20];
5275

5276
	u8         np_cnp_sent_high[0x20];
5277

5278
	u8         np_cnp_sent_low[0x20];
5279

5280
	u8         reserved_at_320[0x560];
5281 5282 5283 5284
};

struct mlx5_ifc_query_cong_statistics_in_bits {
	u8         opcode[0x10];
5285
	u8         reserved_at_10[0x10];
5286

5287
	u8         reserved_at_20[0x10];
5288 5289 5290
	u8         op_mod[0x10];

	u8         clear[0x1];
5291
	u8         reserved_at_41[0x1f];
5292

5293
	u8         reserved_at_60[0x20];
5294 5295 5296 5297
};

struct mlx5_ifc_query_cong_params_out_bits {
	u8         status[0x8];
5298
	u8         reserved_at_8[0x18];
5299 5300 5301

	u8         syndrome[0x20];

5302
	u8         reserved_at_40[0x40];
5303 5304 5305 5306 5307 5308

	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
};

struct mlx5_ifc_query_cong_params_in_bits {
	u8         opcode[0x10];
5309
	u8         reserved_at_10[0x10];
5310

5311
	u8         reserved_at_20[0x10];
5312 5313
	u8         op_mod[0x10];

5314
	u8         reserved_at_40[0x1c];
5315 5316
	u8         cong_protocol[0x4];

5317
	u8         reserved_at_60[0x20];
5318 5319 5320 5321
};

struct mlx5_ifc_query_adapter_out_bits {
	u8         status[0x8];
5322
	u8         reserved_at_8[0x18];
5323 5324 5325

	u8         syndrome[0x20];

5326
	u8         reserved_at_40[0x40];
5327 5328 5329 5330 5331 5332

	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
};

struct mlx5_ifc_query_adapter_in_bits {
	u8         opcode[0x10];
5333
	u8         reserved_at_10[0x10];
5334

5335
	u8         reserved_at_20[0x10];
5336 5337
	u8         op_mod[0x10];

5338
	u8         reserved_at_40[0x40];
5339 5340 5341 5342
};

struct mlx5_ifc_qp_2rst_out_bits {
	u8         status[0x8];
5343
	u8         reserved_at_8[0x18];
5344 5345 5346

	u8         syndrome[0x20];

5347
	u8         reserved_at_40[0x40];
5348 5349 5350 5351
};

struct mlx5_ifc_qp_2rst_in_bits {
	u8         opcode[0x10];
5352
	u8         uid[0x10];
5353

5354
	u8         reserved_at_20[0x10];
5355 5356
	u8         op_mod[0x10];

5357
	u8         reserved_at_40[0x8];
5358 5359
	u8         qpn[0x18];

5360
	u8         reserved_at_60[0x20];
5361 5362 5363 5364
};

struct mlx5_ifc_qp_2err_out_bits {
	u8         status[0x8];
5365
	u8         reserved_at_8[0x18];
5366 5367 5368

	u8         syndrome[0x20];

5369
	u8         reserved_at_40[0x40];
5370 5371 5372 5373
};

struct mlx5_ifc_qp_2err_in_bits {
	u8         opcode[0x10];
5374
	u8         uid[0x10];
5375

5376
	u8         reserved_at_20[0x10];
5377 5378
	u8         op_mod[0x10];

5379
	u8         reserved_at_40[0x8];
5380 5381
	u8         qpn[0x18];

5382
	u8         reserved_at_60[0x20];
5383 5384 5385 5386
};

struct mlx5_ifc_page_fault_resume_out_bits {
	u8         status[0x8];
5387
	u8         reserved_at_8[0x18];
5388 5389 5390

	u8         syndrome[0x20];

5391
	u8         reserved_at_40[0x40];
5392 5393 5394 5395
};

struct mlx5_ifc_page_fault_resume_in_bits {
	u8         opcode[0x10];
5396
	u8         reserved_at_10[0x10];
5397

5398
	u8         reserved_at_20[0x10];
5399 5400 5401
	u8         op_mod[0x10];

	u8         error[0x1];
5402
	u8         reserved_at_41[0x4];
5403 5404
	u8         page_fault_type[0x3];
	u8         wq_number[0x18];
5405

5406 5407
	u8         reserved_at_60[0x8];
	u8         token[0x18];
5408 5409 5410 5411
};

struct mlx5_ifc_nop_out_bits {
	u8         status[0x8];
5412
	u8         reserved_at_8[0x18];
5413 5414 5415

	u8         syndrome[0x20];

5416
	u8         reserved_at_40[0x40];
5417 5418 5419 5420
};

struct mlx5_ifc_nop_in_bits {
	u8         opcode[0x10];
5421
	u8         reserved_at_10[0x10];
5422

5423
	u8         reserved_at_20[0x10];
5424 5425
	u8         op_mod[0x10];

5426
	u8         reserved_at_40[0x40];
5427 5428 5429 5430
};

struct mlx5_ifc_modify_vport_state_out_bits {
	u8         status[0x8];
5431
	u8         reserved_at_8[0x18];
5432 5433 5434

	u8         syndrome[0x20];

5435
	u8         reserved_at_40[0x40];
5436 5437 5438 5439
};

struct mlx5_ifc_modify_vport_state_in_bits {
	u8         opcode[0x10];
5440
	u8         reserved_at_10[0x10];
5441

5442
	u8         reserved_at_20[0x10];
5443 5444 5445
	u8         op_mod[0x10];

	u8         other_vport[0x1];
5446
	u8         reserved_at_41[0xf];
5447 5448
	u8         vport_number[0x10];

5449
	u8         reserved_at_60[0x18];
5450
	u8         admin_state[0x4];
5451
	u8         reserved_at_7c[0x4];
5452 5453 5454 5455
};

struct mlx5_ifc_modify_tis_out_bits {
	u8         status[0x8];
5456
	u8         reserved_at_8[0x18];
5457 5458 5459

	u8         syndrome[0x20];

5460
	u8         reserved_at_40[0x40];
5461 5462
};

5463
struct mlx5_ifc_modify_tis_bitmask_bits {
5464
	u8         reserved_at_0[0x20];
5465

5466 5467 5468
	u8         reserved_at_20[0x1d];
	u8         lag_tx_port_affinity[0x1];
	u8         strict_lag_tx_port_affinity[0x1];
5469 5470 5471
	u8         prio[0x1];
};

5472 5473
struct mlx5_ifc_modify_tis_in_bits {
	u8         opcode[0x10];
5474
	u8         uid[0x10];
5475

5476
	u8         reserved_at_20[0x10];
5477 5478
	u8         op_mod[0x10];

5479
	u8         reserved_at_40[0x8];
5480 5481
	u8         tisn[0x18];

5482
	u8         reserved_at_60[0x20];
5483

5484
	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5485

5486
	u8         reserved_at_c0[0x40];
5487 5488 5489 5490

	struct mlx5_ifc_tisc_bits ctx;
};

5491
struct mlx5_ifc_modify_tir_bitmask_bits {
5492
	u8	   reserved_at_0[0x20];
5493

5494
	u8         reserved_at_20[0x1b];
5495
	u8         self_lb_en[0x1];
5496 5497 5498
	u8         reserved_at_3c[0x1];
	u8         hash[0x1];
	u8         reserved_at_3e[0x1];
5499 5500 5501
	u8         lro[0x1];
};

5502 5503
struct mlx5_ifc_modify_tir_out_bits {
	u8         status[0x8];
5504
	u8         reserved_at_8[0x18];
5505 5506 5507

	u8         syndrome[0x20];

5508
	u8         reserved_at_40[0x40];
5509 5510 5511 5512
};

struct mlx5_ifc_modify_tir_in_bits {
	u8         opcode[0x10];
5513
	u8         uid[0x10];
5514

5515
	u8         reserved_at_20[0x10];
5516 5517
	u8         op_mod[0x10];

5518
	u8         reserved_at_40[0x8];
5519 5520
	u8         tirn[0x18];

5521
	u8         reserved_at_60[0x20];
5522

5523
	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5524

5525
	u8         reserved_at_c0[0x40];
5526 5527 5528 5529 5530 5531

	struct mlx5_ifc_tirc_bits ctx;
};

struct mlx5_ifc_modify_sq_out_bits {
	u8         status[0x8];
5532
	u8         reserved_at_8[0x18];
5533 5534 5535

	u8         syndrome[0x20];

5536
	u8         reserved_at_40[0x40];
5537 5538 5539 5540
};

struct mlx5_ifc_modify_sq_in_bits {
	u8         opcode[0x10];
5541
	u8         uid[0x10];
5542

5543
	u8         reserved_at_20[0x10];
5544 5545 5546
	u8         op_mod[0x10];

	u8         sq_state[0x4];
5547
	u8         reserved_at_44[0x4];
5548 5549
	u8         sqn[0x18];

5550
	u8         reserved_at_60[0x20];
5551 5552 5553

	u8         modify_bitmask[0x40];

5554
	u8         reserved_at_c0[0x40];
5555 5556 5557 5558

	struct mlx5_ifc_sqc_bits ctx;
};

5559 5560 5561 5562 5563 5564 5565 5566 5567 5568 5569 5570 5571 5572 5573 5574 5575 5576 5577 5578 5579 5580 5581 5582 5583 5584 5585 5586 5587 5588 5589 5590 5591 5592 5593 5594 5595
struct mlx5_ifc_modify_scheduling_element_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x1c0];
};

enum {
	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
};

struct mlx5_ifc_modify_scheduling_element_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         scheduling_hierarchy[0x8];
	u8         reserved_at_48[0x18];

	u8         scheduling_element_id[0x20];

	u8         reserved_at_80[0x20];

	u8         modify_bitmask[0x20];

	u8         reserved_at_c0[0x40];

	struct mlx5_ifc_scheduling_context_bits scheduling_context;

	u8         reserved_at_300[0x100];
};

5596 5597
struct mlx5_ifc_modify_rqt_out_bits {
	u8         status[0x8];
5598
	u8         reserved_at_8[0x18];
5599 5600 5601

	u8         syndrome[0x20];

5602
	u8         reserved_at_40[0x40];
5603 5604
};

5605
struct mlx5_ifc_rqt_bitmask_bits {
5606
	u8	   reserved_at_0[0x20];
5607

5608
	u8         reserved_at_20[0x1f];
5609 5610 5611
	u8         rqn_list[0x1];
};

5612 5613
struct mlx5_ifc_modify_rqt_in_bits {
	u8         opcode[0x10];
5614
	u8         uid[0x10];
5615

5616
	u8         reserved_at_20[0x10];
5617 5618
	u8         op_mod[0x10];

5619
	u8         reserved_at_40[0x8];
5620 5621
	u8         rqtn[0x18];

5622
	u8         reserved_at_60[0x20];
5623

5624
	struct mlx5_ifc_rqt_bitmask_bits bitmask;
5625

5626
	u8         reserved_at_c0[0x40];
5627 5628 5629 5630 5631 5632

	struct mlx5_ifc_rqtc_bits ctx;
};

struct mlx5_ifc_modify_rq_out_bits {
	u8         status[0x8];
5633
	u8         reserved_at_8[0x18];
5634 5635 5636

	u8         syndrome[0x20];

5637
	u8         reserved_at_40[0x40];
5638 5639
};

5640 5641
enum {
	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5642
	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5643
	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5644 5645
};

5646 5647
struct mlx5_ifc_modify_rq_in_bits {
	u8         opcode[0x10];
5648
	u8         uid[0x10];
5649

5650
	u8         reserved_at_20[0x10];
5651 5652 5653
	u8         op_mod[0x10];

	u8         rq_state[0x4];
5654
	u8         reserved_at_44[0x4];
5655 5656
	u8         rqn[0x18];

5657
	u8         reserved_at_60[0x20];
5658 5659 5660

	u8         modify_bitmask[0x40];

5661
	u8         reserved_at_c0[0x40];
5662 5663 5664 5665 5666 5667

	struct mlx5_ifc_rqc_bits ctx;
};

struct mlx5_ifc_modify_rmp_out_bits {
	u8         status[0x8];
5668
	u8         reserved_at_8[0x18];
5669 5670 5671

	u8         syndrome[0x20];

5672
	u8         reserved_at_40[0x40];
5673 5674
};

5675
struct mlx5_ifc_rmp_bitmask_bits {
5676
	u8	   reserved_at_0[0x20];
5677

5678
	u8         reserved_at_20[0x1f];
5679 5680 5681
	u8         lwm[0x1];
};

5682 5683
struct mlx5_ifc_modify_rmp_in_bits {
	u8         opcode[0x10];
5684
	u8         uid[0x10];
5685

5686
	u8         reserved_at_20[0x10];
5687 5688 5689
	u8         op_mod[0x10];

	u8         rmp_state[0x4];
5690
	u8         reserved_at_44[0x4];
5691 5692
	u8         rmpn[0x18];

5693
	u8         reserved_at_60[0x20];
5694

5695
	struct mlx5_ifc_rmp_bitmask_bits bitmask;
5696

5697
	u8         reserved_at_c0[0x40];
5698 5699 5700 5701 5702 5703

	struct mlx5_ifc_rmpc_bits ctx;
};

struct mlx5_ifc_modify_nic_vport_context_out_bits {
	u8         status[0x8];
5704
	u8         reserved_at_8[0x18];
5705 5706 5707

	u8         syndrome[0x20];

5708
	u8         reserved_at_40[0x40];
5709 5710 5711
};

struct mlx5_ifc_modify_nic_vport_field_select_bits {
5712 5713
	u8         reserved_at_0[0x12];
	u8	   affiliation[0x1];
5714
	u8	   reserved_at_13[0x1];
5715 5716
	u8         disable_uc_local_lb[0x1];
	u8         disable_mc_local_lb[0x1];
5717 5718
	u8         node_guid[0x1];
	u8         port_guid[0x1];
5719
	u8         min_inline[0x1];
5720 5721 5722
	u8         mtu[0x1];
	u8         change_event[0x1];
	u8         promisc[0x1];
5723 5724 5725
	u8         permanent_address[0x1];
	u8         addresses_list[0x1];
	u8         roce_en[0x1];
5726
	u8         reserved_at_1f[0x1];
5727 5728 5729 5730
};

struct mlx5_ifc_modify_nic_vport_context_in_bits {
	u8         opcode[0x10];
5731
	u8         reserved_at_10[0x10];
5732

5733
	u8         reserved_at_20[0x10];
5734 5735 5736
	u8         op_mod[0x10];

	u8         other_vport[0x1];
5737
	u8         reserved_at_41[0xf];
5738 5739 5740 5741
	u8         vport_number[0x10];

	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;

5742
	u8         reserved_at_80[0x780];
5743 5744 5745 5746 5747 5748

	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
};

struct mlx5_ifc_modify_hca_vport_context_out_bits {
	u8         status[0x8];
5749
	u8         reserved_at_8[0x18];
5750 5751 5752

	u8         syndrome[0x20];

5753
	u8         reserved_at_40[0x40];
5754 5755 5756 5757
};

struct mlx5_ifc_modify_hca_vport_context_in_bits {
	u8         opcode[0x10];
5758
	u8         reserved_at_10[0x10];
5759

5760
	u8         reserved_at_20[0x10];
5761 5762 5763
	u8         op_mod[0x10];

	u8         other_vport[0x1];
5764
	u8         reserved_at_41[0xb];
5765
	u8         port_num[0x4];
5766 5767
	u8         vport_number[0x10];

5768
	u8         reserved_at_60[0x20];
5769 5770 5771 5772 5773 5774

	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
};

struct mlx5_ifc_modify_cq_out_bits {
	u8         status[0x8];
5775
	u8         reserved_at_8[0x18];
5776 5777 5778

	u8         syndrome[0x20];

5779
	u8         reserved_at_40[0x40];
5780 5781 5782 5783 5784 5785 5786 5787 5788
};

enum {
	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
};

struct mlx5_ifc_modify_cq_in_bits {
	u8         opcode[0x10];
5789
	u8         uid[0x10];
5790

5791
	u8         reserved_at_20[0x10];
5792 5793
	u8         op_mod[0x10];

5794
	u8         reserved_at_40[0x8];
5795 5796 5797 5798 5799 5800
	u8         cqn[0x18];

	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;

	struct mlx5_ifc_cqc_bits cq_context;

5801 5802 5803 5804
	u8         reserved_at_280[0x40];

	u8         cq_umem_valid[0x1];
	u8         reserved_at_2c1[0x5bf];
5805 5806 5807 5808 5809 5810

	u8         pas[0][0x40];
};

struct mlx5_ifc_modify_cong_status_out_bits {
	u8         status[0x8];
5811
	u8         reserved_at_8[0x18];
5812 5813 5814

	u8         syndrome[0x20];

5815
	u8         reserved_at_40[0x40];
5816 5817 5818 5819
};

struct mlx5_ifc_modify_cong_status_in_bits {
	u8         opcode[0x10];
5820
	u8         reserved_at_10[0x10];
5821

5822
	u8         reserved_at_20[0x10];
5823 5824
	u8         op_mod[0x10];

5825
	u8         reserved_at_40[0x18];
5826 5827 5828 5829 5830
	u8         priority[0x4];
	u8         cong_protocol[0x4];

	u8         enable[0x1];
	u8         tag_enable[0x1];
5831
	u8         reserved_at_62[0x1e];
5832 5833 5834 5835
};

struct mlx5_ifc_modify_cong_params_out_bits {
	u8         status[0x8];
5836
	u8         reserved_at_8[0x18];
5837 5838 5839

	u8         syndrome[0x20];

5840
	u8         reserved_at_40[0x40];
5841 5842 5843 5844
};

struct mlx5_ifc_modify_cong_params_in_bits {
	u8         opcode[0x10];
5845
	u8         reserved_at_10[0x10];
5846

5847
	u8         reserved_at_20[0x10];
5848 5849
	u8         op_mod[0x10];

5850
	u8         reserved_at_40[0x1c];
5851 5852 5853 5854
	u8         cong_protocol[0x4];

	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;

5855
	u8         reserved_at_80[0x80];
5856 5857 5858 5859 5860 5861

	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
};

struct mlx5_ifc_manage_pages_out_bits {
	u8         status[0x8];
5862
	u8         reserved_at_8[0x18];
5863 5864 5865 5866 5867

	u8         syndrome[0x20];

	u8         output_num_entries[0x20];

5868
	u8         reserved_at_60[0x20];
5869 5870 5871 5872 5873 5874 5875 5876 5877 5878 5879 5880

	u8         pas[0][0x40];
};

enum {
	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
};

struct mlx5_ifc_manage_pages_in_bits {
	u8         opcode[0x10];
5881
	u8         reserved_at_10[0x10];
5882

5883
	u8         reserved_at_20[0x10];
5884 5885
	u8         op_mod[0x10];

5886 5887
	u8         embedded_cpu_function[0x1];
	u8         reserved_at_41[0xf];
5888 5889 5890 5891 5892 5893 5894 5895 5896
	u8         function_id[0x10];

	u8         input_num_entries[0x20];

	u8         pas[0][0x40];
};

struct mlx5_ifc_mad_ifc_out_bits {
	u8         status[0x8];
5897
	u8         reserved_at_8[0x18];
5898 5899 5900

	u8         syndrome[0x20];

5901
	u8         reserved_at_40[0x40];
5902 5903 5904 5905 5906 5907

	u8         response_mad_packet[256][0x8];
};

struct mlx5_ifc_mad_ifc_in_bits {
	u8         opcode[0x10];
5908
	u8         reserved_at_10[0x10];
5909

5910
	u8         reserved_at_20[0x10];
5911 5912 5913
	u8         op_mod[0x10];

	u8         remote_lid[0x10];
5914
	u8         reserved_at_50[0x8];
5915 5916
	u8         port[0x8];

5917
	u8         reserved_at_60[0x20];
5918 5919 5920 5921 5922 5923

	u8         mad[256][0x8];
};

struct mlx5_ifc_init_hca_out_bits {
	u8         status[0x8];
5924
	u8         reserved_at_8[0x18];
5925 5926 5927

	u8         syndrome[0x20];

5928
	u8         reserved_at_40[0x40];
5929 5930 5931 5932
};

struct mlx5_ifc_init_hca_in_bits {
	u8         opcode[0x10];
5933
	u8         reserved_at_10[0x10];
5934

5935
	u8         reserved_at_20[0x10];
5936 5937
	u8         op_mod[0x10];

5938
	u8         reserved_at_40[0x40];
5939
	u8	   sw_owner_id[4][0x20];
5940 5941 5942 5943
};

struct mlx5_ifc_init2rtr_qp_out_bits {
	u8         status[0x8];
5944
	u8         reserved_at_8[0x18];
5945 5946 5947

	u8         syndrome[0x20];

5948
	u8         reserved_at_40[0x40];
5949 5950 5951 5952
};

struct mlx5_ifc_init2rtr_qp_in_bits {
	u8         opcode[0x10];
5953
	u8         uid[0x10];
5954

5955
	u8         reserved_at_20[0x10];
5956 5957
	u8         op_mod[0x10];

5958
	u8         reserved_at_40[0x8];
5959 5960
	u8         qpn[0x18];

5961
	u8         reserved_at_60[0x20];
5962 5963 5964

	u8         opt_param_mask[0x20];

5965
	u8         reserved_at_a0[0x20];
5966 5967 5968

	struct mlx5_ifc_qpc_bits qpc;

5969
	u8         reserved_at_800[0x80];
5970 5971 5972 5973
};

struct mlx5_ifc_init2init_qp_out_bits {
	u8         status[0x8];
5974
	u8         reserved_at_8[0x18];
5975 5976 5977

	u8         syndrome[0x20];

5978
	u8         reserved_at_40[0x40];
5979 5980 5981 5982
};

struct mlx5_ifc_init2init_qp_in_bits {
	u8         opcode[0x10];
5983
	u8         uid[0x10];
5984

5985
	u8         reserved_at_20[0x10];
5986 5987
	u8         op_mod[0x10];

5988
	u8         reserved_at_40[0x8];
5989 5990
	u8         qpn[0x18];

5991
	u8         reserved_at_60[0x20];
5992 5993 5994

	u8         opt_param_mask[0x20];

5995
	u8         reserved_at_a0[0x20];
5996 5997 5998

	struct mlx5_ifc_qpc_bits qpc;

5999
	u8         reserved_at_800[0x80];
6000 6001 6002 6003
};

struct mlx5_ifc_get_dropped_packet_log_out_bits {
	u8         status[0x8];
6004
	u8         reserved_at_8[0x18];
6005 6006 6007

	u8         syndrome[0x20];

6008
	u8         reserved_at_40[0x40];
6009 6010 6011 6012 6013 6014 6015 6016

	u8         packet_headers_log[128][0x8];

	u8         packet_syndrome[64][0x8];
};

struct mlx5_ifc_get_dropped_packet_log_in_bits {
	u8         opcode[0x10];
6017
	u8         reserved_at_10[0x10];
6018

6019
	u8         reserved_at_20[0x10];
6020 6021
	u8         op_mod[0x10];

6022
	u8         reserved_at_40[0x40];
6023 6024 6025 6026
};

struct mlx5_ifc_gen_eqe_in_bits {
	u8         opcode[0x10];
6027
	u8         reserved_at_10[0x10];
6028

6029
	u8         reserved_at_20[0x10];
6030 6031
	u8         op_mod[0x10];

6032
	u8         reserved_at_40[0x18];
6033 6034
	u8         eq_number[0x8];

6035
	u8         reserved_at_60[0x20];
6036 6037 6038 6039 6040 6041

	u8         eqe[64][0x8];
};

struct mlx5_ifc_gen_eq_out_bits {
	u8         status[0x8];
6042
	u8         reserved_at_8[0x18];
6043 6044 6045

	u8         syndrome[0x20];

6046
	u8         reserved_at_40[0x40];
6047 6048 6049 6050
};

struct mlx5_ifc_enable_hca_out_bits {
	u8         status[0x8];
6051
	u8         reserved_at_8[0x18];
6052 6053 6054

	u8         syndrome[0x20];

6055
	u8         reserved_at_40[0x20];
6056 6057 6058 6059
};

struct mlx5_ifc_enable_hca_in_bits {
	u8         opcode[0x10];
6060
	u8         reserved_at_10[0x10];
6061

6062
	u8         reserved_at_20[0x10];
6063 6064
	u8         op_mod[0x10];

6065 6066
	u8         embedded_cpu_function[0x1];
	u8         reserved_at_41[0xf];
6067 6068
	u8         function_id[0x10];

6069
	u8         reserved_at_60[0x20];
6070 6071 6072 6073
};

struct mlx5_ifc_drain_dct_out_bits {
	u8         status[0x8];
6074
	u8         reserved_at_8[0x18];
6075 6076 6077

	u8         syndrome[0x20];

6078
	u8         reserved_at_40[0x40];
6079 6080 6081 6082
};

struct mlx5_ifc_drain_dct_in_bits {
	u8         opcode[0x10];
6083
	u8         uid[0x10];
6084

6085
	u8         reserved_at_20[0x10];
6086 6087
	u8         op_mod[0x10];

6088
	u8         reserved_at_40[0x8];
6089 6090
	u8         dctn[0x18];

6091
	u8         reserved_at_60[0x20];
6092 6093 6094 6095
};

struct mlx5_ifc_disable_hca_out_bits {
	u8         status[0x8];
6096
	u8         reserved_at_8[0x18];
6097 6098 6099

	u8         syndrome[0x20];

6100
	u8         reserved_at_40[0x20];
6101 6102 6103 6104
};

struct mlx5_ifc_disable_hca_in_bits {
	u8         opcode[0x10];
6105
	u8         reserved_at_10[0x10];
6106

6107
	u8         reserved_at_20[0x10];
6108 6109
	u8         op_mod[0x10];

6110 6111
	u8         embedded_cpu_function[0x1];
	u8         reserved_at_41[0xf];
6112 6113
	u8         function_id[0x10];

6114
	u8         reserved_at_60[0x20];
6115 6116 6117 6118
};

struct mlx5_ifc_detach_from_mcg_out_bits {
	u8         status[0x8];
6119
	u8         reserved_at_8[0x18];
6120 6121 6122

	u8         syndrome[0x20];

6123
	u8         reserved_at_40[0x40];
6124 6125 6126 6127
};

struct mlx5_ifc_detach_from_mcg_in_bits {
	u8         opcode[0x10];
6128
	u8         uid[0x10];
6129

6130
	u8         reserved_at_20[0x10];
6131 6132
	u8         op_mod[0x10];

6133
	u8         reserved_at_40[0x8];
6134 6135
	u8         qpn[0x18];

6136
	u8         reserved_at_60[0x20];
6137 6138 6139 6140

	u8         multicast_gid[16][0x8];
};

6141 6142 6143 6144 6145 6146 6147 6148 6149 6150 6151
struct mlx5_ifc_destroy_xrq_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_destroy_xrq_in_bits {
	u8         opcode[0x10];
6152
	u8         uid[0x10];
6153 6154 6155 6156 6157 6158 6159 6160 6161 6162

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x8];
	u8         xrqn[0x18];

	u8         reserved_at_60[0x20];
};

6163 6164
struct mlx5_ifc_destroy_xrc_srq_out_bits {
	u8         status[0x8];
6165
	u8         reserved_at_8[0x18];
6166 6167 6168

	u8         syndrome[0x20];

6169
	u8         reserved_at_40[0x40];
6170 6171 6172 6173
};

struct mlx5_ifc_destroy_xrc_srq_in_bits {
	u8         opcode[0x10];
6174
	u8         uid[0x10];
6175

6176
	u8         reserved_at_20[0x10];
6177 6178
	u8         op_mod[0x10];

6179
	u8         reserved_at_40[0x8];
6180 6181
	u8         xrc_srqn[0x18];

6182
	u8         reserved_at_60[0x20];
6183 6184 6185 6186
};

struct mlx5_ifc_destroy_tis_out_bits {
	u8         status[0x8];
6187
	u8         reserved_at_8[0x18];
6188 6189 6190

	u8         syndrome[0x20];

6191
	u8         reserved_at_40[0x40];
6192 6193 6194 6195
};

struct mlx5_ifc_destroy_tis_in_bits {
	u8         opcode[0x10];
6196
	u8         uid[0x10];
6197

6198
	u8         reserved_at_20[0x10];
6199 6200
	u8         op_mod[0x10];

6201
	u8         reserved_at_40[0x8];
6202 6203
	u8         tisn[0x18];

6204
	u8         reserved_at_60[0x20];
6205 6206 6207 6208
};

struct mlx5_ifc_destroy_tir_out_bits {
	u8         status[0x8];
6209
	u8         reserved_at_8[0x18];
6210 6211 6212

	u8         syndrome[0x20];

6213
	u8         reserved_at_40[0x40];
6214 6215 6216 6217
};

struct mlx5_ifc_destroy_tir_in_bits {
	u8         opcode[0x10];
6218
	u8         uid[0x10];
6219

6220
	u8         reserved_at_20[0x10];
6221 6222
	u8         op_mod[0x10];

6223
	u8         reserved_at_40[0x8];
6224 6225
	u8         tirn[0x18];

6226
	u8         reserved_at_60[0x20];
6227 6228 6229 6230
};

struct mlx5_ifc_destroy_srq_out_bits {
	u8         status[0x8];
6231
	u8         reserved_at_8[0x18];
6232 6233 6234

	u8         syndrome[0x20];

6235
	u8         reserved_at_40[0x40];
6236 6237 6238 6239
};

struct mlx5_ifc_destroy_srq_in_bits {
	u8         opcode[0x10];
6240
	u8         uid[0x10];
6241

6242
	u8         reserved_at_20[0x10];
6243 6244
	u8         op_mod[0x10];

6245
	u8         reserved_at_40[0x8];
6246 6247
	u8         srqn[0x18];

6248
	u8         reserved_at_60[0x20];
6249 6250 6251 6252
};

struct mlx5_ifc_destroy_sq_out_bits {
	u8         status[0x8];
6253
	u8         reserved_at_8[0x18];
6254 6255 6256

	u8         syndrome[0x20];

6257
	u8         reserved_at_40[0x40];
6258 6259 6260 6261
};

struct mlx5_ifc_destroy_sq_in_bits {
	u8         opcode[0x10];
6262
	u8         uid[0x10];
6263

6264
	u8         reserved_at_20[0x10];
6265 6266
	u8         op_mod[0x10];

6267
	u8         reserved_at_40[0x8];
6268 6269
	u8         sqn[0x18];

6270
	u8         reserved_at_60[0x20];
6271 6272
};

6273 6274 6275 6276 6277 6278 6279 6280 6281 6282 6283 6284 6285 6286 6287 6288 6289 6290 6291 6292 6293 6294 6295 6296
struct mlx5_ifc_destroy_scheduling_element_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x1c0];
};

struct mlx5_ifc_destroy_scheduling_element_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         scheduling_hierarchy[0x8];
	u8         reserved_at_48[0x18];

	u8         scheduling_element_id[0x20];

	u8         reserved_at_80[0x180];
};

6297 6298
struct mlx5_ifc_destroy_rqt_out_bits {
	u8         status[0x8];
6299
	u8         reserved_at_8[0x18];
6300 6301 6302

	u8         syndrome[0x20];

6303
	u8         reserved_at_40[0x40];
6304 6305 6306 6307
};

struct mlx5_ifc_destroy_rqt_in_bits {
	u8         opcode[0x10];
6308
	u8         uid[0x10];
6309

6310
	u8         reserved_at_20[0x10];
6311 6312
	u8         op_mod[0x10];

6313
	u8         reserved_at_40[0x8];
6314 6315
	u8         rqtn[0x18];

6316
	u8         reserved_at_60[0x20];
6317 6318 6319 6320
};

struct mlx5_ifc_destroy_rq_out_bits {
	u8         status[0x8];
6321
	u8         reserved_at_8[0x18];
6322 6323 6324

	u8         syndrome[0x20];

6325
	u8         reserved_at_40[0x40];
6326 6327 6328 6329
};

struct mlx5_ifc_destroy_rq_in_bits {
	u8         opcode[0x10];
6330
	u8         uid[0x10];
6331

6332
	u8         reserved_at_20[0x10];
6333 6334
	u8         op_mod[0x10];

6335
	u8         reserved_at_40[0x8];
6336 6337
	u8         rqn[0x18];

6338
	u8         reserved_at_60[0x20];
6339 6340
};

6341 6342 6343 6344 6345 6346 6347 6348 6349 6350 6351 6352 6353 6354 6355 6356 6357 6358 6359 6360 6361 6362
struct mlx5_ifc_set_delay_drop_params_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x20];

	u8         reserved_at_60[0x10];
	u8         delay_drop_timeout[0x10];
};

struct mlx5_ifc_set_delay_drop_params_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

6363 6364
struct mlx5_ifc_destroy_rmp_out_bits {
	u8         status[0x8];
6365
	u8         reserved_at_8[0x18];
6366 6367 6368

	u8         syndrome[0x20];

6369
	u8         reserved_at_40[0x40];
6370 6371 6372 6373
};

struct mlx5_ifc_destroy_rmp_in_bits {
	u8         opcode[0x10];
6374
	u8         uid[0x10];
6375

6376
	u8         reserved_at_20[0x10];
6377 6378
	u8         op_mod[0x10];

6379
	u8         reserved_at_40[0x8];
6380 6381
	u8         rmpn[0x18];

6382
	u8         reserved_at_60[0x20];
6383 6384 6385 6386
};

struct mlx5_ifc_destroy_qp_out_bits {
	u8         status[0x8];
6387
	u8         reserved_at_8[0x18];
6388 6389 6390

	u8         syndrome[0x20];

6391
	u8         reserved_at_40[0x40];
6392 6393 6394 6395
};

struct mlx5_ifc_destroy_qp_in_bits {
	u8         opcode[0x10];
6396
	u8         uid[0x10];
6397

6398
	u8         reserved_at_20[0x10];
6399 6400
	u8         op_mod[0x10];

6401
	u8         reserved_at_40[0x8];
6402 6403
	u8         qpn[0x18];

6404
	u8         reserved_at_60[0x20];
6405 6406 6407 6408
};

struct mlx5_ifc_destroy_psv_out_bits {
	u8         status[0x8];
6409
	u8         reserved_at_8[0x18];
6410 6411 6412

	u8         syndrome[0x20];

6413
	u8         reserved_at_40[0x40];
6414 6415 6416 6417
};

struct mlx5_ifc_destroy_psv_in_bits {
	u8         opcode[0x10];
6418
	u8         reserved_at_10[0x10];
6419

6420
	u8         reserved_at_20[0x10];
6421 6422
	u8         op_mod[0x10];

6423
	u8         reserved_at_40[0x8];
6424 6425
	u8         psvn[0x18];

6426
	u8         reserved_at_60[0x20];
6427 6428 6429 6430
};

struct mlx5_ifc_destroy_mkey_out_bits {
	u8         status[0x8];
6431
	u8         reserved_at_8[0x18];
6432 6433 6434

	u8         syndrome[0x20];

6435
	u8         reserved_at_40[0x40];
6436 6437 6438 6439
};

struct mlx5_ifc_destroy_mkey_in_bits {
	u8         opcode[0x10];
6440
	u8         reserved_at_10[0x10];
6441

6442
	u8         reserved_at_20[0x10];
6443 6444
	u8         op_mod[0x10];

6445
	u8         reserved_at_40[0x8];
6446 6447
	u8         mkey_index[0x18];

6448
	u8         reserved_at_60[0x20];
6449 6450 6451 6452
};

struct mlx5_ifc_destroy_flow_table_out_bits {
	u8         status[0x8];
6453
	u8         reserved_at_8[0x18];
6454 6455 6456

	u8         syndrome[0x20];

6457
	u8         reserved_at_40[0x40];
6458 6459 6460 6461
};

struct mlx5_ifc_destroy_flow_table_in_bits {
	u8         opcode[0x10];
6462
	u8         reserved_at_10[0x10];
6463

6464
	u8         reserved_at_20[0x10];
6465 6466
	u8         op_mod[0x10];

6467 6468 6469 6470 6471
	u8         other_vport[0x1];
	u8         reserved_at_41[0xf];
	u8         vport_number[0x10];

	u8         reserved_at_60[0x20];
6472 6473

	u8         table_type[0x8];
6474
	u8         reserved_at_88[0x18];
6475

6476
	u8         reserved_at_a0[0x8];
6477 6478
	u8         table_id[0x18];

6479
	u8         reserved_at_c0[0x140];
6480 6481 6482 6483
};

struct mlx5_ifc_destroy_flow_group_out_bits {
	u8         status[0x8];
6484
	u8         reserved_at_8[0x18];
6485 6486 6487

	u8         syndrome[0x20];

6488
	u8         reserved_at_40[0x40];
6489 6490 6491 6492
};

struct mlx5_ifc_destroy_flow_group_in_bits {
	u8         opcode[0x10];
6493
	u8         reserved_at_10[0x10];
6494

6495
	u8         reserved_at_20[0x10];
6496 6497
	u8         op_mod[0x10];

6498 6499 6500 6501 6502
	u8         other_vport[0x1];
	u8         reserved_at_41[0xf];
	u8         vport_number[0x10];

	u8         reserved_at_60[0x20];
6503 6504

	u8         table_type[0x8];
6505
	u8         reserved_at_88[0x18];
6506

6507
	u8         reserved_at_a0[0x8];
6508 6509 6510 6511
	u8         table_id[0x18];

	u8         group_id[0x20];

6512
	u8         reserved_at_e0[0x120];
6513 6514 6515 6516
};

struct mlx5_ifc_destroy_eq_out_bits {
	u8         status[0x8];
6517
	u8         reserved_at_8[0x18];
6518 6519 6520

	u8         syndrome[0x20];

6521
	u8         reserved_at_40[0x40];
6522 6523 6524 6525
};

struct mlx5_ifc_destroy_eq_in_bits {
	u8         opcode[0x10];
6526
	u8         reserved_at_10[0x10];
6527

6528
	u8         reserved_at_20[0x10];
6529 6530
	u8         op_mod[0x10];

6531
	u8         reserved_at_40[0x18];
6532 6533
	u8         eq_number[0x8];

6534
	u8         reserved_at_60[0x20];
6535 6536 6537 6538
};

struct mlx5_ifc_destroy_dct_out_bits {
	u8         status[0x8];
6539
	u8         reserved_at_8[0x18];
6540 6541 6542

	u8         syndrome[0x20];

6543
	u8         reserved_at_40[0x40];
6544 6545 6546 6547
};

struct mlx5_ifc_destroy_dct_in_bits {
	u8         opcode[0x10];
6548
	u8         uid[0x10];
6549

6550
	u8         reserved_at_20[0x10];
6551 6552
	u8         op_mod[0x10];

6553
	u8         reserved_at_40[0x8];
6554 6555
	u8         dctn[0x18];

6556
	u8         reserved_at_60[0x20];
6557 6558 6559 6560
};

struct mlx5_ifc_destroy_cq_out_bits {
	u8         status[0x8];
6561
	u8         reserved_at_8[0x18];
6562 6563 6564

	u8         syndrome[0x20];

6565
	u8         reserved_at_40[0x40];
6566 6567 6568 6569
};

struct mlx5_ifc_destroy_cq_in_bits {
	u8         opcode[0x10];
6570
	u8         uid[0x10];
6571

6572
	u8         reserved_at_20[0x10];
6573 6574
	u8         op_mod[0x10];

6575
	u8         reserved_at_40[0x8];
6576 6577
	u8         cqn[0x18];

6578
	u8         reserved_at_60[0x20];
6579 6580 6581 6582
};

struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
	u8         status[0x8];
6583
	u8         reserved_at_8[0x18];
6584 6585 6586

	u8         syndrome[0x20];

6587
	u8         reserved_at_40[0x40];
6588 6589 6590 6591
};

struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
	u8         opcode[0x10];
6592
	u8         reserved_at_10[0x10];
6593

6594
	u8         reserved_at_20[0x10];
6595 6596
	u8         op_mod[0x10];

6597
	u8         reserved_at_40[0x20];
6598

6599
	u8         reserved_at_60[0x10];
6600 6601 6602 6603 6604
	u8         vxlan_udp_port[0x10];
};

struct mlx5_ifc_delete_l2_table_entry_out_bits {
	u8         status[0x8];
6605
	u8         reserved_at_8[0x18];
6606 6607 6608

	u8         syndrome[0x20];

6609
	u8         reserved_at_40[0x40];
6610 6611 6612 6613
};

struct mlx5_ifc_delete_l2_table_entry_in_bits {
	u8         opcode[0x10];
6614
	u8         reserved_at_10[0x10];
6615

6616
	u8         reserved_at_20[0x10];
6617 6618
	u8         op_mod[0x10];

6619
	u8         reserved_at_40[0x60];
6620

6621
	u8         reserved_at_a0[0x8];
6622 6623
	u8         table_index[0x18];

6624
	u8         reserved_at_c0[0x140];
6625 6626 6627 6628
};

struct mlx5_ifc_delete_fte_out_bits {
	u8         status[0x8];
6629
	u8         reserved_at_8[0x18];
6630 6631 6632

	u8         syndrome[0x20];

6633
	u8         reserved_at_40[0x40];
6634 6635 6636 6637
};

struct mlx5_ifc_delete_fte_in_bits {
	u8         opcode[0x10];
6638
	u8         reserved_at_10[0x10];
6639

6640
	u8         reserved_at_20[0x10];
6641 6642
	u8         op_mod[0x10];

6643 6644 6645 6646 6647
	u8         other_vport[0x1];
	u8         reserved_at_41[0xf];
	u8         vport_number[0x10];

	u8         reserved_at_60[0x20];
6648 6649

	u8         table_type[0x8];
6650
	u8         reserved_at_88[0x18];
6651

6652
	u8         reserved_at_a0[0x8];
6653 6654
	u8         table_id[0x18];

6655
	u8         reserved_at_c0[0x40];
6656 6657 6658

	u8         flow_index[0x20];

6659
	u8         reserved_at_120[0xe0];
6660 6661 6662 6663
};

struct mlx5_ifc_dealloc_xrcd_out_bits {
	u8         status[0x8];
6664
	u8         reserved_at_8[0x18];
6665 6666 6667

	u8         syndrome[0x20];

6668
	u8         reserved_at_40[0x40];
6669 6670 6671 6672
};

struct mlx5_ifc_dealloc_xrcd_in_bits {
	u8         opcode[0x10];
6673
	u8         uid[0x10];
6674

6675
	u8         reserved_at_20[0x10];
6676 6677
	u8         op_mod[0x10];

6678
	u8         reserved_at_40[0x8];
6679 6680
	u8         xrcd[0x18];

6681
	u8         reserved_at_60[0x20];
6682 6683 6684 6685
};

struct mlx5_ifc_dealloc_uar_out_bits {
	u8         status[0x8];
6686
	u8         reserved_at_8[0x18];
6687 6688 6689

	u8         syndrome[0x20];

6690
	u8         reserved_at_40[0x40];
6691 6692 6693 6694
};

struct mlx5_ifc_dealloc_uar_in_bits {
	u8         opcode[0x10];
6695
	u8         reserved_at_10[0x10];
6696

6697
	u8         reserved_at_20[0x10];
6698 6699
	u8         op_mod[0x10];

6700
	u8         reserved_at_40[0x8];
6701 6702
	u8         uar[0x18];

6703
	u8         reserved_at_60[0x20];
6704 6705 6706 6707
};

struct mlx5_ifc_dealloc_transport_domain_out_bits {
	u8         status[0x8];
6708
	u8         reserved_at_8[0x18];
6709 6710 6711

	u8         syndrome[0x20];

6712
	u8         reserved_at_40[0x40];
6713 6714 6715 6716
};

struct mlx5_ifc_dealloc_transport_domain_in_bits {
	u8         opcode[0x10];
6717
	u8         uid[0x10];
6718

6719
	u8         reserved_at_20[0x10];
6720 6721
	u8         op_mod[0x10];

6722
	u8         reserved_at_40[0x8];
6723 6724
	u8         transport_domain[0x18];

6725
	u8         reserved_at_60[0x20];
6726 6727 6728 6729
};

struct mlx5_ifc_dealloc_q_counter_out_bits {
	u8         status[0x8];
6730
	u8         reserved_at_8[0x18];
6731 6732 6733

	u8         syndrome[0x20];

6734
	u8         reserved_at_40[0x40];
6735 6736 6737 6738
};

struct mlx5_ifc_dealloc_q_counter_in_bits {
	u8         opcode[0x10];
6739
	u8         reserved_at_10[0x10];
6740

6741
	u8         reserved_at_20[0x10];
6742 6743
	u8         op_mod[0x10];

6744
	u8         reserved_at_40[0x18];
6745 6746
	u8         counter_set_id[0x8];

6747
	u8         reserved_at_60[0x20];
6748 6749 6750 6751
};

struct mlx5_ifc_dealloc_pd_out_bits {
	u8         status[0x8];
6752
	u8         reserved_at_8[0x18];
6753 6754 6755

	u8         syndrome[0x20];

6756
	u8         reserved_at_40[0x40];
6757 6758 6759 6760
};

struct mlx5_ifc_dealloc_pd_in_bits {
	u8         opcode[0x10];
6761
	u8         uid[0x10];
6762

6763
	u8         reserved_at_20[0x10];
6764 6765
	u8         op_mod[0x10];

6766
	u8         reserved_at_40[0x8];
6767 6768
	u8         pd[0x18];

6769
	u8         reserved_at_60[0x20];
6770 6771
};

6772 6773 6774 6775 6776 6777 6778 6779 6780 6781 6782 6783 6784 6785 6786 6787
struct mlx5_ifc_dealloc_flow_counter_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_dealloc_flow_counter_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

6788
	u8         flow_counter_id[0x20];
6789 6790 6791 6792

	u8         reserved_at_60[0x20];
};

6793 6794 6795 6796 6797 6798 6799 6800 6801 6802 6803 6804 6805 6806
struct mlx5_ifc_create_xrq_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x8];
	u8         xrqn[0x18];

	u8         reserved_at_60[0x20];
};

struct mlx5_ifc_create_xrq_in_bits {
	u8         opcode[0x10];
6807
	u8         uid[0x10];
6808 6809 6810 6811 6812 6813 6814 6815 6816

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x40];

	struct mlx5_ifc_xrqc_bits xrq_context;
};

6817 6818
struct mlx5_ifc_create_xrc_srq_out_bits {
	u8         status[0x8];
6819
	u8         reserved_at_8[0x18];
6820 6821 6822

	u8         syndrome[0x20];

6823
	u8         reserved_at_40[0x8];
6824 6825
	u8         xrc_srqn[0x18];

6826
	u8         reserved_at_60[0x20];
6827 6828 6829 6830
};

struct mlx5_ifc_create_xrc_srq_in_bits {
	u8         opcode[0x10];
6831
	u8         uid[0x10];
6832

6833
	u8         reserved_at_20[0x10];
6834 6835
	u8         op_mod[0x10];

6836
	u8         reserved_at_40[0x40];
6837 6838 6839

	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;

6840 6841
	u8         reserved_at_280[0x60];

6842
	u8         xrc_srq_umem_valid[0x1];
6843 6844 6845
	u8         reserved_at_2e1[0x1f];

	u8         reserved_at_300[0x580];
6846 6847 6848 6849 6850 6851

	u8         pas[0][0x40];
};

struct mlx5_ifc_create_tis_out_bits {
	u8         status[0x8];
6852
	u8         reserved_at_8[0x18];
6853 6854 6855

	u8         syndrome[0x20];

6856
	u8         reserved_at_40[0x8];
6857 6858
	u8         tisn[0x18];

6859
	u8         reserved_at_60[0x20];
6860 6861 6862 6863
};

struct mlx5_ifc_create_tis_in_bits {
	u8         opcode[0x10];
6864
	u8         uid[0x10];
6865

6866
	u8         reserved_at_20[0x10];
6867 6868
	u8         op_mod[0x10];

6869
	u8         reserved_at_40[0xc0];
6870 6871 6872 6873 6874 6875

	struct mlx5_ifc_tisc_bits ctx;
};

struct mlx5_ifc_create_tir_out_bits {
	u8         status[0x8];
6876
	u8         reserved_at_8[0x18];
6877 6878 6879

	u8         syndrome[0x20];

6880
	u8         reserved_at_40[0x8];
6881 6882
	u8         tirn[0x18];

6883
	u8         reserved_at_60[0x20];
6884 6885 6886 6887
};

struct mlx5_ifc_create_tir_in_bits {
	u8         opcode[0x10];
6888
	u8         uid[0x10];
6889

6890
	u8         reserved_at_20[0x10];
6891 6892
	u8         op_mod[0x10];

6893
	u8         reserved_at_40[0xc0];
6894 6895 6896 6897 6898 6899

	struct mlx5_ifc_tirc_bits ctx;
};

struct mlx5_ifc_create_srq_out_bits {
	u8         status[0x8];
6900
	u8         reserved_at_8[0x18];
6901 6902 6903

	u8         syndrome[0x20];

6904
	u8         reserved_at_40[0x8];
6905 6906
	u8         srqn[0x18];

6907
	u8         reserved_at_60[0x20];
6908 6909 6910 6911
};

struct mlx5_ifc_create_srq_in_bits {
	u8         opcode[0x10];
6912
	u8         uid[0x10];
6913

6914
	u8         reserved_at_20[0x10];
6915 6916
	u8         op_mod[0x10];

6917
	u8         reserved_at_40[0x40];
6918 6919 6920

	struct mlx5_ifc_srqc_bits srq_context_entry;

6921
	u8         reserved_at_280[0x600];
6922 6923 6924 6925 6926 6927

	u8         pas[0][0x40];
};

struct mlx5_ifc_create_sq_out_bits {
	u8         status[0x8];
6928
	u8         reserved_at_8[0x18];
6929 6930 6931

	u8         syndrome[0x20];

6932
	u8         reserved_at_40[0x8];
6933 6934
	u8         sqn[0x18];

6935
	u8         reserved_at_60[0x20];
6936 6937 6938 6939
};

struct mlx5_ifc_create_sq_in_bits {
	u8         opcode[0x10];
6940
	u8         uid[0x10];
6941

6942
	u8         reserved_at_20[0x10];
6943 6944
	u8         op_mod[0x10];

6945
	u8         reserved_at_40[0xc0];
6946 6947 6948 6949

	struct mlx5_ifc_sqc_bits ctx;
};

6950 6951 6952 6953 6954 6955 6956 6957 6958 6959 6960 6961 6962 6963 6964 6965 6966 6967 6968 6969 6970 6971 6972 6973 6974 6975 6976 6977 6978 6979
struct mlx5_ifc_create_scheduling_element_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];

	u8         scheduling_element_id[0x20];

	u8         reserved_at_a0[0x160];
};

struct mlx5_ifc_create_scheduling_element_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         scheduling_hierarchy[0x8];
	u8         reserved_at_48[0x18];

	u8         reserved_at_60[0xa0];

	struct mlx5_ifc_scheduling_context_bits scheduling_context;

	u8         reserved_at_300[0x100];
};

6980 6981
struct mlx5_ifc_create_rqt_out_bits {
	u8         status[0x8];
6982
	u8         reserved_at_8[0x18];
6983 6984 6985

	u8         syndrome[0x20];

6986
	u8         reserved_at_40[0x8];
6987 6988
	u8         rqtn[0x18];

6989
	u8         reserved_at_60[0x20];
6990 6991 6992 6993
};

struct mlx5_ifc_create_rqt_in_bits {
	u8         opcode[0x10];
6994
	u8         uid[0x10];
6995

6996
	u8         reserved_at_20[0x10];
6997 6998
	u8         op_mod[0x10];

6999
	u8         reserved_at_40[0xc0];
7000 7001 7002 7003 7004 7005

	struct mlx5_ifc_rqtc_bits rqt_context;
};

struct mlx5_ifc_create_rq_out_bits {
	u8         status[0x8];
7006
	u8         reserved_at_8[0x18];
7007 7008 7009

	u8         syndrome[0x20];

7010
	u8         reserved_at_40[0x8];
7011 7012
	u8         rqn[0x18];

7013
	u8         reserved_at_60[0x20];
7014 7015 7016 7017
};

struct mlx5_ifc_create_rq_in_bits {
	u8         opcode[0x10];
7018
	u8         uid[0x10];
7019

7020
	u8         reserved_at_20[0x10];
7021 7022
	u8         op_mod[0x10];

7023
	u8         reserved_at_40[0xc0];
7024 7025 7026 7027 7028 7029

	struct mlx5_ifc_rqc_bits ctx;
};

struct mlx5_ifc_create_rmp_out_bits {
	u8         status[0x8];
7030
	u8         reserved_at_8[0x18];
7031 7032 7033

	u8         syndrome[0x20];

7034
	u8         reserved_at_40[0x8];
7035 7036
	u8         rmpn[0x18];

7037
	u8         reserved_at_60[0x20];
7038 7039 7040 7041
};

struct mlx5_ifc_create_rmp_in_bits {
	u8         opcode[0x10];
7042
	u8         uid[0x10];
7043

7044
	u8         reserved_at_20[0x10];
7045 7046
	u8         op_mod[0x10];

7047
	u8         reserved_at_40[0xc0];
7048 7049 7050 7051 7052 7053

	struct mlx5_ifc_rmpc_bits ctx;
};

struct mlx5_ifc_create_qp_out_bits {
	u8         status[0x8];
7054
	u8         reserved_at_8[0x18];
7055 7056 7057

	u8         syndrome[0x20];

7058
	u8         reserved_at_40[0x8];
7059 7060
	u8         qpn[0x18];

7061
	u8         reserved_at_60[0x20];
7062 7063 7064 7065
};

struct mlx5_ifc_create_qp_in_bits {
	u8         opcode[0x10];
7066
	u8         uid[0x10];
7067

7068
	u8         reserved_at_20[0x10];
7069 7070
	u8         op_mod[0x10];

7071
	u8         reserved_at_40[0x40];
7072 7073 7074

	u8         opt_param_mask[0x20];

7075
	u8         reserved_at_a0[0x20];
7076 7077 7078

	struct mlx5_ifc_qpc_bits qpc;

7079 7080 7081 7082
	u8         reserved_at_800[0x60];

	u8         wq_umem_valid[0x1];
	u8         reserved_at_861[0x1f];
7083 7084 7085 7086 7087 7088

	u8         pas[0][0x40];
};

struct mlx5_ifc_create_psv_out_bits {
	u8         status[0x8];
7089
	u8         reserved_at_8[0x18];
7090 7091 7092

	u8         syndrome[0x20];

7093
	u8         reserved_at_40[0x40];
7094

7095
	u8         reserved_at_80[0x8];
7096 7097
	u8         psv0_index[0x18];

7098
	u8         reserved_at_a0[0x8];
7099 7100
	u8         psv1_index[0x18];

7101
	u8         reserved_at_c0[0x8];
7102 7103
	u8         psv2_index[0x18];

7104
	u8         reserved_at_e0[0x8];
7105 7106 7107 7108 7109
	u8         psv3_index[0x18];
};

struct mlx5_ifc_create_psv_in_bits {
	u8         opcode[0x10];
7110
	u8         reserved_at_10[0x10];
7111

7112
	u8         reserved_at_20[0x10];
7113 7114 7115
	u8         op_mod[0x10];

	u8         num_psv[0x4];
7116
	u8         reserved_at_44[0x4];
7117 7118
	u8         pd[0x18];

7119
	u8         reserved_at_60[0x20];
7120 7121 7122 7123
};

struct mlx5_ifc_create_mkey_out_bits {
	u8         status[0x8];
7124
	u8         reserved_at_8[0x18];
7125 7126 7127

	u8         syndrome[0x20];

7128
	u8         reserved_at_40[0x8];
7129 7130
	u8         mkey_index[0x18];

7131
	u8         reserved_at_60[0x20];
7132 7133 7134 7135
};

struct mlx5_ifc_create_mkey_in_bits {
	u8         opcode[0x10];
7136
	u8         reserved_at_10[0x10];
7137

7138
	u8         reserved_at_20[0x10];
7139 7140
	u8         op_mod[0x10];

7141
	u8         reserved_at_40[0x20];
7142 7143

	u8         pg_access[0x1];
7144 7145
	u8         mkey_umem_valid[0x1];
	u8         reserved_at_62[0x1e];
7146 7147 7148

	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;

7149
	u8         reserved_at_280[0x80];
7150 7151 7152

	u8         translations_octword_actual_size[0x20];

7153
	u8         reserved_at_320[0x560];
7154 7155 7156 7157 7158 7159

	u8         klm_pas_mtt[0][0x20];
};

struct mlx5_ifc_create_flow_table_out_bits {
	u8         status[0x8];
7160
	u8         reserved_at_8[0x18];
7161 7162 7163

	u8         syndrome[0x20];

7164
	u8         reserved_at_40[0x8];
7165 7166
	u8         table_id[0x18];

7167
	u8         reserved_at_60[0x20];
7168 7169
};

7170
struct mlx5_ifc_flow_table_context_bits {
7171
	u8         reformat_en[0x1];
7172 7173 7174 7175 7176 7177 7178 7179 7180 7181 7182 7183 7184 7185 7186 7187
	u8         decap_en[0x1];
	u8         reserved_at_2[0x2];
	u8         table_miss_action[0x4];
	u8         level[0x8];
	u8         reserved_at_10[0x8];
	u8         log_size[0x8];

	u8         reserved_at_20[0x8];
	u8         table_miss_id[0x18];

	u8         reserved_at_40[0x8];
	u8         lag_master_next_table_id[0x18];

	u8         reserved_at_60[0xe0];
};

7188 7189
struct mlx5_ifc_create_flow_table_in_bits {
	u8         opcode[0x10];
7190
	u8         reserved_at_10[0x10];
7191

7192
	u8         reserved_at_20[0x10];
7193 7194
	u8         op_mod[0x10];

7195 7196 7197 7198 7199
	u8         other_vport[0x1];
	u8         reserved_at_41[0xf];
	u8         vport_number[0x10];

	u8         reserved_at_60[0x20];
7200 7201

	u8         table_type[0x8];
7202
	u8         reserved_at_88[0x18];
7203

7204
	u8         reserved_at_a0[0x20];
7205

7206
	struct mlx5_ifc_flow_table_context_bits flow_table_context;
7207 7208 7209 7210
};

struct mlx5_ifc_create_flow_group_out_bits {
	u8         status[0x8];
7211
	u8         reserved_at_8[0x18];
7212 7213 7214

	u8         syndrome[0x20];

7215
	u8         reserved_at_40[0x8];
7216 7217
	u8         group_id[0x18];

7218
	u8         reserved_at_60[0x20];
7219 7220 7221
};

enum {
7222 7223 7224 7225
	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7226 7227 7228 7229
};

struct mlx5_ifc_create_flow_group_in_bits {
	u8         opcode[0x10];
7230
	u8         reserved_at_10[0x10];
7231

7232
	u8         reserved_at_20[0x10];
7233 7234
	u8         op_mod[0x10];

7235 7236 7237 7238 7239
	u8         other_vport[0x1];
	u8         reserved_at_41[0xf];
	u8         vport_number[0x10];

	u8         reserved_at_60[0x20];
7240 7241

	u8         table_type[0x8];
7242
	u8         reserved_at_88[0x18];
7243

7244
	u8         reserved_at_a0[0x8];
7245 7246
	u8         table_id[0x18];

7247 7248 7249
	u8         source_eswitch_owner_vhca_id_valid[0x1];

	u8         reserved_at_c1[0x1f];
7250 7251 7252

	u8         start_flow_index[0x20];

7253
	u8         reserved_at_100[0x20];
7254 7255 7256

	u8         end_flow_index[0x20];

7257
	u8         reserved_at_140[0xa0];
7258

7259
	u8         reserved_at_1e0[0x18];
7260 7261 7262 7263
	u8         match_criteria_enable[0x8];

	struct mlx5_ifc_fte_match_param_bits match_criteria;

7264
	u8         reserved_at_1200[0xe00];
7265 7266 7267 7268
};

struct mlx5_ifc_create_eq_out_bits {
	u8         status[0x8];
7269
	u8         reserved_at_8[0x18];
7270 7271 7272

	u8         syndrome[0x20];

7273
	u8         reserved_at_40[0x18];
7274 7275
	u8         eq_number[0x8];

7276
	u8         reserved_at_60[0x20];
7277 7278 7279 7280
};

struct mlx5_ifc_create_eq_in_bits {
	u8         opcode[0x10];
7281
	u8         reserved_at_10[0x10];
7282

7283
	u8         reserved_at_20[0x10];
7284 7285
	u8         op_mod[0x10];

7286
	u8         reserved_at_40[0x40];
7287 7288 7289

	struct mlx5_ifc_eqc_bits eq_context_entry;

7290
	u8         reserved_at_280[0x40];
7291 7292 7293

	u8         event_bitmask[0x40];

7294
	u8         reserved_at_300[0x580];
7295 7296 7297 7298 7299 7300

	u8         pas[0][0x40];
};

struct mlx5_ifc_create_dct_out_bits {
	u8         status[0x8];
7301
	u8         reserved_at_8[0x18];
7302 7303 7304

	u8         syndrome[0x20];

7305
	u8         reserved_at_40[0x8];
7306 7307
	u8         dctn[0x18];

7308
	u8         reserved_at_60[0x20];
7309 7310 7311 7312
};

struct mlx5_ifc_create_dct_in_bits {
	u8         opcode[0x10];
7313
	u8         uid[0x10];
7314

7315
	u8         reserved_at_20[0x10];
7316 7317
	u8         op_mod[0x10];

7318
	u8         reserved_at_40[0x40];
7319 7320 7321

	struct mlx5_ifc_dctc_bits dct_context_entry;

7322
	u8         reserved_at_280[0x180];
7323 7324 7325 7326
};

struct mlx5_ifc_create_cq_out_bits {
	u8         status[0x8];
7327
	u8         reserved_at_8[0x18];
7328 7329 7330

	u8         syndrome[0x20];

7331
	u8         reserved_at_40[0x8];
7332 7333
	u8         cqn[0x18];

7334
	u8         reserved_at_60[0x20];
7335 7336 7337 7338
};

struct mlx5_ifc_create_cq_in_bits {
	u8         opcode[0x10];
7339
	u8         uid[0x10];
7340

7341
	u8         reserved_at_20[0x10];
7342 7343
	u8         op_mod[0x10];

7344
	u8         reserved_at_40[0x40];
7345 7346 7347

	struct mlx5_ifc_cqc_bits cq_context;

7348 7349 7350 7351
	u8         reserved_at_280[0x60];

	u8         cq_umem_valid[0x1];
	u8         reserved_at_2e1[0x59f];
7352 7353 7354 7355 7356 7357

	u8         pas[0][0x40];
};

struct mlx5_ifc_config_int_moderation_out_bits {
	u8         status[0x8];
7358
	u8         reserved_at_8[0x18];
7359 7360 7361

	u8         syndrome[0x20];

7362
	u8         reserved_at_40[0x4];
7363 7364 7365
	u8         min_delay[0xc];
	u8         int_vector[0x10];

7366
	u8         reserved_at_60[0x20];
7367 7368 7369 7370 7371 7372 7373 7374 7375
};

enum {
	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
};

struct mlx5_ifc_config_int_moderation_in_bits {
	u8         opcode[0x10];
7376
	u8         reserved_at_10[0x10];
7377

7378
	u8         reserved_at_20[0x10];
7379 7380
	u8         op_mod[0x10];

7381
	u8         reserved_at_40[0x4];
7382 7383 7384
	u8         min_delay[0xc];
	u8         int_vector[0x10];

7385
	u8         reserved_at_60[0x20];
7386 7387 7388 7389
};

struct mlx5_ifc_attach_to_mcg_out_bits {
	u8         status[0x8];
7390
	u8         reserved_at_8[0x18];
7391 7392 7393

	u8         syndrome[0x20];

7394
	u8         reserved_at_40[0x40];
7395 7396 7397 7398
};

struct mlx5_ifc_attach_to_mcg_in_bits {
	u8         opcode[0x10];
7399
	u8         uid[0x10];
7400

7401
	u8         reserved_at_20[0x10];
7402 7403
	u8         op_mod[0x10];

7404
	u8         reserved_at_40[0x8];
7405 7406
	u8         qpn[0x18];

7407
	u8         reserved_at_60[0x20];
7408 7409 7410 7411

	u8         multicast_gid[16][0x8];
};

7412 7413 7414 7415 7416 7417 7418 7419 7420 7421 7422 7423 7424 7425 7426 7427 7428 7429 7430 7431 7432 7433 7434
struct mlx5_ifc_arm_xrq_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_arm_xrq_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x8];
	u8         xrqn[0x18];

	u8         reserved_at_60[0x10];
	u8         lwm[0x10];
};

7435 7436
struct mlx5_ifc_arm_xrc_srq_out_bits {
	u8         status[0x8];
7437
	u8         reserved_at_8[0x18];
7438 7439 7440

	u8         syndrome[0x20];

7441
	u8         reserved_at_40[0x40];
7442 7443 7444 7445 7446 7447 7448 7449
};

enum {
	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
};

struct mlx5_ifc_arm_xrc_srq_in_bits {
	u8         opcode[0x10];
7450
	u8         uid[0x10];
7451

7452
	u8         reserved_at_20[0x10];
7453 7454
	u8         op_mod[0x10];

7455
	u8         reserved_at_40[0x8];
7456 7457
	u8         xrc_srqn[0x18];

7458
	u8         reserved_at_60[0x10];
7459 7460 7461 7462 7463
	u8         lwm[0x10];
};

struct mlx5_ifc_arm_rq_out_bits {
	u8         status[0x8];
7464
	u8         reserved_at_8[0x18];
7465 7466 7467

	u8         syndrome[0x20];

7468
	u8         reserved_at_40[0x40];
7469 7470 7471
};

enum {
7472 7473
	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7474 7475 7476 7477
};

struct mlx5_ifc_arm_rq_in_bits {
	u8         opcode[0x10];
7478
	u8         uid[0x10];
7479

7480
	u8         reserved_at_20[0x10];
7481 7482
	u8         op_mod[0x10];

7483
	u8         reserved_at_40[0x8];
7484 7485
	u8         srq_number[0x18];

7486
	u8         reserved_at_60[0x10];
7487 7488 7489 7490 7491
	u8         lwm[0x10];
};

struct mlx5_ifc_arm_dct_out_bits {
	u8         status[0x8];
7492
	u8         reserved_at_8[0x18];
7493 7494 7495

	u8         syndrome[0x20];

7496
	u8         reserved_at_40[0x40];
7497 7498 7499 7500
};

struct mlx5_ifc_arm_dct_in_bits {
	u8         opcode[0x10];
7501
	u8         reserved_at_10[0x10];
7502

7503
	u8         reserved_at_20[0x10];
7504 7505
	u8         op_mod[0x10];

7506
	u8         reserved_at_40[0x8];
7507 7508
	u8         dct_number[0x18];

7509
	u8         reserved_at_60[0x20];
7510 7511 7512 7513
};

struct mlx5_ifc_alloc_xrcd_out_bits {
	u8         status[0x8];
7514
	u8         reserved_at_8[0x18];
7515 7516 7517

	u8         syndrome[0x20];

7518
	u8         reserved_at_40[0x8];
7519 7520
	u8         xrcd[0x18];

7521
	u8         reserved_at_60[0x20];
7522 7523 7524 7525
};

struct mlx5_ifc_alloc_xrcd_in_bits {
	u8         opcode[0x10];
7526
	u8         uid[0x10];
7527

7528
	u8         reserved_at_20[0x10];
7529 7530
	u8         op_mod[0x10];

7531
	u8         reserved_at_40[0x40];
7532 7533 7534 7535
};

struct mlx5_ifc_alloc_uar_out_bits {
	u8         status[0x8];
7536
	u8         reserved_at_8[0x18];
7537 7538 7539

	u8         syndrome[0x20];

7540
	u8         reserved_at_40[0x8];
7541 7542
	u8         uar[0x18];

7543
	u8         reserved_at_60[0x20];
7544 7545 7546 7547
};

struct mlx5_ifc_alloc_uar_in_bits {
	u8         opcode[0x10];
7548
	u8         reserved_at_10[0x10];
7549

7550
	u8         reserved_at_20[0x10];
7551 7552
	u8         op_mod[0x10];

7553
	u8         reserved_at_40[0x40];
7554 7555 7556 7557
};

struct mlx5_ifc_alloc_transport_domain_out_bits {
	u8         status[0x8];
7558
	u8         reserved_at_8[0x18];
7559 7560 7561

	u8         syndrome[0x20];

7562
	u8         reserved_at_40[0x8];
7563 7564
	u8         transport_domain[0x18];

7565
	u8         reserved_at_60[0x20];
7566 7567 7568 7569
};

struct mlx5_ifc_alloc_transport_domain_in_bits {
	u8         opcode[0x10];
7570
	u8         uid[0x10];
7571

7572
	u8         reserved_at_20[0x10];
7573 7574
	u8         op_mod[0x10];

7575
	u8         reserved_at_40[0x40];
7576 7577 7578 7579
};

struct mlx5_ifc_alloc_q_counter_out_bits {
	u8         status[0x8];
7580
	u8         reserved_at_8[0x18];
7581 7582 7583

	u8         syndrome[0x20];

7584
	u8         reserved_at_40[0x18];
7585 7586
	u8         counter_set_id[0x8];

7587
	u8         reserved_at_60[0x20];
7588 7589 7590 7591
};

struct mlx5_ifc_alloc_q_counter_in_bits {
	u8         opcode[0x10];
7592
	u8         uid[0x10];
7593

7594
	u8         reserved_at_20[0x10];
7595 7596
	u8         op_mod[0x10];

7597
	u8         reserved_at_40[0x40];
7598 7599 7600 7601
};

struct mlx5_ifc_alloc_pd_out_bits {
	u8         status[0x8];
7602
	u8         reserved_at_8[0x18];
7603 7604 7605

	u8         syndrome[0x20];

7606
	u8         reserved_at_40[0x8];
7607 7608
	u8         pd[0x18];

7609
	u8         reserved_at_60[0x20];
7610 7611 7612
};

struct mlx5_ifc_alloc_pd_in_bits {
7613
	u8         opcode[0x10];
7614
	u8         uid[0x10];
7615 7616 7617 7618 7619 7620 7621 7622 7623 7624 7625 7626 7627

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_alloc_flow_counter_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

7628
	u8         flow_counter_id[0x20];
7629 7630 7631 7632 7633

	u8         reserved_at_60[0x20];
};

struct mlx5_ifc_alloc_flow_counter_in_bits {
7634
	u8         opcode[0x10];
7635
	u8         reserved_at_10[0x10];
7636

7637
	u8         reserved_at_20[0x10];
7638 7639
	u8         op_mod[0x10];

7640
	u8         reserved_at_40[0x40];
7641 7642 7643 7644
};

struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
	u8         status[0x8];
7645
	u8         reserved_at_8[0x18];
7646 7647 7648

	u8         syndrome[0x20];

7649
	u8         reserved_at_40[0x40];
7650 7651 7652 7653
};

struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
	u8         opcode[0x10];
7654
	u8         reserved_at_10[0x10];
7655

7656
	u8         reserved_at_20[0x10];
7657 7658
	u8         op_mod[0x10];

7659
	u8         reserved_at_40[0x20];
7660

7661
	u8         reserved_at_60[0x10];
7662 7663 7664
	u8         vxlan_udp_port[0x10];
};

7665
struct mlx5_ifc_set_pp_rate_limit_out_bits {
7666 7667 7668 7669 7670 7671 7672 7673
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

7674
struct mlx5_ifc_set_pp_rate_limit_in_bits {
7675 7676 7677 7678 7679 7680 7681 7682 7683 7684 7685 7686
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x10];
	u8         rate_limit_index[0x10];

	u8         reserved_at_60[0x20];

	u8         rate_limit[0x20];
7687

7688 7689 7690 7691 7692 7693
	u8	   burst_upper_bound[0x20];

	u8         reserved_at_c0[0x10];
	u8	   typical_packet_size[0x10];

	u8         reserved_at_e0[0x120];
7694 7695
};

7696 7697
struct mlx5_ifc_access_register_out_bits {
	u8         status[0x8];
7698
	u8         reserved_at_8[0x18];
7699 7700 7701

	u8         syndrome[0x20];

7702
	u8         reserved_at_40[0x40];
7703 7704 7705 7706 7707 7708 7709 7710 7711 7712 7713

	u8         register_data[0][0x20];
};

enum {
	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
};

struct mlx5_ifc_access_register_in_bits {
	u8         opcode[0x10];
7714
	u8         reserved_at_10[0x10];
7715

7716
	u8         reserved_at_20[0x10];
7717 7718
	u8         op_mod[0x10];

7719
	u8         reserved_at_40[0x10];
7720 7721 7722 7723 7724 7725 7726 7727 7728 7729 7730 7731
	u8         register_id[0x10];

	u8         argument[0x20];

	u8         register_data[0][0x20];
};

struct mlx5_ifc_sltp_reg_bits {
	u8         status[0x4];
	u8         version[0x4];
	u8         local_port[0x8];
	u8         pnat[0x2];
7732
	u8         reserved_at_12[0x2];
7733
	u8         lane[0x4];
7734
	u8         reserved_at_18[0x8];
7735

7736
	u8         reserved_at_20[0x20];
7737

7738
	u8         reserved_at_40[0x7];
7739 7740 7741 7742 7743
	u8         polarity[0x1];
	u8         ob_tap0[0x8];
	u8         ob_tap1[0x8];
	u8         ob_tap2[0x8];

7744
	u8         reserved_at_60[0xc];
7745 7746 7747 7748
	u8         ob_preemp_mode[0x4];
	u8         ob_reg[0x8];
	u8         ob_bias[0x8];

7749
	u8         reserved_at_80[0x20];
7750 7751 7752 7753 7754 7755 7756
};

struct mlx5_ifc_slrg_reg_bits {
	u8         status[0x4];
	u8         version[0x4];
	u8         local_port[0x8];
	u8         pnat[0x2];
7757
	u8         reserved_at_12[0x2];
7758
	u8         lane[0x4];
7759
	u8         reserved_at_18[0x8];
7760 7761

	u8         time_to_link_up[0x10];
7762
	u8         reserved_at_30[0xc];
7763 7764 7765 7766 7767
	u8         grade_lane_speed[0x4];

	u8         grade_version[0x8];
	u8         grade[0x18];

7768
	u8         reserved_at_60[0x4];
7769 7770 7771 7772 7773 7774
	u8         height_grade_type[0x4];
	u8         height_grade[0x18];

	u8         height_dz[0x10];
	u8         height_dv[0x10];

7775
	u8         reserved_at_a0[0x10];
7776 7777
	u8         height_sigma[0x10];

7778
	u8         reserved_at_c0[0x20];
7779

7780
	u8         reserved_at_e0[0x4];
7781 7782 7783
	u8         phase_grade_type[0x4];
	u8         phase_grade[0x18];

7784
	u8         reserved_at_100[0x8];
7785
	u8         phase_eo_pos[0x8];
7786
	u8         reserved_at_110[0x8];
7787 7788 7789 7790 7791 7792 7793
	u8         phase_eo_neg[0x8];

	u8         ffe_set_tested[0x10];
	u8         test_errors_per_lane[0x10];
};

struct mlx5_ifc_pvlc_reg_bits {
7794
	u8         reserved_at_0[0x8];
7795
	u8         local_port[0x8];
7796
	u8         reserved_at_10[0x10];
7797

7798
	u8         reserved_at_20[0x1c];
7799 7800
	u8         vl_hw_cap[0x4];

7801
	u8         reserved_at_40[0x1c];
7802 7803
	u8         vl_admin[0x4];

7804
	u8         reserved_at_60[0x1c];
7805 7806 7807 7808 7809 7810
	u8         vl_operational[0x4];
};

struct mlx5_ifc_pude_reg_bits {
	u8         swid[0x8];
	u8         local_port[0x8];
7811
	u8         reserved_at_10[0x4];
7812
	u8         admin_status[0x4];
7813
	u8         reserved_at_18[0x4];
7814 7815
	u8         oper_status[0x4];

7816
	u8         reserved_at_20[0x60];
7817 7818 7819
};

struct mlx5_ifc_ptys_reg_bits {
7820
	u8         reserved_at_0[0x1];
7821
	u8         an_disable_admin[0x1];
7822 7823
	u8         an_disable_cap[0x1];
	u8         reserved_at_3[0x5];
7824
	u8         local_port[0x8];
7825
	u8         reserved_at_10[0xd];
7826 7827
	u8         proto_mask[0x3];

7828
	u8         an_status[0x4];
7829 7830 7831
	u8         reserved_at_24[0x1c];

	u8         ext_eth_proto_capability[0x20];
7832 7833 7834 7835 7836 7837

	u8         eth_proto_capability[0x20];

	u8         ib_link_width_capability[0x10];
	u8         ib_proto_capability[0x10];

7838
	u8         ext_eth_proto_admin[0x20];
7839 7840 7841 7842 7843 7844

	u8         eth_proto_admin[0x20];

	u8         ib_link_width_admin[0x10];
	u8         ib_proto_admin[0x10];

7845
	u8         ext_eth_proto_oper[0x20];
7846 7847 7848 7849 7850 7851

	u8         eth_proto_oper[0x20];

	u8         ib_link_width_oper[0x10];
	u8         ib_proto_oper[0x10];

7852 7853
	u8         reserved_at_160[0x1c];
	u8         connector_type[0x4];
7854 7855 7856

	u8         eth_proto_lp_advertise[0x20];

7857
	u8         reserved_at_1a0[0x60];
7858 7859
};

7860 7861 7862 7863 7864 7865 7866 7867 7868 7869 7870
struct mlx5_ifc_mlcr_reg_bits {
	u8         reserved_at_0[0x8];
	u8         local_port[0x8];
	u8         reserved_at_10[0x20];

	u8         beacon_duration[0x10];
	u8         reserved_at_40[0x10];

	u8         beacon_remain[0x10];
};

7871
struct mlx5_ifc_ptas_reg_bits {
7872
	u8         reserved_at_0[0x20];
7873 7874

	u8         algorithm_options[0x10];
7875
	u8         reserved_at_30[0x4];
7876 7877 7878 7879 7880 7881 7882 7883 7884 7885 7886 7887 7888 7889 7890 7891 7892 7893 7894 7895 7896 7897 7898 7899 7900
	u8         repetitions_mode[0x4];
	u8         num_of_repetitions[0x8];

	u8         grade_version[0x8];
	u8         height_grade_type[0x4];
	u8         phase_grade_type[0x4];
	u8         height_grade_weight[0x8];
	u8         phase_grade_weight[0x8];

	u8         gisim_measure_bits[0x10];
	u8         adaptive_tap_measure_bits[0x10];

	u8         ber_bath_high_error_threshold[0x10];
	u8         ber_bath_mid_error_threshold[0x10];

	u8         ber_bath_low_error_threshold[0x10];
	u8         one_ratio_high_threshold[0x10];

	u8         one_ratio_high_mid_threshold[0x10];
	u8         one_ratio_low_mid_threshold[0x10];

	u8         one_ratio_low_threshold[0x10];
	u8         ndeo_error_threshold[0x10];

	u8         mixer_offset_step_size[0x10];
7901
	u8         reserved_at_110[0x8];
7902 7903 7904 7905 7906
	u8         mix90_phase_for_voltage_bath[0x8];

	u8         mixer_offset_start[0x10];
	u8         mixer_offset_end[0x10];

7907
	u8         reserved_at_140[0x15];
7908 7909 7910 7911 7912 7913 7914
	u8         ber_test_time[0xb];
};

struct mlx5_ifc_pspa_reg_bits {
	u8         swid[0x8];
	u8         local_port[0x8];
	u8         sub_port[0x8];
7915
	u8         reserved_at_18[0x8];
7916

7917
	u8         reserved_at_20[0x20];
7918 7919 7920
};

struct mlx5_ifc_pqdr_reg_bits {
7921
	u8         reserved_at_0[0x8];
7922
	u8         local_port[0x8];
7923
	u8         reserved_at_10[0x5];
7924
	u8         prio[0x3];
7925
	u8         reserved_at_18[0x6];
7926 7927
	u8         mode[0x2];

7928
	u8         reserved_at_20[0x20];
7929

7930
	u8         reserved_at_40[0x10];
7931 7932
	u8         min_threshold[0x10];

7933
	u8         reserved_at_60[0x10];
7934 7935
	u8         max_threshold[0x10];

7936
	u8         reserved_at_80[0x10];
7937 7938
	u8         mark_probability_denominator[0x10];

7939
	u8         reserved_at_a0[0x60];
7940 7941 7942
};

struct mlx5_ifc_ppsc_reg_bits {
7943
	u8         reserved_at_0[0x8];
7944
	u8         local_port[0x8];
7945
	u8         reserved_at_10[0x10];
7946

7947
	u8         reserved_at_20[0x60];
7948

7949
	u8         reserved_at_80[0x1c];
7950 7951
	u8         wrps_admin[0x4];

7952
	u8         reserved_at_a0[0x1c];
7953 7954
	u8         wrps_status[0x4];

7955
	u8         reserved_at_c0[0x8];
7956
	u8         up_threshold[0x8];
7957
	u8         reserved_at_d0[0x8];
7958 7959
	u8         down_threshold[0x8];

7960
	u8         reserved_at_e0[0x20];
7961

7962
	u8         reserved_at_100[0x1c];
7963 7964
	u8         srps_admin[0x4];

7965
	u8         reserved_at_120[0x1c];
7966 7967
	u8         srps_status[0x4];

7968
	u8         reserved_at_140[0x40];
7969 7970 7971
};

struct mlx5_ifc_pplr_reg_bits {
7972
	u8         reserved_at_0[0x8];
7973
	u8         local_port[0x8];
7974
	u8         reserved_at_10[0x10];
7975

7976
	u8         reserved_at_20[0x8];
7977
	u8         lb_cap[0x8];
7978
	u8         reserved_at_30[0x8];
7979 7980 7981 7982
	u8         lb_en[0x8];
};

struct mlx5_ifc_pplm_reg_bits {
7983
	u8         reserved_at_0[0x8];
7984 7985
	u8	   local_port[0x8];
	u8	   reserved_at_10[0x10];
7986

7987
	u8	   reserved_at_20[0x20];
7988

7989 7990 7991 7992
	u8	   port_profile_mode[0x8];
	u8	   static_port_profile[0x8];
	u8	   active_port_profile[0x8];
	u8	   reserved_at_58[0x8];
7993

7994 7995
	u8	   retransmission_active[0x8];
	u8	   fec_mode_active[0x18];
7996

7997 7998 7999 8000 8001 8002 8003 8004 8005 8006 8007 8008 8009 8010 8011
	u8	   rs_fec_correction_bypass_cap[0x4];
	u8	   reserved_at_84[0x8];
	u8	   fec_override_cap_56g[0x4];
	u8	   fec_override_cap_100g[0x4];
	u8	   fec_override_cap_50g[0x4];
	u8	   fec_override_cap_25g[0x4];
	u8	   fec_override_cap_10g_40g[0x4];

	u8	   rs_fec_correction_bypass_admin[0x4];
	u8	   reserved_at_a4[0x8];
	u8	   fec_override_admin_56g[0x4];
	u8	   fec_override_admin_100g[0x4];
	u8	   fec_override_admin_50g[0x4];
	u8	   fec_override_admin_25g[0x4];
	u8	   fec_override_admin_10g_40g[0x4];
8012 8013 8014 8015 8016 8017
};

struct mlx5_ifc_ppcnt_reg_bits {
	u8         swid[0x8];
	u8         local_port[0x8];
	u8         pnat[0x2];
8018
	u8         reserved_at_12[0x8];
8019 8020 8021
	u8         grp[0x6];

	u8         clr[0x1];
8022
	u8         reserved_at_21[0x1c];
8023 8024 8025 8026 8027
	u8         prio_tc[0x3];

	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
};

8028 8029 8030 8031 8032 8033 8034 8035 8036 8037 8038 8039
struct mlx5_ifc_mpcnt_reg_bits {
	u8         reserved_at_0[0x8];
	u8         pcie_index[0x8];
	u8         reserved_at_10[0xa];
	u8         grp[0x6];

	u8         clr[0x1];
	u8         reserved_at_21[0x1f];

	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
};

8040
struct mlx5_ifc_ppad_reg_bits {
8041
	u8         reserved_at_0[0x3];
8042
	u8         single_mac[0x1];
8043
	u8         reserved_at_4[0x4];
8044 8045 8046 8047 8048
	u8         local_port[0x8];
	u8         mac_47_32[0x10];

	u8         mac_31_0[0x20];

8049
	u8         reserved_at_40[0x40];
8050 8051 8052
};

struct mlx5_ifc_pmtu_reg_bits {
8053
	u8         reserved_at_0[0x8];
8054
	u8         local_port[0x8];
8055
	u8         reserved_at_10[0x10];
8056 8057

	u8         max_mtu[0x10];
8058
	u8         reserved_at_30[0x10];
8059 8060

	u8         admin_mtu[0x10];
8061
	u8         reserved_at_50[0x10];
8062 8063

	u8         oper_mtu[0x10];
8064
	u8         reserved_at_70[0x10];
8065 8066 8067
};

struct mlx5_ifc_pmpr_reg_bits {
8068
	u8         reserved_at_0[0x8];
8069
	u8         module[0x8];
8070
	u8         reserved_at_10[0x10];
8071

8072
	u8         reserved_at_20[0x18];
8073 8074
	u8         attenuation_5g[0x8];

8075
	u8         reserved_at_40[0x18];
8076 8077
	u8         attenuation_7g[0x8];

8078
	u8         reserved_at_60[0x18];
8079 8080 8081 8082
	u8         attenuation_12g[0x8];
};

struct mlx5_ifc_pmpe_reg_bits {
8083
	u8         reserved_at_0[0x8];
8084
	u8         module[0x8];
8085
	u8         reserved_at_10[0xc];
8086 8087
	u8         module_status[0x4];

8088
	u8         reserved_at_20[0x60];
8089 8090 8091 8092 8093 8094 8095
};

struct mlx5_ifc_pmpc_reg_bits {
	u8         module_state_updated[32][0x8];
};

struct mlx5_ifc_pmlpn_reg_bits {
8096
	u8         reserved_at_0[0x4];
8097 8098
	u8         mlpn_status[0x4];
	u8         local_port[0x8];
8099
	u8         reserved_at_10[0x10];
8100 8101

	u8         e[0x1];
8102
	u8         reserved_at_21[0x1f];
8103 8104 8105 8106
};

struct mlx5_ifc_pmlp_reg_bits {
	u8         rxtx[0x1];
8107
	u8         reserved_at_1[0x7];
8108
	u8         local_port[0x8];
8109
	u8         reserved_at_10[0x8];
8110 8111 8112 8113 8114 8115 8116 8117 8118 8119
	u8         width[0x8];

	u8         lane0_module_mapping[0x20];

	u8         lane1_module_mapping[0x20];

	u8         lane2_module_mapping[0x20];

	u8         lane3_module_mapping[0x20];

8120
	u8         reserved_at_a0[0x160];
8121 8122 8123
};

struct mlx5_ifc_pmaos_reg_bits {
8124
	u8         reserved_at_0[0x8];
8125
	u8         module[0x8];
8126
	u8         reserved_at_10[0x4];
8127
	u8         admin_status[0x4];
8128
	u8         reserved_at_18[0x4];
8129 8130 8131 8132
	u8         oper_status[0x4];

	u8         ase[0x1];
	u8         ee[0x1];
8133
	u8         reserved_at_22[0x1c];
8134 8135
	u8         e[0x2];

8136
	u8         reserved_at_40[0x40];
8137 8138 8139
};

struct mlx5_ifc_plpc_reg_bits {
8140
	u8         reserved_at_0[0x4];
8141
	u8         profile_id[0xc];
8142
	u8         reserved_at_10[0x4];
8143
	u8         proto_mask[0x4];
8144
	u8         reserved_at_18[0x8];
8145

8146
	u8         reserved_at_20[0x10];
8147 8148
	u8         lane_speed[0x10];

8149
	u8         reserved_at_40[0x17];
8150 8151 8152 8153 8154 8155 8156 8157 8158 8159 8160 8161
	u8         lpbf[0x1];
	u8         fec_mode_policy[0x8];

	u8         retransmission_capability[0x8];
	u8         fec_mode_capability[0x18];

	u8         retransmission_support_admin[0x8];
	u8         fec_mode_support_admin[0x18];

	u8         retransmission_request_admin[0x8];
	u8         fec_mode_request_admin[0x18];

8162
	u8         reserved_at_c0[0x80];
8163 8164 8165
};

struct mlx5_ifc_plib_reg_bits {
8166
	u8         reserved_at_0[0x8];
8167
	u8         local_port[0x8];
8168
	u8         reserved_at_10[0x8];
8169 8170
	u8         ib_port[0x8];

8171
	u8         reserved_at_20[0x60];
8172 8173 8174
};

struct mlx5_ifc_plbf_reg_bits {
8175
	u8         reserved_at_0[0x8];
8176
	u8         local_port[0x8];
8177
	u8         reserved_at_10[0xd];
8178 8179
	u8         lbf_mode[0x3];

8180
	u8         reserved_at_20[0x20];
8181 8182 8183
};

struct mlx5_ifc_pipg_reg_bits {
8184
	u8         reserved_at_0[0x8];
8185
	u8         local_port[0x8];
8186
	u8         reserved_at_10[0x10];
8187 8188

	u8         dic[0x1];
8189
	u8         reserved_at_21[0x19];
8190
	u8         ipg[0x4];
8191
	u8         reserved_at_3e[0x2];
8192 8193 8194
};

struct mlx5_ifc_pifr_reg_bits {
8195
	u8         reserved_at_0[0x8];
8196
	u8         local_port[0x8];
8197
	u8         reserved_at_10[0x10];
8198

8199
	u8         reserved_at_20[0xe0];
8200 8201 8202 8203 8204 8205 8206

	u8         port_filter[8][0x20];

	u8         port_filter_update_en[8][0x20];
};

struct mlx5_ifc_pfcc_reg_bits {
8207
	u8         reserved_at_0[0x8];
8208
	u8         local_port[0x8];
8209 8210 8211 8212 8213
	u8         reserved_at_10[0xb];
	u8         ppan_mask_n[0x1];
	u8         minor_stall_mask[0x1];
	u8         critical_stall_mask[0x1];
	u8         reserved_at_1e[0x2];
8214 8215

	u8         ppan[0x4];
8216
	u8         reserved_at_24[0x4];
8217
	u8         prio_mask_tx[0x8];
8218
	u8         reserved_at_30[0x8];
8219 8220 8221 8222
	u8         prio_mask_rx[0x8];

	u8         pptx[0x1];
	u8         aptx[0x1];
8223 8224
	u8         pptx_mask_n[0x1];
	u8         reserved_at_43[0x5];
8225
	u8         pfctx[0x8];
8226
	u8         reserved_at_50[0x10];
8227 8228 8229

	u8         pprx[0x1];
	u8         aprx[0x1];
8230 8231
	u8         pprx_mask_n[0x1];
	u8         reserved_at_63[0x5];
8232
	u8         pfcrx[0x8];
8233
	u8         reserved_at_70[0x10];
8234

8235 8236 8237 8238
	u8         device_stall_minor_watermark[0x10];
	u8         device_stall_critical_watermark[0x10];

	u8         reserved_at_a0[0x60];
8239 8240 8241 8242
};

struct mlx5_ifc_pelc_reg_bits {
	u8         op[0x4];
8243
	u8         reserved_at_4[0x4];
8244
	u8         local_port[0x8];
8245
	u8         reserved_at_10[0x10];
8246 8247 8248 8249 8250 8251 8252 8253 8254 8255 8256 8257 8258 8259

	u8         op_admin[0x8];
	u8         op_capability[0x8];
	u8         op_request[0x8];
	u8         op_active[0x8];

	u8         admin[0x40];

	u8         capability[0x40];

	u8         request[0x40];

	u8         active[0x40];

8260
	u8         reserved_at_140[0x80];
8261 8262 8263
};

struct mlx5_ifc_peir_reg_bits {
8264
	u8         reserved_at_0[0x8];
8265
	u8         local_port[0x8];
8266
	u8         reserved_at_10[0x10];
8267

8268
	u8         reserved_at_20[0xc];
8269
	u8         error_count[0x4];
8270
	u8         reserved_at_30[0x10];
8271

8272
	u8         reserved_at_40[0xc];
8273
	u8         lane[0x4];
8274
	u8         reserved_at_50[0x8];
8275 8276 8277
	u8         error_type[0x8];
};

8278 8279 8280 8281 8282 8283 8284 8285 8286 8287 8288 8289 8290
struct mlx5_ifc_mpegc_reg_bits {
	u8         reserved_at_0[0x30];
	u8         field_select[0x10];

	u8         tx_overflow_sense[0x1];
	u8         mark_cqe[0x1];
	u8         mark_cnp[0x1];
	u8         reserved_at_43[0x1b];
	u8         tx_lossy_overflow_oper[0x2];

	u8         reserved_at_60[0x100];
};

8291
struct mlx5_ifc_pcam_enhanced_features_bits {
8292 8293
	u8         reserved_at_0[0x6d];
	u8         rx_icrc_encapsulated_counter[0x1];
8294 8295 8296
	u8	   reserved_at_6e[0x4];
	u8         ptys_extended_ethernet[0x1];
	u8	   reserved_at_73[0x3];
8297
	u8         pfcc_mask[0x1];
8298 8299
	u8         reserved_at_77[0x3];
	u8         per_lane_error_counters[0x1];
8300
	u8         rx_buffer_fullness_counters[0x1];
8301 8302
	u8         ptys_connector_type[0x1];
	u8         reserved_at_7d[0x1];
8303 8304 8305 8306
	u8         ppcnt_discard_group[0x1];
	u8         ppcnt_statistical_group[0x1];
};

8307 8308 8309
struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
	u8         port_access_reg_cap_mask_127_to_96[0x20];
	u8         port_access_reg_cap_mask_95_to_64[0x20];
8310 8311 8312 8313

	u8         port_access_reg_cap_mask_63_to_36[0x1c];
	u8         pplm[0x1];
	u8         port_access_reg_cap_mask_34_to_32[0x3];
8314 8315 8316 8317

	u8         port_access_reg_cap_mask_31_to_13[0x13];
	u8         pbmc[0x1];
	u8         pptb[0x1];
8318 8319 8320
	u8         port_access_reg_cap_mask_10_to_09[0x2];
	u8         ppcnt[0x1];
	u8         port_access_reg_cap_mask_07_to_00[0x8];
8321 8322
};

8323 8324 8325 8326 8327 8328 8329 8330 8331
struct mlx5_ifc_pcam_reg_bits {
	u8         reserved_at_0[0x8];
	u8         feature_group[0x8];
	u8         reserved_at_10[0x8];
	u8         access_reg_group[0x8];

	u8         reserved_at_20[0x20];

	union {
8332
		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8333 8334 8335 8336 8337 8338 8339 8340 8341 8342 8343 8344 8345 8346
		u8         reserved_at_0[0x80];
	} port_access_reg_cap_mask;

	u8         reserved_at_c0[0x80];

	union {
		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
		u8         reserved_at_0[0x80];
	} feature_cap_mask;

	u8         reserved_at_1c0[0xc0];
};

struct mlx5_ifc_mcam_enhanced_features_bits {
8347 8348 8349 8350 8351
	u8         reserved_at_0[0x74];
	u8         mark_tx_action_cnp[0x1];
	u8         mark_tx_action_cqe[0x1];
	u8         dynamic_tx_overflow[0x1];
	u8         reserved_at_77[0x4];
8352
	u8         pcie_outbound_stalled[0x1];
8353
	u8         tx_overflow_buffer_pkt[0x1];
8354 8355
	u8         mtpps_enh_out_per_adj[0x1];
	u8         mtpps_fs[0x1];
8356 8357 8358
	u8         pcie_performance_group[0x1];
};

8359 8360 8361 8362 8363 8364 8365
struct mlx5_ifc_mcam_access_reg_bits {
	u8         reserved_at_0[0x1c];
	u8         mcda[0x1];
	u8         mcc[0x1];
	u8         mcqi[0x1];
	u8         reserved_at_1f[0x1];

8366 8367 8368
	u8         regs_95_to_87[0x9];
	u8         mpegc[0x1];
	u8         regs_85_to_68[0x12];
8369 8370
	u8         tracer_registers[0x4];

8371 8372 8373 8374
	u8         regs_63_to_32[0x20];
	u8         regs_31_to_0[0x20];
};

8375 8376 8377 8378 8379 8380 8381 8382 8383
struct mlx5_ifc_mcam_reg_bits {
	u8         reserved_at_0[0x8];
	u8         feature_group[0x8];
	u8         reserved_at_10[0x8];
	u8         access_reg_group[0x8];

	u8         reserved_at_20[0x20];

	union {
8384
		struct mlx5_ifc_mcam_access_reg_bits access_regs;
8385 8386 8387 8388 8389 8390 8391 8392 8393 8394 8395 8396 8397
		u8         reserved_at_0[0x80];
	} mng_access_reg_cap_mask;

	u8         reserved_at_c0[0x80];

	union {
		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
		u8         reserved_at_0[0x80];
	} mng_feature_cap_mask;

	u8         reserved_at_1c0[0x80];
};

8398 8399 8400 8401 8402 8403 8404 8405 8406 8407 8408 8409 8410 8411 8412 8413 8414 8415 8416 8417 8418 8419 8420 8421 8422 8423 8424 8425 8426 8427 8428 8429 8430 8431 8432 8433 8434
struct mlx5_ifc_qcam_access_reg_cap_mask {
	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
	u8         qpdpm[0x1];
	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
	u8         qdpm[0x1];
	u8         qpts[0x1];
	u8         qcap[0x1];
	u8         qcam_access_reg_cap_mask_0[0x1];
};

struct mlx5_ifc_qcam_qos_feature_cap_mask {
	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
	u8         qpts_trust_both[0x1];
};

struct mlx5_ifc_qcam_reg_bits {
	u8         reserved_at_0[0x8];
	u8         feature_group[0x8];
	u8         reserved_at_10[0x8];
	u8         access_reg_group[0x8];
	u8         reserved_at_20[0x20];

	union {
		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
		u8  reserved_at_0[0x80];
	} qos_access_reg_cap_mask;

	u8         reserved_at_c0[0x80];

	union {
		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
		u8  reserved_at_0[0x80];
	} qos_feature_cap_mask;

	u8         reserved_at_1c0[0x80];
};

8435
struct mlx5_ifc_pcap_reg_bits {
8436
	u8         reserved_at_0[0x8];
8437
	u8         local_port[0x8];
8438
	u8         reserved_at_10[0x10];
8439 8440 8441 8442 8443 8444 8445

	u8         port_capability_mask[4][0x20];
};

struct mlx5_ifc_paos_reg_bits {
	u8         swid[0x8];
	u8         local_port[0x8];
8446
	u8         reserved_at_10[0x4];
8447
	u8         admin_status[0x4];
8448
	u8         reserved_at_18[0x4];
8449 8450 8451 8452
	u8         oper_status[0x4];

	u8         ase[0x1];
	u8         ee[0x1];
8453
	u8         reserved_at_22[0x1c];
8454 8455
	u8         e[0x2];

8456
	u8         reserved_at_40[0x40];
8457 8458 8459
};

struct mlx5_ifc_pamp_reg_bits {
8460
	u8         reserved_at_0[0x8];
8461
	u8         opamp_group[0x8];
8462
	u8         reserved_at_10[0xc];
8463 8464 8465
	u8         opamp_group_type[0x4];

	u8         start_index[0x10];
8466
	u8         reserved_at_30[0x4];
8467 8468 8469 8470 8471
	u8         num_of_indices[0xc];

	u8         index_data[18][0x10];
};

8472 8473 8474 8475 8476 8477 8478 8479 8480 8481
struct mlx5_ifc_pcmr_reg_bits {
	u8         reserved_at_0[0x8];
	u8         local_port[0x8];
	u8         reserved_at_10[0x2e];
	u8         fcs_cap[0x1];
	u8         reserved_at_3f[0x1f];
	u8         fcs_chk[0x1];
	u8         reserved_at_5f[0x1];
};

8482
struct mlx5_ifc_lane_2_module_mapping_bits {
8483
	u8         reserved_at_0[0x6];
8484
	u8         rx_lane[0x2];
8485
	u8         reserved_at_8[0x6];
8486
	u8         tx_lane[0x2];
8487
	u8         reserved_at_10[0x8];
8488 8489 8490 8491
	u8         module[0x8];
};

struct mlx5_ifc_bufferx_reg_bits {
8492
	u8         reserved_at_0[0x6];
8493 8494
	u8         lossy[0x1];
	u8         epsb[0x1];
8495
	u8         reserved_at_8[0xc];
8496 8497 8498 8499 8500 8501 8502 8503 8504 8505 8506
	u8         size[0xc];

	u8         xoff_threshold[0x10];
	u8         xon_threshold[0x10];
};

struct mlx5_ifc_set_node_in_bits {
	u8         node_description[64][0x8];
};

struct mlx5_ifc_register_power_settings_bits {
8507
	u8         reserved_at_0[0x18];
8508 8509
	u8         power_settings_level[0x8];

8510
	u8         reserved_at_20[0x60];
8511 8512 8513 8514
};

struct mlx5_ifc_register_host_endianness_bits {
	u8         he[0x1];
8515
	u8         reserved_at_1[0x1f];
8516

8517
	u8         reserved_at_20[0x60];
8518 8519 8520
};

struct mlx5_ifc_umr_pointer_desc_argument_bits {
8521
	u8         reserved_at_0[0x20];
8522 8523 8524 8525 8526 8527 8528 8529 8530 8531 8532 8533

	u8         mkey[0x20];

	u8         addressh_63_32[0x20];

	u8         addressl_31_0[0x20];
};

struct mlx5_ifc_ud_adrs_vector_bits {
	u8         dc_key[0x40];

	u8         ext[0x1];
8534
	u8         reserved_at_41[0x7];
8535 8536 8537 8538 8539 8540 8541 8542
	u8         destination_qp_dct[0x18];

	u8         static_rate[0x4];
	u8         sl_eth_prio[0x4];
	u8         fl[0x1];
	u8         mlid[0x7];
	u8         rlid_udp_sport[0x10];

8543
	u8         reserved_at_80[0x20];
8544 8545 8546 8547 8548 8549 8550

	u8         rmac_47_16[0x20];

	u8         rmac_15_0[0x10];
	u8         tclass[0x8];
	u8         hop_limit[0x8];

8551
	u8         reserved_at_e0[0x1];
8552
	u8         grh[0x1];
8553
	u8         reserved_at_e2[0x2];
8554 8555 8556 8557 8558 8559 8560
	u8         src_addr_index[0x8];
	u8         flow_label[0x14];

	u8         rgid_rip[16][0x8];
};

struct mlx5_ifc_pages_req_event_bits {
8561
	u8         reserved_at_0[0x10];
8562 8563 8564 8565
	u8         function_id[0x10];

	u8         num_pages[0x20];

8566
	u8         reserved_at_40[0xa0];
8567 8568 8569
};

struct mlx5_ifc_eqe_bits {
8570
	u8         reserved_at_0[0x8];
8571
	u8         event_type[0x8];
8572
	u8         reserved_at_10[0x8];
8573 8574
	u8         event_sub_type[0x8];

8575
	u8         reserved_at_20[0xe0];
8576 8577 8578

	union mlx5_ifc_event_auto_bits event_data;

8579
	u8         reserved_at_1e0[0x10];
8580
	u8         signature[0x8];
8581
	u8         reserved_at_1f8[0x7];
8582 8583 8584 8585 8586 8587 8588 8589 8590
	u8         owner[0x1];
};

enum {
	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
};

struct mlx5_ifc_cmd_queue_entry_bits {
	u8         type[0x8];
8591
	u8         reserved_at_8[0x18];
8592 8593 8594 8595 8596 8597

	u8         input_length[0x20];

	u8         input_mailbox_pointer_63_32[0x20];

	u8         input_mailbox_pointer_31_9[0x17];
8598
	u8         reserved_at_77[0x9];
8599 8600 8601 8602 8603 8604 8605 8606

	u8         command_input_inline_data[16][0x8];

	u8         command_output_inline_data[16][0x8];

	u8         output_mailbox_pointer_63_32[0x20];

	u8         output_mailbox_pointer_31_9[0x17];
8607
	u8         reserved_at_1b7[0x9];
8608 8609 8610 8611 8612

	u8         output_length[0x20];

	u8         token[0x8];
	u8         signature[0x8];
8613
	u8         reserved_at_1f0[0x8];
8614 8615 8616 8617 8618 8619
	u8         status[0x7];
	u8         ownership[0x1];
};

struct mlx5_ifc_cmd_out_bits {
	u8         status[0x8];
8620
	u8         reserved_at_8[0x18];
8621 8622 8623 8624 8625 8626 8627 8628

	u8         syndrome[0x20];

	u8         command_output[0x20];
};

struct mlx5_ifc_cmd_in_bits {
	u8         opcode[0x10];
8629
	u8         reserved_at_10[0x10];
8630

8631
	u8         reserved_at_20[0x10];
8632 8633 8634 8635 8636 8637 8638 8639
	u8         op_mod[0x10];

	u8         command[0][0x20];
};

struct mlx5_ifc_cmd_if_box_bits {
	u8         mailbox_data[512][0x8];

8640
	u8         reserved_at_1000[0x180];
8641 8642 8643 8644

	u8         next_pointer_63_32[0x20];

	u8         next_pointer_31_10[0x16];
8645
	u8         reserved_at_11b6[0xa];
8646 8647 8648

	u8         block_number[0x20];

8649
	u8         reserved_at_11e0[0x8];
8650 8651 8652 8653 8654 8655 8656 8657 8658
	u8         token[0x8];
	u8         ctrl_signature[0x8];
	u8         signature[0x8];
};

struct mlx5_ifc_mtt_bits {
	u8         ptag_63_32[0x20];

	u8         ptag_31_8[0x18];
8659
	u8         reserved_at_38[0x6];
8660 8661 8662 8663
	u8         wr_en[0x1];
	u8         rd_en[0x1];
};

8664 8665 8666 8667 8668 8669 8670 8671 8672 8673 8674 8675 8676 8677 8678 8679 8680 8681 8682 8683 8684 8685 8686 8687 8688 8689 8690 8691 8692 8693 8694 8695 8696 8697 8698 8699 8700 8701 8702 8703 8704 8705 8706 8707 8708 8709 8710 8711
struct mlx5_ifc_query_wol_rol_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x10];
	u8         rol_mode[0x8];
	u8         wol_mode[0x8];

	u8         reserved_at_60[0x20];
};

struct mlx5_ifc_query_wol_rol_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_set_wol_rol_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_set_wol_rol_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         rol_mode_valid[0x1];
	u8         wol_mode_valid[0x1];
	u8         reserved_at_42[0xe];
	u8         rol_mode[0x8];
	u8         wol_mode[0x8];

	u8         reserved_at_60[0x20];
};

8712 8713 8714 8715 8716 8717 8718 8719 8720 8721 8722 8723 8724 8725 8726 8727 8728 8729 8730 8731 8732 8733 8734 8735 8736 8737 8738 8739 8740 8741 8742 8743 8744
enum {
	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
};

enum {
	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
};

enum {
	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
};

struct mlx5_ifc_initial_seg_bits {
	u8         fw_rev_minor[0x10];
	u8         fw_rev_major[0x10];

	u8         cmd_interface_rev[0x10];
	u8         fw_rev_subminor[0x10];

8745
	u8         reserved_at_40[0x40];
8746 8747 8748 8749

	u8         cmdq_phy_addr_63_32[0x20];

	u8         cmdq_phy_addr_31_12[0x14];
8750
	u8         reserved_at_b4[0x2];
8751 8752 8753 8754 8755 8756
	u8         nic_interface[0x2];
	u8         log_cmdq_size[0x4];
	u8         log_cmdq_stride[0x4];

	u8         command_doorbell_vector[0x20];

8757
	u8         reserved_at_e0[0xf00];
8758 8759

	u8         initializing[0x1];
8760
	u8         reserved_at_fe1[0x4];
8761
	u8         nic_interface_supported[0x3];
8762 8763
	u8         embedded_cpu[0x1];
	u8         reserved_at_fe9[0x17];
8764 8765 8766 8767 8768

	struct mlx5_ifc_health_buffer_bits health_buffer;

	u8         no_dram_nic_offset[0x20];

8769
	u8         reserved_at_1220[0x6e40];
8770

8771
	u8         reserved_at_8060[0x1f];
8772 8773 8774 8775 8776
	u8         clear_int[0x1];

	u8         health_syndrome[0x8];
	u8         health_counter[0x18];

8777
	u8         reserved_at_80a0[0x17fc0];
8778 8779
};

8780 8781 8782 8783 8784 8785 8786 8787 8788 8789 8790 8791 8792 8793 8794 8795 8796 8797 8798 8799 8800 8801 8802 8803 8804 8805
struct mlx5_ifc_mtpps_reg_bits {
	u8         reserved_at_0[0xc];
	u8         cap_number_of_pps_pins[0x4];
	u8         reserved_at_10[0x4];
	u8         cap_max_num_of_pps_in_pins[0x4];
	u8         reserved_at_18[0x4];
	u8         cap_max_num_of_pps_out_pins[0x4];

	u8         reserved_at_20[0x24];
	u8         cap_pin_3_mode[0x4];
	u8         reserved_at_48[0x4];
	u8         cap_pin_2_mode[0x4];
	u8         reserved_at_50[0x4];
	u8         cap_pin_1_mode[0x4];
	u8         reserved_at_58[0x4];
	u8         cap_pin_0_mode[0x4];

	u8         reserved_at_60[0x4];
	u8         cap_pin_7_mode[0x4];
	u8         reserved_at_68[0x4];
	u8         cap_pin_6_mode[0x4];
	u8         reserved_at_70[0x4];
	u8         cap_pin_5_mode[0x4];
	u8         reserved_at_78[0x4];
	u8         cap_pin_4_mode[0x4];

8806 8807
	u8         field_select[0x20];
	u8         reserved_at_a0[0x60];
8808 8809 8810 8811 8812 8813 8814 8815 8816 8817 8818 8819 8820 8821

	u8         enable[0x1];
	u8         reserved_at_101[0xb];
	u8         pattern[0x4];
	u8         reserved_at_110[0x4];
	u8         pin_mode[0x4];
	u8         pin[0x8];

	u8         reserved_at_120[0x20];

	u8         time_stamp[0x40];

	u8         out_pulse_duration[0x10];
	u8         out_periodic_adjustment[0x10];
8822
	u8         enhanced_out_periodic_adjustment[0x20];
8823

8824
	u8         reserved_at_1c0[0x20];
8825 8826 8827 8828 8829 8830 8831 8832 8833 8834 8835
};

struct mlx5_ifc_mtppse_reg_bits {
	u8         reserved_at_0[0x18];
	u8         pin[0x8];
	u8         event_arm[0x1];
	u8         reserved_at_21[0x1b];
	u8         event_generation_mode[0x4];
	u8         reserved_at_40[0x40];
};

8836 8837 8838 8839 8840 8841 8842 8843 8844 8845 8846 8847 8848 8849 8850 8851 8852 8853 8854 8855 8856 8857 8858 8859 8860 8861 8862 8863 8864 8865 8866 8867 8868 8869 8870 8871 8872 8873 8874 8875 8876 8877 8878 8879 8880 8881 8882 8883 8884 8885 8886 8887 8888 8889 8890 8891 8892 8893 8894 8895 8896 8897 8898 8899 8900 8901 8902 8903 8904 8905 8906 8907 8908 8909 8910 8911 8912 8913 8914
struct mlx5_ifc_mcqi_cap_bits {
	u8         supported_info_bitmask[0x20];

	u8         component_size[0x20];

	u8         max_component_size[0x20];

	u8         log_mcda_word_size[0x4];
	u8         reserved_at_64[0xc];
	u8         mcda_max_write_size[0x10];

	u8         rd_en[0x1];
	u8         reserved_at_81[0x1];
	u8         match_chip_id[0x1];
	u8         match_psid[0x1];
	u8         check_user_timestamp[0x1];
	u8         match_base_guid_mac[0x1];
	u8         reserved_at_86[0x1a];
};

struct mlx5_ifc_mcqi_reg_bits {
	u8         read_pending_component[0x1];
	u8         reserved_at_1[0xf];
	u8         component_index[0x10];

	u8         reserved_at_20[0x20];

	u8         reserved_at_40[0x1b];
	u8         info_type[0x5];

	u8         info_size[0x20];

	u8         offset[0x20];

	u8         reserved_at_a0[0x10];
	u8         data_size[0x10];

	u8         data[0][0x20];
};

struct mlx5_ifc_mcc_reg_bits {
	u8         reserved_at_0[0x4];
	u8         time_elapsed_since_last_cmd[0xc];
	u8         reserved_at_10[0x8];
	u8         instruction[0x8];

	u8         reserved_at_20[0x10];
	u8         component_index[0x10];

	u8         reserved_at_40[0x8];
	u8         update_handle[0x18];

	u8         handle_owner_type[0x4];
	u8         handle_owner_host_id[0x4];
	u8         reserved_at_68[0x1];
	u8         control_progress[0x7];
	u8         error_code[0x8];
	u8         reserved_at_78[0x4];
	u8         control_state[0x4];

	u8         component_size[0x20];

	u8         reserved_at_a0[0x60];
};

struct mlx5_ifc_mcda_reg_bits {
	u8         reserved_at_0[0x8];
	u8         update_handle[0x18];

	u8         offset[0x20];

	u8         reserved_at_40[0x10];
	u8         size[0x10];

	u8         reserved_at_60[0x20];

	u8         data[0][0x20];
};

8915 8916 8917 8918 8919 8920 8921 8922 8923 8924 8925 8926 8927 8928 8929 8930
union mlx5_ifc_ports_control_registers_document_bits {
	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
	struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
	struct mlx5_ifc_pamp_reg_bits pamp_reg;
	struct mlx5_ifc_paos_reg_bits paos_reg;
	struct mlx5_ifc_pcap_reg_bits pcap_reg;
	struct mlx5_ifc_peir_reg_bits peir_reg;
	struct mlx5_ifc_pelc_reg_bits pelc_reg;
	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8931
	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8932 8933 8934 8935 8936 8937 8938 8939 8940 8941 8942 8943 8944 8945 8946
	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
	struct mlx5_ifc_pifr_reg_bits pifr_reg;
	struct mlx5_ifc_pipg_reg_bits pipg_reg;
	struct mlx5_ifc_plbf_reg_bits plbf_reg;
	struct mlx5_ifc_plib_reg_bits plib_reg;
	struct mlx5_ifc_plpc_reg_bits plpc_reg;
	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
	struct mlx5_ifc_ppad_reg_bits ppad_reg;
	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8947
	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8948 8949 8950 8951 8952 8953 8954
	struct mlx5_ifc_pplm_reg_bits pplm_reg;
	struct mlx5_ifc_pplr_reg_bits pplr_reg;
	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
	struct mlx5_ifc_pspa_reg_bits pspa_reg;
	struct mlx5_ifc_ptas_reg_bits ptas_reg;
	struct mlx5_ifc_ptys_reg_bits ptys_reg;
8955
	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8956 8957 8958 8959
	struct mlx5_ifc_pude_reg_bits pude_reg;
	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
	struct mlx5_ifc_slrg_reg_bits slrg_reg;
	struct mlx5_ifc_sltp_reg_bits sltp_reg;
8960 8961
	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8962
	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8963 8964
	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8965 8966 8967
	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
	struct mlx5_ifc_mcc_reg_bits mcc_reg;
	struct mlx5_ifc_mcda_reg_bits mcda_reg;
8968
	u8         reserved_at_0[0x60e0];
8969 8970 8971 8972
};

union mlx5_ifc_debug_enhancements_document_bits {
	struct mlx5_ifc_health_buffer_bits health_buffer;
8973
	u8         reserved_at_0[0x200];
8974 8975 8976 8977
};

union mlx5_ifc_uplink_pci_interface_document_bits {
	struct mlx5_ifc_initial_seg_bits initial_seg;
8978
	u8         reserved_at_0[0x20060];
8979 8980
};

8981 8982
struct mlx5_ifc_set_flow_table_root_out_bits {
	u8         status[0x8];
8983
	u8         reserved_at_8[0x18];
8984 8985 8986

	u8         syndrome[0x20];

8987
	u8         reserved_at_40[0x40];
8988 8989 8990 8991
};

struct mlx5_ifc_set_flow_table_root_in_bits {
	u8         opcode[0x10];
8992
	u8         reserved_at_10[0x10];
8993

8994
	u8         reserved_at_20[0x10];
8995 8996
	u8         op_mod[0x10];

8997 8998 8999 9000 9001
	u8         other_vport[0x1];
	u8         reserved_at_41[0xf];
	u8         vport_number[0x10];

	u8         reserved_at_60[0x20];
9002 9003

	u8         table_type[0x8];
9004
	u8         reserved_at_88[0x18];
9005

9006
	u8         reserved_at_a0[0x8];
9007 9008
	u8         table_id[0x18];

9009 9010 9011
	u8         reserved_at_c0[0x8];
	u8         underlay_qpn[0x18];
	u8         reserved_at_e0[0x120];
9012 9013
};

9014
enum {
9015 9016
	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9017 9018 9019 9020
};

struct mlx5_ifc_modify_flow_table_out_bits {
	u8         status[0x8];
9021
	u8         reserved_at_8[0x18];
9022 9023 9024

	u8         syndrome[0x20];

9025
	u8         reserved_at_40[0x40];
9026 9027 9028 9029
};

struct mlx5_ifc_modify_flow_table_in_bits {
	u8         opcode[0x10];
9030
	u8         reserved_at_10[0x10];
9031

9032
	u8         reserved_at_20[0x10];
9033 9034
	u8         op_mod[0x10];

9035 9036 9037
	u8         other_vport[0x1];
	u8         reserved_at_41[0xf];
	u8         vport_number[0x10];
9038

9039
	u8         reserved_at_60[0x10];
9040 9041 9042
	u8         modify_field_select[0x10];

	u8         table_type[0x8];
9043
	u8         reserved_at_88[0x18];
9044

9045
	u8         reserved_at_a0[0x8];
9046 9047
	u8         table_id[0x18];

9048
	struct mlx5_ifc_flow_table_context_bits flow_table_context;
9049 9050
};

9051 9052 9053 9054 9055 9056 9057 9058 9059 9060 9061 9062 9063 9064 9065 9066 9067 9068 9069 9070 9071 9072 9073 9074 9075 9076 9077 9078 9079 9080 9081 9082 9083 9084 9085
struct mlx5_ifc_ets_tcn_config_reg_bits {
	u8         g[0x1];
	u8         b[0x1];
	u8         r[0x1];
	u8         reserved_at_3[0x9];
	u8         group[0x4];
	u8         reserved_at_10[0x9];
	u8         bw_allocation[0x7];

	u8         reserved_at_20[0xc];
	u8         max_bw_units[0x4];
	u8         reserved_at_30[0x8];
	u8         max_bw_value[0x8];
};

struct mlx5_ifc_ets_global_config_reg_bits {
	u8         reserved_at_0[0x2];
	u8         r[0x1];
	u8         reserved_at_3[0x1d];

	u8         reserved_at_20[0xc];
	u8         max_bw_units[0x4];
	u8         reserved_at_30[0x8];
	u8         max_bw_value[0x8];
};

struct mlx5_ifc_qetc_reg_bits {
	u8                                         reserved_at_0[0x8];
	u8                                         port_number[0x8];
	u8                                         reserved_at_10[0x30];

	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
};

9086 9087 9088 9089 9090 9091 9092 9093 9094 9095 9096 9097 9098 9099 9100 9101 9102 9103 9104 9105
struct mlx5_ifc_qpdpm_dscp_reg_bits {
	u8         e[0x1];
	u8         reserved_at_01[0x0b];
	u8         prio[0x04];
};

struct mlx5_ifc_qpdpm_reg_bits {
	u8                                     reserved_at_0[0x8];
	u8                                     local_port[0x8];
	u8                                     reserved_at_10[0x10];
	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
};

struct mlx5_ifc_qpts_reg_bits {
	u8         reserved_at_0[0x8];
	u8         local_port[0x8];
	u8         reserved_at_10[0x2d];
	u8         trust_state[0x3];
};

9106 9107 9108 9109 9110 9111 9112 9113 9114 9115 9116 9117 9118 9119 9120 9121 9122 9123 9124 9125 9126 9127 9128 9129 9130 9131 9132 9133 9134 9135 9136 9137 9138 9139 9140
struct mlx5_ifc_pptb_reg_bits {
	u8         reserved_at_0[0x2];
	u8         mm[0x2];
	u8         reserved_at_4[0x4];
	u8         local_port[0x8];
	u8         reserved_at_10[0x6];
	u8         cm[0x1];
	u8         um[0x1];
	u8         pm[0x8];

	u8         prio_x_buff[0x20];

	u8         pm_msb[0x8];
	u8         reserved_at_48[0x10];
	u8         ctrl_buff[0x4];
	u8         untagged_buff[0x4];
};

struct mlx5_ifc_pbmc_reg_bits {
	u8         reserved_at_0[0x8];
	u8         local_port[0x8];
	u8         reserved_at_10[0x10];

	u8         xoff_timer_value[0x10];
	u8         xoff_refresh[0x10];

	u8         reserved_at_40[0x9];
	u8         fullness_threshold[0x7];
	u8         port_buffer_size[0x10];

	struct mlx5_ifc_bufferx_reg_bits buffer[10];

	u8         reserved_at_2e0[0x40];
};

9141 9142 9143 9144 9145 9146 9147 9148 9149 9150
struct mlx5_ifc_qtct_reg_bits {
	u8         reserved_at_0[0x8];
	u8         port_number[0x8];
	u8         reserved_at_10[0xd];
	u8         prio[0x3];

	u8         reserved_at_20[0x1d];
	u8         tclass[0x3];
};

9151 9152 9153 9154 9155 9156 9157 9158 9159 9160 9161 9162 9163 9164 9165 9166 9167 9168 9169 9170 9171 9172 9173 9174 9175 9176 9177 9178 9179 9180
struct mlx5_ifc_mcia_reg_bits {
	u8         l[0x1];
	u8         reserved_at_1[0x7];
	u8         module[0x8];
	u8         reserved_at_10[0x8];
	u8         status[0x8];

	u8         i2c_device_address[0x8];
	u8         page_number[0x8];
	u8         device_address[0x10];

	u8         reserved_at_40[0x10];
	u8         size[0x10];

	u8         reserved_at_60[0x20];

	u8         dword_0[0x20];
	u8         dword_1[0x20];
	u8         dword_2[0x20];
	u8         dword_3[0x20];
	u8         dword_4[0x20];
	u8         dword_5[0x20];
	u8         dword_6[0x20];
	u8         dword_7[0x20];
	u8         dword_8[0x20];
	u8         dword_9[0x20];
	u8         dword_10[0x20];
	u8         dword_11[0x20];
};

9181 9182 9183 9184
struct mlx5_ifc_dcbx_param_bits {
	u8         dcbx_cee_cap[0x1];
	u8         dcbx_ieee_cap[0x1];
	u8         dcbx_standby_cap[0x1];
9185
	u8         reserved_at_3[0x5];
9186 9187 9188 9189 9190 9191 9192 9193 9194 9195 9196 9197 9198 9199 9200 9201 9202 9203 9204 9205 9206 9207 9208 9209 9210
	u8         port_number[0x8];
	u8         reserved_at_10[0xa];
	u8         max_application_table_size[6];
	u8         reserved_at_20[0x15];
	u8         version_oper[0x3];
	u8         reserved_at_38[5];
	u8         version_admin[0x3];
	u8         willing_admin[0x1];
	u8         reserved_at_41[0x3];
	u8         pfc_cap_oper[0x4];
	u8         reserved_at_48[0x4];
	u8         pfc_cap_admin[0x4];
	u8         reserved_at_50[0x4];
	u8         num_of_tc_oper[0x4];
	u8         reserved_at_58[0x4];
	u8         num_of_tc_admin[0x4];
	u8         remote_willing[0x1];
	u8         reserved_at_61[3];
	u8         remote_pfc_cap[4];
	u8         reserved_at_68[0x14];
	u8         remote_num_of_tc[0x4];
	u8         reserved_at_80[0x18];
	u8         error[0x8];
	u8         reserved_at_a0[0x160];
};
9211 9212 9213 9214 9215 9216 9217 9218 9219 9220 9221 9222 9223 9224 9225 9226 9227 9228 9229 9230 9231 9232 9233 9234 9235 9236 9237 9238 9239 9240 9241 9242 9243 9244 9245 9246 9247 9248 9249 9250 9251 9252 9253 9254 9255 9256 9257 9258 9259 9260 9261 9262 9263 9264 9265 9266 9267 9268 9269 9270 9271 9272 9273 9274 9275 9276 9277 9278 9279 9280 9281 9282 9283 9284 9285 9286 9287 9288 9289 9290 9291 9292 9293 9294 9295 9296 9297 9298 9299 9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 9310 9311 9312 9313 9314 9315 9316 9317 9318 9319 9320 9321 9322 9323 9324 9325 9326 9327 9328 9329 9330 9331 9332 9333 9334 9335 9336 9337 9338 9339 9340

struct mlx5_ifc_lagc_bits {
	u8         reserved_at_0[0x1d];
	u8         lag_state[0x3];

	u8         reserved_at_20[0x14];
	u8         tx_remap_affinity_2[0x4];
	u8         reserved_at_38[0x4];
	u8         tx_remap_affinity_1[0x4];
};

struct mlx5_ifc_create_lag_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_create_lag_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	struct mlx5_ifc_lagc_bits ctx;
};

struct mlx5_ifc_modify_lag_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_modify_lag_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x20];
	u8         field_select[0x20];

	struct mlx5_ifc_lagc_bits ctx;
};

struct mlx5_ifc_query_lag_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];

	struct mlx5_ifc_lagc_bits ctx;
};

struct mlx5_ifc_query_lag_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_destroy_lag_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_destroy_lag_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_create_vport_lag_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_create_vport_lag_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_destroy_vport_lag_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_destroy_vport_lag_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x40];
};

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struct mlx5_ifc_alloc_memic_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_30[0x20];

	u8	   reserved_at_40[0x18];
	u8	   log_memic_addr_alignment[0x8];

	u8         range_start_addr[0x40];

	u8         range_size[0x20];

	u8         memic_size[0x20];
};

struct mlx5_ifc_alloc_memic_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         memic_start_addr[0x40];
};

struct mlx5_ifc_dealloc_memic_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x40];

	u8         memic_start_addr[0x40];

	u8         memic_size[0x20];

	u8         reserved_at_e0[0x20];
};

struct mlx5_ifc_dealloc_memic_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];
};

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struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
	u8         opcode[0x10];
	u8         uid[0x10];

	u8         reserved_at_20[0x10];
	u8         obj_type[0x10];

	u8         obj_id[0x20];

	u8         reserved_at_60[0x20];
};

struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         obj_id[0x20];

	u8         reserved_at_60[0x20];
};

struct mlx5_ifc_umem_bits {
9418
	u8         reserved_at_0[0x80];
9419

9420
	u8         reserved_at_80[0x1b];
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	u8         log_page_size[0x5];

	u8         page_offset[0x20];

	u8         num_of_mtt[0x40];

	struct mlx5_ifc_mtt_bits  mtt[0];
};

struct mlx5_ifc_uctx_bits {
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	u8         cap[0x20];

9433
	u8         reserved_at_20[0x160];
9434 9435 9436
};

struct mlx5_ifc_create_umem_in_bits {
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	u8         opcode[0x10];
	u8         uid[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x40];

	struct mlx5_ifc_umem_bits  umem;
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};

struct mlx5_ifc_create_uctx_in_bits {
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	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x40];

	struct mlx5_ifc_uctx_bits  uctx;
};

struct mlx5_ifc_destroy_uctx_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x10];
	u8         uid[0x10];

	u8         reserved_at_60[0x20];
9471 9472
};

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struct mlx5_ifc_mtrc_string_db_param_bits {
	u8         string_db_base_address[0x20];

	u8         reserved_at_20[0x8];
	u8         string_db_size[0x18];
};

struct mlx5_ifc_mtrc_cap_bits {
	u8         trace_owner[0x1];
	u8         trace_to_memory[0x1];
	u8         reserved_at_2[0x4];
	u8         trc_ver[0x2];
	u8         reserved_at_8[0x14];
	u8         num_string_db[0x4];

	u8         first_string_trace[0x8];
	u8         num_string_trace[0x8];
	u8         reserved_at_30[0x28];

	u8         log_max_trace_buffer_size[0x8];

	u8         reserved_at_60[0x20];

	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];

	u8         reserved_at_280[0x180];
};

struct mlx5_ifc_mtrc_conf_bits {
	u8         reserved_at_0[0x1c];
	u8         trace_mode[0x4];
	u8         reserved_at_20[0x18];
	u8         log_trace_buffer_size[0x8];
	u8         trace_mkey[0x20];
	u8         reserved_at_60[0x3a0];
};

struct mlx5_ifc_mtrc_stdb_bits {
	u8         string_db_index[0x4];
	u8         reserved_at_4[0x4];
	u8         read_size[0x18];
	u8         start_offset[0x20];
	u8         string_db_data[0];
};

struct mlx5_ifc_mtrc_ctrl_bits {
	u8         trace_status[0x2];
	u8         reserved_at_2[0x2];
	u8         arm_event[0x1];
	u8         reserved_at_5[0xb];
	u8         modify_field_select[0x10];
	u8         reserved_at_20[0x2b];
	u8         current_timestamp52_32[0x15];
	u8         current_timestamp31_0[0x20];
	u8         reserved_at_80[0x180];
};

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struct mlx5_ifc_host_params_context_bits {
	u8         host_number[0x8];
	u8         reserved_at_8[0x8];
	u8         host_num_of_vfs[0x10];

	u8         reserved_at_20[0x10];
	u8         host_pci_bus[0x10];

	u8         reserved_at_40[0x10];
	u8         host_pci_device[0x10];

	u8         reserved_at_60[0x10];
	u8         host_pci_function[0x10];

	u8         reserved_at_80[0x180];
};

struct mlx5_ifc_query_host_params_in_bits {
	u8         opcode[0x10];
	u8         reserved_at_10[0x10];

	u8         reserved_at_20[0x10];
	u8         op_mod[0x10];

	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_query_host_params_out_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         reserved_at_40[0x40];

	struct mlx5_ifc_host_params_context_bits host_params_context;

	u8         reserved_at_280[0x180];
};

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#endif /* MLX5_IFC_H */
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