i915_drv.c 49.5 KB
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/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#include <linux/device.h>
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#include <linux/acpi.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#include <linux/console.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <drm/drm_crtc_helper.h>
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static struct drm_driver driver;

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#define GEN_DEFAULT_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }

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#define GEN_CHV_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  CHV_PIPE_C_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   CHV_TRANSCODER_C_OFFSET, }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
			     CHV_PALETTE_C_OFFSET }
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#define CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }

#define IVB_CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }

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static const struct intel_device_info intel_i830_info = {
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	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_845g_info = {
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	.gen = 2, .num_pipes = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i85x_info = {
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	.gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
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	.cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i865g_info = {
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	.gen = 2, .num_pipes = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i915g_info = {
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	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};
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static const struct intel_device_info intel_i915gm_info = {
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	.gen = 3, .is_mobile = 1, .num_pipes = 2,
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	.cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.supports_tv = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};
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static const struct intel_device_info intel_i945g_info = {
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	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};
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static const struct intel_device_info intel_i945gm_info = {
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	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
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	.has_hotplug = 1, .cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.supports_tv = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i965g_info = {
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	.gen = 4, .is_broadwater = 1, .num_pipes = 2,
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	.has_hotplug = 1,
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	.has_overlay = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i965gm_info = {
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	.gen = 4, .is_crestline = 1, .num_pipes = 2,
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	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
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	.has_overlay = 1,
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	.supports_tv = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_g33_info = {
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	.gen = 3, .is_g33 = 1, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_overlay = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_g45_info = {
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	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
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	.has_pipe_cxsr = 1, .has_hotplug = 1,
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	.ring_mask = RENDER_RING | BSD_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_gm45_info = {
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	.gen = 4, .is_g4x = 1, .num_pipes = 2,
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	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
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	.has_pipe_cxsr = 1, .has_hotplug = 1,
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	.supports_tv = 1,
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	.ring_mask = RENDER_RING | BSD_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_pineview_info = {
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	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_overlay = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_ironlake_d_info = {
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	.gen = 5, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.ring_mask = RENDER_RING | BSD_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_ironlake_m_info = {
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	.gen = 5, .is_mobile = 1, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING | BSD_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_sandybridge_d_info = {
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	.gen = 6, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
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	.has_llc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_sandybridge_m_info = {
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	.gen = 6, .is_mobile = 1, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
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	.has_llc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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#define GEN7_FEATURES  \
	.gen = 7, .num_pipes = 3, \
	.need_gfx_hws = 1, .has_hotplug = 1, \
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	.has_fbc = 1, \
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
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	.has_llc = 1
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static const struct intel_device_info intel_ivybridge_d_info = {
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	GEN7_FEATURES,
	.is_ivybridge = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_ivybridge_m_info = {
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	GEN7_FEATURES,
	.is_ivybridge = 1,
	.is_mobile = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_ivybridge_q_info = {
	GEN7_FEATURES,
	.is_ivybridge = 1,
	.num_pipes = 0, /* legal, last one wins */
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_valleyview_m_info = {
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	GEN7_FEATURES,
	.is_mobile = 1,
	.num_pipes = 2,
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	.is_valleyview = 1,
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	.display_mmio_offset = VLV_DISPLAY_BASE,
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	.has_fbc = 0, /* legal, last one wins */
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	.has_llc = 0, /* legal, last one wins */
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_valleyview_d_info = {
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	GEN7_FEATURES,
	.num_pipes = 2,
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	.is_valleyview = 1,
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	.display_mmio_offset = VLV_DISPLAY_BASE,
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	.has_fbc = 0, /* legal, last one wins */
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	.has_llc = 0, /* legal, last one wins */
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_haswell_d_info = {
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	GEN7_FEATURES,
	.is_haswell = 1,
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	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_haswell_m_info = {
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	GEN7_FEATURES,
	.is_haswell = 1,
	.is_mobile = 1,
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	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_broadwell_d_info = {
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	.gen = 8, .num_pipes = 3,
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	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.has_llc = 1,
	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.has_fbc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_broadwell_m_info = {
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	.gen = 8, .is_mobile = 1, .num_pipes = 3,
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	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.has_llc = 1,
	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.has_fbc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_broadwell_gt3d_info = {
	.gen = 8, .num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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	.has_llc = 1,
	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.has_fbc = 1,
	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_broadwell_gt3m_info = {
	.gen = 8, .is_mobile = 1, .num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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	.has_llc = 1,
	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.has_fbc = 1,
	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_cherryview_info = {
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	.gen = 8, .num_pipes = 3,
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	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.is_valleyview = 1,
	.display_mmio_offset = VLV_DISPLAY_BASE,
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	GEN_CHV_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_skylake_info = {
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	.is_skylake = 1,
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	.gen = 9, .num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.has_llc = 1,
	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.has_fbc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
	IVB_CURSOR_OFFSETS,
};

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static const struct intel_device_info intel_skylake_gt3_info = {
	.is_skylake = 1,
	.gen = 9, .num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
	.has_llc = 1,
	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.has_fbc = 1,
	GEN_DEFAULT_PIPEOFFSETS,
	IVB_CURSOR_OFFSETS,
};

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static const struct intel_device_info intel_broxton_info = {
	.is_preliminary = 1,
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	.is_broxton = 1,
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	.gen = 9,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.num_pipes = 3,
	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.has_fbc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
	IVB_CURSOR_OFFSETS,
};

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static const struct intel_device_info intel_kabylake_info = {
	.is_preliminary = 1,
	.is_kabylake = 1,
	.gen = 9,
	.num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.has_llc = 1,
	.has_ddi = 1,
	.has_fpga_dbg = 1,
	.has_fbc = 1,
	GEN_DEFAULT_PIPEOFFSETS,
	IVB_CURSOR_OFFSETS,
};

static const struct intel_device_info intel_kabylake_gt3_info = {
	.is_preliminary = 1,
	.is_kabylake = 1,
	.gen = 9,
	.num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
	.has_llc = 1,
	.has_ddi = 1,
	.has_fpga_dbg = 1,
	.has_fbc = 1,
	GEN_DEFAULT_PIPEOFFSETS,
	IVB_CURSOR_OFFSETS,
};

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/*
 * Make sure any device matches here are from most specific to most
 * general.  For example, since the Quanta match is based on the subsystem
 * and subvendor IDs, we need it to come before the more general IVB
 * PCI ID matches, otherwise we'll use the wrong info struct above.
 */
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static const struct pci_device_id pciidlist[] = {
	INTEL_I830_IDS(&intel_i830_info),
	INTEL_I845G_IDS(&intel_845g_info),
	INTEL_I85X_IDS(&intel_i85x_info),
	INTEL_I865G_IDS(&intel_i865g_info),
	INTEL_I915G_IDS(&intel_i915g_info),
	INTEL_I915GM_IDS(&intel_i915gm_info),
	INTEL_I945G_IDS(&intel_i945g_info),
	INTEL_I945GM_IDS(&intel_i945gm_info),
	INTEL_I965G_IDS(&intel_i965g_info),
	INTEL_G33_IDS(&intel_g33_info),
	INTEL_I965GM_IDS(&intel_i965gm_info),
	INTEL_GM45_IDS(&intel_gm45_info),
	INTEL_G45_IDS(&intel_g45_info),
	INTEL_PINEVIEW_IDS(&intel_pineview_info),
	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
	INTEL_HSW_D_IDS(&intel_haswell_d_info),
	INTEL_HSW_M_IDS(&intel_haswell_m_info),
	INTEL_VLV_M_IDS(&intel_valleyview_m_info),
	INTEL_VLV_D_IDS(&intel_valleyview_d_info),
	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
	INTEL_CHV_IDS(&intel_cherryview_info),
	INTEL_SKL_GT1_IDS(&intel_skylake_info),
	INTEL_SKL_GT2_IDS(&intel_skylake_info),
	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
	INTEL_BXT_IDS(&intel_broxton_info),
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	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
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	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
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	{0, 0, 0}
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};

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MODULE_DEVICE_TABLE(pci, pciidlist);

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static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
{
	enum intel_pch ret = PCH_NOP;

	/*
	 * In a virtualized passthrough environment we can be in a
	 * setup where the ISA bridge is not able to be passed through.
	 * In this case, a south bridge can be emulated and we have to
	 * make an educated guess as to which PCH is really there.
	 */

	if (IS_GEN5(dev)) {
		ret = PCH_IBX;
		DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
	} else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
		ret = PCH_CPT;
		DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
		ret = PCH_LPT;
		DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
498
	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
499 500 501 502 503 504 505
		ret = PCH_SPT;
		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
	}

	return ret;
}

506
void intel_detect_pch(struct drm_device *dev)
507 508
{
	struct drm_i915_private *dev_priv = dev->dev_private;
509
	struct pci_dev *pch = NULL;
510

B
Ben Widawsky 已提交
511 512 513 514 515 516 517 518
	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
	 * (which really amounts to a PCH but no South Display).
	 */
	if (INTEL_INFO(dev)->num_pipes == 0) {
		dev_priv->pch_type = PCH_NOP;
		return;
	}

519 520 521 522 523
	/*
	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
	 * make graphics device passthrough work easy for VMM, that only
	 * need to expose ISA bridge to let driver know the real hardware
	 * underneath. This is a requirement from virtualization team.
524 525 526 527 528
	 *
	 * In some virtualized environments (e.g. XEN), there is irrelevant
	 * ISA bridge in the system. To work reliably, we should scan trhough
	 * all the ISA bridge devices and check for the first match, instead
	 * of only checking the first one.
529
	 */
530
	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
531
		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
532
			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
533
			dev_priv->pch_id = id;
534

535 536 537
			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_IBX;
				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
538
				WARN_ON(!IS_GEN5(dev));
539
			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
540 541
				dev_priv->pch_type = PCH_CPT;
				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
542
				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
J
Jesse Barnes 已提交
543 544 545
			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
				/* PantherPoint is CPT compatible */
				dev_priv->pch_type = PCH_CPT;
546
				DRM_DEBUG_KMS("Found PantherPoint PCH\n");
547
				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
548 549 550
			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
551 552
				WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
				WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
553 554 555
			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
556 557
				WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
				WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
558 559 560
			} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_SPT;
				DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
561 562
				WARN_ON(!IS_SKYLAKE(dev) &&
					!IS_KABYLAKE(dev));
563 564 565
			} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_SPT;
				DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
566 567
				WARN_ON(!IS_SKYLAKE(dev) &&
					!IS_KABYLAKE(dev));
568 569
			} else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE) {
				dev_priv->pch_type = intel_virt_detect_pch(dev);
570 571 572
			} else
				continue;

573
			break;
574 575
		}
	}
576
	if (!pch)
577 578 579
		DRM_DEBUG_KMS("No PCH found.\n");

	pci_dev_put(pch);
580 581
}

582 583 584
bool i915_semaphore_is_enabled(struct drm_device *dev)
{
	if (INTEL_INFO(dev)->gen < 6)
585
		return false;
586

587 588
	if (i915.semaphores >= 0)
		return i915.semaphores;
589

590 591 592 593
	/* TODO: make semaphores and Execlists play nicely together */
	if (i915.enable_execlists)
		return false;

594 595 596 597
	/* Until we get further testing... */
	if (IS_GEN8(dev))
		return false;

598
#ifdef CONFIG_INTEL_IOMMU
599
	/* Enable semaphores on SNB when IO remapping is off */
600 601 602
	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
		return false;
#endif
603

604
	return true;
605 606
}

607 608 609 610 611 612 613 614 615 616 617 618 619 620 621
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct drm_encoder *encoder;

	drm_modeset_lock_all(dev);
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

		if (intel_encoder->suspend)
			intel_encoder->suspend(intel_encoder);
	}
	drm_modeset_unlock_all(dev);
}

622
static int intel_suspend_complete(struct drm_i915_private *dev_priv);
623 624
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
			      bool rpm_resume);
625
static int skl_resume_prepare(struct drm_i915_private *dev_priv);
626
static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
627

628

629
static int i915_drm_suspend(struct drm_device *dev)
J
Jesse Barnes 已提交
630
{
631
	struct drm_i915_private *dev_priv = dev->dev_private;
632
	pci_power_t opregion_target_state;
633
	int error;
634

635 636 637 638 639
	/* ignore lid events during suspend */
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_SUSPENDED;
	mutex_unlock(&dev_priv->modeset_restore_lock);

640 641
	/* We do a lot of poking in a lot of registers, make sure they work
	 * properly. */
642
	intel_display_set_init_power(dev_priv, true);
643

644 645
	drm_kms_helper_poll_disable(dev);

J
Jesse Barnes 已提交
646 647
	pci_save_state(dev->pdev);

648 649 650 651 652 653
	error = i915_gem_suspend(dev);
	if (error) {
		dev_err(&dev->pdev->dev,
			"GEM idle failed, resume might fail\n");
		return error;
	}
654

655 656
	intel_guc_suspend(dev);

657
	intel_suspend_gt_powersave(dev);
658

659 660 661 662 663
	/*
	 * Disable CRTCs directly since we want to preserve sw state
	 * for _thaw. Also, power gate the CRTC power wells.
	 */
	drm_modeset_lock_all(dev);
664
	intel_display_suspend(dev);
665
	drm_modeset_unlock_all(dev);
666

667
	intel_dp_mst_suspend(dev);
668

669 670
	intel_runtime_pm_disable_interrupts(dev_priv);
	intel_hpd_cancel_work(dev_priv);
671

672
	intel_suspend_encoders(dev_priv);
673

674
	intel_suspend_hw(dev);
675

676 677
	i915_gem_suspend_gtt_mappings(dev);

678 679
	i915_save_state(dev);

680 681 682
	opregion_target_state = PCI_D3cold;
#if IS_ENABLED(CONFIG_ACPI_SLEEP)
	if (acpi_target_system_state() < ACPI_STATE_S3)
683
		opregion_target_state = PCI_D1;
684
#endif
685 686
	intel_opregion_notify_adapter(dev, opregion_target_state);

687
	intel_uncore_forcewake_reset(dev, false);
688
	intel_opregion_fini(dev);
689

690
	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
691

692 693
	dev_priv->suspend_count++;

694 695
	intel_display_set_init_power(dev_priv, false);

696 697 698
	if (HAS_CSR(dev_priv))
		flush_work(&dev_priv->csr.work);

699
	return 0;
700 701
}

702
static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
703 704 705 706
{
	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	int ret;

707 708
	intel_power_domains_suspend(dev_priv);

709 710 711 712
	ret = intel_suspend_complete(dev_priv);

	if (ret) {
		DRM_ERROR("Suspend complete failed: %d\n", ret);
713
		intel_power_domains_init_hw(dev_priv, true);
714 715 716 717 718

		return ret;
	}

	pci_disable_device(drm_dev->pdev);
719
	/*
720
	 * During hibernation on some platforms the BIOS may try to access
721 722
	 * the device even though it's already in D3 and hang the machine. So
	 * leave the device in D0 on those platforms and hope the BIOS will
723 724 725 726 727 728 729
	 * power down the device properly. The issue was seen on multiple old
	 * GENs with different BIOS vendors, so having an explicit blacklist
	 * is inpractical; apply the workaround on everything pre GEN6. The
	 * platforms where the issue was seen:
	 * Lenovo Thinkpad X301, X61s, X60, T60, X41
	 * Fujitsu FSC S7110
	 * Acer Aspire 1830T
730
	 */
731
	if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
732
		pci_set_power_state(drm_dev->pdev, PCI_D3hot);
733 734 735 736

	return 0;
}

737
int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
738 739 740 741 742 743 744 745 746
{
	int error;

	if (!dev || !dev->dev_private) {
		DRM_ERROR("dev: %p\n", dev);
		DRM_ERROR("DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}

747 748 749
	if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
			 state.event != PM_EVENT_FREEZE))
		return -EINVAL;
750 751 752

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
753

754
	error = i915_drm_suspend(dev);
755 756 757
	if (error)
		return error;

758
	return i915_drm_suspend_late(dev, false);
J
Jesse Barnes 已提交
759 760
}

761
static int i915_drm_resume(struct drm_device *dev)
762 763
{
	struct drm_i915_private *dev_priv = dev->dev_private;
764

765 766 767
	mutex_lock(&dev->struct_mutex);
	i915_gem_restore_gtt_mappings(dev);
	mutex_unlock(&dev->struct_mutex);
768

769
	i915_restore_state(dev);
770
	intel_opregion_setup(dev);
771

772 773
	intel_init_pch_refclk(dev);
	drm_mode_config_reset(dev);
774

775 776 777 778 779 780 781 782 783 784
	/*
	 * Interrupts have to be enabled before any batches are run. If not the
	 * GPU will hang. i915_gem_init_hw() will initiate batches to
	 * update/restore the context.
	 *
	 * Modeset enabling in intel_modeset_init_hw() also needs working
	 * interrupts.
	 */
	intel_runtime_pm_enable_interrupts(dev_priv);

785 786 787
	mutex_lock(&dev->struct_mutex);
	if (i915_gem_init_hw(dev)) {
		DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
788
			atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
789 790
	}
	mutex_unlock(&dev->struct_mutex);
791

792 793
	intel_guc_resume(dev);

794
	intel_modeset_init_hw(dev);
795

796 797 798 799
	spin_lock_irq(&dev_priv->irq_lock);
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
	spin_unlock_irq(&dev_priv->irq_lock);
800

801
	drm_modeset_lock_all(dev);
802
	intel_display_resume(dev);
803
	drm_modeset_unlock_all(dev);
804

805
	intel_dp_mst_resume(dev);
806

807 808 809 810 811 812 813 814 815
	/*
	 * ... but also need to make sure that hotplug processing
	 * doesn't cause havoc. Like in the driver load code we don't
	 * bother with the tiny race here where we might loose hotplug
	 * notifications.
	 * */
	intel_hpd_init(dev_priv);
	/* Config may have changed between suspend and resume */
	drm_helper_hpd_irq_event(dev);
816

817 818
	intel_opregion_init(dev);

819
	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
820

821 822 823
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_DONE;
	mutex_unlock(&dev_priv->modeset_restore_lock);
824

825 826
	intel_opregion_notify_adapter(dev, PCI_D0);

827 828
	drm_kms_helper_poll_enable(dev);

829
	return 0;
830 831
}

832
static int i915_drm_resume_early(struct drm_device *dev)
833
{
834
	struct drm_i915_private *dev_priv = dev->dev_private;
835
	int ret = 0;
836

837 838 839 840 841 842 843 844 845
	/*
	 * We have a resume ordering issue with the snd-hda driver also
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an early
	 * resume hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
846 847 848 849 850
	if (pci_enable_device(dev->pdev))
		return -EIO;

	pci_set_master(dev->pdev);

851
	if (IS_VALLEYVIEW(dev_priv))
852
		ret = vlv_resume_prepare(dev_priv, false);
853
	if (ret)
854 855
		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
			  ret);
856 857

	intel_uncore_early_sanitize(dev, true);
858

859 860
	if (IS_BROXTON(dev))
		ret = bxt_resume_prepare(dev_priv);
861
	else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
862
		ret = skl_resume_prepare(dev_priv);
863 864
	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
		hsw_disable_pc8(dev_priv);
865

866
	intel_uncore_sanitize(dev);
867
	intel_power_domains_init_hw(dev_priv, true);
868 869

	return ret;
870 871
}

872
int i915_resume_switcheroo(struct drm_device *dev)
873
{
874
	int ret;
875

876 877 878
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

879
	ret = i915_drm_resume_early(dev);
880 881 882
	if (ret)
		return ret;

883 884 885
	return i915_drm_resume(dev);
}

886
/**
887
 * i915_reset - reset chip after a hang
888 889 890 891 892 893 894 895 896 897 898 899 900
 * @dev: drm device to reset
 *
 * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 * reset or otherwise an error code.
 *
 * Procedure is fairly simple:
 *   - reset the chip using the reset reg
 *   - re-init context state
 *   - re-init hardware status page
 *   - re-init ring buffer
 *   - re-init interrupt state
 *   - re-init display
 */
901
int i915_reset(struct drm_device *dev)
902
{
903
	struct drm_i915_private *dev_priv = dev->dev_private;
904
	bool simulated;
905
	int ret;
906

907 908
	intel_reset_gt_powersave(dev);

909
	mutex_lock(&dev->struct_mutex);
910

911
	i915_gem_reset(dev);
912

913 914
	simulated = dev_priv->gpu_error.stop_rings != 0;

915 916 917 918 919 920 921
	ret = intel_gpu_reset(dev);

	/* Also reset the gpu hangman. */
	if (simulated) {
		DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
		dev_priv->gpu_error.stop_rings = 0;
		if (ret == -ENODEV) {
922 923
			DRM_INFO("Reset not implemented, but ignoring "
				 "error for simulated gpu hangs\n");
924 925
			ret = 0;
		}
926
	}
927

928 929 930
	if (i915_stop_ring_allow_warn(dev_priv))
		pr_notice("drm/i915: Resetting chip after gpu hang\n");

931
	if (ret) {
932
		DRM_ERROR("Failed to reset chip: %i\n", ret);
933
		mutex_unlock(&dev->struct_mutex);
934
		return ret;
935 936
	}

937 938
	intel_overlay_reset(dev_priv);

939 940 941 942 943 944 945 946 947 948 949 950 951 952
	/* Ok, now get things going again... */

	/*
	 * Everything depends on having the GTT running, so we need to start
	 * there.  Fortunately we don't need to do this unless we reset the
	 * chip at a PCI level.
	 *
	 * Next we need to restore the context, but we don't use those
	 * yet either...
	 *
	 * Ring buffer needs to be re-initialized in the KMS case, or if X
	 * was running at the time of the reset (i.e. we weren't VT
	 * switched away).
	 */
953

954 955
	/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
	dev_priv->gpu_error.reload_in_reset = true;
956

957
	ret = i915_gem_init_hw(dev);
958

959
	dev_priv->gpu_error.reload_in_reset = false;
960

961 962 963 964
	mutex_unlock(&dev->struct_mutex);
	if (ret) {
		DRM_ERROR("Failed hw init on reset %d\n", ret);
		return ret;
965 966
	}

967 968 969 970 971 972 973 974 975
	/*
	 * rps/rc6 re-init is necessary to restore state lost after the
	 * reset and the re-install of gt irqs. Skip for ironlake per
	 * previous concerns that it doesn't respond well to some forms
	 * of re-init after reset.
	 */
	if (INTEL_INFO(dev)->gen > 5)
		intel_enable_gt_powersave(dev);

976 977 978
	return 0;
}

979
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
980
{
981 982 983
	struct intel_device_info *intel_info =
		(struct intel_device_info *) ent->driver_data;

984
	if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
985 986 987 988 989
		DRM_INFO("This hardware requires preliminary hardware support.\n"
			 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
		return -ENODEV;
	}

990 991 992 993 994 995 996 997
	/* Only bind to function 0 of the device. Early generations
	 * used function 1 as a placeholder for multi-head. This causes
	 * us confusion instead, especially on the systems where both
	 * functions have the same PCI-ID!
	 */
	if (PCI_FUNC(pdev->devfn))
		return -ENODEV;

998
	return drm_get_pci_dev(pdev, ent, &driver);
999 1000 1001 1002 1003 1004 1005 1006 1007 1008
}

static void
i915_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	drm_put_dev(dev);
}

1009
static int i915_pm_suspend(struct device *dev)
1010
{
1011 1012
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);
1013

1014 1015 1016 1017
	if (!drm_dev || !drm_dev->dev_private) {
		dev_err(dev, "DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}
1018

1019 1020 1021
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

1022
	return i915_drm_suspend(drm_dev);
1023 1024 1025 1026
}

static int i915_pm_suspend_late(struct device *dev)
{
I
Imre Deak 已提交
1027
	struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1028 1029

	/*
D
Damien Lespiau 已提交
1030
	 * We have a suspend ordering issue with the snd-hda driver also
1031 1032 1033 1034 1035 1036 1037 1038 1039
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an late
	 * suspend hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
1040

1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051
	return i915_drm_suspend_late(drm_dev, false);
}

static int i915_pm_poweroff_late(struct device *dev)
{
	struct drm_device *drm_dev = dev_to_i915(dev)->dev;

	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	return i915_drm_suspend_late(drm_dev, true);
1052 1053
}

1054 1055
static int i915_pm_resume_early(struct device *dev)
{
I
Imre Deak 已提交
1056
	struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1057

1058 1059 1060
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

1061
	return i915_drm_resume_early(drm_dev);
1062 1063
}

1064
static int i915_pm_resume(struct device *dev)
1065
{
I
Imre Deak 已提交
1066
	struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1067

1068 1069 1070
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

1071
	return i915_drm_resume(drm_dev);
1072 1073
}

1074 1075 1076 1077 1078
static int skl_suspend_complete(struct drm_i915_private *dev_priv)
{
	return 0;
}

1079
static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1080
{
P
Paulo Zanoni 已提交
1081
	hsw_enable_pc8(dev_priv);
1082 1083

	return 0;
1084 1085
}

1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117
static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;

	/* TODO: when DC5 support is added disable DC5 here. */

	broxton_ddi_phy_uninit(dev);
	broxton_uninit_cdclk(dev);
	bxt_enable_dc9(dev_priv);

	return 0;
}

static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;

	/* TODO: when CSR FW support is added make sure the FW is loaded */

	bxt_disable_dc9(dev_priv);

	/*
	 * TODO: when DC5 support is added enable DC5 here if the CSR FW
	 * is available.
	 */
	broxton_init_cdclk(dev);
	broxton_ddi_phy_init(dev);
	intel_prepare_ddi(dev);

	return 0;
}

1118 1119 1120 1121 1122
static int skl_resume_prepare(struct drm_i915_private *dev_priv)
{
	return 0;
}

1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161
/*
 * Save all Gunit registers that may be lost after a D3 and a subsequent
 * S0i[R123] transition. The list of registers needing a save/restore is
 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
 * registers in the following way:
 * - Driver: saved/restored by the driver
 * - Punit : saved/restored by the Punit firmware
 * - No, w/o marking: no need to save/restore, since the register is R/O or
 *                    used internally by the HW in a way that doesn't depend
 *                    keeping the content across a suspend/resume.
 * - Debug : used for debugging
 *
 * We save/restore all registers marked with 'Driver', with the following
 * exceptions:
 * - Registers out of use, including also registers marked with 'Debug'.
 *   These have no effect on the driver's operation, so we don't save/restore
 *   them to reduce the overhead.
 * - Registers that are fully setup by an initialization function called from
 *   the resume path. For example many clock gating and RPS/RC6 registers.
 * - Registers that provide the right functionality with their reset defaults.
 *
 * TODO: Except for registers that based on the above 3 criteria can be safely
 * ignored, we save/restore all others, practically treating the HW context as
 * a black-box for the driver. Further investigation is needed to reduce the
 * saved/restored registers even further, by following the same 3 criteria.
 */
static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	int i;

	/* GAM 0x4000-0x4770 */
	s->wr_watermark		= I915_READ(GEN7_WR_WATERMARK);
	s->gfx_prio_ctrl	= I915_READ(GEN7_GFX_PRIO_CTRL);
	s->arb_mode		= I915_READ(ARB_MODE);
	s->gfx_pend_tlb0	= I915_READ(GEN7_GFX_PEND_TLB0);
	s->gfx_pend_tlb1	= I915_READ(GEN7_GFX_PEND_TLB1);

	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1162
		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1163 1164

	s->media_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1165
	s->gfx_max_req_count	= I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205

	s->render_hwsp		= I915_READ(RENDER_HWS_PGA_GEN7);
	s->ecochk		= I915_READ(GAM_ECOCHK);
	s->bsd_hwsp		= I915_READ(BSD_HWS_PGA_GEN7);
	s->blt_hwsp		= I915_READ(BLT_HWS_PGA_GEN7);

	s->tlb_rd_addr		= I915_READ(GEN7_TLB_RD_ADDR);

	/* MBC 0x9024-0x91D0, 0x8500 */
	s->g3dctl		= I915_READ(VLV_G3DCTL);
	s->gsckgctl		= I915_READ(VLV_GSCKGCTL);
	s->mbctl		= I915_READ(GEN6_MBCTL);

	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	s->ucgctl1		= I915_READ(GEN6_UCGCTL1);
	s->ucgctl3		= I915_READ(GEN6_UCGCTL3);
	s->rcgctl1		= I915_READ(GEN6_RCGCTL1);
	s->rcgctl2		= I915_READ(GEN6_RCGCTL2);
	s->rstctl		= I915_READ(GEN6_RSTCTL);
	s->misccpctl		= I915_READ(GEN7_MISCCPCTL);

	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	s->gfxpause		= I915_READ(GEN6_GFXPAUSE);
	s->rpdeuhwtc		= I915_READ(GEN6_RPDEUHWTC);
	s->rpdeuc		= I915_READ(GEN6_RPDEUC);
	s->ecobus		= I915_READ(ECOBUS);
	s->pwrdwnupctl		= I915_READ(VLV_PWRDWNUPCTL);
	s->rp_down_timeout	= I915_READ(GEN6_RP_DOWN_TIMEOUT);
	s->rp_deucsw		= I915_READ(GEN6_RPDEUCSW);
	s->rcubmabdtmr		= I915_READ(GEN6_RCUBMABDTMR);
	s->rcedata		= I915_READ(VLV_RCEDATA);
	s->spare2gh		= I915_READ(VLV_SPAREG2H);

	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	s->gt_imr		= I915_READ(GTIMR);
	s->gt_ier		= I915_READ(GTIER);
	s->pm_imr		= I915_READ(GEN6_PMIMR);
	s->pm_ier		= I915_READ(GEN6_PMIER);

	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1206
		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217

	/* GT SA CZ domain, 0x100000-0x138124 */
	s->tilectl		= I915_READ(TILECTL);
	s->gt_fifoctl		= I915_READ(GTFIFOCTL);
	s->gtlc_wake_ctrl	= I915_READ(VLV_GTLC_WAKE_CTRL);
	s->gtlc_survive		= I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	s->pmwgicz		= I915_READ(VLV_PMWGICZ);

	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
1218
	s->pcbr			= I915_READ(VLV_PCBR);
1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243
	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);

	/*
	 * Not saving any of:
	 * DFT,		0x9800-0x9EC0
	 * SARB,	0xB000-0xB1FC
	 * GAC,		0x5208-0x524C, 0x14000-0x14C000
	 * PCI CFG
	 */
}

static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	u32 val;
	int i;

	/* GAM 0x4000-0x4770 */
	I915_WRITE(GEN7_WR_WATERMARK,	s->wr_watermark);
	I915_WRITE(GEN7_GFX_PRIO_CTRL,	s->gfx_prio_ctrl);
	I915_WRITE(ARB_MODE,		s->arb_mode | (0xffff << 16));
	I915_WRITE(GEN7_GFX_PEND_TLB0,	s->gfx_pend_tlb0);
	I915_WRITE(GEN7_GFX_PEND_TLB1,	s->gfx_pend_tlb1);

	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1244
		I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1245 1246

	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1247
	I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287

	I915_WRITE(RENDER_HWS_PGA_GEN7,	s->render_hwsp);
	I915_WRITE(GAM_ECOCHK,		s->ecochk);
	I915_WRITE(BSD_HWS_PGA_GEN7,	s->bsd_hwsp);
	I915_WRITE(BLT_HWS_PGA_GEN7,	s->blt_hwsp);

	I915_WRITE(GEN7_TLB_RD_ADDR,	s->tlb_rd_addr);

	/* MBC 0x9024-0x91D0, 0x8500 */
	I915_WRITE(VLV_G3DCTL,		s->g3dctl);
	I915_WRITE(VLV_GSCKGCTL,	s->gsckgctl);
	I915_WRITE(GEN6_MBCTL,		s->mbctl);

	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	I915_WRITE(GEN6_UCGCTL1,	s->ucgctl1);
	I915_WRITE(GEN6_UCGCTL3,	s->ucgctl3);
	I915_WRITE(GEN6_RCGCTL1,	s->rcgctl1);
	I915_WRITE(GEN6_RCGCTL2,	s->rcgctl2);
	I915_WRITE(GEN6_RSTCTL,		s->rstctl);
	I915_WRITE(GEN7_MISCCPCTL,	s->misccpctl);

	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	I915_WRITE(GEN6_GFXPAUSE,	s->gfxpause);
	I915_WRITE(GEN6_RPDEUHWTC,	s->rpdeuhwtc);
	I915_WRITE(GEN6_RPDEUC,		s->rpdeuc);
	I915_WRITE(ECOBUS,		s->ecobus);
	I915_WRITE(VLV_PWRDWNUPCTL,	s->pwrdwnupctl);
	I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
	I915_WRITE(GEN6_RPDEUCSW,	s->rp_deucsw);
	I915_WRITE(GEN6_RCUBMABDTMR,	s->rcubmabdtmr);
	I915_WRITE(VLV_RCEDATA,		s->rcedata);
	I915_WRITE(VLV_SPAREG2H,	s->spare2gh);

	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	I915_WRITE(GTIMR,		s->gt_imr);
	I915_WRITE(GTIER,		s->gt_ier);
	I915_WRITE(GEN6_PMIMR,		s->pm_imr);
	I915_WRITE(GEN6_PMIER,		s->pm_ier);

	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1288
		I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312

	/* GT SA CZ domain, 0x100000-0x138124 */
	I915_WRITE(TILECTL,			s->tilectl);
	I915_WRITE(GTFIFOCTL,			s->gt_fifoctl);
	/*
	 * Preserve the GT allow wake and GFX force clock bit, they are not
	 * be restored, as they are used to control the s0ix suspend/resume
	 * sequence by the caller.
	 */
	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= VLV_GTLC_ALLOWWAKEREQ;
	val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= VLV_GFX_CLK_FORCE_ON_BIT;
	val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);

	I915_WRITE(VLV_PMWGICZ,			s->pmwgicz);

	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
1313
	I915_WRITE(VLV_PCBR,			s->pcbr);
1314 1315 1316
	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
}

1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
{
	u32 val;
	int err;

#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
	if (force_on)
		val |= VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);

	if (!force_on)
		return 0;

1333
	err = wait_for(COND, 20);
1334 1335 1336 1337 1338 1339 1340 1341
	if (err)
		DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
			  I915_READ(VLV_GTLC_SURVIVABILITY_REG));

	return err;
#undef COND
}

1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401
static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
{
	u32 val;
	int err = 0;

	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= ~VLV_GTLC_ALLOWWAKEREQ;
	if (allow)
		val |= VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
	POSTING_READ(VLV_GTLC_WAKE_CTRL);

#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
	      allow)
	err = wait_for(COND, 1);
	if (err)
		DRM_ERROR("timeout disabling GT waking\n");
	return err;
#undef COND
}

static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
				 bool wait_for_on)
{
	u32 mask;
	u32 val;
	int err;

	mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
	val = wait_for_on ? mask : 0;
#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
	if (COND)
		return 0;

	DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
			wait_for_on ? "on" : "off",
			I915_READ(VLV_GTLC_PW_STATUS));

	/*
	 * RC6 transitioning can be delayed up to 2 msec (see
	 * valleyview_enable_rps), use 3 msec for safety.
	 */
	err = wait_for(COND, 3);
	if (err)
		DRM_ERROR("timeout waiting for GT wells to go %s\n",
			  wait_for_on ? "on" : "off");

	return err;
#undef COND
}

static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
{
	if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
		return;

	DRM_ERROR("GT register access while GT waking disabled\n");
	I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
}

1402
static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424
{
	u32 mask;
	int err;

	/*
	 * Bspec defines the following GT well on flags as debug only, so
	 * don't treat them as hard failures.
	 */
	(void)vlv_wait_for_gt_wells(dev_priv, false);

	mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
	WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);

	vlv_check_no_gt_access(dev_priv);

	err = vlv_force_gfx_clock(dev_priv, true);
	if (err)
		goto err1;

	err = vlv_allow_gt_wake(dev_priv, false);
	if (err)
		goto err2;
1425 1426 1427

	if (!IS_CHERRYVIEW(dev_priv->dev))
		vlv_save_gunit_s0ix_state(dev_priv);
1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443

	err = vlv_force_gfx_clock(dev_priv, false);
	if (err)
		goto err2;

	return 0;

err2:
	/* For safety always re-enable waking and disable gfx clock forcing */
	vlv_allow_gt_wake(dev_priv, true);
err1:
	vlv_force_gfx_clock(dev_priv, false);

	return err;
}

1444 1445
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
				bool rpm_resume)
1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457
{
	struct drm_device *dev = dev_priv->dev;
	int err;
	int ret;

	/*
	 * If any of the steps fail just try to continue, that's the best we
	 * can do at this point. Return the first error code (which will also
	 * leave RPM permanently disabled).
	 */
	ret = vlv_force_gfx_clock(dev_priv, true);

1458 1459
	if (!IS_CHERRYVIEW(dev_priv->dev))
		vlv_restore_gunit_s0ix_state(dev_priv);
1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470

	err = vlv_allow_gt_wake(dev_priv, true);
	if (!ret)
		ret = err;

	err = vlv_force_gfx_clock(dev_priv, false);
	if (!ret)
		ret = err;

	vlv_check_no_gt_access(dev_priv);

1471 1472 1473 1474
	if (rpm_resume) {
		intel_init_clock_gating(dev);
		i915_gem_restore_fences(dev);
	}
1475 1476 1477 1478

	return ret;
}

1479
static int intel_runtime_suspend(struct device *device)
1480 1481 1482 1483
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_i915_private *dev_priv = dev->dev_private;
1484
	int ret;
1485

1486
	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1487 1488
		return -ENODEV;

1489 1490 1491
	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
		return -ENODEV;

1492 1493
	DRM_DEBUG_KMS("Suspending device\n");

1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517
	/*
	 * We could deadlock here in case another thread holding struct_mutex
	 * calls RPM suspend concurrently, since the RPM suspend will wait
	 * first for this RPM suspend to finish. In this case the concurrent
	 * RPM resume will be followed by its RPM suspend counterpart. Still
	 * for consistency return -EAGAIN, which will reschedule this suspend.
	 */
	if (!mutex_trylock(&dev->struct_mutex)) {
		DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
		/*
		 * Bump the expiration timestamp, otherwise the suspend won't
		 * be rescheduled.
		 */
		pm_runtime_mark_last_busy(device);

		return -EAGAIN;
	}
	/*
	 * We are safe here against re-faults, since the fault handler takes
	 * an RPM reference.
	 */
	i915_gem_release_all_mmaps(dev_priv);
	mutex_unlock(&dev->struct_mutex);

1518 1519
	intel_guc_suspend(dev);

1520
	intel_suspend_gt_powersave(dev);
1521
	intel_runtime_pm_disable_interrupts(dev_priv);
1522

1523
	ret = intel_suspend_complete(dev_priv);
1524 1525
	if (ret) {
		DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1526
		intel_runtime_pm_enable_interrupts(dev_priv);
1527 1528 1529

		return ret;
	}
1530

1531
	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1532
	intel_uncore_forcewake_reset(dev, false);
1533
	dev_priv->pm.suspended = true;
1534 1535

	/*
1536 1537
	 * FIXME: We really should find a document that references the arguments
	 * used below!
1538
	 */
1539 1540 1541 1542 1543 1544 1545 1546 1547
	if (IS_BROADWELL(dev)) {
		/*
		 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
		 * being detected, and the call we do at intel_runtime_resume()
		 * won't be able to restore them. Since PCI_D3hot matches the
		 * actual specification and appears to be working, use it.
		 */
		intel_opregion_notify_adapter(dev, PCI_D3hot);
	} else {
1548 1549 1550 1551 1552 1553 1554 1555 1556
		/*
		 * current versions of firmware which depend on this opregion
		 * notification have repurposed the D1 definition to mean
		 * "runtime suspended" vs. what you would normally expect (D3)
		 * to distinguish it from notifications that might be sent via
		 * the suspend path.
		 */
		intel_opregion_notify_adapter(dev, PCI_D1);
	}
1557

1558
	assert_forcewakes_inactive(dev_priv);
1559

1560
	DRM_DEBUG_KMS("Device suspended\n");
1561 1562 1563
	return 0;
}

1564
static int intel_runtime_resume(struct device *device)
1565 1566 1567 1568
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_i915_private *dev_priv = dev->dev_private;
1569
	int ret = 0;
1570

1571 1572
	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
		return -ENODEV;
1573 1574 1575

	DRM_DEBUG_KMS("Resuming device\n");

1576
	intel_opregion_notify_adapter(dev, PCI_D0);
1577 1578
	dev_priv->pm.suspended = false;

1579 1580
	intel_guc_resume(dev);

1581 1582
	if (IS_GEN6(dev_priv))
		intel_init_pch_refclk(dev);
1583 1584 1585

	if (IS_BROXTON(dev))
		ret = bxt_resume_prepare(dev_priv);
1586
	else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1587
		ret = skl_resume_prepare(dev_priv);
1588 1589 1590 1591 1592
	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
		hsw_disable_pc8(dev_priv);
	else if (IS_VALLEYVIEW(dev_priv))
		ret = vlv_resume_prepare(dev_priv, true);

1593 1594 1595 1596
	/*
	 * No point of rolling back things in case of an error, as the best
	 * we can do is to hope that things will still work (and disable RPM).
	 */
1597 1598 1599
	i915_gem_init_swizzling(dev);
	gen6_update_ring_freq(dev);

1600
	intel_runtime_pm_enable_interrupts(dev_priv);
1601 1602 1603 1604 1605 1606 1607 1608 1609

	/*
	 * On VLV/CHV display interrupts are part of the display
	 * power well, so hpd is reinitialized from there. For
	 * everyone else do it here.
	 */
	if (!IS_VALLEYVIEW(dev_priv))
		intel_hpd_init(dev_priv);

1610
	intel_enable_gt_powersave(dev);
1611

1612 1613 1614 1615 1616 1617
	if (ret)
		DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
	else
		DRM_DEBUG_KMS("Device resumed\n");

	return ret;
1618 1619
}

1620 1621 1622 1623
/*
 * This function implements common functionality of runtime and system
 * suspend sequence.
 */
1624 1625 1626 1627
static int intel_suspend_complete(struct drm_i915_private *dev_priv)
{
	int ret;

1628
	if (IS_BROXTON(dev_priv))
1629
		ret = bxt_suspend_complete(dev_priv);
1630
	else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1631
		ret = skl_suspend_complete(dev_priv);
1632
	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1633
		ret = hsw_suspend_complete(dev_priv);
1634
	else if (IS_VALLEYVIEW(dev_priv))
1635
		ret = vlv_suspend_complete(dev_priv);
1636 1637
	else
		ret = 0;
1638 1639 1640 1641

	return ret;
}

1642
static const struct dev_pm_ops i915_pm_ops = {
1643 1644 1645 1646
	/*
	 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
	 * PMSG_RESUME]
	 */
1647
	.suspend = i915_pm_suspend,
1648 1649
	.suspend_late = i915_pm_suspend_late,
	.resume_early = i915_pm_resume_early,
1650
	.resume = i915_pm_resume,
1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666

	/*
	 * S4 event handlers
	 * @freeze, @freeze_late    : called (1) before creating the
	 *                            hibernation image [PMSG_FREEZE] and
	 *                            (2) after rebooting, before restoring
	 *                            the image [PMSG_QUIESCE]
	 * @thaw, @thaw_early       : called (1) after creating the hibernation
	 *                            image, before writing it [PMSG_THAW]
	 *                            and (2) after failing to create or
	 *                            restore the image [PMSG_RECOVER]
	 * @poweroff, @poweroff_late: called after writing the hibernation
	 *                            image, before rebooting [PMSG_HIBERNATE]
	 * @restore, @restore_early : called after rebooting and restoring the
	 *                            hibernation image [PMSG_RESTORE]
	 */
1667 1668 1669 1670 1671
	.freeze = i915_pm_suspend,
	.freeze_late = i915_pm_suspend_late,
	.thaw_early = i915_pm_resume_early,
	.thaw = i915_pm_resume,
	.poweroff = i915_pm_suspend,
1672
	.poweroff_late = i915_pm_poweroff_late,
1673
	.restore_early = i915_pm_resume_early,
1674
	.restore = i915_pm_resume,
1675 1676

	/* S0ix (via runtime suspend) event handlers */
1677 1678
	.runtime_suspend = intel_runtime_suspend,
	.runtime_resume = intel_runtime_resume,
1679 1680
};

1681
static const struct vm_operations_struct i915_gem_vm_ops = {
1682
	.fault = i915_gem_fault,
1683 1684
	.open = drm_gem_vm_open,
	.close = drm_gem_vm_close,
1685 1686
};

1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700
static const struct file_operations i915_driver_fops = {
	.owner = THIS_MODULE,
	.open = drm_open,
	.release = drm_release,
	.unlocked_ioctl = drm_ioctl,
	.mmap = drm_gem_mmap,
	.poll = drm_poll,
	.read = drm_read,
#ifdef CONFIG_COMPAT
	.compat_ioctl = i915_compat_ioctl,
#endif
	.llseek = noop_llseek,
};

L
Linus Torvalds 已提交
1701
static struct drm_driver driver = {
1702 1703
	/* Don't use MTRRs here; the Xserver or userspace app should
	 * deal with them for Intel hardware.
D
Dave Airlie 已提交
1704
	 */
1705
	.driver_features =
1706
	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1707
	    DRIVER_RENDER | DRIVER_MODESET,
1708
	.load = i915_driver_load,
J
Jesse Barnes 已提交
1709
	.unload = i915_driver_unload,
1710
	.open = i915_driver_open,
1711 1712
	.lastclose = i915_driver_lastclose,
	.preclose = i915_driver_preclose,
1713
	.postclose = i915_driver_postclose,
1714
	.set_busid = drm_pci_set_busid,
1715

1716
#if defined(CONFIG_DEBUG_FS)
1717 1718
	.debugfs_init = i915_debugfs_init,
	.debugfs_cleanup = i915_debugfs_cleanup,
1719
#endif
1720
	.gem_free_object = i915_gem_free_object,
1721
	.gem_vm_ops = &i915_gem_vm_ops,
1722 1723 1724 1725 1726 1727

	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	.gem_prime_export = i915_gem_prime_export,
	.gem_prime_import = i915_gem_prime_import,

1728
	.dumb_create = i915_gem_dumb_create,
1729
	.dumb_map_offset = i915_gem_mmap_gtt,
1730
	.dumb_destroy = drm_gem_dumb_destroy,
L
Linus Torvalds 已提交
1731
	.ioctls = i915_ioctls,
1732
	.fops = &i915_driver_fops,
1733 1734 1735 1736 1737 1738
	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
	.date = DRIVER_DATE,
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
L
Linus Torvalds 已提交
1739 1740
};

1741 1742 1743 1744 1745 1746 1747 1748
static struct pci_driver i915_pci_driver = {
	.name = DRIVER_NAME,
	.id_table = pciidlist,
	.probe = i915_pci_probe,
	.remove = i915_pci_remove,
	.driver.pm = &i915_pm_ops,
};

L
Linus Torvalds 已提交
1749 1750 1751
static int __init i915_init(void)
{
	driver.num_ioctls = i915_max_ioctl;
J
Jesse Barnes 已提交
1752 1753

	/*
1754 1755 1756
	 * Enable KMS by default, unless explicitly overriden by
	 * either the i915.modeset prarameter or by the
	 * vga_text_mode_force boot option.
J
Jesse Barnes 已提交
1757
	 */
1758 1759 1760

	if (i915.modeset == 0)
		driver.driver_features &= ~DRIVER_MODESET;
J
Jesse Barnes 已提交
1761 1762

#ifdef CONFIG_VGA_CONSOLE
1763
	if (vgacon_text_force() && i915.modeset == -1)
J
Jesse Barnes 已提交
1764 1765 1766
		driver.driver_features &= ~DRIVER_MODESET;
#endif

D
Daniel Vetter 已提交
1767 1768
	if (!(driver.driver_features & DRIVER_MODESET)) {
		/* Silently fail loading to not upset userspace. */
1769
		DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
D
Daniel Vetter 已提交
1770 1771
		return 0;
	}
1772

1773
	if (i915.nuclear_pageflip)
1774 1775
		driver.driver_features |= DRIVER_ATOMIC;

1776
	return drm_pci_init(&driver, &i915_pci_driver);
L
Linus Torvalds 已提交
1777 1778 1779 1780
}

static void __exit i915_exit(void)
{
1781 1782 1783
	if (!(driver.driver_features & DRIVER_MODESET))
		return; /* Never loaded a driver. */

1784
	drm_pci_exit(&driver, &i915_pci_driver);
L
Linus Torvalds 已提交
1785 1786 1787 1788 1789
}

module_init(i915_init);
module_exit(i915_exit);

1790
MODULE_AUTHOR("Tungsten Graphics, Inc.");
1791
MODULE_AUTHOR("Intel Corporation");
1792

D
Dave Airlie 已提交
1793
MODULE_DESCRIPTION(DRIVER_DESC);
L
Linus Torvalds 已提交
1794
MODULE_LICENSE("GPL and additional rights");