i915_drv.c 43.6 KB
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/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#include <linux/device.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#include <linux/console.h>
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#include <linux/module.h>
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#include <drm/drm_crtc_helper.h>
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static struct drm_driver driver;

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#define GEN_DEFAULT_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
	.dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }

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#define GEN_CHV_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  CHV_PIPE_C_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   CHV_TRANSCODER_C_OFFSET, }, \
	.dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \
			  CHV_DPLL_C_OFFSET }, \
	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \
			     CHV_DPLL_C_MD_OFFSET }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
			     CHV_PALETTE_C_OFFSET }
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#define CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }

#define IVB_CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }

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static const struct intel_device_info intel_i830_info = {
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	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_845g_info = {
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	.gen = 2, .num_pipes = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i85x_info = {
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	.gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
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	.cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i865g_info = {
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	.gen = 2, .num_pipes = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i915g_info = {
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	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};
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static const struct intel_device_info intel_i915gm_info = {
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	.gen = 3, .is_mobile = 1, .num_pipes = 2,
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	.cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.supports_tv = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};
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static const struct intel_device_info intel_i945g_info = {
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	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};
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static const struct intel_device_info intel_i945gm_info = {
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	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
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	.has_hotplug = 1, .cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.supports_tv = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i965g_info = {
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	.gen = 4, .is_broadwater = 1, .num_pipes = 2,
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	.has_hotplug = 1,
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	.has_overlay = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i965gm_info = {
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	.gen = 4, .is_crestline = 1, .num_pipes = 2,
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	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
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	.has_overlay = 1,
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	.supports_tv = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_g33_info = {
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	.gen = 3, .is_g33 = 1, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_overlay = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_g45_info = {
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	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
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	.has_pipe_cxsr = 1, .has_hotplug = 1,
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	.ring_mask = RENDER_RING | BSD_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_gm45_info = {
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	.gen = 4, .is_g4x = 1, .num_pipes = 2,
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	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
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	.has_pipe_cxsr = 1, .has_hotplug = 1,
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	.supports_tv = 1,
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	.ring_mask = RENDER_RING | BSD_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_pineview_info = {
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	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_overlay = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_ironlake_d_info = {
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	.gen = 5, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.ring_mask = RENDER_RING | BSD_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_ironlake_m_info = {
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	.gen = 5, .is_mobile = 1, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING | BSD_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_sandybridge_d_info = {
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	.gen = 6, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
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	.has_llc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_sandybridge_m_info = {
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	.gen = 6, .is_mobile = 1, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
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	.has_llc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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#define GEN7_FEATURES  \
	.gen = 7, .num_pipes = 3, \
	.need_gfx_hws = 1, .has_hotplug = 1, \
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	.has_fbc = 1, \
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
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	.has_llc = 1
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static const struct intel_device_info intel_ivybridge_d_info = {
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	GEN7_FEATURES,
	.is_ivybridge = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_ivybridge_m_info = {
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	GEN7_FEATURES,
	.is_ivybridge = 1,
	.is_mobile = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_ivybridge_q_info = {
	GEN7_FEATURES,
	.is_ivybridge = 1,
	.num_pipes = 0, /* legal, last one wins */
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_valleyview_m_info = {
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	GEN7_FEATURES,
	.is_mobile = 1,
	.num_pipes = 2,
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	.is_valleyview = 1,
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	.display_mmio_offset = VLV_DISPLAY_BASE,
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	.has_fbc = 0, /* legal, last one wins */
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	.has_llc = 0, /* legal, last one wins */
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_valleyview_d_info = {
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	GEN7_FEATURES,
	.num_pipes = 2,
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	.is_valleyview = 1,
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	.display_mmio_offset = VLV_DISPLAY_BASE,
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	.has_fbc = 0, /* legal, last one wins */
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	.has_llc = 0, /* legal, last one wins */
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_haswell_d_info = {
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	GEN7_FEATURES,
	.is_haswell = 1,
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	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_haswell_m_info = {
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	GEN7_FEATURES,
	.is_haswell = 1,
	.is_mobile = 1,
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	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_broadwell_d_info = {
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	.gen = 8, .num_pipes = 3,
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	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.has_llc = 1,
	.has_ddi = 1,
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	.has_fbc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_broadwell_m_info = {
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	.gen = 8, .is_mobile = 1, .num_pipes = 3,
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	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.has_llc = 1,
	.has_ddi = 1,
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	.has_fbc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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};

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static const struct intel_device_info intel_broadwell_gt3d_info = {
	.gen = 8, .num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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	.has_llc = 1,
	.has_ddi = 1,
	.has_fbc = 1,
	GEN_DEFAULT_PIPEOFFSETS,
};

static const struct intel_device_info intel_broadwell_gt3m_info = {
	.gen = 8, .is_mobile = 1, .num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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	.has_llc = 1,
	.has_ddi = 1,
	.has_fbc = 1,
	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_cherryview_info = {
	.is_preliminary = 1,
	.gen = 8, .num_pipes = 2,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.is_valleyview = 1,
	.display_mmio_offset = VLV_DISPLAY_BASE,
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	GEN_CHV_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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/*
 * Make sure any device matches here are from most specific to most
 * general.  For example, since the Quanta match is based on the subsystem
 * and subvendor IDs, we need it to come before the more general IVB
 * PCI ID matches, otherwise we'll use the wrong info struct above.
 */
#define INTEL_PCI_IDS \
	INTEL_I830_IDS(&intel_i830_info),	\
	INTEL_I845G_IDS(&intel_845g_info),	\
	INTEL_I85X_IDS(&intel_i85x_info),	\
	INTEL_I865G_IDS(&intel_i865g_info),	\
	INTEL_I915G_IDS(&intel_i915g_info),	\
	INTEL_I915GM_IDS(&intel_i915gm_info),	\
	INTEL_I945G_IDS(&intel_i945g_info),	\
	INTEL_I945GM_IDS(&intel_i945gm_info),	\
	INTEL_I965G_IDS(&intel_i965g_info),	\
	INTEL_G33_IDS(&intel_g33_info),		\
	INTEL_I965GM_IDS(&intel_i965gm_info),	\
	INTEL_GM45_IDS(&intel_gm45_info), 	\
	INTEL_G45_IDS(&intel_g45_info), 	\
	INTEL_PINEVIEW_IDS(&intel_pineview_info),	\
	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),	\
	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),	\
	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),	\
	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),	\
	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),	\
	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),	\
	INTEL_HSW_D_IDS(&intel_haswell_d_info), \
	INTEL_HSW_M_IDS(&intel_haswell_m_info), \
	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\
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	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\
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	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),	\
	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),	\
	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),	\
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	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
	INTEL_CHV_IDS(&intel_cherryview_info)
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static const struct pci_device_id pciidlist[] = {		/* aka */
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	INTEL_PCI_IDS,
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	{0, 0, 0}
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};

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#if defined(CONFIG_DRM_I915_KMS)
MODULE_DEVICE_TABLE(pci, pciidlist);
#endif

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void intel_detect_pch(struct drm_device *dev)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct pci_dev *pch = NULL;
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	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
	 * (which really amounts to a PCH but no South Display).
	 */
	if (INTEL_INFO(dev)->num_pipes == 0) {
		dev_priv->pch_type = PCH_NOP;
		return;
	}

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	/*
	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
	 * make graphics device passthrough work easy for VMM, that only
	 * need to expose ISA bridge to let driver know the real hardware
	 * underneath. This is a requirement from virtualization team.
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	 *
	 * In some virtualized environments (e.g. XEN), there is irrelevant
	 * ISA bridge in the system. To work reliably, we should scan trhough
	 * all the ISA bridge devices and check for the first match, instead
	 * of only checking the first one.
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	 */
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	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
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		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
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			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
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			dev_priv->pch_id = id;
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			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_IBX;
				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
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				WARN_ON(!IS_GEN5(dev));
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			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
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				dev_priv->pch_type = PCH_CPT;
				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
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				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
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			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
				/* PantherPoint is CPT compatible */
				dev_priv->pch_type = PCH_CPT;
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				DRM_DEBUG_KMS("Found PantherPoint PCH\n");
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				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
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			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
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				WARN_ON(!IS_HASWELL(dev));
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				WARN_ON(IS_ULT(dev));
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			} else if (IS_BROADWELL(dev)) {
				dev_priv->pch_type = PCH_LPT;
				dev_priv->pch_id =
					INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
				DRM_DEBUG_KMS("This is Broadwell, assuming "
					      "LynxPoint LP PCH\n");
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			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
				WARN_ON(!IS_HASWELL(dev));
				WARN_ON(!IS_ULT(dev));
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			} else
				continue;

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			break;
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		}
	}
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	if (!pch)
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		DRM_DEBUG_KMS("No PCH found.\n");

	pci_dev_put(pch);
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}

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bool i915_semaphore_is_enabled(struct drm_device *dev)
{
	if (INTEL_INFO(dev)->gen < 6)
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		return false;
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479 480
	if (i915.semaphores >= 0)
		return i915.semaphores;
481

482 483 484 485
	/* Until we get further testing... */
	if (IS_GEN8(dev))
		return false;

486
#ifdef CONFIG_INTEL_IOMMU
487
	/* Enable semaphores on SNB when IO remapping is off */
488 489 490
	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
		return false;
#endif
491

492
	return true;
493 494
}

495
static int i915_drm_freeze(struct drm_device *dev)
J
Jesse Barnes 已提交
496
{
497
	struct drm_i915_private *dev_priv = dev->dev_private;
498
	struct drm_crtc *crtc;
499

500 501
	intel_runtime_pm_get(dev_priv);

502 503 504 505 506
	/* ignore lid events during suspend */
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_SUSPENDED;
	mutex_unlock(&dev_priv->modeset_restore_lock);

507 508
	/* We do a lot of poking in a lot of registers, make sure they work
	 * properly. */
509
	intel_display_set_init_power(dev_priv, true);
510

511 512
	drm_kms_helper_poll_disable(dev);

J
Jesse Barnes 已提交
513 514
	pci_save_state(dev->pdev);

515
	/* If KMS is active, we do the leavevt stuff here */
516
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
517 518
		int error;

519
		error = i915_gem_suspend(dev);
520
		if (error) {
521
			dev_err(&dev->pdev->dev,
522 523 524
				"GEM idle failed, resume might fail\n");
			return error;
		}
525

526 527
		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);

528
		drm_irq_uninstall(dev);
529
		dev_priv->enable_hotplug_processing = false;
530 531 532 533
		/*
		 * Disable CRTCs directly since we want to preserve sw state
		 * for _thaw.
		 */
534
		mutex_lock(&dev->mode_config.mutex);
535
		for_each_crtc(dev, crtc)
536
			dev_priv->display.crtc_disable(crtc);
537
		mutex_unlock(&dev->mode_config.mutex);
538 539

		intel_modeset_suspend_hw(dev);
540 541
	}

542 543
	i915_gem_suspend_gtt_mappings(dev);

544 545
	i915_save_state(dev);

546
	intel_opregion_fini(dev);
547
	intel_uncore_fini(dev);
548

549
	console_lock();
550
	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
551 552
	console_unlock();

553 554
	dev_priv->suspend_count++;

555
	return 0;
556 557
}

558
int i915_suspend(struct drm_device *dev, pm_message_t state)
559 560 561 562 563 564 565 566 567 568 569 570
{
	int error;

	if (!dev || !dev->dev_private) {
		DRM_ERROR("dev: %p\n", dev);
		DRM_ERROR("DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}

	if (state.event == PM_EVENT_PRETHAW)
		return 0;

571 572 573

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
574

575 576 577 578
	error = i915_drm_freeze(dev);
	if (error)
		return error;

579 580 581 582 583
	if (state.event == PM_EVENT_SUSPEND) {
		/* Shut down the device */
		pci_disable_device(dev->pdev);
		pci_set_power_state(dev->pdev, PCI_D3hot);
	}
J
Jesse Barnes 已提交
584 585 586 587

	return 0;
}

588 589 590 591 592 593 594 595
void intel_console_resume(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private,
			     console_resume_work);
	struct drm_device *dev = dev_priv->dev;

	console_lock();
596
	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
597 598 599
	console_unlock();
}

600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617
static void intel_resume_hotplug(struct drm_device *dev)
{
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;

	mutex_lock(&mode_config->mutex);
	DRM_DEBUG_KMS("running encoder hotplug functions\n");

	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
		if (encoder->hot_plug)
			encoder->hot_plug(encoder);

	mutex_unlock(&mode_config->mutex);

	/* Just fire off a uevent and let userspace tell us what to do */
	drm_helper_hpd_irq_event(dev);
}

618
static int i915_drm_thaw_early(struct drm_device *dev)
J
Jesse Barnes 已提交
619
{
620
	struct drm_i915_private *dev_priv = dev->dev_private;
621

622
	intel_uncore_early_sanitize(dev);
623
	intel_uncore_sanitize(dev);
624 625 626 627 628 629 630 631
	intel_power_domains_init_hw(dev_priv);

	return 0;
}

static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
632 633 634 635 636 637 638 639

	if (drm_core_check_feature(dev, DRIVER_MODESET) &&
	    restore_gtt_mappings) {
		mutex_lock(&dev->struct_mutex);
		i915_gem_restore_gtt_mappings(dev);
		mutex_unlock(&dev->struct_mutex);
	}

640
	i915_restore_state(dev);
641
	intel_opregion_setup(dev);
642

643 644
	/* KMS EnterVT equivalent */
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
P
Paulo Zanoni 已提交
645
		intel_init_pch_refclk(dev);
646
		drm_mode_config_reset(dev);
647

648
		mutex_lock(&dev->struct_mutex);
649 650 651 652
		if (i915_gem_init_hw(dev)) {
			DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
			atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
		}
653
		mutex_unlock(&dev->struct_mutex);
654

655
		/* We need working interrupts for modeset enabling ... */
656
		drm_irq_install(dev, dev->pdev->irq);
657

658
		intel_modeset_init_hw(dev);
659 660 661 662

		drm_modeset_lock_all(dev);
		intel_modeset_setup_hw_state(dev, true);
		drm_modeset_unlock_all(dev);
663 664 665 666 667 668 669

		/*
		 * ... but also need to make sure that hotplug processing
		 * doesn't cause havoc. Like in the driver load code we don't
		 * bother with the tiny race here where we might loose hotplug
		 * notifications.
		 * */
670
		intel_hpd_init(dev);
671
		dev_priv->enable_hotplug_processing = true;
672 673
		/* Config may have changed between suspend and resume */
		intel_resume_hotplug(dev);
J
Jesse Barnes 已提交
674
	}
675

676 677
	intel_opregion_init(dev);

678 679 680 681 682 683
	/*
	 * The console lock can be pretty contented on resume due
	 * to all the printk activity.  Try to keep it out of the hot
	 * path of resume if possible.
	 */
	if (console_trylock()) {
684
		intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
685 686 687 688 689
		console_unlock();
	} else {
		schedule_work(&dev_priv->console_resume_work);
	}

690 691 692
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_DONE;
	mutex_unlock(&dev_priv->modeset_restore_lock);
693 694

	intel_runtime_pm_put(dev_priv);
695
	return 0;
696 697
}

698 699
static int i915_drm_thaw(struct drm_device *dev)
{
700
	if (drm_core_check_feature(dev, DRIVER_MODESET))
701
		i915_check_and_clear_faults(dev);
702

703
	return __i915_drm_thaw(dev, true);
704 705
}

706
static int i915_resume_early(struct drm_device *dev)
707
{
708 709 710
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

711 712 713 714 715 716 717 718 719
	/*
	 * We have a resume ordering issue with the snd-hda driver also
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an early
	 * resume hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
720 721 722 723 724
	if (pci_enable_device(dev->pdev))
		return -EIO;

	pci_set_master(dev->pdev);

725 726 727 728 729 730 731 732
	return i915_drm_thaw_early(dev);
}

int i915_resume(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

733 734
	/*
	 * Platforms with opregion should have sane BIOS, older ones (gen3 and
735 736
	 * earlier) need to restore the GTT mappings since the BIOS might clear
	 * all our scratch PTEs.
737
	 */
738
	ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
739 740 741 742 743
	if (ret)
		return ret;

	drm_kms_helper_poll_enable(dev);
	return 0;
J
Jesse Barnes 已提交
744 745
}

746 747 748 749 750 751 752 753
static int i915_resume_legacy(struct drm_device *dev)
{
	i915_resume_early(dev);
	i915_resume(dev);

	return 0;
}

754
/**
755
 * i915_reset - reset chip after a hang
756 757 758 759 760 761 762 763 764 765 766 767 768
 * @dev: drm device to reset
 *
 * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 * reset or otherwise an error code.
 *
 * Procedure is fairly simple:
 *   - reset the chip using the reset reg
 *   - re-init context state
 *   - re-init hardware status page
 *   - re-init ring buffer
 *   - re-init interrupt state
 *   - re-init display
 */
769
int i915_reset(struct drm_device *dev)
770
{
771
	struct drm_i915_private *dev_priv = dev->dev_private;
772
	bool simulated;
773
	int ret;
774

775
	if (!i915.reset)
C
Chris Wilson 已提交
776 777
		return 0;

778
	mutex_lock(&dev->struct_mutex);
779

780
	i915_gem_reset(dev);
781

782 783
	simulated = dev_priv->gpu_error.stop_rings != 0;

784 785 786 787 788 789 790
	ret = intel_gpu_reset(dev);

	/* Also reset the gpu hangman. */
	if (simulated) {
		DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
		dev_priv->gpu_error.stop_rings = 0;
		if (ret == -ENODEV) {
791 792
			DRM_INFO("Reset not implemented, but ignoring "
				 "error for simulated gpu hangs\n");
793 794
			ret = 0;
		}
795
	}
796

797
	if (ret) {
798
		DRM_ERROR("Failed to reset chip: %i\n", ret);
799
		mutex_unlock(&dev->struct_mutex);
800
		return ret;
801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817
	}

	/* Ok, now get things going again... */

	/*
	 * Everything depends on having the GTT running, so we need to start
	 * there.  Fortunately we don't need to do this unless we reset the
	 * chip at a PCI level.
	 *
	 * Next we need to restore the context, but we don't use those
	 * yet either...
	 *
	 * Ring buffer needs to be re-initialized in the KMS case, or if X
	 * was running at the time of the reset (i.e. we weren't VT
	 * switched away).
	 */
	if (drm_core_check_feature(dev, DRIVER_MODESET) ||
818 819
			!dev_priv->ums.mm_suspended) {
		dev_priv->ums.mm_suspended = 0;
820

821
		ret = i915_gem_init_hw(dev);
822
		mutex_unlock(&dev->struct_mutex);
823 824 825 826
		if (ret) {
			DRM_ERROR("Failed hw init on reset %d\n", ret);
			return ret;
		}
827

828 829 830 831 832
		/*
		 * FIXME: This is horribly race against concurrent pageflip and
		 * vblank wait ioctls since they can observe dev->irqs_disabled
		 * being false when they shouldn't be able to.
		 */
833
		drm_irq_uninstall(dev);
834
		drm_irq_install(dev, dev->pdev->irq);
J
Jeff McGee 已提交
835 836 837 838 839

		/* rps/rc6 re-init is necessary to restore state lost after the
		 * reset and the re-install of drm irq. Skip for ironlake per
		 * previous concerns that it doesn't respond well to some forms
		 * of re-init after reset. */
840
		if (INTEL_INFO(dev)->gen > 5)
841
			intel_reset_gt_powersave(dev);
J
Jeff McGee 已提交
842

843
		intel_hpd_init(dev);
844 845
	} else {
		mutex_unlock(&dev->struct_mutex);
846 847 848 849 850
	}

	return 0;
}

851
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
852
{
853 854 855
	struct intel_device_info *intel_info =
		(struct intel_device_info *) ent->driver_data;

856
	if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
857 858 859 860 861
		DRM_INFO("This hardware requires preliminary hardware support.\n"
			 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
		return -ENODEV;
	}

862 863 864 865 866 867 868 869
	/* Only bind to function 0 of the device. Early generations
	 * used function 1 as a placeholder for multi-head. This causes
	 * us confusion instead, especially on the systems where both
	 * functions have the same PCI-ID!
	 */
	if (PCI_FUNC(pdev->devfn))
		return -ENODEV;

D
Daniel Vetter 已提交
870
	driver.driver_features &= ~(DRIVER_USE_AGP);
871

872
	return drm_get_pci_dev(pdev, ent, &driver);
873 874 875 876 877 878 879 880 881 882
}

static void
i915_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	drm_put_dev(dev);
}

883
static int i915_pm_suspend(struct device *dev)
884
{
885 886
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);
887

888 889 890 891
	if (!drm_dev || !drm_dev->dev_private) {
		dev_err(dev, "DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}
892

893 894 895
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914
	return i915_drm_freeze(drm_dev);
}

static int i915_pm_suspend_late(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	/*
	 * We have a suspedn ordering issue with the snd-hda driver also
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an late
	 * suspend hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
915

916 917
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D3hot);
918

919
	return 0;
920 921
}

922 923 924 925 926 927 928 929
static int i915_pm_resume_early(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	return i915_resume_early(drm_dev);
}

930
static int i915_pm_resume(struct device *dev)
931
{
932 933 934 935
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	return i915_resume(drm_dev);
936 937
}

938
static int i915_pm_freeze(struct device *dev)
939
{
940 941 942 943 944 945 946 947 948
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	if (!drm_dev || !drm_dev->dev_private) {
		dev_err(dev, "DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}

	return i915_drm_freeze(drm_dev);
949 950
}

951 952 953 954 955 956 957 958
static int i915_pm_thaw_early(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	return i915_drm_thaw_early(drm_dev);
}

959
static int i915_pm_thaw(struct device *dev)
960
{
961 962 963 964
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	return i915_drm_thaw(drm_dev);
965 966
}

967
static int i915_pm_poweroff(struct device *dev)
968
{
969 970 971
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

972
	return i915_drm_freeze(drm_dev);
973 974
}

975
static int hsw_runtime_suspend(struct drm_i915_private *dev_priv)
976
{
P
Paulo Zanoni 已提交
977
	hsw_enable_pc8(dev_priv);
978 979

	return 0;
980 981
}

982
static int snb_runtime_resume(struct drm_i915_private *dev_priv)
983 984 985 986
{
	struct drm_device *dev = dev_priv->dev;

	intel_init_pch_refclk(dev);
987 988

	return 0;
989 990
}

991
static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
992
{
P
Paulo Zanoni 已提交
993
	hsw_disable_pc8(dev_priv);
994 995

	return 0;
996 997
}

998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189
/*
 * Save all Gunit registers that may be lost after a D3 and a subsequent
 * S0i[R123] transition. The list of registers needing a save/restore is
 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
 * registers in the following way:
 * - Driver: saved/restored by the driver
 * - Punit : saved/restored by the Punit firmware
 * - No, w/o marking: no need to save/restore, since the register is R/O or
 *                    used internally by the HW in a way that doesn't depend
 *                    keeping the content across a suspend/resume.
 * - Debug : used for debugging
 *
 * We save/restore all registers marked with 'Driver', with the following
 * exceptions:
 * - Registers out of use, including also registers marked with 'Debug'.
 *   These have no effect on the driver's operation, so we don't save/restore
 *   them to reduce the overhead.
 * - Registers that are fully setup by an initialization function called from
 *   the resume path. For example many clock gating and RPS/RC6 registers.
 * - Registers that provide the right functionality with their reset defaults.
 *
 * TODO: Except for registers that based on the above 3 criteria can be safely
 * ignored, we save/restore all others, practically treating the HW context as
 * a black-box for the driver. Further investigation is needed to reduce the
 * saved/restored registers even further, by following the same 3 criteria.
 */
static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	int i;

	/* GAM 0x4000-0x4770 */
	s->wr_watermark		= I915_READ(GEN7_WR_WATERMARK);
	s->gfx_prio_ctrl	= I915_READ(GEN7_GFX_PRIO_CTRL);
	s->arb_mode		= I915_READ(ARB_MODE);
	s->gfx_pend_tlb0	= I915_READ(GEN7_GFX_PEND_TLB0);
	s->gfx_pend_tlb1	= I915_READ(GEN7_GFX_PEND_TLB1);

	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);

	s->media_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
	s->gfx_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);

	s->render_hwsp		= I915_READ(RENDER_HWS_PGA_GEN7);
	s->ecochk		= I915_READ(GAM_ECOCHK);
	s->bsd_hwsp		= I915_READ(BSD_HWS_PGA_GEN7);
	s->blt_hwsp		= I915_READ(BLT_HWS_PGA_GEN7);

	s->tlb_rd_addr		= I915_READ(GEN7_TLB_RD_ADDR);

	/* MBC 0x9024-0x91D0, 0x8500 */
	s->g3dctl		= I915_READ(VLV_G3DCTL);
	s->gsckgctl		= I915_READ(VLV_GSCKGCTL);
	s->mbctl		= I915_READ(GEN6_MBCTL);

	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	s->ucgctl1		= I915_READ(GEN6_UCGCTL1);
	s->ucgctl3		= I915_READ(GEN6_UCGCTL3);
	s->rcgctl1		= I915_READ(GEN6_RCGCTL1);
	s->rcgctl2		= I915_READ(GEN6_RCGCTL2);
	s->rstctl		= I915_READ(GEN6_RSTCTL);
	s->misccpctl		= I915_READ(GEN7_MISCCPCTL);

	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	s->gfxpause		= I915_READ(GEN6_GFXPAUSE);
	s->rpdeuhwtc		= I915_READ(GEN6_RPDEUHWTC);
	s->rpdeuc		= I915_READ(GEN6_RPDEUC);
	s->ecobus		= I915_READ(ECOBUS);
	s->pwrdwnupctl		= I915_READ(VLV_PWRDWNUPCTL);
	s->rp_down_timeout	= I915_READ(GEN6_RP_DOWN_TIMEOUT);
	s->rp_deucsw		= I915_READ(GEN6_RPDEUCSW);
	s->rcubmabdtmr		= I915_READ(GEN6_RCUBMABDTMR);
	s->rcedata		= I915_READ(VLV_RCEDATA);
	s->spare2gh		= I915_READ(VLV_SPAREG2H);

	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	s->gt_imr		= I915_READ(GTIMR);
	s->gt_ier		= I915_READ(GTIER);
	s->pm_imr		= I915_READ(GEN6_PMIMR);
	s->pm_ier		= I915_READ(GEN6_PMIER);

	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);

	/* GT SA CZ domain, 0x100000-0x138124 */
	s->tilectl		= I915_READ(TILECTL);
	s->gt_fifoctl		= I915_READ(GTFIFOCTL);
	s->gtlc_wake_ctrl	= I915_READ(VLV_GTLC_WAKE_CTRL);
	s->gtlc_survive		= I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	s->pmwgicz		= I915_READ(VLV_PMWGICZ);

	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);

	/*
	 * Not saving any of:
	 * DFT,		0x9800-0x9EC0
	 * SARB,	0xB000-0xB1FC
	 * GAC,		0x5208-0x524C, 0x14000-0x14C000
	 * PCI CFG
	 */
}

static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	u32 val;
	int i;

	/* GAM 0x4000-0x4770 */
	I915_WRITE(GEN7_WR_WATERMARK,	s->wr_watermark);
	I915_WRITE(GEN7_GFX_PRIO_CTRL,	s->gfx_prio_ctrl);
	I915_WRITE(ARB_MODE,		s->arb_mode | (0xffff << 16));
	I915_WRITE(GEN7_GFX_PEND_TLB0,	s->gfx_pend_tlb0);
	I915_WRITE(GEN7_GFX_PEND_TLB1,	s->gfx_pend_tlb1);

	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
		I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);

	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);

	I915_WRITE(RENDER_HWS_PGA_GEN7,	s->render_hwsp);
	I915_WRITE(GAM_ECOCHK,		s->ecochk);
	I915_WRITE(BSD_HWS_PGA_GEN7,	s->bsd_hwsp);
	I915_WRITE(BLT_HWS_PGA_GEN7,	s->blt_hwsp);

	I915_WRITE(GEN7_TLB_RD_ADDR,	s->tlb_rd_addr);

	/* MBC 0x9024-0x91D0, 0x8500 */
	I915_WRITE(VLV_G3DCTL,		s->g3dctl);
	I915_WRITE(VLV_GSCKGCTL,	s->gsckgctl);
	I915_WRITE(GEN6_MBCTL,		s->mbctl);

	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	I915_WRITE(GEN6_UCGCTL1,	s->ucgctl1);
	I915_WRITE(GEN6_UCGCTL3,	s->ucgctl3);
	I915_WRITE(GEN6_RCGCTL1,	s->rcgctl1);
	I915_WRITE(GEN6_RCGCTL2,	s->rcgctl2);
	I915_WRITE(GEN6_RSTCTL,		s->rstctl);
	I915_WRITE(GEN7_MISCCPCTL,	s->misccpctl);

	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	I915_WRITE(GEN6_GFXPAUSE,	s->gfxpause);
	I915_WRITE(GEN6_RPDEUHWTC,	s->rpdeuhwtc);
	I915_WRITE(GEN6_RPDEUC,		s->rpdeuc);
	I915_WRITE(ECOBUS,		s->ecobus);
	I915_WRITE(VLV_PWRDWNUPCTL,	s->pwrdwnupctl);
	I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
	I915_WRITE(GEN6_RPDEUCSW,	s->rp_deucsw);
	I915_WRITE(GEN6_RCUBMABDTMR,	s->rcubmabdtmr);
	I915_WRITE(VLV_RCEDATA,		s->rcedata);
	I915_WRITE(VLV_SPAREG2H,	s->spare2gh);

	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	I915_WRITE(GTIMR,		s->gt_imr);
	I915_WRITE(GTIER,		s->gt_ier);
	I915_WRITE(GEN6_PMIMR,		s->pm_imr);
	I915_WRITE(GEN6_PMIER,		s->pm_ier);

	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
		I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);

	/* GT SA CZ domain, 0x100000-0x138124 */
	I915_WRITE(TILECTL,			s->tilectl);
	I915_WRITE(GTFIFOCTL,			s->gt_fifoctl);
	/*
	 * Preserve the GT allow wake and GFX force clock bit, they are not
	 * be restored, as they are used to control the s0ix suspend/resume
	 * sequence by the caller.
	 */
	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= VLV_GTLC_ALLOWWAKEREQ;
	val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= VLV_GFX_CLK_FORCE_ON_BIT;
	val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);

	I915_WRITE(VLV_PMWGICZ,			s->pmwgicz);

	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
}

1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
{
	u32 val;
	int err;

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);

#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
	/* Wait for a previous force-off to settle */
	if (force_on) {
1201
		err = wait_for(!COND, 20);
1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217
		if (err) {
			DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
				  I915_READ(VLV_GTLC_SURVIVABILITY_REG));
			return err;
		}
	}

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
	if (force_on)
		val |= VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);

	if (!force_on)
		return 0;

1218
	err = wait_for(COND, 20);
1219 1220 1221 1222 1223 1224 1225 1226
	if (err)
		DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
			  I915_READ(VLV_GTLC_SURVIVABILITY_REG));

	return err;
#undef COND
}

1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357
static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
{
	u32 val;
	int err = 0;

	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= ~VLV_GTLC_ALLOWWAKEREQ;
	if (allow)
		val |= VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
	POSTING_READ(VLV_GTLC_WAKE_CTRL);

#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
	      allow)
	err = wait_for(COND, 1);
	if (err)
		DRM_ERROR("timeout disabling GT waking\n");
	return err;
#undef COND
}

static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
				 bool wait_for_on)
{
	u32 mask;
	u32 val;
	int err;

	mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
	val = wait_for_on ? mask : 0;
#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
	if (COND)
		return 0;

	DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
			wait_for_on ? "on" : "off",
			I915_READ(VLV_GTLC_PW_STATUS));

	/*
	 * RC6 transitioning can be delayed up to 2 msec (see
	 * valleyview_enable_rps), use 3 msec for safety.
	 */
	err = wait_for(COND, 3);
	if (err)
		DRM_ERROR("timeout waiting for GT wells to go %s\n",
			  wait_for_on ? "on" : "off");

	return err;
#undef COND
}

static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
{
	if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
		return;

	DRM_ERROR("GT register access while GT waking disabled\n");
	I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
}

static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
{
	u32 mask;
	int err;

	/*
	 * Bspec defines the following GT well on flags as debug only, so
	 * don't treat them as hard failures.
	 */
	(void)vlv_wait_for_gt_wells(dev_priv, false);

	mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
	WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);

	vlv_check_no_gt_access(dev_priv);

	err = vlv_force_gfx_clock(dev_priv, true);
	if (err)
		goto err1;

	err = vlv_allow_gt_wake(dev_priv, false);
	if (err)
		goto err2;
	vlv_save_gunit_s0ix_state(dev_priv);

	err = vlv_force_gfx_clock(dev_priv, false);
	if (err)
		goto err2;

	return 0;

err2:
	/* For safety always re-enable waking and disable gfx clock forcing */
	vlv_allow_gt_wake(dev_priv, true);
err1:
	vlv_force_gfx_clock(dev_priv, false);

	return err;
}

static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	int err;
	int ret;

	/*
	 * If any of the steps fail just try to continue, that's the best we
	 * can do at this point. Return the first error code (which will also
	 * leave RPM permanently disabled).
	 */
	ret = vlv_force_gfx_clock(dev_priv, true);

	vlv_restore_gunit_s0ix_state(dev_priv);

	err = vlv_allow_gt_wake(dev_priv, true);
	if (!ret)
		ret = err;

	err = vlv_force_gfx_clock(dev_priv, false);
	if (!ret)
		ret = err;

	vlv_check_no_gt_access(dev_priv);

	intel_init_clock_gating(dev);
	i915_gem_restore_fences(dev);

	return ret;
}

1358
static int intel_runtime_suspend(struct device *device)
1359 1360 1361 1362
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_i915_private *dev_priv = dev->dev_private;
1363
	int ret;
1364

1365
	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1366 1367
		return -ENODEV;

1368
	WARN_ON(!HAS_RUNTIME_PM(dev));
1369
	assert_force_wake_inactive(dev_priv);
1370 1371 1372

	DRM_DEBUG_KMS("Suspending device\n");

1373 1374 1375 1376 1377 1378
	/*
	 * rps.work can't be rearmed here, since we get here only after making
	 * sure the GPU is idle and the RPS freq is set to the minimum. See
	 * intel_mark_idle().
	 */
	cancel_work_sync(&dev_priv->rps.work);
1379 1380
	intel_runtime_pm_disable_interrupts(dev);

1381 1382 1383 1384
	if (IS_GEN6(dev)) {
		ret = 0;
	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
		ret = hsw_runtime_suspend(dev_priv);
1385 1386
	} else if (IS_VALLEYVIEW(dev)) {
		ret = vlv_runtime_suspend(dev_priv);
1387 1388
	} else {
		ret = -ENODEV;
1389
		WARN_ON(1);
1390 1391 1392 1393 1394 1395 1396 1397
	}

	if (ret) {
		DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
		intel_runtime_pm_restore_interrupts(dev);

		return ret;
	}
1398

1399 1400
	i915_gem_release_all_mmaps(dev_priv);

1401
	del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1402
	dev_priv->pm.suspended = true;
1403 1404 1405 1406 1407 1408 1409 1410 1411

	/*
	 * current versions of firmware which depend on this opregion
	 * notification have repurposed the D1 definition to mean
	 * "runtime suspended" vs. what you would normally expect (D3)
	 * to distinguish it from notifications that might be sent
	 * via the suspend path.
	 */
	intel_opregion_notify_adapter(dev, PCI_D1);
1412

1413
	DRM_DEBUG_KMS("Device suspended\n");
1414 1415 1416
	return 0;
}

1417
static int intel_runtime_resume(struct device *device)
1418 1419 1420 1421
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_i915_private *dev_priv = dev->dev_private;
1422
	int ret;
1423 1424 1425 1426 1427

	WARN_ON(!HAS_RUNTIME_PM(dev));

	DRM_DEBUG_KMS("Resuming device\n");

1428
	intel_opregion_notify_adapter(dev, PCI_D0);
1429 1430
	dev_priv->pm.suspended = false;

1431 1432 1433 1434
	if (IS_GEN6(dev)) {
		ret = snb_runtime_resume(dev_priv);
	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
		ret = hsw_runtime_resume(dev_priv);
1435 1436
	} else if (IS_VALLEYVIEW(dev)) {
		ret = vlv_runtime_resume(dev_priv);
1437
	} else {
1438
		WARN_ON(1);
1439 1440
		ret = -ENODEV;
	}
1441

1442 1443 1444 1445
	/*
	 * No point of rolling back things in case of an error, as the best
	 * we can do is to hope that things will still work (and disable RPM).
	 */
1446 1447 1448
	i915_gem_init_swizzling(dev);
	gen6_update_ring_freq(dev);

1449
	intel_runtime_pm_restore_interrupts(dev);
1450
	intel_reset_gt_powersave(dev);
1451

1452 1453 1454 1455 1456 1457
	if (ret)
		DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
	else
		DRM_DEBUG_KMS("Device resumed\n");

	return ret;
1458 1459
}

1460
static const struct dev_pm_ops i915_pm_ops = {
1461
	.suspend = i915_pm_suspend,
1462 1463
	.suspend_late = i915_pm_suspend_late,
	.resume_early = i915_pm_resume_early,
1464 1465
	.resume = i915_pm_resume,
	.freeze = i915_pm_freeze,
1466
	.thaw_early = i915_pm_thaw_early,
1467 1468
	.thaw = i915_pm_thaw,
	.poweroff = i915_pm_poweroff,
1469
	.restore_early = i915_pm_resume_early,
1470
	.restore = i915_pm_resume,
1471 1472
	.runtime_suspend = intel_runtime_suspend,
	.runtime_resume = intel_runtime_resume,
1473 1474
};

1475
static const struct vm_operations_struct i915_gem_vm_ops = {
1476
	.fault = i915_gem_fault,
1477 1478
	.open = drm_gem_vm_open,
	.close = drm_gem_vm_close,
1479 1480
};

1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494
static const struct file_operations i915_driver_fops = {
	.owner = THIS_MODULE,
	.open = drm_open,
	.release = drm_release,
	.unlocked_ioctl = drm_ioctl,
	.mmap = drm_gem_mmap,
	.poll = drm_poll,
	.read = drm_read,
#ifdef CONFIG_COMPAT
	.compat_ioctl = i915_compat_ioctl,
#endif
	.llseek = noop_llseek,
};

L
Linus Torvalds 已提交
1495
static struct drm_driver driver = {
1496 1497
	/* Don't use MTRRs here; the Xserver or userspace app should
	 * deal with them for Intel hardware.
D
Dave Airlie 已提交
1498
	 */
1499
	.driver_features =
D
Daniel Vetter 已提交
1500
	    DRIVER_USE_AGP |
1501 1502
	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
	    DRIVER_RENDER,
1503
	.load = i915_driver_load,
J
Jesse Barnes 已提交
1504
	.unload = i915_driver_unload,
1505
	.open = i915_driver_open,
1506 1507
	.lastclose = i915_driver_lastclose,
	.preclose = i915_driver_preclose,
1508
	.postclose = i915_driver_postclose,
1509 1510 1511

	/* Used in place of i915_pm_ops for non-DRIVER_MODESET */
	.suspend = i915_suspend,
1512
	.resume = i915_resume_legacy,
1513

1514
	.device_is_agp = i915_driver_device_is_agp,
1515 1516
	.master_create = i915_master_create,
	.master_destroy = i915_master_destroy,
1517
#if defined(CONFIG_DEBUG_FS)
1518 1519
	.debugfs_init = i915_debugfs_init,
	.debugfs_cleanup = i915_debugfs_cleanup,
1520
#endif
1521
	.gem_free_object = i915_gem_free_object,
1522
	.gem_vm_ops = &i915_gem_vm_ops,
1523 1524 1525 1526 1527 1528

	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	.gem_prime_export = i915_gem_prime_export,
	.gem_prime_import = i915_gem_prime_import,

1529 1530
	.dumb_create = i915_gem_dumb_create,
	.dumb_map_offset = i915_gem_mmap_gtt,
1531
	.dumb_destroy = drm_gem_dumb_destroy,
L
Linus Torvalds 已提交
1532
	.ioctls = i915_ioctls,
1533
	.fops = &i915_driver_fops,
1534 1535 1536 1537 1538 1539
	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
	.date = DRIVER_DATE,
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
L
Linus Torvalds 已提交
1540 1541
};

1542 1543 1544 1545 1546 1547 1548 1549
static struct pci_driver i915_pci_driver = {
	.name = DRIVER_NAME,
	.id_table = pciidlist,
	.probe = i915_pci_probe,
	.remove = i915_pci_remove,
	.driver.pm = &i915_pm_ops,
};

L
Linus Torvalds 已提交
1550 1551 1552
static int __init i915_init(void)
{
	driver.num_ioctls = i915_max_ioctl;
J
Jesse Barnes 已提交
1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563

	/*
	 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
	 * explicitly disabled with the module pararmeter.
	 *
	 * Otherwise, just follow the parameter (defaulting to off).
	 *
	 * Allow optional vga_text_mode_force boot option to override
	 * the default behavior.
	 */
#if defined(CONFIG_DRM_I915_KMS)
1564
	if (i915.modeset != 0)
J
Jesse Barnes 已提交
1565 1566
		driver.driver_features |= DRIVER_MODESET;
#endif
1567
	if (i915.modeset == 1)
J
Jesse Barnes 已提交
1568 1569 1570
		driver.driver_features |= DRIVER_MODESET;

#ifdef CONFIG_VGA_CONSOLE
1571
	if (vgacon_text_force() && i915.modeset == -1)
J
Jesse Barnes 已提交
1572 1573 1574
		driver.driver_features &= ~DRIVER_MODESET;
#endif

D
Daniel Vetter 已提交
1575
	if (!(driver.driver_features & DRIVER_MODESET)) {
1576
		driver.get_vblank_timestamp = NULL;
D
Daniel Vetter 已提交
1577 1578 1579 1580 1581
#ifndef CONFIG_DRM_I915_UMS
		/* Silently fail loading to not upset userspace. */
		return 0;
#endif
	}
1582

1583
	return drm_pci_init(&driver, &i915_pci_driver);
L
Linus Torvalds 已提交
1584 1585 1586 1587
}

static void __exit i915_exit(void)
{
1588 1589 1590 1591 1592
#ifndef CONFIG_DRM_I915_UMS
	if (!(driver.driver_features & DRIVER_MODESET))
		return; /* Never loaded a driver. */
#endif

1593
	drm_pci_exit(&driver, &i915_pci_driver);
L
Linus Torvalds 已提交
1594 1595 1596 1597 1598
}

module_init(i915_init);
module_exit(i915_exit);

D
Dave Airlie 已提交
1599 1600
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
L
Linus Torvalds 已提交
1601
MODULE_LICENSE("GPL and additional rights");