1. 18 11月, 2015 2 次提交
    • P
      drm/i915/gen9: Turn DC handling into a power well · 9f836f90
      Patrik Jakobsson 提交于
      Handle DC off as a power well where enabling the power well will prevent
      the DMC to enter selected DC states (required around modesets and Aux
      A). Disabling the power well will allow DC states again. For now the
      highest DC state is DC6 for Skylake and DC5 for Broxton but will be
      configurable for Skylake in a later patch.
      
      v2: Check both DC5 and DC6 bits in power well enabled function (Ville)
      v3:
      - Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
      - Add PW2 dependency to DC_OFF (Imre)
      v4: Put DC_OFF before PW2 in BXT power well array
      Signed-off-by: NPatrik Jakobsson <patrik.jakobsson@linux.intel.com>
      Reviewed-by: NImre Deak <imre.deak@intel.com>
      [fixed line over 80 and parenthesis alignment checkpatch warns (imre)]
      Link: http://patchwork.freedesktop.org/patch/msgid/1447687201-24759-1-git-send-email-patrik.jakobsson@linux.intel.com
      9f836f90
    • I
      drm/i915/skl: init/uninit display core as part of the HW power domain state · 73dfc227
      Imre Deak 提交于
      We need to initialize the display core part early, before initializing
      the rest of the display power state. This is also described in the bspec
      termed "Display initialization sequence". Atm we run this sequence
      during driver loading after power domain HW state initialization which
      is too late and during runtime suspend/resume which is unneeded and can
      interere with DMC functionality which handles HW resources toggled
      by this init/uninit sequence automatically. The init sequence must be
      run as the first step of HW power state initialization and during
      system resume. The uninit sequence must be run during system suspend.
      
      To address the above move the init sequence to the initial HW power
      state setup and the uninit sequence to a new power domains suspend
      function called during system suspend.
      
      As part of the init sequence we also have to reprogram the DMC firmware
      as it's lost across a system suspend/resume cycle.
      
      After this change CD clock initialization during driver loading will
      happen only later after other dependent HW/SW parts are initialized,
      while during system resume it will get initialized as the last step of
      the init sequence. This distinction can be removed by some refactoring
      of platform independent parts. I left this refactoring out from this
      series since I didn't want to change non-SKL parts. This is a TODO for
      later.
      
      v2:
      - fix error path in i915_drm_suspend_late()
      - don't try to re-program the DMC firmware if it failed to load
      Signed-off-by: NImre Deak <imre.deak@intel.com>
      Reviewed-by: NPatrik Jakobsson <patrik.jakobsson@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1447774433-20834-1-git-send-email-imre.deak@intel.com
      73dfc227
  2. 12 11月, 2015 5 次提交
  3. 29 10月, 2015 5 次提交
  4. 19 10月, 2015 1 次提交
  5. 06 10月, 2015 1 次提交
  6. 30 9月, 2015 2 次提交
  7. 23 9月, 2015 1 次提交
  8. 02 9月, 2015 2 次提交
  9. 31 8月, 2015 1 次提交
  10. 26 8月, 2015 2 次提交
  11. 05 8月, 2015 1 次提交
  12. 28 7月, 2015 1 次提交
    • D
      drm/i915: Fake AGP is dead · 3b9a02e8
      Daniel Vetter 提交于
      Remove the leftovers, yay!
      
      AGP for i915 kms died long ago with
      
      commit 3bb6ce66
      Author: Daniel Vetter <daniel.vetter@ffwll.ch>
      Date:   Wed Nov 13 22:14:16 2013 +0100
      
          drm/i915: Kill legeacy AGP for gen3 kms
      
      and with ums now gone to there's really no users any more.
      
      Note that device_is_agp is only called when DRIVER_USE_AGP is set and
      since we've unconditionally cleared that since a while there are
      really no users left for i915_driver_device_is_agp.
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com>
      3b9a02e8
  13. 27 7月, 2015 1 次提交
  14. 17 7月, 2015 1 次提交
  15. 15 7月, 2015 1 次提交
  16. 14 7月, 2015 1 次提交
  17. 23 6月, 2015 2 次提交
  18. 22 6月, 2015 2 次提交
  19. 12 6月, 2015 3 次提交
  20. 29 5月, 2015 1 次提交
  21. 22 5月, 2015 1 次提交
    • D
      drm/i915/skl: Deinit/init the display at suspend/resume · 5d96d8af
      Damien Lespiau 提交于
      We need to re-init the display hardware when going out of suspend. This
      includes:
      
        - Hooking the PCH to the reset logic
        - Restoring CDCDLK
        - Enabling the DDB power
      
      Among those, only the CDCDLK one is a bit tricky. There's some
      complexity in that:
      
        - DPLL0 (which is the source for CDCLK) has two VCOs, each with a set
          of supported frequencies. As eDP also uses DPLL0 for its link rate,
          once DPLL0 is on, we restrict the possible eDP link rates the chosen
          VCO.
        - CDCLK also limits the bandwidth available to push pixels.
      
      So, as a first step, this commit restore what the BIOS set, until I can
      do more testing.
      
      In case that's of interest for the reviewer, I've unit tested the
      function that derives the decimal frequency field:
      
        #include <stdio.h>
        #include <stdint.h>
        #include <assert.h>
      
        #define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
      
        static const struct dpll_freq {
                unsigned int freq;
                unsigned int decimal;
        } freqs[] = {
                { .freq = 308570, .decimal = 0b01001100111},
                { .freq = 337500, .decimal = 0b01010100001},
                { .freq = 432000, .decimal = 0b01101011110},
                { .freq = 450000, .decimal = 0b01110000010},
                { .freq = 540000, .decimal = 0b10000110110},
                { .freq = 617140, .decimal = 0b10011010000},
                { .freq = 675000, .decimal = 0b10101000100},
        };
      
        static void intbits(unsigned int v)
        {
                int i;
      
                for(i = 10; i >= 0; i--)
                        putchar('0' + ((v >> i) & 1));
        }
      
        static unsigned int freq_decimal(unsigned int freq /* in kHz */)
        {
                return (freq - 1000) / 500;
        }
      
        static void test_freq(const struct dpll_freq *entry)
        {
                unsigned int decimal = freq_decimal(entry->freq);
      
                printf("freq: %d, expected: ", entry->freq);
                intbits(entry->decimal);
                printf(", got: ");
                intbits(decimal);
                putchar('\n');
      
                assert(decimal == entry->decimal);
        }
      
        int main(int argc, char **argv)
        {
                int i;
      
                for (i = 0; i < ARRAY_SIZE(freqs); i++)
                        test_freq(&freqs[i]);
      
                return 0;
        }
      
      v2:
        - Rebase on top of -nightly
        - Use (freq - 1000) / 500 for the decimal frequency (Ville)
        - Fix setting the enable bit of HSW_NDE_RSTWRN_OPT (Ville)
        - Rename skl_display_{resume,suspend} to skl_{init,uninit}_cdclk to
          be consistent with the BXT code (Ville)
        - Store boot CDCLK in ddi_pll_init (Ville)
        - Merge dev_priv's skl_boot_cdclk into cdclk_freq
        - Use LCPLL_PLL_LOCK instead of (1 << 30) (Ville)
        - Replace various '0' by SKL_DPLL0 to be a bit more explicit that
          we're programming DPLL0
        - Busy poll the PCU before doing the frequency change. It takes about
          3/4 cycles, each separated by 10us, to get the ACK from the CPU
          (Ville)
      
      v3:
        - Restore dev_priv->skl_boot_cdclk, leaving unification with
          dev_priv->cdclk_freq for a later patch (Daniel, Ville)
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      5d96d8af
  22. 20 5月, 2015 3 次提交