i915_pci.c 25.5 KB
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/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

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#include <linux/console.h>
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#include <linux/vgaarb.h>
#include <linux/vga_switcheroo.h>

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#include <drm/drm_drv.h>

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#include "display/intel_fbdev.h"

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#include "i915_drv.h"
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#include "i915_globals.h"
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#include "i915_selftest.h"
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#define PLATFORM(x) .platform = (x)
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#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)

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#define I845_PIPE_OFFSETS \
	.pipe_offsets = { \
		[TRANSCODER_A] = PIPE_A_OFFSET,	\
	}, \
	.trans_offsets = { \
		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
	}

#define I9XX_PIPE_OFFSETS \
	.pipe_offsets = { \
		[TRANSCODER_A] = PIPE_A_OFFSET,	\
		[TRANSCODER_B] = PIPE_B_OFFSET, \
	}, \
	.trans_offsets = { \
		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
	}

#define IVB_PIPE_OFFSETS \
	.pipe_offsets = { \
		[TRANSCODER_A] = PIPE_A_OFFSET,	\
		[TRANSCODER_B] = PIPE_B_OFFSET, \
		[TRANSCODER_C] = PIPE_C_OFFSET, \
	}, \
	.trans_offsets = { \
		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
	}

#define HSW_PIPE_OFFSETS \
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	.pipe_offsets = { \
		[TRANSCODER_A] = PIPE_A_OFFSET,	\
		[TRANSCODER_B] = PIPE_B_OFFSET, \
		[TRANSCODER_C] = PIPE_C_OFFSET, \
		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
	}, \
	.trans_offsets = { \
		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
	}
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#define CHV_PIPE_OFFSETS \
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	.pipe_offsets = { \
		[TRANSCODER_A] = PIPE_A_OFFSET, \
		[TRANSCODER_B] = PIPE_B_OFFSET, \
		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
	}, \
	.trans_offsets = { \
		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
	}
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#define I845_CURSOR_OFFSETS \
	.cursor_offsets = { \
		[PIPE_A] = CURSOR_A_OFFSET, \
	}

#define I9XX_CURSOR_OFFSETS \
	.cursor_offsets = { \
		[PIPE_A] = CURSOR_A_OFFSET, \
		[PIPE_B] = CURSOR_B_OFFSET, \
	}

#define CHV_CURSOR_OFFSETS \
	.cursor_offsets = { \
		[PIPE_A] = CURSOR_A_OFFSET, \
		[PIPE_B] = CURSOR_B_OFFSET, \
		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
	}
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#define IVB_CURSOR_OFFSETS \
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	.cursor_offsets = { \
		[PIPE_A] = CURSOR_A_OFFSET, \
		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
	}
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#define I9XX_COLORS \
	.color = { .gamma_lut_size = 256 }
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#define I965_COLORS \
	.color = { .gamma_lut_size = 129, \
		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
	}
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#define ILK_COLORS \
	.color = { .gamma_lut_size = 1024 }
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#define IVB_COLORS \
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	.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
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#define CHV_COLORS \
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	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
	}
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#define GLK_COLORS \
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	.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
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		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
					DRM_COLOR_LUT_EQUAL_CHANNELS, \
	}
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/* Keep in gen based order, and chronological order within a gen */
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#define GEN_DEFAULT_PAGE_SIZES \
	.page_sizes = I915_GTT_PAGE_SIZE_4K

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#define I830_FEATURES \
	GEN(2), \
	.is_mobile = 1, \
	.num_pipes = 2, \
	.display.has_overlay = 1, \
	.display.cursor_needs_physical = 1, \
	.display.overlay_needs_physical = 1, \
	.display.has_gmch = 1, \
	.gpu_reset_clobbers_display = true, \
	.hws_needs_physical = 1, \
	.unfenced_needs_alignment = 1, \
	.engine_mask = BIT(RCS0), \
	.has_snoop = true, \
	.has_coherent_ggtt = false, \
	I9XX_PIPE_OFFSETS, \
	I9XX_CURSOR_OFFSETS, \
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	I9XX_COLORS, \
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	GEN_DEFAULT_PAGE_SIZES

#define I845_FEATURES \
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	GEN(2), \
	.num_pipes = 1, \
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	.display.has_overlay = 1, \
	.display.overlay_needs_physical = 1, \
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	.display.has_gmch = 1, \
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	.gpu_reset_clobbers_display = true, \
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	.hws_needs_physical = 1, \
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	.unfenced_needs_alignment = 1, \
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	.engine_mask = BIT(RCS0), \
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	.has_snoop = true, \
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	.has_coherent_ggtt = false, \
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	I845_PIPE_OFFSETS, \
	I845_CURSOR_OFFSETS, \
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	I9XX_COLORS, \
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	GEN_DEFAULT_PAGE_SIZES
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static const struct intel_device_info intel_i830_info = {
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	I830_FEATURES,
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	PLATFORM(INTEL_I830),
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};

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static const struct intel_device_info intel_i845g_info = {
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	I845_FEATURES,
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	PLATFORM(INTEL_I845G),
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};

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static const struct intel_device_info intel_i85x_info = {
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	I830_FEATURES,
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	PLATFORM(INTEL_I85X),
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	.display.has_fbc = 1,
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};

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static const struct intel_device_info intel_i865g_info = {
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	I845_FEATURES,
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	PLATFORM(INTEL_I865G),
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};

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#define GEN3_FEATURES \
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	GEN(3), \
	.num_pipes = 2, \
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	.display.has_gmch = 1, \
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	.gpu_reset_clobbers_display = true, \
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	.engine_mask = BIT(RCS0), \
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	.has_snoop = true, \
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	.has_coherent_ggtt = true, \
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	I9XX_PIPE_OFFSETS, \
	I9XX_CURSOR_OFFSETS, \
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	I9XX_COLORS, \
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	GEN_DEFAULT_PAGE_SIZES
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static const struct intel_device_info intel_i915g_info = {
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	GEN3_FEATURES,
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	PLATFORM(INTEL_I915G),
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	.has_coherent_ggtt = false,
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	.display.cursor_needs_physical = 1,
	.display.has_overlay = 1,
	.display.overlay_needs_physical = 1,
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	.hws_needs_physical = 1,
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	.unfenced_needs_alignment = 1,
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};
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static const struct intel_device_info intel_i915gm_info = {
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	GEN3_FEATURES,
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	PLATFORM(INTEL_I915GM),
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	.is_mobile = 1,
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	.display.cursor_needs_physical = 1,
	.display.has_overlay = 1,
	.display.overlay_needs_physical = 1,
	.display.supports_tv = 1,
	.display.has_fbc = 1,
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	.hws_needs_physical = 1,
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	.unfenced_needs_alignment = 1,
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};
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static const struct intel_device_info intel_i945g_info = {
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	GEN3_FEATURES,
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	PLATFORM(INTEL_I945G),
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	.display.has_hotplug = 1,
	.display.cursor_needs_physical = 1,
	.display.has_overlay = 1,
	.display.overlay_needs_physical = 1,
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	.hws_needs_physical = 1,
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	.unfenced_needs_alignment = 1,
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};
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static const struct intel_device_info intel_i945gm_info = {
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	GEN3_FEATURES,
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	PLATFORM(INTEL_I945GM),
	.is_mobile = 1,
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	.display.has_hotplug = 1,
	.display.cursor_needs_physical = 1,
	.display.has_overlay = 1,
	.display.overlay_needs_physical = 1,
	.display.supports_tv = 1,
	.display.has_fbc = 1,
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	.hws_needs_physical = 1,
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	.unfenced_needs_alignment = 1,
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};

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static const struct intel_device_info intel_g33_info = {
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	GEN3_FEATURES,
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	PLATFORM(INTEL_G33),
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	.display.has_hotplug = 1,
	.display.has_overlay = 1,
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};

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static const struct intel_device_info intel_pineview_g_info = {
	GEN3_FEATURES,
	PLATFORM(INTEL_PINEVIEW),
	.display.has_hotplug = 1,
	.display.has_overlay = 1,
};

static const struct intel_device_info intel_pineview_m_info = {
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	GEN3_FEATURES,
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	PLATFORM(INTEL_PINEVIEW),
	.is_mobile = 1,
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	.display.has_hotplug = 1,
	.display.has_overlay = 1,
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};

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#define GEN4_FEATURES \
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	GEN(4), \
	.num_pipes = 2, \
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	.display.has_hotplug = 1, \
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	.display.has_gmch = 1, \
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	.gpu_reset_clobbers_display = true, \
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	.engine_mask = BIT(RCS0), \
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	.has_snoop = true, \
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	.has_coherent_ggtt = true, \
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	I9XX_PIPE_OFFSETS, \
	I9XX_CURSOR_OFFSETS, \
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	I965_COLORS, \
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	GEN_DEFAULT_PAGE_SIZES
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static const struct intel_device_info intel_i965g_info = {
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	GEN4_FEATURES,
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	PLATFORM(INTEL_I965G),
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	.display.has_overlay = 1,
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	.hws_needs_physical = 1,
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	.has_snoop = false,
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};

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static const struct intel_device_info intel_i965gm_info = {
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	GEN4_FEATURES,
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	PLATFORM(INTEL_I965GM),
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	.is_mobile = 1,
	.display.has_fbc = 1,
	.display.has_overlay = 1,
	.display.supports_tv = 1,
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	.hws_needs_physical = 1,
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	.has_snoop = false,
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};

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static const struct intel_device_info intel_g45_info = {
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	GEN4_FEATURES,
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	PLATFORM(INTEL_G45),
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	.engine_mask = BIT(RCS0) | BIT(VCS0),
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	.gpu_reset_clobbers_display = false,
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};

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static const struct intel_device_info intel_gm45_info = {
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	GEN4_FEATURES,
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	PLATFORM(INTEL_GM45),
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	.is_mobile = 1,
	.display.has_fbc = 1,
	.display.supports_tv = 1,
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	.engine_mask = BIT(RCS0) | BIT(VCS0),
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	.gpu_reset_clobbers_display = false,
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};

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#define GEN5_FEATURES \
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	GEN(5), \
	.num_pipes = 2, \
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	.display.has_hotplug = 1, \
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	.engine_mask = BIT(RCS0) | BIT(VCS0), \
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	.has_snoop = true, \
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	.has_coherent_ggtt = true, \
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	/* ilk does support rc6, but we do not implement [power] contexts */ \
	.has_rc6 = 0, \
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	I9XX_PIPE_OFFSETS, \
	I9XX_CURSOR_OFFSETS, \
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	ILK_COLORS, \
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	GEN_DEFAULT_PAGE_SIZES
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static const struct intel_device_info intel_ironlake_d_info = {
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	GEN5_FEATURES,
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	PLATFORM(INTEL_IRONLAKE),
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};

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static const struct intel_device_info intel_ironlake_m_info = {
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	GEN5_FEATURES,
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	PLATFORM(INTEL_IRONLAKE),
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	.is_mobile = 1,
	.display.has_fbc = 1,
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};

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#define GEN6_FEATURES \
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	GEN(6), \
	.num_pipes = 2, \
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	.display.has_hotplug = 1, \
	.display.has_fbc = 1, \
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	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
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	.has_coherent_ggtt = true, \
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	.has_llc = 1, \
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	.has_rc6 = 1, \
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	.has_rc6p = 1, \
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	.has_rps = true, \
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	.ppgtt_type = INTEL_PPGTT_ALIASING, \
	.ppgtt_size = 31, \
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	I9XX_PIPE_OFFSETS, \
	I9XX_CURSOR_OFFSETS, \
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	ILK_COLORS, \
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	GEN_DEFAULT_PAGE_SIZES
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#define SNB_D_PLATFORM \
	GEN6_FEATURES, \
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	PLATFORM(INTEL_SANDYBRIDGE)
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static const struct intel_device_info intel_sandybridge_d_gt1_info = {
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	SNB_D_PLATFORM,
	.gt = 1,
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};

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static const struct intel_device_info intel_sandybridge_d_gt2_info = {
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	SNB_D_PLATFORM,
	.gt = 2,
};

#define SNB_M_PLATFORM \
	GEN6_FEATURES, \
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	PLATFORM(INTEL_SANDYBRIDGE), \
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	.is_mobile = 1


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static const struct intel_device_info intel_sandybridge_m_gt1_info = {
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	SNB_M_PLATFORM,
	.gt = 1,
};

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static const struct intel_device_info intel_sandybridge_m_gt2_info = {
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	SNB_M_PLATFORM,
	.gt = 2,
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};

#define GEN7_FEATURES  \
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	GEN(7), \
	.num_pipes = 3, \
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	.display.has_hotplug = 1, \
	.display.has_fbc = 1, \
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	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
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	.has_coherent_ggtt = true, \
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	.has_llc = 1, \
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	.has_rc6 = 1, \
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	.has_rc6p = 1, \
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	.has_rps = true, \
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	.ppgtt_type = INTEL_PPGTT_FULL, \
	.ppgtt_size = 31, \
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	IVB_PIPE_OFFSETS, \
	IVB_CURSOR_OFFSETS, \
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	IVB_COLORS, \
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	GEN_DEFAULT_PAGE_SIZES
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#define IVB_D_PLATFORM \
	GEN7_FEATURES, \
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	PLATFORM(INTEL_IVYBRIDGE), \
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	.has_l3_dpf = 1

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static const struct intel_device_info intel_ivybridge_d_gt1_info = {
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	IVB_D_PLATFORM,
	.gt = 1,
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};

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static const struct intel_device_info intel_ivybridge_d_gt2_info = {
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	IVB_D_PLATFORM,
	.gt = 2,
};

#define IVB_M_PLATFORM \
	GEN7_FEATURES, \
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	PLATFORM(INTEL_IVYBRIDGE), \
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	.is_mobile = 1, \
	.has_l3_dpf = 1

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static const struct intel_device_info intel_ivybridge_m_gt1_info = {
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	IVB_M_PLATFORM,
	.gt = 1,
};

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static const struct intel_device_info intel_ivybridge_m_gt2_info = {
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	IVB_M_PLATFORM,
	.gt = 2,
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};

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static const struct intel_device_info intel_ivybridge_q_info = {
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	GEN7_FEATURES,
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	PLATFORM(INTEL_IVYBRIDGE),
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	.gt = 2,
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	.num_pipes = 0, /* legal, last one wins */
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	.has_l3_dpf = 1,
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};

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static const struct intel_device_info intel_valleyview_info = {
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	PLATFORM(INTEL_VALLEYVIEW),
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	GEN(7),
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	.is_lp = 1,
	.num_pipes = 2,
	.has_runtime_pm = 1,
	.has_rc6 = 1,
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	.has_rps = true,
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	.display.has_gmch = 1,
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	.display.has_hotplug = 1,
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	.ppgtt_type = INTEL_PPGTT_FULL,
	.ppgtt_size = 31,
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	.has_snoop = true,
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	.has_coherent_ggtt = false,
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	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
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	.display_mmio_offset = VLV_DISPLAY_BASE,
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	I9XX_PIPE_OFFSETS,
	I9XX_CURSOR_OFFSETS,
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	I965_COLORS,
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	GEN_DEFAULT_PAGE_SIZES,
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};

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#define G75_FEATURES  \
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	GEN7_FEATURES, \
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	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
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	.display.has_ddi = 1, \
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	.has_fpga_dbg = 1, \
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	.display.has_psr = 1, \
	.display.has_dp_mst = 1, \
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	.has_rc6p = 0 /* RC6p removed-by HSW */, \
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	HSW_PIPE_OFFSETS, \
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	.has_runtime_pm = 1
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#define HSW_PLATFORM \
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	G75_FEATURES, \
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	PLATFORM(INTEL_HASWELL), \
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	.has_l3_dpf = 1

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static const struct intel_device_info intel_haswell_gt1_info = {
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	HSW_PLATFORM,
	.gt = 1,
};

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static const struct intel_device_info intel_haswell_gt2_info = {
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	HSW_PLATFORM,
	.gt = 2,
};

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static const struct intel_device_info intel_haswell_gt3_info = {
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	HSW_PLATFORM,
	.gt = 3,
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};

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#define GEN8_FEATURES \
	G75_FEATURES, \
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	GEN(8), \
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	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
		      I915_GTT_PAGE_SIZE_2M, \
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	.has_logical_ring_contexts = 1, \
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	.ppgtt_type = INTEL_PPGTT_FULL, \
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	.ppgtt_size = 48, \
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	.has_64bit_reloc = 1, \
	.has_reset_engine = 1
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#define BDW_PLATFORM \
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	GEN8_FEATURES, \
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	PLATFORM(INTEL_BROADWELL)
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static const struct intel_device_info intel_broadwell_gt1_info = {
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	BDW_PLATFORM,
	.gt = 1,
};

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static const struct intel_device_info intel_broadwell_gt2_info = {
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	BDW_PLATFORM,
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	.gt = 2,
};

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static const struct intel_device_info intel_broadwell_rsvd_info = {
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	BDW_PLATFORM,
	.gt = 3,
	/* According to the device ID those devices are GT3, they were
	 * previously treated as not GT3, keep it like that.
	 */
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};

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static const struct intel_device_info intel_broadwell_gt3_info = {
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	BDW_PLATFORM,
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	.gt = 3,
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	.engine_mask =
		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
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};

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static const struct intel_device_info intel_cherryview_info = {
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	PLATFORM(INTEL_CHERRYVIEW),
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	GEN(8),
	.num_pipes = 3,
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	.display.has_hotplug = 1,
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	.is_lp = 1,
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	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
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	.has_64bit_reloc = 1,
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	.has_runtime_pm = 1,
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	.has_rc6 = 1,
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	.has_rps = true,
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	.has_logical_ring_contexts = 1,
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	.display.has_gmch = 1,
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	.ppgtt_type = INTEL_PPGTT_FULL,
	.ppgtt_size = 32,
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	.has_reset_engine = 1,
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	.has_snoop = true,
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	.has_coherent_ggtt = false,
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	.display_mmio_offset = VLV_DISPLAY_BASE,
581 582
	CHV_PIPE_OFFSETS,
	CHV_CURSOR_OFFSETS,
583
	CHV_COLORS,
584
	GEN_DEFAULT_PAGE_SIZES,
585 586
};

587
#define GEN9_DEFAULT_PAGE_SIZES \
588
	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
589 590
		      I915_GTT_PAGE_SIZE_64K | \
		      I915_GTT_PAGE_SIZE_2M
591

592 593
#define GEN9_FEATURES \
	GEN8_FEATURES, \
594
	GEN(9), \
595
	GEN9_DEFAULT_PAGE_SIZES, \
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596
	.has_logical_ring_preemption = 1, \
597
	.display.has_csr = 1, \
598
	.has_guc = 1, \
599
	.display.has_ipc = 1, \
600 601
	.ddb_size = 896

602 603
#define SKL_PLATFORM \
	GEN9_FEATURES, \
604
	PLATFORM(INTEL_SKYLAKE)
605

606
static const struct intel_device_info intel_skylake_gt1_info = {
607
	SKL_PLATFORM,
608
	.gt = 1,
609 610
};

611
static const struct intel_device_info intel_skylake_gt2_info = {
612
	SKL_PLATFORM,
613 614 615 616 617
	.gt = 2,
};

#define SKL_GT3_PLUS_PLATFORM \
	SKL_PLATFORM, \
618 619
	.engine_mask = \
		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
620 621


622
static const struct intel_device_info intel_skylake_gt3_info = {
623 624 625 626
	SKL_GT3_PLUS_PLATFORM,
	.gt = 3,
};

627
static const struct intel_device_info intel_skylake_gt4_info = {
628 629
	SKL_GT3_PLUS_PLATFORM,
	.gt = 4,
630 631
};

632
#define GEN9_LP_FEATURES \
633
	GEN(9), \
634
	.is_lp = 1, \
635
	.display.has_hotplug = 1, \
636
	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
637 638
	.num_pipes = 3, \
	.has_64bit_reloc = 1, \
639
	.display.has_ddi = 1, \
640
	.has_fpga_dbg = 1, \
641 642
	.display.has_fbc = 1, \
	.display.has_psr = 1, \
643
	.has_runtime_pm = 1, \
644
	.display.has_csr = 1, \
645
	.has_rc6 = 1, \
646
	.has_rps = true, \
647
	.display.has_dp_mst = 1, \
648
	.has_logical_ring_contexts = 1, \
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649
	.has_logical_ring_preemption = 1, \
650
	.has_guc = 1, \
651
	.ppgtt_type = INTEL_PPGTT_FULL, \
652
	.ppgtt_size = 48, \
653
	.has_reset_engine = 1, \
654
	.has_snoop = true, \
655
	.has_coherent_ggtt = false, \
656
	.display.has_ipc = 1, \
657
	HSW_PIPE_OFFSETS, \
658
	IVB_CURSOR_OFFSETS, \
659
	IVB_COLORS, \
660
	GEN9_DEFAULT_PAGE_SIZES
661

662
static const struct intel_device_info intel_broxton_info = {
663
	GEN9_LP_FEATURES,
664
	PLATFORM(INTEL_BROXTON),
665
	.ddb_size = 512,
666 667
};

668
static const struct intel_device_info intel_geminilake_info = {
669
	GEN9_LP_FEATURES,
670
	PLATFORM(INTEL_GEMINILAKE),
671
	.ddb_size = 1024,
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	GLK_COLORS,
673 674
};

675
#define KBL_PLATFORM \
676
	GEN9_FEATURES, \
677
	PLATFORM(INTEL_KABYLAKE)
678

679
static const struct intel_device_info intel_kabylake_gt1_info = {
680
	KBL_PLATFORM,
681 682 683
	.gt = 1,
};

684
static const struct intel_device_info intel_kabylake_gt2_info = {
685 686
	KBL_PLATFORM,
	.gt = 2,
687 688
};

689
static const struct intel_device_info intel_kabylake_gt3_info = {
690
	KBL_PLATFORM,
691
	.gt = 3,
692 693
	.engine_mask =
		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
694 695
};

696
#define CFL_PLATFORM \
697
	GEN9_FEATURES, \
698
	PLATFORM(INTEL_COFFEELAKE)
699

700
static const struct intel_device_info intel_coffeelake_gt1_info = {
701 702 703 704
	CFL_PLATFORM,
	.gt = 1,
};

705
static const struct intel_device_info intel_coffeelake_gt2_info = {
706
	CFL_PLATFORM,
707
	.gt = 2,
708 709
};

710
static const struct intel_device_info intel_coffeelake_gt3_info = {
711
	CFL_PLATFORM,
712
	.gt = 3,
713 714
	.engine_mask =
		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
715 716
};

717 718
#define GEN10_FEATURES \
	GEN9_FEATURES, \
719
	GEN(10), \
720
	.ddb_size = 1024, \
721
	.has_coherent_ggtt = false, \
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	GLK_COLORS
723

724
static const struct intel_device_info intel_cannonlake_info = {
725
	GEN10_FEATURES,
726
	PLATFORM(INTEL_CANNONLAKE),
727
	.gt = 2,
728 729
};

730 731
#define GEN11_FEATURES \
	GEN10_FEATURES, \
732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747
	.pipe_offsets = { \
		[TRANSCODER_A] = PIPE_A_OFFSET, \
		[TRANSCODER_B] = PIPE_B_OFFSET, \
		[TRANSCODER_C] = PIPE_C_OFFSET, \
		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
	}, \
	.trans_offsets = { \
		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
	}, \
748
	GEN(11), \
749
	.ddb_size = 2048, \
750
	.has_logical_ring_elsq = 1, \
751
	.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
752

753
static const struct intel_device_info intel_icelake_11_info = {
754
	GEN11_FEATURES,
755
	PLATFORM(INTEL_ICELAKE),
756 757
	.engine_mask =
		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
758 759
};

760 761
static const struct intel_device_info intel_elkhartlake_info = {
	GEN11_FEATURES,
762
	PLATFORM(INTEL_ELKHARTLAKE),
763
	.require_force_probe = 1,
764
	.engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
765 766 767
	.ppgtt_size = 36,
};

768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796
#define GEN12_FEATURES \
	GEN11_FEATURES, \
	GEN(12), \
	.pipe_offsets = { \
		[TRANSCODER_A] = PIPE_A_OFFSET, \
		[TRANSCODER_B] = PIPE_B_OFFSET, \
		[TRANSCODER_C] = PIPE_C_OFFSET, \
		[TRANSCODER_D] = PIPE_D_OFFSET, \
		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
	}, \
	.trans_offsets = { \
		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
	}

static const struct intel_device_info intel_tigerlake_12_info = {
	GEN12_FEATURES,
	PLATFORM(INTEL_TIGERLAKE),
	.num_pipes = 4,
	.require_force_probe = 1,
	.engine_mask =
		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
};

797
#undef GEN
798
#undef PLATFORM
799

800 801 802 803 804 805 806 807
/*
 * Make sure any device matches here are from most specific to most
 * general.  For example, since the Quanta match is based on the subsystem
 * and subvendor IDs, we need it to come before the more general IVB
 * PCI ID matches, otherwise we'll use the wrong info struct above.
 */
static const struct pci_device_id pciidlist[] = {
	INTEL_I830_IDS(&intel_i830_info),
808
	INTEL_I845G_IDS(&intel_i845g_info),
809 810 811 812 813 814 815 816 817 818 819
	INTEL_I85X_IDS(&intel_i85x_info),
	INTEL_I865G_IDS(&intel_i865g_info),
	INTEL_I915G_IDS(&intel_i915g_info),
	INTEL_I915GM_IDS(&intel_i915gm_info),
	INTEL_I945G_IDS(&intel_i945g_info),
	INTEL_I945GM_IDS(&intel_i945gm_info),
	INTEL_I965G_IDS(&intel_i965g_info),
	INTEL_G33_IDS(&intel_g33_info),
	INTEL_I965GM_IDS(&intel_i965gm_info),
	INTEL_GM45_IDS(&intel_gm45_info),
	INTEL_G45_IDS(&intel_g45_info),
820 821
	INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info),
	INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info),
822 823
	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
824 825 826 827
	INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
	INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
	INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
	INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
828
	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
829 830 831 832 833 834 835
	INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
	INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
	INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
	INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
	INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
	INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
	INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
836
	INTEL_VLV_IDS(&intel_valleyview_info),
837 838
	INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
	INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
839
	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
840
	INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
841
	INTEL_CHV_IDS(&intel_cherryview_info),
842 843
	INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
	INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
844
	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
845
	INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
846
	INTEL_BXT_IDS(&intel_broxton_info),
847
	INTEL_GLK_IDS(&intel_geminilake_info),
848 849
	INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
	INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
850 851
	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
852
	INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
853 854
	INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
	INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
855
	INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
856
	INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
857
	INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
858
	INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
859 860
	INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
	INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
861
	INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
862
	INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
A
Anusha Srivatsa 已提交
863 864
	INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
	INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
865
	INTEL_CNL_IDS(&intel_cannonlake_info),
P
Paulo Zanoni 已提交
866
	INTEL_ICL_11_IDS(&intel_icelake_11_info),
867
	INTEL_EHL_IDS(&intel_elkhartlake_info),
L
Lucas De Marchi 已提交
868
	INTEL_TGL_12_IDS(&intel_tigerlake_12_info),
869 870 871 872
	{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);

873 874
static void i915_pci_remove(struct pci_dev *pdev)
{
875 876 877 878 879
	struct drm_device *dev;

	dev = pci_get_drvdata(pdev);
	if (!dev) /* driver load aborted, nothing to cleanup */
		return;
880

881
	i915_driver_remove(dev);
882
	drm_dev_put(dev);
883 884

	pci_set_drvdata(pdev, NULL);
885 886
}

887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924
/* is device_id present in comma separated list of ids */
static bool force_probe(u16 device_id, const char *devices)
{
	char *s, *p, *tok;
	bool ret;

	/* FIXME: transitional */
	if (i915_modparams.alpha_support) {
		DRM_INFO("i915.alpha_support is deprecated, use i915.force_probe=%04x instead\n",
			 device_id);
		return true;
	}

	if (!devices || !*devices)
		return false;

	/* match everything */
	if (strcmp(devices, "*") == 0)
		return true;

	s = kstrdup(devices, GFP_KERNEL);
	if (!s)
		return false;

	for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
		u16 val;

		if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
			ret = true;
			break;
		}
	}

	kfree(s);

	return ret;
}

925 926 927 928
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct intel_device_info *intel_info =
		(struct intel_device_info *) ent->driver_data;
929
	int err;
930

931 932 933 934 935 936 937
	if (intel_info->require_force_probe &&
	    !force_probe(pdev->device, i915_modparams.force_probe)) {
		DRM_INFO("Your graphics device %04x is not properly supported by the driver in this\n"
			 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
			 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
			 "or (recommended) check for kernel updates.\n",
			 pdev->device, pdev->device, pdev->device);
938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955
		return -ENODEV;
	}

	/* Only bind to function 0 of the device. Early generations
	 * used function 1 as a placeholder for multi-head. This causes
	 * us confusion instead, especially on the systems where both
	 * functions have the same PCI-ID!
	 */
	if (PCI_FUNC(pdev->devfn))
		return -ENODEV;

	/*
	 * apple-gmux is needed on dual GPU MacBook Pro
	 * to probe the panel if we're the inactive GPU.
	 */
	if (vga_switcheroo_client_probe_defer(pdev))
		return -EPROBE_DEFER;

956
	err = i915_driver_probe(pdev, ent);
957 958
	if (err)
		return err;
959

960
	if (i915_inject_probe_failure()) {
961 962 963 964
		i915_pci_remove(pdev);
		return -ENODEV;
	}

965 966 967 968 969
	err = i915_live_selftests(pdev);
	if (err) {
		i915_pci_remove(pdev);
		return err > 0 ? -ENOTTY : err;
	}
970

971
	return 0;
972 973
}

974
static struct pci_driver i915_pci_driver = {
975 976 977 978 979 980
	.name = DRIVER_NAME,
	.id_table = pciidlist,
	.probe = i915_pci_probe,
	.remove = i915_pci_remove,
	.driver.pm = &i915_pm_ops,
};
981 982 983 984

static int __init i915_init(void)
{
	bool use_kms = true;
985 986
	int err;

987 988 989
	err = i915_globals_init();
	if (err)
		return err;
990

991 992 993
	err = i915_mock_selftests();
	if (err)
		return err > 0 ? 0 : err;
994 995 996 997 998 999 1000

	/*
	 * Enable KMS by default, unless explicitly overriden by
	 * either the i915.modeset prarameter or by the
	 * vga_text_mode_force boot option.
	 */

1001
	if (i915_modparams.modeset == 0)
1002 1003
		use_kms = false;

1004
	if (vgacon_text_force() && i915_modparams.modeset == -1)
1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021
		use_kms = false;

	if (!use_kms) {
		/* Silently fail loading to not upset userspace. */
		DRM_DEBUG_DRIVER("KMS disabled.\n");
		return 0;
	}

	return pci_register_driver(&i915_pci_driver);
}

static void __exit i915_exit(void)
{
	if (!i915_pci_driver.driver.owner)
		return;

	pci_unregister_driver(&i915_pci_driver);
1022
	i915_globals_exit();
1023 1024 1025 1026 1027 1028 1029 1030 1031 1032
}

module_init(i915_init);
module_exit(i915_exit);

MODULE_AUTHOR("Tungsten Graphics, Inc.");
MODULE_AUTHOR("Intel Corporation");

MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");