1. 06 6月, 2015 1 次提交
    • D
      PCI: xgene: Add APM X-Gene v1 PCIe MSI/MSIX termination driver · dcd19de3
      Duc Dang 提交于
      APM X-Gene v1 SoC supports its own implementation of MSI, which is not
      compliant to GIC V2M specification for MSI Termination.
      
      There is a single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports.
      This MSI block supports 2048 MSI termination ports coalesced into 16
      physical HW IRQ lines and shared across all 5 PCIe ports.
      
      As there are only 16 HW IRQs to serve 2048 MSI vectors, to support
      set_affinity correctly for each MSI vectors, the 16 HW IRQs are statically
      allocated to 8 X-Gene v1 cores (2 HW IRQs for each cores).  To steer MSI
      interrupt to target CPU, MSI vector is moved around these HW IRQs lines.
      With this approach, the total MSI vectors this driver supports is reduced
      to 256.
      
      [bhelgaas: squash doc, driver, maintainer update]
      Signed-off-by: NDuc Dang <dhdang@apm.com>
      Signed-off-by: NTanmay Inamdar <tinamdar@apm.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
      dcd19de3
  2. 20 5月, 2015 1 次提交
    • H
      PCI: iproc: Add BCMA PCIe driver · 4785ffbd
      Hauke Mehrtens 提交于
      This driver adds support for the PCIe 2.0 controller found on the BCMA bus.
      This controller can be found on (mostly) all Broadcom BCM470X / BCM5301X
      ARM SoCs.
      
      The driver found in the Broadcom SDK does some more stuff, like setting up
      some DMA memory areas, chaining MPS and MRRS to 512 and also some PHY
      changes like "improving" the PCIe jitter and doing some special
      initialization for the 3rd PCIe port.
      
      This was tested on a bcm4708 board with 2 PCIe ports and wireless cards
      connected to them.
      
      PCI_DOMAINS is needed by this driver, because normally there is more than
      one PCIe controller and without PCI_DOMAINS only the first controller gets
      registered.  This controller gets 6 IRQs; the last one is trigged by all
      IRQ events.
      
      [bhelgaas: fix "GPLv2" MODULE_LICENSE typo]
      Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NRafał Miłecki <zajec5@gmail.com>
      Acked-by: NRay Jui <rjui@broadcom.com.com>
      4785ffbd
  3. 09 4月, 2015 1 次提交
  4. 29 1月, 2015 1 次提交
  5. 14 11月, 2014 1 次提交
  6. 02 10月, 2014 1 次提交
  7. 05 9月, 2014 1 次提交
    • M
      PCI: keystone: Add TI Keystone PCIe driver · 0c4ffcfe
      Murali Karicheri 提交于
      The Keystone PCIe controller is based on v3.65 version of the Designware
      h/w.  Main differences are:
      
          1. No ATU support
          2. Legacy and MSI IRQ functions are implemented in application register
             space
          3. MSI interrupts are multiplexed over 8 IRQ lines to the Host side.
      
      All of the application register space handing code is organized into
      pci-keystone-dw.c and the functions are called from pci-keystone.c to
      implement PCI controller driver.  Also add necessary DT documentation and
      update the MAINTAINERS file for the driver.
      
      [bhelgaas: spelling and whitespace fixes]
      Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      CC: Russell King <linux@arm.linux.org.uk>
      CC: Grant Likely <grant.likely@linaro.org>
      CC: Rob Herring <robh+dt@kernel.org>
      CC: Mohit Kumar <mohit.kumar@st.com>
      CC: Pratyush Anand <pratyush.anand@st.com>
      CC: Jingoo Han <jg1.han@samsung.com>
      CC: Richard Zhu <r65037@freescale.com>
      CC: Kishon Vijay Abraham I <kishon@ti.com>
      CC: Marek Vasut <marex@denx.de>
      CC: Arnd Bergmann <arnd@arndb.de>
      CC: Pawel Moll <pawel.moll@arm.com>
      CC: Mark Rutland <mark.rutland@arm.com>
      CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
      CC: Kumar Gala <galak@codeaurora.org>
      CC: Randy Dunlap <rdunlap@infradead.org>
      CC: Grant Likely <grant.likely@linaro.org>
      0c4ffcfe
  8. 04 9月, 2014 1 次提交
  9. 23 7月, 2014 1 次提交
  10. 14 7月, 2014 1 次提交
  11. 31 5月, 2014 1 次提交
  12. 28 5月, 2014 1 次提交
  13. 31 10月, 2013 1 次提交
  14. 28 9月, 2013 1 次提交
  15. 14 8月, 2013 1 次提交
  16. 13 8月, 2013 1 次提交
  17. 27 6月, 2013 1 次提交
  18. 21 5月, 2013 1 次提交
    • T
      pci: PCIe driver for Marvell Armada 370/XP systems · 45361a4f
      Thomas Petazzoni 提交于
      This driver implements the support for the PCIe interfaces on the
      Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
      cover earlier families of Marvell SoCs, such as Dove, Orion and
      Kirkwood.
      
      The driver implements the hw_pci operations needed by the core ARM PCI
      code to setup PCI devices and get their corresponding IRQs, and the
      pci_ops operations that are used by the PCI core to read/write the
      configuration space of PCI devices.
      
      Since the PCIe interfaces of Marvell SoCs are completely separate and
      not linked together in a bus, this driver sets up an emulated PCI host
      bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
      interface.
      
      In addition, this driver enumerates the different PCIe slots, and for
      those having a device plugged in, it sets up the necessary address
      decoding windows, using the mvebu-mbus driver.
      Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Acked-by: NBjorn Helgaas <bhelgaas@google.com>
      Signed-off-by: NJason Cooper <jason@lakedaemon.net>
      45361a4f