1. 05 3月, 2014 30 次提交
    • S
      ARM: imx6: move v7_cpu_resume() into suspend-imx6.S · c356bdb4
      Shawn Guo 提交于
      The suspend-imx6.S is introduced recently for suspend low-level assembly
      code.  Since function v7_cpu_resume() is only used by suspend support,
      it makes sense to move the function into suspend-imx6.S, and control the
      build of the file with CONFIG_SUSPEND option.
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      c356bdb4
    • P
      ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority · 7ea653ef
      Philipp Zabel 提交于
      This is needed so that the IPU framebuffer scanout cannot be
      starved by VPU or GPU activity.
      Some boards like the SabreLite and SabreSD seem to set this in
      the DCD already, but the documented register reset values do not
      contain the necessary settings.
      Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      7ea653ef
    • P
      ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr · ef3adc18
      Philipp Zabel 提交于
      Masks for IPU AXI transaction QoS settings
      Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      ef3adc18
    • S
      bus: imx-weim: support CS GPR configuration · 8d9ee21e
      Shawn Guo 提交于
      For imx50-weim and imx6q-weim type of devices, there might a WEIM CS
      space configuration register in General Purpose Register controller,
      e.g. IOMUXC_GPR1 on i.MX6Q.
      
      Depending on which configuration of the following 4 is chosen for given
      system, IOMUXC_GPR1[11:0] should be set up as 05, 033, 0113 or 01111
      correspondingly.
      
      	CS0(128M) CS1(0M)  CS2(0M)  CS3(0M)
      	CS0(64M)  CS1(64M) CS2(0M)  CS3(0M)
      	CS0(64M)  CS1(32M) CS2(32M) CS3(0M)
      	CS0(32M)  CS1(32M) CS2(32M) CS3(32M)
      
      The patch creates a function for such type of devices, which scans
      'ranges' property of WEIM node and build the GPR value incrementally.
      Thus the WEIM CS GPR can be set up automatically at boot time.
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      Reviewed-by: NPhilippe De Muyter <phdm@macqel.be>
      Tested-by: NPhilippe De Muyter <phdm@macqel.be>
      8d9ee21e
    • F
      ARM: mach-imx: Kconfig: Remove IMX_HAVE_PLATFORM_IMX2_WDT from SOC_IMX53 · 7899d7d5
      Fabio Estevam 提交于
      SOC_IMX53 is a device-tree only platform, so we don't need
      IMX_HAVE_PLATFORM_IMX2_WDT at all because this symbol only provides some code
      to help register imx2-wdt platform devices.
      Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
      Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      7899d7d5
    • F
      ARM: imx_v6_v7_defconfig: Select CONFIG_DEBUG_FS · c0f1a4fe
      Fabio Estevam 提交于
      CONFIG_DEBUG_FS is a very useful debug option as it allow us to access key
      data such as the clock tree, for example:
      
      mount -t debugfs debugfs /sys/kernel/debug
      cat /sys/kernel/debug/clk/clk_summary
      Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      c0f1a4fe
    • F
      ARM: mach-imx: Select CONFIG_SRAM at ARCH_MXC level · 67f5b308
      Fabio Estevam 提交于
      Booting a mx6q system built with multi_v7_defconfig leads to the following
      error messages on boot:
      
      [    0.037758] imx6q_ocram_suspend_init: ocram pool unavailable!
      [    0.037768] imx6_pm_common_init: failed to initialize ocram suspend -19!
      
      This happens because CONFIG_SRAM is not selected by default in
      multi_v7_defconfig.
      
      Fix this by selecting CONFIG_SRAM at ARCH_MXC level, so that other SoCs could
      use the SRAM driver as well.
      
      As SRAM automatically selects GENERIC_ALLOCATOR, just drop it from the Kconfig
      entry.
      Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      67f5b308
    • A
      ARM: imx: add speed grading check for i.mx6 soc · c962a099
      Anson Huang 提交于
      The fuse map of speed_grading[1:0] defines the max speed
      of ARM, see below the definition:
      
      2b'11: 1200000000Hz;
      2b'10: 996000000Hz;
      2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
      2b'00: 792000000Hz;
      
      Need to remove all illegal setpoints according to fuse
      map.
      Signed-off-by: NAnson Huang <b20788@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      c962a099
    • A
      ARM: imx: avoid calling clk APIs in idle thread which may cause schedule · 6e6cdf66
      Anson Huang 提交于
      As clk_pllv3_wait_lock will call usleep_range, and the clk APIs
      mutex lock may be held when CPU entering idle, so calling clk
      APIs must be avoided in cpu idle thread, this is to avoid reschedule
      warning in cpu idle, just access register directly to achieve that.
      
      bad: scheduling from the idle thread!
      CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.14.0-rc1+ #657
      Backtrace:
      [<80012188>] (dump_backtrace) from [<8001246c>] (show_stack+0x18/0x1c)
       r6:808c0038 r5:00000000 r4:808e5a1c r3:00000000
      [<80012454>] (show_stack) from [<8064b2ec>] (dump_stack+0x84/0x9c)
      [<8064b268>] (dump_stack) from [<80055ee0>] (dequeue_task_idle+0x20/0x30)
       r5:808bef40 r4:bf7dff40
      [<80055ec0>] (dequeue_task_idle) from [<8004f028>] (dequeue_task+0x30/0x50)
       r4:bf7dff40 r3:80055ec0
      [<8004eff8>] (dequeue_task) from [<800503c0>] (deactivate_task+0x30/0x34)
       r4:bf7dff40
      [<80050390>] (deactivate_task) from [<8064d8e4>] (__schedule+0x2c8/0x5c0)
      [<8064d61c>] (__schedule) from [<8064dc14>] (schedule+0x38/0x88)
       r10:80912964 r9:808c1e50 r8:808c0038 r7:808cbf30 r6:80e128ec r5:60000093
       r4:80912968
      [<8064dbdc>] (schedule) from [<8064dfec>] (schedule_preempt_disabled+0x10/0x14)
      [<8064dfdc>] (schedule_preempt_disabled) from [<8064ebc0>] (mutex_lock_nested+0x1c0/0x3c0)
      [<8064ea00>] (mutex_lock_nested) from [<804ae71c>] (clk_prepare_lock+0x44/0xe4)
       r10:806554cc r9:bf7df1bc r8:808cf4f8 r7:808cf544 r6:bf7df1b8 r5:808c0010
       r4:80e69750
      [<804ae6d8>] (clk_prepare_lock) from [<804af214>] (clk_get_rate+0x14/0x64)
       r6:bf7df1b8 r5:00000002 r4:bf017000 r3:80922ad0
      [<804af200>] (clk_get_rate) from [<80025d30>] (imx6sl_set_wait_clk+0x18/0x20)
       r5:00000002 r4:00000001
      [<80025d18>] (imx6sl_set_wait_clk) from [<80023454>] (imx6sl_enter_wait+0x20/0x48)
      [<80023434>] (imx6sl_enter_wait) from [<80477c24>] (cpuidle_enter_state+0x44/0xfc)
       r4:3c386e48 r3:80023434
      [<80477be0>] (cpuidle_enter_state) from [<80477dd8>] (cpuidle_idle_call+0xfc/0x160)
       r8:808cf4f8 r7:00000001 r6:80e69534 r5:00000000 r4:bf7df1b8
      [<80477cdc>] (cpuidle_idle_call) from [<8000f61c>] (arch_cpu_idle+0x10/0x50)
       r9:808c0000 r8:00000000 r7:80921a89 r6:808c8938 r5:808c899c r4:808c0000
      [<8000f60c>] (arch_cpu_idle) from [<8006fa94>] (cpu_startup_entry+0x108/0x160)
      [<8006f98c>] (cpu_startup_entry) from [<806452ac>] (rest_init+0xb4/0xdc)
       r7:808afae0
      [<806451f8>] (rest_init) from [<8086fb58>] (start_kernel+0x328/0x38c)
       r6:ffffffff r5:808c8880 r4:808c8a30
      [<8086f830>] (start_kernel) from [<80008074>] (0x80008074)
      Signed-off-by: NAnson Huang <b20788@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      6e6cdf66
    • S
      ARM: imx6q: support ptp and rmii clock from pad · 810c0ca8
      Shawn Guo 提交于
      On imx6qdl, the ENET RMII and PTP clock can come from either internal
      ANATOP/CCM or external clock source through pad GPIO_16.  But in case
      of the external clock source, bit IOMUXC_GPR1[21] needs to be cleared.
      
      The patch adds the support for systems that use an external clock source
      and distinguishes above two cases by checking if the PTP clock specified
      in device tree is the one coming from the internal ANATOP/CCM.
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      810c0ca8
    • S
      ARM: imx6q: remove unneeded clk lookups · b30c6d01
      Shawn Guo 提交于
      Since commit (a94f8ecb ARM: imx6q: remove board specific CLKO setup),
      a number of clk lookups in imx6q clock driver is no longer needed.
      Let's remove them.
      
      The cpu0 lookup is also removed since we are now running imx6 cpufreq
      driver and looking up clocks from device tree.
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      b30c6d01
    • F
      ARM: imx_v6_v7_defconfig: Select CONFIG_MMC_UNSAFE_RESUME · f19e1c4a
      Fabio Estevam 提交于
      PM subsystem treats mmc card as removed during suspend.
      
      If MMC is used to store the root file system, it is better to tell the kernel
      not to treat it as a removable media, so select CONFIG_MMC_UNSAFE_RESUME for
      such purpose.
      Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      f19e1c4a
    • F
      ARM: imx_v4_v5_defconfig: Select CONFIG_MMC_UNSAFE_RESUME · 135d6908
      Fabio Estevam 提交于
      PM subsystem treats mmc card as removed during suspend.
      
      If MMC is used to store the root file system, it is better to tell the kernel
      not to treat it as a removable media, so select CONFIG_MMC_UNSAFE_RESUME for
      such purpose.
      Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      135d6908
    • S
      ARM: imx: enable delaytimer on the imx timer · 1119c84a
      Sebastian Andrzej Siewior 提交于
      The imx can support timer-based delays, so implement this.
      Skips past jiffy calibration.
      Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      1119c84a
    • A
      ARM: imx: add always-on clock array for i.mx6sl to maintain correct usecount · 17626b7c
      Anson Huang 提交于
      IPG, ARM and MMDC's clock should be enabled during kernel boot up,
      so we need to maintain their usecount, otherwise, they may be
      disabled unexpectedly if their children's clock are turned off, and
      caused their parent PLLs also get disabled, which is incorrect.
      Signed-off-by: NAnson Huang <b20788@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      17626b7c
    • A
      ARM: imx: add suspend in ocram support for i.mx6sl · 64b08681
      Anson Huang 提交于
      i.MX6SL's suspend in ocram function is derived from i.MX6Q,
      it can lower the DDR IO power from ~10mA@1.2V to ~1mA@1.2V,
      measured on i.MX6SL EVK board, SH5.
      Signed-off-by: NAnson Huang <b20788@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      64b08681
    • A
      ARM: imx: add suspend in ocram support for i.mx6dl · da9e9261
      Anson Huang 提交于
      i.MX6DL's suspend in ocram function is derived from i.MX6Q,
      it can lower the DDR IO power from ~26mA@1.5V to ~15mA@1.5V,
      measured on i.MX6DL SabreSD board, R25.
      Signed-off-by: NAnson Huang <b20788@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      da9e9261
    • A
      ARM: imx: add suspend in ocram support for i.mx6q · df595746
      Anson Huang 提交于
      When system enter suspend, we can set the DDR IO to
      high-Z state to save DDR IOs' power consumption, this
      operation can save many power(from ~26mA@1.5V to ~15mA@1.5V,
      measured on i.MX6Q SabreSD board, R25) of DDR IOs. To
      achieve that, we need to copy the suspend code to ocram
      and run the low level hardware related code(set DDR IOs
      to high-Z state) in ocram.
      
      If there is no ocram space available, then system will
      still do suspend in external DDR, hence no DDR IOs will
      be set to high-Z.
      
      The OCRAM usage layout is as below,
      
      ocram suspend region(4K currently):
      ======================== high address ======================
                                    .
                                    .
                                    .
                                    ^
                                    ^
                                    ^
                            imx6_suspend code
                   PM_INFO structure(imx6_cpu_pm_info)
      ======================== low address =======================
      Reviewed-by: NSascha Hauer <s.hauer@pengutronix.de>
      Signed-off-by: NAnson Huang <b20788@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      df595746
    • S
      ARM i.MX: remove PWM platform support · 02ae8e86
      Sascha Hauer 提交于
      As the i.MX pwm driver is devicetree only, remove the platform
      support for this device.
      Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      02ae8e86
    • L
      ARM: imx: clk-vf610: Suppress duplicate const sparse warning · b78f1e80
      Liu Ying 提交于
      There should be no duplicate const specifiers for those static
      constant character string arrays defined for clock mux options.
      Also, the arrays are only taken as the 5th argument for the
      imx_clk_mux() function, which is in the type of 'const char
      **parents'.  So, let's remove the 2nd const specifier right
      after 'char'.
      
      This patch fixes these sparse warnings:
      arch/arm/mach-imx/clk-vf610.c:66:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:67:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:68:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:69:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:70:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:71:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:72:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:73:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:74:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:75:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:76:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:77:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:78:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:79:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:80:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:81:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:83:25: warning: duplicate const
      arch/arm/mach-imx/clk-vf610.c:84:25: warning: duplicate const
      Signed-off-by: NLiu Ying <Ying.Liu@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      b78f1e80
    • L
      ARM: imx: clk-imx6sl: Suppress duplicate const sparse warning · b21c22e3
      Liu Ying 提交于
      There should be no duplicate const specifiers for those static
      constant character string arrays defined for clock mux options.
      Also, the arrays are only taken as the 5th argument for the
      imx_clk_mux() function, which is in the type of 'const char
      **parents'.  So, let's remove the 2nd const specifier right
      after 'char'.
      
      This patch fixes these sparse warnings:
      arch/arm/mach-imx/clk-imx6sl.c:21:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:22:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:23:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:24:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:25:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:26:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:27:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:28:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:29:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:30:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:31:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:32:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:33:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:34:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:35:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:36:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:37:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:38:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:39:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:40:25: warning: duplicate const
      arch/arm/mach-imx/clk-imx6sl.c:41:25: warning: duplicate const
      Signed-off-by: NLiu Ying <Ying.Liu@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      b21c22e3
    • J
      ARM: imx: add select on ARCH_MXC for cpufreq support · 5a1513f6
      John Tobias 提交于
      Move ARCH_HAS_CPUFREQ, ARCH_HAS_OPP and PM_OPP on ARCH_MXC so that
      the user can enable the cpufreq support for iMX6Q and/or iMX6SL.
      Signed-off-by: NJohn Tobias <john.tobias.ph@gmail.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      5a1513f6
    • D
      ARM: imx_v6_v7_defconfig: Enable some drivers used on the cpuimx35. · 80130a59
      Denis Carikli 提交于
      The eukrea cpuimx35 has a pcf8563 RTC and a LCD gpio regulator.
      
      We enable the respective drivers in order to be able to use theses
        features with this configuration.
      
      Cc: Sascha Hauer <kernel@pengutronix.de>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: Fabio Estevam <fabio.estevam@freescale.com>
      Cc: Eric Bénard <eric@eukrea.com>
      Signed-off-by: NDenis Carikli <denis@eukrea.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      80130a59
    • D
      ARM i.MX35: build in pinctrl support. · c51bcd15
      Denis Carikli 提交于
      shawn.guo: While at it, we drop 'select PINCTRL' from SOC_IMX35, since
      it's been covered by ARCH_MXC.
      
      Cc: Rob Herring <rob.herring@calxeda.com>
      Cc: Pawel Moll <pawel.moll@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
      Cc: devicetree@vger.kernel.org
      Cc: Sascha Hauer <kernel@pengutronix.de>
      Cc: Fabio Estevam <fabio.estevam@freescale.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Eric Bénard <eric@eukrea.com>
      Signed-off-by: NDenis Carikli <denis@eukrea.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      c51bcd15
    • D
      ARM: imx_v6_v7_defconfig: Enable backlight gpio support. · 94645973
      Denis Carikli 提交于
      The eukrea mbimxsd51 has a gpio backlight for its
        LCD display, so we turn that driver on.
      
      Cc: Sascha Hauer <kernel@pengutronix.de>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: Fabio Estevam <fabio.estevam@freescale.com>
      Cc: Eric Bénard <eric@eukrea.com>
      Signed-off-by: NDenis Carikli <denis@eukrea.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      94645973
    • A
      ARM: imx: add cpuidle support for i.mx6sl · 751f7e99
      Anson Huang 提交于
      Add cpuidle support for i.MX6SL, currently only support
      two cpuidle levels(ARM wfi and WAIT mode), and add software
      workaround for WAIT mode errata as below:
      
      ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
                during WAIT mode entry process could cause cache memory
                corruption.
      
      Software workaround:
          To prevent this issue from occurring, software should ensure that
      the ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
      entering WAIT mode.
      Signed-off-by: NAnson Huang <b20788@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      751f7e99
    • A
      ARM: imx: AHB rate must be set to 132MHz on i.mx6sl · 848db4a0
      Anson Huang 提交于
      The reset value of AHB divider is 3, so current AHB rate
      is 99MHz which is not correct for kernel, need to ensure
      AHB rate is 132MHz in clk driver, as ipg is sourcing from
      AHB, and it should be 66MHz by default.
      Signed-off-by: NAnson Huang <b20788@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      848db4a0
    • F
      ARM: imx: Use INT_MEM_CLK_LPM as the bit name · fa6be65e
      Fabio Estevam 提交于
      Bit 17 of register CCM_CGPR is called INT_MEM_CLK_LPM as per the mx6
      reference manual, so use this name instead.
      Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      fa6be65e
    • F
      ARM: imx_v6_v7_defconfig: Select PCI support · c0bea59c
      Fabio Estevam 提交于
      Let PCI driver be enabled by default.
      Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
      Reviewed-by: NMarek Vasut <marex@denx.de>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      c0bea59c
    • S
      Merge tag 'kconfig-cleanup-for-3.15' into imx/soc · c1b2a174
      Shawn Guo 提交于
      - Remove common kconfig options required by multi-platform builds out
      of individual platforms as they are redundant.
      - Make SMP, CACHE_L2X0 and GPIO config options user visible on
      multi-platform builds as most platforms enable these options and all
      platforms can run with them enabled.
      - Make multi-platform v6 default to more optimal v6k rather than v6
      - Remove the last bit of mach-virt and convert it to just a kconfig
      option.
      
      Conflicts:
      	arch/arm/mach-omap2/Kconfig
      c1b2a174
  2. 24 2月, 2014 10 次提交