ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr
Masks for IPU AXI transaction QoS settings Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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Masks for IPU AXI transaction QoS settings Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>