Add support for the global clock controller found on MSM8998
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: NJoonwoo Park <joonwoop@codeaurora.org>
Signed-off-by: NImran Khan <kimran@codeaurora.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
[bjorn: Specify regs for alpha_plls, fix white spaces and add binding]
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add clock binding doc update for imx6sll.
Signed-off-by: NBai Ping <ping.bai@nxp.com>
Acked-by: NDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Document that Stratix10 clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the Stratix10
platform.
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This patch adds the reset binding entry for STM32MP1
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

The Allwinner H6 CCU has a "HDMI Slow Clock", which is currently missing
in the ccu-sun50i-h6 driver.

Add this missing clock to the driver.

Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>

XO is onchip buffer clock to generate 19.2MHz.

This patch adds support to 5 XO buffer clocks found on PMIC8921,
these buffer clocks can be controlled from external pin or in
manual mode.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

add new clocks according to ECO design change
Signed-off-by: NWeiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This patch adds DSI clock for STM32F469 board
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Update of END_PRIMARY_CLK was missed, it should be after CLK_SYSCLK
hsi and sysclk are overwritten by gpioa and gpiob.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Tested-by: NPhilippe Cornu <philippe.cornu@st.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys.
Signed-off-by: NRyder Lee <ryder.lee@mediatek.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Just add binding for a fixed-factor clock axisel_d4, which would be
referenced by PWM devices on MT7623 or MT2701 SoC.

Cc: stable@vger.kernel.org
Fixes: 1de9b216 ("clk: mediatek: Add dt-bindings for MT2701 clocks")
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add new power domains(MFG_SC1/MFG_SC2/MFG_SC3)
for MT2712 according to ECO design change.
Signed-off-by: NWeiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>

The Allwinner H6 SoC has a CCU which has been largely rearranged.

Add support for it in the sunxi-ng CCU framework.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>

Added index of RTC gate clocks which are used by some devices on aon
area of SC9860, for example the Watchdog timer.
Signed-off-by: NChunyan Zhang <chunyan.zhang@spreadtrum.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add support for specifying event actions to trigger wakeup when using
the gpio-keys input device as a wakeup source.

This would allow the device to configure when to wakeup the system. For
example a gpio-keys input device for pen insert, may only want to wakeup
the system when ejecting the pen.
Suggested-by: NBrian Norris <briannorris@chromium.org>
Signed-off-by: NJeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>

Add the new HIFI pll to axg clock bindings
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Move the definitions of constants used in the dt-bindings from
include/sound/rt5651.h to include/dt-bindings/sound/rt5651.h.

As dt-bindings headers may also be parsed by the dt-compiler, they cannot
use enums, only defines, so this commit also changes the code declaring
the constants to use defines.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Add relevant header files required for dt-bindings of SCPSYS power domain
control for subsystems found on MT7623A SoC.
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Cc: Rob Herring <robh@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
[mb: clean-up commit message]
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>

This patch introduces the mechanism to probe stm32mp1 driver.
It also defines registers definition.
This patch also introduces the generic mechanism to register
a clock (a simple gate, divider and fixed factor).

All clocks will be defined in one table.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

This clock is needed by the memory built-in self test work around.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NJon Hunter <jonathanh@nvidia.com>
Tested-by: NJon Hunter <jonathanh@nvidia.com>
Tested-by: NHector Martin <marcan@marcan.st>
Tested-by: NAndre Heider <a.heider@gmail.com>
Tested-by: NMikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: NMikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

STM32F769 SoC provides 2 SDMMC instances, add missing
RCC SDMMC2 entry for it.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

Meson8b is a cost reduced variant of the Meson8 SoC. It's package size
is smaller than Meson8.
Unfortunately there are a few key differences which cannot be seen
without close inspection of the code and the public S805 datasheet:
- the GPIOX bank is missing the GPIOX_12, GPIOX_13, GPIOX_14 and
  GPIOX_15 GPIOs
- the GPIOY bank is missing the GPIOY_2, GPIOY_4, GPIOY_5, GPIOY_15 and
  GPIOY_16 GPIOs
- the GPIODV bank is missing all GPIOs except GPIODV_9, GPIODV_24,
  GPIODV_25, GPIODV_26, GPIODV_27, GPIODV_28 and GPIODV_29
- the GPIOZ bank is missing completely
- there is a new GPIO bank called "DIF"

This means that Meson8b only has 83 actual GPIO lines. Without any holes
there would be 130 GPIO lines in total (120 are inherited from Meson8
plus 10 new from the DIF bank).

GPIOs greater GPIOZ_3 (whose ID is 83 - as a reminder: this is exactly
the number of actual GPIO lines on Meson8b and also the value of
meson8b_cbus_pinctrl_data.num_pins) cannot berequested. Using CARD_6
(which used ID 100 prior to this patch, "base of the GPIO controller was
382) as an example:
$ echo 482 > /sys/class/gpio/export
export_store: invalid GPIO 482

This removes all non-existing pins from to dt-bindings header file
(include/dt-bindings/gpio/meson8b-gpio.h). This allows us to have a
consecutive numbering for the GPIO #defines (GPIOY_2 doesn't exist for
example, so previously the GPIOY_3 ID was "GPIOY_1 + 2", after this
patch it is "GPIOY_1 + 1"). As a nice side-effect this means that we get
compile-time (instead of runtime) errors if Meson8b .dts uses a pin that
only exists on Meson8.

Additionally the pinctrl-meson8b driver has to be updated to handle this
new GPIO numbering. By default a struct meson_bank only handles GPIO
banks where the pins are numbered consecutively because it calculates
the bit offsets based on the GPIO IDs.
This is solved by  taking the original BANK() definition and splitting it
into consecutive subsets (X0..11 and X16..21). The bit offsets for each
new bank includes the skipped GPIOs (the definition of the "X0..11" bank
is identical to the old "X" bank apart from the "last IRQ" field, the
definition of the new, split "X16..21" bank takes the original "X" bank
and adds 16 - the start of the new split bank - to the "first IRQ",
pullen bit, pull bit, dir bit, out bit and in bit).

Commit 984cffde ("pinctrl: Fix gpio/pin mapping for Meson8b")
fixed the same issue by setting "ngpio" (of the gpio_chip) to 130.
Unfortunately this broke in db80f0e1 ("pinctrl: meson: get rid of
unneeded domain structures").
The solution from this patch was considered to be better than the
previous attempt at fixing this because it provides compile-time error
checking for the GPIOs that exist on Meson8 but don't exist on Meson8b.

The following pins were tested on an Odroid-C1 using the sysfs GPIO
interface checking that their value (high or low) could be read:
- GPIOX_0, GPIOX_1, GPIOX_2, GPIOX_3, GPIOX_4, GPIOX_5, GPIOX_6,
  GPIOX_7, GPIOX_8, GPIOX_9, GPIOX_10, GPIOX_11, GPIOX_18, GPIOX_19,
  GPIOX_20, GPIOX_21
- GPIOY_3, GPIOY_7, GPIOY_8
(some of these had to be pulled up because they were low by default,
others were high by default so these had to be pulled down)
Reported-by: NLinus Lüssing <linus.luessing@c0d3.blue>
Suggested-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add missing pinctrl binding about I2C2 and SPI2 which would be used in
devicetree related files.
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

CLK_PLL_VIDEO needs to be referenced in HDMI DT entry as a possible
PHY clock parent.

Export it so it can be used later in DT.
Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>

According to the i.MX7D Reference Manual, the Keypad Port module
(KPP) requires this clock gate to be enabled.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add CAAM clock so that we could use the Cryptographic Acceleration and
Assurance Module (CAAM) hardware block.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: "Horia Geantă" <horia.geanta@nxp.com>
Cc: Aymen Sghaier <aymen.sghaier@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NRui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The clock COMBPHY1 has already been supported by hi3798cv200 driver,
but COMBPHY0 is missing.  It adds COMBPHY0 clock support.

Since the mux table is being shared by COMBPHY0 and COMBPHY1, it renames
comphy1_mux_p and comphy1_mux_table a bit to drop instance number '1'
from there.
Signed-off-by: NJianguo Sun <sunjianguo1@huawei.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

It's a coding-style fix, which corrects the indentation for all those
clock definitions, so that the code looks nicer and new definitions can
be added with a recommended indentation.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Initial support for R-Car M3-N (r8a77965), including core and module
clocks.

Based on Table 8.2d of "R-Car Series, 3rd Generation User's Manual:
Hardware (Rev. 0.80, Oct 31, 2017)".
Signed-off-by: NJacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Define the device tree bindings for the TDA1997X.
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NSakari Ailus <sakari.ailus@iki.fi>
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Signed-off-by: NHans Verkuil <hans.verkuil@cisco.com>
[hans.verkuil@cisco.com: make a proper commit message]
Signed-off-by: NMauro Carvalho Chehab <mchehab@s-opensource.com>

According to the i.MX7D Reference Manual,
SNVS block has a clock gate, accessing SNVS block
would need this clock gate to be enabled, add it
into clock tree so that SNVS module driver can
operate this clock gate.
Signed-off-by: NAnson Huang <Anson.Huang@nxp.com>
Acked-by: NDong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add support for R-Car M3-N (R8A77965) power areas.
Signed-off-by: NJacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add macros usable by the device tree sources to reference the R8A77980
CPG core clocks by index. The data come from the table 8.2e of the R-Car
Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017),
however I had to add the Z2 clock which is somehow present only on the
figure 8.1e...

Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: NVladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add macros usable by the device tree sources to reference R8A77980 SYSC
power domains by index.

Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: NVladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Signed-off-by: NWadim Egorov <w.egorov@phytec.de>
Signed-off-by: NDaniel Schultz <d.schultz@phytec.de>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This clock is not hclk_vio but hclk_vio_niu, the clock for the interconnect
output. The clock got fixed and the id was never used in this incorrect form,
so remove it.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This will be used from the devicetree bindings to specify the clocks
that should be obtained from the jz4770-cgu driver.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Maarten ter Huurne <maarten@treewalker.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18481/Signed-off-by: NJames Hogan <jhogan@kernel.org>

PCIE and NSS has MISC reset register in which single register has
multiple reset bit. The patch adds the DT bindings for these MISC
resets.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds the DT bindings for following IPQ8074 clocks

 - General PLL’s, NSS UBI PLL and NSS Crypto PLL.
 - 2 instances of PCIE, USB, SDCC.
 - 2 NSS UBI core and common NSS clocks. NSS is network switching
   system which accelerates the ethernet traffic. IPQ8074
   NSS has two UBI cores. Some clocks are separate for each UBI core
   and remaining NSS clocks are common.
 - NSS ethernet port clocks. IPQ8074 has 6 ethernet ports and
   each port uses different TX and RX clocks.
 - Crypto engine clocks.
 - General purpose clocks which comes over GPIO.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>