未验证 提交 55de0f31 编写于 作者: J Jernej Skrabec 提交者: Maxime Ripard

clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO

CLK_PLL_VIDEO needs to be referenced in HDMI DT entry as a possible
PHY clock parent.

Export it so it can be used later in DT.
Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>
上级 b1a1ad4b
...@@ -26,7 +26,9 @@ ...@@ -26,7 +26,9 @@
#define CLK_PLL_AUDIO_2X 3 #define CLK_PLL_AUDIO_2X 3
#define CLK_PLL_AUDIO_4X 4 #define CLK_PLL_AUDIO_4X 4
#define CLK_PLL_AUDIO_8X 5 #define CLK_PLL_AUDIO_8X 5
#define CLK_PLL_VIDEO 6
/* PLL_VIDEO is exported */
#define CLK_PLL_VE 7 #define CLK_PLL_VE 7
#define CLK_PLL_DDR 8 #define CLK_PLL_DDR 8
......
...@@ -43,6 +43,8 @@ ...@@ -43,6 +43,8 @@
#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ #ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
#define _DT_BINDINGS_CLK_SUN8I_H3_H_ #define _DT_BINDINGS_CLK_SUN8I_H3_H_
#define CLK_PLL_VIDEO 6
#define CLK_PLL_PERIPH0 9 #define CLK_PLL_PERIPH0 9
#define CLK_CPUX 14 #define CLK_CPUX 14
......
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