提交 8465baae 编写于 作者: W Weiyi Lu 提交者: Stephen Boyd

dt-bindings: clock: add clocks for MT2712

add new clocks according to ECO design change
Signed-off-by: NWeiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
上级 7928b2cb
...@@ -222,7 +222,13 @@ ...@@ -222,7 +222,13 @@
#define CLK_TOP_APLL_DIV_PDN5 183 #define CLK_TOP_APLL_DIV_PDN5 183
#define CLK_TOP_APLL_DIV_PDN6 184 #define CLK_TOP_APLL_DIV_PDN6 184
#define CLK_TOP_APLL_DIV_PDN7 185 #define CLK_TOP_APLL_DIV_PDN7 185
#define CLK_TOP_NR_CLK 186 #define CLK_TOP_APLL1_D3 186
#define CLK_TOP_APLL1_REF_SEL 187
#define CLK_TOP_APLL2_REF_SEL 188
#define CLK_TOP_NFI2X_EN 189
#define CLK_TOP_NFIECC_EN 190
#define CLK_TOP_NFI1X_CK_EN 191
#define CLK_TOP_NR_CLK 192
/* INFRACFG */ /* INFRACFG */
...@@ -281,7 +287,9 @@ ...@@ -281,7 +287,9 @@
#define CLK_PERI_MSDC30_3_EN 41 #define CLK_PERI_MSDC30_3_EN 41
#define CLK_PERI_MSDC50_0_HCLK_EN 42 #define CLK_PERI_MSDC50_0_HCLK_EN 42
#define CLK_PERI_MSDC50_3_HCLK_EN 43 #define CLK_PERI_MSDC50_3_HCLK_EN 43
#define CLK_PERI_NR_CLK 44 #define CLK_PERI_MSDC30_0_QTR_EN 44
#define CLK_PERI_MSDC30_3_QTR_EN 45
#define CLK_PERI_NR_CLK 46
/* MCUCFG */ /* MCUCFG */
......
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