Switch to the stable UART bindings and add the correct gate clocks
to the non-AO UART nodes.
This fixes the non-AO UARTs if the bootloader didn't un-gate the clocks.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The SAR ADC modules doesn't require The "sana" clock.
Acked-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NXingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: NYixun Lan <yixun.lan@amlogic.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Amlogic's vendor kernel prints these PL310 L2 cache controller settings
during boot:
  8 ways, 4096 sets, CACHE_ID 0x4100a0c9,  Cache size: 1048576 B
  AUX_CTRL 0x7ec80001, PERFETCH_CTRL 0x71000007, POWER_CTRL  0x00000000
  TAG_LATENCY 0x00000111, DATA_LATENCY 0x00000222

Add the "prefetch-data", "prefetch-instr" and "arm,shared-override"
properties to get the same L2 cache controller configuration as the
vendor kernel.
Two differences still remain:
- L310_AUX_CTRL_NS_INT_CTRL is currently not supported by the cache-l2x0
driver
- bit 23 is set by the vendor kernel, but this is defined in cache-l2x0.h
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Meson6, Meson8 and Meson8b use a similar IP block which has access to
512 bytes of efuse data.
During SoC manufacturing some calibration settings for the CVBS
connector and the internal temperature sensor are written to this efuse.
On some boards it additionally stores for example the MAC addresses.

The efuse is enabled on Meson8 and Meson8b but kept disabled on Meson6
since we do not have a clock driver there (which is required to read
data from the efuse).
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Booting the secondary CPU cores involves the following nodes/devices:
- SCU (Snoop-Control-Unit, for which we already have a DT node)
- a reset line for each CPU core, provided by the reset-controller
  which is built into the clock-controller
- the PMU (power management unit) which controls the power of the CPU
  cores
- a range in the SRAM specifically reserved for booting secondary CPU
  cores
- the "enable-method" which activates booting the secondary CPU cores

This adds all required nodes and properties to boot the secondary CPU
cores.
Suggested-by: NCarlo Caione <carlo@caione.org>
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Meson6, Meson8 and Meson8b are using the same MMC controller IP. This
adds the MMC controller node to meson.dtsi so it can be used by all
SoCs.

The controller itself is a bit special, because it has multiple slots.
Each slot is accessed through a sub-node of the controller. However,
currently the driver for this hardware only supports one slot.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Remove pin offset on the AO controller. meson pinctrl no longer has
this quirk
Tested-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The SoC type and version information is encoded in different register
blocks.
The SoC type information is part of the "assist" registers.
The misc version information is part of the "bootrom" registers.
On Meson8, Meson8b and Meson8m2 there is additionally information about
the minor version. This information is stored in the "analog top"
registers.

Add the nodes for these register blocks so we can decode the SoC type
and version information.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The clock controller provides a few reset lines as well. Add the
corresponding CPU cores.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

pwm_ab and pwm_cd are already inherited from meson.dtsi, we only need to
define the correct "compatible" string so the pwm-meson driver can
choose the parent clocks correctly.
pwm_ef is added to meson8.dtsi directly (similar to how it's done in
meson8b.dtsi) as this controller only exists on Meson8 and Meson8b.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Until now clk81 was used as gate clock for the ethernet controller on
Meson8 whereas Meson8b did not configure a gate clock at all. Use
CLKID_ETH for both SoCs, which is the real gate clock for the ethernet
controller.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Amlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many
other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be
used during SMP boot.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This adds the DWC2 USB controller nodes and the corresponding USB2 PHY
nodes to meson.dtsi (as the same - or at least a very similar) IP block
is used on all SoCs (at the same physical address).
Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the
DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be
initialized by the dwc2 driver.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

All supported Meson SoCs have a random number generator in CBUS.
Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number
register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two
32-bit random number registers. The existing meson-rng driver only
supports the lower 32-bit - but it still works fine on the older SoCs
apart from this small limitation.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

There seem to be two memory regions that need to be reserved, otherwise
the system just hangs when running:
$ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \
  --vm-keep -m 1

The first memory region is really crucial and without it the system
hangs. I could not find any references to this in Amlogic's GPL kernel
sources.
The second region is used by the "suspend firmware". The u-boot sources
(/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend
firmware is located at "64M + 15M" which matches CONFIG_MESON_SUSPEND in
the Amlogic GPL kernel sources. The "suspend firmware" is responsible
for waking up the system from suspend state.

This also fixes reading the full SD card as without this the system
would simply hang (probably related to the first memory region, if some
buffer is allocated there).
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8
and Meson8b to allow boards to use it. Some boards use it to connect a
button to it.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This adds the definition of the PWM_E (CBUS) and PWM_F (AOBUS) to
meson8.dtsi, allowing devices to use them. PWM_E can be used on some
devices to generate the 32.768kHz clock for the SDIO wifi module, while
PWM_F can be used to control the power LED.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This replaces the "/include/" syntax with the "#include" syntax in all
Amlogic Meson .dts and .dtsi files. That is required to use preprocessor
defines (like GIC_SPI and IRQ_TYPE_EDGE_RISING) in meson.dtsi (all files
which directly or indirectly include meson.dtsi need to use the
"#include" syntax, otherwise the .dts files cannot be compiled).
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The IR receiver pins are currently defined in the CBUS pin-controller.
However the pins are in the AO region, which is controlled by the AOBUS
pin-controller. Move the pins to pinctrl_aobus so they can actually be
used.

Fixes: b60e1157 ("ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8b")
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This removes the dummy clk81 gate and replaces it with the actual clock
controller's CLKID_CLK81. This will also allow us to pass the real clock
IDs to all devices where the clock is controlled by clkc in the future.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This patch extends the L2 cache controller node for the Amlogic Meson8
and Meson8b SoCs with some missing parameters. These are taken from the
Amlogic GPL kernel source.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
[apply the change to Meson8 and Meson8b and updated description]
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The Amlogic Meson SoCs have most of the internal peripherals organized
in busses. Use them to make the dts easier to read and to avoid
duplicated register (bus) offset definitions.

The bus information is taken from the vendor kernel:
	#define IO_CBUS_PHY_BASE        0xc1100000  ///2M
	#define IO_AOBUS_PHY_BASE       0xc8100000  ///1M

There are more internal busses (such as the abp bus which seems to
contain audio, HDMI and Mali registers), but since we don't have
drivers for them yet these are not added (yet).
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
[khilman: minor whitespace fix]
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Tested-by: NKevin Hilman <khilman@baylibre.com>

Add pinctrl node to the DTSI file for meson8 and sub-nodes for some
standard mux configurations.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NCarlo Caione <carlo@endlessm.com>

This enables the L2 cache controller available in Amlogic SoCs.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NCarlo Caione <carlo@caione.org>

This adds a dtsi for Amlogic Meson8 SoCs. It differs from the Meson6
dtsi for the number of Cortex-A9 cores (4 vs 2) and for the frequency
of clk81.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NCarlo Caione <carlo@caione.org>

The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex
A9 and an ARM Mali-400 GPU.
This patch adds two basic DTSI for the preliminary support of Meson and
Meson6 SoCs. Another DTS is also added for supporting the atv1200 board,
produced by Geniatech inc.
Signed-off-by: NCarlo Caione <carlo@caione.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>