1. 30 5月, 2017 1 次提交
  2. 20 7月, 2016 1 次提交
  3. 19 7月, 2016 1 次提交
  4. 15 7月, 2016 1 次提交
  5. 12 5月, 2016 6 次提交
  6. 11 5月, 2016 15 次提交
  7. 02 5月, 2016 1 次提交
  8. 14 4月, 2016 1 次提交
    • A
      dmaengine: dw: rename masters to reflect actual topology · c422025c
      Andy Shevchenko 提交于
      The source and destination masters are reflecting buses or their layers to
      where the different devices can be connected. The patch changes the master
      names to reflect which one is related to which independently on the transfer
      direction.
      
      The outcome of the change is that the memory data width is now always limited
      by a data width of the master which is dedicated to communicate to memory.
      
      The patch will not break anything since all current users have the same data
      width for all masters. Though it would be nice to revisit avr32 platforms to
      check what is the actual hardware topology in use there. It seems that it has
      one bus and two masters on it as stated by Table 8-2, that's why everything
      works independently on the master in use. The purpose of the sequential patch
      is to fix the driver for configuration of more than one bus.
      
      The change is done in the assumption that src_master and dst_master are
      reflecting a connection to the memory and peripheral correspondently on avr32
      and otherwise on the rest.
      Acked-by: NHans-Christian Egtvedt <egtvedt@samfundet.no>
      Acked-by: NMark Brown <broonie@kernel.org>
      Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      c422025c
  9. 31 3月, 2015 1 次提交
  10. 25 3月, 2015 3 次提交
  11. 08 1月, 2015 6 次提交
  12. 07 1月, 2015 1 次提交
  13. 20 10月, 2014 1 次提交
  14. 27 3月, 2014 1 次提交