1. 23 2月, 2016 1 次提交
  2. 21 6月, 2015 1 次提交
    • T
      clk: samsung: add infrastructure to register cpu clocks · ddeac8d9
      Thomas Abraham 提交于
      The CPU clock provider supplies the clock to the CPU clock domain. The
      composition and organization of the CPU clock provider could vary among
      Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
      and gates. This patch defines a new clock type for CPU clock provider and
      adds infrastructure to register the CPU clock providers for Samsung
      platforms.
      
      Changes by Bartlomiej:
      - fixed issue with setting lower dividers before the parent clock speed
        was lowered (the issue resulted in lockup on Exynos4210 SoC based
        Origen board when "ondemand" cpufreq governor was stress tested)
      - fixed missing spin_unlock on error in exynos_cpuclk_post_rate_change()
        problem by moving cfg_data search outside of the spin locked area
      - removed leftover kfree() in exynos_register_cpu_clock() that could
        result in dereferencing the NULL pointer on error
      - moved spin_lock earlier in exynos_cpuclk_pre_rate_change() to cover
        reading of E4210_SRC_CPU and E4210_DIV_CPU1 registers
      - added missing "last chance" checks to wait_until_divider_stable() and
        wait_until_mux_stable() (needed in case that IRQ handling took long
        time to proceed and resulted in function printing incorrect error
        message about timeout)
      - moved E4210_CPU_DIV[0,1]() macros just before their only users,
        this resulted in moving them from patch #2 to patch #3/6 ("clk:
        samsung: exynos4: add cpu clock configuration data and instantiate
        cpu clock")
      - removed E5250_CPU_DIV[0,1](), E5420_EGL_DIV0() and E5420_KFC_DIV()
        macros for now
      - added my Copyrights to drivers/clk/samsung/clk-cpu.c
      
      Cc: Tomasz Figa <tomasz.figa@gmail.com>
      Cc: Mike Turquette <mturquette@linaro.org>
      Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
      Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
      Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
      Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
      ddeac8d9
  3. 29 4月, 2015 1 次提交
  4. 05 2月, 2015 1 次提交
  5. 31 10月, 2014 2 次提交
  6. 26 7月, 2014 1 次提交
  7. 19 7月, 2014 2 次提交
  8. 31 5月, 2014 1 次提交
  9. 15 5月, 2014 2 次提交
  10. 13 5月, 2014 1 次提交
    • H
      clk: samsung: add clock controller driver for s3c2410, s3c2440 and s3c2442 · 3f7c01ad
      Heiko Stuebner 提交于
      This driver can handle the clock controllers of the socs mentioned above,
      as they share a common clock tree with only small differences.
      
      The clock structure is built according to the manuals of the included
      SoCs and might include changes in comparison to the previous clock
      structure.
      
      As pll-rate-tables only the 12mhz variants are currently included.
      The original code was wrongly checking for 169mhz xti values [a 0 to much
      at the end], so the original 16mhz pll table would have never been
      included and its values are so obscure that I have no possibility to
      at least check their sane-ness. When using the formula from the manual
      the resulting frequency is near the table value but still slightly off.
      Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
      Acked-by: NMike Turquette <mturquette@linaro.org>
      Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
      3f7c01ad
  11. 09 5月, 2014 1 次提交
  12. 15 4月, 2014 2 次提交
  13. 17 9月, 2013 1 次提交
  14. 06 8月, 2013 1 次提交
  15. 19 6月, 2013 2 次提交
  16. 25 3月, 2013 5 次提交