This patch adds clock driver of Exynos4415 SoC based on Cortex-A9 using
common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and generates system clocks for CPU,
busses and function clocks for individual IPs.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NSeung-Woo Kim <sw0312.kim@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>