The cavium,pci-thunder-ecam devices are exactly ECAM-based PCI root
complexes.  These root complexes (loosely referred to as ECAM units in the
hardware manuals) are used to access the Thunder on-chip devices.  They
are special in that all the BARs on devices behind these root complexes are
at fixed addresses.

Add a driver for these devices that synthesizes Enhanced Allocation (EA)
capability entries for each BAR.

Since this EA synthesis is needed for exactly two chip models, we can hard-
code some assumptions about the device topology and the layout of the
config space of specific DEVFNs in the driver.

[bhelgaas: changelog, whitespace]
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRob Herring <robh@kernel.org>

The root complexes used to access off-chip PCIe devices (called PEM units
in the hardware manuals) on some Cavium ThunderX processors require quirky
access methods for the config space of the PCIe bridge.

Add a driver to provide these config space accessor functions.  Use the
pci-host-common code to configure the PCI machinery.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Move pci_host_common_probe() and associated functions to pci-host-common.c,
where it can be shared with other drivers.  Make it public (not static)
and update Kconfig and Makefile to build it.  No functional change
intended.

[bhelgaas: split into separate patch, changelog]
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NWill Deacon <will.deacon@arm.com>

Add PCIe MSI support for both PAXB and PAXC interfaces on all iProc-based
platforms.

The iProc PCIe MSI support deploys an event queue-based implementation.
Each event queue is serviced by a GIC interrupt and can support up to 64
MSI vectors.  Host memory is allocated for the event queues, and each event
queue consists of 64 word-sized entries.  MSI data is written to the lower
16-bit of each entry, whereas the upper 16-bit of the entry is reserved for
the controller for internal processing.

Each event queue is tracked by a head pointer and tail pointer.  Head
pointer indicates the next entry in the event queue to be processed by
the driver and is updated by the driver after processing is done.
The controller uses the tail pointer as the next MSI data insertion
point.  The controller ensures MSI data is flushed to host memory before
updating the tail pointer and then triggering the interrupt.

MSI IRQ affinity is supported by evenly distributing the interrupts to each
CPU core.  MSI vector is moved from one GIC interrupt to another in order
to steer to the target CPU.

Therefore, the actual number of supported MSI vectors is:

  M * 64 / N

where M denotes the number of GIC interrupts (event queues), and N denotes
the number of CPU cores.

This iProc event queue-based MSI support should not be used with newer
platforms with integrated MSI support in the GIC (e.g., giv2m or
gicv3-its).

[bhelgaas: fold in Kconfig fixes from Arnd Bergmann <arnd@arndb.de>]
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NVikram Prakash <vikramp@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>

The PCIe driver reuses the Designware common code for host and MSI
initialization, and also programs the Qualcomm application specific
registers.

[bhelgaas: remove COMPILE_TEST Kconfig dependency]
Signed-off-by: NStanimir Varbanov <svarbanov@mm-sol.com>
Signed-off-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add Altera PCIe MSI driver.  This soft IP supports a configurable number of
vectors, which is a DTS parameter.

[bhelgaas: Kconfig depend on PCIE_ALTERA, typos, whitespace]
Signed-off-by: NLey Foon Tan <lftan@altera.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NRob Herring <robh@kernel.org>

Add PCIe host support for HiSilicon SoC Hip05, related DT binding
documentation, and maintainer update.

[bhelgaas: changelog, 32-bit only config write warning text]
Signed-off-by: NZhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: NGabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Nliudongdong <liudongdong3@huawei.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org> (DT binding)

Add the Altera PCIe host controller driver.

[bhelgaas: whitespace, fold in DT and maintainer updates, OF_PCI
dependency from Arnd]
Signed-off-by: NLey Foon Tan <lftan@altera.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: Rob Herring <robh@kernel.org> (DT binding)

APM X-Gene v1 SoC supports its own implementation of MSI, which is not
compliant to GIC V2M specification for MSI Termination.

There is a single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports.
This MSI block supports 2048 MSI termination ports coalesced into 16
physical HW IRQ lines and shared across all 5 PCIe ports.

As there are only 16 HW IRQs to serve 2048 MSI vectors, to support
set_affinity correctly for each MSI vectors, the 16 HW IRQs are statically
allocated to 8 X-Gene v1 cores (2 HW IRQs for each cores).  To steer MSI
interrupt to target CPU, MSI vector is moved around these HW IRQs lines.
With this approach, the total MSI vectors this driver supports is reduced
to 256.

[bhelgaas: squash doc, driver, maintainer update]
Signed-off-by: NDuc Dang <dhdang@apm.com>
Signed-off-by: NTanmay Inamdar <tinamdar@apm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>

This driver adds support for the PCIe 2.0 controller found on the BCMA bus.
This controller can be found on (mostly) all Broadcom BCM470X / BCM5301X
ARM SoCs.

The driver found in the Broadcom SDK does some more stuff, like setting up
some DMA memory areas, chaining MPS and MRRS to 512 and also some PHY
changes like "improving" the PCIe jitter and doing some special
initialization for the 3rd PCIe port.

This was tested on a bcm4708 board with 2 PCIe ports and wireless cards
connected to them.

PCI_DOMAINS is needed by this driver, because normally there is more than
one PCIe controller and without PCI_DOMAINS only the first controller gets
registered.  This controller gets 6 IRQs; the last one is trigged by all
IRQ events.

[bhelgaas: fix "GPLv2" MODULE_LICENSE typo]
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRafał Miłecki <zajec5@gmail.com>
Acked-by: NRay Jui <rjui@broadcom.com.com>

Add support for the Broadcom iProc PCIe controller.

pcie-iproc.c is the common core driver, and a front-end bus interface needs
to be added to support different bus interfaces.

pcie-iproc-platform.c contains the support for the platform bus interface.
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

This converts the Versatile PCI host code to a platform driver using the
commom DT parsing and setup.  The driver uses only an empty ARM
pci_sys_data struct and does not use pci_common_init_dev init function.
The old host code will be removed in a subsequent commit when Versatile is
completely converted to DT.

I've tested this on QEMU with the sym53c8xx driver in both i/o and memory
mapped modes.
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
CC: Russell King <linux@arm.linux.org.uk>
CC: Peter Maydell <peter.maydell@linaro.org>

Add support for Freescale Layerscape PCIe controller.  This driver re-uses
the Synopsis DesignWare core code.

[bhelgaas: add Kconfig dependency on CONFIG_ARM]
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Add the AppliedMicro X-Gene SOC PCIe host controller driver.  The X-Gene
PCIe controller supports up to 8 lanes and GEN3 speed.  The X-Gene SOC
supports up to 5 PCIe ports.

[bhelgaas: folded in MAINTAINERS and bindings updates]
Tested-by: NMing Lei <ming.lei@canonical.com>
Tested-by: NDann Frazier <dann.frazier@canonical.com>
Signed-off-by: NTanmay Inamdar <tinamdar@apm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com> (driver)

The Keystone PCIe controller is based on v3.65 version of the Designware
h/w.  Main differences are:

    1. No ATU support
    2. Legacy and MSI IRQ functions are implemented in application register
       space
    3. MSI interrupts are multiplexed over 8 IRQ lines to the Host side.

All of the application register space handing code is organized into
pci-keystone-dw.c and the functions are called from pci-keystone.c to
implement PCI controller driver.  Also add necessary DT documentation and
update the MAINTAINERS file for the driver.

[bhelgaas: spelling and whitespace fixes]
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Mohit Kumar <mohit.kumar@st.com>
CC: Pratyush Anand <pratyush.anand@st.com>
CC: Jingoo Han <jg1.han@samsung.com>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>

This is the driver for Xilinx AXI PCIe Host Bridge Soft IP.

[bhelgaas: minor whitespace fixes]
Signed-off-by: NSrikanth Thokala <sthokal@xilinx.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Add support for PCIe controller in DRA7xx.  This driver re-uses the
designware core code that is already present in kernel.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>

ARM based ST Microelectronics's SPEAr1310 and SPEAr1340 SOCs have onchip
designware PCIe controller. To make that usable, this patch adds a wrapper
driver based on existing designware driver.

Adds bindings for this new driver and update MAINTAINERS as well.

Cc: linux-pci@vger.kernel.org
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NPratyush Anand <pratyush.anand@st.com>
Signed-off-by: NMohit Kumar <mohit.kumar@st.com>
[viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>

Add support for a generic PCI host controller, such as a
firmware-initialised device with static windows or an emulation by
something such as kvmtool.

The controller itself has no configuration registers and has its address
spaces described entirely by the device-tree (using the bindings from
ePAPR).  Both CAM and ECAM are supported for Config Space accesses.

Add corresponding documentation for the DT binding.

[bhelgaas: currently uses the ARM-specific pci_common_init_dev() interface]
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NLiviu Dudau <liviu.dudau@arm.com>

This PCIe Host driver currently does not support MSI, so cards fall back to
INTx interrupts.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>

This adds internal PCI controller driver for R-Car Gen2 SoC.  There are
three PCI controllers available with only a single EHCI/OHCI device
built-in on each PCI bus.  This gives us three USB channels.  Channel 0 is
shared with the USBHS device, while channel 2 is shared with the USBSS.

The PCI controllers do not support I/O port space mapping, and it is not
needed here.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add support for the PCIe port present on the i.MX6 family of controllers.
These use the Synopsis Designware core tied to their own PHY.
Signed-off-by: NSean Cross <xobs@kosagi.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>

Move the PCIe driver from arch/arm/mach-tegra into the drivers/pci/host
directory. The motivation is to collect various host controller drivers
in the same location in order to facilitate refactoring.

The Tegra PCIe driver has been largely rewritten, both in order to turn
it into a proper platform driver and to add MSI (based on code by
Krishna Kishore <kthota@nvidia.com>) as well as device tree support.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
[swarren, split DT changes into a separate patch in another branch]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys Designware part;
other parts are Exynos specific.

Also, the Synopsys Designware part can be shared with other
platforms; thus, it can be split two parts such as Synopsys
Designware part and Exynos specific part.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>

Exynos5440 has a PCIe controller which can be used as Root Complex.
This driver supports a PCIe controller as Root Complex mode.
Signed-off-by: NSurendranath Gurivireddy Balla <suren.reddy@samsung.com>
Signed-off-by: NSiva Reddy Kallam <siva.kallam@samsung.com>
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.

The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.

Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.

In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>