This patch adds a driver for the MLC NAND controller of the LPC32xx SoC.

[dwmw2: 21st century pedantry]
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Via of_get_named_gpio(), wp_gpio can become -EPROBE_DEFER which now makes
probe() return -EPROBE_DEFER as well to wait until the gpio controller is
probed before trying to probe lpc32xx_slc again.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This patch makes the lpc32xx_slc driver use of_get_named_gpio() instead of
of_get_named_gpio_flags() whose flags are discarded anyway.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This patch supports missing wp gpio.
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>

The Programmable Multibit ECC (PMECC) controller is a programmable binary
BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller
can be used to support both SLC and MLC NAND Flash devices. It supports to
generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data.

To use PMECC in this driver, the user needs to set the address and size of
PMECC, PMECC error location controllers and ROM. And also needs to pass the
correction capability, the sector size and ROM lookup table offsets via dt.

This driver has been tested on AT91SAM9X5-EK and AT91SAM9N12-EK with JFFS2,
YAFFS2, UBIFS and mtd-utils.
Signed-off-by: NHong Xu <hong.xu@atmel.com>
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Tested-by: NRichard Genoud <richard.genoud@gmail.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Add DT support for PMECC parameters.
Signed-off-by: NHong Xu <hong.xu@atmel.com>
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The SBC8260 support was dropped back when we moved from ppc to
powerpc.  We are now also dropping the support for the EOL SBC8560,
so we can also delete this mapping support, as they were the only
users of it.

Artem: also remove the symbol from the Makefile.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Amend the comment to reflect the fact NAND_BBT_NO_OOB refers to the
location of the bad block table marker.
Signed-off-by: NShmulik Ladkani <shmulik.ladkani@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Signed-off-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This function only returns 0 or -1, so make that clear.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

These descriptors are for BBT's that don't use OOB; the "no_bbt" name doesn't
really make sense.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The commit bf4289cb removed the use of
CONFIG_MTD_NAND_ATMEL_ECC_NONE and CONFIG_MTD_NAND_ATMEL_ECC_HW but the
Kconfig file was forgotten.

This patch remove those inoperative options.
Signed-off-by: NRichard Genoud <richard.genoud@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This manufacturer ID is used under the name Spansion.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The Kconfig help on "Flash cmd/query data swapping" still mentions
LART_ENDIAN_BYTE. That option used to be relevant for setting
CONFIG_MTD_CFI_LART_BIT_SWAP. That option and macro got both removed in
v2.4.11-pre4. So, although LART endianness sounds intriguing, that part
of the help text can be removed.

And, while we're touching this choice, move the help text up one level.
Currently it's available under the "NO" option, while it's relevant for
all three options.
Signed-off-by: NPaul Bolle <pebolle@tiscali.nl>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This patch adds support for the SLC NAND controller inside the LPC32xx SoC.

[dwmw2: 21st century pedantry]
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

There is an implemention of hardware ECC write page function which may return an
error indication.
For instance, using Atmel HW PMECC to write one page into a nand flash, the hardware
engine will compute the BCH ecc code for this page. so we need read a the
status register to theck whether the ecc code is generated.
But we cannot assume the status register always can be ready, for example,
incorrect hardware configuration or hardware issue, in such case we need
write_page() to return a error code.

Since the definition of 'write_page' function in struct nand_ecc_ctrl is 'void'.
So this patch will:
  1. add return 'int' value for 'write_page' function.
  2. to be consitent, add return 'int' value for 'write_page_raw' fuctions too.
  3. add code to test the return value, and if negative, indicate an
  error happend when write page with ECC.
  4. fix the compile warning in all impacted nand flash driver.

Note: I couldn't compile-test all of these easily, as some had ARCH dependencies.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This patch moves hw ecc initialization code to one function.
Signed-off-by: NHong Xu <hong.xu@atmel.com>
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The code responsible for reading the version of the mirror bbt was
incorrectly using the descriptor of the main bbt.

Pass the mirror bbt descriptor to 'scan_read_raw' when reading the
version of the mirror bbt.
Signed-off-by: NShmulik Ladkani <shmulik.ladkani@gmail.com>
Acked-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: stable@vger.kernel.org [v2.6.37+]
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This adds snippets to the i.MX51/53 devicetrees for the nand
flash controller.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The only relevant change between i.MX51 and i.MX53 is that
a bitfield is shifted one bit to the left.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The i.MX v3 nand controller (i.MX5) needs two memory resources.
Traditionally we have the AXI resource first. For sorting in this
driver into the devicetree it feels much more natural to have the
IP resource first. This patch swaps the ordering of these two
resources.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

To make the error path simpler and to make subsequent patches
easier.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Previously the remove method was looping and removing all chips,
which is obviously not the right thing to do — left over from when
the driver was organized differently and that was the remove method for
the entire controller.  This would result in bad things happening if
you have more than one NAND chip, and remove the module.

This also fixes priv->dev to properly point to the chip's device rather than
the controller's.  Until now priv->dev was only used for error/debug prints
(and it's an improvement there), so this shouldn't break anything.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Adds JEDEC ID for the 1.8V version of WinBond w25q32.
Signed-off-by: NFederico Fuga <fuga@studiofuga.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Prepare the clock before enabling it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

According to its documentation, the NAND_NO_READRDY option is always used
when autoincrement is not supported. Autoincrement support was recently
dropped, so we can drop this options as well (defaulting to "no read ready
check").
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This option was never used and isn't currently used.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Eon's new NAND flash: EN27LN1G08.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This is a clean-up patch which removes the own pseudo-random numbers generator
from the speed- and stress-tests and makes them use the 'random32()' generator
instead.

[dwmw2: Merge later fix for negative offsets]
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

In hardware ecc mode, the flctl now writes and reads the oob data
provided by the user. Additionally the ECC is now returned in normal
page reads, not only when using the explicit NAND_CMD_READOOB command.
Signed-off-by: NBastian Hecht <hechtb@gmail.com>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

There are multiple reasons for a rewrite:
 - a race exists: when _4ECCEND is set, _4ECCFA may become true too
   meanwhile, which is lost and a non-correctable error is treated as
   correctable.
 - the ECC statistics don't get properly propagated to the base code.
 - empty pages would get marked as corrupted

The rewrite resolves the issues and I hope it gives a more explicit
code flow structure.
Signed-off-by: NBastian Hecht <hechtb@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

When we use hardware ecc, the flctl is run in so-called "sector access
mode". We can bundle 4 sector accesses when using 2KiB page sizes to read
a whole page at once and speed up things.
Signed-off-by: NBastian Hecht <hechtb@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

As the equation mtd->writesize == eccsteps * eccsize holds, we can
simplify the code. The second loop of the 1st hunk is never entered,
so we delete it.
Signed-off-by: NBastian Hecht <hechtb@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The flctl uses 10 bytes ECC data for every 512 bytes sector. This patch
makes the controller write all 40 bytes instead of 10 bytes only.
Signed-off-by: NBastian Hecht <hechtb@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The flctl hardware has changed and a new OOB layout must be adapted for
2KiB page size NAND chips when using hardware ECC.
The related bit fields ECCPOS[0-2] are gone — the bits are marked as
reserved now in the datasheet. As there are no official users of the
hardware ECC so far, they are completely removed.
Signed-off-by: NBastian Hecht <hechtb@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

When the data transfer between the controller and the NAND chip fails,
we now get notified.
Signed-off-by: NBastian Hecht <hechtb@gmail.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Add the unmapping for the error case and for the driver removal.
Signed-off-by: NBastian Hecht <hechtb@gmail.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>