The module 0 style clocks, or storage module clocks as named in the
official SDK, are almost the same as the module 0 clocks on earlier
Allwinner SoCs. The only difference is wider mux register bits.

As with earlier Allwinner SoCs, mmc module clocks are a special case
of mod0 clocks, with phase controls for 2 child clocks, output and
sample.

This patch adds support for both.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Instead of having three different clocks for the main MMC clock and the two
phase sub-clocks, which involved having three different drivers sharing the
same register, rework it to have the same single driver registering three
different clocks.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NChen-Yu Tsai <wens@csie.org>
Tested-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMike Turquette <mturquette@linaro.org>

This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate calculation.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Some clock modules on the A31 use PLL6x2 as one of their inputs.
This patch changes the PLL6 implementation for A31 to a divs clock,
i.e. clock with multiple outputs that have different dividers.
The first output will be the normal PLL6 output, and the second
will be PLL6x2.

This patch fixes the PLL6 N factor in the clock driver, and removes
any /2 dividers in the PLL6 factors clock part. The N factor counts
from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This driver does not match the hardware, which is actually compatible
to sun4i-a10-apb1-clk. Since we've switch to the correct one, drop
this driver.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The clock controller module (CCM) has several clock inputs, which
are connected to external crystal oscillators. To reflect this,
assign these fixed clocks to the CCM node directly.

This especially resolves initialization order dependencies we had
with the earlier initialization code: When resolving of the fixed
clocks failed in clk-vf610, the code created fixed clocks with a
rate of 0.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Commit 8e33f91a ("clk: shmobile: clk-mstp: change to using
clock-indices") forgot to replace all occurrences of
"renesas,clock-indices" in the driver-specific binding documentation.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

It adds the DT support for mmp2 clock subsystem.
Signed-off-by: NChao Xie <chao.xie@marvell.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

It adds the DT support for pxa910 clock subsystem.
Signed-off-by: NChao Xie <chao.xie@marvell.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

It adds the DT support for pxa168 clock subsystem.
Signed-off-by: NChao Xie <chao.xie@marvell.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Describes how to specify the parents for clocks with EXSRC bits.
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: NArun Parameswaran <aparames@broadcom.com>
Tested-by: NJonathan Richardson <jonathar@broadcom.com>
Reviewed-by: NJD (Jiandong) Zheng <jdzheng@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

This commit unifies the APB1 mux with the APB1 clock, using the new
factors infrastructure.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
[wens@csie.org: Add mux mask bits]
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com>
Change-Id: I7950afa9650d15ec7ce2cca89bb2a1e38586d4a5
Signed-off-by: NScott Wood <scottwood@freescale.com>

Add clock support for the RTC block in Exynos7.
Signed-off-by: NNaveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.
Signed-off-by: NNaveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.
Signed-off-by: NNaveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: NThomas Abraham <thomas.ab@samsung.com>
Tested-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch adds DT binding documentation for Exynos4415 SoC system
clock controllers.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Reviewed-by: NArun Parameswaran <aparames@broadcom.com>
Tested-by: NJonathan Richardson <jonathar@broadcom.com>
Reviewed-by: NJD (Jiandong) Zheng <jdzheng@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NScott Branden <sbranden@broadcom.com>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

This adds the gate clocks for AHB/APB busses on the A80 SoC.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A80 SoC has 12 PLL clocks, 3 AHB clocks, 2 APB clocks, and a
new "GT" bus, which I assume is some kind of data bus connecting
the processor cores, memory and various busses. Also there is a
bus clock for a ARM CCI400 module.

As far as I can tell, the GT bus and CCI400 bus clock must be
protected.

This patch adds driver support for peripheral related PLLs and
bus clocks on the A80. The GT and CCI400 clocks are added as well
as these 2 along with the PLLs they are clocked from must not be
disabled.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Document the device-tree binding of Marvell PXA based SoCs.
PXA clocks are mostly fixed rate and fixed ratio clocks derived from an
external oscillator, and gated by a register set (CKEN or CKEN*).
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The MBUS clock on sun8i is slightly different from the old mod0 clocks.
The divider is 3 bits wider, while also needing a divider table for the
higher 4 values, which all set the same divider.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The MMC clock we thought we had until now are actually not one but three
different clocks.

The main one is unchanged, and will have three outputs:
  - The clock fed into the MMC
  - a sample and output clocks, to deal with when should we output/sample data
    to/from the MMC bus

The phase control we had are actually controlling the two latter clocks, but
the main MMC one is unchanged.

We can adjust the phase with a 3 bits value, from 0 to 7, 0 meaning a 180 phase
shift, and the other values being the number of periods from the MMC parent
clock to outphase the clock of.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

Even though the mbus clock is a regular module clock, given its nature, it
needs to be enabled all the time.

Introduce a new compatible, to differentiate it from the other module clocks.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

The added gpio-gate-clock is a basic clock that can be enabled and
disabled trough a gpio output. The DT binding document for the clock
is also added. For EPROBE_DEFER handling the registering of the clock
has to be delayed until of_clk_get() call time.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Document the new compatible for clock in DMC (Dynamic Memory
Controller) domain of Exynos3250 Clock Management Unit (CMU).
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>

Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix
interconnect (h32mx) has a clock that can be setup at the half of the h64mx
clock (which is mck). The h32mx clock can not exceed 90 MHz.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add Device Tree binding documentation for the clocks
outputs in the Maxim 77802 Power Management IC.
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Like most clock drivers, the Maxim 77686 PMIC clock binding
follows the convention that the "#clock-cells" property is
used to specify the number of cells in a clock provider.

But the binding document is not clear enough that it shall
be set to 1 since the PMIC support multiple clocks outputs.

Also, explain that the clocks identifiers are defined in a
header file that can be included by Device Tree source with
client nodes to avoid using magic numbers.

Finally, add "clock-output-names" as an optional property
since now is supported by the clock driver.
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Correct spelling typo in treewide.
Signed-off-by: NHayato Suzuki <hytszk@gmail.com>
Acked-by: NRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

This patch adds DT binding documentation for the Cirrus Logic
CLPS711X-based CPUs clock subsystem.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

A Flexgen structure is composed by:
- a clock cross bar (represented by a mux element)
- a pre and final dividers (represented by a divider and gate elements)
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Naming convention was changed in dts file but the
clock binding documentation hasn't been updated.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds helper functions to configure clock parents and rates
as specified through 'assigned-clock-parents', 'assigned-clock-rates'
DT properties for a clock provider or clock consumer device.
The helpers are now being called by the bus code for the platform, I2C
and SPI busses, before the driver probing and also in the clock core
after registration of a clock provider.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds a driver for clock controller being a part of Audio
Subsystem present on S5PV210 and compatible SoCs. It is used to provide
clocks for other IP blocks of this subsystem.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>