Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

LPC32xx SoC has a 128 bits unique id that can be used as a system
serial number, if none has been provided by atags or dt.
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

This patch adjusts the LPC32xx platform support to the new pl08x DMA interface,
fixing the compile error resulting from changed pl08x structures.
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Remove SPI0_CS, MMC_CD and MMC_WP gpios as they moved to devicetree.
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

USB and I2C initialization can be removed safely from the board specific
phy3250.c, now that initialization moved to the generalized clock.c.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Tested-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

Move most of usb clock initialization from lpc32xx_udc and ohci-nxp to
clock.c. Also adds ohci clocks and otg clocks.
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

This patch fixes a bug, (wrongfully) resetting the value of
LPC32XX_CLKPWR_MS_CTRL back to its initial contents (after careful setup). This
was discovered only with a board/bootloader combination (EA3250) where the
contents of the respective register wasn't already at the correct value on
Linux boot.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This patch makes sure certain MMC bits are cleared as they should for
initialization.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This patch moves MMC/SD controller initialization from the board specific file
phy3250.c to clock.c.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

Move i2s1 dma init to be done when it's clock is enabled.
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Move the irda configuration to serial.c where other special cases are
handled
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Remove SSP0, CLCD and DMA clocks that are already migrated to
the clock framework.
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Leave chipselect and spi devices binding to the devicetree
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

The lpc32xx spi0 chipselect will be requested directly from the
pl022 driver
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Add ea3250.dtb and phy3250.dtb to the list of dtbs to be built
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

ARCH_NR_GPIOS was defined statically to include exactly all SoC specific GPIOs.
Now if additional GPIOs need to be added dynamically, e.g. via DT, none are
available. Removing the mach specific setting, leaving ARCH_NR_GPIOS to the
default of 256 (currently in include/asm-generic/gpio.h).
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This patch switches from static serial driver initialization to devicetree
configuration. This way, the Standard UARTs of the LPC32xx SoC can be enabled
individually via DT.

E.g., instead of Kconfig configuration, the phy3250.dts activates
UARTs 3 and 5.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Tested-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This patch adds support for the MMC controller of the LPC32xx SoC to the
platform initialization via the pl08x primecell driver. Lacking more complete
DT support, done via DT auxdata.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

The clock.c file needs to be changed to match the automatic device name to its
clock.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NRob Herring <rob.herring@calxeda.com>

This patch adds DMA channel configuration to the LPC32xx platform file.  The
configured DMA signalling is generic for LPC32xx SoC and is not board specific.
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Since we now support two MTD NAND controllers (MLC and SLC) for LPC32xx via DT,
we don't initialize the SLC controller statically anymore, but do it via the
clock setup (see previous patch).
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Tested-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This patch adds clock initialization for the MLC NAND controller of the LPC32xx
SoC and adjusts it for the SLC controller.
Signed-off-by: NRoland Stigge <stigge@antcom.de>

This patch adds device tree support for gpio-lpc32xx.c.

To register the various GPIO banks as (struct) gpio_chips via the same DT
gpio-controller, we utilize the adjusted of_xlate API to manipulate the
actually used struct gpio_chip.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The platforms using i2c-pnx.c both defined a duplicated i2c.h (used nowhere
else). This patch removes those and integrates the contents into the driver
itself.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

As a precondition for device tree conversion, the platforms using i2c-pnx.c are
converted to using mem and irq resources instead of platform data.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

This patch moves non-boardspecific LPC32xx code to common.c
Signed-off-by: NRoland Stigge <stigge@antcom.de>

This patch does the actual device tree switch for the LPC32xx SoC.
Signed-off-by: NRoland Stigge <stigge@antcom.de>

This patch removes two Kconfig options now unused (the network driver is
configured via DT now).
Signed-off-by: NRoland Stigge <stigge@antcom.de>

This patch adjusts the clocks of the LPC32xx SoC to be picked up correctly by
the respective drivers.

* AMBA dmaengine
* watchdog
* I2C
* TSC
* MMC
* Ethernet
* ADC
* USB Device

(All except the pl08xdmac AMBA dmaengine via DT generated device name)
Signed-off-by: NRoland Stigge <stigge@antcom.de>

This patch makes use of the default macro CLKDEV_INIT() for clock registration.
Signed-off-by: NRoland Stigge <stigge@antcom.de>

The platforms using i2c-pnx.c both defined a duplicated i2c.h (used nowhere
else). This patch removes those and integrates the contents into the driver
itself.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

As a precondition for device tree conversion, the platforms using i2c-pnx.c are
converted to using mem and irq resources instead of platform data.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

During a complex merge for v3.4, one line of the commit
c20b909b ("ARM: LPC32xx: Ethernet support") was
reverted wrongly ("lpc-eth.0" -> "lpc-net.0") while the other conflicts were
merged correctly. This patch re-applies the clock name "lpc-eth.0".
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch adds ethernet support to the LPC32xx ARM architecture. The actual
driver in drivers/net is contained in a separate patch.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NArnd Bergmann <arnd@arndb.de>

This patch adds OHCI support to the LPC32xx ARM platform. Besides the trivial
addition of platform "usb-ohci" support, fixes for the USB PLL have been added
to arch/arm/mach-lpc32xx/clock.c, ported from NXP's lpclinux.com.

(This is the mach-lpc32xx specific part, the USB subsystem specific changes are
in a separate patch for the USB maintainers.)
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Now that many platforms don't need mach/io.h, remove the unused ones.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NJamie Iles <jamie@jamieiles.com>
Acked-by: NPawel Moll <pawel.moll@arm.com>
Acked-by: NNicolas Pitre <nico@linaro.org>

Some of the LPC32XX_* macros were typed ("LCP32XX_*"), which is fixed by this
patch. (Besides another LCP doc typo.)

Further, the LPC32XX_GPIO_P2_MUX_SET/CLR/STATE macros were missing.
Signed-off-by: NRoland Stigge <stigge@antcom.de>

This patch fixes a wrong loop limit on UART init.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Cc: stable@vger.kernel.org

This patch fixes a HW bug by flushing RX FIFOs of the UARTs on init. It was
ported from NXP's git.lpclinux.com tree.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Cc: stable@vger.kernel.org

This patch fixes the wakeup disable function by clearing latched events.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Cc: stable@vger.kernel.org