提交 · 4526e7b857076ba613cc7199fc7fd17d60e86ede · openanolis / cloud-kernel

21 1月, 2015 3 次提交

clk: Skip fetching index for single parent clocks · 4526e7b8

由 Stephen Boyd 提交于 12月 22, 2014

We don't need to fetch the parent index for clocks if they only
have one parent. Doing this also avoid an unnecessary allocation
for the parent cache.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

4526e7b8

clk-gate: fix bit # check in clk_register_gate() · 2e9dcdae

由 Sergei Shtylyov 提交于 12月 24, 2014

In case CLK_GATE_HIWORD_MASK flag is passed to clk_register_gate(), the bit #
should be no higher than 15, however the corresponding check is obviously off-
by-one.

Fixes: 04577994 ("clk: gate: add CLK_GATE_HIWORD_MASK")
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

2e9dcdae

clk: ppc-corenet: fix section mismatch warning · 66619ac5

由 Kevin Hao 提交于 12月 03, 2014

In order to fix the following section mismatch warning:
  WARNING: drivers/clk/built-in.o(.data+0xe4): Section mismatch in reference from the variable ppc_corenet_clk_driver to the function .init.text:ppc_corenet_clk_probe()
  The variable ppc_corenet_clk_driver references
  the function __init ppc_corenet_clk_probe()
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

  WARNING: drivers/clk/built-in.o(.data+0x10c): Section mismatch in reference from the variable ppc_corenet_clk_driver to the variable .init.rodata:ppc_clk_ids
  The variable ppc_corenet_clk_driver references
  the variable __initconst ppc_clk_ids
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

We can't just add the __init annotation to ppc_corenet_clk_driver or
remove the __init from ppc_corenet_clk_probe() and ppc_clk_ids.
So choose to use CLK_OF_DECLARE to scan and init the clock devices.
Signed-off-by: NKevin Hao <haokexin@gmail.com>
Acked-by: NScott Wood <scottwood@freescale.com>
Acked-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

66619ac5

18 1月, 2015 6 次提交

clk: exynos-audss: Fix memory leak on driver unbind or probe failure · 27c76c43

由 Krzysztof Kozlowski 提交于 1月 05, 2015

The memory allocated by basic clock divider/gate/mux (struct clk_gate,
clk_divider and clk_mux) was leaking. During driver unbind or probe
failure the driver only unregistered the clocks.

Use clk_unregister_{gate,divider,mux} to release all resources.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

27c76c43

clk: Add clk_unregister_{divider, gate, mux} to close memory leak · 4e3c021f

由 Krzysztof Kozlowski 提交于 1月 05, 2015

The common clk_register_{divider,gate,mux} functions allocated memory
for internal data which wasn't freed anywhere. Drivers using these
helpers could only unregister clocks but the memory would still leak.

Add corresponding unregister functions which will release all resources.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

4e3c021f

clk: TI CDCE706 clock synthesizer driver · 0c7665c3

由 Max Filippov 提交于 1月 12, 2015

The driver allows using CDCE706 in its default configuration recorded in
EEPROM and adjusting of synthesized clocks by consumers.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

0c7665c3

clk: fix possible null pointer dereference · c7662fc5

由 Stanimir Varbanov 提交于 1月 05, 2015

The commit 646cafc6 (clk: Change clk_ops->determine_rate to
return a clk_hw as the best parent) opens a possibility for
null pointer dereference, fix this.
Signed-off-by: NStanimir Varbanov <svarbanov@mm-sol.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

c7662fc5

Revert "clk: ppc-corenet: Fix Section mismatch warning" · 176a107b

由 Kevin Hao 提交于 12月 03, 2014

This reverts commit da788acb.

That commit tried to fix the section mismatch warning by moving the
ppc_corenet_clk_driver struct to init section. This is definitely wrong
because the kernel would free the memories occupied by this struct
after boot while this driver is still registered in the driver core.
The kernel would panic when accessing this driver struct.

Cc: stable@vger.kernel.org # 3.17
Signed-off-by: NKevin Hao <haokexin@gmail.com>
Acked-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

176a107b

clk: rockchip: fix deadlock possibility in cpuclk · a5e1baf7

由 Heiko Stübner 提交于 1月 16, 2015

Lockdep reported a possible deadlock between the cpuclk lock and for example
the i2c driver.

       CPU0                    CPU1
       ----                    ----
  lock(clk_lock);
                               local_irq_disable();
                               lock(&(&i2c->lock)->rlock);
                               lock(clk_lock);
  <Interrupt>
    lock(&(&i2c->lock)->rlock);

 *** DEADLOCK ***

The generic clock-types of the core ccf already use spin_lock_irqsave when
touching clock registers, so do the same for the cpuclk.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: removed initialization of "flags"]

a5e1baf7

14 1月, 2015 2 次提交

clk: berlin: bg2q: remove non-exist "smemc" gate clock · b71e8ecd

由 Jisheng Zhang 提交于 12月 31, 2014

The "smemc" clock is removed on BG2Q SoCs. In fact, bit19 of clkenable
register is for nfc. Current code use bit19 for non-exist "smemc"
incorrectly, this prevents eMMC from working due to the sdhci's
"core" clk is still gated.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Cc: stable@vger.kernel.org # 3.16+
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

b71e8ecd

clk: at91: keep slow clk enabled to prevent system hang · dca1a4b5

由 Boris Brezillon 提交于 1月 13, 2015

All slow clk users are not properly claiming it (get + prepare + enable)
before using it.
If all users properly claiming this clock release it, the clock is
disabled, but faulty users still depends on it, and the system hangs.

This fix prevents the slow clock from being disabled, and should solve the
hanging issue, but offending drivers should be patched to properly claim
this clock.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: NBo Shen <voice.shen@atmel.com>
Cc: stable@vger.kernel.org
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

dca1a4b5

29 12月, 2014 2 次提交

clk: rockchip: fix rk3288 cpuclk core dividers · 9880d427

由 Heiko Stuebner 提交于 12月 18, 2014

Commit 0e5bdb3f (clk: rockchip: switch to using the new cpuclk type
for armclk) didn't take into account that the divider used on rk3288
are of the (n+1) type.

The rk3066 and rk3188 socs use more complex divider types making it
necessary for the list-elements to be the real register-values to write.

Therefore reduce divider values in the table accordingly so that they
really are the values that should be written to the registers and match
the dividers actually specified for the rk3288.
Reported-by: NSonny Rao <sonnyrao@chromium.org>
Fixes: 0e5bdb3f ("clk: rockchip: switch to using the new cpuclk type for armclk")
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Cc: stable@vger.kernel.org

9880d427

clk: rockchip: fix rk3066 pll lock bit location · 12551f02

由 Heiko Stuebner 提交于 12月 24, 2014

The bit locations indicating the locking status of the plls on rk3066 are
shifted by one to the right when compared to the rk3188, bits [7:4] instead
of [8:5] on the rk3188, thus indicating the locking state of the wrong pll
or a completely different information in case of the gpll.

The recently introduced pll init code exposed that problem on some rk3066
boards when it tried to bring the boot-pll value in line with the value
from the rate table.

Fix this by defining separate pll definitions for rk3066 with the correct
locking indices.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Fixes: 2c14736c ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks")
Tested-by: NFUKAUMI Naoki <naobsd@gmail.com>
Cc: stable@vger.kernel.org

12551f02

21 12月, 2014 2 次提交

clk: rockchip: Fix clock gate for rk3188 hclk_emem_peri · 5039d16a

由 Romain Perier 提交于 12月 12, 2014

Do not disable clock gate "hclk_emem_peri", otherwise EMAC clocks no longer work
and it breaks ethernet on RK3066 and RK3188. It fixes a regression introduced by
commit 78eaf609 ("clk: rockchip: disable unused clocks").
Signed-off-by: NRomain Perier <romain.perier@gmail.com>
Fixes: 78eaf609 ("clk: rockchip: disable unused clocks")
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

5039d16a

clk: rockchip: add CLK_IGNORE_UNUSED flag to fix rk3066/rk3188 USB Host · caa6934a

由 Julien CHAUVEAU 提交于 12月 12, 2014

This patch adds CLK_IGNORE_UNUSED flag to hclk_usb_peri, hclk_usbotg0
and hclk_usbotg1 because these clocks must remain enabled to use the
USB controllers in host mode.

This fixes a regression introduced by commit 78eaf609
("clk: rockchip: disable unused clocks").
Signed-off-by: NJulien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Fixes: 78eaf609 ("clk: rockchip: disable unused clocks")
Reviewed-by: NRomain Perier <romain.perier@gmail.com>
Tested-by: NRomain Perier <romain.perier@gmail.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

caa6934a

17 12月, 2014 1 次提交

clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated · f1e9203e

由 Krzysztof Kozlowski 提交于 12月 05, 2014

Audio subsystem clocks are located in separate block. On Exynos 5420 if
clock for this block (from main clock domain) 'mau_epll' is gated then
any read or write to audss registers will block.

This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
after introducing runtime PM to pl330 DMA driver. After that commit the
'mau_epll' was gated, because the "amba" clock was disabled and there
were no more users of mau_epll.

The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because
   samsung_pinmux_setup() tried to access memory from audss block which was
   gated.

Add a workaround for this by enabling the 'mau_epll' clock in probe.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

f1e9203e

16 12月, 2014 1 次提交

clk: Really fix deadlock with mmap_sem · 89f7e9de

由 Stephen Boyd 提交于 12月 12, 2014

Commit 6314b679 (clk: Don't hold prepare_lock across debugfs
creation, 2014-09-04) forgot to update one place where we hold
the prepare_lock while creating debugfs directories. This means
we still have the chance of a deadlock that the commit was trying
to fix. Actually fix it by moving the debugfs creation outside
the prepare_lock.

Cc: <stable@vger.kernel.org> # 3.18
Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Fixes: 6314b679 "clk: Don't hold prepare_lock across debugfs creation"
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: removed lockdep_assert]

89f7e9de

12 12月, 2014 1 次提交

clk: mmp: fix sparse non static symbol warning · 74fc23aa

由 Wei Yongjun 提交于 12月 09, 2014

Fixes the following sparse warnings:

drivers/clk/mmp/clk-frac.c:113:6: warning:
 symbol 'clk_factor_init' was not declared. Should it be static?
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

74fc23aa

04 12月, 2014 5 次提交

clk: Change clk_ops->determine_rate to return a clk_hw as the best parent · 646cafc6