Add gpio support to pinctrl driver for Actions Semi S900 SoC.
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add gpio bindings for Actions Semi S900 SoC.
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds a pair of context save/restore functions to save/restore the
state of a set of pinctrl registers. The context is lost during rtc only
suspend with ddr in self-refresh on am43xx. Currently the save/restore
is being done unconditionally. This will be optimized later with a
pdata-quirk function which will allow is to save/restore only when doing
the rtc only mode with ddr in self refresh.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The data pin 0-7 of the NAND controller are actually missing from
the nand pinctrl group, so we fix it here.

Fixes: 0f15f500 ("pinctrl: meson: Add GXL pinctrl definitions")
Reported-by: NLiang Yang <liang.yang@amlogic.com>
Signed-off-by: NYixun Lan <yixun.lan@amlogic.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The data pin 0-7 of the NAND controller are actually missing from
the nand pinctrl group, so we fix it here.

Fixes: cd1e3b01 ("pinctrl: amlogic: gxbb: add nand pins")
Reported-by: NLiang Yang <liang.yang@amlogic.com>
Signed-off-by: NYixun Lan <yixun.lan@amlogic.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

I was debugging some gpio issues and I thought that the output of gpio
debugfs was telling me the high or low level of the gpios with a '1' or
a '0'. We saw a line like this though:

 gpio93  : in 4 2mA pull down

and I started to think that there may be a gas leak in the building
because '4' doesn't mean high or low, and other pins said '0' or '1'. It
turns out, '4' is the function selection for the pinmux of the gpio and
not the value on the pin. Reading code helps decipher what debugfs is
actually saying.

Add support to read the input or output pin depending on how the pin is
configured so we can easily see the high or low value of the pin in
debugfs. Now the output looks like

 gpio93  : in   low  func4 2mA pull down

which clearly shows that the pin is an input, low, with function 4 and a
2mA drive strength plus a pull down.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The "dev" function is selected with the value 0x4 not 0x01.

Fixes: commit d7ae8f8d ("pinctrl: mvebu: pinctrl driver for 98DX3236 SoC")
Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

DebugFS strings about pin pull status for no_keeper SoC are wrong

Fix this by adding a different string array for no_keeper SoC
Signed-off-by: NClément Péron <peron.clem@gmail.com>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks.
Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so
that main clk-controller driver could get an actual parent clock for the
CDEV1/2 clocks.
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
Reviewed-by: NMarcel Ziswiler <marcel@ziswiler.com>
Tested-by: NMarcel Ziswiler <marcel@ziswiler.com>
Tested-by: NMarc Dietrich <marvin24@gmx.de>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs,
which controls the PL and PM pin banks.

Add support for it.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The new helper returns index of the matching string in an array.
We are going to use it here.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Properties to set initial value of pin output buffer.
This can be useful for configure hardware in overlay files, and in early
boot for checking it states in QA sanity tests.
Signed-off-by: NMatheus Castello <matheus@castello.eng.br>
Reviewed-by: NEric Anholt <eric@anholt.net>
Acked-by: NStefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

To keep driver up to date we add generic pinctrl binding support, which
covers the features used in this driver and has additional node properties
that this SoC has compatibility, so enabling future implementations of
these properties without the need to create new node properties in the
device trees.

The logic of this change maintain the old brcm legacy binding support in
order to keep the ABI stable.
Signed-off-by: NMatheus Castello <matheus@castello.eng.br>
Reviewed-by: NEric Anholt <eric@anholt.net>
Acked-by: NStefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add PFC support for the R8A77470 SoC including pin groups for
some on-chip devices such as SCIF and MMC.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Reviewed-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds pins, groups and functions for parallel RGB output
signals from DU. The HDMI and TCON pins are added to separate groups.

Based on a similar patch of the R8A7796 PFC driver by Niklas Söderlund
<niklas.soderlund+renesas@ragnatech.se>.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
[Kieran: Rebase on top of tree]
Signed-off-by: NKieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

GPL-2. is not a valid SPDX identifier. Make it GPL-2.0

Fixes: 490e687e ("pinctrl: sh-pfc: Initial R-Car M3-N support")
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Jacopo Mondi <jacopo+renesas@jmondi.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

I've included the pin I/O voltage control into the R8A77970 PFC driver but
it was incomplete because:
- SH_PFC_PIN_CFG_IO_VOLTAGE pin flags weren't set properly;
- sh_pfc_soc_info::ioctrl_regs wasn't set at all...

Fixes: b92ac66a ("pinctrl: sh-pfc: Add R8A77970 PFC support")
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the pin I/O voltage level control support to the R8A77980 PFC driver.

Loosely based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: NVladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Document PFC support for the R8A77470 SoC.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Reviewed-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to
R8A77965 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds MSIOF{0,1,2,3} pins, groups and functions to the
R8A77965 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Correct MSIOF3 SS2_E comment]
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

For a constant format without additional arguments, use seq_puts()
instead of seq_printf(). Also, it fixes the following checkpatch
warning.

WARNING: Prefer seq_puts to seq_printf
+		seq_printf(s, "N/A");

WARNING: Prefer seq_puts to seq_printf
+	seq_printf(s, "\n");

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The current code comments of PIN_FUNC_ID actually is not true for
SHARE_MUX_CONF_REG case which should be a 4 u32 PIN_FUNC_ID.
Fix the comments and re-org it a bit for better extendibility
as we may add a different size for SCU based PIN_FUNC_ID later.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The unsigned integer nfuncs is being error checked with a value less
or equal to zero; this is always false if of_get_child_count returns a
-ve for an error condition since nfuncs is not signed. Fix this by
making variables nfuncs and i signed integers.

Detected with Coccinelle:
drivers/pinctrl/freescale/pinctrl-imx.c:620:6-12: WARNING: Unsigned
expression compared with zero: nfuncs <= 0

Cc: Linus Walleij <linus.walleij@linaro.org>
Reported-by: NColin Ian King <colin.king@canonical.com>
Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The MPEG2-TS input/output core both accepts serial TS and parallel TS.

The serial TS interface uses following pins:
  hscin0_s : HS0DOUT[0-3]
  hscin1_s : HS0DOUT[4-7]
  hscin2_s : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN0
  hscout0_s: HS0DOUT[0-3]
  hscout1_s: HS0DOUT[4-7]

And the parallel TS interface uses following pins:
  hscin0_p : HS0BCLKIN, HS0SYNCIN, HS0VALIN, HS0DIN[0-7]
  hscin1_p : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN[0-7]
  hscout0_p: HS0BCLKOUT, HS0SYNCOUT, HS0VALOUT, HS0DOUT[0-7]
Signed-off-by: NKatsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The MPEG2-TS input/output core both accepts serial TS and parallel TS.

The serial TS interface uses following pins:
  hscin0_s : HS0DOUT[0-3]
  hscin1_s : HS0DOUT[4-7]
  hscin2_s : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN0
  hscin3_s : HS1DIN[2-5]
  hscout0_s: HS0DOUT[0-3]
  hscout1_s: HS0DOUT[4-7]

And the parallel TS interface uses following pins:
  hscin0_p : HS0BCLKIN, HS0SYNCIN, HS0VALIN, HS0DIN[0-7]
  hscin1_p : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN[0-7]
  hscout0_p: HS0BCLKOUT, HS0SYNCOUT, HS0VALOUT, HS0DOUT[0-7]
Signed-off-by: NKatsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

1. Fix Kconfig dependency for Actions Semi S900 pinctrl driver which
generates below warning in x86:

WARNING: unmet direct dependencies detected for PINCTRL_OWL
  Depends on [n]: PINCTRL [=y] && (ARCH_ACTIONS || COMPILE_TEST [=n]) && OF [=n]
  Selected by [y]:
  - PINCTRL_S900 [=y] && PINCTRL [=y]

2. Add help text for OWL pinctrl driver
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reported-by: NRandy Dunlap <rdunlap@infradead.org>
Tested-by: NRandy Dunlap <rdunlap@infradead.org>
Acked-by: NRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

There is a missing break in case PIN_CONFIG_DRIVE_STRENGTH leading to
a fall-through to the PIN_CONFIG_SLEW_RATE case that performs different
checks against *arg. This looks like an unintentional missing break so
add in the break.

Detected by CoverityScan, CID#1468456, 1468459 ("Missing break in switch")

Fixes: 513d7a2f7e0f ("pinctrl: actions: Add Actions S900 pinctrl driver")
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Acked-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

s900_functions, s900_padinfo and s900_pads are local to the source and do
not need to be in global scope, so make them static.

Cleans up sparse warnings:
drivers/pinctrl/actions/pinctrl-s900.c:1445:30: warning: symbol
's900_functions' was not declared. Should it be static?
drivers/pinctrl/actions/pinctrl-s900.c:1664:20: warning: symbol
's900_padinfo' was not declared. Should it be static?
drivers/pinctrl/actions/pinctrl-s900.c:207:31: warning: symbol
's900_pads' was not declared. Should it be static?
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Acked-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the information related to the tdm pins of the A113D SoC
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

These are only available on the Meson8m2 SoC (which uses the same
DesignWare Ethernet MAC as Meson8b).
The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII
PHYs or the RGMII TX clock (as far as we know the frequency is
controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP
block).
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add Meson8m2 support to the existing Meson8 pinctrl driver. Since there
are only very few changes (Meson8m2 has an extra signal on 10 CBUS pins,
no other differences were found so far).
Add the new compatible strings for Meson8m2 to the existing Meson8
driver so we don't have to duplicate the whole driver.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Meson8m2 SoC is a variant of Meson8 with some updates from Meson8b
(such as the Gigabit capable DesignWare MAC).
It is mostly pin compatible with Meson8, only 10 (existing) CBUS pins
get an additional function (four of these are Ethernet RXD2, RXD3, TXD2
and TXD3 which are required when the board uses an RGMII PHY).
The AOBUS pins seem to be identical on Meson8 and Meson8m2.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Fulfill the pinmux macros for MT7623
Signed-off-by: NRyder Lee <ryder.lee@mediatek.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The pinctrl-mcp23s08 driver doesn't provide a specific gpiospec
of_xlate() function, causing the gpiolib-of's of_gpio_simple_xlate()
function to be used instead, which takes the gpiospec's second cell as
the flags specifier according to 'include/dt-bindings/gpio/gpio.h'.

The pinctrl-mcp23s08 bindings document was mentioning that the flags
were unused, which is not accurate because values in that second cell
are indeed used by the gpiolib-of's of_gpio_simple_xlate() for
configuring the gpio (e.g. its polarity).

This way, replace the "flags currently unused" reference in the
dt-bindings document with references to the appropriate files specifying
the possible flag values and gpiospec description.

CC: devicetree@vger.kernel.org
Signed-off-by: NRicardo Silva <rjpdasilva@gmail.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Added generic pin configuration and multiplexing support,
and should be preferred than brcm legacy one.
Signed-off-by: NMatheus Castello <matheus@castello.eng.br>
Reviewed-by: NEric Anholt <eric@anholt.net>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Newer versions of the firmware for the Qualcomm Datacenter Technologies
QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
prevent older kernels from accidentally accessing the restricted GPIOs,
we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
and introduce a new property "gpios".  This property is an array of
specific GPIOs that are accessible.  When an older kernel boots on
newer (restricted) firmware, it will fail to probe.

To implement the sparse GPIO map, we register all of the GPIOs, but
fill in the data only for available GPIOs.  This ensures that the driver
cannot accidentally access an unavailable GPIO.

The pinctrl-msm driver also scans the "gpios" property to determine
which pins are available, and ensure that only those can be registered.

Support for QCOM8001 is removed as there is no longer any firmware that
implements it.
Signed-off-by: NTimur Tabi <timur@codeaurora.org>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>