- 16 11月, 2012 17 次提交
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由 Joseph Lo 提交于
The L2 RAM is in different power domain from the CPU cluster. So the L2 content can be retained over CPU suspend/resume. To do that, we need to disable L2 after the MMU is disabled, and enable L2 before the MMU is enabled. But the L2 controller is in the same power domain with the CPU cluster. We need to restore it's settings and re-enable it after the power be resumed. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
This is a power gating idle mode. It support power gating vdd_cpu rail after all cpu cores in "powered-down" status. For Tegra30, the CPU0 can enter this state only when all secondary CPU is offline. We need to take care and make sure whole secondary CPUs were offline and checking the CPU power gate status. After that, the CPU0 can go into "powered-down" state safely. Then shut off the CPU rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Base on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
The flow controller can help CPU to go into suspend mode (powered-down state). When CPU go into powered-down state, it needs some careful settings before getting into and after leaving. The enter and exit functions do that by configuring appropriate mode for flow controller. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
Add suspend, resume and rail_off_ready API into tegra_cpu_car_ops. These functions were used for CPU powered-down state maintenance. One thing needs to notice the rail_off_ready API only availalbe for cpu_g cluster not cpu_lp cluster. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
Enable csite (debug and trace controller) clock at init to prevent it be disabled. And this also the necessary clock for CPU be brought up or resumed from a power-gating low power state. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
This supports power-gated idle on secondary CPUs for Tegra30. The secondary CPUs can go into powered-down state independently. When CPU goes into this state, it saves it's contexts and puts itself to flow controlled WFI state. After that, it will been power gated. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
The CPU suspending on Tegra means CPU power gating. We add a resume function for taking care the CPUs that resume from power gating status. This function was been hooked to the reset handler. We take care everything here before go into kernel. Be aware of that, you may see the legacy power status "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Scott Williams <scwilliams@nvidia.com> Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
The different Tegra chips may have different CPU idle states and data. Individual CPU idle driver make it more easy to maintain. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
For the naming consistency under the mach-tegra, we re-name the file of "sleep-tXX" to "sleep-tegraXX" (e.g., sleep-t30 to sleep-tegra30). Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
The Tegra CPU idle LP3 state is doing ARM WFI only. So it's same with the common ARM_CPUIDLE_WFI_STATE. Using it to replace LP3 now. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Thierry Reding 提交于
Setup the clock parents for the two display controllers and HDMI. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Thierry Reding 提交于
Add the OF_DEV_AUXDATA table entries required to associate the proper names with host1x and its children. In turn, this allows the devices to find the required clocks. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Thierry Reding 提交于
Extend the pll_d frequency table with a few entries to support common HDMI and LVDS display modes and setup the clock parents for the two display controllers and HDMI. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Thierry Reding 提交于
Add the OF_DEV_AUXDATA table entries required to associate the proper names with host1x and its children. In turn, this allows the devices to find the required clocks. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Danny Huang 提交于
This patch adds speedo-based process identification support for Tegra30. Signed-off-by: NDanny Huang <dahuang@nvidia.com> [swarren s/Tegra3/Tegra30/ in log print, s/T30/Tegra30/ in commit description] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Danny Huang 提交于
Detect CPU and core process ID by checking speedo corner tables. This can provide a more accurate process ID. Signed-off-by: NDanny Huang <dahuang@nvidia.com> [swarren s/Tegra2/Tegra20/ in log print] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Danny Huang 提交于
Change the spare fuse base from a definition to a variable. It provides flexibilty to read spare fuse on different chip. Signed-off-by: NDanny Huang <dahuang@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 15 11月, 2012 1 次提交
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由 Peter De Schrijver 提交于
This patch implements ARM linux patch 6395/1 for Tegra. See commit 1a8e41cd "ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register" for details. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> [swarren: added commit subject for referenced patch] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 14 11月, 2012 1 次提交
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由 Laxman Dewangan 提交于
Add OF_DEV_AUXDATA for sflash controller driver for Tegra20 board dt files. Set the parent clock of sflash controller to PLLP and configure clock to 20MHz. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 10 11月, 2012 1 次提交
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由 Joseph Lo 提交于
Enable the data prefetch on L2. The bit28 in aux ctrl register. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
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- 06 11月, 2012 9 次提交
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由 Laxman Dewangan 提交于
Add OF_DEV_AUXDATA for slink driver for Tegra20 and Tegra30 board dt files. Set the parent clock of slink controller to PLLP and configure clock to 100MHz. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
Moving L2 cache init to DT support. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
Adding the AHB and APB bus clock for Tegra30. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Wei Ni 提交于
Set up the wlan clock tree for Tegra20 and Tegra30. Signed-off-by: NWei Ni <wni@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Nothing outside mach-tegra uses this file, so there's no need for it to be in <mach/>. Since uncompress.h and debug-macro.S remain in include/mach, they need to include "../../irammap.h" becaue of this change. Both these usages will be removed shortly, when Tegra's DEBUG_LL implementation is updated not to pass information through IRAM. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Nothing outside mach-tegra uses this file, so there's no need for it to be in <mach/>. Since uncompress.h and debug-macro.S remain in include/mach, they need to include "../../iomap.h" becaue of this change. uncompress.h will soon be deleted in later multi-platform/single-zImage patches. debug-macro.S will need to continue to include this header using an explicit relative path, to avoid duplicating the physical->virtual address mapping that iomap.h dictates. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Remove includes of <mach/dma.h> from sound/soc; nothing from it is used. Remove include of <mach/dma.h> from mach-tegra/apbio.c; since the DMA transfers made by this file don't need flow-control with any peripheral, there's no need to set any slave ID. Once those changes are made, there are no remaining users of <mach/dma.h> so remove it. Drivers should get this information from device tree. This removal is necessary for single zImage. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
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由 Stephen Warren 提交于
We wish to empty arch/arm/mach-tegra/include/mach/ as much as possible to enable single zImage. Move tegra-ahb.h to a more central location (suggested by Arnd, OK'd by Greg KH), and actually make tegra-ahb.c include the header to ensure client and provider agree on the prototype. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
This should make it easier to delete or move <mach/*.h>; something that is useful for single-zImage. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 17 10月, 2012 3 次提交
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由 Sivaram Nair 提交于
This undoes commit 20f46658 "ARM: tegra: remove tegra_timer from tegra_list_clks" by bringing back the tegra_timer clock. tegra_timer is indeed a clock (hidden by the PERIPH_CLK macro) which should be added to the tegra_list_clks. The above commit caused tegra_init_timer() failing to get the clk reference. Signed-off-by: NSivaram Nair <sivaramn@nvidia.com> [swarren: added the reverted commit's subject to this patch description] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Sivaram Nair 提交于
The timer variable is renamed to avoid confusion and symbol name clash with the tegra_timer clock. Signed-off-by: NSivaram Nair <sivaramn@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Mark Zhang 提交于
Change the type of variable from "unsigned long" to "u64". This avoids the overflow while clock rate calculating. Signed-off-by: NMark Zhang <markz@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 14 10月, 2012 1 次提交
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由 Russell King 提交于
As suggested by Andrew Morton: This is a pet peeve of mine. Any time there's a long list of items (header file inclusions, kconfig entries, array initalisers, etc) and someone wants to add a new item, they *always* go and stick it at the end of the list. Guys, don't do this. Either put the new item into a randomly-chosen position or, probably better, alphanumerically sort the list. lets sort all our select statements alphanumerically. This commit was created by the following perl: while (<>) { while (/\\\s*$/) { $_ .= <>; } undef %selects if /^\s*config\s+/; if (/^\s+select\s+(\w+).*/) { if (defined($selects{$1})) { if ($selects{$1} eq $_) { print STDERR "Warning: removing duplicated $1 entry\n"; } else { print STDERR "Error: $1 differently selected\n". "\tOld: $selects{$1}\n". "\tNew: $_\n"; exit 1; } } $selects{$1} = $_; next; } if (%selects and (/^\s*$/ or /^\s+help/ or /^\s+---help---/ or /^endif/ or /^endchoice/)) { foreach $k (sort (keys %selects)) { print "$selects{$k}"; } undef %selects; } print; } if (%selects) { foreach $k (sort (keys %selects)) { print "$selects{$k}"; } } It found two duplicates: Warning: removing duplicated S5P_SETUP_MIPIPHY entry Warning: removing duplicated HARDIRQS_SW_RESEND entry and they are identical duplicates, hence the shrinkage in the diffstat of two lines. We have four testers reporting success of this change (Tony, Stephen, Linus and Sekhar.) Acked-by: NJason Cooper <jason@lakedaemon.net> Acked-by: NTony Lindgren <tony@atomide.com> Acked-by: NStephen Warren <swarren@nvidia.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 07 10月, 2012 2 次提交
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由 Stephen Warren 提交于
Since the complete conversion to device tree, there are no board- specific Kconfig options left, so remove the useless Kconfig entry. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Arnd Bergmann 提交于
The PL310_ERRATA_753970 and ARM_ERRATA_764369 symbols only make sense when the base features for them are enabled, so select them conditionally in Kconfig to avoid warnings like: warning: (UX500_SOC_COMMON) selects PL310_ERRATA_753970 which has unmet direct dependencies (CACHE_PL310) warning: (ARCH_TEGRA_2x_SOC && ARCH_TEGRA_3x_SOC && UX500_SOC_COMMON) selects ARM_ERRATA_764369 which has unmet direct dependencies (CPU_V7 && SMP) Signed-off-by: NArnd Bergmann <arnd@arndb.de> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NStephen Warren <swarren@nvidia.com>
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- 20 9月, 2012 3 次提交
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由 Thierry Reding 提交于
The Tamonten Evaluation Carrier is an evaluation board for the Tamonten SOM. More information is available here: http://www.avionic-design.de/en/products/nvidia-tegra-tamonten-system-en/nvidia-tegra-tamonten-evboard-en.htmlSigned-off-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Thierry Reding 提交于
The Medcom is a 16:9 15" terminal that is used for patient infotainment in hospitals. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Thierry Reding 提交于
The Plutux is a set-top box device based on the Tamonten SOM and can be connected to a display via HDMI. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 18 9月, 2012 1 次提交
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由 Stephen Warren 提交于
There's no need to place these defines into arch/arm/mach-tegra/include/. Move them into the SMMU driver to clean up mach-tegra, as a pre-requisite for single-zImage. Signed-off-by: NStephen Warren <swarren@nvidia.com> Cc: Hiroshi Doyu <hdoyu@nvidia.com> Acked-by: NHiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>
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- 17 9月, 2012 1 次提交
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由 Laxman Dewangan 提交于
Remove the support code which uses the legacy APB DMA driver for accessing the apbio register. The driver will use the dmaengine based APB DMA driver for accessing apbio register. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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