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  1. 25 1月, 2008 1 次提交
    • D
      [POWERPC] Enable RTC for Ebony and Walnut (v2) · 22258fa4
      由 David Gibson 提交于 
      This patch extends the Ebony and Walnut platform code to instantiate
the existing ds1742 RTC class driver for the DS1743 RTC/NVRAM chip
found on both those boards.  The patch uses a helper function to scan
the device tree and instantiate the appropriate platform_device based
on it, so it should be easy to extend for other boards which have mmio
mapped RTC chips.

Along with this, the device tree binding for the ds1743 chips is
tweaked, based on the existing DS1385 OF binding found at:
	http://playground.sun.com/1275/proposals/Closed/Remanded/Accepted/346-it.txt
Although that document covers the NVRAM portion of the chip, whereas
here we're interested in the RTC portion, so it's not entirely clear
if that's a good model.

This implements only RTC class driver support - that is /dev/rtc0, not
/dev/rtc, and the low-level get/set time callbacks remain
unimplemented.  That means in order to get at the clock you will
either need a modified version of hwclock which will look at
/dev/rtc0, or you'll need to configure udev to symlink rtc0 to rtc.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      22258fa4
  3. 24 1月, 2008 17 次提交
  5. 19 1月, 2008 4 次提交
  7. 17 1月, 2008 8 次提交
  9. 16 1月, 2008 1 次提交
  11. 15 1月, 2008 1 次提交
    • P
      [POWERPC] Fix boot failure on POWER6 · dfbe0d3b
      由 Paul Mackerras 提交于 
      Commit 473980a9 added a call to clear
the SLB shadow buffer before registering it.  Unfortunately this means
that we clear out the entries that slb_initialize has previously set in
there.  On POWER6, the hypervisor uses the SLB shadow buffer when doing
partition switches, and that means that after the next partition switch,
each non-boot CPU has no SLB entries to map the kernel text and data,
which causes it to crash.

This fixes it by reverting most of 473980a9 and instead clearing the
3rd entry explicitly in slb_initialize.  This fixes the problem that
473980a9 was trying to solve, but without breaking POWER6.
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      dfbe0d3b
  13. 11 1月, 2008 1 次提交
  15. 09 1月, 2008 1 次提交
  17. 03 1月, 2008 3 次提交
  19. 02 1月, 2008 1 次提交
  21. 28 12月, 2007 2 次提交
    • O
      [POWERPC] pasemi: Distribute interrupts evenly across cpus · d87bf3be
      由 Olof Johansson 提交于 
      By default the OpenPIC on PWRficient will bias to one core (since that
will improve changes of the other core being able to stay idle/powered
down). However, this conflicts with most irq load balancing schemes,
since setting an interrupt to be delivered to either core doesn't really
result in the load being shared. It also doesn't work well with the
soft irq disable feature of PPC, since EE will stay on until the first
interrupt is taken while soft disabled.

Set the gconf0 config bit that enables even distribution of interrupts
among the two cores.
Signed-off-by: NOlof Johansson <olof@lixom.net>
      d87bf3be
    • O
      [POWERPC] pasemi: Implement NMI support · f365355e
      由 Olof Johansson 提交于 
      Some PWRficient-based boards have a NMI button that's wired up to a GPIO
as interrupt source. By configuring the openpic accordingly, these get
delivered as a machine check with high priority, instead of as an external
interrupt.

The device tree contains a property "nmi-source" in the openpic node
for these systems, and it's the (hwirq) source for the input.

Also, for these interrupts, the IACK is read from another register than
the regular (MCACK instead), but they are EOI'd as usual. So implement
said function for the mpic driver.

Finally, move a couple of external function defines to include/ instead
of local under sysdev. Being able to mask/unmask and eoi directly saves
us from setting up a dummy irq handler that will never be called.
Signed-off-by: NOlof Johansson <olof@lixom.net>
      f365355e