1. 08 11月, 2014 1 次提交
  2. 26 9月, 2014 1 次提交
  3. 20 3月, 2014 1 次提交
    • S
      arm, hw-breakpoint: Fix CPU hotplug callback registration · c5929bd3
      Srivatsa S. Bhat 提交于
      Subsystems that want to register CPU hotplug callbacks, as well as perform
      initialization for the CPUs that are already online, often do it as shown
      below:
      
      	get_online_cpus();
      
      	for_each_online_cpu(cpu)
      		init_cpu(cpu);
      
      	register_cpu_notifier(&foobar_cpu_notifier);
      
      	put_online_cpus();
      
      This is wrong, since it is prone to ABBA deadlocks involving the
      cpu_add_remove_lock and the cpu_hotplug.lock (when running concurrently
      with CPU hotplug operations).
      
      Instead, the correct and race-free way of performing the callback
      registration is:
      
      	cpu_notifier_register_begin();
      
      	for_each_online_cpu(cpu)
      		init_cpu(cpu);
      
      	/* Note the use of the double underscored version of the API */
      	__register_cpu_notifier(&foobar_cpu_notifier);
      
      	cpu_notifier_register_done();
      
      Fix the hw-breakpoint code in arm by using this latter form of callback
      registration.
      
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Ingo Molnar <mingo@kernel.org>
      Acked-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NSrivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      c5929bd3
  4. 10 2月, 2014 1 次提交
  5. 29 10月, 2013 1 次提交
  6. 15 7月, 2013 1 次提交
    • P
      arm: delete __cpuinit/__CPUINIT usage from all ARM users · 8bd26e3a
      Paul Gortmaker 提交于
      The __cpuinit type of throwaway sections might have made sense
      some time ago when RAM was more constrained, but now the savings
      do not offset the cost and complications.  For example, the fix in
      commit 5e427ec2 ("x86: Fix bit corruption at CPU resume time")
      is a good example of the nasty type of bugs that can be created
      with improper use of the various __init prefixes.
      
      After a discussion on LKML[1] it was decided that cpuinit should go
      the way of devinit and be phased out.  Once all the users are gone,
      we can then finally remove the macros themselves from linux/init.h.
      
      Note that some harmless section mismatch warnings may result, since
      notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
      and are flagged as __cpuinit  -- so if we remove the __cpuinit from
      the arch specific callers, we will also get section mismatch warnings.
      As an intermediate step, we intend to turn the linux/init.h cpuinit
      related content into no-ops as early as possible, since that will get
      rid of these warnings.  In any case, they are temporary and harmless.
      
      This removes all the ARM uses of the __cpuinit macros from C code,
      and all __CPUINIT from assembly code.  It also had two ".previous"
      section statements that were paired off against __CPUINIT
      (aka .section ".cpuinit.text") that also get removed here.
      
      [1] https://lkml.org/lkml/2013/5/20/589
      
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
      8bd26e3a
  7. 17 4月, 2013 1 次提交
  8. 23 3月, 2013 1 次提交
  9. 04 3月, 2013 1 次提交
  10. 11 1月, 2013 3 次提交
    • D
      ARM: hw_breakpoint: Debug powerdown support for self-hosted debug · 9a6eb310
      Dietmar Eggemann 提交于
      This patch introduces debug powerdown support for self-hosted debug for v7
      and v7.1 debug architecture for a SinglePower system, i.e. a system without a
      separate core and debug power domain. On a SinglePower system the OS Lock is
      lost over a powerdown.
      
      If CONFIG_CPU_PM is set the new function pm_init() registers hw_breakpoint
      with CPU PM for a system supporting OS Save and Restore.
      
      Receiving a CPU PM EXIT notifier indicates that a single CPU has exited a low
      power state. A call to reset_ctrl_regs() is hooked into the CPU PM EXIT
      notifier chain. This function makes sure that the sticky power-down is clear
      (only v7 debug), the OS Double Lock is clear (only v7.1 debug) and it clears
      the OS Lock for v7 debug (for a system supporting OS Save and Restore) and
      v7.1 debug. Furthermore, it clears any vector-catch events and all
      breakpoint/watchpoint control/value registers for v7 and v7.1 debug.
      Signed-off-by: NDietmar Eggemann <dietmar.eggemann@arm.com>
      [will: removed redundant has_ossr check]
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      9a6eb310
    • D
      ARM: hw_breakpoint: Check function for OS Save and Restore mechanism · 57ba8997
      Dietmar Eggemann 提交于
      v7 debug introduced OS Save and Restore mechanism. On a v7 debug SinglePower
      system, i.e a system without a separate core and debug power domain, which does
      not support external debug over powerdown, it is implementation defined whether
      OS Save and Restore is implemented.
      v7.1 debug requires OS Save and Restore mechanism. v6 debug and v6.1 debug do
      not implement it.
      
      A new global variable bool has_ossr is introduced and is determined in
      arch_hw_breakpoint_init() like debug_arch or the number of BRPs/WRPs.
      
      The logic how to check if OS Save and Restore is supported has changed with
      this patch. In reset_ctrl_regs() a mask consisting of OSLM[1] (OSLSR.3) and
      OSLM[0] (OSLSR.0) was used to check if the system supports OS Save and
      Restore. In the new function core_has_os_save_restore() only OSLM[0] is used.
      It is not necessary to check OSLM[1] too since it is v7.1 debug specific and
      v7.1 debug requires OS Save and Restore and thus OS Lock.
      Signed-off-by: NDietmar Eggemann <dietmar.eggemann@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      57ba8997
    • D
      ARM: coresight: common definition for (OS) Lock Access Register key value · 02051ead
      Dietmar Eggemann 提交于
      Coresight components and debug are using a common lock control mechansim.
      Writing 0xC5ACCE55 to the Lock Access Register (LAR) in case of a coresight
      components enables further access to the coresight device registers. Writing
      any other value to it removes the write access.
      Writing 0xC5ACCE55 to the OS Lock Access Register (OSLAR) in case of debug
      locks the debug register for further access to the debug registers. Writing
      any other value to it unlocks the debug registers.
      
      Unfortunately, the existing coresight code uses the terms lock and unlock the
      other way around. Unlocking stands for enabling write access and locking for
      removing write access.
      
      That is why the definition of the LAR and OSLAR key value has been changed to
      CS_LAR_KEY.
      Signed-off-by: NDietmar Eggemann <dietmar.eggemann@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      02051ead
  11. 09 11月, 2012 8 次提交
  12. 25 8月, 2012 2 次提交
  13. 29 3月, 2012 1 次提交
  14. 08 12月, 2011 1 次提交
  15. 08 10月, 2011 1 次提交
  16. 31 8月, 2011 5 次提交
  17. 02 7月, 2011 1 次提交
  18. 11 4月, 2011 1 次提交
  19. 10 3月, 2011 1 次提交
  20. 26 2月, 2011 1 次提交
  21. 12 2月, 2011 2 次提交
  22. 15 12月, 2010 1 次提交
  23. 06 12月, 2010 3 次提交
    • W
      ARM: hw_breakpoint: fix warnings generated by sparse · 4a55c18e
      Will Deacon 提交于
      sparse doesn't like per-cpu accesses such as:
      
      static DEFINE_PER_CPU(struct perf_event *, foo[MAXLEN]);
      struct perf_event **bar = __get_cpu_var(foo);
      
      and shouts quite loudly about it:
      
      | warning: incorrect type in assignment (different modifiers)
      |    expected struct perf_event **slots
      |    got struct perf_event *[noderef] *<noident>
      
      This patch adds casts to these sorts of assignments in hw_breakpoint.c
      in order to silence the warnings.
      Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      4a55c18e
    • W
      ARM: hw_breakpoint: disallow per-cpu breakpoints without overflow handler · 3ce70b2e
      Will Deacon 提交于
      Single-stepping a breakpoint requires us to disable it temporarily so that
      we don't get stuck in a recursive debug trap. With per-cpu breakpoints this
      presents a problem where an interrupt can be taken before the single-step has
      completed and a new task is eventually scheduled. This new task will not
      hit the breakpoint because it will have been disabled during the previous
      handling code.
      
      This patch disallows per-cpu breakpoints on ARM when an overflow handler
      is not present. A similar effect can be created by placing breakpoints on
      a shell and then running applications there.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      3ce70b2e
    • W
      ARM: hw_breakpoint: unify single-stepping code for watchpoints and breakpoints · 9ebb3cbc
      Will Deacon 提交于
      The single-stepping code is currently different depending on whether
      we are stepping over a breakpoint or a watchpoint. There is no good
      reason for this, so let's sort it out.
      
      This patch adds functions for enabling/disabling single-step for
      a particular hw_breakpoint and integrates this with the exception
      handling code.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      9ebb3cbc