gpio-omap.c 39.7 KB
Newer Older
1 2 3
/*
 * Support functions for OMAP GPIO
 *
4
 * Copyright (C) 2003-2005 Nokia Corporation
5
 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6
 *
7 8 9
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
10 11 12 13 14 15 16 17
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
18
#include <linux/syscore_ops.h>
19
#include <linux/err.h>
20
#include <linux/clk.h>
21
#include <linux/io.h>
22
#include <linux/device.h>
23
#include <linux/pm_runtime.h>
24
#include <linux/pm.h>
25 26 27
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/irqdomain.h>
28
#include <linux/irqchip/chained_irq.h>
29 30
#include <linux/gpio.h>
#include <linux/platform_data/gpio-omap.h>
31

32 33
#define OFF_MODE	1

34 35
static LIST_HEAD(omap_gpio_list);

36 37 38 39 40 41 42 43 44 45 46
struct gpio_regs {
	u32 irqenable1;
	u32 irqenable2;
	u32 wake_en;
	u32 ctrl;
	u32 oe;
	u32 leveldetect0;
	u32 leveldetect1;
	u32 risingdetect;
	u32 fallingdetect;
	u32 dataout;
47 48
	u32 debounce;
	u32 debounce_en;
49 50
};

51
struct gpio_bank {
52
	struct list_head node;
53
	void __iomem *base;
54
	u16 irq;
55 56
	int irq_base;
	struct irq_domain *domain;
57 58
	u32 non_wakeup_gpios;
	u32 enabled_non_wakeup_gpios;
59
	struct gpio_regs context;
60
	u32 saved_datain;
61
	u32 level_mask;
62
	u32 toggle_mask;
63
	spinlock_t lock;
D
David Brownell 已提交
64
	struct gpio_chip chip;
65
	struct clk *dbck;
C
Charulatha V 已提交
66
	u32 mod_usage;
67
	u32 dbck_enable_mask;
68
	bool dbck_enabled;
69
	struct device *dev;
70
	bool is_mpuio;
71
	bool dbck_flag;
72
	bool loses_context;
73
	int stride;
74
	u32 width;
75
	int context_loss_count;
76 77
	int power_mode;
	bool workaround_enabled;
78 79

	void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
80
	int (*get_context_loss_count)(struct device *dev);
81 82

	struct omap_gpio_reg_offs *regs;
83 84
};

85 86
#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
87
#define GPIO_MOD_CTRL_BIT	BIT(0)
88

89 90 91 92 93
static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
{
	return gpio_irq - bank->irq_base + bank->chip.base;
}

94 95
static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
{
96
	void __iomem *reg = bank->base;
97 98
	u32 l;

99
	reg += bank->regs->direction;
100 101 102 103 104 105
	l = __raw_readl(reg);
	if (is_input)
		l |= 1 << gpio;
	else
		l &= ~(1 << gpio);
	__raw_writel(l, reg);
106
	bank->context.oe = l;
107 108
}

109 110 111

/* set data out value using dedicate set/clear register */
static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
112
{
113
	void __iomem *reg = bank->base;
114
	u32 l = GPIO_BIT(bank, gpio);
115

116
	if (enable) {
117
		reg += bank->regs->set_dataout;
118 119
		bank->context.dataout |= l;
	} else {
120
		reg += bank->regs->clr_dataout;
121 122
		bank->context.dataout &= ~l;
	}
123 124 125 126

	__raw_writel(l, reg);
}

127 128
/* set data out value using mask register */
static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
129
{
130 131 132
	void __iomem *reg = bank->base + bank->regs->dataout;
	u32 gpio_bit = GPIO_BIT(bank, gpio);
	u32 l;
133

134 135 136 137 138
	l = __raw_readl(reg);
	if (enable)
		l |= gpio_bit;
	else
		l &= ~gpio_bit;
139
	__raw_writel(l, reg);
140
	bank->context.dataout = l;
141 142
}

143
static int _get_gpio_datain(struct gpio_bank *bank, int offset)
144
{
145
	void __iomem *reg = bank->base + bank->regs->datain;
146

147
	return (__raw_readl(reg) & (1 << offset)) != 0;
148
}
149

150
static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
151
{
152
	void __iomem *reg = bank->base + bank->regs->dataout;
153

154
	return (__raw_readl(reg) & (1 << offset)) != 0;
155 156
}

157 158 159 160
static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
{
	int l = __raw_readl(base + reg);

161
	if (set)
162 163 164 165 166 167
		l |= mask;
	else
		l &= ~mask;

	__raw_writel(l, base + reg);
}
168

169 170 171 172 173
static inline void _gpio_dbck_enable(struct gpio_bank *bank)
{
	if (bank->dbck_enable_mask && !bank->dbck_enabled) {
		clk_enable(bank->dbck);
		bank->dbck_enabled = true;
174 175 176

		__raw_writel(bank->dbck_enable_mask,
			     bank->base + bank->regs->debounce_en);
177 178 179 180 181 182
	}
}

static inline void _gpio_dbck_disable(struct gpio_bank *bank)
{
	if (bank->dbck_enable_mask && bank->dbck_enabled) {
183 184 185 186 187 188 189
		/*
		 * Disable debounce before cutting it's clock. If debounce is
		 * enabled but the clock is not, GPIO module seems to be unable
		 * to detect events and generate interrupts at least on OMAP3.
		 */
		__raw_writel(0, bank->base + bank->regs->debounce_en);

190 191 192 193 194
		clk_disable(bank->dbck);
		bank->dbck_enabled = false;
	}
}

195 196 197 198 199 200 201 202 203 204 205 206
/**
 * _set_gpio_debounce - low level gpio debounce time
 * @bank: the gpio bank we're acting upon
 * @gpio: the gpio number on this @gpio
 * @debounce: debounce time to use
 *
 * OMAP's debounce time is in 31us steps so we need
 * to convert and round up to the closest unit.
 */
static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
		unsigned debounce)
{
207
	void __iomem		*reg;
208 209 210
	u32			val;
	u32			l;

211 212 213
	if (!bank->dbck_flag)
		return;

214 215 216 217 218 219 220
	if (debounce < 32)
		debounce = 0x01;
	else if (debounce > 7936)
		debounce = 0xff;
	else
		debounce = (debounce / 0x1f) - 1;

221
	l = GPIO_BIT(bank, gpio);
222

223
	clk_enable(bank->dbck);
224
	reg = bank->base + bank->regs->debounce;
225 226
	__raw_writel(debounce, reg);

227
	reg = bank->base + bank->regs->debounce_en;
228 229
	val = __raw_readl(reg);

230
	if (debounce)
231
		val |= l;
232
	else
233
		val &= ~l;
234
	bank->dbck_enable_mask = val;
235 236

	__raw_writel(val, reg);
237 238 239 240 241 242 243 244 245 246
	clk_disable(bank->dbck);
	/*
	 * Enable debounce clock per module.
	 * This call is mandatory because in omap_gpio_request() when
	 * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
	 * runtime callbck fails to turn on dbck because dbck_enable_mask
	 * used within _gpio_dbck_enable() is still not initialized at
	 * that point. Therefore we have to enable dbck here.
	 */
	_gpio_dbck_enable(bank);
247 248 249 250
	if (bank->dbck_enable_mask) {
		bank->context.debounce = debounce;
		bank->context.debounce_en = val;
	}
251 252
}

253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286
/**
 * _clear_gpio_debounce - clear debounce settings for a gpio
 * @bank: the gpio bank we're acting upon
 * @gpio: the gpio number on this @gpio
 *
 * If a gpio is using debounce, then clear the debounce enable bit and if
 * this is the only gpio in this bank using debounce, then clear the debounce
 * time too. The debounce clock will also be disabled when calling this function
 * if this is the only gpio in the bank using debounce.
 */
static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
{
	u32 gpio_bit = GPIO_BIT(bank, gpio);

	if (!bank->dbck_flag)
		return;

	if (!(bank->dbck_enable_mask & gpio_bit))
		return;

	bank->dbck_enable_mask &= ~gpio_bit;
	bank->context.debounce_en &= ~gpio_bit;
	__raw_writel(bank->context.debounce_en,
		     bank->base + bank->regs->debounce_en);

	if (!bank->dbck_enable_mask) {
		bank->context.debounce = 0;
		__raw_writel(bank->context.debounce, bank->base +
			     bank->regs->debounce);
		clk_disable(bank->dbck);
		bank->dbck_enabled = false;
	}
}

287
static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
288
						unsigned trigger)
289
{
290
	void __iomem *base = bank->base;
291 292
	u32 gpio_bit = 1 << gpio;

293 294 295 296 297 298 299 300 301
	_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
		  trigger & IRQ_TYPE_LEVEL_LOW);
	_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
		  trigger & IRQ_TYPE_LEVEL_HIGH);
	_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
		  trigger & IRQ_TYPE_EDGE_RISING);
	_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
		  trigger & IRQ_TYPE_EDGE_FALLING);

302 303 304 305 306 307 308 309 310 311
	bank->context.leveldetect0 =
			__raw_readl(bank->base + bank->regs->leveldetect0);
	bank->context.leveldetect1 =
			__raw_readl(bank->base + bank->regs->leveldetect1);
	bank->context.risingdetect =
			__raw_readl(bank->base + bank->regs->risingdetect);
	bank->context.fallingdetect =
			__raw_readl(bank->base + bank->regs->fallingdetect);

	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
312
		_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
313 314 315
		bank->context.wake_en =
			__raw_readl(bank->base + bank->regs->wkup_en);
	}
316

317
	/* This part needs to be executed always for OMAP{34xx, 44xx} */
318 319 320 321 322 323 324
	if (!bank->regs->irqctrl) {
		/* On omap24xx proceed only when valid GPIO bit is set */
		if (bank->non_wakeup_gpios) {
			if (!(bank->non_wakeup_gpios & gpio_bit))
				goto exit;
		}

325 326 327 328 329 330 331
		/*
		 * Log the edge gpio and manually trigger the IRQ
		 * after resume if the input level changes
		 * to avoid irq lost during PER RET/OFF mode
		 * Applies for omap2 non-wakeup gpio and all omap3 gpios
		 */
		if (trigger & IRQ_TYPE_EDGE_BOTH)
332 333 334 335
			bank->enabled_non_wakeup_gpios |= gpio_bit;
		else
			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
	}
336

337
exit:
338 339 340
	bank->level_mask =
		__raw_readl(bank->base + bank->regs->leveldetect0) |
		__raw_readl(bank->base + bank->regs->leveldetect1);
341 342
}

343
#ifdef CONFIG_ARCH_OMAP1
344 345 346 347 348 349 350 351 352
/*
 * This only applies to chips that can't do both rising and falling edge
 * detection at once.  For all other chips, this function is a noop.
 */
static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
{
	void __iomem *reg = bank->base;
	u32 l = 0;

353
	if (!bank->regs->irqctrl)
354
		return;
355 356

	reg += bank->regs->irqctrl;
357 358 359 360 361 362 363 364 365

	l = __raw_readl(reg);
	if ((l >> gpio) & 1)
		l &= ~(1 << gpio);
	else
		l |= 1 << gpio;

	__raw_writel(l, reg);
}
366 367
#else
static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
368
#endif
369

370 371
static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
							unsigned trigger)
372 373
{
	void __iomem *reg = bank->base;
374
	void __iomem *base = bank->base;
375
	u32 l = 0;
376

377 378 379 380 381
	if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
		set_gpio_trigger(bank, gpio, trigger);
	} else if (bank->regs->irqctrl) {
		reg += bank->regs->irqctrl;

382
		l = __raw_readl(reg);
383
		if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
384
			bank->toggle_mask |= 1 << gpio;
385
		if (trigger & IRQ_TYPE_EDGE_RISING)
386
			l |= 1 << gpio;
387
		else if (trigger & IRQ_TYPE_EDGE_FALLING)
388
			l &= ~(1 << gpio);
389
		else
390 391 392 393
			return -EINVAL;

		__raw_writel(l, reg);
	} else if (bank->regs->edgectrl1) {
394
		if (gpio & 0x08)
395
			reg += bank->regs->edgectrl2;
396
		else
397 398
			reg += bank->regs->edgectrl1;

399 400 401
		gpio &= 0x07;
		l = __raw_readl(reg);
		l &= ~(3 << (gpio << 1));
402
		if (trigger & IRQ_TYPE_EDGE_RISING)
403
			l |= 2 << (gpio << 1);
404
		if (trigger & IRQ_TYPE_EDGE_FALLING)
405
			l |= 1 << (gpio << 1);
406 407 408

		/* Enable wake-up during idle for dynamic tick */
		_gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
409 410
		bank->context.wake_en =
			__raw_readl(bank->base + bank->regs->wkup_en);
411
		__raw_writel(l, reg);
412
	}
413
	return 0;
414 415
}

416
static int gpio_irq_type(struct irq_data *d, unsigned type)
417
{
418
	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
419
	unsigned gpio = 0;
420
	int retval;
D
David Brownell 已提交
421
	unsigned long flags;
422

423 424
#ifdef CONFIG_ARCH_OMAP1
	if (d->irq > IH_MPUIO_BASE)
425
		gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
426 427 428
#endif

	if (!gpio)
429
		gpio = irq_to_gpio(bank, d->irq);
430

431
	if (type & ~IRQ_TYPE_SENSE_MASK)
432
		return -EINVAL;
433

434 435
	if (!bank->regs->leveldetect0 &&
		(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
436 437
		return -EINVAL;

D
David Brownell 已提交
438
	spin_lock_irqsave(&bank->lock, flags);
439
	retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
D
David Brownell 已提交
440
	spin_unlock_irqrestore(&bank->lock, flags);
441 442

	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
T
Thomas Gleixner 已提交
443
		__irq_set_handler_locked(d->irq, handle_level_irq);
444
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
T
Thomas Gleixner 已提交
445
		__irq_set_handler_locked(d->irq, handle_edge_irq);
446

447
	return retval;
448 449 450 451
}

static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
{
452
	void __iomem *reg = bank->base;
453

454
	reg += bank->regs->irqstatus;
455
	__raw_writel(gpio_mask, reg);
456 457

	/* Workaround for clearing DSP GPIO interrupts to allow retention */
458 459
	if (bank->regs->irqstatus2) {
		reg = bank->base + bank->regs->irqstatus2;
460
		__raw_writel(gpio_mask, reg);
461
	}
462 463 464

	/* Flush posted write for the irq status to avoid spurious interrupts */
	__raw_readl(reg);
465 466 467 468
}

static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
{
469
	_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
470 471
}

472 473 474
static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
{
	void __iomem *reg = bank->base;
475
	u32 l;
476
	u32 mask = (1 << bank->width) - 1;
477

478
	reg += bank->regs->irqenable;
479
	l = __raw_readl(reg);
480
	if (bank->regs->irqenable_inv)
481 482 483
		l = ~l;
	l &= mask;
	return l;
484 485
}

486
static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
487
{
488
	void __iomem *reg = bank->base;
489 490
	u32 l;

491 492 493
	if (bank->regs->set_irqenable) {
		reg += bank->regs->set_irqenable;
		l = gpio_mask;
494
		bank->context.irqenable1 |= gpio_mask;
495 496
	} else {
		reg += bank->regs->irqenable;
497
		l = __raw_readl(reg);
498 499
		if (bank->regs->irqenable_inv)
			l &= ~gpio_mask;
500 501
		else
			l |= gpio_mask;
502
		bank->context.irqenable1 = l;
503 504 505 506 507 508 509 510 511 512 513 514
	}

	__raw_writel(l, reg);
}

static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
{
	void __iomem *reg = bank->base;
	u32 l;

	if (bank->regs->clr_irqenable) {
		reg += bank->regs->clr_irqenable;
515
		l = gpio_mask;
516
		bank->context.irqenable1 &= ~gpio_mask;
517 518
	} else {
		reg += bank->regs->irqenable;
519
		l = __raw_readl(reg);
520
		if (bank->regs->irqenable_inv)
521
			l |= gpio_mask;
522
		else
523
			l &= ~gpio_mask;
524
		bank->context.irqenable1 = l;
525
	}
526

527 528 529 530 531
	__raw_writel(l, reg);
}

static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
{
532 533 534 535
	if (enable)
		_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
	else
		_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
536 537
}

538 539 540 541 542 543 544 545 546 547
/*
 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
 * 1510 does not seem to have a wake-up register. If JTAG is connected
 * to the target, system will wake up always on GPIO events. While
 * system is running all registered GPIO interrupts need to have wake-up
 * enabled. When system is suspended, only selected GPIO interrupts need
 * to have wake-up enabled.
 */
static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
{
548 549
	u32 gpio_bit = GPIO_BIT(bank, gpio);
	unsigned long flags;
D
David Brownell 已提交
550

551
	if (bank->non_wakeup_gpios & gpio_bit) {
552
		dev_err(bank->dev,
553
			"Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
554 555
		return -EINVAL;
	}
556 557 558

	spin_lock_irqsave(&bank->lock, flags);
	if (enable)
559
		bank->context.wake_en |= gpio_bit;
560
	else
561
		bank->context.wake_en &= ~gpio_bit;
562

563
	__raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
564 565 566
	spin_unlock_irqrestore(&bank->lock, flags);

	return 0;
567 568
}

569 570
static void _reset_gpio(struct gpio_bank *bank, int gpio)
{
571
	_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
572 573
	_set_gpio_irqenable(bank, gpio, 0);
	_clear_gpio_irqstatus(bank, gpio);
574
	_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
575
	_clear_gpio_debounce(bank, gpio);
576 577
}

578
/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
579
static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
580
{
581 582
	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
	unsigned int gpio = irq_to_gpio(bank, d->irq);
583

584
	return _set_gpio_wakeup(bank, gpio, enable);
585 586
}

587
static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
588
{
589
	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
D
David Brownell 已提交
590
	unsigned long flags;
D
David Brownell 已提交
591

592 593 594 595 596 597
	/*
	 * If this is the first gpio_request for the bank,
	 * enable the bank module.
	 */
	if (!bank->mod_usage)
		pm_runtime_get_sync(bank->dev);
598

599
	spin_lock_irqsave(&bank->lock, flags);
600 601 602
	/* Set trigger to none. You need to enable the desired trigger with
	 * request_irq() or set_irq_type().
	 */
603
	_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
604

605 606
	if (bank->regs->pinctrl) {
		void __iomem *reg = bank->base + bank->regs->pinctrl;
607

608
		/* Claim the pin for MPU */
609
		__raw_writel(__raw_readl(reg) | (1 << offset), reg);
610
	}
611

612 613 614 615 616 617 618 619
	if (bank->regs->ctrl && !bank->mod_usage) {
		void __iomem *reg = bank->base + bank->regs->ctrl;
		u32 ctrl;

		ctrl = __raw_readl(reg);
		/* Module is enabled, clocks are not gated */
		ctrl &= ~GPIO_MOD_CTRL_BIT;
		__raw_writel(ctrl, reg);
620
		bank->context.ctrl = ctrl;
C
Charulatha V 已提交
621
	}
622 623 624

	bank->mod_usage |= 1 << offset;

D
David Brownell 已提交
625
	spin_unlock_irqrestore(&bank->lock, flags);
626 627 628 629

	return 0;
}

630
static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
631
{
632
	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
633
	void __iomem *base = bank->base;
D
David Brownell 已提交
634
	unsigned long flags;
635

D
David Brownell 已提交
636
	spin_lock_irqsave(&bank->lock, flags);
637

638
	if (bank->regs->wkup_en) {
639
		/* Disable wake-up during idle for dynamic tick */
640
		_gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
641 642 643
		bank->context.wake_en =
			__raw_readl(bank->base + bank->regs->wkup_en);
	}
644

645 646 647 648 649 650 651 652 653 654
	bank->mod_usage &= ~(1 << offset);

	if (bank->regs->ctrl && !bank->mod_usage) {
		void __iomem *reg = bank->base + bank->regs->ctrl;
		u32 ctrl;

		ctrl = __raw_readl(reg);
		/* Module is disabled, clocks are gated */
		ctrl |= GPIO_MOD_CTRL_BIT;
		__raw_writel(ctrl, reg);
655
		bank->context.ctrl = ctrl;
C
Charulatha V 已提交
656
	}
657

658
	_reset_gpio(bank, bank->chip.base + offset);
D
David Brownell 已提交
659
	spin_unlock_irqrestore(&bank->lock, flags);
660 661 662 663 664 665 666

	/*
	 * If this is the last gpio to be freed in the bank,
	 * disable the bank module.
	 */
	if (!bank->mod_usage)
		pm_runtime_put(bank->dev);
667 668 669 670 671 672 673 674 675 676 677
}

/*
 * We need to unmask the GPIO bank interrupt as soon as possible to
 * avoid missing GPIO interrupts for other lines in the bank.
 * Then we need to mask-read-clear-unmask the triggered GPIO lines
 * in the bank to avoid missing nested interrupts for a GPIO line.
 * If we wait to unmask individual GPIO lines in the bank after the
 * line's interrupt handler has been run, we may miss some nested
 * interrupts.
 */
678
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
679
{
680
	void __iomem *isr_reg = NULL;
681
	u32 isr;
682
	unsigned int gpio_irq, gpio_index;
683
	struct gpio_bank *bank;
684
	int unmasked = 0;
685
	struct irq_chip *chip = irq_desc_get_chip(desc);
686

687
	chained_irq_enter(chip, desc);
688

T
Thomas Gleixner 已提交
689
	bank = irq_get_handler_data(irq);
690
	isr_reg = bank->base + bank->regs->irqstatus;
691
	pm_runtime_get_sync(bank->dev);
692 693 694 695

	if (WARN_ON(!isr_reg))
		goto exit;

696
	while(1) {
697
		u32 isr_saved, level_mask = 0;
698
		u32 enabled;
699

700 701
		enabled = _get_gpio_irqbank_mask(bank);
		isr_saved = isr = __raw_readl(isr_reg) & enabled;
702

703
		if (bank->level_mask)
704
			level_mask = bank->level_mask & enabled;
705 706 707 708

		/* clear edge sensitive interrupts before handler(s) are
		called so that we don't miss any interrupt occurred while
		executing them */
709
		_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
710
		_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
711
		_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
712 713 714

		/* if there is only edge sensitive GPIO pin interrupts
		configured, we could unmask GPIO bank interrupt immediately */
715 716
		if (!level_mask && !unmasked) {
			unmasked = 1;
717
			chained_irq_exit(chip, desc);
718
		}
719 720 721 722

		if (!isr)
			break;

723
		gpio_irq = bank->irq_base;
724
		for (; isr != 0; isr >>= 1, gpio_irq++) {
725
			int gpio = irq_to_gpio(bank, gpio_irq);
726

727 728
			if (!(isr & 1))
				continue;
729

730 731
			gpio_index = GPIO_INDEX(bank, gpio);

732 733 734 735 736 737 738 739 740 741
			/*
			 * Some chips can't respond to both rising and falling
			 * at the same time.  If this irq was requested with
			 * both flags, we need to flip the ICR data for the IRQ
			 * to respond to the IRQ for the opposite direction.
			 * This will be indicated in the bank toggle_mask.
			 */
			if (bank->toggle_mask & (1 << gpio_index))
				_toggle_gpio_edge_triggering(bank, gpio_index);

742
			generic_handle_irq(gpio_irq);
743
		}
744
	}
745 746 747 748
	/* if bank has any level sensitive GPIO pin interrupt
	configured, we must unmask the bank interrupt only after
	handler(s) are executed in order to avoid spurious bank
	interrupt */
749
exit:
750
	if (!unmasked)
751
		chained_irq_exit(chip, desc);
752
	pm_runtime_put(bank->dev);
753 754
}

755
static void gpio_irq_shutdown(struct irq_data *d)
756
{
757
	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
758
	unsigned int gpio = irq_to_gpio(bank, d->irq);
759
	unsigned long flags;
760

761
	spin_lock_irqsave(&bank->lock, flags);
762
	_reset_gpio(bank, gpio);
763
	spin_unlock_irqrestore(&bank->lock, flags);
764 765
}

766
static void gpio_ack_irq(struct irq_data *d)
767
{
768
	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
769
	unsigned int gpio = irq_to_gpio(bank, d->irq);
770 771 772 773

	_clear_gpio_irqstatus(bank, gpio);
}

774
static void gpio_mask_irq(struct irq_data *d)
775
{
776
	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
777
	unsigned int gpio = irq_to_gpio(bank, d->irq);
778
	unsigned long flags;
779

780
	spin_lock_irqsave(&bank->lock, flags);
781
	_set_gpio_irqenable(bank, gpio, 0);
782
	_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
783
	spin_unlock_irqrestore(&bank->lock, flags);
784 785
}

786
static void gpio_unmask_irq(struct irq_data *d)
787
{
788
	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
789
	unsigned int gpio = irq_to_gpio(bank, d->irq);
790
	unsigned int irq_mask = GPIO_BIT(bank, gpio);
791
	u32 trigger = irqd_get_trigger_type(d);
792
	unsigned long flags;
793

794
	spin_lock_irqsave(&bank->lock, flags);
795
	if (trigger)
796
		_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
797 798 799 800 801 802 803

	/* For level-triggered GPIOs, the clearing must be done after
	 * the HW source is cleared, thus after the handler has run */
	if (bank->level_mask & irq_mask) {
		_set_gpio_irqenable(bank, gpio, 0);
		_clear_gpio_irqstatus(bank, gpio);
	}
804

K
Kevin Hilman 已提交
805
	_set_gpio_irqenable(bank, gpio, 1);
806
	spin_unlock_irqrestore(&bank->lock, flags);
807 808
}

809 810
static struct irq_chip gpio_irq_chip = {
	.name		= "GPIO",
811 812 813 814 815 816
	.irq_shutdown	= gpio_irq_shutdown,
	.irq_ack	= gpio_ack_irq,
	.irq_mask	= gpio_mask_irq,
	.irq_unmask	= gpio_unmask_irq,
	.irq_set_type	= gpio_irq_type,
	.irq_set_wake	= gpio_wake_enable,
817 818 819 820
};

/*---------------------------------------------------------------------*/

821
static int omap_mpuio_suspend_noirq(struct device *dev)
D
David Brownell 已提交
822
{
823
	struct platform_device *pdev = to_platform_device(dev);
D
David Brownell 已提交
824
	struct gpio_bank	*bank = platform_get_drvdata(pdev);
825 826
	void __iomem		*mask_reg = bank->base +
					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
D
David Brownell 已提交
827
	unsigned long		flags;
D
David Brownell 已提交
828

D
David Brownell 已提交
829
	spin_lock_irqsave(&bank->lock, flags);
830
	__raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
D
David Brownell 已提交
831
	spin_unlock_irqrestore(&bank->lock, flags);
D
David Brownell 已提交
832 833 834 835

	return 0;
}

836
static int omap_mpuio_resume_noirq(struct device *dev)
D
David Brownell 已提交
837
{
838
	struct platform_device *pdev = to_platform_device(dev);
D
David Brownell 已提交
839
	struct gpio_bank	*bank = platform_get_drvdata(pdev);
840 841
	void __iomem		*mask_reg = bank->base +
					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
D
David Brownell 已提交
842
	unsigned long		flags;
D
David Brownell 已提交
843

D
David Brownell 已提交
844
	spin_lock_irqsave(&bank->lock, flags);
845
	__raw_writel(bank->context.wake_en, mask_reg);
D
David Brownell 已提交
846
	spin_unlock_irqrestore(&bank->lock, flags);
D
David Brownell 已提交
847 848 849 850

	return 0;
}

851
static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
852 853 854 855
	.suspend_noirq = omap_mpuio_suspend_noirq,
	.resume_noirq = omap_mpuio_resume_noirq,
};

856
/* use platform_driver for this. */
D
David Brownell 已提交
857 858 859
static struct platform_driver omap_mpuio_driver = {
	.driver		= {
		.name	= "mpuio",
860
		.pm	= &omap_mpuio_dev_pm_ops,
D
David Brownell 已提交
861 862 863 864 865 866 867 868 869 870 871 872
	},
};

static struct platform_device omap_mpuio_device = {
	.name		= "mpuio",
	.id		= -1,
	.dev = {
		.driver = &omap_mpuio_driver.driver,
	}
	/* could list the /proc/iomem resources */
};

873
static inline void mpuio_init(struct gpio_bank *bank)
D
David Brownell 已提交
874
{
875
	platform_set_drvdata(&omap_mpuio_device, bank);
876

D
David Brownell 已提交
877 878 879 880
	if (platform_driver_register(&omap_mpuio_driver) == 0)
		(void) platform_device_register(&omap_mpuio_device);
}

881
/*---------------------------------------------------------------------*/
882

D
David Brownell 已提交
883 884 885 886 887 888 889 890 891 892 893 894
static int gpio_input(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_bank *bank;
	unsigned long flags;

	bank = container_of(chip, struct gpio_bank, chip);
	spin_lock_irqsave(&bank->lock, flags);
	_set_gpio_direction(bank, offset, 1);
	spin_unlock_irqrestore(&bank->lock, flags);
	return 0;
}

895 896
static int gpio_is_input(struct gpio_bank *bank, int mask)
{
897
	void __iomem *reg = bank->base + bank->regs->direction;
898 899 900 901

	return __raw_readl(reg) & mask;
}

D
David Brownell 已提交
902 903
static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
904 905 906
	struct gpio_bank *bank;
	u32 mask;

C
Charulatha V 已提交
907
	bank = container_of(chip, struct gpio_bank, chip);
908
	mask = (1 << offset);
909 910

	if (gpio_is_input(bank, mask))
911
		return _get_gpio_datain(bank, offset);
912
	else
913
		return _get_gpio_dataout(bank, offset);
D
David Brownell 已提交
914 915 916 917 918 919 920 921 922
}

static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
{
	struct gpio_bank *bank;
	unsigned long flags;

	bank = container_of(chip, struct gpio_bank, chip);
	spin_lock_irqsave(&bank->lock, flags);
923
	bank->set_dataout(bank, offset, value);
D
David Brownell 已提交
924 925 926 927 928
	_set_gpio_direction(bank, offset, 0);
	spin_unlock_irqrestore(&bank->lock, flags);
	return 0;
}

929 930 931 932 933 934 935
static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
		unsigned debounce)
{
	struct gpio_bank *bank;
	unsigned long flags;

	bank = container_of(chip, struct gpio_bank, chip);
936

937 938 939 940 941 942 943
	spin_lock_irqsave(&bank->lock, flags);
	_set_gpio_debounce(bank, offset, debounce);
	spin_unlock_irqrestore(&bank->lock, flags);

	return 0;
}

D
David Brownell 已提交
944 945 946 947 948 949 950
static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct gpio_bank *bank;
	unsigned long flags;

	bank = container_of(chip, struct gpio_bank, chip);
	spin_lock_irqsave(&bank->lock, flags);
951
	bank->set_dataout(bank, offset, value);
D
David Brownell 已提交
952 953 954
	spin_unlock_irqrestore(&bank->lock, flags);
}

955 956 957 958 959
static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_bank *bank;

	bank = container_of(chip, struct gpio_bank, chip);
960
	return bank->irq_base + offset;
961 962
}

D
David Brownell 已提交
963 964
/*---------------------------------------------------------------------*/

965
static void __init omap_gpio_show_rev(struct gpio_bank *bank)
T
Tony Lindgren 已提交
966
{
967
	static bool called;
T
Tony Lindgren 已提交
968 969
	u32 rev;

970
	if (called || bank->regs->revision == USHRT_MAX)
T
Tony Lindgren 已提交
971 972
		return;

973 974
	rev = __raw_readw(bank->base + bank->regs->revision);
	pr_info("OMAP GPIO hardware version %d.%d\n",
T
Tony Lindgren 已提交
975
		(rev >> 4) & 0x0f, rev & 0x0f);
976 977

	called = true;
T
Tony Lindgren 已提交
978 979
}

980 981 982 983 984
/* This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

985
static void omap_gpio_mod_init(struct gpio_bank *bank)
986
{
987 988
	void __iomem *base = bank->base;
	u32 l = 0xffffffff;
989

990 991 992
	if (bank->width == 16)
		l = 0xffff;

993
	if (bank->is_mpuio) {
994 995
		__raw_writel(l, bank->base + bank->regs->irqenable);
		return;
996
	}
997 998

	_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
999
	_gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
1000
	if (bank->regs->debounce_en)
1001
		__raw_writel(0, base + bank->regs->debounce_en);
1002

1003 1004
	/* Save OE default value (0xffffffff) in the context */
	bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
1005 1006
	 /* Initialize interface clk ungated, module enabled */
	if (bank->regs->ctrl)
1007
		__raw_writel(0, base + bank->regs->ctrl);
1008 1009 1010 1011

	bank->dbck = clk_get(bank->dev, "dbclk");
	if (IS_ERR(bank->dbck))
		dev_err(bank->dev, "Could not get gpio dbck\n");
1012 1013
}

B
Bill Pemberton 已提交
1014
static void
1015 1016 1017 1018 1019 1020 1021 1022
omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
		    unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
				    handle_simple_irq);
1023 1024 1025 1026 1027
	if (!gc) {
		dev_err(bank->dev, "Memory alloc failed for gc\n");
		return;
	}

1028 1029 1030 1031 1032 1033
	ct = gc->chip_types;

	/* NOTE: No ack required, reading IRQ status clears it. */
	ct->chip.irq_mask = irq_gc_mask_set_bit;
	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
	ct->chip.irq_set_type = gpio_irq_type;
1034 1035

	if (bank->regs->wkup_en)
1036 1037 1038 1039 1040 1041 1042
		ct->chip.irq_set_wake = gpio_wake_enable,

	ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

B
Bill Pemberton 已提交
1043
static void omap_gpio_chip_init(struct gpio_bank *bank)
1044
{
1045
	int j;
1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059
	static int gpio;

	/*
	 * REVISIT eventually switch from OMAP-specific gpio structs
	 * over to the generic ones
	 */
	bank->chip.request = omap_gpio_request;
	bank->chip.free = omap_gpio_free;
	bank->chip.direction_input = gpio_input;
	bank->chip.get = gpio_get;
	bank->chip.direction_output = gpio_output;
	bank->chip.set_debounce = gpio_debounce;
	bank->chip.set = gpio_set;
	bank->chip.to_irq = gpio_2irq;
1060
	if (bank->is_mpuio) {
1061
		bank->chip.label = "mpuio";
1062 1063
		if (bank->regs->wkup_en)
			bank->chip.dev = &omap_mpuio_device.dev;
1064 1065 1066 1067
		bank->chip.base = OMAP_MPUIO(0);
	} else {
		bank->chip.label = "gpio";
		bank->chip.base = gpio;
1068
		gpio += bank->width;
1069
	}
1070
	bank->chip.ngpio = bank->width;
1071 1072 1073

	gpiochip_add(&bank->chip);

1074
	for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) {
1075
		irq_set_lockdep_class(j, &gpio_lock_class);
T
Thomas Gleixner 已提交
1076
		irq_set_chip_data(j, bank);
1077
		if (bank->is_mpuio) {
1078 1079
			omap_mpuio_alloc_gc(bank, j, bank->width);
		} else {
T
Thomas Gleixner 已提交
1080
			irq_set_chip(j, &gpio_irq_chip);
1081 1082 1083
			irq_set_handler(j, handle_simple_irq);
			set_irq_flags(j, IRQF_VALID);
		}
1084
	}
T
Thomas Gleixner 已提交
1085 1086
	irq_set_chained_handler(bank->irq, gpio_irq_handler);
	irq_set_handler_data(bank->irq, bank);
1087 1088
}

1089 1090
static const struct of_device_id omap_gpio_match[];

B
Bill Pemberton 已提交
1091
static int omap_gpio_probe(struct platform_device *pdev)
1092
{
1093
	struct device *dev = &pdev->dev;
1094 1095
	struct device_node *node = dev->of_node;
	const struct of_device_id *match;
1096
	const struct omap_gpio_platform_data *pdata;
1097
	struct resource *res;
1098
	struct gpio_bank *bank;
1099
	int ret = 0;
1100

1101 1102 1103 1104
	match = of_match_device(of_match_ptr(omap_gpio_match), dev);

	pdata = match ? match->data : dev->platform_data;
	if (!pdata)
1105
		return -EINVAL;
1106

1107
	bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1108
	if (!bank) {
1109
		dev_err(dev, "Memory alloc failed\n");
1110
		return -ENOMEM;
1111
	}
1112

1113 1114
	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (unlikely(!res)) {
1115
		dev_err(dev, "Invalid IRQ resource\n");
1116
		return -ENODEV;
1117
	}
1118

1119
	bank->irq = res->start;
1120
	bank->dev = dev;
1121
	bank->dbck_flag = pdata->dbck_flag;
1122
	bank->stride = pdata->bank_stride;
1123
	bank->width = pdata->bank_width;
1124
	bank->is_mpuio = pdata->is_mpuio;
1125
	bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1126
	bank->loses_context = pdata->loses_context;
1127
	bank->regs = pdata->regs;
1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139
#ifdef CONFIG_OF_GPIO
	bank->chip.of_node = of_node_get(node);
#endif

	bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
	if (bank->irq_base < 0) {
		dev_err(dev, "Couldn't allocate IRQ numbers\n");
		return -ENODEV;
	}

	bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base,
					     0, &irq_domain_simple_ops, NULL);
1140 1141 1142 1143 1144

	if (bank->regs->set_dataout && bank->regs->clr_dataout)
		bank->set_dataout = _set_gpio_dataout_reg;
	else
		bank->set_dataout = _set_gpio_dataout_mask;
T
Tony Lindgren 已提交
1145

1146
	spin_lock_init(&bank->lock);
T
Tony Lindgren 已提交
1147

1148 1149 1150
	/* Static mapping, never released */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(!res)) {
1151
		dev_err(dev, "Invalid mem resource\n");
1152 1153 1154 1155 1156 1157 1158
		return -ENODEV;
	}

	if (!devm_request_mem_region(dev, res->start, resource_size(res),
				     pdev->name)) {
		dev_err(dev, "Region already claimed\n");
		return -EBUSY;
1159
	}
1160

1161
	bank->base = devm_ioremap(dev, res->start, resource_size(res));
1162
	if (!bank->base) {
1163
		dev_err(dev, "Could not ioremap\n");
1164
		return -ENOMEM;
1165 1166
	}

1167 1168
	platform_set_drvdata(pdev, bank);

1169
	pm_runtime_enable(bank->dev);
1170
	pm_runtime_irq_safe(bank->dev);
1171 1172
	pm_runtime_get_sync(bank->dev);

1173
	if (bank->is_mpuio)
1174 1175
		mpuio_init(bank);

1176
	omap_gpio_mod_init(bank);
1177
	omap_gpio_chip_init(bank);
1178
	omap_gpio_show_rev(bank);
T
Tony Lindgren 已提交
1179

1180 1181 1182
	if (bank->loses_context)
		bank->get_context_loss_count = pdata->get_context_loss_count;

1183 1184
	pm_runtime_put(bank->dev);

1185
	list_add_tail(&bank->node, &omap_gpio_list);
1186

1187
	return ret;
1188 1189
}

1190 1191
#ifdef CONFIG_ARCH_OMAP2PLUS

1192
#if defined(CONFIG_PM_RUNTIME)
1193
static void omap_gpio_restore_context(struct gpio_bank *bank);
1194

1195
static int omap_gpio_runtime_suspend(struct device *dev)
1196
{
1197 1198 1199 1200
	struct platform_device *pdev = to_platform_device(dev);
	struct gpio_bank *bank = platform_get_drvdata(pdev);
	u32 l1 = 0, l2 = 0;
	unsigned long flags;
1201
	u32 wake_low, wake_hi;
1202

1203
	spin_lock_irqsave(&bank->lock, flags);
1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224

	/*
	 * Only edges can generate a wakeup event to the PRCM.
	 *
	 * Therefore, ensure any wake-up capable GPIOs have
	 * edge-detection enabled before going idle to ensure a wakeup
	 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
	 * NDA TRM 25.5.3.1)
	 *
	 * The normal values will be restored upon ->runtime_resume()
	 * by writing back the values saved in bank->context.
	 */
	wake_low = bank->context.leveldetect0 & bank->context.wake_en;
	if (wake_low)
		__raw_writel(wake_low | bank->context.fallingdetect,
			     bank->base + bank->regs->fallingdetect);
	wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
	if (wake_hi)
		__raw_writel(wake_hi | bank->context.risingdetect,
			     bank->base + bank->regs->risingdetect);

1225 1226 1227
	if (!bank->enabled_non_wakeup_gpios)
		goto update_gpio_context_count;

1228 1229
	if (bank->power_mode != OFF_MODE) {
		bank->power_mode = 0;
1230
		goto update_gpio_context_count;
1231 1232 1233 1234 1235 1236 1237 1238
	}
	/*
	 * If going to OFF, remove triggering for all
	 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
	 * generated.  See OMAP2420 Errata item 1.101.
	 */
	bank->saved_datain = __raw_readl(bank->base +
						bank->regs->datain);
1239 1240
	l1 = bank->context.fallingdetect;
	l2 = bank->context.risingdetect;
1241

1242 1243
	l1 &= ~bank->enabled_non_wakeup_gpios;
	l2 &= ~bank->enabled_non_wakeup_gpios;
1244

1245 1246
	__raw_writel(l1, bank->base + bank->regs->fallingdetect);
	__raw_writel(l2, bank->base + bank->regs->risingdetect);
1247

1248
	bank->workaround_enabled = true;
1249

1250
update_gpio_context_count:
1251 1252
	if (bank->get_context_loss_count)
		bank->context_loss_count =
1253 1254
				bank->get_context_loss_count(bank->dev);

1255
	_gpio_dbck_disable(bank);
1256
	spin_unlock_irqrestore(&bank->lock, flags);
1257

1258
	return 0;
1259 1260
}

1261
static int omap_gpio_runtime_resume(struct device *dev)
1262
{
1263 1264 1265 1266 1267
	struct platform_device *pdev = to_platform_device(dev);
	struct gpio_bank *bank = platform_get_drvdata(pdev);
	int context_lost_cnt_after;
	u32 l = 0, gen, gen0, gen1;
	unsigned long flags;
1268

1269
	spin_lock_irqsave(&bank->lock, flags);
1270
	_gpio_dbck_enable(bank);
1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282

	/*
	 * In ->runtime_suspend(), level-triggered, wakeup-enabled
	 * GPIOs were set to edge trigger also in order to be able to
	 * generate a PRCM wakeup.  Here we restore the
	 * pre-runtime_suspend() values for edge triggering.
	 */
	__raw_writel(bank->context.fallingdetect,
		     bank->base + bank->regs->fallingdetect);
	__raw_writel(bank->context.risingdetect,
		     bank->base + bank->regs->risingdetect);

1283 1284 1285
	if (bank->get_context_loss_count) {
		context_lost_cnt_after =
			bank->get_context_loss_count(bank->dev);
1286
		if (context_lost_cnt_after != bank->context_loss_count) {
1287 1288 1289 1290
			omap_gpio_restore_context(bank);
		} else {
			spin_unlock_irqrestore(&bank->lock, flags);
			return 0;
1291
		}
1292
	}
1293

1294 1295 1296 1297 1298
	if (!bank->workaround_enabled) {
		spin_unlock_irqrestore(&bank->lock, flags);
		return 0;
	}

1299
	__raw_writel(bank->context.fallingdetect,
1300
			bank->base + bank->regs->fallingdetect);
1301
	__raw_writel(bank->context.risingdetect,
1302 1303
			bank->base + bank->regs->risingdetect);
	l = __raw_readl(bank->base + bank->regs->datain);
1304

1305 1306 1307 1308 1309 1310 1311 1312
	/*
	 * Check if any of the non-wakeup interrupt GPIOs have changed
	 * state.  If so, generate an IRQ by software.  This is
	 * horribly racy, but it's the best we can do to work around
	 * this silicon bug.
	 */
	l ^= bank->saved_datain;
	l &= bank->enabled_non_wakeup_gpios;
1313

1314 1315 1316 1317
	/*
	 * No need to generate IRQs for the rising edge for gpio IRQs
	 * configured with falling edge only; and vice versa.
	 */
1318
	gen0 = l & bank->context.fallingdetect;
1319
	gen0 &= bank->saved_datain;
1320

1321
	gen1 = l & bank->context.risingdetect;
1322
	gen1 &= ~(bank->saved_datain);
1323

1324
	/* FIXME: Consider GPIO IRQs with level detections properly! */
1325 1326
	gen = l & (~(bank->context.fallingdetect) &
					 ~(bank->context.risingdetect));
1327 1328
	/* Consider all GPIO IRQs needed to be updated */
	gen |= gen0 | gen1;
1329

1330 1331
	if (gen) {
		u32 old0, old1;
1332

1333 1334
		old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
		old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1335

1336
		if (!bank->regs->irqstatus_raw0) {
1337
			__raw_writel(old0 | gen, bank->base +
1338
						bank->regs->leveldetect0);
1339
			__raw_writel(old1 | gen, bank->base +
1340
						bank->regs->leveldetect1);
1341
		}
1342

1343
		if (bank->regs->irqstatus_raw0) {
1344
			__raw_writel(old0 | l, bank->base +
1345
						bank->regs->leveldetect0);
1346
			__raw_writel(old1 | l, bank->base +
1347
						bank->regs->leveldetect1);
1348
		}
1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382
		__raw_writel(old0, bank->base + bank->regs->leveldetect0);
		__raw_writel(old1, bank->base + bank->regs->leveldetect1);
	}

	bank->workaround_enabled = false;
	spin_unlock_irqrestore(&bank->lock, flags);

	return 0;
}
#endif /* CONFIG_PM_RUNTIME */

void omap2_gpio_prepare_for_idle(int pwr_mode)
{
	struct gpio_bank *bank;

	list_for_each_entry(bank, &omap_gpio_list, node) {
		if (!bank->mod_usage || !bank->loses_context)
			continue;

		bank->power_mode = pwr_mode;

		pm_runtime_put_sync_suspend(bank->dev);
	}
}

void omap2_gpio_resume_after_idle(void)
{
	struct gpio_bank *bank;

	list_for_each_entry(bank, &omap_gpio_list, node) {
		if (!bank->mod_usage || !bank->loses_context)
			continue;

		pm_runtime_get_sync(bank->dev);
1383 1384 1385
	}
}

1386
#if defined(CONFIG_PM_RUNTIME)
1387
static void omap_gpio_restore_context(struct gpio_bank *bank)
1388
{
1389
	__raw_writel(bank->context.wake_en,
1390 1391
				bank->base + bank->regs->wkup_en);
	__raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1392
	__raw_writel(bank->context.leveldetect0,
1393
				bank->base + bank->regs->leveldetect0);
1394
	__raw_writel(bank->context.leveldetect1,
1395
				bank->base + bank->regs->leveldetect1);
1396
	__raw_writel(bank->context.risingdetect,
1397
				bank->base + bank->regs->risingdetect);
1398
	__raw_writel(bank->context.fallingdetect,
1399
				bank->base + bank->regs->fallingdetect);
1400 1401 1402 1403 1404 1405
	if (bank->regs->set_dataout && bank->regs->clr_dataout)
		__raw_writel(bank->context.dataout,
				bank->base + bank->regs->set_dataout);
	else
		__raw_writel(bank->context.dataout,
				bank->base + bank->regs->dataout);
1406 1407
	__raw_writel(bank->context.oe, bank->base + bank->regs->direction);

1408 1409 1410 1411 1412 1413
	if (bank->dbck_enable_mask) {
		__raw_writel(bank->context.debounce, bank->base +
					bank->regs->debounce);
		__raw_writel(bank->context.debounce_en,
					bank->base + bank->regs->debounce_en);
	}
1414 1415 1416 1417 1418

	__raw_writel(bank->context.irqenable1,
				bank->base + bank->regs->irqenable);
	__raw_writel(bank->context.irqenable2,
				bank->base + bank->regs->irqenable2);
1419
}
1420
#endif /* CONFIG_PM_RUNTIME */
1421
#else
1422 1423
#define omap_gpio_runtime_suspend NULL
#define omap_gpio_runtime_resume NULL
1424 1425
#endif

1426
static const struct dev_pm_ops gpio_pm_ops = {
1427 1428
	SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
									NULL)
1429 1430
};

1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477
#if defined(CONFIG_OF)
static struct omap_gpio_reg_offs omap2_gpio_regs = {
	.revision =		OMAP24XX_GPIO_REVISION,
	.direction =		OMAP24XX_GPIO_OE,
	.datain =		OMAP24XX_GPIO_DATAIN,
	.dataout =		OMAP24XX_GPIO_DATAOUT,
	.set_dataout =		OMAP24XX_GPIO_SETDATAOUT,
	.clr_dataout =		OMAP24XX_GPIO_CLEARDATAOUT,
	.irqstatus =		OMAP24XX_GPIO_IRQSTATUS1,
	.irqstatus2 =		OMAP24XX_GPIO_IRQSTATUS2,
	.irqenable =		OMAP24XX_GPIO_IRQENABLE1,
	.irqenable2 =		OMAP24XX_GPIO_IRQENABLE2,
	.set_irqenable =	OMAP24XX_GPIO_SETIRQENABLE1,
	.clr_irqenable =	OMAP24XX_GPIO_CLEARIRQENABLE1,
	.debounce =		OMAP24XX_GPIO_DEBOUNCE_VAL,
	.debounce_en =		OMAP24XX_GPIO_DEBOUNCE_EN,
	.ctrl =			OMAP24XX_GPIO_CTRL,
	.wkup_en =		OMAP24XX_GPIO_WAKE_EN,
	.leveldetect0 =		OMAP24XX_GPIO_LEVELDETECT0,
	.leveldetect1 =		OMAP24XX_GPIO_LEVELDETECT1,
	.risingdetect =		OMAP24XX_GPIO_RISINGDETECT,
	.fallingdetect =	OMAP24XX_GPIO_FALLINGDETECT,
};

static struct omap_gpio_reg_offs omap4_gpio_regs = {
	.revision =		OMAP4_GPIO_REVISION,
	.direction =		OMAP4_GPIO_OE,
	.datain =		OMAP4_GPIO_DATAIN,
	.dataout =		OMAP4_GPIO_DATAOUT,
	.set_dataout =		OMAP4_GPIO_SETDATAOUT,
	.clr_dataout =		OMAP4_GPIO_CLEARDATAOUT,
	.irqstatus =		OMAP4_GPIO_IRQSTATUS0,
	.irqstatus2 =		OMAP4_GPIO_IRQSTATUS1,
	.irqenable =		OMAP4_GPIO_IRQSTATUSSET0,
	.irqenable2 =		OMAP4_GPIO_IRQSTATUSSET1,
	.set_irqenable =	OMAP4_GPIO_IRQSTATUSSET0,
	.clr_irqenable =	OMAP4_GPIO_IRQSTATUSCLR0,
	.debounce =		OMAP4_GPIO_DEBOUNCINGTIME,
	.debounce_en =		OMAP4_GPIO_DEBOUNCENABLE,
	.ctrl =			OMAP4_GPIO_CTRL,
	.wkup_en =		OMAP4_GPIO_IRQWAKEN0,
	.leveldetect0 =		OMAP4_GPIO_LEVELDETECT0,
	.leveldetect1 =		OMAP4_GPIO_LEVELDETECT1,
	.risingdetect =		OMAP4_GPIO_RISINGDETECT,
	.fallingdetect =	OMAP4_GPIO_FALLINGDETECT,
};

1478
static const struct omap_gpio_platform_data omap2_pdata = {
1479 1480 1481 1482 1483
	.regs = &omap2_gpio_regs,
	.bank_width = 32,
	.dbck_flag = false,
};

1484
static const struct omap_gpio_platform_data omap3_pdata = {
1485 1486 1487 1488 1489
	.regs = &omap2_gpio_regs,
	.bank_width = 32,
	.dbck_flag = true,
};

1490
static const struct omap_gpio_platform_data omap4_pdata = {
1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513
	.regs = &omap4_gpio_regs,
	.bank_width = 32,
	.dbck_flag = true,
};

static const struct of_device_id omap_gpio_match[] = {
	{
		.compatible = "ti,omap4-gpio",
		.data = &omap4_pdata,
	},
	{
		.compatible = "ti,omap3-gpio",
		.data = &omap3_pdata,
	},
	{
		.compatible = "ti,omap2-gpio",
		.data = &omap2_pdata,
	},
	{ },
};
MODULE_DEVICE_TABLE(of, omap_gpio_match);
#endif

1514 1515 1516 1517
static struct platform_driver omap_gpio_driver = {
	.probe		= omap_gpio_probe,
	.driver		= {
		.name	= "omap_gpio",
1518
		.pm	= &gpio_pm_ops,
1519
		.of_match_table = of_match_ptr(omap_gpio_match),
1520 1521 1522
	},
};

1523
/*
1524 1525 1526
 * gpio driver register needs to be done before
 * machine_init functions access gpio APIs.
 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1527
 */
1528
static int __init omap_gpio_drv_reg(void)
1529
{
1530
	return platform_driver_register(&omap_gpio_driver);
1531
}
1532
postcore_initcall(omap_gpio_drv_reg);