gpio-omap.c 35.7 KB
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/*
 * Support functions for OMAP GPIO
 *
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 * Copyright (C) 2003-2005 Nokia Corporation
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 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
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 *
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 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
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 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
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#include <linux/syscore_ops.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
#include <linux/pm_runtime.h>
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#include <linux/pm.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <mach/irqs.h>
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#include <asm/gpio.h>
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#include <asm/mach/irq.h>

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#define OFF_MODE	1

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static LIST_HEAD(omap_gpio_list);

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struct gpio_regs {
	u32 irqenable1;
	u32 irqenable2;
	u32 wake_en;
	u32 ctrl;
	u32 oe;
	u32 leveldetect0;
	u32 leveldetect1;
	u32 risingdetect;
	u32 fallingdetect;
	u32 dataout;
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	u32 debounce;
	u32 debounce_en;
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};

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struct gpio_bank {
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	struct list_head node;
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	unsigned long pbase;
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	void __iomem *base;
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	u16 irq;
	u16 virtual_irq_start;
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	u32 suspend_wakeup;
	u32 saved_wakeup;
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	u32 non_wakeup_gpios;
	u32 enabled_non_wakeup_gpios;
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	struct gpio_regs context;
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	u32 saved_datain;
	u32 saved_fallingdetect;
	u32 saved_risingdetect;
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	u32 level_mask;
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	u32 toggle_mask;
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	spinlock_t lock;
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	struct gpio_chip chip;
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	struct clk *dbck;
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	u32 mod_usage;
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	u32 dbck_enable_mask;
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	bool dbck_enabled;
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	struct device *dev;
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	bool is_mpuio;
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	bool dbck_flag;
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	bool loses_context;
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	int stride;
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	u32 width;
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	int context_loss_count;
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	u16 id;
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	int power_mode;
	bool workaround_enabled;
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	void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
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	int (*get_context_loss_count)(struct device *dev);
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	struct omap_gpio_reg_offs *regs;
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};

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#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
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#define GPIO_MOD_CTRL_BIT	BIT(0)
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static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
{
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	void __iomem *reg = bank->base;
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	u32 l;

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	reg += bank->regs->direction;
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	l = __raw_readl(reg);
	if (is_input)
		l |= 1 << gpio;
	else
		l &= ~(1 << gpio);
	__raw_writel(l, reg);
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	bank->context.oe = l;
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}

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/* set data out value using dedicate set/clear register */
static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
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{
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	void __iomem *reg = bank->base;
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	u32 l = GPIO_BIT(bank, gpio);
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	if (enable)
		reg += bank->regs->set_dataout;
	else
		reg += bank->regs->clr_dataout;
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	__raw_writel(l, reg);
}

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/* set data out value using mask register */
static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
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{
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	void __iomem *reg = bank->base + bank->regs->dataout;
	u32 gpio_bit = GPIO_BIT(bank, gpio);
	u32 l;
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	l = __raw_readl(reg);
	if (enable)
		l |= gpio_bit;
	else
		l &= ~gpio_bit;
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	__raw_writel(l, reg);
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	bank->context.dataout = l;
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}

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static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
{
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	void __iomem *reg = bank->base + bank->regs->datain;
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	return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
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}
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static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
{
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	void __iomem *reg = bank->base + bank->regs->dataout;
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	return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
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}

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static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
{
	int l = __raw_readl(base + reg);

	if (set) 
		l |= mask;
	else
		l &= ~mask;

	__raw_writel(l, base + reg);
}
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static inline void _gpio_dbck_enable(struct gpio_bank *bank)
{
	if (bank->dbck_enable_mask && !bank->dbck_enabled) {
		clk_enable(bank->dbck);
		bank->dbck_enabled = true;
	}
}

static inline void _gpio_dbck_disable(struct gpio_bank *bank)
{
	if (bank->dbck_enable_mask && bank->dbck_enabled) {
		clk_disable(bank->dbck);
		bank->dbck_enabled = false;
	}
}

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/**
 * _set_gpio_debounce - low level gpio debounce time
 * @bank: the gpio bank we're acting upon
 * @gpio: the gpio number on this @gpio
 * @debounce: debounce time to use
 *
 * OMAP's debounce time is in 31us steps so we need
 * to convert and round up to the closest unit.
 */
static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
		unsigned debounce)
{
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	void __iomem		*reg;
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	u32			val;
	u32			l;

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	if (!bank->dbck_flag)
		return;

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	if (debounce < 32)
		debounce = 0x01;
	else if (debounce > 7936)
		debounce = 0xff;
	else
		debounce = (debounce / 0x1f) - 1;

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	l = GPIO_BIT(bank, gpio);
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	clk_enable(bank->dbck);
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	reg = bank->base + bank->regs->debounce;
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	__raw_writel(debounce, reg);

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	reg = bank->base + bank->regs->debounce_en;
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	val = __raw_readl(reg);

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	if (debounce)
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		val |= l;
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	else
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		val &= ~l;
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	bank->dbck_enable_mask = val;
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	__raw_writel(val, reg);
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	clk_disable(bank->dbck);
	/*
	 * Enable debounce clock per module.
	 * This call is mandatory because in omap_gpio_request() when
	 * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
	 * runtime callbck fails to turn on dbck because dbck_enable_mask
	 * used within _gpio_dbck_enable() is still not initialized at
	 * that point. Therefore we have to enable dbck here.
	 */
	_gpio_dbck_enable(bank);
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	if (bank->dbck_enable_mask) {
		bank->context.debounce = debounce;
		bank->context.debounce_en = val;
	}
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}

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static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
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						int trigger)
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{
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	void __iomem *base = bank->base;
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	u32 gpio_bit = 1 << gpio;

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	_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
		  trigger & IRQ_TYPE_LEVEL_LOW);
	_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
		  trigger & IRQ_TYPE_LEVEL_HIGH);
	_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
		  trigger & IRQ_TYPE_EDGE_RISING);
	_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
		  trigger & IRQ_TYPE_EDGE_FALLING);

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	bank->context.leveldetect0 =
			__raw_readl(bank->base + bank->regs->leveldetect0);
	bank->context.leveldetect1 =
			__raw_readl(bank->base + bank->regs->leveldetect1);
	bank->context.risingdetect =
			__raw_readl(bank->base + bank->regs->risingdetect);
	bank->context.fallingdetect =
			__raw_readl(bank->base + bank->regs->fallingdetect);

	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
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		_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
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		bank->context.wake_en =
			__raw_readl(bank->base + bank->regs->wkup_en);
	}
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	/* This part needs to be executed always for OMAP{34xx, 44xx} */
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	if (!bank->regs->irqctrl) {
		/* On omap24xx proceed only when valid GPIO bit is set */
		if (bank->non_wakeup_gpios) {
			if (!(bank->non_wakeup_gpios & gpio_bit))
				goto exit;
		}

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		/*
		 * Log the edge gpio and manually trigger the IRQ
		 * after resume if the input level changes
		 * to avoid irq lost during PER RET/OFF mode
		 * Applies for omap2 non-wakeup gpio and all omap3 gpios
		 */
		if (trigger & IRQ_TYPE_EDGE_BOTH)
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			bank->enabled_non_wakeup_gpios |= gpio_bit;
		else
			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
	}
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exit:
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	bank->level_mask =
		__raw_readl(bank->base + bank->regs->leveldetect0) |
		__raw_readl(bank->base + bank->regs->leveldetect1);
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}

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#ifdef CONFIG_ARCH_OMAP1
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/*
 * This only applies to chips that can't do both rising and falling edge
 * detection at once.  For all other chips, this function is a noop.
 */
static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
{
	void __iomem *reg = bank->base;
	u32 l = 0;

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	if (!bank->regs->irqctrl)
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		return;
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	reg += bank->regs->irqctrl;
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	l = __raw_readl(reg);
	if ((l >> gpio) & 1)
		l &= ~(1 << gpio);
	else
		l |= 1 << gpio;

	__raw_writel(l, reg);
}
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#else
static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
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#endif
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static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
{
	void __iomem *reg = bank->base;
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	void __iomem *base = bank->base;
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	u32 l = 0;
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	if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
		set_gpio_trigger(bank, gpio, trigger);
	} else if (bank->regs->irqctrl) {
		reg += bank->regs->irqctrl;

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		l = __raw_readl(reg);
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		if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
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			bank->toggle_mask |= 1 << gpio;
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		if (trigger & IRQ_TYPE_EDGE_RISING)
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			l |= 1 << gpio;
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		else if (trigger & IRQ_TYPE_EDGE_FALLING)
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			l &= ~(1 << gpio);
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		else
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			return -EINVAL;

		__raw_writel(l, reg);
	} else if (bank->regs->edgectrl1) {
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		if (gpio & 0x08)
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			reg += bank->regs->edgectrl2;
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		else
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			reg += bank->regs->edgectrl1;

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		gpio &= 0x07;
		l = __raw_readl(reg);
		l &= ~(3 << (gpio << 1));
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		if (trigger & IRQ_TYPE_EDGE_RISING)
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			l |= 2 << (gpio << 1);
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		if (trigger & IRQ_TYPE_EDGE_FALLING)
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			l |= 1 << (gpio << 1);
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		/* Enable wake-up during idle for dynamic tick */
		_gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
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		bank->context.wake_en =
			__raw_readl(bank->base + bank->regs->wkup_en);
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		__raw_writel(l, reg);
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	}
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	return 0;
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}

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static int gpio_irq_type(struct irq_data *d, unsigned type)
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{
	struct gpio_bank *bank;
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	unsigned gpio;
	int retval;
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	unsigned long flags;
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	if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
		gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
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	else
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		gpio = d->irq - IH_GPIO_BASE;
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	if (type & ~IRQ_TYPE_SENSE_MASK)
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		return -EINVAL;
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	bank = irq_data_get_irq_chip_data(d);

	if (!bank->regs->leveldetect0 &&
		(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
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		return -EINVAL;

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	spin_lock_irqsave(&bank->lock, flags);
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	retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
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	spin_unlock_irqrestore(&bank->lock, flags);
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	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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		__irq_set_handler_locked(d->irq, handle_level_irq);
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	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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		__irq_set_handler_locked(d->irq, handle_edge_irq);
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	return retval;
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}

static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
{
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	void __iomem *reg = bank->base;
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	reg += bank->regs->irqstatus;
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	__raw_writel(gpio_mask, reg);
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	/* Workaround for clearing DSP GPIO interrupts to allow retention */
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	if (bank->regs->irqstatus2) {
		reg = bank->base + bank->regs->irqstatus2;
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		__raw_writel(gpio_mask, reg);
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	}
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	/* Flush posted write for the irq status to avoid spurious interrupts */
	__raw_readl(reg);
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}

static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
{
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	_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
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}

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static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
{
	void __iomem *reg = bank->base;
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	u32 l;
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	u32 mask = (1 << bank->width) - 1;
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	reg += bank->regs->irqenable;
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	l = __raw_readl(reg);
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	if (bank->regs->irqenable_inv)
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		l = ~l;
	l &= mask;
	return l;
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}

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static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
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{
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	void __iomem *reg = bank->base;
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	u32 l;

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	if (bank->regs->set_irqenable) {
		reg += bank->regs->set_irqenable;
		l = gpio_mask;
	} else {
		reg += bank->regs->irqenable;
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		l = __raw_readl(reg);
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		if (bank->regs->irqenable_inv)
			l &= ~gpio_mask;
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		else
			l |= gpio_mask;
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	}

	__raw_writel(l, reg);
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	bank->context.irqenable1 = l;
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}

static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
{
	void __iomem *reg = bank->base;
	u32 l;

	if (bank->regs->clr_irqenable) {
		reg += bank->regs->clr_irqenable;
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		l = gpio_mask;
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	} else {
		reg += bank->regs->irqenable;
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		l = __raw_readl(reg);
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		if (bank->regs->irqenable_inv)
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			l |= gpio_mask;
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		else
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			l &= ~gpio_mask;
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	}
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	__raw_writel(l, reg);
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	bank->context.irqenable1 = l;
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}

static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
{
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	_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
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}

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/*
 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
 * 1510 does not seem to have a wake-up register. If JTAG is connected
 * to the target, system will wake up always on GPIO events. While
 * system is running all registered GPIO interrupts need to have wake-up
 * enabled. When system is suspended, only selected GPIO interrupts need
 * to have wake-up enabled.
 */
static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
{
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	u32 gpio_bit = GPIO_BIT(bank, gpio);
	unsigned long flags;
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	if (bank->non_wakeup_gpios & gpio_bit) {
		dev_err(bank->dev, 
			"Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
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		return -EINVAL;
	}
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	spin_lock_irqsave(&bank->lock, flags);
	if (enable)
		bank->suspend_wakeup |= gpio_bit;
	else
		bank->suspend_wakeup &= ~gpio_bit;

	spin_unlock_irqrestore(&bank->lock, flags);

	return 0;
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}

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static void _reset_gpio(struct gpio_bank *bank, int gpio)
{
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	_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
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	_set_gpio_irqenable(bank, gpio, 0);
	_clear_gpio_irqstatus(bank, gpio);
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	_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
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}

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/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
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static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
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{
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	unsigned int gpio = d->irq - IH_GPIO_BASE;
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	struct gpio_bank *bank;
	int retval;

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	bank = irq_data_get_irq_chip_data(d);
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	retval = _set_gpio_wakeup(bank, gpio, enable);
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	return retval;
}

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static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
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	unsigned long flags;
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	/*
	 * If this is the first gpio_request for the bank,
	 * enable the bank module.
	 */
	if (!bank->mod_usage)
		pm_runtime_get_sync(bank->dev);
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	spin_lock_irqsave(&bank->lock, flags);
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	/* Set trigger to none. You need to enable the desired trigger with
	 * request_irq() or set_irq_type().
	 */
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	_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
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	if (bank->regs->pinctrl) {
		void __iomem *reg = bank->base + bank->regs->pinctrl;
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		/* Claim the pin for MPU */
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		__raw_writel(__raw_readl(reg) | (1 << offset), reg);
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	}
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	if (bank->regs->ctrl && !bank->mod_usage) {
		void __iomem *reg = bank->base + bank->regs->ctrl;
		u32 ctrl;

		ctrl = __raw_readl(reg);
		/* Module is enabled, clocks are not gated */
		ctrl &= ~GPIO_MOD_CTRL_BIT;
		__raw_writel(ctrl, reg);
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		bank->context.ctrl = ctrl;
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	}
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	bank->mod_usage |= 1 << offset;

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	spin_unlock_irqrestore(&bank->lock, flags);
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	return 0;
}

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static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
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{
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	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
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	void __iomem *base = bank->base;
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	unsigned long flags;
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	spin_lock_irqsave(&bank->lock, flags);
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	if (bank->regs->wkup_en) {
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		/* Disable wake-up during idle for dynamic tick */
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		_gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
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		bank->context.wake_en =
			__raw_readl(bank->base + bank->regs->wkup_en);
	}
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	bank->mod_usage &= ~(1 << offset);

	if (bank->regs->ctrl && !bank->mod_usage) {
		void __iomem *reg = bank->base + bank->regs->ctrl;
		u32 ctrl;

		ctrl = __raw_readl(reg);
		/* Module is disabled, clocks are gated */
		ctrl |= GPIO_MOD_CTRL_BIT;
		__raw_writel(ctrl, reg);
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		bank->context.ctrl = ctrl;
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	}
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	_reset_gpio(bank, bank->chip.base + offset);
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	spin_unlock_irqrestore(&bank->lock, flags);
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	/*
	 * If this is the last gpio to be freed in the bank,
	 * disable the bank module.
	 */
	if (!bank->mod_usage)
		pm_runtime_put(bank->dev);
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}

/*
 * We need to unmask the GPIO bank interrupt as soon as possible to
 * avoid missing GPIO interrupts for other lines in the bank.
 * Then we need to mask-read-clear-unmask the triggered GPIO lines
 * in the bank to avoid missing nested interrupts for a GPIO line.
 * If we wait to unmask individual GPIO lines in the bank after the
 * line's interrupt handler has been run, we may miss some nested
 * interrupts.
 */
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static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
627
{
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	void __iomem *isr_reg = NULL;
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	u32 isr;
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	unsigned int gpio_irq, gpio_index;
631
	struct gpio_bank *bank;
632 633
	u32 retrigger = 0;
	int unmasked = 0;
634
	struct irq_chip *chip = irq_desc_get_chip(desc);
635

636
	chained_irq_enter(chip, desc);
637

T
Thomas Gleixner 已提交
638
	bank = irq_get_handler_data(irq);
639
	isr_reg = bank->base + bank->regs->irqstatus;
640
	pm_runtime_get_sync(bank->dev);
641 642 643 644

	if (WARN_ON(!isr_reg))
		goto exit;

645
	while(1) {
646
		u32 isr_saved, level_mask = 0;
647
		u32 enabled;
648

649 650
		enabled = _get_gpio_irqbank_mask(bank);
		isr_saved = isr = __raw_readl(isr_reg) & enabled;
651

652
		if (bank->level_mask)
653
			level_mask = bank->level_mask & enabled;
654 655 656 657

		/* clear edge sensitive interrupts before handler(s) are
		called so that we don't miss any interrupt occurred while
		executing them */
658
		_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
659
		_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
660
		_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
661 662 663

		/* if there is only edge sensitive GPIO pin interrupts
		configured, we could unmask GPIO bank interrupt immediately */
664 665
		if (!level_mask && !unmasked) {
			unmasked = 1;
666
			chained_irq_exit(chip, desc);
667
		}
668

669 670
		isr |= retrigger;
		retrigger = 0;
671 672 673 674 675
		if (!isr)
			break;

		gpio_irq = bank->virtual_irq_start;
		for (; isr != 0; isr >>= 1, gpio_irq++) {
676
			gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
677

678 679
			if (!(isr & 1))
				continue;
680

681 682 683 684 685 686 687 688 689 690
			/*
			 * Some chips can't respond to both rising and falling
			 * at the same time.  If this irq was requested with
			 * both flags, we need to flip the ICR data for the IRQ
			 * to respond to the IRQ for the opposite direction.
			 * This will be indicated in the bank toggle_mask.
			 */
			if (bank->toggle_mask & (1 << gpio_index))
				_toggle_gpio_edge_triggering(bank, gpio_index);

691
			generic_handle_irq(gpio_irq);
692
		}
693
	}
694 695 696 697
	/* if bank has any level sensitive GPIO pin interrupt
	configured, we must unmask the bank interrupt only after
	handler(s) are executed in order to avoid spurious bank
	interrupt */
698
exit:
699
	if (!unmasked)
700
		chained_irq_exit(chip, desc);
701
	pm_runtime_put(bank->dev);
702 703
}

704
static void gpio_irq_shutdown(struct irq_data *d)
705
{
706 707
	unsigned int gpio = d->irq - IH_GPIO_BASE;
	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
708
	unsigned long flags;
709

710
	spin_lock_irqsave(&bank->lock, flags);
711
	_reset_gpio(bank, gpio);
712
	spin_unlock_irqrestore(&bank->lock, flags);
713 714
}

715
static void gpio_ack_irq(struct irq_data *d)
716
{
717 718
	unsigned int gpio = d->irq - IH_GPIO_BASE;
	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
719 720 721 722

	_clear_gpio_irqstatus(bank, gpio);
}

723
static void gpio_mask_irq(struct irq_data *d)
724
{
725 726
	unsigned int gpio = d->irq - IH_GPIO_BASE;
	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
727
	unsigned long flags;
728

729
	spin_lock_irqsave(&bank->lock, flags);
730
	_set_gpio_irqenable(bank, gpio, 0);
731
	_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
732
	spin_unlock_irqrestore(&bank->lock, flags);
733 734
}

735
static void gpio_unmask_irq(struct irq_data *d)
736
{
737 738
	unsigned int gpio = d->irq - IH_GPIO_BASE;
	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
739
	unsigned int irq_mask = GPIO_BIT(bank, gpio);
740
	u32 trigger = irqd_get_trigger_type(d);
741
	unsigned long flags;
742

743
	spin_lock_irqsave(&bank->lock, flags);
744
	if (trigger)
745
		_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
746 747 748 749 750 751 752

	/* For level-triggered GPIOs, the clearing must be done after
	 * the HW source is cleared, thus after the handler has run */
	if (bank->level_mask & irq_mask) {
		_set_gpio_irqenable(bank, gpio, 0);
		_clear_gpio_irqstatus(bank, gpio);
	}
753

K
Kevin Hilman 已提交
754
	_set_gpio_irqenable(bank, gpio, 1);
755
	spin_unlock_irqrestore(&bank->lock, flags);
756 757
}

758 759
static struct irq_chip gpio_irq_chip = {
	.name		= "GPIO",
760 761 762 763 764 765
	.irq_shutdown	= gpio_irq_shutdown,
	.irq_ack	= gpio_ack_irq,
	.irq_mask	= gpio_mask_irq,
	.irq_unmask	= gpio_unmask_irq,
	.irq_set_type	= gpio_irq_type,
	.irq_set_wake	= gpio_wake_enable,
766 767 768 769
};

/*---------------------------------------------------------------------*/

770
static int omap_mpuio_suspend_noirq(struct device *dev)
D
David Brownell 已提交
771
{
772
	struct platform_device *pdev = to_platform_device(dev);
D
David Brownell 已提交
773
	struct gpio_bank	*bank = platform_get_drvdata(pdev);
774 775
	void __iomem		*mask_reg = bank->base +
					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
D
David Brownell 已提交
776
	unsigned long		flags;
D
David Brownell 已提交
777

D
David Brownell 已提交
778
	spin_lock_irqsave(&bank->lock, flags);
D
David Brownell 已提交
779 780
	bank->saved_wakeup = __raw_readl(mask_reg);
	__raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
D
David Brownell 已提交
781
	spin_unlock_irqrestore(&bank->lock, flags);
D
David Brownell 已提交
782 783 784 785

	return 0;
}

786
static int omap_mpuio_resume_noirq(struct device *dev)
D
David Brownell 已提交
787
{
788
	struct platform_device *pdev = to_platform_device(dev);
D
David Brownell 已提交
789
	struct gpio_bank	*bank = platform_get_drvdata(pdev);
790 791
	void __iomem		*mask_reg = bank->base +
					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
D
David Brownell 已提交
792
	unsigned long		flags;
D
David Brownell 已提交
793

D
David Brownell 已提交
794
	spin_lock_irqsave(&bank->lock, flags);
D
David Brownell 已提交
795
	__raw_writel(bank->saved_wakeup, mask_reg);
D
David Brownell 已提交
796
	spin_unlock_irqrestore(&bank->lock, flags);
D
David Brownell 已提交
797 798 799 800

	return 0;
}

801
static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
802 803 804 805
	.suspend_noirq = omap_mpuio_suspend_noirq,
	.resume_noirq = omap_mpuio_resume_noirq,
};

806
/* use platform_driver for this. */
D
David Brownell 已提交
807 808 809
static struct platform_driver omap_mpuio_driver = {
	.driver		= {
		.name	= "mpuio",
810
		.pm	= &omap_mpuio_dev_pm_ops,
D
David Brownell 已提交
811 812 813 814 815 816 817 818 819 820 821 822
	},
};

static struct platform_device omap_mpuio_device = {
	.name		= "mpuio",
	.id		= -1,
	.dev = {
		.driver = &omap_mpuio_driver.driver,
	}
	/* could list the /proc/iomem resources */
};

823
static inline void mpuio_init(struct gpio_bank *bank)
D
David Brownell 已提交
824
{
825
	platform_set_drvdata(&omap_mpuio_device, bank);
826

D
David Brownell 已提交
827 828 829 830
	if (platform_driver_register(&omap_mpuio_driver) == 0)
		(void) platform_device_register(&omap_mpuio_device);
}

831
/*---------------------------------------------------------------------*/
832

D
David Brownell 已提交
833 834 835 836 837 838 839 840 841 842 843 844
static int gpio_input(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_bank *bank;
	unsigned long flags;

	bank = container_of(chip, struct gpio_bank, chip);
	spin_lock_irqsave(&bank->lock, flags);
	_set_gpio_direction(bank, offset, 1);
	spin_unlock_irqrestore(&bank->lock, flags);
	return 0;
}

845 846
static int gpio_is_input(struct gpio_bank *bank, int mask)
{
847
	void __iomem *reg = bank->base + bank->regs->direction;
848 849 850 851

	return __raw_readl(reg) & mask;
}

D
David Brownell 已提交
852 853
static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
854 855 856 857 858 859
	struct gpio_bank *bank;
	void __iomem *reg;
	int gpio;
	u32 mask;

	gpio = chip->base + offset;
C
Charulatha V 已提交
860
	bank = container_of(chip, struct gpio_bank, chip);
861
	reg = bank->base;
862
	mask = GPIO_BIT(bank, gpio);
863 864 865 866 867

	if (gpio_is_input(bank, mask))
		return _get_gpio_datain(bank, gpio);
	else
		return _get_gpio_dataout(bank, gpio);
D
David Brownell 已提交
868 869 870 871 872 873 874 875 876
}

static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
{
	struct gpio_bank *bank;
	unsigned long flags;

	bank = container_of(chip, struct gpio_bank, chip);
	spin_lock_irqsave(&bank->lock, flags);
877
	bank->set_dataout(bank, offset, value);
D
David Brownell 已提交
878 879 880 881 882
	_set_gpio_direction(bank, offset, 0);
	spin_unlock_irqrestore(&bank->lock, flags);
	return 0;
}

883 884 885 886 887 888 889
static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
		unsigned debounce)
{
	struct gpio_bank *bank;
	unsigned long flags;

	bank = container_of(chip, struct gpio_bank, chip);
890 891 892 893 894 895 896

	if (!bank->dbck) {
		bank->dbck = clk_get(bank->dev, "dbclk");
		if (IS_ERR(bank->dbck))
			dev_err(bank->dev, "Could not get gpio dbck\n");
	}

897 898 899 900 901 902 903
	spin_lock_irqsave(&bank->lock, flags);
	_set_gpio_debounce(bank, offset, debounce);
	spin_unlock_irqrestore(&bank->lock, flags);

	return 0;
}

D
David Brownell 已提交
904 905 906 907 908 909 910
static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct gpio_bank *bank;
	unsigned long flags;

	bank = container_of(chip, struct gpio_bank, chip);
	spin_lock_irqsave(&bank->lock, flags);
911
	bank->set_dataout(bank, offset, value);
D
David Brownell 已提交
912 913 914
	spin_unlock_irqrestore(&bank->lock, flags);
}

915 916 917 918 919 920 921 922
static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_bank *bank;

	bank = container_of(chip, struct gpio_bank, chip);
	return bank->virtual_irq_start + offset;
}

D
David Brownell 已提交
923 924
/*---------------------------------------------------------------------*/

925
static void __init omap_gpio_show_rev(struct gpio_bank *bank)
T
Tony Lindgren 已提交
926
{
927
	static bool called;
T
Tony Lindgren 已提交
928 929
	u32 rev;

930
	if (called || bank->regs->revision == USHRT_MAX)
T
Tony Lindgren 已提交
931 932
		return;

933 934
	rev = __raw_readw(bank->base + bank->regs->revision);
	pr_info("OMAP GPIO hardware version %d.%d\n",
T
Tony Lindgren 已提交
935
		(rev >> 4) & 0x0f, rev & 0x0f);
936 937

	called = true;
T
Tony Lindgren 已提交
938 939
}

940 941 942 943 944
/* This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

945
static void omap_gpio_mod_init(struct gpio_bank *bank)
946
{
947 948
	void __iomem *base = bank->base;
	u32 l = 0xffffffff;
949

950 951 952
	if (bank->width == 16)
		l = 0xffff;

953
	if (bank->is_mpuio) {
954 955
		__raw_writel(l, bank->base + bank->regs->irqenable);
		return;
956
	}
957 958 959 960 961 962 963 964 965

	_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
	_gpio_rmw(base, bank->regs->irqstatus, l,
					bank->regs->irqenable_inv == false);
	_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0);
	_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0);
	if (bank->regs->debounce_en)
		_gpio_rmw(base, bank->regs->debounce_en, 0, 1);

966 967
	/* Save OE default value (0xffffffff) in the context */
	bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
968 969 970
	 /* Initialize interface clk ungated, module enabled */
	if (bank->regs->ctrl)
		_gpio_rmw(base, bank->regs->ctrl, 0, 1);
971 972
}

973 974 975 976 977 978 979 980 981
static __init void
omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
		    unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
				    handle_simple_irq);
982 983 984 985 986
	if (!gc) {
		dev_err(bank->dev, "Memory alloc failed for gc\n");
		return;
	}

987 988 989 990 991 992
	ct = gc->chip_types;

	/* NOTE: No ack required, reading IRQ status clears it. */
	ct->chip.irq_mask = irq_gc_mask_set_bit;
	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
	ct->chip.irq_set_type = gpio_irq_type;
993 994

	if (bank->regs->wkup_en)
995 996 997 998 999 1000 1001
		ct->chip.irq_set_wake = gpio_wake_enable,

	ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

1002
static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1003
{
1004
	int j;
1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018
	static int gpio;

	/*
	 * REVISIT eventually switch from OMAP-specific gpio structs
	 * over to the generic ones
	 */
	bank->chip.request = omap_gpio_request;
	bank->chip.free = omap_gpio_free;
	bank->chip.direction_input = gpio_input;
	bank->chip.get = gpio_get;
	bank->chip.direction_output = gpio_output;
	bank->chip.set_debounce = gpio_debounce;
	bank->chip.set = gpio_set;
	bank->chip.to_irq = gpio_2irq;
1019
	if (bank->is_mpuio) {
1020
		bank->chip.label = "mpuio";
1021 1022
		if (bank->regs->wkup_en)
			bank->chip.dev = &omap_mpuio_device.dev;
1023 1024 1025 1026
		bank->chip.base = OMAP_MPUIO(0);
	} else {
		bank->chip.label = "gpio";
		bank->chip.base = gpio;
1027
		gpio += bank->width;
1028
	}
1029
	bank->chip.ngpio = bank->width;
1030 1031 1032 1033

	gpiochip_add(&bank->chip);

	for (j = bank->virtual_irq_start;
1034
		     j < bank->virtual_irq_start + bank->width; j++) {
1035
		irq_set_lockdep_class(j, &gpio_lock_class);
T
Thomas Gleixner 已提交
1036
		irq_set_chip_data(j, bank);
1037
		if (bank->is_mpuio) {
1038 1039
			omap_mpuio_alloc_gc(bank, j, bank->width);
		} else {
T
Thomas Gleixner 已提交
1040
			irq_set_chip(j, &gpio_irq_chip);
1041 1042 1043
			irq_set_handler(j, handle_simple_irq);
			set_irq_flags(j, IRQF_VALID);
		}
1044
	}
T
Thomas Gleixner 已提交
1045 1046
	irq_set_chained_handler(bank->irq, gpio_irq_handler);
	irq_set_handler_data(bank->irq, bank);
1047 1048
}

1049
static int __devinit omap_gpio_probe(struct platform_device *pdev)
1050
{
1051 1052
	struct omap_gpio_platform_data *pdata;
	struct resource *res;
1053
	struct gpio_bank *bank;
1054
	int ret = 0;
1055

1056 1057 1058
	if (!pdev->dev.platform_data) {
		ret = -EINVAL;
		goto err_exit;
1059 1060
	}

1061 1062 1063 1064 1065 1066
	bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL);
	if (!bank) {
		dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
		ret = -ENOMEM;
		goto err_exit;
	}
1067

1068 1069
	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (unlikely(!res)) {
1070 1071 1072 1073
		dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n",
				pdev->id);
		ret = -ENODEV;
		goto err_free;
1074
	}
1075

1076
	bank->irq = res->start;
1077 1078 1079
	bank->id = pdev->id;

	pdata = pdev->dev.platform_data;
1080 1081 1082
	bank->virtual_irq_start = pdata->virtual_irq_start;
	bank->dev = &pdev->dev;
	bank->dbck_flag = pdata->dbck_flag;
1083
	bank->stride = pdata->bank_stride;
1084
	bank->width = pdata->bank_width;
1085
	bank->is_mpuio = pdata->is_mpuio;
1086
	bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1087
	bank->loses_context = pdata->loses_context;
1088
	bank->get_context_loss_count = pdata->get_context_loss_count;
1089 1090 1091 1092 1093 1094
	bank->regs = pdata->regs;

	if (bank->regs->set_dataout && bank->regs->clr_dataout)
		bank->set_dataout = _set_gpio_dataout_reg;
	else
		bank->set_dataout = _set_gpio_dataout_mask;
T
Tony Lindgren 已提交
1095

1096
	spin_lock_init(&bank->lock);
T
Tony Lindgren 已提交
1097

1098 1099 1100
	/* Static mapping, never released */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(!res)) {
1101 1102 1103 1104
		dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n",
				pdev->id);
		ret = -ENODEV;
		goto err_free;
1105
	}
1106

1107 1108
	bank->base = ioremap(res->start, resource_size(res));
	if (!bank->base) {
1109 1110 1111 1112
		dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n",
				pdev->id);
		ret = -ENOMEM;
		goto err_free;
1113 1114
	}

1115 1116
	platform_set_drvdata(pdev, bank);

1117
	pm_runtime_enable(bank->dev);
1118
	pm_runtime_irq_safe(bank->dev);
1119 1120
	pm_runtime_get_sync(bank->dev);

1121
	if (bank->is_mpuio)
1122 1123
		mpuio_init(bank);

1124
	omap_gpio_mod_init(bank);
1125
	omap_gpio_chip_init(bank);
1126
	omap_gpio_show_rev(bank);
T
Tony Lindgren 已提交
1127

1128 1129
	pm_runtime_put(bank->dev);

1130
	list_add_tail(&bank->node, &omap_gpio_list);
1131

1132 1133 1134 1135 1136 1137
	return ret;

err_free:
	kfree(bank);
err_exit:
	return ret;
1138 1139
}

1140 1141 1142 1143
#ifdef CONFIG_ARCH_OMAP2PLUS

#if defined(CONFIG_PM_SLEEP)
static int omap_gpio_suspend(struct device *dev)
1144
{
1145 1146 1147 1148 1149
	struct platform_device *pdev = to_platform_device(dev);
	struct gpio_bank *bank = platform_get_drvdata(pdev);
	void __iomem *base = bank->base;
	void __iomem *wakeup_enable;
	unsigned long flags;
1150

1151 1152
	if (!bank->mod_usage || !bank->loses_context)
		return 0;
1153

1154 1155
	if (!bank->regs->wkup_en || !bank->suspend_wakeup)
		return 0;
1156

1157
	wakeup_enable = bank->base + bank->regs->wkup_en;
1158

1159 1160 1161 1162 1163
	spin_lock_irqsave(&bank->lock, flags);
	bank->saved_wakeup = __raw_readl(wakeup_enable);
	_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
	_gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
	spin_unlock_irqrestore(&bank->lock, flags);
1164 1165 1166 1167

	return 0;
}

1168
static int omap_gpio_resume(struct device *dev)
1169
{
1170 1171 1172 1173
	struct platform_device *pdev = to_platform_device(dev);
	struct gpio_bank *bank = platform_get_drvdata(pdev);
	void __iomem *base = bank->base;
	unsigned long flags;
1174

1175 1176
	if (!bank->mod_usage || !bank->loses_context)
		return 0;
1177

1178 1179
	if (!bank->regs->wkup_en || !bank->saved_wakeup)
		return 0;
1180

1181 1182 1183 1184
	spin_lock_irqsave(&bank->lock, flags);
	_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
	_gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
	spin_unlock_irqrestore(&bank->lock, flags);
1185

1186 1187 1188
	return 0;
}
#endif /* CONFIG_PM_SLEEP */
1189

1190
#if defined(CONFIG_PM_RUNTIME)
1191
static void omap_gpio_restore_context(struct gpio_bank *bank);
1192

1193
static int omap_gpio_runtime_suspend(struct device *dev)
1194
{
1195 1196 1197 1198
	struct platform_device *pdev = to_platform_device(dev);
	struct gpio_bank *bank = platform_get_drvdata(pdev);
	u32 l1 = 0, l2 = 0;
	unsigned long flags;
1199

1200 1201 1202
	spin_lock_irqsave(&bank->lock, flags);
	if (bank->power_mode != OFF_MODE) {
		bank->power_mode = 0;
1203
		goto update_gpio_context_count;
1204 1205 1206 1207 1208 1209 1210
	}
	/*
	 * If going to OFF, remove triggering for all
	 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
	 * generated.  See OMAP2420 Errata item 1.101.
	 */
	if (!(bank->enabled_non_wakeup_gpios))
1211
		goto update_gpio_context_count;
1212

1213 1214 1215 1216
	bank->saved_datain = __raw_readl(bank->base +
						bank->regs->datain);
	l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
	l2 = __raw_readl(bank->base + bank->regs->risingdetect);
1217

1218 1219 1220 1221
	bank->saved_fallingdetect = l1;
	bank->saved_risingdetect = l2;
	l1 &= ~bank->enabled_non_wakeup_gpios;
	l2 &= ~bank->enabled_non_wakeup_gpios;
1222

1223 1224
	__raw_writel(l1, bank->base + bank->regs->fallingdetect);
	__raw_writel(l2, bank->base + bank->regs->risingdetect);
1225

1226
	bank->workaround_enabled = true;
1227

1228
update_gpio_context_count:
1229 1230
	if (bank->get_context_loss_count)
		bank->context_loss_count =
1231 1232
				bank->get_context_loss_count(bank->dev);

1233
	_gpio_dbck_disable(bank);
1234
	spin_unlock_irqrestore(&bank->lock, flags);
1235

1236
	return 0;
1237 1238
}

1239
static int omap_gpio_runtime_resume(struct device *dev)
1240
{
1241 1242 1243 1244 1245
	struct platform_device *pdev = to_platform_device(dev);
	struct gpio_bank *bank = platform_get_drvdata(pdev);
	int context_lost_cnt_after;
	u32 l = 0, gen, gen0, gen1;
	unsigned long flags;
1246

1247
	spin_lock_irqsave(&bank->lock, flags);
1248
	_gpio_dbck_enable(bank);
1249 1250 1251 1252
	if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
		spin_unlock_irqrestore(&bank->lock, flags);
		return 0;
	}
1253

1254 1255 1256 1257 1258 1259 1260 1261 1262
	if (bank->get_context_loss_count) {
		context_lost_cnt_after =
			bank->get_context_loss_count(bank->dev);
		if (context_lost_cnt_after != bank->context_loss_count ||
						!context_lost_cnt_after) {
			omap_gpio_restore_context(bank);
		} else {
			spin_unlock_irqrestore(&bank->lock, flags);
			return 0;
1263
		}
1264
	}
1265

1266 1267 1268 1269 1270
	__raw_writel(bank->saved_fallingdetect,
			bank->base + bank->regs->fallingdetect);
	__raw_writel(bank->saved_risingdetect,
			bank->base + bank->regs->risingdetect);
	l = __raw_readl(bank->base + bank->regs->datain);
1271

1272 1273 1274 1275 1276 1277 1278 1279
	/*
	 * Check if any of the non-wakeup interrupt GPIOs have changed
	 * state.  If so, generate an IRQ by software.  This is
	 * horribly racy, but it's the best we can do to work around
	 * this silicon bug.
	 */
	l ^= bank->saved_datain;
	l &= bank->enabled_non_wakeup_gpios;
1280

1281 1282 1283 1284 1285 1286
	/*
	 * No need to generate IRQs for the rising edge for gpio IRQs
	 * configured with falling edge only; and vice versa.
	 */
	gen0 = l & bank->saved_fallingdetect;
	gen0 &= bank->saved_datain;
1287

1288 1289
	gen1 = l & bank->saved_risingdetect;
	gen1 &= ~(bank->saved_datain);
1290

1291 1292 1293 1294
	/* FIXME: Consider GPIO IRQs with level detections properly! */
	gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect));
	/* Consider all GPIO IRQs needed to be updated */
	gen |= gen0 | gen1;
1295

1296 1297
	if (gen) {
		u32 old0, old1;
1298

1299 1300
		old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
		old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1301

1302 1303
		if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
			__raw_writel(old0 | gen, bank->base +
1304
						bank->regs->leveldetect0);
1305
			__raw_writel(old1 | gen, bank->base +
1306
						bank->regs->leveldetect1);
1307
		}
1308

1309 1310
		if (cpu_is_omap44xx()) {
			__raw_writel(old0 | l, bank->base +
1311
						bank->regs->leveldetect0);
1312
			__raw_writel(old1 | l, bank->base +
1313
						bank->regs->leveldetect1);
1314
		}
1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348
		__raw_writel(old0, bank->base + bank->regs->leveldetect0);
		__raw_writel(old1, bank->base + bank->regs->leveldetect1);
	}

	bank->workaround_enabled = false;
	spin_unlock_irqrestore(&bank->lock, flags);

	return 0;
}
#endif /* CONFIG_PM_RUNTIME */

void omap2_gpio_prepare_for_idle(int pwr_mode)
{
	struct gpio_bank *bank;

	list_for_each_entry(bank, &omap_gpio_list, node) {
		if (!bank->mod_usage || !bank->loses_context)
			continue;

		bank->power_mode = pwr_mode;

		pm_runtime_put_sync_suspend(bank->dev);
	}
}

void omap2_gpio_resume_after_idle(void)
{
	struct gpio_bank *bank;

	list_for_each_entry(bank, &omap_gpio_list, node) {
		if (!bank->mod_usage || !bank->loses_context)
			continue;

		pm_runtime_get_sync(bank->dev);
1349 1350 1351
	}
}

1352
#if defined(CONFIG_PM_RUNTIME)
1353
static void omap_gpio_restore_context(struct gpio_bank *bank)
1354
{
1355
	__raw_writel(bank->context.irqenable1,
1356
				bank->base + bank->regs->irqenable);
1357
	__raw_writel(bank->context.irqenable2,
1358
				bank->base + bank->regs->irqenable2);
1359
	__raw_writel(bank->context.wake_en,
1360 1361 1362
				bank->base + bank->regs->wkup_en);
	__raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
	__raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1363
	__raw_writel(bank->context.leveldetect0,
1364
				bank->base + bank->regs->leveldetect0);
1365
	__raw_writel(bank->context.leveldetect1,
1366
				bank->base + bank->regs->leveldetect1);
1367
	__raw_writel(bank->context.risingdetect,
1368
				bank->base + bank->regs->risingdetect);
1369
	__raw_writel(bank->context.fallingdetect,
1370 1371
				bank->base + bank->regs->fallingdetect);
	__raw_writel(bank->context.dataout, bank->base + bank->regs->dataout);
1372 1373 1374 1375 1376 1377
	if (bank->dbck_enable_mask) {
		__raw_writel(bank->context.debounce, bank->base +
					bank->regs->debounce);
		__raw_writel(bank->context.debounce_en,
					bank->base + bank->regs->debounce_en);
	}
1378
}
1379
#endif /* CONFIG_PM_RUNTIME */
1380 1381 1382
#else
#define omap_gpio_suspend NULL
#define omap_gpio_resume NULL
1383 1384
#define omap_gpio_runtime_suspend NULL
#define omap_gpio_runtime_resume NULL
1385 1386
#endif

1387 1388
static const struct dev_pm_ops gpio_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
1389 1390
	SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
									NULL)
1391 1392
};

1393 1394 1395 1396
static struct platform_driver omap_gpio_driver = {
	.probe		= omap_gpio_probe,
	.driver		= {
		.name	= "omap_gpio",
1397
		.pm	= &gpio_pm_ops,
1398 1399 1400
	},
};

1401
/*
1402 1403 1404
 * gpio driver register needs to be done before
 * machine_init functions access gpio APIs.
 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1405
 */
1406
static int __init omap_gpio_drv_reg(void)
1407
{
1408
	return platform_driver_register(&omap_gpio_driver);
1409
}
1410
postcore_initcall(omap_gpio_drv_reg);