davinci-mcasp.c 32.4 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
/*
 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
 *
 * Multi-channel Audio Serial Port Driver
 *
 * Author: Nirmal Pandey <n-pandey@ti.com>,
 *         Suresh Rajashekara <suresh.r@ti.com>
 *         Steve Chen <schen@.mvista.com>
 *
 * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
 * Copyright:   (C) 2009  Texas Instruments, India
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
21
#include <linux/slab.h>
22 23
#include <linux/delay.h>
#include <linux/io.h>
24
#include <linux/clk.h>
25
#include <linux/pm_runtime.h>
26 27 28
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
29 30 31 32 33 34

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
35
#include <sound/dmaengine_pcm.h>
36 37 38 39

#include "davinci-pcm.h"
#include "davinci-mcasp.h"

40 41 42 43 44 45 46 47 48 49
struct davinci_mcasp_context {
	u32	txfmtctl;
	u32	rxfmtctl;
	u32	txfmt;
	u32	rxfmt;
	u32	aclkxctl;
	u32	aclkrctl;
	u32	pdir;
};

50
struct davinci_mcasp {
51
	struct davinci_pcm_dma_params dma_params[2];
52
	struct snd_dmaengine_dai_dma_data dma_data[2];
53
	void __iomem *base;
54
	u32 fifo_base;
55 56 57 58 59 60 61 62 63
	struct device *dev;

	/* McASP specific data */
	int	tdm_slots;
	u8	op_mode;
	u8	num_serializer;
	u8	*serial_dir;
	u8	version;
	u16	bclk_lrclk_ratio;
64
	int	streams;
65

66 67 68
	int	sysclk_freq;
	bool	bclk_master;

69 70 71 72
	/* McASP FIFO related */
	u8	txnumevt;
	u8	rxnumevt;

73 74
	bool	dat_port;

75
#ifdef CONFIG_PM_SLEEP
76
	struct davinci_mcasp_context context;
77 78 79
#endif
};

80 81
static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
				  u32 val)
82
{
83
	void __iomem *reg = mcasp->base + offset;
84 85 86
	__raw_writel(__raw_readl(reg) | val, reg);
}

87 88
static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
				  u32 val)
89
{
90
	void __iomem *reg = mcasp->base + offset;
91 92 93
	__raw_writel((__raw_readl(reg) & ~(val)), reg);
}

94 95
static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
				  u32 val, u32 mask)
96
{
97
	void __iomem *reg = mcasp->base + offset;
98 99 100
	__raw_writel((__raw_readl(reg) & ~mask) | val, reg);
}

101 102
static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
				 u32 val)
103
{
104
	__raw_writel(val, mcasp->base + offset);
105 106
}

107
static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
108
{
109
	return (u32)__raw_readl(mcasp->base + offset);
110 111
}

112
static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
113 114 115
{
	int i = 0;

116
	mcasp_set_bits(mcasp, ctl_reg, val);
117 118 119 120

	/* programming GBLCTL needs to read back from GBLCTL and verfiy */
	/* loop count is to avoid the lock-up */
	for (i = 0; i < 1000; i++) {
121
		if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
122 123 124
			break;
	}

125
	if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
126 127 128
		printk(KERN_ERR "GBLCTL write error\n");
}

129 130
static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
{
131 132
	u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
	u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
133 134 135 136

	return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
}

137
static void mcasp_start_rx(struct davinci_mcasp *mcasp)
138
{
139 140
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
141 142 143 144 145 146 147

	/*
	 * When ASYNC == 0 the transmit and receive sections operate
	 * synchronously from the transmit clock and frame sync. We need to make
	 * sure that the TX signlas are enabled when starting reception.
	 */
	if (mcasp_is_synchronous(mcasp)) {
148 149
		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
150 151
	}

152 153
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
154

155 156 157
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
158

159 160
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
161 162

	if (mcasp_is_synchronous(mcasp))
163
		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
164 165
}

166
static void mcasp_start_tx(struct davinci_mcasp *mcasp)
167
{
168 169 170
	u8 offset = 0, i;
	u32 cnt;

171 172 173 174
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
175

176 177 178
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
179 180
	for (i = 0; i < mcasp->num_serializer; i++) {
		if (mcasp->serial_dir[i] == TX_MODE) {
181 182 183 184 185 186 187
			offset = i;
			break;
		}
	}

	/* wait for TX ready */
	cnt = 0;
188
	while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
189 190 191
		 TXSTATE) && (cnt < 100000))
		cnt++;

192
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
193 194
}

195
static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
196
{
197 198
	u32 reg;

199 200
	mcasp->streams++;

201
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
202
		if (mcasp->txnumevt) {	/* enable FIFO */
203
			reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
204 205
			mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
			mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
206
		}
207
		mcasp_start_tx(mcasp);
208
	} else {
209
		if (mcasp->rxnumevt) {	/* enable FIFO */
210
			reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
211 212
			mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
			mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
213
		}
214
		mcasp_start_rx(mcasp);
215
	}
216 217
}

218
static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
219
{
220 221 222 223 224
	/*
	 * In synchronous mode stop the TX clocks if no other stream is
	 * running
	 */
	if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
225
		mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
226

227 228
	mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
229 230
}

231
static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
232
{
233 234 235 236 237 238 239 240 241
	u32 val = 0;

	/*
	 * In synchronous mode keep TX clocks running if the capture stream is
	 * still running.
	 */
	if (mcasp_is_synchronous(mcasp) && mcasp->streams)
		val =  TXHCLKRST | TXCLKRST | TXFSRST;

242 243
	mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
244 245
}

246
static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
247
{
248 249
	u32 reg;

250 251
	mcasp->streams--;

252
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
253
		if (mcasp->txnumevt) {	/* disable FIFO */
254
			reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
255
			mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
256
		}
257
		mcasp_stop_tx(mcasp);
258
	} else {
259
		if (mcasp->rxnumevt) {	/* disable FIFO */
260
			reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
261
			mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
262
		}
263
		mcasp_stop_rx(mcasp);
264
	}
265 266 267 268 269
}

static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
					 unsigned int fmt)
{
270
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
271
	int ret = 0;
272

273
	pm_runtime_get_sync(mcasp->dev);
274 275 276
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_B:
	case SND_SOC_DAIFMT_AC97:
277 278
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
279 280 281
		break;
	default:
		/* configure a full-word SYNC pulse (LRCLK) */
282 283
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
284 285

		/* make 1st data bit occur one ACLK cycle after the frame sync */
286 287
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
288 289 290
		break;
	}

291 292 293
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* codec is clock and frame slave */
294 295
		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
296

297 298
		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
299

300 301
		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
302
		mcasp->bclk_master = 1;
303
		break;
304 305
	case SND_SOC_DAIFMT_CBM_CFS:
		/* codec is clock master and frame slave */
306 307
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
308

309 310
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
311

312 313
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
314
		mcasp->bclk_master = 0;
315
		break;
316 317
	case SND_SOC_DAIFMT_CBM_CFM:
		/* codec is clock and frame master */
318 319
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
320

321 322
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
323

324 325
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
			       ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
326
		mcasp->bclk_master = 0;
327 328 329
		break;

	default:
330 331
		ret = -EINVAL;
		goto out;
332 333 334 335
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_IB_NF:
336 337
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
338

339 340
		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
341 342 343
		break;

	case SND_SOC_DAIFMT_NB_IF:
344 345
		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
346

347 348
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
349 350 351
		break;

	case SND_SOC_DAIFMT_IB_IF:
352 353
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
354

355 356
		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
357 358 359
		break;

	case SND_SOC_DAIFMT_NB_NF:
360 361
		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
362

363 364
		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
365 366 367
		break;

	default:
368 369
		ret = -EINVAL;
		break;
370
	}
371 372 373
out:
	pm_runtime_put_sync(mcasp->dev);
	return ret;
374 375
}

376 377
static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
{
378
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
379 380 381

	switch (div_id) {
	case 0:		/* MCLK divider */
382
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
383
			       AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
384
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
385 386 387 388
			       AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
		break;

	case 1:		/* BCLK divider */
389
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
390
			       ACLKXDIV(div - 1), ACLKXDIV_MASK);
391
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
392 393 394
			       ACLKRDIV(div - 1), ACLKRDIV_MASK);
		break;

395
	case 2:		/* BCLK/LRCLK ratio */
396
		mcasp->bclk_lrclk_ratio = div;
397 398
		break;

399 400 401 402 403 404 405
	default:
		return -EINVAL;
	}

	return 0;
}

406 407 408
static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
				    unsigned int freq, int dir)
{
409
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
410 411

	if (dir == SND_SOC_CLOCK_OUT) {
412 413 414
		mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
415
	} else {
416 417 418
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
419 420
	}

421 422
	mcasp->sysclk_freq = freq;

423 424 425
	return 0;
}

426
static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
427
				       int word_length)
428
{
429
	u32 fmt;
D
Daniel Mack 已提交
430 431
	u32 tx_rotate = (word_length / 4) & 0x7;
	u32 rx_rotate = (32 - word_length) / 4;
432
	u32 mask = (1ULL << word_length) - 1;
433

434 435 436 437 438
	/*
	 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
	 * callback, take it into account here. That allows us to for example
	 * send 32 bits per channel to the codec, while only 16 of them carry
	 * audio payload.
439 440 441
	 * The clock ratio is given for a full period of data (for I2S format
	 * both left and right channels), so it has to be divided by number of
	 * tdm-slots (for I2S - divided by 2).
442
	 */
443 444
	if (mcasp->bclk_lrclk_ratio)
		word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
445

446 447
	/* mapping of the XSSZ bit-field as described in the datasheet */
	fmt = (word_length >> 1) - 1;
448

449
	if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
450 451 452 453 454 455 456 457 458
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
			       RXSSZ(0x0F));
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
			       TXSSZ(0x0F));
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
			       TXROT(7));
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
			       RXROT(7));
		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
459 460
	}

461
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
462

463 464 465
	return 0;
}

466
static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
467
				    int channels)
468 469
{
	int i;
470 471
	u8 tx_ser = 0;
	u8 rx_ser = 0;
472
	u8 ser;
473
	u8 slots = mcasp->tdm_slots;
474
	u8 max_active_serializers = (channels + slots - 1) / slots;
475
	u32 reg;
476
	/* Default configuration */
477
	if (mcasp->version != MCASP_VERSION_4)
478
		mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
479 480

	/* All PINS as McASP */
481
	mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
482 483

	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
484 485
		mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
486
	} else {
487 488
		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
489 490
	}

491
	for (i = 0; i < mcasp->num_serializer; i++) {
492 493
		mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
			       mcasp->serial_dir[i]);
494
		if (mcasp->serial_dir[i] == TX_MODE &&
495
					tx_ser < max_active_serializers) {
496
			mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
497
			tx_ser++;
498
		} else if (mcasp->serial_dir[i] == RX_MODE &&
499
					rx_ser < max_active_serializers) {
500
			mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
501
			rx_ser++;
502
		} else {
503 504
			mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
				       SRMOD_INACTIVE, SRMOD_MASK);
505 506 507
		}
	}

508 509 510 511 512 513
	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
		ser = tx_ser;
	else
		ser = rx_ser;

	if (ser < max_active_serializers) {
514
		dev_warn(mcasp->dev, "stream has more channels (%d) than are "
515 516 517 518
			"enabled in mcasp (%d)\n", channels, ser * slots);
		return -EINVAL;
	}

519 520 521
	if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
		if (mcasp->txnumevt * tx_ser > 64)
			mcasp->txnumevt = 1;
522

523
		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
524 525 526
		mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK);
		mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8),
			       NUMEVT_MASK);
527 528
	}

529 530 531
	if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
		if (mcasp->rxnumevt * rx_ser > 64)
			mcasp->rxnumevt = 1;
532 533

		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
534 535 536
		mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK);
		mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8),
			       NUMEVT_MASK);
537
	}
538 539

	return 0;
540 541
}

542
static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
543 544 545
{
	int i, active_slots;
	u32 mask = 0;
546
	u32 busel = 0;
547

548 549 550 551 552 553
	if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
		dev_err(mcasp->dev, "tdm slot %d not supported\n",
			mcasp->tdm_slots);
		return -EINVAL;
	}

554
	active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
555 556 557
	for (i = 0; i < active_slots; i++)
		mask |= (1 << i);

558
	mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
559

560 561 562
	if (!mcasp->dat_port)
		busel = TXSEL;

563 564 565 566 567 568 569 570 571 572 573
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
	mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
		       FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));

	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
	mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
	mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
		       FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));

	return 0;
574 575 576
}

/* S/PDIF */
577
static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
578 579 580
{
	/* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
	   and LSB first */
581
	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
582 583

	/* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
584
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
585 586

	/* Set the TX tdm : for all the slots */
587
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
588 589

	/* Set the TX clock controls : div = 1 and internal */
590
	mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
591

592
	mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
593 594

	/* Only 44100 and 48000 are valid, both have the same setting */
595
	mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
596 597

	/* Enable the DIT */
598
	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
599 600

	return 0;
601 602 603 604 605 606
}

static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
					struct snd_pcm_hw_params *params,
					struct snd_soc_dai *cpu_dai)
{
607
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
608
	struct davinci_pcm_dma_params *dma_params =
609
					&mcasp->dma_params[substream->stream];
610 611
	struct snd_dmaengine_dai_dma_data *dma_data =
					&mcasp->dma_data[substream->stream];
612
	int word_length;
613
	u8 fifo_level;
614
	u8 slots = mcasp->tdm_slots;
615
	u8 active_serializers;
616
	int channels = params_channels(params);
617
	int ret;
618 619 620 621 622 623 624 625 626 627 628 629

	/* If mcasp is BCLK master we need to set BCLK divider */
	if (mcasp->bclk_master) {
		unsigned int bclk_freq = snd_soc_params_to_bclk(params);
		if (mcasp->sysclk_freq % bclk_freq != 0) {
			dev_err(mcasp->dev, "Can't produce requred BCLK\n");
			return -EINVAL;
		}
		davinci_mcasp_set_clkdiv(
			cpu_dai, 1, mcasp->sysclk_freq / bclk_freq);
	}

630 631 632 633
	ret = mcasp_common_hw_param(mcasp, substream->stream, channels);
	if (ret)
		return ret;

634
	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
635
		ret = mcasp_dit_hw_param(mcasp);
636
	else
637 638 639 640
		ret = mcasp_i2s_hw_param(mcasp, substream->stream);

	if (ret)
		return ret;
641 642

	switch (params_format(params)) {
643
	case SNDRV_PCM_FORMAT_U8:
644 645
	case SNDRV_PCM_FORMAT_S8:
		dma_params->data_type = 1;
646
		word_length = 8;
647 648
		break;

649
	case SNDRV_PCM_FORMAT_U16_LE:
650 651
	case SNDRV_PCM_FORMAT_S16_LE:
		dma_params->data_type = 2;
652
		word_length = 16;
653 654
		break;

655 656 657
	case SNDRV_PCM_FORMAT_U24_3LE:
	case SNDRV_PCM_FORMAT_S24_3LE:
		dma_params->data_type = 3;
658
		word_length = 24;
659 660
		break;

661 662
	case SNDRV_PCM_FORMAT_U24_LE:
	case SNDRV_PCM_FORMAT_S24_LE:
663
	case SNDRV_PCM_FORMAT_U32_LE:
664 665
	case SNDRV_PCM_FORMAT_S32_LE:
		dma_params->data_type = 4;
666
		word_length = 32;
667 668 669 670 671 672
		break;

	default:
		printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
		return -EINVAL;
	}
673

674 675 676 677 678 679 680
	/* Calculate FIFO level */
	active_serializers = (channels + slots - 1) / slots;
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		fifo_level = mcasp->txnumevt * active_serializers;
	else
		fifo_level = mcasp->rxnumevt * active_serializers;

681
	if (mcasp->version == MCASP_VERSION_2 && !fifo_level)
682 683
		dma_params->acnt = 4;
	else
684 685
		dma_params->acnt = dma_params->data_type;

686
	dma_params->fifo_level = fifo_level;
687 688
	dma_data->maxburst = fifo_level;

689
	davinci_config_channel_size(mcasp, word_length);
690 691 692 693 694 695 696

	return 0;
}

static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
				     int cmd, struct snd_soc_dai *cpu_dai)
{
697
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
698 699 700 701
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_RESUME:
702 703
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
704
		davinci_mcasp_start(mcasp, substream->stream);
705 706
		break;
	case SNDRV_PCM_TRIGGER_SUSPEND:
707
	case SNDRV_PCM_TRIGGER_STOP:
708
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
709
		davinci_mcasp_stop(mcasp, substream->stream);
710 711 712 713 714 715 716 717 718
		break;

	default:
		ret = -EINVAL;
	}

	return ret;
}

719 720 721
static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
				 struct snd_soc_dai *dai)
{
722
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
723

724 725 726 727 728 729
	if (mcasp->version == MCASP_VERSION_4)
		snd_soc_dai_set_dma_data(dai, substream,
					&mcasp->dma_data[substream->stream]);
	else
		snd_soc_dai_set_dma_data(dai, substream, mcasp->dma_params);

730 731 732
	return 0;
}

733
static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
734
	.startup	= davinci_mcasp_startup,
735 736 737
	.trigger	= davinci_mcasp_trigger,
	.hw_params	= davinci_mcasp_hw_params,
	.set_fmt	= davinci_mcasp_set_dai_fmt,
738
	.set_clkdiv	= davinci_mcasp_set_clkdiv,
739
	.set_sysclk	= davinci_mcasp_set_sysclk,
740 741
};

742 743 744 745
#ifdef CONFIG_PM_SLEEP
static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
{
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
746
	struct davinci_mcasp_context *context = &mcasp->context;
747

748 749 750 751 752 753 754
	context->txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
	context->rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
	context->txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
	context->rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
	context->aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
	context->aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
	context->pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
755 756 757 758 759 760 761

	return 0;
}

static int davinci_mcasp_resume(struct snd_soc_dai *dai)
{
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
762 763 764 765 766 767 768 769 770
	struct davinci_mcasp_context *context = &mcasp->context;

	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, context->txfmtctl);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, context->rxfmtctl);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, context->txfmt);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, context->rxfmt);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, context->aclkxctl);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, context->aclkrctl);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, context->pdir);
771 772 773 774 775 776 777 778

	return 0;
}
#else
#define davinci_mcasp_suspend NULL
#define davinci_mcasp_resume NULL
#endif

779 780
#define DAVINCI_MCASP_RATES	SNDRV_PCM_RATE_8000_192000

781 782 783 784
#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
				SNDRV_PCM_FMTBIT_U8 | \
				SNDRV_PCM_FMTBIT_S16_LE | \
				SNDRV_PCM_FMTBIT_U16_LE | \
785 786 787 788
				SNDRV_PCM_FMTBIT_S24_LE | \
				SNDRV_PCM_FMTBIT_U24_LE | \
				SNDRV_PCM_FMTBIT_S24_3LE | \
				SNDRV_PCM_FMTBIT_U24_3LE | \
789 790 791
				SNDRV_PCM_FMTBIT_S32_LE | \
				SNDRV_PCM_FMTBIT_U32_LE)

792
static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
793
	{
794
		.name		= "davinci-mcasp.0",
795 796
		.suspend	= davinci_mcasp_suspend,
		.resume		= davinci_mcasp_resume,
797 798
		.playback	= {
			.channels_min	= 2,
799
			.channels_max	= 32 * 16,
800
			.rates 		= DAVINCI_MCASP_RATES,
801
			.formats	= DAVINCI_MCASP_PCM_FMTS,
802 803 804
		},
		.capture 	= {
			.channels_min 	= 2,
805
			.channels_max	= 32 * 16,
806
			.rates 		= DAVINCI_MCASP_RATES,
807
			.formats	= DAVINCI_MCASP_PCM_FMTS,
808 809 810 811 812
		},
		.ops 		= &davinci_mcasp_dai_ops,

	},
	{
813
		.name		= "davinci-mcasp.1",
814 815 816 817
		.playback 	= {
			.channels_min	= 1,
			.channels_max	= 384,
			.rates		= DAVINCI_MCASP_RATES,
818
			.formats	= DAVINCI_MCASP_PCM_FMTS,
819 820 821 822 823 824
		},
		.ops 		= &davinci_mcasp_dai_ops,
	},

};

825 826 827 828
static const struct snd_soc_component_driver davinci_mcasp_component = {
	.name		= "davinci-mcasp",
};

829
/* Some HW specific values and defaults. The rest is filled in from DT. */
830
static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
831 832 833 834 835 836
	.tx_dma_offset = 0x400,
	.rx_dma_offset = 0x400,
	.asp_chan_q = EVENTQ_0,
	.version = MCASP_VERSION_1,
};

837
static struct davinci_mcasp_pdata da830_mcasp_pdata = {
838 839 840 841 842 843
	.tx_dma_offset = 0x2000,
	.rx_dma_offset = 0x2000,
	.asp_chan_q = EVENTQ_0,
	.version = MCASP_VERSION_2,
};

844
static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
845 846 847 848 849 850
	.tx_dma_offset = 0,
	.rx_dma_offset = 0,
	.asp_chan_q = EVENTQ_0,
	.version = MCASP_VERSION_3,
};

851
static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
852 853 854 855 856 857
	.tx_dma_offset = 0x200,
	.rx_dma_offset = 0x284,
	.asp_chan_q = EVENTQ_0,
	.version = MCASP_VERSION_4,
};

858 859 860
static const struct of_device_id mcasp_dt_ids[] = {
	{
		.compatible = "ti,dm646x-mcasp-audio",
861
		.data = &dm646x_mcasp_pdata,
862 863 864
	},
	{
		.compatible = "ti,da830-mcasp-audio",
865
		.data = &da830_mcasp_pdata,
866
	},
867
	{
868
		.compatible = "ti,am33xx-mcasp-audio",
869
		.data = &am33xx_mcasp_pdata,
870
	},
871 872 873 874
	{
		.compatible = "ti,dra7-mcasp-audio",
		.data = &dra7_mcasp_pdata,
	},
875 876 877 878
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mcasp_dt_ids);

879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918
static int mcasp_reparent_fck(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct clk *gfclk, *parent_clk;
	const char *parent_name;
	int ret;

	if (!node)
		return 0;

	parent_name = of_get_property(node, "fck_parent", NULL);
	if (!parent_name)
		return 0;

	gfclk = clk_get(&pdev->dev, "fck");
	if (IS_ERR(gfclk)) {
		dev_err(&pdev->dev, "failed to get fck\n");
		return PTR_ERR(gfclk);
	}

	parent_clk = clk_get(NULL, parent_name);
	if (IS_ERR(parent_clk)) {
		dev_err(&pdev->dev, "failed to get parent clock\n");
		ret = PTR_ERR(parent_clk);
		goto err1;
	}

	ret = clk_set_parent(gfclk, parent_clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to reparent fck\n");
		goto err2;
	}

err2:
	clk_put(parent_clk);
err1:
	clk_put(gfclk);
	return ret;
}

919
static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
920 921 922
						struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
923
	struct davinci_mcasp_pdata *pdata = NULL;
924
	const struct of_device_id *match =
925
			of_match_device(mcasp_dt_ids, &pdev->dev);
926
	struct of_phandle_args dma_spec;
927 928 929 930 931 932 933 934 935

	const u32 *of_serial_dir32;
	u32 val;
	int i, ret = 0;

	if (pdev->dev.platform_data) {
		pdata = pdev->dev.platform_data;
		return pdata;
	} else if (match) {
936
		pdata = (struct davinci_mcasp_pdata*) match->data;
937 938 939 940 941 942 943 944 945 946 947
	} else {
		/* control shouldn't reach here. something is wrong */
		ret = -EINVAL;
		goto nodata;
	}

	ret = of_property_read_u32(np, "op-mode", &val);
	if (ret >= 0)
		pdata->op_mode = val;

	ret = of_property_read_u32(np, "tdm-slots", &val);
948 949 950 951 952 953 954 955
	if (ret >= 0) {
		if (val < 2 || val > 32) {
			dev_err(&pdev->dev,
				"tdm-slots must be in rage [2-32]\n");
			ret = -EINVAL;
			goto nodata;
		}

956
		pdata->tdm_slots = val;
957
	}
958 959 960 961

	of_serial_dir32 = of_get_property(np, "serial-dir", &val);
	val /= sizeof(u32);
	if (of_serial_dir32) {
962 963 964
		u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
						 (sizeof(*of_serial_dir) * val),
						 GFP_KERNEL);
965 966 967 968 969
		if (!of_serial_dir) {
			ret = -ENOMEM;
			goto nodata;
		}

970
		for (i = 0; i < val; i++)
971 972
			of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);

973
		pdata->num_serializer = val;
974 975 976
		pdata->serial_dir = of_serial_dir;
	}

977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998
	ret = of_property_match_string(np, "dma-names", "tx");
	if (ret < 0)
		goto nodata;

	ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
					 &dma_spec);
	if (ret < 0)
		goto nodata;

	pdata->tx_dma_channel = dma_spec.args[0];

	ret = of_property_match_string(np, "dma-names", "rx");
	if (ret < 0)
		goto nodata;

	ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
					 &dma_spec);
	if (ret < 0)
		goto nodata;

	pdata->rx_dma_channel = dma_spec.args[0];

999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025
	ret = of_property_read_u32(np, "tx-num-evt", &val);
	if (ret >= 0)
		pdata->txnumevt = val;

	ret = of_property_read_u32(np, "rx-num-evt", &val);
	if (ret >= 0)
		pdata->rxnumevt = val;

	ret = of_property_read_u32(np, "sram-size-playback", &val);
	if (ret >= 0)
		pdata->sram_size_playback = val;

	ret = of_property_read_u32(np, "sram-size-capture", &val);
	if (ret >= 0)
		pdata->sram_size_capture = val;

	return  pdata;

nodata:
	if (ret < 0) {
		dev_err(&pdev->dev, "Error populating platform data, err %d\n",
			ret);
		pdata = NULL;
	}
	return  pdata;
}

1026 1027
static int davinci_mcasp_probe(struct platform_device *pdev)
{
1028
	struct davinci_pcm_dma_params *dma_params;
1029
	struct snd_dmaengine_dai_dma_data *dma_data;
1030
	struct resource *mem, *ioarea, *res, *dat;
1031
	struct davinci_mcasp_pdata *pdata;
1032
	struct davinci_mcasp *mcasp;
1033
	int ret;
1034

1035 1036 1037 1038 1039
	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
		dev_err(&pdev->dev, "No platform data supplied\n");
		return -EINVAL;
	}

1040
	mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1041
			   GFP_KERNEL);
1042
	if (!mcasp)
1043 1044
		return	-ENOMEM;

1045 1046 1047 1048 1049 1050
	pdata = davinci_mcasp_set_pdata_from_of(pdev);
	if (!pdata) {
		dev_err(&pdev->dev, "no platform data\n");
		return -EINVAL;
	}

1051
	mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1052
	if (!mem) {
1053
		dev_warn(mcasp->dev,
1054 1055 1056 1057 1058 1059
			 "\"mpu\" mem resource not found, using index 0\n");
		mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (!mem) {
			dev_err(&pdev->dev, "no mem resource?\n");
			return -ENODEV;
		}
1060 1061
	}

1062
	ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1063
			resource_size(mem), pdev->name);
1064 1065
	if (!ioarea) {
		dev_err(&pdev->dev, "Audio region already claimed\n");
1066
		return -EBUSY;
1067 1068
	}

1069
	pm_runtime_enable(&pdev->dev);
1070

1071 1072 1073 1074 1075
	ret = pm_runtime_get_sync(&pdev->dev);
	if (IS_ERR_VALUE(ret)) {
		dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
		return ret;
	}
1076

1077 1078
	mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
	if (!mcasp->base) {
1079 1080 1081 1082 1083
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -ENOMEM;
		goto err_release_clk;
	}

1084 1085 1086 1087 1088 1089 1090
	mcasp->op_mode = pdata->op_mode;
	mcasp->tdm_slots = pdata->tdm_slots;
	mcasp->num_serializer = pdata->num_serializer;
	mcasp->serial_dir = pdata->serial_dir;
	mcasp->version = pdata->version;
	mcasp->txnumevt = pdata->txnumevt;
	mcasp->rxnumevt = pdata->rxnumevt;
1091

1092
	mcasp->dev = &pdev->dev;
1093

1094
	dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1095 1096
	if (dat)
		mcasp->dat_port = true;
1097

1098
	dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1099
	dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1100 1101 1102 1103
	dma_params->asp_chan_q = pdata->asp_chan_q;
	dma_params->ram_chan_q = pdata->ram_chan_q;
	dma_params->sram_pool = pdata->sram_pool;
	dma_params->sram_size = pdata->sram_size_playback;
1104
	if (dat)
1105
		dma_params->dma_addr = dat->start;
1106
	else
1107
		dma_params->dma_addr = mem->start + pdata->tx_dma_offset;
1108

1109
	/* Unconditional dmaengine stuff */
1110
	dma_data->addr = dma_params->dma_addr;
1111

1112
	res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1113
	if (res)
1114
		dma_params->channel = res->start;
1115
	else
1116
		dma_params->channel = pdata->tx_dma_channel;
1117

1118 1119 1120 1121 1122 1123
	/* dmaengine filter data for DT and non-DT boot */
	if (pdev->dev.of_node)
		dma_data->filter_data = "tx";
	else
		dma_data->filter_data = &dma_params->channel;

1124
	dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1125
	dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1126 1127 1128 1129
	dma_params->asp_chan_q = pdata->asp_chan_q;
	dma_params->ram_chan_q = pdata->ram_chan_q;
	dma_params->sram_pool = pdata->sram_pool;
	dma_params->sram_size = pdata->sram_size_capture;
1130
	if (dat)
1131
		dma_params->dma_addr = dat->start;
1132
	else
1133
		dma_params->dma_addr = mem->start + pdata->rx_dma_offset;
1134

1135
	/* Unconditional dmaengine stuff */
1136
	dma_data->addr = dma_params->dma_addr;
1137

1138 1139
	if (mcasp->version < MCASP_VERSION_3) {
		mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1140
		/* dma_params->dma_addr is pointing to the data port address */
1141 1142 1143 1144
		mcasp->dat_port = true;
	} else {
		mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
	}
1145 1146

	res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1147
	if (res)
1148
		dma_params->channel = res->start;
1149
	else
1150
		dma_params->channel = pdata->rx_dma_channel;
1151

1152 1153 1154 1155 1156
	/* dmaengine filter data for DT and non-DT boot */
	if (pdev->dev.of_node)
		dma_data->filter_data = "rx";
	else
		dma_data->filter_data = &dma_params->channel;
1157

1158
	dev_set_drvdata(&pdev->dev, mcasp);
1159 1160 1161

	mcasp_reparent_fck(pdev);

1162 1163
	ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
					 &davinci_mcasp_dai[pdata->op_mode], 1);
1164 1165

	if (ret != 0)
1166
		goto err_release_clk;
1167

1168 1169 1170 1171 1172 1173
	if (mcasp->version != MCASP_VERSION_4) {
		ret = davinci_soc_platform_register(&pdev->dev);
		if (ret) {
			dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
			goto err_unregister_component;
		}
1174 1175
	}

1176 1177
	return 0;

1178 1179
err_unregister_component:
	snd_soc_unregister_component(&pdev->dev);
1180
err_release_clk:
1181 1182
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
1183 1184 1185 1186 1187
	return ret;
}

static int davinci_mcasp_remove(struct platform_device *pdev)
{
1188
	struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev);
1189

1190
	snd_soc_unregister_component(&pdev->dev);
1191 1192
	if (mcasp->version != MCASP_VERSION_4)
		davinci_soc_platform_unregister(&pdev->dev);
1193 1194 1195

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
1196 1197 1198 1199 1200 1201 1202 1203 1204 1205

	return 0;
}

static struct platform_driver davinci_mcasp_driver = {
	.probe		= davinci_mcasp_probe,
	.remove		= davinci_mcasp_remove,
	.driver		= {
		.name	= "davinci-mcasp",
		.owner	= THIS_MODULE,
1206
		.of_match_table = mcasp_dt_ids,
1207 1208 1209
	},
};

1210
module_platform_driver(davinci_mcasp_driver);
1211 1212 1213 1214

MODULE_AUTHOR("Steve Chen");
MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
MODULE_LICENSE("GPL");