davinci-mcasp.c 32.0 KB
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/*
 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
 *
 * Multi-channel Audio Serial Port Driver
 *
 * Author: Nirmal Pandey <n-pandey@ti.com>,
 *         Suresh Rajashekara <suresh.r@ti.com>
 *         Steve Chen <schen@.mvista.com>
 *
 * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
 * Copyright:   (C) 2009  Texas Instruments, India
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
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#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
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#include <sound/dmaengine_pcm.h>
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#include "davinci-pcm.h"
#include "davinci-mcasp.h"

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struct davinci_mcasp {
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	struct davinci_pcm_dma_params dma_params[2];
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	struct snd_dmaengine_dai_dma_data dma_data[2];
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	void __iomem *base;
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	u32 fifo_base;
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	struct device *dev;

	/* McASP specific data */
	int	tdm_slots;
	u8	op_mode;
	u8	num_serializer;
	u8	*serial_dir;
	u8	version;
	u16	bclk_lrclk_ratio;
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	int	streams;
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	int	sysclk_freq;
	bool	bclk_master;

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	/* McASP FIFO related */
	u8	txnumevt;
	u8	rxnumevt;

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	bool	dat_port;

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#ifdef CONFIG_PM_SLEEP
	struct {
		u32	txfmtctl;
		u32	rxfmtctl;
		u32	txfmt;
		u32	rxfmt;
		u32	aclkxctl;
		u32	aclkrctl;
		u32	pdir;
	} context;
#endif
};

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static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
				  u32 val)
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{
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	void __iomem *reg = mcasp->base + offset;
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	__raw_writel(__raw_readl(reg) | val, reg);
}

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static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
				  u32 val)
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{
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	void __iomem *reg = mcasp->base + offset;
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	__raw_writel((__raw_readl(reg) & ~(val)), reg);
}

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static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
				  u32 val, u32 mask)
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{
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	void __iomem *reg = mcasp->base + offset;
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	__raw_writel((__raw_readl(reg) & ~mask) | val, reg);
}

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static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
				 u32 val)
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{
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	__raw_writel(val, mcasp->base + offset);
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}

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static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
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{
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	return (u32)__raw_readl(mcasp->base + offset);
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}

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static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
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{
	int i = 0;

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	mcasp_set_bits(mcasp, ctl_reg, val);
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	/* programming GBLCTL needs to read back from GBLCTL and verfiy */
	/* loop count is to avoid the lock-up */
	for (i = 0; i < 1000; i++) {
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		if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
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			break;
	}

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	if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
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		printk(KERN_ERR "GBLCTL write error\n");
}

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static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
{
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	u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
	u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
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	return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
}

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static void mcasp_start_rx(struct davinci_mcasp *mcasp)
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{
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	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
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	/*
	 * When ASYNC == 0 the transmit and receive sections operate
	 * synchronously from the transmit clock and frame sync. We need to make
	 * sure that the TX signlas are enabled when starting reception.
	 */
	if (mcasp_is_synchronous(mcasp)) {
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		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
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	}

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	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
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	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
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	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
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	if (mcasp_is_synchronous(mcasp))
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		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
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}

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static void mcasp_start_tx(struct davinci_mcasp *mcasp)
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{
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	u8 offset = 0, i;
	u32 cnt;

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	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
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	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
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	for (i = 0; i < mcasp->num_serializer; i++) {
		if (mcasp->serial_dir[i] == TX_MODE) {
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			offset = i;
			break;
		}
	}

	/* wait for TX ready */
	cnt = 0;
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	while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
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		 TXSTATE) && (cnt < 100000))
		cnt++;

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	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
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}

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static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
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{
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	u32 reg;

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	mcasp->streams++;

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	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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		if (mcasp->txnumevt) {	/* enable FIFO */
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			reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
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			mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
			mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
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		}
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		mcasp_start_tx(mcasp);
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	} else {
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		if (mcasp->rxnumevt) {	/* enable FIFO */
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			reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
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			mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
			mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
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		}
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		mcasp_start_rx(mcasp);
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	}
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}

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static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
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{
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	/*
	 * In synchronous mode stop the TX clocks if no other stream is
	 * running
	 */
	if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
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		mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
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	mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
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}

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static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
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{
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	u32 val = 0;

	/*
	 * In synchronous mode keep TX clocks running if the capture stream is
	 * still running.
	 */
	if (mcasp_is_synchronous(mcasp) && mcasp->streams)
		val =  TXHCLKRST | TXCLKRST | TXFSRST;

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	mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
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}

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static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
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{
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	u32 reg;

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	mcasp->streams--;

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	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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		if (mcasp->txnumevt) {	/* disable FIFO */
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			reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
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			mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
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		}
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		mcasp_stop_tx(mcasp);
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	} else {
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		if (mcasp->rxnumevt) {	/* disable FIFO */
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			reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
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			mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
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		}
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		mcasp_stop_rx(mcasp);
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	}
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}

static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
					 unsigned int fmt)
{
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	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
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	int ret = 0;
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	pm_runtime_get_sync(mcasp->dev);
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	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_B:
	case SND_SOC_DAIFMT_AC97:
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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		break;
	default:
		/* configure a full-word SYNC pulse (LRCLK) */
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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		/* make 1st data bit occur one ACLK cycle after the frame sync */
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
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		break;
	}

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	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* codec is clock and frame slave */
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
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		mcasp->bclk_master = 1;
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		break;
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	case SND_SOC_DAIFMT_CBM_CFS:
		/* codec is clock master and frame slave */
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
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		mcasp->bclk_master = 0;
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		break;
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	case SND_SOC_DAIFMT_CBM_CFM:
		/* codec is clock and frame master */
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
			       ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
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		mcasp->bclk_master = 0;
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		break;

	default:
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		ret = -EINVAL;
		goto out;
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	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_IB_NF:
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
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		break;

	case SND_SOC_DAIFMT_NB_IF:
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
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		break;

	case SND_SOC_DAIFMT_IB_IF:
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
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		break;

	case SND_SOC_DAIFMT_NB_NF:
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
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		break;

	default:
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		ret = -EINVAL;
		break;
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	}
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out:
	pm_runtime_put_sync(mcasp->dev);
	return ret;
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}

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static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
{
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	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
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	switch (div_id) {
	case 0:		/* MCLK divider */
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		mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
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			       AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
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		mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
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			       AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
		break;

	case 1:		/* BCLK divider */
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		mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
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			       ACLKXDIV(div - 1), ACLKXDIV_MASK);
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		mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
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			       ACLKRDIV(div - 1), ACLKRDIV_MASK);
		break;

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	case 2:		/* BCLK/LRCLK ratio */
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		mcasp->bclk_lrclk_ratio = div;
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		break;

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	default:
		return -EINVAL;
	}

	return 0;
}

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static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
				    unsigned int freq, int dir)
{
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	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
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	if (dir == SND_SOC_CLOCK_OUT) {
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
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	} else {
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
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	}

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	mcasp->sysclk_freq = freq;

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	return 0;
}

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static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
425
				       int word_length)
426
{
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	u32 fmt;
D
Daniel Mack 已提交
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	u32 tx_rotate = (word_length / 4) & 0x7;
	u32 rx_rotate = (32 - word_length) / 4;
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	u32 mask = (1ULL << word_length) - 1;
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	/*
	 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
	 * callback, take it into account here. That allows us to for example
	 * send 32 bits per channel to the codec, while only 16 of them carry
	 * audio payload.
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	 * The clock ratio is given for a full period of data (for I2S format
	 * both left and right channels), so it has to be divided by number of
	 * tdm-slots (for I2S - divided by 2).
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	 */
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	if (mcasp->bclk_lrclk_ratio)
		word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
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	/* mapping of the XSSZ bit-field as described in the datasheet */
	fmt = (word_length >> 1) - 1;
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	if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
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		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
			       RXSSZ(0x0F));
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
			       TXSSZ(0x0F));
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
			       TXROT(7));
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
			       RXROT(7));
		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
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	}

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	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
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	return 0;
}

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static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
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				    int channels)
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{
	int i;
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	u8 tx_ser = 0;
	u8 rx_ser = 0;
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	u8 ser;
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	u8 slots = mcasp->tdm_slots;
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	u8 max_active_serializers = (channels + slots - 1) / slots;
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	u32 reg;
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	/* Default configuration */
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	if (mcasp->version != MCASP_VERSION_4)
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
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	/* All PINS as McASP */
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	mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
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	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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		mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
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	} else {
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		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
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	}

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	for (i = 0; i < mcasp->num_serializer; i++) {
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
			       mcasp->serial_dir[i]);
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		if (mcasp->serial_dir[i] == TX_MODE &&
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					tx_ser < max_active_serializers) {
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			mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
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			tx_ser++;
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		} else if (mcasp->serial_dir[i] == RX_MODE &&
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					rx_ser < max_active_serializers) {
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			mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
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			rx_ser++;
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		} else {
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			mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
				       SRMOD_INACTIVE, SRMOD_MASK);
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		}
	}

506 507 508 509 510 511
	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
		ser = tx_ser;
	else
		ser = rx_ser;

	if (ser < max_active_serializers) {
512
		dev_warn(mcasp->dev, "stream has more channels (%d) than are "
513 514 515 516
			"enabled in mcasp (%d)\n", channels, ser * slots);
		return -EINVAL;
	}

517 518 519
	if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
		if (mcasp->txnumevt * tx_ser > 64)
			mcasp->txnumevt = 1;
520

521
		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
522 523 524
		mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK);
		mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8),
			       NUMEVT_MASK);
525 526
	}

527 528 529
	if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
		if (mcasp->rxnumevt * rx_ser > 64)
			mcasp->rxnumevt = 1;
530 531

		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
532 533 534
		mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK);
		mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8),
			       NUMEVT_MASK);
535
	}
536 537

	return 0;
538 539
}

540
static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
541 542 543
{
	int i, active_slots;
	u32 mask = 0;
544
	u32 busel = 0;
545

546 547 548 549 550 551
	if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
		dev_err(mcasp->dev, "tdm slot %d not supported\n",
			mcasp->tdm_slots);
		return -EINVAL;
	}

552
	active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
553 554 555
	for (i = 0; i < active_slots; i++)
		mask |= (1 << i);

556
	mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
557

558 559 560
	if (!mcasp->dat_port)
		busel = TXSEL;

561 562 563 564 565 566 567 568 569 570 571
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
	mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
		       FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));

	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
	mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
	mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
		       FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));

	return 0;
572 573 574
}

/* S/PDIF */
575
static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
576 577 578
{
	/* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
	   and LSB first */
579
	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
580 581

	/* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
582
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
583 584

	/* Set the TX tdm : for all the slots */
585
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
586 587

	/* Set the TX clock controls : div = 1 and internal */
588
	mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
589

590
	mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
591 592

	/* Only 44100 and 48000 are valid, both have the same setting */
593
	mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
594 595

	/* Enable the DIT */
596
	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
597 598

	return 0;
599 600 601 602 603 604
}

static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
					struct snd_pcm_hw_params *params,
					struct snd_soc_dai *cpu_dai)
{
605
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
606
	struct davinci_pcm_dma_params *dma_params =
607
					&mcasp->dma_params[substream->stream];
608 609
	struct snd_dmaengine_dai_dma_data *dma_data =
					&mcasp->dma_data[substream->stream];
610
	int word_length;
611
	u8 fifo_level;
612
	u8 slots = mcasp->tdm_slots;
613
	u8 active_serializers;
614
	int channels;
615
	int ret;
616 617
	struct snd_interval *pcm_channels = hw_param_interval(params,
					SNDRV_PCM_HW_PARAM_CHANNELS);
618 619 620 621 622 623 624 625 626 627 628 629

	/* If mcasp is BCLK master we need to set BCLK divider */
	if (mcasp->bclk_master) {
		unsigned int bclk_freq = snd_soc_params_to_bclk(params);
		if (mcasp->sysclk_freq % bclk_freq != 0) {
			dev_err(mcasp->dev, "Can't produce requred BCLK\n");
			return -EINVAL;
		}
		davinci_mcasp_set_clkdiv(
			cpu_dai, 1, mcasp->sysclk_freq / bclk_freq);
	}

630
	channels = pcm_channels->min;
631

632 633
	active_serializers = (channels + slots - 1) / slots;

634 635 636 637
	ret = mcasp_common_hw_param(mcasp, substream->stream, channels);
	if (ret)
		return ret;

638
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
639
		fifo_level = mcasp->txnumevt * active_serializers;
640
	else
641
		fifo_level = mcasp->rxnumevt * active_serializers;
642

643
	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
644
		ret = mcasp_dit_hw_param(mcasp);
645
	else
646 647 648 649
		ret = mcasp_i2s_hw_param(mcasp, substream->stream);

	if (ret)
		return ret;
650 651

	switch (params_format(params)) {
652
	case SNDRV_PCM_FORMAT_U8:
653 654
	case SNDRV_PCM_FORMAT_S8:
		dma_params->data_type = 1;
655
		word_length = 8;
656 657
		break;

658
	case SNDRV_PCM_FORMAT_U16_LE:
659 660
	case SNDRV_PCM_FORMAT_S16_LE:
		dma_params->data_type = 2;
661
		word_length = 16;
662 663
		break;

664 665 666
	case SNDRV_PCM_FORMAT_U24_3LE:
	case SNDRV_PCM_FORMAT_S24_3LE:
		dma_params->data_type = 3;
667
		word_length = 24;
668 669
		break;

670 671
	case SNDRV_PCM_FORMAT_U24_LE:
	case SNDRV_PCM_FORMAT_S24_LE:
672
	case SNDRV_PCM_FORMAT_U32_LE:
673 674
	case SNDRV_PCM_FORMAT_S32_LE:
		dma_params->data_type = 4;
675
		word_length = 32;
676 677 678 679 680 681
		break;

	default:
		printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
		return -EINVAL;
	}
682

683
	if (mcasp->version == MCASP_VERSION_2 && !fifo_level)
684 685
		dma_params->acnt = 4;
	else
686 687
		dma_params->acnt = dma_params->data_type;

688
	dma_params->fifo_level = fifo_level;
689 690
	dma_data->maxburst = fifo_level;

691
	davinci_config_channel_size(mcasp, word_length);
692 693 694 695 696 697 698

	return 0;
}

static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
				     int cmd, struct snd_soc_dai *cpu_dai)
{
699
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
700 701 702 703
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_RESUME:
704 705
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
706
		davinci_mcasp_start(mcasp, substream->stream);
707 708
		break;
	case SNDRV_PCM_TRIGGER_SUSPEND:
709
	case SNDRV_PCM_TRIGGER_STOP:
710
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
711
		davinci_mcasp_stop(mcasp, substream->stream);
712 713 714 715 716 717 718 719 720
		break;

	default:
		ret = -EINVAL;
	}

	return ret;
}

721 722 723
static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
				 struct snd_soc_dai *dai)
{
724
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
725

726 727 728 729 730 731
	if (mcasp->version == MCASP_VERSION_4)
		snd_soc_dai_set_dma_data(dai, substream,
					&mcasp->dma_data[substream->stream]);
	else
		snd_soc_dai_set_dma_data(dai, substream, mcasp->dma_params);

732 733 734
	return 0;
}

735
static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
736
	.startup	= davinci_mcasp_startup,
737 738 739
	.trigger	= davinci_mcasp_trigger,
	.hw_params	= davinci_mcasp_hw_params,
	.set_fmt	= davinci_mcasp_set_dai_fmt,
740
	.set_clkdiv	= davinci_mcasp_set_clkdiv,
741
	.set_sysclk	= davinci_mcasp_set_sysclk,
742 743
};

744 745
#define DAVINCI_MCASP_RATES	SNDRV_PCM_RATE_8000_192000

746 747 748 749
#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
				SNDRV_PCM_FMTBIT_U8 | \
				SNDRV_PCM_FMTBIT_S16_LE | \
				SNDRV_PCM_FMTBIT_U16_LE | \
750 751 752 753
				SNDRV_PCM_FMTBIT_S24_LE | \
				SNDRV_PCM_FMTBIT_U24_LE | \
				SNDRV_PCM_FMTBIT_S24_3LE | \
				SNDRV_PCM_FMTBIT_U24_3LE | \
754 755 756
				SNDRV_PCM_FMTBIT_S32_LE | \
				SNDRV_PCM_FMTBIT_U32_LE)

757
static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
758
	{
759
		.name		= "davinci-mcasp.0",
760 761
		.playback	= {
			.channels_min	= 2,
762
			.channels_max	= 32 * 16,
763
			.rates 		= DAVINCI_MCASP_RATES,
764
			.formats	= DAVINCI_MCASP_PCM_FMTS,
765 766 767
		},
		.capture 	= {
			.channels_min 	= 2,
768
			.channels_max	= 32 * 16,
769
			.rates 		= DAVINCI_MCASP_RATES,
770
			.formats	= DAVINCI_MCASP_PCM_FMTS,
771 772 773 774 775
		},
		.ops 		= &davinci_mcasp_dai_ops,

	},
	{
776
		.name		= "davinci-mcasp.1",
777 778 779 780
		.playback 	= {
			.channels_min	= 1,
			.channels_max	= 384,
			.rates		= DAVINCI_MCASP_RATES,
781
			.formats	= DAVINCI_MCASP_PCM_FMTS,
782 783 784 785 786 787
		},
		.ops 		= &davinci_mcasp_dai_ops,
	},

};

788 789 790 791
static const struct snd_soc_component_driver davinci_mcasp_component = {
	.name		= "davinci-mcasp",
};

792 793 794 795 796 797 798 799 800 801 802 803 804 805 806
/* Some HW specific values and defaults. The rest is filled in from DT. */
static struct snd_platform_data dm646x_mcasp_pdata = {
	.tx_dma_offset = 0x400,
	.rx_dma_offset = 0x400,
	.asp_chan_q = EVENTQ_0,
	.version = MCASP_VERSION_1,
};

static struct snd_platform_data da830_mcasp_pdata = {
	.tx_dma_offset = 0x2000,
	.rx_dma_offset = 0x2000,
	.asp_chan_q = EVENTQ_0,
	.version = MCASP_VERSION_2,
};

807
static struct snd_platform_data am33xx_mcasp_pdata = {
808 809 810 811 812 813
	.tx_dma_offset = 0,
	.rx_dma_offset = 0,
	.asp_chan_q = EVENTQ_0,
	.version = MCASP_VERSION_3,
};

814 815 816 817 818 819 820
static struct snd_platform_data dra7_mcasp_pdata = {
	.tx_dma_offset = 0x200,
	.rx_dma_offset = 0x284,
	.asp_chan_q = EVENTQ_0,
	.version = MCASP_VERSION_4,
};

821 822 823
static const struct of_device_id mcasp_dt_ids[] = {
	{
		.compatible = "ti,dm646x-mcasp-audio",
824
		.data = &dm646x_mcasp_pdata,
825 826 827
	},
	{
		.compatible = "ti,da830-mcasp-audio",
828
		.data = &da830_mcasp_pdata,
829
	},
830
	{
831
		.compatible = "ti,am33xx-mcasp-audio",
832
		.data = &am33xx_mcasp_pdata,
833
	},
834 835 836 837
	{
		.compatible = "ti,dra7-mcasp-audio",
		.data = &dra7_mcasp_pdata,
	},
838 839 840 841
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mcasp_dt_ids);

842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881
static int mcasp_reparent_fck(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct clk *gfclk, *parent_clk;
	const char *parent_name;
	int ret;

	if (!node)
		return 0;

	parent_name = of_get_property(node, "fck_parent", NULL);
	if (!parent_name)
		return 0;

	gfclk = clk_get(&pdev->dev, "fck");
	if (IS_ERR(gfclk)) {
		dev_err(&pdev->dev, "failed to get fck\n");
		return PTR_ERR(gfclk);
	}

	parent_clk = clk_get(NULL, parent_name);
	if (IS_ERR(parent_clk)) {
		dev_err(&pdev->dev, "failed to get parent clock\n");
		ret = PTR_ERR(parent_clk);
		goto err1;
	}

	ret = clk_set_parent(gfclk, parent_clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to reparent fck\n");
		goto err2;
	}

err2:
	clk_put(parent_clk);
err1:
	clk_put(gfclk);
	return ret;
}

882 883 884 885 886 887
static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
						struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct snd_platform_data *pdata = NULL;
	const struct of_device_id *match =
888
			of_match_device(mcasp_dt_ids, &pdev->dev);
889
	struct of_phandle_args dma_spec;
890 891 892 893 894 895 896 897 898

	const u32 *of_serial_dir32;
	u32 val;
	int i, ret = 0;

	if (pdev->dev.platform_data) {
		pdata = pdev->dev.platform_data;
		return pdata;
	} else if (match) {
899
		pdata = (struct snd_platform_data *) match->data;
900 901 902 903 904 905 906 907 908 909 910
	} else {
		/* control shouldn't reach here. something is wrong */
		ret = -EINVAL;
		goto nodata;
	}

	ret = of_property_read_u32(np, "op-mode", &val);
	if (ret >= 0)
		pdata->op_mode = val;

	ret = of_property_read_u32(np, "tdm-slots", &val);
911 912 913 914 915 916 917 918
	if (ret >= 0) {
		if (val < 2 || val > 32) {
			dev_err(&pdev->dev,
				"tdm-slots must be in rage [2-32]\n");
			ret = -EINVAL;
			goto nodata;
		}

919
		pdata->tdm_slots = val;
920
	}
921 922 923 924

	of_serial_dir32 = of_get_property(np, "serial-dir", &val);
	val /= sizeof(u32);
	if (of_serial_dir32) {
925 926 927
		u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
						 (sizeof(*of_serial_dir) * val),
						 GFP_KERNEL);
928 929 930 931 932
		if (!of_serial_dir) {
			ret = -ENOMEM;
			goto nodata;
		}

933
		for (i = 0; i < val; i++)
934 935
			of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);

936
		pdata->num_serializer = val;
937 938 939
		pdata->serial_dir = of_serial_dir;
	}

940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961
	ret = of_property_match_string(np, "dma-names", "tx");
	if (ret < 0)
		goto nodata;

	ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
					 &dma_spec);
	if (ret < 0)
		goto nodata;

	pdata->tx_dma_channel = dma_spec.args[0];

	ret = of_property_match_string(np, "dma-names", "rx");
	if (ret < 0)
		goto nodata;

	ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
					 &dma_spec);
	if (ret < 0)
		goto nodata;

	pdata->rx_dma_channel = dma_spec.args[0];

962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988
	ret = of_property_read_u32(np, "tx-num-evt", &val);
	if (ret >= 0)
		pdata->txnumevt = val;

	ret = of_property_read_u32(np, "rx-num-evt", &val);
	if (ret >= 0)
		pdata->rxnumevt = val;

	ret = of_property_read_u32(np, "sram-size-playback", &val);
	if (ret >= 0)
		pdata->sram_size_playback = val;

	ret = of_property_read_u32(np, "sram-size-capture", &val);
	if (ret >= 0)
		pdata->sram_size_capture = val;

	return  pdata;

nodata:
	if (ret < 0) {
		dev_err(&pdev->dev, "Error populating platform data, err %d\n",
			ret);
		pdata = NULL;
	}
	return  pdata;
}

989 990 991
static int davinci_mcasp_probe(struct platform_device *pdev)
{
	struct davinci_pcm_dma_params *dma_data;
992
	struct resource *mem, *ioarea, *res, *dat;
993
	struct snd_platform_data *pdata;
994
	struct davinci_mcasp *mcasp;
995
	int ret;
996

997 998 999 1000 1001
	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
		dev_err(&pdev->dev, "No platform data supplied\n");
		return -EINVAL;
	}

1002
	mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1003
			   GFP_KERNEL);
1004
	if (!mcasp)
1005 1006
		return	-ENOMEM;

1007 1008 1009 1010 1011 1012
	pdata = davinci_mcasp_set_pdata_from_of(pdev);
	if (!pdata) {
		dev_err(&pdev->dev, "no platform data\n");
		return -EINVAL;
	}

1013
	mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1014
	if (!mem) {
1015
		dev_warn(mcasp->dev,
1016 1017 1018 1019 1020 1021
			 "\"mpu\" mem resource not found, using index 0\n");
		mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (!mem) {
			dev_err(&pdev->dev, "no mem resource?\n");
			return -ENODEV;
		}
1022 1023
	}

1024
	ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1025
			resource_size(mem), pdev->name);
1026 1027
	if (!ioarea) {
		dev_err(&pdev->dev, "Audio region already claimed\n");
1028
		return -EBUSY;
1029 1030
	}

1031
	pm_runtime_enable(&pdev->dev);
1032

1033 1034 1035 1036 1037
	ret = pm_runtime_get_sync(&pdev->dev);
	if (IS_ERR_VALUE(ret)) {
		dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
		return ret;
	}
1038

1039 1040
	mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
	if (!mcasp->base) {
1041 1042 1043 1044 1045
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -ENOMEM;
		goto err_release_clk;
	}

1046 1047 1048 1049 1050 1051 1052
	mcasp->op_mode = pdata->op_mode;
	mcasp->tdm_slots = pdata->tdm_slots;
	mcasp->num_serializer = pdata->num_serializer;
	mcasp->serial_dir = pdata->serial_dir;
	mcasp->version = pdata->version;
	mcasp->txnumevt = pdata->txnumevt;
	mcasp->rxnumevt = pdata->rxnumevt;
1053

1054
	mcasp->dev = &pdev->dev;
1055

1056
	dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1057 1058
	if (dat)
		mcasp->dat_port = true;
1059

1060
	dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1061 1062
	dma_data->asp_chan_q = pdata->asp_chan_q;
	dma_data->ram_chan_q = pdata->ram_chan_q;
1063
	dma_data->sram_pool = pdata->sram_pool;
1064
	dma_data->sram_size = pdata->sram_size_playback;
1065 1066 1067 1068
	if (dat)
		dma_data->dma_addr = dat->start;
	else
		dma_data->dma_addr = mem->start + pdata->tx_dma_offset;
1069

1070 1071 1072
	/* Unconditional dmaengine stuff */
	mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = dma_data->dma_addr;

1073
	res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1074 1075 1076 1077
	if (res)
		dma_data->channel = res->start;
	else
		dma_data->channel = pdata->tx_dma_channel;
1078

1079
	dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1080 1081
	dma_data->asp_chan_q = pdata->asp_chan_q;
	dma_data->ram_chan_q = pdata->ram_chan_q;
1082
	dma_data->sram_pool = pdata->sram_pool;
1083
	dma_data->sram_size = pdata->sram_size_capture;
1084 1085 1086 1087 1088
	if (dat)
		dma_data->dma_addr = dat->start;
	else
		dma_data->dma_addr = mem->start + pdata->rx_dma_offset;

1089 1090 1091
	/* Unconditional dmaengine stuff */
	mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = dma_data->dma_addr;

1092 1093 1094 1095 1096 1097 1098
	if (mcasp->version < MCASP_VERSION_3) {
		mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
		/* dma_data->dma_addr is pointing to the data port address */
		mcasp->dat_port = true;
	} else {
		mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
	}
1099 1100

	res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1101 1102 1103 1104
	if (res)
		dma_data->channel = res->start;
	else
		dma_data->channel = pdata->rx_dma_channel;
1105

1106 1107 1108 1109
	/* Unconditional dmaengine stuff */
	mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = "tx";
	mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].filter_data = "rx";

1110
	dev_set_drvdata(&pdev->dev, mcasp);
1111 1112 1113

	mcasp_reparent_fck(pdev);

1114 1115
	ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
					 &davinci_mcasp_dai[pdata->op_mode], 1);
1116 1117

	if (ret != 0)
1118
		goto err_release_clk;
1119

1120 1121 1122 1123 1124 1125
	if (mcasp->version != MCASP_VERSION_4) {
		ret = davinci_soc_platform_register(&pdev->dev);
		if (ret) {
			dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
			goto err_unregister_component;
		}
1126 1127
	}

1128 1129
	return 0;

1130 1131
err_unregister_component:
	snd_soc_unregister_component(&pdev->dev);
1132
err_release_clk:
1133 1134
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
1135 1136 1137 1138 1139
	return ret;
}

static int davinci_mcasp_remove(struct platform_device *pdev)
{
1140
	struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev);
1141

1142
	snd_soc_unregister_component(&pdev->dev);
1143 1144
	if (mcasp->version != MCASP_VERSION_4)
		davinci_soc_platform_unregister(&pdev->dev);
1145 1146 1147

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
1148 1149 1150 1151

	return 0;
}

1152 1153 1154
#ifdef CONFIG_PM_SLEEP
static int davinci_mcasp_suspend(struct device *dev)
{
1155
	struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1156

1157 1158 1159 1160 1161 1162 1163
	mcasp->context.txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
	mcasp->context.rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
	mcasp->context.txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
	mcasp->context.rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
	mcasp->context.aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
	mcasp->context.aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
	mcasp->context.pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
1164 1165 1166 1167 1168 1169

	return 0;
}

static int davinci_mcasp_resume(struct device *dev)
{
1170
	struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1171 1172 1173 1174 1175 1176 1177 1178

	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
1179 1180 1181 1182 1183 1184 1185 1186 1187

	return 0;
}
#endif

SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops,
		  davinci_mcasp_suspend,
		  davinci_mcasp_resume);

1188 1189 1190 1191 1192 1193
static struct platform_driver davinci_mcasp_driver = {
	.probe		= davinci_mcasp_probe,
	.remove		= davinci_mcasp_remove,
	.driver		= {
		.name	= "davinci-mcasp",
		.owner	= THIS_MODULE,
1194
		.pm	= &davinci_mcasp_pm_ops,
1195
		.of_match_table = mcasp_dt_ids,
1196 1197 1198
	},
};

1199
module_platform_driver(davinci_mcasp_driver);
1200 1201 1202 1203

MODULE_AUTHOR("Steve Chen");
MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
MODULE_LICENSE("GPL");