davinci-mcasp.c 29.2 KB
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/*
 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
 *
 * Multi-channel Audio Serial Port Driver
 *
 * Author: Nirmal Pandey <n-pandey@ti.com>,
 *         Suresh Rajashekara <suresh.r@ti.com>
 *         Steve Chen <schen@.mvista.com>
 *
 * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
 * Copyright:   (C) 2009  Texas Instruments, India
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
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#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include "davinci-pcm.h"
#include "davinci-mcasp.h"

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struct davinci_mcasp {
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	struct davinci_pcm_dma_params dma_params[2];
	void __iomem *base;
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	u32 fifo_base;
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	struct device *dev;

	/* McASP specific data */
	int	tdm_slots;
	u8	op_mode;
	u8	num_serializer;
	u8	*serial_dir;
	u8	version;
	u16	bclk_lrclk_ratio;

	/* McASP FIFO related */
	u8	txnumevt;
	u8	rxnumevt;

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	bool	dat_port;

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#ifdef CONFIG_PM_SLEEP
	struct {
		u32	txfmtctl;
		u32	rxfmtctl;
		u32	txfmt;
		u32	rxfmt;
		u32	aclkxctl;
		u32	aclkrctl;
		u32	pdir;
	} context;
#endif
};

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static inline void mcasp_set_bits(void __iomem *reg, u32 val)
{
	__raw_writel(__raw_readl(reg) | val, reg);
}

static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
{
	__raw_writel((__raw_readl(reg) & ~(val)), reg);
}

static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
{
	__raw_writel((__raw_readl(reg) & ~mask) | val, reg);
}

static inline void mcasp_set_reg(void __iomem *reg, u32 val)
{
	__raw_writel(val, reg);
}

static inline u32 mcasp_get_reg(void __iomem *reg)
{
	return (unsigned int)__raw_readl(reg);
}

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static void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
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{
	int i = 0;

	mcasp_set_bits(regs, val);

	/* programming GBLCTL needs to read back from GBLCTL and verfiy */
	/* loop count is to avoid the lock-up */
	for (i = 0; i < 1000; i++) {
		if ((mcasp_get_reg(regs) & val) == val)
			break;
	}

	if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
		printk(KERN_ERR "GBLCTL write error\n");
}

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static void mcasp_start_rx(struct davinci_mcasp *mcasp)
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{
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	mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
	mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
	mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
	mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXBUF_REG, 0);
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	mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
	mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
	mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXBUF_REG, 0);
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	mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
	mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
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}

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static void mcasp_start_tx(struct davinci_mcasp *mcasp)
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{
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	u8 offset = 0, i;
	u32 cnt;

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	mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
	mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
	mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
	mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXBUF_REG, 0);
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	mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
	mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
	mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXBUF_REG, 0);
	for (i = 0; i < mcasp->num_serializer; i++) {
		if (mcasp->serial_dir[i] == TX_MODE) {
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			offset = i;
			break;
		}
	}

	/* wait for TX ready */
	cnt = 0;
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	while (!(mcasp_get_reg(mcasp->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
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		 TXSTATE) && (cnt < 100000))
		cnt++;

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	mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXBUF_REG, 0);
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}

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static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
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{
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	u32 reg;

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	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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		if (mcasp->txnumevt) {	/* enable FIFO */
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			reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
			mcasp_clr_bits(mcasp->base + reg, FIFO_ENABLE);
			mcasp_set_bits(mcasp->base + reg, FIFO_ENABLE);
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		}
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		mcasp_start_tx(mcasp);
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	} else {
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		if (mcasp->rxnumevt) {	/* enable FIFO */
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			reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
			mcasp_clr_bits(mcasp->base + reg, FIFO_ENABLE);
			mcasp_set_bits(mcasp->base + reg, FIFO_ENABLE);
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		}
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		mcasp_start_rx(mcasp);
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	}
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}

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static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
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{
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	mcasp_set_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
	mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
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}

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static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
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{
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	mcasp_set_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
	mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
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}

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static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
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{
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	u32 reg;

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	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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		if (mcasp->txnumevt) {	/* disable FIFO */
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			reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
			mcasp_clr_bits(mcasp->base + reg, FIFO_ENABLE);
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		}
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		mcasp_stop_tx(mcasp);
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	} else {
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		if (mcasp->rxnumevt) {	/* disable FIFO */
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			reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
			mcasp_clr_bits(mcasp->base + reg, FIFO_ENABLE);
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		}
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		mcasp_stop_rx(mcasp);
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	}
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}

static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
					 unsigned int fmt)
{
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	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
	void __iomem *base = mcasp->base;
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	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_B:
	case SND_SOC_DAIFMT_AC97:
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		mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
		mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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		break;
	default:
		/* configure a full-word SYNC pulse (LRCLK) */
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		mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
		mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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		/* make 1st data bit occur one ACLK cycle after the frame sync */
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		mcasp_set_bits(base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
		mcasp_set_bits(base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
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		break;
	}

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	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* codec is clock and frame slave */
		mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
		mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);

		mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
		mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);

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		mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
				ACLKX | ACLKR);
		mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
				AFSX | AFSR);
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		break;
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	case SND_SOC_DAIFMT_CBM_CFS:
		/* codec is clock master and frame slave */
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		mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
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		mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);

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		mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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		mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);

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		mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
				ACLKX | ACLKR);
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		mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
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				AFSX | AFSR);
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		break;
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	case SND_SOC_DAIFMT_CBM_CFM:
		/* codec is clock and frame master */
		mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
		mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);

		mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
		mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);

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		mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
				ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
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		break;

	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_IB_NF:
		mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
		mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);

		mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
		mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
		break;

	case SND_SOC_DAIFMT_NB_IF:
		mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
		mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);

		mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
		mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
		break;

	case SND_SOC_DAIFMT_IB_IF:
		mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
		mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);

		mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
		mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
		break;

	case SND_SOC_DAIFMT_NB_NF:
		mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
		mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);

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		mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
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		mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

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static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
{
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	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
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	switch (div_id) {
	case 0:		/* MCLK divider */
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		mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG,
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			       AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
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		mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_AHCLKRCTL_REG,
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			       AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
		break;

	case 1:		/* BCLK divider */
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		mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG,
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			       ACLKXDIV(div - 1), ACLKXDIV_MASK);
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		mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_ACLKRCTL_REG,
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			       ACLKRDIV(div - 1), ACLKRDIV_MASK);
		break;

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	case 2:		/* BCLK/LRCLK ratio */
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		mcasp->bclk_lrclk_ratio = div;
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		break;

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	default:
		return -EINVAL;
	}

	return 0;
}

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static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
				    unsigned int freq, int dir)
{
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	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
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	if (dir == SND_SOC_CLOCK_OUT) {
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		mcasp_set_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
		mcasp_set_bits(mcasp->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
		mcasp_set_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
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	} else {
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		mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
		mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
		mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
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	}

	return 0;
}

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static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
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				       int word_length)
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{
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	u32 fmt;
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Daniel Mack 已提交
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	u32 tx_rotate = (word_length / 4) & 0x7;
	u32 rx_rotate = (32 - word_length) / 4;
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	u32 mask = (1ULL << word_length) - 1;
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	/*
	 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
	 * callback, take it into account here. That allows us to for example
	 * send 32 bits per channel to the codec, while only 16 of them carry
	 * audio payload.
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	 * The clock ratio is given for a full period of data (for I2S format
	 * both left and right channels), so it has to be divided by number of
	 * tdm-slots (for I2S - divided by 2).
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	 */
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	if (mcasp->bclk_lrclk_ratio)
		word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
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	/* mapping of the XSSZ bit-field as described in the datasheet */
	fmt = (word_length >> 1) - 1;
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	if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
		mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG,
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				RXSSZ(fmt), RXSSZ(0x0F));
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		mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG,
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				TXSSZ(fmt), TXSSZ(0x0F));
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		mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG,
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Daniel Mack 已提交
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				TXROT(tx_rotate), TXROT(7));
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		mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG,
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Daniel Mack 已提交
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				RXROT(rx_rotate), RXROT(7));
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		mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXMASK_REG,
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				mask);
	}

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	mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXMASK_REG, mask);
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	return 0;
}

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static int davinci_hw_common_param(struct davinci_mcasp *mcasp, int stream,
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				    int channels)
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{
	int i;
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	u8 tx_ser = 0;
	u8 rx_ser = 0;
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	u8 ser;
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	u8 slots = mcasp->tdm_slots;
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	u8 max_active_serializers = (channels + slots - 1) / slots;
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	u32 reg;
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	/* Default configuration */
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	mcasp_set_bits(mcasp->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
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	/* All PINS as McASP */
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	mcasp_set_reg(mcasp->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
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	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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		mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
		mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_XEVTCTL_REG,
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				TXDATADMADIS);
	} else {
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		mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
		mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_REVTCTL_REG,
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				RXDATADMADIS);
	}

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	for (i = 0; i < mcasp->num_serializer; i++) {
		mcasp_set_bits(mcasp->base + DAVINCI_MCASP_XRSRCTL_REG(i),
					mcasp->serial_dir[i]);
		if (mcasp->serial_dir[i] == TX_MODE &&
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					tx_ser < max_active_serializers) {
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			mcasp_set_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG,
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					AXR(i));
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			tx_ser++;
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		} else if (mcasp->serial_dir[i] == RX_MODE &&
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					rx_ser < max_active_serializers) {
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			mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG,
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					AXR(i));
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			rx_ser++;
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		} else {
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			mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_XRSRCTL_REG(i),
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					SRMOD_INACTIVE, SRMOD_MASK);
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		}
	}

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	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
		ser = tx_ser;
	else
		ser = rx_ser;

	if (ser < max_active_serializers) {
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		dev_warn(mcasp->dev, "stream has more channels (%d) than are "
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			"enabled in mcasp (%d)\n", channels, ser * slots);
		return -EINVAL;
	}

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	if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
		if (mcasp->txnumevt * tx_ser > 64)
			mcasp->txnumevt = 1;
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		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
		mcasp_mod_bits(mcasp->base + reg, tx_ser, NUMDMA_MASK);
		mcasp_mod_bits(mcasp->base + reg,
			       ((mcasp->txnumevt * tx_ser) << 8), NUMEVT_MASK);
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	}

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	if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
		if (mcasp->rxnumevt * rx_ser > 64)
			mcasp->rxnumevt = 1;
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		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
		mcasp_mod_bits(mcasp->base + reg, rx_ser, NUMDMA_MASK);
		mcasp_mod_bits(mcasp->base + reg,
			       ((mcasp->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
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	}
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	return 0;
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}

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static void davinci_hw_param(struct davinci_mcasp *mcasp, int stream)
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{
	int i, active_slots;
	u32 mask = 0;
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	u32 busel = 0;
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	active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
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	for (i = 0; i < active_slots; i++)
		mask |= (1 << i);

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	mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
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	if (!mcasp->dat_port)
		busel = TXSEL;

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	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		/* bit stream is MSB first  with no delay */
		/* DSP_B mode */
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		mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXTDM_REG, mask);
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		mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG,
			       busel | TXORD);
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		if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
			mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_TXFMCTL_REG,
					FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
508 509
		else
			printk(KERN_ERR "playback tdm slot %d not supported\n",
510
				mcasp->tdm_slots);
511 512 513
	} else {
		/* bit stream is MSB first with no delay */
		/* DSP_B mode */
514 515
		mcasp_set_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG,
			       busel | RXORD);
516
		mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXTDM_REG, mask);
517

518 519 520
		if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
			mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RXFMCTL_REG,
					FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
521 522
		else
			printk(KERN_ERR "capture tdm slot %d not supported\n",
523
				mcasp->tdm_slots);
524 525 526 527
	}
}

/* S/PDIF */
528
static void davinci_hw_dit_param(struct davinci_mcasp *mcasp)
529 530 531
{
	/* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
	   and LSB first */
532
	mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG,
533 534 535
						TXROT(6) | TXSSZ(15));

	/* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
536
	mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXFMCTL_REG,
537 538 539
						AFSXE | FSXMOD(0x180));

	/* Set the TX tdm : for all the slots */
540
	mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
541 542

	/* Set the TX clock controls : div = 1 and internal */
543
	mcasp_set_bits(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG,
544 545
						ACLKXE | TX_ASYNC);

546
	mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
547 548

	/* Only 44100 and 48000 are valid, both have the same setting */
549
	mcasp_set_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
550 551

	/* Enable the DIT */
552
	mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
553 554 555 556 557 558
}

static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
					struct snd_pcm_hw_params *params,
					struct snd_soc_dai *cpu_dai)
{
559
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
560
	struct davinci_pcm_dma_params *dma_params =
561
					&mcasp->dma_params[substream->stream];
562
	int word_length;
563
	u8 fifo_level;
564
	u8 slots = mcasp->tdm_slots;
565
	u8 active_serializers;
566 567 568 569
	int channels;
	struct snd_interval *pcm_channels = hw_param_interval(params,
					SNDRV_PCM_HW_PARAM_CHANNELS);
	channels = pcm_channels->min;
570

571 572
	active_serializers = (channels + slots - 1) / slots;

573
	if (davinci_hw_common_param(mcasp, substream->stream, channels) == -EINVAL)
574
		return -EINVAL;
575
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
576
		fifo_level = mcasp->txnumevt * active_serializers;
577
	else
578
		fifo_level = mcasp->rxnumevt * active_serializers;
579

580 581
	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
		davinci_hw_dit_param(mcasp);
582
	else
583
		davinci_hw_param(mcasp, substream->stream);
584 585

	switch (params_format(params)) {
586
	case SNDRV_PCM_FORMAT_U8:
587 588
	case SNDRV_PCM_FORMAT_S8:
		dma_params->data_type = 1;
589
		word_length = 8;
590 591
		break;

592
	case SNDRV_PCM_FORMAT_U16_LE:
593 594
	case SNDRV_PCM_FORMAT_S16_LE:
		dma_params->data_type = 2;
595
		word_length = 16;
596 597
		break;

598 599 600
	case SNDRV_PCM_FORMAT_U24_3LE:
	case SNDRV_PCM_FORMAT_S24_3LE:
		dma_params->data_type = 3;
601
		word_length = 24;
602 603
		break;

604 605
	case SNDRV_PCM_FORMAT_U24_LE:
	case SNDRV_PCM_FORMAT_S24_LE:
606
	case SNDRV_PCM_FORMAT_U32_LE:
607 608
	case SNDRV_PCM_FORMAT_S32_LE:
		dma_params->data_type = 4;
609
		word_length = 32;
610 611 612 613 614 615
		break;

	default:
		printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
		return -EINVAL;
	}
616

617
	if (mcasp->version == MCASP_VERSION_2 && !fifo_level)
618 619
		dma_params->acnt = 4;
	else
620 621
		dma_params->acnt = dma_params->data_type;

622
	dma_params->fifo_level = fifo_level;
623
	davinci_config_channel_size(mcasp, word_length);
624 625 626 627 628 629 630

	return 0;
}

static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
				     int cmd, struct snd_soc_dai *cpu_dai)
{
631
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
632 633 634 635
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_RESUME:
636 637
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
638
		ret = pm_runtime_get_sync(mcasp->dev);
639
		if (IS_ERR_VALUE(ret))
640 641
			dev_err(mcasp->dev, "pm_runtime_get_sync() failed\n");
		davinci_mcasp_start(mcasp, substream->stream);
642 643 644
		break;

	case SNDRV_PCM_TRIGGER_SUSPEND:
645 646
		davinci_mcasp_stop(mcasp, substream->stream);
		ret = pm_runtime_put_sync(mcasp->dev);
647
		if (IS_ERR_VALUE(ret))
648
			dev_err(mcasp->dev, "pm_runtime_put_sync() failed\n");
649 650 651
		break;

	case SNDRV_PCM_TRIGGER_STOP:
652
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
653
		davinci_mcasp_stop(mcasp, substream->stream);
654 655 656 657 658 659 660 661 662
		break;

	default:
		ret = -EINVAL;
	}

	return ret;
}

663 664 665
static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
				 struct snd_soc_dai *dai)
{
666
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
667

668
	snd_soc_dai_set_dma_data(dai, substream, mcasp->dma_params);
669 670 671
	return 0;
}

672
static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
673
	.startup	= davinci_mcasp_startup,
674 675 676
	.trigger	= davinci_mcasp_trigger,
	.hw_params	= davinci_mcasp_hw_params,
	.set_fmt	= davinci_mcasp_set_dai_fmt,
677
	.set_clkdiv	= davinci_mcasp_set_clkdiv,
678
	.set_sysclk	= davinci_mcasp_set_sysclk,
679 680
};

681 682
#define DAVINCI_MCASP_RATES	SNDRV_PCM_RATE_8000_192000

683 684 685 686
#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
				SNDRV_PCM_FMTBIT_U8 | \
				SNDRV_PCM_FMTBIT_S16_LE | \
				SNDRV_PCM_FMTBIT_U16_LE | \
687 688 689 690
				SNDRV_PCM_FMTBIT_S24_LE | \
				SNDRV_PCM_FMTBIT_U24_LE | \
				SNDRV_PCM_FMTBIT_S24_3LE | \
				SNDRV_PCM_FMTBIT_U24_3LE | \
691 692 693
				SNDRV_PCM_FMTBIT_S32_LE | \
				SNDRV_PCM_FMTBIT_U32_LE)

694
static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
695
	{
696
		.name		= "davinci-mcasp.0",
697 698
		.playback	= {
			.channels_min	= 2,
699
			.channels_max	= 32 * 16,
700
			.rates 		= DAVINCI_MCASP_RATES,
701
			.formats	= DAVINCI_MCASP_PCM_FMTS,
702 703 704
		},
		.capture 	= {
			.channels_min 	= 2,
705
			.channels_max	= 32 * 16,
706
			.rates 		= DAVINCI_MCASP_RATES,
707
			.formats	= DAVINCI_MCASP_PCM_FMTS,
708 709 710 711 712
		},
		.ops 		= &davinci_mcasp_dai_ops,

	},
	{
713
		.name		= "davinci-mcasp.1",
714 715 716 717
		.playback 	= {
			.channels_min	= 1,
			.channels_max	= 384,
			.rates		= DAVINCI_MCASP_RATES,
718
			.formats	= DAVINCI_MCASP_PCM_FMTS,
719 720 721 722 723 724
		},
		.ops 		= &davinci_mcasp_dai_ops,
	},

};

725 726 727 728
static const struct snd_soc_component_driver davinci_mcasp_component = {
	.name		= "davinci-mcasp",
};

729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750
/* Some HW specific values and defaults. The rest is filled in from DT. */
static struct snd_platform_data dm646x_mcasp_pdata = {
	.tx_dma_offset = 0x400,
	.rx_dma_offset = 0x400,
	.asp_chan_q = EVENTQ_0,
	.version = MCASP_VERSION_1,
};

static struct snd_platform_data da830_mcasp_pdata = {
	.tx_dma_offset = 0x2000,
	.rx_dma_offset = 0x2000,
	.asp_chan_q = EVENTQ_0,
	.version = MCASP_VERSION_2,
};

static struct snd_platform_data omap2_mcasp_pdata = {
	.tx_dma_offset = 0,
	.rx_dma_offset = 0,
	.asp_chan_q = EVENTQ_0,
	.version = MCASP_VERSION_3,
};

751 752 753
static const struct of_device_id mcasp_dt_ids[] = {
	{
		.compatible = "ti,dm646x-mcasp-audio",
754
		.data = &dm646x_mcasp_pdata,
755 756 757
	},
	{
		.compatible = "ti,da830-mcasp-audio",
758
		.data = &da830_mcasp_pdata,
759
	},
760
	{
761
		.compatible = "ti,am33xx-mcasp-audio",
762
		.data = &omap2_mcasp_pdata,
763
	},
764 765 766 767 768 769 770 771 772 773
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mcasp_dt_ids);

static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
						struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct snd_platform_data *pdata = NULL;
	const struct of_device_id *match =
774
			of_match_device(mcasp_dt_ids, &pdev->dev);
775
	struct of_phandle_args dma_spec;
776 777 778 779 780 781 782 783 784

	const u32 *of_serial_dir32;
	u32 val;
	int i, ret = 0;

	if (pdev->dev.platform_data) {
		pdata = pdev->dev.platform_data;
		return pdata;
	} else if (match) {
785
		pdata = (struct snd_platform_data *) match->data;
786 787 788 789 790 791 792 793 794 795 796
	} else {
		/* control shouldn't reach here. something is wrong */
		ret = -EINVAL;
		goto nodata;
	}

	ret = of_property_read_u32(np, "op-mode", &val);
	if (ret >= 0)
		pdata->op_mode = val;

	ret = of_property_read_u32(np, "tdm-slots", &val);
797 798 799 800 801 802 803 804
	if (ret >= 0) {
		if (val < 2 || val > 32) {
			dev_err(&pdev->dev,
				"tdm-slots must be in rage [2-32]\n");
			ret = -EINVAL;
			goto nodata;
		}

805
		pdata->tdm_slots = val;
806
	}
807 808 809 810

	of_serial_dir32 = of_get_property(np, "serial-dir", &val);
	val /= sizeof(u32);
	if (of_serial_dir32) {
811 812 813
		u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
						 (sizeof(*of_serial_dir) * val),
						 GFP_KERNEL);
814 815 816 817 818
		if (!of_serial_dir) {
			ret = -ENOMEM;
			goto nodata;
		}

819
		for (i = 0; i < val; i++)
820 821
			of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);

822
		pdata->num_serializer = val;
823 824 825
		pdata->serial_dir = of_serial_dir;
	}

826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847
	ret = of_property_match_string(np, "dma-names", "tx");
	if (ret < 0)
		goto nodata;

	ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
					 &dma_spec);
	if (ret < 0)
		goto nodata;

	pdata->tx_dma_channel = dma_spec.args[0];

	ret = of_property_match_string(np, "dma-names", "rx");
	if (ret < 0)
		goto nodata;

	ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
					 &dma_spec);
	if (ret < 0)
		goto nodata;

	pdata->rx_dma_channel = dma_spec.args[0];

848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874
	ret = of_property_read_u32(np, "tx-num-evt", &val);
	if (ret >= 0)
		pdata->txnumevt = val;

	ret = of_property_read_u32(np, "rx-num-evt", &val);
	if (ret >= 0)
		pdata->rxnumevt = val;

	ret = of_property_read_u32(np, "sram-size-playback", &val);
	if (ret >= 0)
		pdata->sram_size_playback = val;

	ret = of_property_read_u32(np, "sram-size-capture", &val);
	if (ret >= 0)
		pdata->sram_size_capture = val;

	return  pdata;

nodata:
	if (ret < 0) {
		dev_err(&pdev->dev, "Error populating platform data, err %d\n",
			ret);
		pdata = NULL;
	}
	return  pdata;
}

875 876 877
static int davinci_mcasp_probe(struct platform_device *pdev)
{
	struct davinci_pcm_dma_params *dma_data;
878
	struct resource *mem, *ioarea, *res, *dat;
879
	struct snd_platform_data *pdata;
880
	struct davinci_mcasp *mcasp;
881
	int ret;
882

883 884 885 886 887
	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
		dev_err(&pdev->dev, "No platform data supplied\n");
		return -EINVAL;
	}

888
	mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
889
			   GFP_KERNEL);
890
	if (!mcasp)
891 892
		return	-ENOMEM;

893 894 895 896 897 898
	pdata = davinci_mcasp_set_pdata_from_of(pdev);
	if (!pdata) {
		dev_err(&pdev->dev, "no platform data\n");
		return -EINVAL;
	}

899
	mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
900
	if (!mem) {
901
		dev_warn(mcasp->dev,
902 903 904 905 906 907
			 "\"mpu\" mem resource not found, using index 0\n");
		mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (!mem) {
			dev_err(&pdev->dev, "no mem resource?\n");
			return -ENODEV;
		}
908 909
	}

910
	ioarea = devm_request_mem_region(&pdev->dev, mem->start,
911
			resource_size(mem), pdev->name);
912 913
	if (!ioarea) {
		dev_err(&pdev->dev, "Audio region already claimed\n");
914
		return -EBUSY;
915 916
	}

917
	pm_runtime_enable(&pdev->dev);
918

919 920 921 922 923
	ret = pm_runtime_get_sync(&pdev->dev);
	if (IS_ERR_VALUE(ret)) {
		dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
		return ret;
	}
924

925 926
	mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
	if (!mcasp->base) {
927 928 929 930 931
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -ENOMEM;
		goto err_release_clk;
	}

932 933 934 935 936 937 938
	mcasp->op_mode = pdata->op_mode;
	mcasp->tdm_slots = pdata->tdm_slots;
	mcasp->num_serializer = pdata->num_serializer;
	mcasp->serial_dir = pdata->serial_dir;
	mcasp->version = pdata->version;
	mcasp->txnumevt = pdata->txnumevt;
	mcasp->rxnumevt = pdata->rxnumevt;
939

940
	mcasp->dev = &pdev->dev;
941

942
	dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
943 944
	if (dat)
		mcasp->dat_port = true;
945

946
	dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
947 948
	dma_data->asp_chan_q = pdata->asp_chan_q;
	dma_data->ram_chan_q = pdata->ram_chan_q;
949
	dma_data->sram_pool = pdata->sram_pool;
950
	dma_data->sram_size = pdata->sram_size_playback;
951 952 953 954
	if (dat)
		dma_data->dma_addr = dat->start;
	else
		dma_data->dma_addr = mem->start + pdata->tx_dma_offset;
955 956

	res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
957 958 959 960
	if (res)
		dma_data->channel = res->start;
	else
		dma_data->channel = pdata->tx_dma_channel;
961

962
	dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
963 964
	dma_data->asp_chan_q = pdata->asp_chan_q;
	dma_data->ram_chan_q = pdata->ram_chan_q;
965
	dma_data->sram_pool = pdata->sram_pool;
966
	dma_data->sram_size = pdata->sram_size_capture;
967 968 969 970 971 972 973 974 975 976 977 978
	if (dat)
		dma_data->dma_addr = dat->start;
	else
		dma_data->dma_addr = mem->start + pdata->rx_dma_offset;

	if (mcasp->version < MCASP_VERSION_3) {
		mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
		/* dma_data->dma_addr is pointing to the data port address */
		mcasp->dat_port = true;
	} else {
		mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
	}
979 980

	res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
981 982 983 984
	if (res)
		dma_data->channel = res->start;
	else
		dma_data->channel = pdata->rx_dma_channel;
985

986
	dev_set_drvdata(&pdev->dev, mcasp);
987 988
	ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
					 &davinci_mcasp_dai[pdata->op_mode], 1);
989 990

	if (ret != 0)
991
		goto err_release_clk;
992 993 994 995

	ret = davinci_soc_platform_register(&pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
996
		goto err_unregister_component;
997 998
	}

999 1000
	return 0;

1001 1002
err_unregister_component:
	snd_soc_unregister_component(&pdev->dev);
1003
err_release_clk:
1004 1005
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
1006 1007 1008 1009 1010 1011
	return ret;
}

static int davinci_mcasp_remove(struct platform_device *pdev)
{

1012
	snd_soc_unregister_component(&pdev->dev);
1013
	davinci_soc_platform_unregister(&pdev->dev);
1014 1015 1016

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
1017 1018 1019 1020

	return 0;
}

1021 1022 1023
#ifdef CONFIG_PM_SLEEP
static int davinci_mcasp_suspend(struct device *dev)
{
1024 1025
	struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
	void __iomem *base = mcasp->base;
1026

1027 1028 1029 1030 1031 1032 1033
	mcasp->context.txfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_TXFMCTL_REG);
	mcasp->context.rxfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_RXFMCTL_REG);
	mcasp->context.txfmt = mcasp_get_reg(base + DAVINCI_MCASP_TXFMT_REG);
	mcasp->context.rxfmt = mcasp_get_reg(base + DAVINCI_MCASP_RXFMT_REG);
	mcasp->context.aclkxctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKXCTL_REG);
	mcasp->context.aclkrctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKRCTL_REG);
	mcasp->context.pdir = mcasp_get_reg(base + DAVINCI_MCASP_PDIR_REG);
1034 1035 1036 1037 1038 1039

	return 0;
}

static int davinci_mcasp_resume(struct device *dev)
{
1040 1041 1042 1043 1044 1045 1046 1047 1048 1049
	struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
	void __iomem *base = mcasp->base;

	mcasp_set_reg(base + DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl);
	mcasp_set_reg(base + DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl);
	mcasp_set_reg(base + DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt);
	mcasp_set_reg(base + DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt);
	mcasp_set_reg(base + DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl);
	mcasp_set_reg(base + DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl);
	mcasp_set_reg(base + DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
1050 1051 1052 1053 1054 1055 1056 1057 1058

	return 0;
}
#endif

SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops,
		  davinci_mcasp_suspend,
		  davinci_mcasp_resume);

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static struct platform_driver davinci_mcasp_driver = {
	.probe		= davinci_mcasp_probe,
	.remove		= davinci_mcasp_remove,
	.driver		= {
		.name	= "davinci-mcasp",
		.owner	= THIS_MODULE,
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		.pm	= &davinci_mcasp_pm_ops,
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		.of_match_table = mcasp_dt_ids,
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	},
};

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module_platform_driver(davinci_mcasp_driver);
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MODULE_AUTHOR("Steve Chen");
MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
MODULE_LICENSE("GPL");