pci.h 71.1 KB
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/*
 *	pci.h
 *
 *	PCI defines and function prototypes
 *	Copyright 1994, Drew Eckhardt
 *	Copyright 1997--1999 Martin Mares <mj@ucw.cz>
 *
 *	For more information, please consult the following manuals (look at
 *	http://www.pcisig.com/ for how to get them):
 *
 *	PCI BIOS Specification
 *	PCI Local Bus Specification
 *	PCI to PCI Bridge Specification
 *	PCI System Design Guide
 */
#ifndef LINUX_PCI_H
#define LINUX_PCI_H


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#include <linux/mod_devicetable.h>

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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
#include <linux/list.h>
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#include <linux/compiler.h>
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#include <linux/errno.h>
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#include <linux/kobject.h>
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#include <linux/atomic.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/resource_ext.h>
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#include <uapi/linux/pci.h>
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#include <linux/pci_ids.h>

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/*
 * The PCI interface treats multi-function devices as independent
 * devices.  The slot/function address of each device is encoded
 * in a single byte as follows:
 *
 *	7:3 = slot
 *	2:0 = function
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 *
 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
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 * In the interest of not exposing interfaces to user-space unnecessarily,
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 * the following kernel-only defines are being added here.
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 */
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#define PCI_DEVID(bus, devfn)  ((((u16)(bus)) << 8) | (devfn))
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/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)

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/* pci_slot represents a physical slot */
struct pci_slot {
	struct pci_bus *bus;		/* The bus this slot is on */
	struct list_head list;		/* node in list of slots on this bus */
	struct hotplug_slot *hotplug;	/* Hotplug info (migrate over time) */
	unsigned char number;		/* PCI_SLOT(pci_dev->devfn) */
	struct kobject kobj;
};

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static inline const char *pci_slot_name(const struct pci_slot *slot)
{
	return kobject_name(&slot->kobj);
}

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/* File state for mmap()s on /proc/bus/pci/X/Y */
enum pci_mmap_state {
	pci_mmap_io,
	pci_mmap_mem
};

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/*
 *  For PCI devices, the region numbers are assigned this way:
 */
enum {
	/* #0-5: standard PCI resources */
	PCI_STD_RESOURCES,
	PCI_STD_RESOURCE_END = 5,

	/* #6: expansion ROM resource */
	PCI_ROM_RESOURCE,

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	/* device specific resources */
#ifdef CONFIG_PCI_IOV
	PCI_IOV_RESOURCES,
	PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
#endif

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	/* resources assigned to buses behind the bridge */
#define PCI_BRIDGE_RESOURCE_NUM 4

	PCI_BRIDGE_RESOURCES,
	PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
				  PCI_BRIDGE_RESOURCE_NUM - 1,

	/* total resources associated with a PCI device */
	PCI_NUM_RESOURCES,

	/* preserve this for compatibility */
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	DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
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};
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typedef int __bitwise pci_power_t;

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#define PCI_D0		((pci_power_t __force) 0)
#define PCI_D1		((pci_power_t __force) 1)
#define PCI_D2		((pci_power_t __force) 2)
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#define PCI_D3hot	((pci_power_t __force) 3)
#define PCI_D3cold	((pci_power_t __force) 4)
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#define PCI_UNKNOWN	((pci_power_t __force) 5)
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#define PCI_POWER_ERROR	((pci_power_t __force) -1)
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/* Remember to update this when the list above changes! */
extern const char *pci_power_names[];

static inline const char *pci_power_name(pci_power_t state)
{
	return pci_power_names[1 + (int) state];
}

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#define PCI_PM_D2_DELAY		200
#define PCI_PM_D3_WAIT		10
#define PCI_PM_D3COLD_WAIT	100
#define PCI_PM_BUS_WAIT		50
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/** The pci_channel state describes connectivity between the CPU and
 *  the pci device.  If some PCI bus between here and the pci device
 *  has crashed or locked up, this info is reflected here.
 */
typedef unsigned int __bitwise pci_channel_state_t;

enum pci_channel_state {
	/* I/O channel is in normal state */
	pci_channel_io_normal = (__force pci_channel_state_t) 1,

	/* I/O to channel is blocked */
	pci_channel_io_frozen = (__force pci_channel_state_t) 2,

	/* PCI card is dead */
	pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
};

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typedef unsigned int __bitwise pcie_reset_state_t;

enum pcie_reset_state {
	/* Reset is NOT asserted (Use to deassert reset) */
	pcie_deassert_reset = (__force pcie_reset_state_t) 1,

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	/* Use #PERST to reset PCIe device */
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	pcie_warm_reset = (__force pcie_reset_state_t) 2,

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	/* Use PCIe Hot Reset to reset device */
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	pcie_hot_reset = (__force pcie_reset_state_t) 3
};

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typedef unsigned short __bitwise pci_dev_flags_t;
enum pci_dev_flags {
	/* INTX_DISABLE in PCI_COMMAND register disables MSI
	 * generation too.
	 */
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	PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
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	/* Device configuration is irrevocably lost if disabled into D3 */
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	PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
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	/* Provide indication device is assigned by a Virtual Machine Manager */
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	PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
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	/* Flag for quirk use to store if quirk-specific ACS is enabled */
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	PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
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	/* Flag to indicate the device uses dma_alias_devfn */
	PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4),
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	/* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
	PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
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	/* Do not use bus resets for device */
	PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
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	/* Do not use PM reset even if device advertises NoSoftRst- */
	PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
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	/* Get VPD from function 0 VPD */
	PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
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};

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enum pci_irq_reroute_variant {
	INTEL_IRQ_REROUTE_VARIANT = 1,
	MAX_IRQ_REROUTE_VARIANTS = 3
};

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typedef unsigned short __bitwise pci_bus_flags_t;
enum pci_bus_flags {
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	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
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};

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/* These values come from the PCI Express Spec */
enum pcie_link_width {
	PCIE_LNK_WIDTH_RESRV	= 0x00,
	PCIE_LNK_X1		= 0x01,
	PCIE_LNK_X2		= 0x02,
	PCIE_LNK_X4		= 0x04,
	PCIE_LNK_X8		= 0x08,
	PCIE_LNK_X12		= 0x0C,
	PCIE_LNK_X16		= 0x10,
	PCIE_LNK_X32		= 0x20,
	PCIE_LNK_WIDTH_UNKNOWN  = 0xFF,
};

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/* Based on the PCI Hotplug Spec, but some values are made up by us */
enum pci_bus_speed {
	PCI_SPEED_33MHz			= 0x00,
	PCI_SPEED_66MHz			= 0x01,
	PCI_SPEED_66MHz_PCIX		= 0x02,
	PCI_SPEED_100MHz_PCIX		= 0x03,
	PCI_SPEED_133MHz_PCIX		= 0x04,
	PCI_SPEED_66MHz_PCIX_ECC	= 0x05,
	PCI_SPEED_100MHz_PCIX_ECC	= 0x06,
	PCI_SPEED_133MHz_PCIX_ECC	= 0x07,
	PCI_SPEED_66MHz_PCIX_266	= 0x09,
	PCI_SPEED_100MHz_PCIX_266	= 0x0a,
	PCI_SPEED_133MHz_PCIX_266	= 0x0b,
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	AGP_UNKNOWN			= 0x0c,
	AGP_1X				= 0x0d,
	AGP_2X				= 0x0e,
	AGP_4X				= 0x0f,
	AGP_8X				= 0x10,
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	PCI_SPEED_66MHz_PCIX_533	= 0x11,
	PCI_SPEED_100MHz_PCIX_533	= 0x12,
	PCI_SPEED_133MHz_PCIX_533	= 0x13,
	PCIE_SPEED_2_5GT		= 0x14,
	PCIE_SPEED_5_0GT		= 0x15,
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	PCIE_SPEED_8_0GT		= 0x16,
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	PCI_SPEED_UNKNOWN		= 0xff,
};

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struct pci_cap_saved_data {
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	u16 cap_nr;
	bool cap_extended;
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	unsigned int size;
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	u32 data[0];
};

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struct pci_cap_saved_state {
	struct hlist_node next;
	struct pci_cap_saved_data cap;
};

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struct pcie_link_state;
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struct pci_vpd;
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struct pci_sriov;
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struct pci_ats;
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/*
 * The pci_dev structure is used to describe PCI devices.
 */
struct pci_dev {
	struct list_head bus_list;	/* node in per-bus list */
	struct pci_bus	*bus;		/* bus this device is on */
	struct pci_bus	*subordinate;	/* bus this device bridges to */

	void		*sysdata;	/* hook for sys-specific extension */
	struct proc_dir_entry *procent;	/* device entry in /proc/bus/pci */
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	struct pci_slot	*slot;		/* Physical slot this device is in */
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	unsigned int	devfn;		/* encoded device & function index */
	unsigned short	vendor;
	unsigned short	device;
	unsigned short	subsystem_vendor;
	unsigned short	subsystem_device;
	unsigned int	class;		/* 3 bytes: (base,sub,prog-if) */
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	u8		revision;	/* PCI revision, low byte of class word */
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	u8		hdr_type;	/* PCI header type (`multi' flag masked out) */
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	u8		pcie_cap;	/* PCIe capability offset */
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	u8		msi_cap;	/* MSI capability offset */
	u8		msix_cap;	/* MSI-X capability offset */
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	u8		pcie_mpss:3;	/* PCIe Max Payload Size Supported */
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	u8		rom_base_reg;	/* which config register controls the ROM */
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	u8		pin;		/* which interrupt pin this device uses */
	u16		pcie_flags_reg;	/* cached PCIe Capabilities Register */
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	u8		dma_alias_devfn;/* devfn of DMA alias, if any */
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	struct pci_driver *driver;	/* which driver has allocated this device */
	u64		dma_mask;	/* Mask of the bits of bus address this
					   device implements.  Normally this is
					   0xffffffff.  You only need to change
					   this if your device has broken DMA
					   or supports 64-bit transfers.  */

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	struct device_dma_parameters dma_parms;

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	pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
					   this is D0-D3, D0 being fully functional,
					   and D3 being off. */
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	u8		pm_cap;		/* PM capability offset */
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	unsigned int	pme_support:5;	/* Bitmask of states from which PME#
					   can be generated */
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	unsigned int	pme_interrupt:1;
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	unsigned int	pme_poll:1;	/* Poll device's PME status bit */
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	unsigned int	d1_support:1;	/* Low power state D1 is supported */
	unsigned int	d2_support:1;	/* Low power state D2 is supported */
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	unsigned int	no_d1d2:1;	/* D1 and D2 are forbidden */
	unsigned int	no_d3cold:1;	/* D3cold is forbidden */
	unsigned int	d3cold_allowed:1;	/* D3cold is allowed by user */
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	unsigned int	mmio_always_on:1;	/* disallow turning off io/mem
						   decoding during bar sizing */
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	unsigned int	wakeup_prepared:1;
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	unsigned int	runtime_d3cold:1;	/* whether go through runtime
						   D3cold, not set for devices
						   powered on/off by the
						   corresponding bridge */
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	unsigned int	ignore_hotplug:1;	/* Ignore hotplug events */
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	unsigned int	d3_delay;	/* D3->D0 transition time in ms */
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	unsigned int	d3cold_delay;	/* D3cold->D0 transition time in ms */
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#ifdef CONFIG_PCIEASPM
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	struct pcie_link_state	*link_state;	/* ASPM link state */
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#endif

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	pci_channel_state_t error_state;	/* current connectivity state */
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	struct	device	dev;		/* Generic device interface */

	int		cfg_size;	/* Size of configuration space */

	/*
	 * Instead of touching interrupt line and base address registers
	 * directly, use the values stored here. They might be different!
	 */
	unsigned int	irq;
	struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */

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	bool match_driver;		/* Skip attaching driver */
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	/* These fields are used by common fixups */
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	unsigned int	transparent:1;	/* Subtractive decode PCI bridge */
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	unsigned int	multifunction:1;/* Part of multi-function device */
	/* keep track of device state */
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	unsigned int	is_added:1;
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	unsigned int	is_busmaster:1; /* device is busmaster */
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	unsigned int	no_msi:1;	/* device may not use msi */
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	unsigned int	no_64bit_msi:1; /* device may only use 32-bit MSIs */
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	unsigned int	block_cfg_access:1;	/* config space access is blocked */
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	unsigned int	broken_parity_status:1;	/* Device generates false positive parity */
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	unsigned int	irq_reroute_variant:2;	/* device needs IRQ rerouting variant */
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	unsigned int	msi_enabled:1;
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	unsigned int	msix_enabled:1;
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	unsigned int	ari_enabled:1;	/* ARI forwarding */
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	unsigned int	ats_enabled:1;	/* Address Translation Service */
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	unsigned int	is_managed:1;
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	unsigned int    needs_freset:1; /* Dev requires fundamental reset */
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	unsigned int	state_saved:1;
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	unsigned int	is_physfn:1;
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	unsigned int	is_virtfn:1;
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	unsigned int	reset_fn:1;
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	unsigned int    is_hotplug_bridge:1;
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	unsigned int    __aer_firmware_first_valid:1;
	unsigned int	__aer_firmware_first:1;
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	unsigned int	broken_intx_masking:1;
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	unsigned int	io_window_1k:1;	/* Intel P2P bridge 1K I/O windows */
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	unsigned int	irq_managed:1;
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	unsigned int	has_secondary_link:1;
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	unsigned int	non_compliant_bars:1;	/* broken BARs; ignore them */
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	pci_dev_flags_t dev_flags;
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	atomic_t	enable_cnt;	/* pci_enable_device has been called */
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	u32		saved_config_space[16]; /* config space saved at suspend time */
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	struct hlist_head saved_cap_space;
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	struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
	int rom_attr_enabled;		/* has display of the rom attribute been enabled? */
	struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
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	struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
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#ifdef CONFIG_PCI_MSI
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	const struct attribute_group **msi_irq_groups;
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#endif
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	struct pci_vpd *vpd;
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#ifdef CONFIG_PCI_ATS
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	union {
		struct pci_sriov *sriov;	/* SR-IOV capability related */
		struct pci_dev *physfn;	/* the PF this VF is associated with */
	};
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	u16		ats_cap;	/* ATS Capability offset */
	u8		ats_stu;	/* ATS Smallest Translation Unit */
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	atomic_t	ats_ref_cnt;	/* number of VFs with ATS enabled */
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#endif
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	phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
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	size_t romlen; /* Length of ROM if it's not from the BAR */
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	char *driver_override; /* Driver name to force a match */
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};

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static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
{
#ifdef CONFIG_PCI_IOV
	if (dev->is_virtfn)
		dev = dev->physfn;
#endif
	return dev;
}

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struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
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#define	to_pci_dev(n) container_of(n, struct pci_dev, dev)
#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)

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static inline int pci_channel_offline(struct pci_dev *pdev)
{
	return (pdev->error_state != pci_channel_io_normal);
}

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struct pci_host_bridge {
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	struct device dev;
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	struct pci_bus *bus;		/* root bus */
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	struct list_head windows;	/* resource_entry */
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	void (*release_fn)(struct pci_host_bridge *);
	void *release_data;
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	unsigned int ignore_reset_delay:1;	/* for entire hierarchy */
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	/* Resource alignment requirements */
	resource_size_t (*align_resource)(struct pci_dev *dev,
			const struct resource *res,
			resource_size_t start,
			resource_size_t size,
			resource_size_t align);
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};
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#define	to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
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struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);

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void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
		     void (*release_fn)(struct pci_host_bridge *),
		     void *release_data);
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int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);

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/*
 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
 * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
 * buses below host bridges or subtractive decode bridges) go in the list.
 * Use pci_bus_for_each_resource() to iterate through all the resources.
 */

/*
 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
 * and there's no way to program the bridge with the details of the window.
 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
 * decode bit set, because they are explicit and can be programmed with _SRS.
 */
#define PCI_SUBTRACTIVE_DECODE	0x1

struct pci_bus_resource {
	struct list_head list;
	struct resource *res;
	unsigned int flags;
};
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#define PCI_REGION_FLAG_MASK	0x0fU	/* These bits of resource flags tell us the PCI region flags */
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struct pci_bus {
	struct list_head node;		/* node in list of buses */
	struct pci_bus	*parent;	/* parent bus this bridge is on */
	struct list_head children;	/* list of child buses */
	struct list_head devices;	/* list of devices on this bus */
	struct pci_dev	*self;		/* bridge device as seen by parent */
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	struct list_head slots;		/* list of slots on this bus;
					   protected by pci_slot_mutex */
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	struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
	struct list_head resources;	/* address space routed to this bus */
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	struct resource busn_res;	/* bus numbers routed to this bus */
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	struct pci_ops	*ops;		/* configuration access functions */
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	struct msi_controller *msi;	/* MSI controller */
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	void		*sysdata;	/* hook for sys-specific extension */
	struct proc_dir_entry *procdir;	/* directory entry in /proc/bus/pci */

	unsigned char	number;		/* bus number */
	unsigned char	primary;	/* number of primary bridge */
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	unsigned char	max_bus_speed;	/* enum pci_bus_speed */
	unsigned char	cur_bus_speed;	/* enum pci_bus_speed */
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#ifdef CONFIG_PCI_DOMAINS_GENERIC
	int		domain_nr;
#endif
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	char		name[48];

	unsigned short  bridge_ctl;	/* manage NO_ISA/FBB/et al behaviors */
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	pci_bus_flags_t bus_flags;	/* inherited by child buses */
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	struct device		*bridge;
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	struct device		dev;
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	struct bin_attribute	*legacy_io; /* legacy I/O for this bus */
	struct bin_attribute	*legacy_mem; /* legacy mem */
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	unsigned int		is_added:1;
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};

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#define to_pci_bus(n)	container_of(n, struct pci_bus, dev)
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/*
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 * Returns true if the PCI bus is root (behind host-PCI bridge),
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 * false otherwise
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 *
 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
 * This is incorrect because "virtual" buses added for SR-IOV (via
 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
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 */
static inline bool pci_is_root_bus(struct pci_bus *pbus)
{
	return !(pbus->parent);
}

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/**
 * pci_is_bridge - check if the PCI device is a bridge
 * @dev: PCI device
 *
 * Return true if the PCI device is bridge whether it has subordinate
 * or not.
 */
static inline bool pci_is_bridge(struct pci_dev *dev)
{
	return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
		dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
}

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static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
{
	dev = pci_physfn(dev);
	if (pci_is_root_bus(dev->bus))
		return NULL;

	return dev->bus->self;
}

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struct device *pci_get_host_bridge_device(struct pci_dev *dev);
void pci_put_host_bridge_device(struct device *dev);

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#ifdef CONFIG_PCI_MSI
static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
{
	return pci_dev->msi_enabled || pci_dev->msix_enabled;
}
#else
static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
#endif

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/*
 * Error values that may be returned by PCI functions.
 */
#define PCIBIOS_SUCCESSFUL		0x00
#define PCIBIOS_FUNC_NOT_SUPPORTED	0x81
#define PCIBIOS_BAD_VENDOR_ID		0x83
#define PCIBIOS_DEVICE_NOT_FOUND	0x86
#define PCIBIOS_BAD_REGISTER_NUMBER	0x87
#define PCIBIOS_SET_FAILED		0x88
#define PCIBIOS_BUFFER_TOO_SMALL	0x89

547
/*
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 * Translate above to generic errno for passing back through non-PCI code.
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 */
static inline int pcibios_err_to_errno(int err)
{
	if (err <= PCIBIOS_SUCCESSFUL)
		return err; /* Assume already errno */

	switch (err) {
	case PCIBIOS_FUNC_NOT_SUPPORTED:
		return -ENOENT;
	case PCIBIOS_BAD_VENDOR_ID:
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		return -ENOTTY;
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	case PCIBIOS_DEVICE_NOT_FOUND:
		return -ENODEV;
	case PCIBIOS_BAD_REGISTER_NUMBER:
		return -EFAULT;
	case PCIBIOS_SET_FAILED:
		return -EIO;
	case PCIBIOS_BUFFER_TOO_SMALL:
		return -ENOSPC;
	}

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	return -ERANGE;
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}

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/* Low-level architecture-dependent routines */

struct pci_ops {
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	int (*add_bus)(struct pci_bus *bus);
	void (*remove_bus)(struct pci_bus *bus);
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	void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
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	int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
	int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
};

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/*
 * ACPI needs to be able to access PCI config space before we've done a
 * PCI bus scan and created pci_bus structures.
 */
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int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
		 int reg, int len, u32 *val);
int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
		  int reg, int len, u32 val);
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#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
typedef u64 pci_bus_addr_t;
#else
typedef u32 pci_bus_addr_t;
#endif

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struct pci_bus_region {
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	pci_bus_addr_t start;
	pci_bus_addr_t end;
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};

struct pci_dynids {
	spinlock_t lock;            /* protects list, index */
	struct list_head list;      /* for IDs added at runtime */
};

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/*
 * PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
 * a set of callbacks in struct pci_error_handlers, that device driver
 * will be notified of PCI bus errors, and will be driven to recovery
 * when an error occurs.
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 */

typedef unsigned int __bitwise pci_ers_result_t;

enum pci_ers_result {
	/* no result/none/not supported in device driver */
	PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,

	/* Device driver can recover without slot reset */
	PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,

	/* Device driver wants slot to be reset. */
	PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,

	/* Device has completely failed, is unrecoverable */
	PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,

	/* Device driver is fully recovered and operational */
	PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
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	/* No AER capabilities registered for the driver */
	PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
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};

/* PCI bus error event callbacks */
639
struct pci_error_handlers {
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	/* PCI bus error detected on this device */
	pci_ers_result_t (*error_detected)(struct pci_dev *dev,
642
					   enum pci_channel_state error);
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	/* MMIO has been re-enabled, but not DMA */
	pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);

	/* PCI Express link has been reset */
	pci_ers_result_t (*link_reset)(struct pci_dev *dev);

	/* PCI slot has been reset */
	pci_ers_result_t (*slot_reset)(struct pci_dev *dev);

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	/* PCI function reset prepare or completed */
	void (*reset_notify)(struct pci_dev *dev, bool prepare);

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	/* Device driver may resume normal operations */
	void (*resume)(struct pci_dev *dev);
};


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struct module;
struct pci_driver {
	struct list_head node;
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	const char *name;
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	const struct pci_device_id *id_table;	/* must be non-NULL for probe to be called */
	int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);	/* New device inserted */
	void (*remove) (struct pci_dev *dev);	/* Device removed (NULL if not a hot-plug capable driver) */
	int  (*suspend) (struct pci_dev *dev, pm_message_t state);	/* Device suspended */
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	int  (*suspend_late) (struct pci_dev *dev, pm_message_t state);
	int  (*resume_early) (struct pci_dev *dev);
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	int  (*resume) (struct pci_dev *dev);	                /* Device woken up */
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	void (*shutdown) (struct pci_dev *dev);
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	int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
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	const struct pci_error_handlers *err_handler;
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	struct device_driver	driver;
	struct pci_dynids dynids;
};

679
#define	to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
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/**
682
 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
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 * @_table: device table name
 *
685
 * This macro is deprecated and should not be used in new code.
686
 */
687
#define DEFINE_PCI_DEVICE_TABLE(_table) \
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	const struct pci_device_id _table[]
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/**
 * PCI_DEVICE - macro used to describe a specific pci device
 * @vend: the 16 bit PCI Vendor ID
 * @dev: the 16 bit PCI Device ID
 *
 * This macro is used to create a struct pci_device_id that matches a
 * specific device.  The subvendor and subdevice fields will be set to
 * PCI_ANY_ID.
 */
#define PCI_DEVICE(vend,dev) \
	.vendor = (vend), .device = (dev), \
	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID

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/**
 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
 * @vend: the 16 bit PCI Vendor ID
 * @dev: the 16 bit PCI Device ID
 * @subvend: the 16 bit PCI Subvendor ID
 * @subdev: the 16 bit PCI Subdevice ID
 *
 * This macro is used to create a struct pci_device_id that matches a
 * specific device with subsystem information.
 */
#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
	.vendor = (vend), .device = (dev), \
	.subvendor = (subvend), .subdevice = (subdev)

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/**
 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
 * @dev_class: the class, subclass, prog-if triple for this device
 * @dev_class_mask: the class mask for this device
 *
 * This macro is used to create a struct pci_device_id that matches a
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 * specific PCI class.  The vendor, device, subvendor, and subdevice
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 * fields will be set to PCI_ANY_ID.
 */
#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
	.class = (dev_class), .class_mask = (dev_class_mask), \
	.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID

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/**
 * PCI_VDEVICE - macro used to describe a specific pci device in short form
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 * @vend: the vendor name
 * @dev: the 16 bit PCI Device ID
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 *
 * This macro is used to create a struct pci_device_id that matches a
 * specific PCI device.  The subvendor, and subdevice fields will be set
 * to PCI_ANY_ID. The macro allows the next field to follow as the device
 * private data.
 */

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#define PCI_VDEVICE(vend, dev) \
	.vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
745

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enum {
	PCI_REASSIGN_ALL_RSRC	= 0x00000001,	/* ignore firmware setup */
	PCI_REASSIGN_ALL_BUS	= 0x00000002,	/* reassign all bus numbers */
	PCI_PROBE_ONLY		= 0x00000004,	/* use existing setup */
	PCI_CAN_SKIP_ISA_ALIGN	= 0x00000008,	/* don't do ISA alignment */
	PCI_ENABLE_PROC_DOMAINS	= 0x00000010,	/* enable domains in /proc */
	PCI_COMPAT_DOMAIN_0	= 0x00000020,	/* ... except domain 0 */
	PCI_SCAN_ALL_PCIE_DEVS	= 0x00000040,	/* scan all, not just dev 0 */
};

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/* these external functions are only available when PCI support is enabled */
#ifdef CONFIG_PCI

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extern unsigned int pci_flags;

static inline void pci_set_flags(int flags) { pci_flags = flags; }
static inline void pci_add_flags(int flags) { pci_flags |= flags; }
static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
static inline int pci_has_flag(int flag) { return pci_flags & flag; }

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void pcie_bus_configure_settings(struct pci_bus *bus);
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enum pcie_bus_config_types {
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	PCIE_BUS_TUNE_OFF,	/* don't touch MPS at all */
	PCIE_BUS_DEFAULT,	/* ensure MPS matches upstream bridge */
	PCIE_BUS_SAFE,		/* use largest MPS boot-time devices support */
	PCIE_BUS_PERFORMANCE,	/* use MPS and MRRS for best performance */
	PCIE_BUS_PEER2PEER,	/* set MPS = 128 for all devices */
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};

extern enum pcie_bus_config_types pcie_bus_config;

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extern struct bus_type pci_bus_type;

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/* Do NOT directly access these two variables, unless you are arch-specific PCI
 * code, or PCI core code. */
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extern struct list_head pci_root_buses;	/* list of all known PCI buses */
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/* Some device drivers need know if PCI is initiated */
784
int no_pci_devices(void);
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void pcibios_resource_survey_bus(struct pci_bus *bus);
787
void pcibios_bus_add_device(struct pci_dev *pdev);
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void pcibios_add_bus(struct pci_bus *bus);
void pcibios_remove_bus(struct pci_bus *bus);
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void pcibios_fixup_bus(struct pci_bus *);
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int __must_check pcibios_enable_device(struct pci_dev *, int mask);
792
/* Architecture-specific versions may override this (weak) */
793
char *pcibios_setup(char *str);
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/* Used only when drivers/pci/setup.c is used */
796
resource_size_t pcibios_align_resource(void *, const struct resource *,
797
				resource_size_t,
798
				resource_size_t);
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void pcibios_update_irq(struct pci_dev *, int irq);

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/* Weak but can be overriden by arch */
void pci_fixup_cardbus(struct pci_bus *);

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/* Generic PCI functions used internally */

806
void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
807
			     struct resource *res);
808
void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
809
			     struct pci_bus_region *region);
810
void pcibios_scan_specific_bus(int busn);
811
struct pci_bus *pci_find_bus(int domain, int busnr);
812
void pci_bus_add_devices(const struct pci_bus *bus);
813
struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
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struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
				    struct pci_ops *ops, void *sysdata,
				    struct list_head *resources);
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int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
void pci_bus_release_busn_res(struct pci_bus *b);
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struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
				      struct pci_ops *ops, void *sysdata,
				      struct list_head *resources,
				      struct msi_controller *msi);
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struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
825 826
					     struct pci_ops *ops, void *sysdata,
					     struct list_head *resources);
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struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
				int busnr);
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void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
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struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
831 832
				 const char *name,
				 struct hotplug_slot *hotplug);
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void pci_destroy_slot(struct pci_slot *slot);
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#ifdef CONFIG_SYSFS
void pci_dev_assign_slot(struct pci_dev *dev);
#else
static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
#endif
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int pci_scan_slot(struct pci_bus *bus, int devfn);
840
struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
841
void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
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unsigned int pci_scan_child_bus(struct pci_bus *bus);
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void pci_bus_add_device(struct pci_dev *dev);
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void pci_read_bridge_bases(struct pci_bus *child);
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struct resource *pci_find_parent_resource(const struct pci_dev *dev,
					  struct resource *res);
847
struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
848
u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
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int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
850
u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
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struct pci_dev *pci_dev_get(struct pci_dev *dev);
void pci_dev_put(struct pci_dev *dev);
void pci_remove_bus(struct pci_bus *b);
void pci_stop_and_remove_bus_device(struct pci_dev *dev);
855
void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
856 857
void pci_stop_root_bus(struct pci_bus *bus);
void pci_remove_root_bus(struct pci_bus *bus);
858
void pci_setup_cardbus(struct pci_bus *bus);
859
void pci_sort_breadthfirst(void);
860 861 862
#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
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/* Generic PCI functions exported to card drivers */

866 867 868 869 870 871 872
enum pci_lost_interrupt_reason {
	PCI_LOST_IRQ_NO_INFORMATION = 0,
	PCI_LOST_IRQ_DISABLE_MSI,
	PCI_LOST_IRQ_DISABLE_MSIX,
	PCI_LOST_IRQ_DISABLE_ACPI,
};
enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
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int pci_find_capability(struct pci_dev *dev, int cap);
int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
int pci_find_ext_capability(struct pci_dev *dev, int cap);
876
int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
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int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
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struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
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881 882
struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
				struct pci_dev *from);
883
struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
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				unsigned int ss_vendor, unsigned int ss_device,
885
				struct pci_dev *from);
886
struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
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struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
					    unsigned int devfn);
static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
						   unsigned int devfn)
{
	return pci_get_domain_bus_and_slot(0, bus, devfn);
}
894
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
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int pci_dev_present(const struct pci_device_id *ids);

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int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
			     int where, u8 *val);
int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
			     int where, u16 *val);
int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
			      int where, u32 *val);
int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
			      int where, u8 val);
int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
			      int where, u16 val);
int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
			       int where, u32 val);
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int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
			    int where, int size, u32 *val);
int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
			    int where, int size, u32 val);
int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
			      int where, int size, u32 *val);
int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
			       int where, int size, u32 val);

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struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
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921
static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
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{
923
	return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
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}
925
static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
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{
927
	return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
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}
929
static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
930
					u32 *val)
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{
932
	return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
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}
934
static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
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{
936
	return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
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}
938
static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
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{
940
	return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
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}
942
static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
943
					 u32 val)
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{
945
	return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
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946 947
}

948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
				       u16 clear, u16 set);
int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
					u32 clear, u32 set);

static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
					   u16 set)
{
	return pcie_capability_clear_and_set_word(dev, pos, 0, set);
}

static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
					    u32 set)
{
	return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
}

static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
					     u16 clear)
{
	return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
}

static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
					      u32 clear)
{
	return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
}

981 982 983 984 985 986 987 988
/* user-space driven config access */
int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);

989
int __must_check pci_enable_device(struct pci_dev *dev);
990 991
int __must_check pci_enable_device_io(struct pci_dev *dev);
int __must_check pci_enable_device_mem(struct pci_dev *dev);
992
int __must_check pci_reenable_device(struct pci_dev *);
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Tejun Heo 已提交
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int __must_check pcim_enable_device(struct pci_dev *pdev);
void pcim_pin_device(struct pci_dev *pdev);

996 997 998 999 1000
static inline int pci_is_enabled(struct pci_dev *pdev)
{
	return (atomic_read(&pdev->enable_cnt) > 0);
}

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1001 1002 1003 1004 1005
static inline int pci_is_managed(struct pci_dev *pdev)
{
	return pdev->is_managed;
}

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void pci_disable_device(struct pci_dev *dev);
1007 1008

extern unsigned int pcibios_max_latency;
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void pci_set_master(struct pci_dev *dev);
1010
void pci_clear_master(struct pci_dev *dev);
1011

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Brian King 已提交
1012
int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
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Tejun Heo 已提交
1013
int pci_set_cacheline_size(struct pci_dev *dev);
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1014
#define HAVE_PCI_SET_MWI
1015
int __must_check pci_set_mwi(struct pci_dev *dev);
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1016
int pci_try_set_mwi(struct pci_dev *dev);
L
Linus Torvalds 已提交
1017
void pci_clear_mwi(struct pci_dev *dev);
B
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1018
void pci_intx(struct pci_dev *dev, int enable);
1019 1020 1021
bool pci_intx_mask_supported(struct pci_dev *dev);
bool pci_check_and_mask_intx(struct pci_dev *dev);
bool pci_check_and_unmask_intx(struct pci_dev *dev);
1022
int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1023
int pci_wait_for_pending_transaction(struct pci_dev *dev);
1024 1025 1026
int pcix_get_max_mmrbc(struct pci_dev *dev);
int pcix_get_mmrbc(struct pci_dev *dev);
int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1027
int pcie_get_readrq(struct pci_dev *dev);
1028
int pcie_set_readrq(struct pci_dev *dev, int rq);
1029 1030
int pcie_get_mps(struct pci_dev *dev);
int pcie_set_mps(struct pci_dev *dev, int mps);
1031 1032
int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
			  enum pcie_link_width *width);
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1033
int __pci_reset_function(struct pci_dev *dev);
1034
int __pci_reset_function_locked(struct pci_dev *dev);
1035
int pci_reset_function(struct pci_dev *dev);
1036
int pci_try_reset_function(struct pci_dev *dev);
1037
int pci_probe_reset_slot(struct pci_slot *slot);
1038
int pci_reset_slot(struct pci_slot *slot);
1039
int pci_try_reset_slot(struct pci_slot *slot);
1040
int pci_probe_reset_bus(struct pci_bus *bus);
1041
int pci_reset_bus(struct pci_bus *bus);
1042
int pci_try_reset_bus(struct pci_bus *bus);
1043 1044
void pci_reset_secondary_bus(struct pci_dev *dev);
void pcibios_reset_secondary_bus(struct pci_dev *dev);
1045
void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1046
void pci_update_resource(struct pci_dev *dev, int resno);
1047
int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1048
int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1049
int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1050
bool pci_device_is_present(struct pci_dev *pdev);
1051
void pci_ignore_hotplug(struct pci_dev *dev);
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1052 1053

/* ROM control related routines */
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int pci_enable_rom(struct pci_dev *pdev);
void pci_disable_rom(struct pci_dev *pdev);
1056
void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
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void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1058
size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1059
void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
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1060 1061 1062

/* Power management related routines */
int pci_save_state(struct pci_dev *dev);
1063
void pci_restore_state(struct pci_dev *dev);
1064
struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1065 1066
int pci_load_saved_state(struct pci_dev *dev,
			 struct pci_saved_state *state);
1067 1068
int pci_load_and_free_saved_state(struct pci_dev *dev,
				  struct pci_saved_state **state);
1069 1070 1071 1072 1073 1074
struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
						   u16 cap);
int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
				u16 cap, unsigned int size);
1075
int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1076 1077
int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1078
bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1079
void pci_pme_active(struct pci_dev *dev, bool enable);
1080 1081
int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
		      bool runtime, bool enable);
1082
int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1083 1084
int pci_prepare_to_sleep(struct pci_dev *dev);
int pci_back_from_sleep(struct pci_dev *dev);
1085
bool pci_dev_run_wake(struct pci_dev *dev);
1086 1087
bool pci_check_pme_status(struct pci_dev *dev);
void pci_pme_wakeup_bus(struct pci_bus *bus);
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1089 1090 1091 1092 1093
static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
				  bool enable)
{
	return __pci_enable_wake(dev, state, false, enable);
}
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Linus Torvalds 已提交
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1095 1096 1097 1098
/* PCI Virtual Channel */
int pci_save_vc_state(struct pci_dev *dev);
void pci_restore_vc_state(struct pci_dev *dev);
void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1099

1100 1101 1102 1103
/* For use by arch with custom probe code */
void set_pcie_port_type(struct pci_dev *pdev);
void set_pcie_hotplug_bridge(struct pci_dev *pdev);

1104
/* Functions for PCI Hotplug drivers to use */
1105
int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1106
unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
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1107
unsigned int pci_rescan_bus(struct pci_bus *bus);
1108 1109
void pci_lock_rescan_remove(void);
void pci_unlock_rescan_remove(void);
1110

1111 1112 1113 1114
/* Vital product data routines */
ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);

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1115
/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1116
resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1117
void pci_bus_assign_resources(const struct pci_bus *bus);
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void pci_bus_size_bridges(struct pci_bus *bus);
int pci_claim_resource(struct pci_dev *, int);
1120
int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
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1121
void pci_assign_unassigned_resources(void);
1122
void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1123
void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1124
void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
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1125
void pdev_enable_device(struct pci_dev *);
1126
int pci_enable_resources(struct pci_dev *, int mask);
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1127
void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1128
		    int (*)(const struct pci_dev *, u8, u8));
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1129
#define HAVE_PCI_REQ_REGIONS	2
1130
int __must_check pci_request_regions(struct pci_dev *, const char *);
1131
int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
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void pci_release_regions(struct pci_dev *);
1133
int __must_check pci_request_region(struct pci_dev *, int, const char *);
1134
int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
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void pci_release_region(struct pci_dev *, int);
1136
int pci_request_selected_regions(struct pci_dev *, int, const char *);
1137
int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1138
void pci_release_selected_regions(struct pci_dev *, int);
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1139 1140

/* drivers/pci/bus.c */
1141 1142
struct pci_bus *pci_bus_get(struct pci_bus *bus);
void pci_bus_put(struct pci_bus *bus);
1143
void pci_add_resource(struct list_head *resources, struct resource *res);
1144 1145
void pci_add_resource_offset(struct list_head *resources, struct resource *res,
			     resource_size_t offset);
1146
void pci_free_resource_list(struct list_head *resources);
1147 1148 1149 1150
void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
void pci_bus_remove_resources(struct pci_bus *bus);

1151
#define pci_bus_for_each_resource(bus, res, i)				\
1152 1153 1154
	for (i = 0;							\
	    (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
	     i++)
1155

1156 1157 1158
int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
			struct resource *res, resource_size_t size,
			resource_size_t align, resource_size_t min,
1159
			unsigned long type_mask,
1160 1161
			resource_size_t (*alignf)(void *,
						  const struct resource *,
1162 1163
						  resource_size_t,
						  resource_size_t),
1164
			void *alignf_data);
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Linus Torvalds 已提交
1165

1166 1167 1168

int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);

Y
Yinghai Lu 已提交
1169
static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1170 1171 1172 1173 1174 1175 1176
{
	struct pci_bus_region region;

	pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
	return region.start;
}

1177
/* Proper probing supporting hot-pluggable devices */
1178 1179
int __must_check __pci_register_driver(struct pci_driver *, struct module *,
				       const char *mod_name);
1180 1181 1182 1183 1184 1185

/*
 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
 */
#define pci_register_driver(driver)		\
	__pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1186

1187
void pci_unregister_driver(struct pci_driver *dev);
1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200

/**
 * module_pci_driver() - Helper macro for registering a PCI driver
 * @__pci_driver: pci_driver struct
 *
 * Helper macro for PCI drivers which do not do anything special in module
 * init/exit. This eliminates a lot of boilerplate. Each module may only
 * use this macro once, and calling it replaces module_init() and module_exit()
 */
#define module_pci_driver(__pci_driver) \
	module_driver(__pci_driver, pci_register_driver, \
		       pci_unregister_driver)

1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211
/**
 * builtin_pci_driver() - Helper macro for registering a PCI driver
 * @__pci_driver: pci_driver struct
 *
 * Helper macro for PCI drivers which do not do anything special in their
 * init code. This eliminates a lot of boilerplate. Each driver may only
 * use this macro once, and calling it replaces device_initcall(...)
 */
#define builtin_pci_driver(__pci_driver) \
	builtin_driver(__pci_driver, pci_register_driver)

1212
struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
T
Tejun Heo 已提交
1213 1214 1215 1216 1217
int pci_add_dynid(struct pci_driver *drv,
		  unsigned int vendor, unsigned int device,
		  unsigned int subvendor, unsigned int subdevice,
		  unsigned int class, unsigned int class_mask,
		  unsigned long driver_data);
1218 1219 1220 1221
const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
					 struct pci_dev *dev);
int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
		    int pass);
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Linus Torvalds 已提交
1222

1223
void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1224
		  void *userdata);
1225
int pci_cfg_space_size(struct pci_dev *dev);
1226
unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1227
void pci_setup_bridge(struct pci_bus *bus);
1228 1229
resource_size_t pcibios_window_alignment(struct pci_bus *bus,
					 unsigned long type);
1230
resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1231

1232 1233 1234
#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)

1235
int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1236
		      unsigned int command_bits, u32 flags);
1237

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Linus Torvalds 已提交
1238 1239
/* kmem_cache style wrapper around pci_alloc_consistent() */

1240
#include <linux/pci-dma.h>
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1241 1242 1243 1244 1245 1246 1247
#include <linux/dmapool.h>

#define	pci_pool dma_pool
#define pci_pool_create(name, pdev, size, align, allocation) \
		dma_pool_create(name, &pdev->dev, size, align, allocation)
#define	pci_pool_destroy(pool) dma_pool_destroy(pool)
#define	pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1248 1249
#define	pci_pool_zalloc(pool, flags, handle) \
		dma_pool_zalloc(pool, flags, handle)
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#define	pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)

struct msix_entry {
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Yinghai Lu 已提交
1253
	u32	vector;	/* kernel uses to write allocated vector */
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1254 1255 1256
	u16	entry;	/* driver uses to specify entry, OS writes */
};

1257 1258
#ifdef CONFIG_PCI_MSI
int pci_msi_vec_count(struct pci_dev *dev);
1259 1260
void pci_msi_shutdown(struct pci_dev *dev);
void pci_disable_msi(struct pci_dev *dev);
1261
int pci_msix_vec_count(struct pci_dev *dev);
1262 1263 1264 1265 1266
int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
void pci_msix_shutdown(struct pci_dev *dev);
void pci_disable_msix(struct pci_dev *dev);
void pci_restore_msi_state(struct pci_dev *dev);
int pci_msi_enabled(void);
1267
int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1268 1269 1270 1271 1272 1273 1274
static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
{
	int rc = pci_enable_msi_range(dev, nvec, nvec);
	if (rc < 0)
		return rc;
	return 0;
}
1275 1276
int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
			  int minvec, int maxvec);
1277 1278 1279 1280 1281 1282 1283 1284
static inline int pci_enable_msix_exact(struct pci_dev *dev,
					struct msix_entry *entries, int nvec)
{
	int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
	if (rc < 0)
		return rc;
	return 0;
}
1285
#else
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1286 1287 1288 1289
static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
static inline void pci_msi_shutdown(struct pci_dev *dev) { }
static inline void pci_disable_msi(struct pci_dev *dev) { }
static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1290 1291
static inline int pci_enable_msix(struct pci_dev *dev,
				  struct msix_entry *entries, int nvec)
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1292 1293 1294 1295 1296
{ return -ENOSYS; }
static inline void pci_msix_shutdown(struct pci_dev *dev) { }
static inline void pci_disable_msix(struct pci_dev *dev) { }
static inline void pci_restore_msi_state(struct pci_dev *dev) { }
static inline int pci_msi_enabled(void) { return 0; }
1297 1298
static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
				       int maxvec)
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{ return -ENOSYS; }
1300 1301
static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
{ return -ENOSYS; }
1302 1303
static inline int pci_enable_msix_range(struct pci_dev *dev,
		      struct msix_entry *entries, int minvec, int maxvec)
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{ return -ENOSYS; }
1305 1306 1307
static inline int pci_enable_msix_exact(struct pci_dev *dev,
		      struct msix_entry *entries, int nvec)
{ return -ENOSYS; }
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#endif

1310
#ifdef CONFIG_PCIEPORTBUS
1311 1312
extern bool pcie_ports_disabled;
extern bool pcie_ports_auto;
1313 1314 1315 1316
#else
#define pcie_ports_disabled	true
#define pcie_ports_auto		false
#endif
1317

1318
#ifdef CONFIG_PCIEASPM
1319
bool pcie_aspm_support_enabled(void);
1320 1321
#else
static inline bool pcie_aspm_support_enabled(void) { return false; }
1322 1323
#endif

1324 1325 1326 1327 1328 1329 1330 1331
#ifdef CONFIG_PCIEAER
void pci_no_aer(void);
bool pci_aer_available(void);
#else
static inline void pci_no_aer(void) { }
static inline bool pci_aer_available(void) { return false; }
#endif

1332
#ifdef CONFIG_PCIE_ECRC
1333 1334
void pcie_set_ecrc_checking(struct pci_dev *dev);
void pcie_ecrc_get_policy(char *str);
1335
#else
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Bjorn Helgaas 已提交
1336 1337
static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
static inline void pcie_ecrc_get_policy(char *str) { }
1338 1339
#endif

1340
#define pci_enable_msi(pdev)	pci_enable_msi_exact(pdev, 1)
1341

1342 1343 1344 1345 1346 1347
#ifdef CONFIG_HT_IRQ
/* The functions a driver should call */
int  ht_create_irq(struct pci_dev *dev, int idx);
void ht_destroy_irq(unsigned int irq);
#endif /* CONFIG_HT_IRQ */

1348 1349 1350
#ifdef CONFIG_PCI_ATS
/* Address Translation Service */
void pci_ats_init(struct pci_dev *dev);
1351 1352 1353
int pci_enable_ats(struct pci_dev *dev, int ps);
void pci_disable_ats(struct pci_dev *dev);
int pci_ats_queue_depth(struct pci_dev *dev);
1354
#else
1355 1356 1357 1358
static inline void pci_ats_init(struct pci_dev *d) { }
static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
static inline void pci_disable_ats(struct pci_dev *d) { }
static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1359 1360
#endif

1361 1362 1363
void pci_cfg_access_lock(struct pci_dev *dev);
bool pci_cfg_access_trylock(struct pci_dev *dev);
void pci_cfg_access_unlock(struct pci_dev *dev);
1364

1365 1366
/*
 * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
1367
 * a PCI domain is defined to be a set of PCI buses which share
1368 1369
 * configuration space.
 */
1370 1371
#ifdef CONFIG_PCI_DOMAINS
extern int pci_domains_supported;
1372
int pci_get_new_domain_nr(void);
1373 1374
#else
enum { pci_domains_supported = 0 };
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static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1377
static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1378
#endif /* CONFIG_PCI_DOMAINS */
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1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397
/*
 * Generic implementation for PCI domain support. If your
 * architecture does not need custom management of PCI
 * domains then this implementation will be used
 */
#ifdef CONFIG_PCI_DOMAINS_GENERIC
static inline int pci_domain_nr(struct pci_bus *bus)
{
	return bus->domain_nr;
}
void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent);
#else
static inline void pci_bus_assign_domain_nr(struct pci_bus *bus,
					struct device *parent)
{
}
#endif

1398 1399
/* some architectures require additional setup to direct VGA traffic */
typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1400
		      unsigned int command_bits, u32 flags);
1401
void pci_register_set_vga_state(arch_set_vga_state_t func);
1402

1403
#else /* CONFIG_PCI is not enabled */
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1405 1406 1407 1408 1409
static inline void pci_set_flags(int flags) { }
static inline void pci_add_flags(int flags) { }
static inline void pci_clear_flags(int flags) { }
static inline int pci_has_flag(int flag) { return 0; }

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/*
 *  If the system does not have PCI, clearly these return errors.  Define
 *  these as simple inline functions to avoid hair in drivers.
 */

1415 1416 1417
#define _PCI_NOP(o, s, t) \
	static inline int pci_##o##_config_##s(struct pci_dev *dev, \
						int where, t val) \
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		{ return PCIBIOS_FUNC_NOT_SUPPORTED; }
1419 1420 1421 1422

#define _PCI_NOP_ALL(o, x)	_PCI_NOP(o, byte, u8 x) \
				_PCI_NOP(o, word, u16 x) \
				_PCI_NOP(o, dword, u32 x)
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_PCI_NOP_ALL(read, *)
_PCI_NOP_ALL(write,)

1426
static inline struct pci_dev *pci_get_device(unsigned int vendor,
1427 1428
					     unsigned int device,
					     struct pci_dev *from)
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1429
{ return NULL; }
1430

1431 1432 1433 1434
static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
					     unsigned int device,
					     unsigned int ss_vendor,
					     unsigned int ss_device,
1435
					     struct pci_dev *from)
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1436
{ return NULL; }
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1438 1439
static inline struct pci_dev *pci_get_class(unsigned int class,
					    struct pci_dev *from)
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1440
{ return NULL; }
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1441 1442

#define pci_dev_present(ids)	(0)
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#define no_pci_devices()	(1)
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#define pci_dev_put(dev)	do { } while (0)

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static inline void pci_set_master(struct pci_dev *dev) { }
static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
static inline void pci_disable_device(struct pci_dev *dev) { }
1449
static inline int pci_assign_resource(struct pci_dev *dev, int i)
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{ return -EBUSY; }
1451 1452
static inline int __pci_register_driver(struct pci_driver *drv,
					struct module *owner)
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1453
{ return 0; }
1454
static inline int pci_register_driver(struct pci_driver *drv)
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1455 1456
{ return 0; }
static inline void pci_unregister_driver(struct pci_driver *drv) { }
1457
static inline int pci_find_capability(struct pci_dev *dev, int cap)
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1458
{ return 0; }
1459 1460
static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
					   int cap)
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1461
{ return 0; }
1462
static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
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1463
{ return 0; }
1464

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/* Power management related routines */
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1466 1467
static inline int pci_save_state(struct pci_dev *dev) { return 0; }
static inline void pci_restore_state(struct pci_dev *dev) { }
1468
static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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1469
{ return 0; }
1470
static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
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1471
{ return 0; }
1472 1473
static inline pci_power_t pci_choose_state(struct pci_dev *dev,
					   pm_message_t state)
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{ return PCI_D0; }
1475 1476
static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
				  int enable)
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1477
{ return 0; }
1478

1479
static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
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1480 1481
{ return -EIO; }
static inline void pci_release_regions(struct pci_dev *dev) { }
1482

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static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1484 1485
static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
{ return 0; }
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static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1487

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static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
{ return NULL; }
static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
						unsigned int devfn)
{ return NULL; }
static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
						unsigned int devfn)
{ return NULL; }

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static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1499
static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1500

1501 1502 1503
#define dev_is_pci(d) (false)
#define dev_is_pf(d) (false)
#define dev_num_vf(d) (0)
1504
#endif /* CONFIG_PCI */
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1506 1507 1508
/* Include architecture-dependent settings and functions */

#include <asm/pci.h>
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1510 1511 1512 1513
#ifndef pci_root_bus_fwnode
#define pci_root_bus_fwnode(bus)	NULL
#endif

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/* these helpers provide future and backwards compatibility
 * for accessing popular PCI BAR info */
1516 1517 1518
#define pci_resource_start(dev, bar)	((dev)->resource[(bar)].start)
#define pci_resource_end(dev, bar)	((dev)->resource[(bar)].end)
#define pci_resource_flags(dev, bar)	((dev)->resource[(bar)].flags)
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#define pci_resource_len(dev,bar) \
1520 1521 1522 1523 1524 1525
	((pci_resource_start((dev), (bar)) == 0 &&	\
	  pci_resource_end((dev), (bar)) ==		\
	  pci_resource_start((dev), (bar))) ? 0 :	\
							\
	 (pci_resource_end((dev), (bar)) -		\
	  pci_resource_start((dev), (bar)) + 1))
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/* Similar to the helpers above, these manipulate per-pci_dev
 * driver-specific data.  They are really just a wrapper around
 * the generic device structure functions of these calls.
 */
1531
static inline void *pci_get_drvdata(struct pci_dev *pdev)
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{
	return dev_get_drvdata(&pdev->dev);
}

1536
static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
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{
	dev_set_drvdata(&pdev->dev, data);
}

/* If you want to know what to call your pci_dev, ask this function.
 * Again, it's a wrapper around the generic device.
 */
1544
static inline const char *pci_name(const struct pci_dev *pdev)
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{
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	return dev_name(&pdev->dev);
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1547 1548
}

1549 1550 1551 1552 1553 1554

/* Some archs don't want to expose struct resource to userland as-is
 * in sysfs and /proc
 */
#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1555
		const struct resource *rsrc, resource_size_t *start,
1556
		resource_size_t *end)
1557 1558 1559 1560 1561 1562 1563
{
	*start = rsrc->start;
	*end = rsrc->end;
}
#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */


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/*
 *  The world is not perfect and supplies us with broken PCI devices.
 *  For at least a part of these bugs we need a work-around, so both
 *  generic (drivers/pci/quirks.c) and per-architecture code can define
 *  fixup hooks to be called for particular buggy devices.
 */

struct pci_fixup {
1572 1573 1574 1575
	u16 vendor;		/* You can use PCI_ANY_ID here of course */
	u16 device;		/* You can use PCI_ANY_ID here of course */
	u32 class;		/* You can use PCI_ANY_ID here too */
	unsigned int class_shift;	/* should be 0, 8, 16 */
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	void (*hook)(struct pci_dev *dev);
};

enum pci_fixup_pass {
	pci_fixup_early,	/* Before probing BARs */
	pci_fixup_header,	/* After reading configuration header */
	pci_fixup_final,	/* Final phase of device fixups */
	pci_fixup_enable,	/* pci_enable_device() time */
1584
	pci_fixup_resume,	/* pci_device_resume() */
1585
	pci_fixup_suspend,	/* pci_device_suspend() */
1586
	pci_fixup_resume_early, /* pci_device_resume_early() */
1587
	pci_fixup_suspend_late,	/* pci_device_suspend_late() */
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};

/* Anonymous variables would be nice... */
1591 1592
#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class,	\
				  class_shift, hook)			\
1593
	static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used	\
1594 1595 1596 1597 1598 1599
	__attribute__((__section__(#section), aligned((sizeof(void *)))))    \
		= { vendor, device, class, class_shift, hook };

#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,		\
					 class_shift, hook)		\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,			\
1600
		hook, vendor, device, class, class_shift, hook)
1601 1602 1603
#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,		\
					 class_shift, hook)		\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,			\
1604
		hook, vendor, device, class, class_shift, hook)
1605 1606 1607
#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,		\
					 class_shift, hook)		\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,			\
1608
		hook, vendor, device, class, class_shift, hook)
1609 1610 1611
#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,		\
					 class_shift, hook)		\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,			\
1612
		hook, vendor, device, class, class_shift, hook)
1613 1614 1615
#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,		\
					 class_shift, hook)		\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,			\
1616
		resume##hook, vendor, device, class,	\
1617 1618 1619 1620
		class_shift, hook)
#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,	\
					 class_shift, hook)		\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,		\
1621
		resume_early##hook, vendor, device,	\
1622 1623 1624 1625
		class, class_shift, hook)
#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,		\
					 class_shift, hook)		\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,			\
1626
		suspend##hook, vendor, device, class,	\
1627
		class_shift, hook)
1628 1629 1630 1631 1632
#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class,	\
					 class_shift, hook)		\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,		\
		suspend_late##hook, vendor, device,	\
		class, class_shift, hook)
1633

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#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)			\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,			\
1636
		hook, vendor, device, PCI_ANY_ID, 0, hook)
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#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)			\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,			\
1639
		hook, vendor, device, PCI_ANY_ID, 0, hook)
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#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)			\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,			\
1642
		hook, vendor, device, PCI_ANY_ID, 0, hook)
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1643 1644
#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)			\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,			\
1645
		hook, vendor, device, PCI_ANY_ID, 0, hook)
1646 1647
#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)			\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,			\
1648
		resume##hook, vendor, device,		\
1649
		PCI_ANY_ID, 0, hook)
1650 1651
#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)		\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,		\
1652
		resume_early##hook, vendor, device,	\
1653
		PCI_ANY_ID, 0, hook)
1654 1655
#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)			\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,			\
1656
		suspend##hook, vendor, device,		\
1657
		PCI_ANY_ID, 0, hook)
1658 1659 1660 1661
#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook)		\
	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,		\
		suspend_late##hook, vendor, device,	\
		PCI_ANY_ID, 0, hook)
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1663
#ifdef CONFIG_PCI_QUIRKS
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void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1665
int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1666
void pci_dev_specific_enable_acs(struct pci_dev *dev);
1667 1668
#else
static inline void pci_fixup_device(enum pci_fixup_pass pass,
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				    struct pci_dev *dev) { }
1670 1671 1672 1673 1674
static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
					       u16 acs_flags)
{
	return -ENOTTY;
}
1675
static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { }
1676
#endif
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1678
void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
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1679
void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1680
void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1681 1682
int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1683
				   const char *name);
1684
void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
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extern int pci_pci_problems;
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1687
#define PCIPCI_FAIL		1	/* No PCI PCI DMA */
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#define PCIPCI_TRITON		2
#define PCIPCI_NATOMA		4
#define PCIPCI_VIAETBF		8
#define PCIPCI_VSFX		16
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#define PCIPCI_ALIMAGIK		32	/* Need low latency setting */
#define PCIAGP_FAIL		64	/* No PCI to AGP DMA */
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1695 1696
extern unsigned long pci_cardbus_io_size;
extern unsigned long pci_cardbus_mem_size;
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extern u8 pci_dfl_cache_line_size;
1698
extern u8 pci_cache_line_size;
1699

1700 1701 1702
extern unsigned long pci_hotplug_io_size;
extern unsigned long pci_hotplug_mem_size;

1703
/* Architecture-specific versions may override these (weak) */
1704
void pcibios_disable_device(struct pci_dev *dev);
1705
void pcibios_set_master(struct pci_dev *dev);
1706 1707
int pcibios_set_pcie_reset_state(struct pci_dev *dev,
				 enum pcie_reset_state state);
M
Matthew Garrett 已提交
1708
int pcibios_add_device(struct pci_dev *dev);
1709
void pcibios_release_device(struct pci_dev *dev);
1710
void pcibios_penalize_isa_irq(int irq, int active);
1711 1712
int pcibios_alloc_irq(struct pci_dev *dev);
void pcibios_free_irq(struct pci_dev *dev);
1713

1714 1715 1716 1717
#ifdef CONFIG_HIBERNATE_CALLBACKS
extern struct dev_pm_ops pcibios_pm_ops;
#endif

1718
#ifdef CONFIG_PCI_MMCONFIG
1719 1720
void __init pci_mmcfg_early_init(void);
void __init pci_mmcfg_late_init(void);
1721
#else
1722
static inline void pci_mmcfg_early_init(void) { }
1723 1724 1725
static inline void pci_mmcfg_late_init(void) { }
#endif

1726
int pci_ext_cfg_avail(void);
1727

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1728
void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1729
void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1730

1731
#ifdef CONFIG_PCI_IOV
1732 1733 1734
int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);

1735 1736
int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
void pci_disable_sriov(struct pci_dev *dev);
1737 1738
int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1739
int pci_num_vf(struct pci_dev *dev);
1740
int pci_vfs_assigned(struct pci_dev *dev);
1741 1742
int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
int pci_sriov_get_totalvfs(struct pci_dev *dev);
1743
resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1744
#else
1745 1746 1747 1748 1749 1750 1751 1752
static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
{
	return -ENOSYS;
}
static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
{
	return -ENOSYS;
}
1753
static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
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1754
{ return -ENODEV; }
1755 1756 1757 1758 1759 1760
static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
{
	return -ENOSYS;
}
static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
					 int id, int reset) { }
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1761 1762
static inline void pci_disable_sriov(struct pci_dev *dev) { }
static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1763
static inline int pci_vfs_assigned(struct pci_dev *dev)
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1764
{ return 0; }
1765
static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
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Bjorn Helgaas 已提交
1766
{ return 0; }
1767
static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
B
Bjorn Helgaas 已提交
1768
{ return 0; }
1769 1770
static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
{ return 0; }
1771 1772
#endif

1773
#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1774 1775
void pci_hp_create_module_link(struct pci_slot *pci_slot);
void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1776 1777
#endif

K
Kenji Kaneshige 已提交
1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793
/**
 * pci_pcie_cap - get the saved PCIe capability offset
 * @dev: PCI device
 *
 * PCIe capability offset is calculated at PCI device initialization
 * time and saved in the data structure. This function returns saved
 * PCIe capability offset. Using this instead of pci_find_capability()
 * reduces unnecessary search in the PCI configuration space. If you
 * need to calculate PCIe capability offset from raw device for some
 * reasons, please use pci_find_capability() instead.
 */
static inline int pci_pcie_cap(struct pci_dev *dev)
{
	return dev->pcie_cap;
}

K
Kenji Kaneshige 已提交
1794 1795 1796 1797
/**
 * pci_is_pcie - check if the PCI device is PCI Express capable
 * @dev: PCI device
 *
1798
 * Returns: true if the PCI device is PCI Express capable, false otherwise.
K
Kenji Kaneshige 已提交
1799 1800 1801
 */
static inline bool pci_is_pcie(struct pci_dev *dev)
{
1802
	return pci_pcie_cap(dev);
K
Kenji Kaneshige 已提交
1803 1804
}

1805 1806 1807 1808 1809 1810 1811 1812 1813
/**
 * pcie_caps_reg - get the PCIe Capabilities Register
 * @dev: PCI device
 */
static inline u16 pcie_caps_reg(const struct pci_dev *dev)
{
	return dev->pcie_flags_reg;
}

1814 1815 1816 1817 1818 1819
/**
 * pci_pcie_type - get the PCIe device/port type
 * @dev: PCI device
 */
static inline int pci_pcie_type(const struct pci_dev *dev)
{
1820
	return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1821 1822
}

C
Chris Wright 已提交
1823
void pci_request_acs(void);
1824 1825 1826
bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
bool pci_acs_path_enabled(struct pci_dev *start,
			  struct pci_dev *end, u16 acs_flags);
1827

1828
#define PCI_VPD_LRDT			0x80	/* Large Resource Data Type */
1829
#define PCI_VPD_LRDT_ID(x)		((x) | PCI_VPD_LRDT)
1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840

/* Large Resource Data Type Tag Item Names */
#define PCI_VPD_LTIN_ID_STRING		0x02	/* Identifier String */
#define PCI_VPD_LTIN_RO_DATA		0x10	/* Read-Only Data */
#define PCI_VPD_LTIN_RW_DATA		0x11	/* Read-Write Data */

#define PCI_VPD_LRDT_ID_STRING		PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
#define PCI_VPD_LRDT_RO_DATA		PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
#define PCI_VPD_LRDT_RW_DATA		PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)

/* Small Resource Data Type Tag Item Names */
H
Hannes Reinecke 已提交
1841
#define PCI_VPD_STIN_END		0x0f	/* End */
1842

H
Hannes Reinecke 已提交
1843
#define PCI_VPD_SRDT_END		(PCI_VPD_STIN_END << 3)
1844 1845 1846

#define PCI_VPD_SRDT_TIN_MASK		0x78
#define PCI_VPD_SRDT_LEN_MASK		0x07
H
Hannes Reinecke 已提交
1847
#define PCI_VPD_LRDT_TIN_MASK		0x7f
1848 1849 1850

#define PCI_VPD_LRDT_TAG_SIZE		3
#define PCI_VPD_SRDT_TAG_SIZE		1
1851

1852 1853
#define PCI_VPD_INFO_FLD_HDR_SIZE	3

1854 1855 1856
#define PCI_VPD_RO_KEYWORD_PARTNO	"PN"
#define PCI_VPD_RO_KEYWORD_MFR_ID	"MN"
#define PCI_VPD_RO_KEYWORD_VENDOR0	"V0"
1857
#define PCI_VPD_RO_KEYWORD_CHKSUM	"RV"
1858

1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869
/**
 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
 *
 * Returns the extracted Large Resource Data Type length.
 */
static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
{
	return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
}

H
Hannes Reinecke 已提交
1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880
/**
 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
 *
 * Returns the extracted Large Resource Data Type Tag item.
 */
static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
{
    return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
}

1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891
/**
 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
 *
 * Returns the extracted Small Resource Data Type length.
 */
static inline u8 pci_vpd_srdt_size(const u8 *srdt)
{
	return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
}

H
Hannes Reinecke 已提交
1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902
/**
 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
 *
 * Returns the extracted Small Resource Data Type Tag Item.
 */
static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
{
	return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
}

1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913
/**
 * pci_vpd_info_field_size - Extracts the information field length
 * @lrdt: Pointer to the beginning of an information field header
 *
 * Returns the extracted information field length.
 */
static inline u8 pci_vpd_info_field_size(const u8 *info_field)
{
	return info_field[2];
}

1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925
/**
 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
 * @buf: Pointer to buffered vpd data
 * @off: The offset into the buffer at which to begin the search
 * @len: The length of the vpd buffer
 * @rdt: The Resource Data Type to search for
 *
 * Returns the index where the Resource Data Type was found or
 * -ENOENT otherwise.
 */
int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);

1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938
/**
 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
 * @buf: Pointer to buffered vpd data
 * @off: The offset into the buffer at which to begin the search
 * @len: The length of the buffer area, relative to off, in which to search
 * @kw: The keyword to search for
 *
 * Returns the index where the information field keyword was found or
 * -ENOENT otherwise.
 */
int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
			      unsigned int len, const char *kw);

1939 1940 1941
/* PCI <-> OF binding helpers */
#ifdef CONFIG_OF
struct device_node;
1942
struct irq_domain;
1943 1944 1945 1946
void pci_set_of_node(struct pci_dev *dev);
void pci_release_of_node(struct pci_dev *dev);
void pci_set_bus_of_node(struct pci_bus *bus);
void pci_release_bus_of_node(struct pci_bus *bus);
1947
struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
1948 1949

/* Arch may override this (weak) */
1950
struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1951

1952 1953
static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev *pdev)
1954 1955 1956 1957
{
	return pdev ? pdev->dev.of_node : NULL;
}

1958 1959 1960 1961 1962
static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
{
	return bus ? bus->dev.of_node : NULL;
}

1963 1964 1965 1966 1967
#else /* CONFIG_OF */
static inline void pci_set_of_node(struct pci_dev *dev) { }
static inline void pci_release_of_node(struct pci_dev *dev) { }
static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1968 1969
static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
1970 1971
static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
1972 1973
#endif  /* CONFIG_OF */

1974 1975 1976 1977 1978 1979 1980 1981 1982 1983
#ifdef CONFIG_ACPI
struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);

void
pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
#else
static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
#endif

G
Gavin Shan 已提交
1984 1985 1986 1987 1988 1989 1990
#ifdef CONFIG_EEH
static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
{
	return pdev->dev.archdata.edev;
}
#endif

A
Alex Williamson 已提交
1991 1992 1993 1994
int pci_for_each_dma_alias(struct pci_dev *pdev,
			   int (*fn)(struct pci_dev *pdev,
				     u16 alias, void *data), void *data);

1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007
/* helper functions for operation of device flag */
static inline void pci_set_dev_assigned(struct pci_dev *pdev)
{
	pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
}
static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
{
	pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
}
static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
{
	return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
}
2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018

/**
 * pci_ari_enabled - query ARI forwarding status
 * @bus: the PCI bus
 *
 * Returns true if ARI forwarding is enabled.
 */
static inline bool pci_ari_enabled(struct pci_bus *bus)
{
	return bus->self && bus->self->ari_enabled;
}
2019 2020 2021 2022

/* provide the legacy pci_dma_* API */
#include <linux/pci-dma-compat.h>

L
Linus Torvalds 已提交
2023
#endif /* LINUX_PCI_H */