Kconfig

#
#	EDAC Kconfig
#	Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
#	Licensed and distributed under the GPL

config EDAC_ATOMIC_SCRUB
	bool

config EDAC_SUPPORT
	bool

menuconfig EDAC
	bool "EDAC (Error Detection And Correction) reporting"
	depends on HAS_IOMEM && EDAC_SUPPORT
	help
	  EDAC is designed to report errors in the core system.
	  These are low-level errors that are reported in the CPU or
	  supporting chipset or other subsystems:
	  memory errors, cache errors, PCI errors, thermal throttling, etc..
	  If unsure, select 'Y'.

	  If this code is reporting problems on your system, please
	  see the EDAC project web pages for more information at:

	  <http://bluesmoke.sourceforge.net/>

	  and:

	  <http://buttersideup.com/edacwiki>

	  There is also a mailing list for the EDAC project, which can
	  be found via the sourceforge page.

if EDAC

config EDAC_LEGACY_SYSFS
	bool "EDAC legacy sysfs"
	default y
	help
	  Enable the compatibility sysfs nodes.
	  Use 'Y' if your edac utilities aren't ported to work with the newer
	  structures.

config EDAC_DEBUG
	bool "Debugging"
	help
	  This turns on debugging information for the entire EDAC subsystem.
	  You do so by inserting edac_module with "edac_debug_level=x." Valid
	  levels are 0-4 (from low to high) and by default it is set to 2.
	  Usually you should select 'N' here.

config EDAC_DECODE_MCE
	tristate "Decode MCEs in human-readable form (only on AMD for now)"
	depends on CPU_SUP_AMD && X86_MCE_AMD
	default y
	---help---
	  Enable this option if you want to decode Machine Check Exceptions
	  occurring on your machine in human-readable form.

	  You should definitely say Y here in case you want to decode MCEs
	  which occur really early upon boot, before the module infrastructure
	  has been initialized.

config EDAC_MCE_INJ
	tristate "Simple MCE injection interface"
	depends on EDAC_DECODE_MCE && DEBUG_FS
	default n
	help
	  This is a simple debugfs interface to inject MCEs and test different
	  aspects of the MCE handling code.

	  WARNING: Do not even assume this interface is staying stable!

config EDAC_MM_EDAC
	tristate "Main Memory EDAC (Error Detection And Correction) reporting"
	select RAS
	help
	  Some systems are able to detect and correct errors in main
	  memory.  EDAC can report statistics on memory error
	  detection and correction (EDAC - or commonly referred to ECC
	  errors).  EDAC will also try to decode where these errors
	  occurred so that a particular failing memory module can be
	  replaced.  If unsure, select 'Y'.

config EDAC_GHES
	bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
	depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
	default y
	help
	  Not all machines support hardware-driven error report. Some of those
	  provide a BIOS-driven error report mechanism via ACPI, using the
	  APEI/GHES driver. By enabling this option, the error reports provided
	  by GHES are sent to userspace via the EDAC API.

	  When this option is enabled, it will disable the hardware-driven
	  mechanisms, if a GHES BIOS is detected, entering into the
	  "Firmware First" mode.

	  It should be noticed that keeping both GHES and a hardware-driven
	  error mechanism won't work well, as BIOS will race with OS, while
	  reading the error registers. So, if you want to not use "Firmware
	  first" GHES error mechanism, you should disable GHES either at
	  compilation time or by passing "ghes.disable=1" Kernel parameter
	  at boot time.

	  In doubt, say 'Y'.

config EDAC_AMD64
	tristate "AMD64 (Opteron, Athlon64)"
	depends on EDAC_MM_EDAC && AMD_NB && EDAC_DECODE_MCE
	help
	  Support for error detection and correction of DRAM ECC errors on
	  the AMD64 families (>= K8) of memory controllers.

config EDAC_AMD64_ERROR_INJECTION
	bool "Sysfs HW Error injection facilities"
	depends on EDAC_AMD64
	help
	  Recent Opterons (Family 10h and later) provide for Memory Error
	  Injection into the ECC detection circuits. The amd64_edac module
	  allows the operator/user to inject Uncorrectable and Correctable
	  errors into DRAM.

	  When enabled, in each of the respective memory controller directories
	  (/sys/devices/system/edac/mc/mcX), there are 3 input files:

	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
	  - inject_word (0..8, 16-bit word of 16-byte section),
	  - inject_ecc_vector (hex ecc vector: select bits of inject word)

	  In addition, there are two control files, inject_read and inject_write,
	  which trigger the DRAM ECC Read and Write respectively.

config EDAC_AMD76X
	tristate "AMD 76x (760, 762, 768)"
	depends on EDAC_MM_EDAC && PCI && X86_32
	help
	  Support for error detection and correction on the AMD 76x
	  series of chipsets used with the Athlon processor.

config EDAC_E7XXX
	tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
	depends on EDAC_MM_EDAC && PCI && X86_32
	help
	  Support for error detection and correction on the Intel
	  E7205, E7500, E7501 and E7505 server chipsets.

config EDAC_E752X
	tristate "Intel e752x (e7520, e7525, e7320) and 3100"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  E7520, E7525, E7320 server chipsets.

config EDAC_I82443BXGX
	tristate "Intel 82443BX/GX (440BX/GX)"
	depends on EDAC_MM_EDAC && PCI && X86_32
	depends on BROKEN
	help
	  Support for error detection and correction on the Intel
	  82443BX/GX memory controllers (440BX/GX chipsets).

config EDAC_I82875P
	tristate "Intel 82875p (D82875P, E7210)"
	depends on EDAC_MM_EDAC && PCI && X86_32
	help
	  Support for error detection and correction on the Intel
	  DP82785P and E7210 server chipsets.

config EDAC_I82975X
	tristate "Intel 82975x (D82975x)"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  DP82975x server chipsets.

config EDAC_I3000
	tristate "Intel 3000/3010"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  3000 and 3010 server chipsets.

config EDAC_I3200
	tristate "Intel 3200"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  3200 and 3210 server chipsets.

config EDAC_IE31200
	tristate "Intel e312xx"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  E3-1200 based DRAM controllers.

config EDAC_X38
	tristate "Intel X38"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  X38 server chipsets.

config EDAC_I5400
	tristate "Intel 5400 (Seaburg) chipsets"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction the Intel
	  i5400 MCH chipset (Seaburg).

config EDAC_I7CORE
	tristate "Intel i7 Core (Nehalem) processors"
	depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
	help
	  Support for error detection and correction the Intel
	  i7 Core (Nehalem) Integrated Memory Controller that exists on
	  newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
	  and Xeon 55xx processors.

config EDAC_I82860
	tristate "Intel 82860"
	depends on EDAC_MM_EDAC && PCI && X86_32
	help
	  Support for error detection and correction on the Intel
	  82860 chipset.

config EDAC_R82600
	tristate "Radisys 82600 embedded chipset"
	depends on EDAC_MM_EDAC && PCI && X86_32
	help
	  Support for error detection and correction on the Radisys
	  82600 embedded chipset.

config EDAC_I5000
	tristate "Intel Greencreek/Blackford chipset"
	depends on EDAC_MM_EDAC && X86 && PCI
	help
	  Support for error detection and correction the Intel
	  Greekcreek/Blackford chipsets.

config EDAC_I5100
	tristate "Intel San Clemente MCH"
	depends on EDAC_MM_EDAC && X86 && PCI
	help
	  Support for error detection and correction the Intel
	  San Clemente MCH.

config EDAC_I7300
	tristate "Intel Clarksboro MCH"
	depends on EDAC_MM_EDAC && X86 && PCI
	help
	  Support for error detection and correction the Intel
	  Clarksboro MCH (Intel 7300 chipset).

config EDAC_SBRIDGE
	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
	depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
	depends on PCI_MMCONFIG
	help
	  Support for error detection and correction the Intel
	  Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.

config EDAC_MPC85XX
	tristate "Freescale MPC83xx / MPC85xx"
	depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
	help
	  Support for error detection and correction on the Freescale
	  MPC8349, MPC8560, MPC8540, MPC8548

config EDAC_MV64X60
	tristate "Marvell MV64x60"
	depends on EDAC_MM_EDAC && MV64X60
	help
	  Support for error detection and correction on the Marvell
	  MV64360 and MV64460 chipsets.

config EDAC_PASEMI
	tristate "PA Semi PWRficient"
	depends on EDAC_MM_EDAC && PCI
	depends on PPC_PASEMI
	help
	  Support for error detection and correction on PA Semi
	  PWRficient.

config EDAC_CELL
	tristate "Cell Broadband Engine memory controller"
	depends on EDAC_MM_EDAC && PPC_CELL_COMMON
	help
	  Support for error detection and correction on the
	  Cell Broadband Engine internal memory controller
	  on platform without a hypervisor

config EDAC_PPC4XX
	tristate "PPC4xx IBM DDR2 Memory Controller"
	depends on EDAC_MM_EDAC && 4xx
	help
	  This enables support for EDAC on the ECC memory used
	  with the IBM DDR2 memory controller found in various
	  PowerPC 4xx embedded processors such as the 405EX[r],
	  440SP, 440SPe, 460EX, 460GT and 460SX.

config EDAC_AMD8131
	tristate "AMD8131 HyperTransport PCI-X Tunnel"
	depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
	help
	  Support for error detection and correction on the
	  AMD8131 HyperTransport PCI-X Tunnel chip.
	  Note, add more Kconfig dependency if it's adopted
	  on some machine other than Maple.

config EDAC_AMD8111
	tristate "AMD8111 HyperTransport I/O Hub"
	depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
	help
	  Support for error detection and correction on the
	  AMD8111 HyperTransport I/O Hub chip.
	  Note, add more Kconfig dependency if it's adopted
	  on some machine other than Maple.

config EDAC_CPC925
	tristate "IBM CPC925 Memory Controller (PPC970FX)"
	depends on EDAC_MM_EDAC && PPC64
	help
	  Support for error detection and correction on the
	  IBM CPC925 Bridge and Memory Controller, which is
	  a companion chip to the PowerPC 970 family of
	  processors.

config EDAC_TILE
	tristate "Tilera Memory Controller"
	depends on EDAC_MM_EDAC && TILE
	default y
	help
	  Support for error detection and correction on the
	  Tilera memory controller.

config EDAC_HIGHBANK_MC
	tristate "Highbank Memory Controller"
	depends on EDAC_MM_EDAC && ARCH_HIGHBANK
	help
	  Support for error detection and correction on the
	  Calxeda Highbank memory controller.

config EDAC_HIGHBANK_L2
	tristate "Highbank L2 Cache"
	depends on EDAC_MM_EDAC && ARCH_HIGHBANK
	help
	  Support for error detection and correction on the
	  Calxeda Highbank memory controller.

config EDAC_OCTEON_PC
	tristate "Cavium Octeon Primary Caches"
	depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
	help
	  Support for error detection and correction on the primary caches of
	  the cnMIPS cores of Cavium Octeon family SOCs.

config EDAC_OCTEON_L2C
	tristate "Cavium Octeon Secondary Caches (L2C)"
	depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
	help
	  Support for error detection and correction on the
	  Cavium Octeon family of SOCs.

config EDAC_OCTEON_LMC
	tristate "Cavium Octeon DRAM Memory Controller (LMC)"
	depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
	help
	  Support for error detection and correction on the
	  Cavium Octeon family of SOCs.

config EDAC_OCTEON_PCI
	tristate "Cavium Octeon PCI Controller"
	depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
	help
	  Support for error detection and correction on the
	  Cavium Octeon family of SOCs.

config EDAC_ALTERA_MC
	bool "Altera SDRAM Memory Controller EDAC"
	depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
	help
	  Support for error detection and correction on the
	  Altera SDRAM memory controller. Note that the
	  preloader must initialize the SDRAM before loading
	  the kernel.

config EDAC_SYNOPSYS
	tristate "Synopsys DDR Memory Controller"
	depends on EDAC_MM_EDAC && ARCH_ZYNQ
	help
	  Support for error detection and correction on the Synopsys DDR
	  memory controller.

endif # EDAC