Kconfig 11.4 KB
Newer Older
A
Alan Cox 已提交
1 2
#
#	EDAC Kconfig
3
#	Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
A
Alan Cox 已提交
4 5 6
#	Licensed and distributed under the GPL
#

B
Borislav Petkov 已提交
7 8 9
config EDAC_SUPPORT
	bool

10
menuconfig EDAC
11
	bool "EDAC (Error Detection And Correction) reporting"
12
	depends on HAS_IOMEM
R
Ralf Baechle 已提交
13
	depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
A
Alan Cox 已提交
14 15 16
	help
	  EDAC is designed to report errors in the core system.
	  These are low-level errors that are reported in the CPU or
17 18 19
	  supporting chipset or other subsystems:
	  memory errors, cache errors, PCI errors, thermal throttling, etc..
	  If unsure, select 'Y'.
A
Alan Cox 已提交
20

T
Tim Small 已提交
21 22 23 24 25 26 27 28 29 30 31 32
	  If this code is reporting problems on your system, please
	  see the EDAC project web pages for more information at:

	  <http://bluesmoke.sourceforge.net/>

	  and:

	  <http://buttersideup.com/edacwiki>

	  There is also a mailing list for the EDAC project, which can
	  be found via the sourceforge page.

33
if EDAC
A
Alan Cox 已提交
34

35 36 37 38 39 40 41 42
config EDAC_LEGACY_SYSFS
	bool "EDAC legacy sysfs"
	default y
	help
	  Enable the compatibility sysfs nodes.
	  Use 'Y' if your edac utilities aren't ported to work with the newer
	  structures.

A
Alan Cox 已提交
43 44 45
config EDAC_DEBUG
	bool "Debugging"
	help
46 47 48 49
	  This turns on debugging information for the entire EDAC subsystem.
	  You do so by inserting edac_module with "edac_debug_level=x." Valid
	  levels are 0-4 (from low to high) and by default it is set to 2.
	  Usually you should select 'N' here.
A
Alan Cox 已提交
50

B
Borislav Petkov 已提交
51
config EDAC_DECODE_MCE
52
	tristate "Decode MCEs in human-readable form (only on AMD for now)"
53
	depends on CPU_SUP_AMD && X86_MCE_AMD
54 55 56
	default y
	---help---
	  Enable this option if you want to decode Machine Check Exceptions
L
Lucas De Marchi 已提交
57
	  occurring on your machine in human-readable form.
58 59 60 61 62

	  You should definitely say Y here in case you want to decode MCEs
	  which occur really early upon boot, before the module infrastructure
	  has been initialized.

B
Borislav Petkov 已提交
63 64 65 66 67 68 69 70 71 72
config EDAC_MCE_INJ
	tristate "Simple MCE injection interface over /sysfs"
	depends on EDAC_DECODE_MCE
	default n
	help
	  This is a simple interface to inject MCEs over /sysfs and test
	  the MCE decoding code in EDAC.

	  This is currently AMD-only.

A
Alan Cox 已提交
73 74 75 76 77 78 79 80 81 82
config EDAC_MM_EDAC
	tristate "Main Memory EDAC (Error Detection And Correction) reporting"
	help
	  Some systems are able to detect and correct errors in main
	  memory.  EDAC can report statistics on memory error
	  detection and correction (EDAC - or commonly referred to ECC
	  errors).  EDAC will also try to decode where these errors
	  occurred so that a particular failing memory module can be
	  replaced.  If unsure, select 'Y'.

83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
config EDAC_GHES
	bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
	depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
	default y
	help
	  Not all machines support hardware-driven error report. Some of those
	  provide a BIOS-driven error report mechanism via ACPI, using the
	  APEI/GHES driver. By enabling this option, the error reports provided
	  by GHES are sent to userspace via the EDAC API.

	  When this option is enabled, it will disable the hardware-driven
	  mechanisms, if a GHES BIOS is detected, entering into the
	  "Firmware First" mode.

	  It should be noticed that keeping both GHES and a hardware-driven
	  error mechanism won't work well, as BIOS will race with OS, while
	  reading the error registers. So, if you want to not use "Firmware
	  first" GHES error mechanism, you should disable GHES either at
	  compilation time or by passing "ghes.disable=1" Kernel parameter
	  at boot time.

	  In doubt, say 'Y'.

106
config EDAC_AMD64
107 108
	tristate "AMD64 (Opteron, Athlon64) K8, F10h"
	depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
109
	help
110 111
	  Support for error detection and correction of DRAM ECC errors on
	  the AMD64 families of memory controllers (K8 and F10h)
112 113

config EDAC_AMD64_ERROR_INJECTION
B
Borislav Petkov 已提交
114
	bool "Sysfs HW Error injection facilities"
115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130
	depends on EDAC_AMD64
	help
	  Recent Opterons (Family 10h and later) provide for Memory Error
	  Injection into the ECC detection circuits. The amd64_edac module
	  allows the operator/user to inject Uncorrectable and Correctable
	  errors into DRAM.

	  When enabled, in each of the respective memory controller directories
	  (/sys/devices/system/edac/mc/mcX), there are 3 input files:

	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
	  - inject_word (0..8, 16-bit word of 16-byte section),
	  - inject_ecc_vector (hex ecc vector: select bits of inject word)

	  In addition, there are two control files, inject_read and inject_write,
	  which trigger the DRAM ECC Read and Write respectively.
A
Alan Cox 已提交
131 132 133

config EDAC_AMD76X
	tristate "AMD 76x (760, 762, 768)"
D
Dave Jones 已提交
134
	depends on EDAC_MM_EDAC && PCI && X86_32
A
Alan Cox 已提交
135 136 137 138 139 140
	help
	  Support for error detection and correction on the AMD 76x
	  series of chipsets used with the Athlon processor.

config EDAC_E7XXX
	tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
141
	depends on EDAC_MM_EDAC && PCI && X86_32
A
Alan Cox 已提交
142 143 144 145 146
	help
	  Support for error detection and correction on the Intel
	  E7205, E7500, E7501 and E7505 server chipsets.

config EDAC_E752X
147
	tristate "Intel e752x (e7520, e7525, e7320) and 3100"
148
	depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
A
Alan Cox 已提交
149 150 151 152
	help
	  Support for error detection and correction on the Intel
	  E7520, E7525, E7320 server chipsets.

153 154 155
config EDAC_I82443BXGX
	tristate "Intel 82443BX/GX (440BX/GX)"
	depends on EDAC_MM_EDAC && PCI && X86_32
156
	depends on BROKEN
157 158 159 160
	help
	  Support for error detection and correction on the Intel
	  82443BX/GX memory controllers (440BX/GX chipsets).

A
Alan Cox 已提交
161 162
config EDAC_I82875P
	tristate "Intel 82875p (D82875P, E7210)"
163
	depends on EDAC_MM_EDAC && PCI && X86_32
A
Alan Cox 已提交
164 165 166 167
	help
	  Support for error detection and correction on the Intel
	  DP82785P and E7210 server chipsets.

168 169 170 171 172 173 174
config EDAC_I82975X
	tristate "Intel 82975x (D82975x)"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  DP82975x server chipsets.

175 176
config EDAC_I3000
	tristate "Intel 3000/3010"
177
	depends on EDAC_MM_EDAC && PCI && X86
178 179 180 181
	help
	  Support for error detection and correction on the Intel
	  3000 and 3010 server chipsets.

182 183
config EDAC_I3200
	tristate "Intel 3200"
184
	depends on EDAC_MM_EDAC && PCI && X86
185 186 187 188
	help
	  Support for error detection and correction on the Intel
	  3200 and 3210 server chipsets.

H
Hitoshi Mitake 已提交
189 190 191 192 193 194 195
config EDAC_X38
	tristate "Intel X38"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  X38 server chipsets.

196 197 198 199 200 201 202
config EDAC_I5400
	tristate "Intel 5400 (Seaburg) chipsets"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction the Intel
	  i5400 MCH chipset (Seaburg).

203 204
config EDAC_I7CORE
	tristate "Intel i7 Core (Nehalem) processors"
205
	depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
206 207
	help
	  Support for error detection and correction the Intel
208 209 210
	  i7 Core (Nehalem) Integrated Memory Controller that exists on
	  newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
	  and Xeon 55xx processors.
211

A
Alan Cox 已提交
212 213
config EDAC_I82860
	tristate "Intel 82860"
214
	depends on EDAC_MM_EDAC && PCI && X86_32
A
Alan Cox 已提交
215 216 217 218 219 220
	help
	  Support for error detection and correction on the Intel
	  82860 chipset.

config EDAC_R82600
	tristate "Radisys 82600 embedded chipset"
221
	depends on EDAC_MM_EDAC && PCI && X86_32
A
Alan Cox 已提交
222 223 224 225
	help
	  Support for error detection and correction on the Radisys
	  82600 embedded chipset.

226 227 228 229 230 231 232
config EDAC_I5000
	tristate "Intel Greencreek/Blackford chipset"
	depends on EDAC_MM_EDAC && X86 && PCI
	help
	  Support for error detection and correction the Intel
	  Greekcreek/Blackford chipsets.

233 234 235 236 237 238 239
config EDAC_I5100
	tristate "Intel San Clemente MCH"
	depends on EDAC_MM_EDAC && X86 && PCI
	help
	  Support for error detection and correction the Intel
	  San Clemente MCH.

240 241 242 243 244 245 246
config EDAC_I7300
	tristate "Intel Clarksboro MCH"
	depends on EDAC_MM_EDAC && X86 && PCI
	help
	  Support for error detection and correction the Intel
	  Clarksboro MCH (Intel 7300 chipset).

247 248
config EDAC_SBRIDGE
	tristate "Intel Sandy-Bridge Integrated MC"
249
	depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
250
	depends on PCI_MMCONFIG
251 252 253 254
	help
	  Support for error detection and correction the Intel
	  Sandy Bridge Integrated Memory Controller.

255
config EDAC_MPC85XX
256
	tristate "Freescale MPC83xx / MPC85xx"
257
	depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
258 259
	help
	  Support for error detection and correction on the Freescale
260
	  MPC8349, MPC8560, MPC8540, MPC8548
261

262 263 264 265 266 267 268
config EDAC_MV64X60
	tristate "Marvell MV64x60"
	depends on EDAC_MM_EDAC && MV64X60
	help
	  Support for error detection and correction on the Marvell
	  MV64360 and MV64460 chipsets.

269 270 271
config EDAC_PASEMI
	tristate "PA Semi PWRficient"
	depends on EDAC_MM_EDAC && PCI
272
	depends on PPC_PASEMI
273 274 275 276
	help
	  Support for error detection and correction on PA Semi
	  PWRficient.

277 278
config EDAC_CELL
	tristate "Cell Broadband Engine memory controller"
279
	depends on EDAC_MM_EDAC && PPC_CELL_COMMON
280 281 282 283
	help
	  Support for error detection and correction on the
	  Cell Broadband Engine internal memory controller
	  on platform without a hypervisor
284

G
Grant Erickson 已提交
285 286 287 288 289 290 291 292 293
config EDAC_PPC4XX
	tristate "PPC4xx IBM DDR2 Memory Controller"
	depends on EDAC_MM_EDAC && 4xx
	help
	  This enables support for EDAC on the ECC memory used
	  with the IBM DDR2 memory controller found in various
	  PowerPC 4xx embedded processors such as the 405EX[r],
	  440SP, 440SPe, 460EX, 460GT and 460SX.

294 295
config EDAC_AMD8131
	tristate "AMD8131 HyperTransport PCI-X Tunnel"
296
	depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
297 298 299
	help
	  Support for error detection and correction on the
	  AMD8131 HyperTransport PCI-X Tunnel chip.
300 301
	  Note, add more Kconfig dependency if it's adopted
	  on some machine other than Maple.
302

303 304
config EDAC_AMD8111
	tristate "AMD8111 HyperTransport I/O Hub"
305
	depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
306 307 308
	help
	  Support for error detection and correction on the
	  AMD8111 HyperTransport I/O Hub chip.
309 310
	  Note, add more Kconfig dependency if it's adopted
	  on some machine other than Maple.
311

312 313 314 315 316 317 318 319 320
config EDAC_CPC925
	tristate "IBM CPC925 Memory Controller (PPC970FX)"
	depends on EDAC_MM_EDAC && PPC64
	help
	  Support for error detection and correction on the
	  IBM CPC925 Bridge and Memory Controller, which is
	  a companion chip to the PowerPC 970 family of
	  processors.

321 322 323 324 325 326 327 328
config EDAC_TILE
	tristate "Tilera Memory Controller"
	depends on EDAC_MM_EDAC && TILE
	default y
	help
	  Support for error detection and correction on the
	  Tilera memory controller.

329 330 331 332 333 334 335
config EDAC_HIGHBANK_MC
	tristate "Highbank Memory Controller"
	depends on EDAC_MM_EDAC && ARCH_HIGHBANK
	help
	  Support for error detection and correction on the
	  Calxeda Highbank memory controller.

336 337 338 339 340 341 342
config EDAC_HIGHBANK_L2
	tristate "Highbank L2 Cache"
	depends on EDAC_MM_EDAC && ARCH_HIGHBANK
	help
	  Support for error detection and correction on the
	  Calxeda Highbank memory controller.

R
Ralf Baechle 已提交
343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370
config EDAC_OCTEON_PC
	tristate "Cavium Octeon Primary Caches"
	depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
	help
	  Support for error detection and correction on the primary caches of
	  the cnMIPS cores of Cavium Octeon family SOCs.

config EDAC_OCTEON_L2C
	tristate "Cavium Octeon Secondary Caches (L2C)"
	depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
	help
	  Support for error detection and correction on the
	  Cavium Octeon family of SOCs.

config EDAC_OCTEON_LMC
	tristate "Cavium Octeon DRAM Memory Controller (LMC)"
	depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
	help
	  Support for error detection and correction on the
	  Cavium Octeon family of SOCs.

config EDAC_OCTEON_PCI
	tristate "Cavium Octeon PCI Controller"
	depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON
	help
	  Support for error detection and correction on the
	  Cavium Octeon family of SOCs.

371
endif # EDAC