amdgpu_cs.c 39.1 KB
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/*
 * Copyright 2008 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 */
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#include <linux/pagemap.h>
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#include <linux/sync_file.h>
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#include <drm/drmP.h>
#include <drm/amdgpu_drm.h>
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#include <drm/drm_syncobj.h>
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#include "amdgpu.h"
#include "amdgpu_trace.h"

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static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
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				      struct drm_amdgpu_cs_chunk_fence *data,
				      uint32_t *offset)
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{
	struct drm_gem_object *gobj;
40
	unsigned long size;
41

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	gobj = drm_gem_object_lookup(p->filp, data->handle);
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	if (gobj == NULL)
		return -EINVAL;

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	p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
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	p->uf_entry.priority = 0;
	p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
	p->uf_entry.tv.shared = true;
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	p->uf_entry.user_pages = NULL;
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	size = amdgpu_bo_size(p->uf_entry.robj);
	if (size != PAGE_SIZE || (data->offset + 8) > size)
		return -EINVAL;

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	*offset = data->offset;
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	drm_gem_object_put_unlocked(gobj);
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	if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
		amdgpu_bo_unref(&p->uf_entry.robj);
		return -EINVAL;
	}

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	return 0;
}

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static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
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{
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	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
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	struct amdgpu_vm *vm = &fpriv->vm;
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	union drm_amdgpu_cs *cs = data;
	uint64_t *chunk_array_user;
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	uint64_t *chunk_array;
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	unsigned size, num_ibs = 0;
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	uint32_t uf_offset = 0;
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	int i;
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	int ret;
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	if (cs->in.num_chunks == 0)
		return 0;

	chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
	if (!chunk_array)
		return -ENOMEM;
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	p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
	if (!p->ctx) {
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		ret = -EINVAL;
		goto free_chunk;
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	}
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	/* skip guilty context job */
	if (atomic_read(&p->ctx->guilty) == 1) {
		ret = -ECANCELED;
		goto free_chunk;
	}

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	mutex_lock(&p->ctx->lock);

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	/* get chunks */
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	chunk_array_user = u64_to_user_ptr(cs->in.chunks);
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	if (copy_from_user(chunk_array, chunk_array_user,
			   sizeof(uint64_t)*cs->in.num_chunks)) {
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		ret = -EFAULT;
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		goto free_chunk;
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	}

	p->nchunks = cs->in.num_chunks;
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	p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
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			    GFP_KERNEL);
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	if (!p->chunks) {
		ret = -ENOMEM;
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		goto free_chunk;
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	}

	for (i = 0; i < p->nchunks; i++) {
		struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
		struct drm_amdgpu_cs_chunk user_chunk;
		uint32_t __user *cdata;

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		chunk_ptr = u64_to_user_ptr(chunk_array[i]);
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		if (copy_from_user(&user_chunk, chunk_ptr,
				       sizeof(struct drm_amdgpu_cs_chunk))) {
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			ret = -EFAULT;
			i--;
			goto free_partial_kdata;
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		}
		p->chunks[i].chunk_id = user_chunk.chunk_id;
		p->chunks[i].length_dw = user_chunk.length_dw;

		size = p->chunks[i].length_dw;
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		cdata = u64_to_user_ptr(user_chunk.chunk_data);
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		p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
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		if (p->chunks[i].kdata == NULL) {
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			ret = -ENOMEM;
			i--;
			goto free_partial_kdata;
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		}
		size *= sizeof(uint32_t);
		if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
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			ret = -EFAULT;
			goto free_partial_kdata;
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		}

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		switch (p->chunks[i].chunk_id) {
		case AMDGPU_CHUNK_ID_IB:
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			++num_ibs;
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			break;

		case AMDGPU_CHUNK_ID_FENCE:
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			size = sizeof(struct drm_amdgpu_cs_chunk_fence);
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			if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
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				ret = -EINVAL;
				goto free_partial_kdata;
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			}
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			ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
							 &uf_offset);
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			if (ret)
				goto free_partial_kdata;

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			break;

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		case AMDGPU_CHUNK_ID_DEPENDENCIES:
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		case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
		case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
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			break;

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		default:
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			ret = -EINVAL;
			goto free_partial_kdata;
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		}
	}

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	ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
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	if (ret)
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		goto free_all_kdata;
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	if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
		ret = -ECANCELED;
		goto free_all_kdata;
	}
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	if (p->uf_entry.robj)
		p->job->uf_addr = uf_offset;
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	kfree(chunk_array);
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	return 0;

free_all_kdata:
	i = p->nchunks - 1;
free_partial_kdata:
	for (; i >= 0; i--)
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		kvfree(p->chunks[i].kdata);
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	kfree(p->chunks);
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	p->chunks = NULL;
	p->nchunks = 0;
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free_chunk:
	kfree(chunk_array);

	return ret;
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}

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/* Convert microseconds to bytes. */
static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
{
	if (us <= 0 || !adev->mm_stats.log2_max_MBps)
		return 0;

	/* Since accum_us is incremented by a million per second, just
	 * multiply it by the number of MB/s to get the number of bytes.
	 */
	return us << adev->mm_stats.log2_max_MBps;
}

static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
{
	if (!adev->mm_stats.log2_max_MBps)
		return 0;

	return bytes >> adev->mm_stats.log2_max_MBps;
}

/* Returns how many bytes TTM can move right now. If no bytes can be moved,
 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 * which means it can go over the threshold once. If that happens, the driver
 * will be in debt and no other buffer migrations can be done until that debt
 * is repaid.
 *
 * This approach allows moving a buffer of any size (it's important to allow
 * that).
 *
 * The currency is simply time in microseconds and it increases as the clock
 * ticks. The accumulated microseconds (us) are converted to bytes and
 * returned.
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 */
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static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
					      u64 *max_bytes,
					      u64 *max_vis_bytes)
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{
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	s64 time_us, increment_us;
	u64 free_vram, total_vram, used_vram;
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	/* Allow a maximum of 200 accumulated ms. This is basically per-IB
	 * throttling.
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	 *
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	 * It means that in order to get full max MBps, at least 5 IBs per
	 * second must be submitted and not more than 200ms apart from each
	 * other.
	 */
	const s64 us_upper_bound = 200000;
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	if (!adev->mm_stats.log2_max_MBps) {
		*max_bytes = 0;
		*max_vis_bytes = 0;
		return;
	}
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	total_vram = adev->gmc.real_vram_size - adev->vram_pin_size;
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	used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
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	free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;

	spin_lock(&adev->mm_stats.lock);

	/* Increase the amount of accumulated us. */
	time_us = ktime_to_us(ktime_get());
	increment_us = time_us - adev->mm_stats.last_update_us;
	adev->mm_stats.last_update_us = time_us;
	adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
                                      us_upper_bound);

	/* This prevents the short period of low performance when the VRAM
	 * usage is low and the driver is in debt or doesn't have enough
	 * accumulated us to fill VRAM quickly.
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	 *
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	 * The situation can occur in these cases:
	 * - a lot of VRAM is freed by userspace
	 * - the presence of a big buffer causes a lot of evictions
	 *   (solution: split buffers into smaller ones)
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	 *
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	 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
	 * accum_us to a positive number.
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	 */
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	if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
		s64 min_us;

		/* Be more aggresive on dGPUs. Try to fill a portion of free
		 * VRAM now.
		 */
		if (!(adev->flags & AMD_IS_APU))
			min_us = bytes_to_us(adev, free_vram / 4);
		else
			min_us = 0; /* Reset accum_us on APUs. */

		adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
	}
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	/* This is set to 0 if the driver is in debt to disallow (optional)
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	 * buffer moves.
	 */
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	*max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);

	/* Do the same for visible VRAM if half of it is free */
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	if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size) {
		u64 total_vis_vram = adev->gmc.visible_vram_size;
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		u64 used_vis_vram =
			amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
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		if (used_vis_vram < total_vis_vram) {
			u64 free_vis_vram = total_vis_vram - used_vis_vram;
			adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
							  increment_us, us_upper_bound);

			if (free_vis_vram >= total_vis_vram / 2)
				adev->mm_stats.accum_us_vis =
					max(bytes_to_us(adev, free_vis_vram / 2),
					    adev->mm_stats.accum_us_vis);
		}

		*max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
	} else {
		*max_vis_bytes = 0;
	}
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	spin_unlock(&adev->mm_stats.lock);
}

/* Report how many bytes have really been moved for the last command
 * submission. This can result in a debt that can stop buffer migrations
 * temporarily.
 */
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void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
				  u64 num_vis_bytes)
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{
	spin_lock(&adev->mm_stats.lock);
	adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
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	adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
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	spin_unlock(&adev->mm_stats.lock);
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}

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static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
				 struct amdgpu_bo *bo)
{
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	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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	struct ttm_operation_ctx ctx = {
		.interruptible = true,
		.no_wait_gpu = false,
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		.resv = bo->tbo.resv,
		.flags = 0
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	};
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	uint32_t domain;
	int r;

	if (bo->pin_count)
		return 0;

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	/* Don't move this buffer if we have depleted our allowance
	 * to move it. Don't move anything if the threshold is zero.
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	 */
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	if (p->bytes_moved < p->bytes_moved_threshold) {
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		if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
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		    (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
			/* And don't move a CPU_ACCESS_REQUIRED BO to limited
			 * visible VRAM if we've depleted our allowance to do
			 * that.
			 */
			if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
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				domain = bo->preferred_domains;
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			else
				domain = bo->allowed_domains;
		} else {
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			domain = bo->preferred_domains;
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		}
	} else {
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		domain = bo->allowed_domains;
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	}
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retry:
	amdgpu_ttm_placement_from_domain(bo, domain);
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	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
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	p->bytes_moved += ctx.bytes_moved;
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	if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
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	    amdgpu_bo_in_cpu_visible_vram(bo))
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		p->bytes_moved_vis += ctx.bytes_moved;
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	if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
		domain = bo->allowed_domains;
		goto retry;
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	}

	return r;
}

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/* Last resort, try to evict something from the current working set */
static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
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				struct amdgpu_bo *validated)
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{
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	uint32_t domain = validated->allowed_domains;
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	struct ttm_operation_ctx ctx = { true, false };
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	int r;

	if (!p->evictable)
		return false;

	for (;&p->evictable->tv.head != &p->validated;
	     p->evictable = list_prev_entry(p->evictable, tv.head)) {

		struct amdgpu_bo_list_entry *candidate = p->evictable;
		struct amdgpu_bo *bo = candidate->robj;
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		struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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		bool update_bytes_moved_vis;
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		uint32_t other;

		/* If we reached our current BO we can forget it */
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		if (candidate->robj == validated)
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			break;

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		/* We can't move pinned BOs here */
		if (bo->pin_count)
			continue;

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		other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);

		/* Check if this BO is in one of the domains we need space for */
		if (!(other & domain))
			continue;

		/* Check if we can move this BO somewhere else */
		other = bo->allowed_domains & ~domain;
		if (!other)
			continue;

		/* Good we can try to move this BO somewhere else */
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		update_bytes_moved_vis =
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			adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
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			amdgpu_bo_in_cpu_visible_vram(bo);
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		amdgpu_ttm_placement_from_domain(bo, other);
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		r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
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		p->bytes_moved += ctx.bytes_moved;
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		if (update_bytes_moved_vis)
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			p->bytes_moved_vis += ctx.bytes_moved;
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		if (unlikely(r))
			break;

		p->evictable = list_prev_entry(p->evictable, tv.head);
		list_move(&candidate->tv.head, &p->validated);

		return true;
	}

	return false;
}

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static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
{
	struct amdgpu_cs_parser *p = param;
	int r;

	do {
		r = amdgpu_cs_bo_validate(p, bo);
	} while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
	if (r)
		return r;

	if (bo->shadow)
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		r = amdgpu_cs_bo_validate(p, bo->shadow);
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	return r;
}

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static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
475
			    struct list_head *validated)
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{
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	struct ttm_operation_ctx ctx = { true, false };
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	struct amdgpu_bo_list_entry *lobj;
	int r;

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	list_for_each_entry(lobj, validated, tv.head) {
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		struct amdgpu_bo *bo = lobj->robj;
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		bool binding_userptr = false;
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		struct mm_struct *usermm;
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		usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
		if (usermm && usermm != current->mm)
			return -EPERM;

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		/* Check if we have user pages and nobody bound the BO already */
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		if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
		    lobj->user_pages) {
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			amdgpu_ttm_placement_from_domain(bo,
							 AMDGPU_GEM_DOMAIN_CPU);
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			r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
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			if (r)
				return r;
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			amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
						     lobj->user_pages);
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			binding_userptr = true;
		}

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		if (p->evictable == lobj)
			p->evictable = NULL;

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		r = amdgpu_cs_validate(p, bo);
507
		if (r)
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			return r;
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510
		if (binding_userptr) {
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			kvfree(lobj->user_pages);
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			lobj->user_pages = NULL;
		}
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	}
	return 0;
}

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static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
				union drm_amdgpu_cs *cs)
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{
	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
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	struct amdgpu_bo_list_entry *e;
523
	struct list_head duplicates;
524
	unsigned i, tries = 10;
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	struct amdgpu_bo *gds;
	struct amdgpu_bo *gws;
	struct amdgpu_bo *oa;
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	int r;
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	INIT_LIST_HEAD(&p->validated);

	p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
533
	if (p->bo_list) {
534
		amdgpu_bo_list_get_list(p->bo_list, &p->validated);
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		if (p->bo_list->first_userptr != p->bo_list->num_entries)
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			p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
537
	}
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539
	INIT_LIST_HEAD(&duplicates);
540
	amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
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542
	if (p->uf_entry.robj && !p->uf_entry.robj->parent)
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		list_add(&p->uf_entry.tv.head, &p->validated);

545 546 547 548 549 550
	while (1) {
		struct list_head need_pages;
		unsigned i;

		r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
					   &duplicates);
551
		if (unlikely(r != 0)) {
552 553
			if (r != -ERESTARTSYS)
				DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
554
			goto error_free_pages;
555
		}
556 557 558 559 560 561 562 563

		/* Without a BO list we don't have userptr BOs */
		if (!p->bo_list)
			break;

		INIT_LIST_HEAD(&need_pages);
		for (i = p->bo_list->first_userptr;
		     i < p->bo_list->num_entries; ++i) {
564
			struct amdgpu_bo *bo;
565 566

			e = &p->bo_list->array[i];
567
			bo = e->robj;
568

569
			if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm,
570 571 572
				 &e->user_invalidated) && e->user_pages) {

				/* We acquired a page array, but somebody
573
				 * invalidated it. Free it and try again
574 575
				 */
				release_pages(e->user_pages,
576
					      bo->tbo.ttm->num_pages);
M
Michal Hocko 已提交
577
				kvfree(e->user_pages);
578 579 580
				e->user_pages = NULL;
			}

581
			if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
582 583 584 585 586 587 588 589 590 591 592 593 594 595
			    !e->user_pages) {
				list_del(&e->tv.head);
				list_add(&e->tv.head, &need_pages);

				amdgpu_bo_unreserve(e->robj);
			}
		}

		if (list_empty(&need_pages))
			break;

		/* Unreserve everything again. */
		ttm_eu_backoff_reservation(&p->ticket, &p->validated);

596
		/* We tried too many times, just abort */
597 598
		if (!--tries) {
			r = -EDEADLK;
599
			DRM_ERROR("deadlock in %s\n", __func__);
600 601 602
			goto error_free_pages;
		}

A
Alex Xie 已提交
603
		/* Fill the page arrays for all userptrs. */
604 605 606
		list_for_each_entry(e, &need_pages, tv.head) {
			struct ttm_tt *ttm = e->robj->tbo.ttm;

M
Michal Hocko 已提交
607 608 609
			e->user_pages = kvmalloc_array(ttm->num_pages,
							 sizeof(struct page*),
							 GFP_KERNEL | __GFP_ZERO);
610 611
			if (!e->user_pages) {
				r = -ENOMEM;
612
				DRM_ERROR("calloc failure in %s\n", __func__);
613 614 615 616 617
				goto error_free_pages;
			}

			r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
			if (r) {
618
				DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
M
Michal Hocko 已提交
619
				kvfree(e->user_pages);
620 621 622 623 624 625 626 627
				e->user_pages = NULL;
				goto error_free_pages;
			}
		}

		/* And try again. */
		list_splice(&need_pages, &p->validated);
	}
628

629 630
	amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
					  &p->bytes_moved_vis_threshold);
631
	p->bytes_moved = 0;
632
	p->bytes_moved_vis = 0;
633 634 635
	p->evictable = list_last_entry(&p->validated,
				       struct amdgpu_bo_list_entry,
				       tv.head);
636

637 638 639 640 641 642 643
	r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
				      amdgpu_cs_validate, p);
	if (r) {
		DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
		goto error_validate;
	}

644
	r = amdgpu_cs_list_validate(p, &duplicates);
645 646
	if (r) {
		DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
647
		goto error_validate;
648
	}
649

650
	r = amdgpu_cs_list_validate(p, &p->validated);
651 652
	if (r) {
		DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
653
		goto error_validate;
654
	}
655

656 657
	amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
				     p->bytes_moved_vis);
658

659 660 661 662
	if (p->bo_list) {
		struct amdgpu_vm *vm = &fpriv->vm;
		unsigned i;

663 664 665
		gds = p->bo_list->gds_obj;
		gws = p->bo_list->gws_obj;
		oa = p->bo_list->oa_obj;
666 667 668 669 670
		for (i = 0; i < p->bo_list->num_entries; i++) {
			struct amdgpu_bo *bo = p->bo_list->array[i].robj;

			p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
		}
671 672 673 674 675
	} else {
		gds = p->adev->gds.gds_gfx_bo;
		gws = p->adev->gds.gws_gfx_bo;
		oa = p->adev->gds.oa_gfx_bo;
	}
676

677 678 679 680 681 682 683 684 685 686 687
	if (gds) {
		p->job->gds_base = amdgpu_bo_gpu_offset(gds);
		p->job->gds_size = amdgpu_bo_size(gds);
	}
	if (gws) {
		p->job->gws_base = amdgpu_bo_gpu_offset(gws);
		p->job->gws_size = amdgpu_bo_size(gws);
	}
	if (oa) {
		p->job->oa_base = amdgpu_bo_gpu_offset(oa);
		p->job->oa_size = amdgpu_bo_size(oa);
688
	}
689

690 691 692
	if (!r && p->uf_entry.robj) {
		struct amdgpu_bo *uf = p->uf_entry.robj;

693
		r = amdgpu_ttm_alloc_gart(&uf->tbo);
694 695
		p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
	}
696

697
error_validate:
698
	if (r)
699
		ttm_eu_backoff_reservation(&p->ticket, &p->validated);
A
Alex Deucher 已提交
700

701 702 703 704 705 706 707 708 709 710 711
error_free_pages:

	if (p->bo_list) {
		for (i = p->bo_list->first_userptr;
		     i < p->bo_list->num_entries; ++i) {
			e = &p->bo_list->array[i];

			if (!e->user_pages)
				continue;

			release_pages(e->user_pages,
712
				      e->robj->tbo.ttm->num_pages);
M
Michal Hocko 已提交
713
			kvfree(e->user_pages);
714 715 716
		}
	}

A
Alex Deucher 已提交
717 718 719 720 721 722 723 724 725 726
	return r;
}

static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
{
	struct amdgpu_bo_list_entry *e;
	int r;

	list_for_each_entry(e, &p->validated, tv.head) {
		struct reservation_object *resv = e->robj->tbo.resv;
727 728
		r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
				     amdgpu_bo_explicit_sync(e->robj));
A
Alex Deucher 已提交
729 730 731 732 733 734 735

		if (r)
			return r;
	}
	return 0;
}

736 737 738 739 740 741 742 743
/**
 * cs_parser_fini() - clean parser states
 * @parser:	parser structure holding parsing context.
 * @error:	error number
 *
 * If error is set than unvalidate buffer, otherwise just free memory
 * used by parsing context.
 **/
744 745
static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
				  bool backoff)
C
Chunming Zhou 已提交
746
{
747 748
	unsigned i;

749
	if (error && backoff)
A
Alex Deucher 已提交
750 751
		ttm_eu_backoff_reservation(&parser->ticket,
					   &parser->validated);
752 753 754 755 756

	for (i = 0; i < parser->num_post_dep_syncobjs; i++)
		drm_syncobj_put(parser->post_dep_syncobjs[i]);
	kfree(parser->post_dep_syncobjs);

757
	dma_fence_put(parser->fence);
758

759 760
	if (parser->ctx) {
		mutex_unlock(&parser->ctx->lock);
761
		amdgpu_ctx_put(parser->ctx);
762
	}
763 764 765
	if (parser->bo_list)
		amdgpu_bo_list_put(parser->bo_list);

A
Alex Deucher 已提交
766
	for (i = 0; i < parser->nchunks; i++)
M
Michal Hocko 已提交
767
		kvfree(parser->chunks[i].kdata);
A
Alex Deucher 已提交
768
	kfree(parser->chunks);
769 770
	if (parser->job)
		amdgpu_job_free(parser->job);
771
	amdgpu_bo_unref(&parser->uf_entry.robj);
A
Alex Deucher 已提交
772 773
}

774
static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
A
Alex Deucher 已提交
775 776
{
	struct amdgpu_device *adev = p->adev;
777 778
	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
	struct amdgpu_vm *vm = &fpriv->vm;
A
Alex Deucher 已提交
779 780 781 782
	struct amdgpu_bo_va *bo_va;
	struct amdgpu_bo *bo;
	int i, r;

783
	r = amdgpu_vm_clear_freed(adev, vm, NULL);
A
Alex Deucher 已提交
784 785 786
	if (r)
		return r;

787 788 789 790 791
	r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
	if (r)
		return r;

	r = amdgpu_sync_fence(adev, &p->job->sync,
792
			      fpriv->prt_va->last_pt_update, false);
793 794 795
	if (r)
		return r;

M
Monk Liu 已提交
796 797
	if (amdgpu_sriov_vf(adev)) {
		struct dma_fence *f;
798 799

		bo_va = fpriv->csa_va;
M
Monk Liu 已提交
800 801 802 803 804 805
		BUG_ON(!bo_va);
		r = amdgpu_vm_bo_update(adev, bo_va, false);
		if (r)
			return r;

		f = bo_va->last_pt_update;
806
		r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
M
Monk Liu 已提交
807 808 809 810
		if (r)
			return r;
	}

A
Alex Deucher 已提交
811 812
	if (p->bo_list) {
		for (i = 0; i < p->bo_list->num_entries; i++) {
813
			struct dma_fence *f;
814

A
Alex Deucher 已提交
815 816 817 818 819 820 821 822 823
			/* ignore duplicates */
			bo = p->bo_list->array[i].robj;
			if (!bo)
				continue;

			bo_va = p->bo_list->array[i].bo_va;
			if (bo_va == NULL)
				continue;

824
			r = amdgpu_vm_bo_update(adev, bo_va, false);
A
Alex Deucher 已提交
825 826 827
			if (r)
				return r;

828
			f = bo_va->last_pt_update;
829
			r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
830 831
			if (r)
				return r;
A
Alex Deucher 已提交
832
		}
833 834 835

	}

836
	r = amdgpu_vm_handle_moved(adev, vm);
837 838 839
	if (r)
		return r;

840 841 842 843
	r = amdgpu_vm_update_directories(adev, vm);
	if (r)
		return r;

844
	r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
845 846
	if (r)
		return r;
847 848 849 850 851 852 853 854 855

	if (amdgpu_vm_debug && p->bo_list) {
		/* Invalidate all BOs to test for userspace bugs */
		for (i = 0; i < p->bo_list->num_entries; i++) {
			/* ignore duplicates */
			bo = p->bo_list->array[i].robj;
			if (!bo)
				continue;

856
			amdgpu_vm_bo_invalidate(adev, bo, false);
857
		}
A
Alex Deucher 已提交
858 859
	}

860
	return r;
A
Alex Deucher 已提交
861 862 863
}

static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
864
				 struct amdgpu_cs_parser *p)
A
Alex Deucher 已提交
865
{
866
	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
A
Alex Deucher 已提交
867
	struct amdgpu_vm *vm = &fpriv->vm;
868
	struct amdgpu_ring *ring = p->job->ring;
869
	int r;
A
Alex Deucher 已提交
870 871

	/* Only for UVD/VCE VM emulation */
872 873
	if (p->job->ring->funcs->parse_cs) {
		unsigned i, j;
874

875 876
		for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
			struct drm_amdgpu_cs_chunk_ib *chunk_ib;
877 878
			struct amdgpu_bo_va_mapping *m;
			struct amdgpu_bo *aobj = NULL;
879
			struct amdgpu_cs_chunk *chunk;
880
			uint64_t offset, va_start;
881
			struct amdgpu_ib *ib;
882 883
			uint8_t *kptr;

884 885 886 887 888 889 890
			chunk = &p->chunks[i];
			ib = &p->job->ibs[j];
			chunk_ib = chunk->kdata;

			if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
				continue;

891 892
			va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
			r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
893 894 895 896
			if (r) {
				DRM_ERROR("IB va_start is invalid\n");
				return r;
			}
A
Alex Deucher 已提交
897

898
			if ((va_start + chunk_ib->ib_bytes) >
899
			    (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
900 901 902 903 904 905 906 907 908 909 910
				DRM_ERROR("IB va_start+ib_bytes is invalid\n");
				return -EINVAL;
			}

			/* the IB should be reserved at this point */
			r = amdgpu_bo_kmap(aobj, (void **)&kptr);
			if (r) {
				return r;
			}

			offset = m->start * AMDGPU_GPU_PAGE_SIZE;
911
			kptr += va_start - offset;
912 913 914 915 916

			memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
			amdgpu_bo_kunmap(aobj);

			r = amdgpu_ring_parse_cs(ring, p, j);
A
Alex Deucher 已提交
917 918
			if (r)
				return r;
919 920

			j++;
A
Alex Deucher 已提交
921
		}
922 923 924
	}

	if (p->job->vm) {
925
		p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
926

927
		r = amdgpu_bo_vm_update_pte(p);
928 929 930
		if (r)
			return r;
	}
A
Alex Deucher 已提交
931

932
	return amdgpu_cs_sync_rings(p);
A
Alex Deucher 已提交
933 934 935 936 937 938 939 940
}

static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
			     struct amdgpu_cs_parser *parser)
{
	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
	struct amdgpu_vm *vm = &fpriv->vm;
	int i, j;
M
Monk Liu 已提交
941
	int r, ce_preempt = 0, de_preempt = 0;
A
Alex Deucher 已提交
942

943
	for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
A
Alex Deucher 已提交
944 945 946 947 948 949
		struct amdgpu_cs_chunk *chunk;
		struct amdgpu_ib *ib;
		struct drm_amdgpu_cs_chunk_ib *chunk_ib;
		struct amdgpu_ring *ring;

		chunk = &parser->chunks[i];
950
		ib = &parser->job->ibs[j];
A
Alex Deucher 已提交
951 952 953 954 955
		chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;

		if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
			continue;

956
		if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
957
			if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
958 959 960 961
				if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
					ce_preempt++;
				else
					de_preempt++;
962
			}
963 964 965

			/* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
			if (ce_preempt > 1 || de_preempt > 1)
966
				return -EINVAL;
M
Monk Liu 已提交
967 968
		}

969 970
		r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type,
					 chunk_ib->ip_instance, chunk_ib->ring, &ring);
971
		if (r)
A
Alex Deucher 已提交
972 973
			return r;

M
Monk Liu 已提交
974
		if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
975 976 977 978 979 980 981
			parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
			if (!parser->ctx->preamble_presented) {
				parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
				parser->ctx->preamble_presented = true;
			}
		}

982 983 984 985 986
		if (parser->job->ring && parser->job->ring != ring)
			return -EINVAL;

		parser->job->ring = ring;

987 988 989 990 991 992
		r =  amdgpu_ib_get(adev, vm,
					ring->funcs->parse_cs ? chunk_ib->ib_bytes : 0,
					ib);
		if (r) {
			DRM_ERROR("Failed to get ib !\n");
			return r;
A
Alex Deucher 已提交
993 994
		}

995
		ib->gpu_addr = chunk_ib->va_start;
996
		ib->length_dw = chunk_ib->ib_bytes / 4;
997
		ib->flags = chunk_ib->flags;
998

A
Alex Deucher 已提交
999 1000 1001
		j++;
	}

1002
	/* UVD & VCE fw doesn't support user fences */
1003
	if (parser->job->uf_addr && (
1004 1005
	    parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
	    parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
1006
		return -EINVAL;
A
Alex Deucher 已提交
1007

1008
	return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->job->ring->idx);
A
Alex Deucher 已提交
1009 1010
}

1011 1012
static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
				       struct amdgpu_cs_chunk *chunk)
1013
{
1014
	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1015 1016 1017
	unsigned num_deps;
	int i, r;
	struct drm_amdgpu_cs_chunk_dep *deps;
1018

1019 1020 1021
	deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
	num_deps = chunk->length_dw * 4 /
		sizeof(struct drm_amdgpu_cs_chunk_dep);
1022

1023 1024 1025 1026
	for (i = 0; i < num_deps; ++i) {
		struct amdgpu_ring *ring;
		struct amdgpu_ctx *ctx;
		struct dma_fence *fence;
1027

1028 1029 1030
		ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
		if (ctx == NULL)
			return -EINVAL;
1031

1032 1033 1034 1035 1036 1037 1038 1039
		r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr,
					 deps[i].ip_type,
					 deps[i].ip_instance,
					 deps[i].ring, &ring);
		if (r) {
			amdgpu_ctx_put(ctx);
			return r;
		}
1040

1041 1042 1043 1044 1045 1046 1047
		fence = amdgpu_ctx_get_fence(ctx, ring,
					     deps[i].handle);
		if (IS_ERR(fence)) {
			r = PTR_ERR(fence);
			amdgpu_ctx_put(ctx);
			return r;
		} else if (fence) {
1048 1049
			r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,
					true);
1050 1051 1052 1053 1054 1055 1056 1057
			dma_fence_put(fence);
			amdgpu_ctx_put(ctx);
			if (r)
				return r;
		}
	}
	return 0;
}
1058

1059 1060 1061 1062 1063
static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
						 uint32_t handle)
{
	int r;
	struct dma_fence *fence;
1064
	r = drm_syncobj_find_fence(p->filp, handle, &fence);
1065 1066 1067
	if (r)
		return r;

1068
	r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107
	dma_fence_put(fence);

	return r;
}

static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
					    struct amdgpu_cs_chunk *chunk)
{
	unsigned num_deps;
	int i, r;
	struct drm_amdgpu_cs_chunk_sem *deps;

	deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
	num_deps = chunk->length_dw * 4 /
		sizeof(struct drm_amdgpu_cs_chunk_sem);

	for (i = 0; i < num_deps; ++i) {
		r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
		if (r)
			return r;
	}
	return 0;
}

static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
					     struct amdgpu_cs_chunk *chunk)
{
	unsigned num_deps;
	int i;
	struct drm_amdgpu_cs_chunk_sem *deps;
	deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
	num_deps = chunk->length_dw * 4 /
		sizeof(struct drm_amdgpu_cs_chunk_sem);

	p->post_dep_syncobjs = kmalloc_array(num_deps,
					     sizeof(struct drm_syncobj *),
					     GFP_KERNEL);
	p->num_post_dep_syncobjs = 0;

1108 1109 1110
	if (!p->post_dep_syncobjs)
		return -ENOMEM;

1111 1112 1113 1114 1115 1116 1117 1118 1119
	for (i = 0; i < num_deps; ++i) {
		p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
		if (!p->post_dep_syncobjs[i])
			return -EINVAL;
		p->num_post_dep_syncobjs++;
	}
	return 0;
}

1120 1121 1122 1123
static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
				  struct amdgpu_cs_parser *p)
{
	int i, r;
1124

1125 1126
	for (i = 0; i < p->nchunks; ++i) {
		struct amdgpu_cs_chunk *chunk;
1127

1128
		chunk = &p->chunks[i];
1129

1130 1131 1132 1133
		if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
			r = amdgpu_cs_process_fence_dep(p, chunk);
			if (r)
				return r;
1134 1135 1136 1137 1138 1139 1140 1141
		} else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
			r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
			if (r)
				return r;
		} else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
			r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
			if (r)
				return r;
1142 1143 1144 1145 1146 1147
		}
	}

	return 0;
}

1148 1149 1150 1151
static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
{
	int i;

1152 1153
	for (i = 0; i < p->num_post_dep_syncobjs; ++i)
		drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
1154 1155
}

1156 1157 1158
static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
			    union drm_amdgpu_cs *cs)
{
1159
	struct amdgpu_ring *ring = p->job->ring;
1160
	struct drm_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
1161
	struct amdgpu_job *job;
1162
	unsigned i;
1163 1164
	uint64_t seq;

1165
	int r;
1166

1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179
	amdgpu_mn_lock(p->mn);
	if (p->bo_list) {
		for (i = p->bo_list->first_userptr;
		     i < p->bo_list->num_entries; ++i) {
			struct amdgpu_bo *bo = p->bo_list->array[i].robj;

			if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {
				amdgpu_mn_unlock(p->mn);
				return -ERESTARTSYS;
			}
		}
	}

1180 1181
	job = p->job;
	p->job = NULL;
1182

1183
	r = drm_sched_job_init(&job->base, &ring->sched, entity, p->filp);
1184
	if (r) {
1185
		amdgpu_job_free(job);
1186
		amdgpu_mn_unlock(p->mn);
1187
		return r;
1188 1189
	}

1190
	job->owner = p->filp;
1191
	job->fence_ctx = entity->fence_context;
1192
	p->fence = dma_fence_get(&job->base.s_fence->finished);
1193

1194 1195 1196 1197 1198 1199 1200 1201 1202
	r = amdgpu_ctx_add_fence(p->ctx, ring, p->fence, &seq);
	if (r) {
		dma_fence_put(p->fence);
		dma_fence_put(&job->base.s_fence->finished);
		amdgpu_job_free(job);
		amdgpu_mn_unlock(p->mn);
		return r;
	}

1203 1204
	amdgpu_cs_post_dependencies(p);

1205 1206 1207
	cs->out.handle = seq;
	job->uf_sequence = seq;

1208
	amdgpu_job_free_resources(job);
1209
	amdgpu_ring_priority_get(job->ring, job->base.s_priority);
1210 1211

	trace_amdgpu_cs_ioctl(job);
1212
	drm_sched_entity_push_job(&job->base, entity);
1213 1214 1215 1216

	ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
	amdgpu_mn_unlock(p->mn);

1217 1218 1219
	return 0;
}

C
Chunming Zhou 已提交
1220 1221 1222 1223
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	struct amdgpu_device *adev = dev->dev_private;
	union drm_amdgpu_cs *cs = data;
1224
	struct amdgpu_cs_parser parser = {};
1225 1226
	bool reserved_buffers = false;
	int i, r;
C
Chunming Zhou 已提交
1227

1228
	if (!adev->accel_working)
C
Chunming Zhou 已提交
1229
		return -EBUSY;
1230

1231 1232 1233 1234
	parser.adev = adev;
	parser.filp = filp;

	r = amdgpu_cs_parser_init(&parser, data);
A
Alex Deucher 已提交
1235
	if (r) {
C
Chunming Zhou 已提交
1236
		DRM_ERROR("Failed to initialize parser !\n");
1237
		goto out;
1238 1239
	}

1240 1241 1242 1243
	r = amdgpu_cs_ib_fill(adev, &parser);
	if (r)
		goto out;

1244 1245 1246 1247 1248 1249 1250
	r = amdgpu_cs_parser_bos(&parser, data);
	if (r) {
		if (r == -ENOMEM)
			DRM_ERROR("Not enough memory for command submission!\n");
		else if (r != -ERESTARTSYS)
			DRM_ERROR("Failed to process the buffer list %d!\n", r);
		goto out;
1251 1252
	}

1253
	reserved_buffers = true;
1254

1255 1256 1257 1258 1259 1260
	r = amdgpu_cs_dependencies(adev, &parser);
	if (r) {
		DRM_ERROR("Failed in the dependencies handling %d!\n", r);
		goto out;
	}

1261
	for (i = 0; i < parser.job->num_ibs; i++)
1262
		trace_amdgpu_cs(&parser, i);
1263

1264
	r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1265 1266 1267
	if (r)
		goto out;

C
Christian König 已提交
1268
	r = amdgpu_cs_submit(&parser, cs);
A
Alex Deucher 已提交
1269 1270

out:
1271
	amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
A
Alex Deucher 已提交
1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289
	return r;
}

/**
 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 *
 * @dev: drm device
 * @data: data from userspace
 * @filp: file private
 *
 * Wait for the command submission identified by handle to finish.
 */
int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *filp)
{
	union drm_amdgpu_wait_cs *wait = data;
	struct amdgpu_device *adev = dev->dev_private;
	unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1290
	struct amdgpu_ring *ring = NULL;
1291
	struct amdgpu_ctx *ctx;
1292
	struct dma_fence *fence;
A
Alex Deucher 已提交
1293 1294
	long r;

1295 1296 1297
	ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
	if (ctx == NULL)
		return -EINVAL;
A
Alex Deucher 已提交
1298

1299 1300 1301 1302 1303 1304 1305 1306
	r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
				 wait->in.ip_type, wait->in.ip_instance,
				 wait->in.ring, &ring);
	if (r) {
		amdgpu_ctx_put(ctx);
		return r;
	}

1307 1308 1309 1310
	fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
	if (IS_ERR(fence))
		r = PTR_ERR(fence);
	else if (fence) {
1311
		r = dma_fence_wait_timeout(fence, true, timeout);
1312 1313
		if (r > 0 && fence->error)
			r = fence->error;
1314
		dma_fence_put(fence);
1315 1316
	} else
		r = 1;
C
Chunming Zhou 已提交
1317

1318
	amdgpu_ctx_put(ctx);
A
Alex Deucher 已提交
1319 1320 1321 1322 1323 1324 1325 1326 1327
	if (r < 0)
		return r;

	memset(wait, 0, sizeof(*wait));
	wait->out.status = (r == 0);

	return 0;
}

1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347
/**
 * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
 *
 * @adev: amdgpu device
 * @filp: file private
 * @user: drm_amdgpu_fence copied from user space
 */
static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
					     struct drm_file *filp,
					     struct drm_amdgpu_fence *user)
{
	struct amdgpu_ring *ring;
	struct amdgpu_ctx *ctx;
	struct dma_fence *fence;
	int r;

	ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
	if (ctx == NULL)
		return ERR_PTR(-EINVAL);

1348 1349 1350 1351 1352 1353 1354
	r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type,
				 user->ip_instance, user->ring, &ring);
	if (r) {
		amdgpu_ctx_put(ctx);
		return ERR_PTR(r);
	}

1355 1356 1357 1358 1359 1360
	fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no);
	amdgpu_ctx_put(ctx);

	return fence;
}

1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416
int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *filp)
{
	struct amdgpu_device *adev = dev->dev_private;
	union drm_amdgpu_fence_to_handle *info = data;
	struct dma_fence *fence;
	struct drm_syncobj *syncobj;
	struct sync_file *sync_file;
	int fd, r;

	fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
	if (IS_ERR(fence))
		return PTR_ERR(fence);

	switch (info->in.what) {
	case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
		r = drm_syncobj_create(&syncobj, 0, fence);
		dma_fence_put(fence);
		if (r)
			return r;
		r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
		drm_syncobj_put(syncobj);
		return r;

	case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
		r = drm_syncobj_create(&syncobj, 0, fence);
		dma_fence_put(fence);
		if (r)
			return r;
		r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
		drm_syncobj_put(syncobj);
		return r;

	case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
		fd = get_unused_fd_flags(O_CLOEXEC);
		if (fd < 0) {
			dma_fence_put(fence);
			return fd;
		}

		sync_file = sync_file_create(fence);
		dma_fence_put(fence);
		if (!sync_file) {
			put_unused_fd(fd);
			return -ENOMEM;
		}

		fd_install(fd, sync_file->file);
		info->out.handle = fd;
		return 0;

	default:
		return -EINVAL;
	}
}

1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444
/**
 * amdgpu_cs_wait_all_fence - wait on all fences to signal
 *
 * @adev: amdgpu device
 * @filp: file private
 * @wait: wait parameters
 * @fences: array of drm_amdgpu_fence
 */
static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
				     struct drm_file *filp,
				     union drm_amdgpu_wait_fences *wait,
				     struct drm_amdgpu_fence *fences)
{
	uint32_t fence_count = wait->in.fence_count;
	unsigned int i;
	long r = 1;

	for (i = 0; i < fence_count; i++) {
		struct dma_fence *fence;
		unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);

		fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
		if (IS_ERR(fence))
			return PTR_ERR(fence);
		else if (!fence)
			continue;

		r = dma_fence_wait_timeout(fence, true, timeout);
1445
		dma_fence_put(fence);
1446 1447 1448 1449 1450
		if (r < 0)
			return r;

		if (r == 0)
			break;
1451 1452 1453

		if (fence->error)
			return fence->error;
1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498
	}

	memset(wait, 0, sizeof(*wait));
	wait->out.status = (r > 0);

	return 0;
}

/**
 * amdgpu_cs_wait_any_fence - wait on any fence to signal
 *
 * @adev: amdgpu device
 * @filp: file private
 * @wait: wait parameters
 * @fences: array of drm_amdgpu_fence
 */
static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
				    struct drm_file *filp,
				    union drm_amdgpu_wait_fences *wait,
				    struct drm_amdgpu_fence *fences)
{
	unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
	uint32_t fence_count = wait->in.fence_count;
	uint32_t first = ~0;
	struct dma_fence **array;
	unsigned int i;
	long r;

	/* Prepare the fence array */
	array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);

	if (array == NULL)
		return -ENOMEM;

	for (i = 0; i < fence_count; i++) {
		struct dma_fence *fence;

		fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
		if (IS_ERR(fence)) {
			r = PTR_ERR(fence);
			goto err_free_fence_array;
		} else if (fence) {
			array[i] = fence;
		} else { /* NULL, the fence has been already signaled */
			r = 1;
M
Monk Liu 已提交
1499
			first = i;
1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512
			goto out;
		}
	}

	r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
				       &first);
	if (r < 0)
		goto err_free_fence_array;

out:
	memset(wait, 0, sizeof(*wait));
	wait->out.status = (r > 0);
	wait->out.first_signaled = first;
1513

1514
	if (first < fence_count && array[first])
1515 1516 1517
		r = array[first]->error;
	else
		r = 0;
1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549

err_free_fence_array:
	for (i = 0; i < fence_count; i++)
		dma_fence_put(array[i]);
	kfree(array);

	return r;
}

/**
 * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
 *
 * @dev: drm device
 * @data: data from userspace
 * @filp: file private
 */
int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp)
{
	struct amdgpu_device *adev = dev->dev_private;
	union drm_amdgpu_wait_fences *wait = data;
	uint32_t fence_count = wait->in.fence_count;
	struct drm_amdgpu_fence *fences_user;
	struct drm_amdgpu_fence *fences;
	int r;

	/* Get the fences from userspace */
	fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
			GFP_KERNEL);
	if (fences == NULL)
		return -ENOMEM;

1550
	fences_user = u64_to_user_ptr(wait->in.fences);
1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567
	if (copy_from_user(fences, fences_user,
		sizeof(struct drm_amdgpu_fence) * fence_count)) {
		r = -EFAULT;
		goto err_free_fences;
	}

	if (wait->in.wait_all)
		r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
	else
		r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);

err_free_fences:
	kfree(fences);

	return r;
}

A
Alex Deucher 已提交
1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578
/**
 * amdgpu_cs_find_bo_va - find bo_va for VM address
 *
 * @parser: command submission parser context
 * @addr: VM address
 * @bo: resulting BO of the mapping found
 *
 * Search the buffer objects in the command submission context for a certain
 * virtual memory address. Returns allocation structure when found, NULL
 * otherwise.
 */
1579 1580 1581
int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
			   uint64_t addr, struct amdgpu_bo **bo,
			   struct amdgpu_bo_va_mapping **map)
A
Alex Deucher 已提交
1582
{
1583
	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1584
	struct ttm_operation_ctx ctx = { false, false };
1585
	struct amdgpu_vm *vm = &fpriv->vm;
A
Alex Deucher 已提交
1586
	struct amdgpu_bo_va_mapping *mapping;
1587 1588
	int r;

A
Alex Deucher 已提交
1589
	addr /= AMDGPU_GPU_PAGE_SIZE;
1590

1591 1592 1593
	mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
	if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
		return -EINVAL;
1594

1595 1596
	*bo = mapping->bo_va->base.bo;
	*map = mapping;
1597

1598 1599 1600
	/* Double check that the BO is reserved by this CS */
	if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
		return -EINVAL;
1601

1602 1603 1604
	if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
		(*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
		amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);
1605
		r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1606
		if (r)
1607
			return r;
1608 1609
	}

1610
	return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1611
}