amdgpu_cs.c 24.5 KB
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/*
 * Copyright 2008 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 */
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#include <linux/pagemap.h>
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#include <drm/drmP.h>
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "amdgpu_trace.h"

int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
		       u32 ip_instance, u32 ring,
		       struct amdgpu_ring **out_ring)
{
	/* Right now all IPs have only one instance - multiple rings. */
	if (ip_instance != 0) {
		DRM_ERROR("invalid ip instance: %d\n", ip_instance);
		return -EINVAL;
	}

	switch (ip_type) {
	default:
		DRM_ERROR("unknown ip type: %d\n", ip_type);
		return -EINVAL;
	case AMDGPU_HW_IP_GFX:
		if (ring < adev->gfx.num_gfx_rings) {
			*out_ring = &adev->gfx.gfx_ring[ring];
		} else {
			DRM_ERROR("only %d gfx rings are supported now\n",
				  adev->gfx.num_gfx_rings);
			return -EINVAL;
		}
		break;
	case AMDGPU_HW_IP_COMPUTE:
		if (ring < adev->gfx.num_compute_rings) {
			*out_ring = &adev->gfx.compute_ring[ring];
		} else {
			DRM_ERROR("only %d compute rings are supported now\n",
				  adev->gfx.num_compute_rings);
			return -EINVAL;
		}
		break;
	case AMDGPU_HW_IP_DMA:
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		if (ring < adev->sdma.num_instances) {
			*out_ring = &adev->sdma.instance[ring].ring;
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		} else {
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			DRM_ERROR("only %d SDMA rings are supported\n",
				  adev->sdma.num_instances);
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			return -EINVAL;
		}
		break;
	case AMDGPU_HW_IP_UVD:
		*out_ring = &adev->uvd.ring;
		break;
	case AMDGPU_HW_IP_VCE:
		if (ring < 2){
			*out_ring = &adev->vce.ring[ring];
		} else {
			DRM_ERROR("only two VCE rings are supported\n");
			return -EINVAL;
		}
		break;
	}
	return 0;
}

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static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
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				      struct amdgpu_user_fence *uf,
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				      struct drm_amdgpu_cs_chunk_fence *fence_data)
{
	struct drm_gem_object *gobj;
	uint32_t handle;

	handle = fence_data->handle;
	gobj = drm_gem_object_lookup(p->adev->ddev, p->filp,
				     fence_data->handle);
	if (gobj == NULL)
		return -EINVAL;

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	uf->bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
	uf->offset = fence_data->offset;
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	if (amdgpu_ttm_tt_get_usermm(uf->bo->tbo.ttm)) {
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		drm_gem_object_unreference_unlocked(gobj);
		return -EINVAL;
	}

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	p->uf_entry.robj = amdgpu_bo_ref(uf->bo);
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	p->uf_entry.priority = 0;
	p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
	p->uf_entry.tv.shared = true;
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	p->uf_entry.user_pages = NULL;
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	drm_gem_object_unreference_unlocked(gobj);
	return 0;
}

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int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
{
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	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
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	struct amdgpu_vm *vm = &fpriv->vm;
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	union drm_amdgpu_cs *cs = data;
	uint64_t *chunk_array_user;
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	uint64_t *chunk_array;
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	struct amdgpu_user_fence uf = {};
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	unsigned size, num_ibs = 0;
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	int i;
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	int ret;
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	if (cs->in.num_chunks == 0)
		return 0;

	chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
	if (!chunk_array)
		return -ENOMEM;
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	p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
	if (!p->ctx) {
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		ret = -EINVAL;
		goto free_chunk;
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	}
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	/* get chunks */
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	chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
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	if (copy_from_user(chunk_array, chunk_array_user,
			   sizeof(uint64_t)*cs->in.num_chunks)) {
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		ret = -EFAULT;
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		goto put_ctx;
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	}

	p->nchunks = cs->in.num_chunks;
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	p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
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			    GFP_KERNEL);
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	if (!p->chunks) {
		ret = -ENOMEM;
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		goto put_ctx;
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	}

	for (i = 0; i < p->nchunks; i++) {
		struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
		struct drm_amdgpu_cs_chunk user_chunk;
		uint32_t __user *cdata;

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		chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
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		if (copy_from_user(&user_chunk, chunk_ptr,
				       sizeof(struct drm_amdgpu_cs_chunk))) {
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			ret = -EFAULT;
			i--;
			goto free_partial_kdata;
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		}
		p->chunks[i].chunk_id = user_chunk.chunk_id;
		p->chunks[i].length_dw = user_chunk.length_dw;

		size = p->chunks[i].length_dw;
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		cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
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		p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
		if (p->chunks[i].kdata == NULL) {
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			ret = -ENOMEM;
			i--;
			goto free_partial_kdata;
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		}
		size *= sizeof(uint32_t);
		if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
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			ret = -EFAULT;
			goto free_partial_kdata;
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		}

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		switch (p->chunks[i].chunk_id) {
		case AMDGPU_CHUNK_ID_IB:
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			++num_ibs;
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			break;

		case AMDGPU_CHUNK_ID_FENCE:
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			size = sizeof(struct drm_amdgpu_cs_chunk_fence);
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			if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
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				ret = -EINVAL;
				goto free_partial_kdata;
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			}
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			ret = amdgpu_cs_user_fence_chunk(p, &uf, (void *)p->chunks[i].kdata);
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			if (ret)
				goto free_partial_kdata;

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			break;

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		case AMDGPU_CHUNK_ID_DEPENDENCIES:
			break;

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		default:
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			ret = -EINVAL;
			goto free_partial_kdata;
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		}
	}

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	ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
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	if (ret)
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		goto free_all_kdata;
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	p->job->uf = uf;

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	kfree(chunk_array);
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	return 0;

free_all_kdata:
	i = p->nchunks - 1;
free_partial_kdata:
	for (; i >= 0; i--)
		drm_free_large(p->chunks[i].kdata);
	kfree(p->chunks);
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put_ctx:
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	amdgpu_ctx_put(p->ctx);
free_chunk:
	kfree(chunk_array);

	return ret;
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}

/* Returns how many bytes TTM can move per IB.
 */
static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
{
	u64 real_vram_size = adev->mc.real_vram_size;
	u64 vram_usage = atomic64_read(&adev->vram_usage);

	/* This function is based on the current VRAM usage.
	 *
	 * - If all of VRAM is free, allow relocating the number of bytes that
	 *   is equal to 1/4 of the size of VRAM for this IB.

	 * - If more than one half of VRAM is occupied, only allow relocating
	 *   1 MB of data for this IB.
	 *
	 * - From 0 to one half of used VRAM, the threshold decreases
	 *   linearly.
	 *         __________________
	 * 1/4 of -|\               |
	 * VRAM    | \              |
	 *         |  \             |
	 *         |   \            |
	 *         |    \           |
	 *         |     \          |
	 *         |      \         |
	 *         |       \________|1 MB
	 *         |----------------|
	 *    VRAM 0 %             100 %
	 *         used            used
	 *
	 * Note: It's a threshold, not a limit. The threshold must be crossed
	 * for buffer relocations to stop, so any buffer of an arbitrary size
	 * can be moved as long as the threshold isn't crossed before
	 * the relocation takes place. We don't want to disable buffer
	 * relocations completely.
	 *
	 * The idea is that buffers should be placed in VRAM at creation time
	 * and TTM should only do a minimum number of relocations during
	 * command submission. In practice, you need to submit at least
	 * a dozen IBs to move all buffers to VRAM if they are in GTT.
	 *
	 * Also, things can get pretty crazy under memory pressure and actual
	 * VRAM usage can change a lot, so playing safe even at 50% does
	 * consistently increase performance.
	 */

	u64 half_vram = real_vram_size >> 1;
	u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
	u64 bytes_moved_threshold = half_free_vram >> 1;
	return max(bytes_moved_threshold, 1024*1024ull);
}

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int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
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			    struct list_head *validated)
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{
	struct amdgpu_bo_list_entry *lobj;
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	u64 initial_bytes_moved;
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	int r;

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	list_for_each_entry(lobj, validated, tv.head) {
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		struct amdgpu_bo *bo = lobj->robj;
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		bool binding_userptr = false;
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		struct mm_struct *usermm;
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		uint32_t domain;
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		usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
		if (usermm && usermm != current->mm)
			return -EPERM;

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		/* Check if we have user pages and nobody bound the BO already */
		if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
			size_t size = sizeof(struct page *);

			size *= bo->tbo.ttm->num_pages;
			memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
			binding_userptr = true;
		}

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		if (bo->pin_count)
			continue;

		/* Avoid moving this one if we have moved too many buffers
		 * for this IB already.
		 *
		 * Note that this allows moving at least one buffer of
		 * any size, because it doesn't take the current "bo"
		 * into account. We don't want to disallow buffer moves
		 * completely.
		 */
		if (p->bytes_moved <= p->bytes_moved_threshold)
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			domain = bo->prefered_domains;
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		else
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			domain = bo->allowed_domains;
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	retry:
		amdgpu_ttm_placement_from_domain(bo, domain);
		initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
		r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
		p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
			       initial_bytes_moved;

		if (unlikely(r)) {
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			if (r != -ERESTARTSYS && domain != bo->allowed_domains) {
				domain = bo->allowed_domains;
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				goto retry;
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			}
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			return r;
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		}
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		if (binding_userptr) {
			drm_free_large(lobj->user_pages);
			lobj->user_pages = NULL;
		}
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	}
	return 0;
}

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static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
				union drm_amdgpu_cs *cs)
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{
	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
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	struct amdgpu_bo_list_entry *e;
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	struct list_head duplicates;
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	bool need_mmap_lock = false;
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	unsigned i, tries = 10;
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	int r;
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	INIT_LIST_HEAD(&p->validated);

	p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
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	if (p->bo_list) {
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		need_mmap_lock = p->bo_list->first_userptr !=
			p->bo_list->num_entries;
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		amdgpu_bo_list_get_list(p->bo_list, &p->validated);
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	}
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	INIT_LIST_HEAD(&duplicates);
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	amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
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	if (p->job->uf.bo)
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		list_add(&p->uf_entry.tv.head, &p->validated);

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	if (need_mmap_lock)
		down_read(&current->mm->mmap_sem);

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	while (1) {
		struct list_head need_pages;
		unsigned i;

		r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
					   &duplicates);
		if (unlikely(r != 0))
			goto error_free_pages;

		/* Without a BO list we don't have userptr BOs */
		if (!p->bo_list)
			break;

		INIT_LIST_HEAD(&need_pages);
		for (i = p->bo_list->first_userptr;
		     i < p->bo_list->num_entries; ++i) {

			e = &p->bo_list->array[i];

			if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
				 &e->user_invalidated) && e->user_pages) {

				/* We acquired a page array, but somebody
				 * invalidated it. Free it an try again
				 */
				release_pages(e->user_pages,
					      e->robj->tbo.ttm->num_pages,
					      false);
				drm_free_large(e->user_pages);
				e->user_pages = NULL;
			}

			if (e->robj->tbo.ttm->state != tt_bound &&
			    !e->user_pages) {
				list_del(&e->tv.head);
				list_add(&e->tv.head, &need_pages);

				amdgpu_bo_unreserve(e->robj);
			}
		}

		if (list_empty(&need_pages))
			break;

		/* Unreserve everything again. */
		ttm_eu_backoff_reservation(&p->ticket, &p->validated);

		/* We tried to often, just abort */
		if (!--tries) {
			r = -EDEADLK;
			goto error_free_pages;
		}

		/* Fill the page arrays for all useptrs. */
		list_for_each_entry(e, &need_pages, tv.head) {
			struct ttm_tt *ttm = e->robj->tbo.ttm;

			e->user_pages = drm_calloc_large(ttm->num_pages,
							 sizeof(struct page*));
			if (!e->user_pages) {
				r = -ENOMEM;
				goto error_free_pages;
			}

			r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
			if (r) {
				drm_free_large(e->user_pages);
				e->user_pages = NULL;
				goto error_free_pages;
			}
		}

		/* And try again. */
		list_splice(&need_pages, &p->validated);
	}
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	amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
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	p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev);
	p->bytes_moved = 0;

	r = amdgpu_cs_list_validate(p, &duplicates);
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	if (r)
		goto error_validate;

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	r = amdgpu_cs_list_validate(p, &p->validated);
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	if (r)
		goto error_validate;

	if (p->bo_list) {
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		struct amdgpu_bo *gds = p->bo_list->gds_obj;
		struct amdgpu_bo *gws = p->bo_list->gws_obj;
		struct amdgpu_bo *oa = p->bo_list->oa_obj;
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		struct amdgpu_vm *vm = &fpriv->vm;
		unsigned i;

		for (i = 0; i < p->bo_list->num_entries; i++) {
			struct amdgpu_bo *bo = p->bo_list->array[i].robj;

			p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
		}
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		if (gds) {
			p->job->gds_base = amdgpu_bo_gpu_offset(gds);
			p->job->gds_size = amdgpu_bo_size(gds);
		}
		if (gws) {
			p->job->gws_base = amdgpu_bo_gpu_offset(gws);
			p->job->gws_size = amdgpu_bo_size(gws);
		}
		if (oa) {
			p->job->oa_base = amdgpu_bo_gpu_offset(oa);
			p->job->oa_size = amdgpu_bo_size(oa);
		}
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	}
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error_validate:
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	if (r) {
		amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm);
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		ttm_eu_backoff_reservation(&p->ticket, &p->validated);
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	}
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error_free_pages:

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	if (need_mmap_lock)
		up_read(&current->mm->mmap_sem);

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	if (p->bo_list) {
		for (i = p->bo_list->first_userptr;
		     i < p->bo_list->num_entries; ++i) {
			e = &p->bo_list->array[i];

			if (!e->user_pages)
				continue;

			release_pages(e->user_pages,
				      e->robj->tbo.ttm->num_pages,
				      false);
			drm_free_large(e->user_pages);
		}
	}

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	return r;
}

static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
{
	struct amdgpu_bo_list_entry *e;
	int r;

	list_for_each_entry(e, &p->validated, tv.head) {
		struct reservation_object *resv = e->robj->tbo.resv;
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		r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
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		if (r)
			return r;
	}
	return 0;
}

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/**
 * cs_parser_fini() - clean parser states
 * @parser:	parser structure holding parsing context.
 * @error:	error number
 *
 * If error is set than unvalidate buffer, otherwise just free memory
 * used by parsing context.
 **/
static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
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{
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	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
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	unsigned i;

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	if (!error) {
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		amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);

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		ttm_eu_fence_buffer_objects(&parser->ticket,
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					    &parser->validated,
					    parser->fence);
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	} else if (backoff) {
		ttm_eu_backoff_reservation(&parser->ticket,
					   &parser->validated);
	}
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	fence_put(parser->fence);
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	if (parser->ctx)
		amdgpu_ctx_put(parser->ctx);
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	if (parser->bo_list)
		amdgpu_bo_list_put(parser->bo_list);

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	for (i = 0; i < parser->nchunks; i++)
		drm_free_large(parser->chunks[i].kdata);
	kfree(parser->chunks);
579 580
	if (parser->job)
		amdgpu_job_free(parser->job);
581
	amdgpu_bo_unref(&parser->uf_entry.robj);
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}

static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
				   struct amdgpu_vm *vm)
{
	struct amdgpu_device *adev = p->adev;
	struct amdgpu_bo_va *bo_va;
	struct amdgpu_bo *bo;
	int i, r;

	r = amdgpu_vm_update_page_directory(adev, vm);
	if (r)
		return r;

596
	r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence);
597 598 599
	if (r)
		return r;

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	r = amdgpu_vm_clear_freed(adev, vm);
	if (r)
		return r;

	if (p->bo_list) {
		for (i = 0; i < p->bo_list->num_entries; i++) {
606 607
			struct fence *f;

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			/* ignore duplicates */
			bo = p->bo_list->array[i].robj;
			if (!bo)
				continue;

			bo_va = p->bo_list->array[i].bo_va;
			if (bo_va == NULL)
				continue;

			r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
			if (r)
				return r;

621
			f = bo_va->last_pt_update;
622
			r = amdgpu_sync_fence(adev, &p->job->sync, f);
623 624
			if (r)
				return r;
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Alex Deucher 已提交
625
		}
626 627 628

	}

629
	r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync);
630 631 632 633 634 635 636 637 638 639 640

	if (amdgpu_vm_debug && p->bo_list) {
		/* Invalidate all BOs to test for userspace bugs */
		for (i = 0; i < p->bo_list->num_entries; i++) {
			/* ignore duplicates */
			bo = p->bo_list->array[i].robj;
			if (!bo)
				continue;

			amdgpu_vm_bo_invalidate(adev, bo);
		}
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	}

643
	return r;
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}

static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
647
				 struct amdgpu_cs_parser *p)
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648
{
649
	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
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650
	struct amdgpu_vm *vm = &fpriv->vm;
651
	struct amdgpu_ring *ring = p->job->ring;
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	int i, r;

	/* Only for UVD/VCE VM emulation */
655 656 657
	if (ring->funcs->parse_cs) {
		for (i = 0; i < p->job->num_ibs; i++) {
			r = amdgpu_ring_parse_cs(ring, p, i);
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			if (r)
				return r;
		}
	}

663
	r = amdgpu_bo_vm_update_pte(p, vm);
664
	if (!r)
665
		amdgpu_cs_sync_rings(p);
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	return r;
}

static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
{
	if (r == -EDEADLK) {
		r = amdgpu_gpu_reset(adev);
		if (!r)
			r = -EAGAIN;
	}
	return r;
}

static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
			     struct amdgpu_cs_parser *parser)
{
	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
	struct amdgpu_vm *vm = &fpriv->vm;
	int i, j;
	int r;

688
	for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
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		struct amdgpu_cs_chunk *chunk;
		struct amdgpu_ib *ib;
		struct drm_amdgpu_cs_chunk_ib *chunk_ib;
		struct amdgpu_ring *ring;

		chunk = &parser->chunks[i];
695
		ib = &parser->job->ibs[j];
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		chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;

		if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
			continue;

		r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
				       chunk_ib->ip_instance, chunk_ib->ring,
				       &ring);
704
		if (r)
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			return r;

707 708 709 710 711
		if (parser->job->ring && parser->job->ring != ring)
			return -EINVAL;

		parser->job->ring = ring;

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712
		if (ring->funcs->parse_cs) {
713
			struct amdgpu_bo_va_mapping *m;
714
			struct amdgpu_bo *aobj = NULL;
715 716
			uint64_t offset;
			uint8_t *kptr;
717

718 719
			m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
						   &aobj);
720 721 722
			if (!aobj) {
				DRM_ERROR("IB va_start is invalid\n");
				return -EINVAL;
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Alex Deucher 已提交
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			}

725 726 727 728 729 730
			if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
			    (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
				DRM_ERROR("IB va_start+ib_bytes is invalid\n");
				return -EINVAL;
			}

731
			/* the IB should be reserved at this point */
732
			r = amdgpu_bo_kmap(aobj, (void **)&kptr);
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			if (r) {
				return r;
			}

737 738 739
			offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
			kptr += chunk_ib->va_start - offset;

740
			r =  amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib);
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			if (r) {
				DRM_ERROR("Failed to get ib !\n");
				return r;
			}

			memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
			amdgpu_bo_kunmap(aobj);
		} else {
749
			r =  amdgpu_ib_get(adev, vm, 0, ib);
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750 751 752 753 754 755 756 757
			if (r) {
				DRM_ERROR("Failed to get ib !\n");
				return r;
			}

			ib->gpu_addr = chunk_ib->va_start;
		}

758
		ib->length_dw = chunk_ib->ib_bytes / 4;
759
		ib->flags = chunk_ib->flags;
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Alex Deucher 已提交
760 761 762 763
		j++;
	}

	/* wrap the last IB with user fence */
764
	if (parser->job->uf.bo) {
765
		struct amdgpu_ib *ib = &parser->job->ibs[parser->job->num_ibs - 1];
A
Alex Deucher 已提交
766 767

		/* UVD & VCE fw doesn't support user fences */
768 769
		if (parser->job->ring->type == AMDGPU_RING_TYPE_UVD ||
		    parser->job->ring->type == AMDGPU_RING_TYPE_VCE)
A
Alex Deucher 已提交
770 771
			return -EINVAL;

772
		ib->user = &parser->job->uf;
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773 774 775 776 777
	}

	return 0;
}

778 779 780
static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
				  struct amdgpu_cs_parser *p)
{
781
	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799
	int i, j, r;

	for (i = 0; i < p->nchunks; ++i) {
		struct drm_amdgpu_cs_chunk_dep *deps;
		struct amdgpu_cs_chunk *chunk;
		unsigned num_deps;

		chunk = &p->chunks[i];

		if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
			continue;

		deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
		num_deps = chunk->length_dw * 4 /
			sizeof(struct drm_amdgpu_cs_chunk_dep);

		for (j = 0; j < num_deps; ++j) {
			struct amdgpu_ring *ring;
800
			struct amdgpu_ctx *ctx;
801
			struct fence *fence;
802 803 804 805 806 807 808

			r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
					       deps[j].ip_instance,
					       deps[j].ring, &ring);
			if (r)
				return r;

809 810 811 812
			ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
			if (ctx == NULL)
				return -EINVAL;

813 814 815 816
			fence = amdgpu_ctx_get_fence(ctx, ring,
						     deps[j].handle);
			if (IS_ERR(fence)) {
				r = PTR_ERR(fence);
817
				amdgpu_ctx_put(ctx);
818
				return r;
819

820
			} else if (fence) {
821 822
				r = amdgpu_sync_fence(adev, &p->job->sync,
						      fence);
823 824 825 826 827
				fence_put(fence);
				amdgpu_ctx_put(ctx);
				if (r)
					return r;
			}
828 829 830 831 832 833
		}
	}

	return 0;
}

834 835 836
static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
			    union drm_amdgpu_cs *cs)
{
837
	struct amdgpu_ring *ring = p->job->ring;
838
	struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
839
	struct fence *fence;
840
	struct amdgpu_job *job;
841
	int r;
842

843 844
	job = p->job;
	p->job = NULL;
845

846
	r = amd_sched_job_init(&job->base, &ring->sched,
847 848 849
			       entity, amdgpu_job_timeout_func,
			       amdgpu_job_free_func,
			       p->filp, &fence);
850
	if (r) {
851
		amdgpu_job_free(job);
852
		return r;
853 854
	}

855
	job->owner = p->filp;
856
	job->ctx = entity->fence_context;
857 858
	p->fence = fence_get(fence);
	cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, fence);
859 860 861 862 863 864 865 866
	job->ibs[job->num_ibs - 1].sequence = cs->out.handle;

	trace_amdgpu_cs_ioctl(job);
	amd_sched_entity_push_job(&job->base);

	return 0;
}

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Chunming Zhou 已提交
867 868 869 870
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	struct amdgpu_device *adev = dev->dev_private;
	union drm_amdgpu_cs *cs = data;
871
	struct amdgpu_cs_parser parser = {};
872 873
	bool reserved_buffers = false;
	int i, r;
C
Chunming Zhou 已提交
874

875
	if (!adev->accel_working)
C
Chunming Zhou 已提交
876
		return -EBUSY;
877

878 879 880 881
	parser.adev = adev;
	parser.filp = filp;

	r = amdgpu_cs_parser_init(&parser, data);
A
Alex Deucher 已提交
882
	if (r) {
C
Chunming Zhou 已提交
883
		DRM_ERROR("Failed to initialize parser !\n");
884
		amdgpu_cs_parser_fini(&parser, r, false);
A
Alex Deucher 已提交
885 886 887
		r = amdgpu_cs_handle_lockup(adev, r);
		return r;
	}
888
	r = amdgpu_cs_parser_bos(&parser, data);
889 890 891 892 893 894
	if (r == -ENOMEM)
		DRM_ERROR("Not enough memory for command submission!\n");
	else if (r && r != -ERESTARTSYS)
		DRM_ERROR("Failed to process the buffer list %d!\n", r);
	else if (!r) {
		reserved_buffers = true;
895
		r = amdgpu_cs_ib_fill(adev, &parser);
896 897 898
	}

	if (!r) {
899
		r = amdgpu_cs_dependencies(adev, &parser);
900 901 902 903 904 905 906
		if (r)
			DRM_ERROR("Failed in the dependencies handling %d!\n", r);
	}

	if (r)
		goto out;

907
	for (i = 0; i < parser.job->num_ibs; i++)
908
		trace_amdgpu_cs(&parser, i);
909

910
	r = amdgpu_cs_ib_vm_chunk(adev, &parser);
911 912 913
	if (r)
		goto out;

C
Christian König 已提交
914
	r = amdgpu_cs_submit(&parser, cs);
A
Alex Deucher 已提交
915 916

out:
917
	amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
A
Alex Deucher 已提交
918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936
	r = amdgpu_cs_handle_lockup(adev, r);
	return r;
}

/**
 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 *
 * @dev: drm device
 * @data: data from userspace
 * @filp: file private
 *
 * Wait for the command submission identified by handle to finish.
 */
int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *filp)
{
	union drm_amdgpu_wait_cs *wait = data;
	struct amdgpu_device *adev = dev->dev_private;
	unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
937
	struct amdgpu_ring *ring = NULL;
938
	struct amdgpu_ctx *ctx;
939
	struct fence *fence;
A
Alex Deucher 已提交
940 941
	long r;

942 943 944 945 946
	r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
			       wait->in.ring, &ring);
	if (r)
		return r;

947 948 949
	ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
	if (ctx == NULL)
		return -EINVAL;
A
Alex Deucher 已提交
950

951 952 953 954 955 956 957 958
	fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
	if (IS_ERR(fence))
		r = PTR_ERR(fence);
	else if (fence) {
		r = fence_wait_timeout(fence, true, timeout);
		fence_put(fence);
	} else
		r = 1;
C
Chunming Zhou 已提交
959

960
	amdgpu_ctx_put(ctx);
A
Alex Deucher 已提交
961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985
	if (r < 0)
		return r;

	memset(wait, 0, sizeof(*wait));
	wait->out.status = (r == 0);

	return 0;
}

/**
 * amdgpu_cs_find_bo_va - find bo_va for VM address
 *
 * @parser: command submission parser context
 * @addr: VM address
 * @bo: resulting BO of the mapping found
 *
 * Search the buffer objects in the command submission context for a certain
 * virtual memory address. Returns allocation structure when found, NULL
 * otherwise.
 */
struct amdgpu_bo_va_mapping *
amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
		       uint64_t addr, struct amdgpu_bo **bo)
{
	struct amdgpu_bo_va_mapping *mapping;
986 987 988 989
	unsigned i;

	if (!parser->bo_list)
		return NULL;
A
Alex Deucher 已提交
990 991 992

	addr /= AMDGPU_GPU_PAGE_SIZE;

993 994 995 996 997
	for (i = 0; i < parser->bo_list->num_entries; i++) {
		struct amdgpu_bo_list_entry *lobj;

		lobj = &parser->bo_list->array[i];
		if (!lobj->bo_va)
A
Alex Deucher 已提交
998 999
			continue;

1000
		list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
1001 1002 1003 1004
			if (mapping->it.start > addr ||
			    addr > mapping->it.last)
				continue;

1005
			*bo = lobj->bo_va->bo;
1006 1007 1008
			return mapping;
		}

1009
		list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
A
Alex Deucher 已提交
1010 1011 1012 1013
			if (mapping->it.start > addr ||
			    addr > mapping->it.last)
				continue;

1014
			*bo = lobj->bo_va->bo;
A
Alex Deucher 已提交
1015 1016 1017 1018 1019 1020
			return mapping;
		}
	}

	return NULL;
}