tg3.c 361.5 KB
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/*
 * tg3.c: Broadcom Tigon3 ethernet driver.
 *
 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
 * Copyright (C) 2004 Sun Microsystems Inc.
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 * Copyright (C) 2005-2009 Broadcom Corporation.
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 *
 * Firmware is:
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 *	Derived from proprietary unpublished source code,
 *	Copyright (C) 2000-2003 Broadcom Corporation.
 *
 *	Permission is hereby granted for the distribution of this firmware
 *	data in hexadecimal or equivalent format, provided this copyright
 *	notice is accompanying it.
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 */


#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/compiler.h>
#include <linux/slab.h>
#include <linux/delay.h>
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#include <linux/in.h>
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#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/brcmphy.h>
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#include <linux/if_vlan.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/workqueue.h>
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#include <linux/prefetch.h>
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#include <linux/dma-mapping.h>
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#include <linux/firmware.h>
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#include <net/checksum.h>
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#include <net/ip.h>
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#include <asm/system.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <asm/uaccess.h>

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#ifdef CONFIG_SPARC
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#include <asm/idprom.h>
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#include <asm/prom.h>
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#endif

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#define BAR_0	0
#define BAR_2	2

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#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
#define TG3_VLAN_TAG_USED 1
#else
#define TG3_VLAN_TAG_USED 0
#endif

#include "tg3.h"

#define DRV_MODULE_NAME		"tg3"
#define PFX DRV_MODULE_NAME	": "
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#define DRV_MODULE_VERSION	"3.98"
#define DRV_MODULE_RELDATE	"February 25, 2009"
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#define TG3_DEF_MAC_MODE	0
#define TG3_DEF_RX_MODE		0
#define TG3_DEF_TX_MODE		0
#define TG3_DEF_MSG_ENABLE	  \
	(NETIF_MSG_DRV		| \
	 NETIF_MSG_PROBE	| \
	 NETIF_MSG_LINK		| \
	 NETIF_MSG_TIMER	| \
	 NETIF_MSG_IFDOWN	| \
	 NETIF_MSG_IFUP		| \
	 NETIF_MSG_RX_ERR	| \
	 NETIF_MSG_TX_ERR)

/* length of time before we decide the hardware is borked,
 * and dev->tx_timeout() should be called to fix the problem
 */
#define TG3_TX_TIMEOUT			(5 * HZ)

/* hardware minimum and maximum for a single frame's data payload */
#define TG3_MIN_MTU			60
#define TG3_MAX_MTU(tp)	\
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	((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
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/* These numbers seem to be hard coded in the NIC firmware somehow.
 * You can't change the ring sizes, but you can change where you place
 * them in the NIC onboard memory.
 */
#define TG3_RX_RING_SIZE		512
#define TG3_DEF_RX_RING_PENDING		200
#define TG3_RX_JUMBO_RING_SIZE		256
#define TG3_DEF_RX_JUMBO_RING_PENDING	100

/* Do not place this n-ring entries value into the tp struct itself,
 * we really want to expose these constants to GCC so that modulo et
 * al.  operations are done with shifts and masks instead of with
 * hw multiply/modulo instructions.  Another solution would be to
 * replace things like '% foo' with '& (foo - 1)'.
 */
#define TG3_RX_RCB_RING_SIZE(tp)	\
	((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)

#define TG3_TX_RING_SIZE		512
#define TG3_DEF_TX_RING_PENDING		(TG3_TX_RING_SIZE - 1)

#define TG3_RX_RING_BYTES	(sizeof(struct tg3_rx_buffer_desc) * \
				 TG3_RX_RING_SIZE)
#define TG3_RX_JUMBO_RING_BYTES	(sizeof(struct tg3_rx_buffer_desc) * \
			         TG3_RX_JUMBO_RING_SIZE)
#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
			           TG3_RX_RCB_RING_SIZE(tp))
#define TG3_TX_RING_BYTES	(sizeof(struct tg3_tx_buffer_desc) * \
				 TG3_TX_RING_SIZE)
#define NEXT_TX(N)		(((N) + 1) & (TG3_TX_RING_SIZE - 1))

#define RX_PKT_BUF_SZ		(1536 + tp->rx_offset + 64)
#define RX_JUMBO_PKT_BUF_SZ	(9046 + tp->rx_offset + 64)

/* minimum number of free TX descriptors required to wake up TX process */
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#define TG3_TX_WAKEUP_THRESH(tp)		((tp)->tx_pending / 4)
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#define TG3_RAW_IP_ALIGN 2

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/* number of ETHTOOL_GSTATS u64's */
#define TG3_NUM_STATS		(sizeof(struct tg3_ethtool_stats)/sizeof(u64))

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#define TG3_NUM_TEST		6

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#define FIRMWARE_TG3		"tigon/tg3.bin"
#define FIRMWARE_TG3TSO		"tigon/tg3_tso.bin"
#define FIRMWARE_TG3TSO5	"tigon/tg3_tso5.bin"

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static char version[] __devinitdata =
	DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";

MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_MODULE_VERSION);
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MODULE_FIRMWARE(FIRMWARE_TG3);
MODULE_FIRMWARE(FIRMWARE_TG3TSO);
MODULE_FIRMWARE(FIRMWARE_TG3TSO5);

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static int tg3_debug = -1;	/* -1 == use TG3_DEF_MSG_ENABLE as value */
module_param(tg3_debug, int, 0);
MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");

static struct pci_device_id tg3_pci_tbl[] = {
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
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	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
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	{PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
	{PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
	{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
	{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
	{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
	{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
	{PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
	{}
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};

MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);

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static const struct {
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	const char string[ETH_GSTRING_LEN];
} ethtool_stats_keys[TG3_NUM_STATS] = {
	{ "rx_octets" },
	{ "rx_fragments" },
	{ "rx_ucast_packets" },
	{ "rx_mcast_packets" },
	{ "rx_bcast_packets" },
	{ "rx_fcs_errors" },
	{ "rx_align_errors" },
	{ "rx_xon_pause_rcvd" },
	{ "rx_xoff_pause_rcvd" },
	{ "rx_mac_ctrl_rcvd" },
	{ "rx_xoff_entered" },
	{ "rx_frame_too_long_errors" },
	{ "rx_jabbers" },
	{ "rx_undersize_packets" },
	{ "rx_in_length_errors" },
	{ "rx_out_length_errors" },
	{ "rx_64_or_less_octet_packets" },
	{ "rx_65_to_127_octet_packets" },
	{ "rx_128_to_255_octet_packets" },
	{ "rx_256_to_511_octet_packets" },
	{ "rx_512_to_1023_octet_packets" },
	{ "rx_1024_to_1522_octet_packets" },
	{ "rx_1523_to_2047_octet_packets" },
	{ "rx_2048_to_4095_octet_packets" },
	{ "rx_4096_to_8191_octet_packets" },
	{ "rx_8192_to_9022_octet_packets" },

	{ "tx_octets" },
	{ "tx_collisions" },

	{ "tx_xon_sent" },
	{ "tx_xoff_sent" },
	{ "tx_flow_control" },
	{ "tx_mac_errors" },
	{ "tx_single_collisions" },
	{ "tx_mult_collisions" },
	{ "tx_deferred" },
	{ "tx_excessive_collisions" },
	{ "tx_late_collisions" },
	{ "tx_collide_2times" },
	{ "tx_collide_3times" },
	{ "tx_collide_4times" },
	{ "tx_collide_5times" },
	{ "tx_collide_6times" },
	{ "tx_collide_7times" },
	{ "tx_collide_8times" },
	{ "tx_collide_9times" },
	{ "tx_collide_10times" },
	{ "tx_collide_11times" },
	{ "tx_collide_12times" },
	{ "tx_collide_13times" },
	{ "tx_collide_14times" },
	{ "tx_collide_15times" },
	{ "tx_ucast_packets" },
	{ "tx_mcast_packets" },
	{ "tx_bcast_packets" },
	{ "tx_carrier_sense_errors" },
	{ "tx_discards" },
	{ "tx_errors" },

	{ "dma_writeq_full" },
	{ "dma_write_prioq_full" },
	{ "rxbds_empty" },
	{ "rx_discards" },
	{ "rx_errors" },
	{ "rx_threshold_hit" },

	{ "dma_readq_full" },
	{ "dma_read_prioq_full" },
	{ "tx_comp_queue_full" },

	{ "ring_set_send_prod_index" },
	{ "ring_status_update" },
	{ "nic_irqs" },
	{ "nic_avoided_irqs" },
	{ "nic_tx_threshold_hit" }
};

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static const struct {
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	const char string[ETH_GSTRING_LEN];
} ethtool_test_keys[TG3_NUM_TEST] = {
	{ "nvram test     (online) " },
	{ "link test      (online) " },
	{ "register test  (offline)" },
	{ "memory test    (offline)" },
	{ "loopback test  (offline)" },
	{ "interrupt test (offline)" },
};

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static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
{
	writel(val, tp->regs + off);
}

static u32 tg3_read32(struct tg3 *tp, u32 off)
{
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	return (readl(tp->regs + off));
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}

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static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
{
	writel(val, tp->aperegs + off);
}

static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
{
	return (readl(tp->aperegs + off));
}

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static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
{
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	unsigned long flags;

	spin_lock_irqsave(&tp->indirect_lock, flags);
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	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
	pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
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	spin_unlock_irqrestore(&tp->indirect_lock, flags);
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}

static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
{
	writel(val, tp->regs + off);
	readl(tp->regs + off);
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}

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static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
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{
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	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&tp->indirect_lock, flags);
	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
	pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
	spin_unlock_irqrestore(&tp->indirect_lock, flags);
	return val;
}

static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
{
	unsigned long flags;

	if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
		pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
				       TG3_64BIT_REG_LOW, val);
		return;
	}
	if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
		pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
				       TG3_64BIT_REG_LOW, val);
		return;
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	}
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	spin_lock_irqsave(&tp->indirect_lock, flags);
	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
	pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
	spin_unlock_irqrestore(&tp->indirect_lock, flags);

	/* In indirect mode when disabling interrupts, we also need
	 * to clear the interrupt bit in the GRC local ctrl register.
	 */
	if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
	    (val == 0x1)) {
		pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
				       tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
	}
}

static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&tp->indirect_lock, flags);
	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
	pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
	spin_unlock_irqrestore(&tp->indirect_lock, flags);
	return val;
}

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/* usec_wait specifies the wait time in usec when writing to certain registers
 * where it is unsafe to read back the register without some delay.
 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 */
static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
427
{
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	if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
	    (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
		/* Non-posted methods */
		tp->write32(tp, off, val);
	else {
		/* Posted method */
		tg3_write32(tp, off, val);
		if (usec_wait)
			udelay(usec_wait);
		tp->read32(tp, off);
	}
	/* Wait again after the read for the posted method to guarantee that
	 * the wait time is met.
	 */
	if (usec_wait)
		udelay(usec_wait);
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}

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static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
{
	tp->write32_mbox(tp, off, val);
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	if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
	    !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
		tp->read32_mbox(tp, off);
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}

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static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
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{
	void __iomem *mbox = tp->regs + off;
	writel(val, mbox);
	if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
		writel(val, mbox);
	if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
		readl(mbox);
}

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static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
{
	return (readl(tp->regs + off + GRCMBOX_BASE));
}

static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
{
	writel(val, tp->regs + off + GRCMBOX_BASE);
}

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#define tw32_mailbox(reg, val)	tp->write32_mbox(tp, reg, val)
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#define tw32_mailbox_f(reg, val)	tw32_mailbox_flush(tp, (reg), (val))
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#define tw32_rx_mbox(reg, val)	tp->write32_rx_mbox(tp, reg, val)
#define tw32_tx_mbox(reg, val)	tp->write32_tx_mbox(tp, reg, val)
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#define tr32_mailbox(reg)	tp->read32_mbox(tp, reg)
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#define tw32(reg,val)		tp->write32(tp, reg, val)
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#define tw32_f(reg,val)		_tw32_flush(tp,(reg),(val), 0)
#define tw32_wait_f(reg,val,us)	_tw32_flush(tp,(reg),(val), (us))
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#define tr32(reg)		tp->read32(tp, reg)
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static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
{
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	unsigned long flags;

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	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
	    (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
		return;

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	spin_lock_irqsave(&tp->indirect_lock, flags);
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	if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
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		/* Always leave this as zero. */
		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
	} else {
		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
		tw32_f(TG3PCI_MEM_WIN_DATA, val);
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		/* Always leave this as zero. */
		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
	}
	spin_unlock_irqrestore(&tp->indirect_lock, flags);
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}

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static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
{
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	unsigned long flags;

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	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
	    (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
		*val = 0;
		return;
	}

520
	spin_lock_irqsave(&tp->indirect_lock, flags);
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	if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
		pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
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		/* Always leave this as zero. */
		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
	} else {
		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
		*val = tr32(TG3PCI_MEM_WIN_DATA);

		/* Always leave this as zero. */
		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
	}
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	spin_unlock_irqrestore(&tp->indirect_lock, flags);
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}

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static void tg3_ape_lock_init(struct tg3 *tp)
{
	int i;

	/* Make sure the driver hasn't any stale locks. */
	for (i = 0; i < 8; i++)
		tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
				APE_LOCK_GRANT_DRIVER);
}

static int tg3_ape_lock(struct tg3 *tp, int locknum)
{
	int i, off;
	int ret = 0;
	u32 status;

	if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
		return 0;

	switch (locknum) {
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		case TG3_APE_LOCK_GRC:
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		case TG3_APE_LOCK_MEM:
			break;
		default:
			return -EINVAL;
	}

	off = 4 * locknum;

	tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);

	/* Wait for up to 1 millisecond to acquire lock. */
	for (i = 0; i < 100; i++) {
		status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
		if (status == APE_LOCK_GRANT_DRIVER)
			break;
		udelay(10);
	}

	if (status != APE_LOCK_GRANT_DRIVER) {
		/* Revoke the lock request. */
		tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
				APE_LOCK_GRANT_DRIVER);

		ret = -EBUSY;
	}

	return ret;
}

static void tg3_ape_unlock(struct tg3 *tp, int locknum)
{
	int off;

	if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
		return;

	switch (locknum) {
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		case TG3_APE_LOCK_GRC:
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		case TG3_APE_LOCK_MEM:
			break;
		default:
			return;
	}

	off = 4 * locknum;
	tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
}

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static void tg3_disable_ints(struct tg3 *tp)
{
	tw32(TG3PCI_MISC_HOST_CTRL,
	     (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
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	tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
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}

static inline void tg3_cond_int(struct tg3 *tp)
{
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	if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
	    (tp->hw_status->status & SD_STATUS_UPDATED))
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		tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
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	else
		tw32(HOSTCC_MODE, tp->coalesce_mode |
		     (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
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}

static void tg3_enable_ints(struct tg3 *tp)
{
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	tp->irq_sync = 0;
	wmb();

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	tw32(TG3PCI_MISC_HOST_CTRL,
	     (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
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	tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
		       (tp->last_tag << 24));
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	if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
		tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
			       (tp->last_tag << 24));
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	tg3_cond_int(tp);
}

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static inline unsigned int tg3_has_work(struct tg3 *tp)
{
	struct tg3_hw_status *sblk = tp->hw_status;
	unsigned int work_exists = 0;

	/* check for phy events */
	if (!(tp->tg3_flags &
	      (TG3_FLAG_USE_LINKCHG_REG |
	       TG3_FLAG_POLL_SERDES))) {
		if (sblk->status & SD_STATUS_LINK_CHG)
			work_exists = 1;
	}
	/* check for RX/TX work to do */
	if (sblk->idx[0].tx_consumer != tp->tx_cons ||
	    sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
		work_exists = 1;

	return work_exists;
}

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/* tg3_restart_ints
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 *  similar to tg3_enable_ints, but it accurately determines whether there
 *  is new work pending and can return without flushing the PIO write
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 *  which reenables interrupts
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 */
static void tg3_restart_ints(struct tg3 *tp)
{
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	tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
		     tp->last_tag << 24);
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	mmiowb();

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	/* When doing tagged status, this work check is unnecessary.
	 * The last_tag we write above tells the chip which piece of
	 * work we've completed.
	 */
	if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
	    tg3_has_work(tp))
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		tw32(HOSTCC_MODE, tp->coalesce_mode |
		     (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
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}

static inline void tg3_netif_stop(struct tg3 *tp)
{
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	tp->dev->trans_start = jiffies;	/* prevent tx timeout */
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	napi_disable(&tp->napi);
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	netif_tx_disable(tp->dev);
}

static inline void tg3_netif_start(struct tg3 *tp)
{
	netif_wake_queue(tp->dev);
	/* NOTE: unconditional netif_wake_queue is only appropriate
	 * so long as all callers are assured to have free tx slots
	 * (such as after tg3_init_hw)
	 */
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	napi_enable(&tp->napi);
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	tp->hw_status->status |= SD_STATUS_UPDATED;
	tg3_enable_ints(tp);
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}

static void tg3_switch_clocks(struct tg3 *tp)
{
	u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
	u32 orig_clock_ctrl;

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	if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
	    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
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		return;

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	orig_clock_ctrl = clock_ctrl;
	clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
		       CLOCK_CTRL_CLKRUN_OENABLE |
		       0x1f);
	tp->pci_clock_ctrl = clock_ctrl;

	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
		if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
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			tw32_wait_f(TG3PCI_CLOCK_CTRL,
				    clock_ctrl | CLOCK_CTRL_625_CORE, 40);
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		}
	} else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
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		tw32_wait_f(TG3PCI_CLOCK_CTRL,
			    clock_ctrl |
			    (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
			    40);
		tw32_wait_f(TG3PCI_CLOCK_CTRL,
			    clock_ctrl | (CLOCK_CTRL_ALTCLK),
			    40);
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	}
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	tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
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}

#define PHY_BUSY_LOOPS	5000

static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
{
	u32 frame_val;
	unsigned int loops;
	int ret;

	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
		tw32_f(MAC_MI_MODE,
		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
		udelay(80);
	}

	*val = 0x0;

	frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
		      MI_COM_PHY_ADDR_MASK);
	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
		      MI_COM_REG_ADDR_MASK);
	frame_val |= (MI_COM_CMD_READ | MI_COM_START);
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	tw32_f(MAC_MI_COM, frame_val);

	loops = PHY_BUSY_LOOPS;
	while (loops != 0) {
		udelay(10);
		frame_val = tr32(MAC_MI_COM);

		if ((frame_val & MI_COM_BUSY) == 0) {
			udelay(5);
			frame_val = tr32(MAC_MI_COM);
			break;
		}
		loops -= 1;
	}

	ret = -EBUSY;
	if (loops != 0) {
		*val = frame_val & MI_COM_DATA_MASK;
		ret = 0;
	}

	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
		tw32_f(MAC_MI_MODE, tp->mi_mode);
		udelay(80);
	}

	return ret;
}

static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
{
	u32 frame_val;
	unsigned int loops;
	int ret;

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	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
	    (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
		return 0;

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	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
		tw32_f(MAC_MI_MODE,
		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
		udelay(80);
	}

	frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
		      MI_COM_PHY_ADDR_MASK);
	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
		      MI_COM_REG_ADDR_MASK);
	frame_val |= (val & MI_COM_DATA_MASK);
	frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
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	tw32_f(MAC_MI_COM, frame_val);

	loops = PHY_BUSY_LOOPS;
	while (loops != 0) {
		udelay(10);
		frame_val = tr32(MAC_MI_COM);
		if ((frame_val & MI_COM_BUSY) == 0) {
			udelay(5);
			frame_val = tr32(MAC_MI_COM);
			break;
		}
		loops -= 1;
	}

	ret = -EBUSY;
	if (loops != 0)
		ret = 0;

	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
		tw32_f(MAC_MI_MODE, tp->mi_mode);
		udelay(80);
	}

	return ret;
}

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static int tg3_bmcr_reset(struct tg3 *tp)
{
	u32 phy_control;
	int limit, err;

	/* OK, reset it, and poll the BMCR_RESET bit until it
	 * clears or we time out.
	 */
	phy_control = BMCR_RESET;
	err = tg3_writephy(tp, MII_BMCR, phy_control);
	if (err != 0)
		return -EBUSY;

	limit = 5000;
	while (limit--) {
		err = tg3_readphy(tp, MII_BMCR, &phy_control);
		if (err != 0)
			return -EBUSY;

		if ((phy_control & BMCR_RESET) == 0) {
			udelay(40);
			break;
		}
		udelay(10);
	}
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	if (limit < 0)
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		return -EBUSY;

	return 0;
}

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static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
{
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	struct tg3 *tp = bp->priv;
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	u32 val;

	if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
		return -EAGAIN;

	if (tg3_readphy(tp, reg, &val))
		return -EIO;

	return val;
}

static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
{
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	struct tg3 *tp = bp->priv;
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	if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
		return -EAGAIN;

	if (tg3_writephy(tp, reg, val))
		return -EIO;

	return 0;
}

static int tg3_mdio_reset(struct mii_bus *bp)
{
	return 0;
}

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static void tg3_mdio_config_5785(struct tg3 *tp)
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{
	u32 val;
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	struct phy_device *phydev;
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	phydev = tp->mdio_bus->phy_map[PHY_ADDR];
	switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
	case TG3_PHY_ID_BCM50610:
		val = MAC_PHYCFG2_50610_LED_MODES;
		break;
	case TG3_PHY_ID_BCMAC131:
		val = MAC_PHYCFG2_AC131_LED_MODES;
		break;
	case TG3_PHY_ID_RTL8211C:
		val = MAC_PHYCFG2_RTL8211C_LED_MODES;
		break;
	case TG3_PHY_ID_RTL8201E:
		val = MAC_PHYCFG2_RTL8201E_LED_MODES;
		break;
	default:
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		return;
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	}

	if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
		tw32(MAC_PHYCFG2, val);

		val = tr32(MAC_PHYCFG1);
		val &= ~MAC_PHYCFG1_RGMII_INT;
		tw32(MAC_PHYCFG1, val);

		return;
	}

	if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
		val |= MAC_PHYCFG2_EMODE_MASK_MASK |
		       MAC_PHYCFG2_FMODE_MASK_MASK |
		       MAC_PHYCFG2_GMODE_MASK_MASK |
		       MAC_PHYCFG2_ACT_MASK_MASK   |
		       MAC_PHYCFG2_QUAL_MASK_MASK |
		       MAC_PHYCFG2_INBAND_ENABLE;

	tw32(MAC_PHYCFG2, val);
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	val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
				    MAC_PHYCFG1_RGMII_SND_STAT_EN);
	if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
		if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
			val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
		if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
			val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
	}
	tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);

	val = tr32(MAC_EXT_RGMII_MODE);
	val &= ~(MAC_RGMII_MODE_RX_INT_B |
		 MAC_RGMII_MODE_RX_QUALITY |
		 MAC_RGMII_MODE_RX_ACTIVITY |
		 MAC_RGMII_MODE_RX_ENG_DET |
		 MAC_RGMII_MODE_TX_ENABLE |
		 MAC_RGMII_MODE_TX_LOWPWR |
		 MAC_RGMII_MODE_TX_RESET);
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	if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
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		if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
			val |= MAC_RGMII_MODE_RX_INT_B |
			       MAC_RGMII_MODE_RX_QUALITY |
			       MAC_RGMII_MODE_RX_ACTIVITY |
			       MAC_RGMII_MODE_RX_ENG_DET;
		if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
			val |= MAC_RGMII_MODE_TX_ENABLE |
			       MAC_RGMII_MODE_TX_LOWPWR |
			       MAC_RGMII_MODE_TX_RESET;
	}
	tw32(MAC_EXT_RGMII_MODE, val);
}

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static void tg3_mdio_start(struct tg3 *tp)
{
	if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
971
		mutex_lock(&tp->mdio_bus->mdio_lock);
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		tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
973
		mutex_unlock(&tp->mdio_bus->mdio_lock);
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	}

	tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
	tw32_f(MAC_MI_MODE, tp->mi_mode);
	udelay(80);
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	if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
		tg3_mdio_config_5785(tp);
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}

static void tg3_mdio_stop(struct tg3 *tp)
{
	if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
988
		mutex_lock(&tp->mdio_bus->mdio_lock);
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		tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
990
		mutex_unlock(&tp->mdio_bus->mdio_lock);
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	}
}

static int tg3_mdio_init(struct tg3 *tp)
{
	int i;
	u32 reg;
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	struct phy_device *phydev;
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	tg3_mdio_start(tp);

	if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
	    (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
		return 0;

1006 1007 1008
	tp->mdio_bus = mdiobus_alloc();
	if (tp->mdio_bus == NULL)
		return -ENOMEM;
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1010 1011
	tp->mdio_bus->name     = "tg3 mdio bus";
	snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
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		 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1013 1014 1015 1016 1017 1018 1019
	tp->mdio_bus->priv     = tp;
	tp->mdio_bus->parent   = &tp->pdev->dev;
	tp->mdio_bus->read     = &tg3_mdio_read;
	tp->mdio_bus->write    = &tg3_mdio_write;
	tp->mdio_bus->reset    = &tg3_mdio_reset;
	tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
	tp->mdio_bus->irq      = &tp->mdio_irq[0];
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	for (i = 0; i < PHY_MAX_ADDR; i++)
1022
		tp->mdio_bus->irq[i] = PHY_POLL;
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	/* The bus registration will look for all the PHYs on the mdio bus.
	 * Unfortunately, it does not ensure the PHY is powered up before
	 * accessing the PHY ID registers.  A chip reset is the
	 * quickest way to bring the device back to an operational state..
	 */
	if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
		tg3_bmcr_reset(tp);

1032
	i = mdiobus_register(tp->mdio_bus);
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	if (i) {
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		printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
			tp->dev->name, i);
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		mdiobus_free(tp->mdio_bus);
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		return i;
	}
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1040
	phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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	if (!phydev || !phydev->drv) {
		printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
		mdiobus_unregister(tp->mdio_bus);
		mdiobus_free(tp->mdio_bus);
		return -ENODEV;
	}

	switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
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	case TG3_PHY_ID_BCM57780:
		phydev->interface = PHY_INTERFACE_MODE_GMII;
		break;
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	case TG3_PHY_ID_BCM50610:
		if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
			phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
		if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
			phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
		if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
			phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
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		/* fallthru */
	case TG3_PHY_ID_RTL8211C:
		phydev->interface = PHY_INTERFACE_MODE_RGMII;
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		break;
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	case TG3_PHY_ID_RTL8201E:
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	case TG3_PHY_ID_BCMAC131:
		phydev->interface = PHY_INTERFACE_MODE_MII;
		break;
	}

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	tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
		tg3_mdio_config_5785(tp);
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	return 0;
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}

static void tg3_mdio_fini(struct tg3 *tp)
{
	if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
		tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1082 1083
		mdiobus_unregister(tp->mdio_bus);
		mdiobus_free(tp->mdio_bus);
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		tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
	}
}

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/* tp->lock is held. */
static inline void tg3_generate_fw_event(struct tg3 *tp)
{
	u32 val;

	val = tr32(GRC_RX_CPU_EVENT);
	val |= GRC_RX_CPU_DRIVER_EVENT;
	tw32_f(GRC_RX_CPU_EVENT, val);

	tp->last_event_jiffies = jiffies;
}

#define TG3_FW_EVENT_TIMEOUT_USEC 2500

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/* tp->lock is held. */
static void tg3_wait_for_event_ack(struct tg3 *tp)
{
	int i;
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	unsigned int delay_cnt;
	long time_remain;

	/* If enough time has passed, no wait is necessary. */
	time_remain = (long)(tp->last_event_jiffies + 1 +
		      usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
		      (long)jiffies;
	if (time_remain < 0)
		return;

	/* Check if we can shorten the wait time. */
	delay_cnt = jiffies_to_usecs(time_remain);
	if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
		delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
	delay_cnt = (delay_cnt >> 3) + 1;
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	for (i = 0; i < delay_cnt; i++) {
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		if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
			break;
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		udelay(8);
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	}
}

/* tp->lock is held. */
static void tg3_ump_link_report(struct tg3 *tp)
{
	u32 reg;
	u32 val;

	if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
	    !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
		return;

	tg3_wait_for_event_ack(tp);

	tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);

	tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);

	val = 0;
	if (!tg3_readphy(tp, MII_BMCR, &reg))
		val = reg << 16;
	if (!tg3_readphy(tp, MII_BMSR, &reg))
		val |= (reg & 0xffff);
	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);

	val = 0;
	if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
		val = reg << 16;
	if (!tg3_readphy(tp, MII_LPA, &reg))
		val |= (reg & 0xffff);
	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);

	val = 0;
	if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
		if (!tg3_readphy(tp, MII_CTRL1000, &reg))
			val = reg << 16;
		if (!tg3_readphy(tp, MII_STAT1000, &reg))
			val |= (reg & 0xffff);
	}
	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);

	if (!tg3_readphy(tp, MII_PHYADDR, &reg))
		val = reg << 16;
	else
		val = 0;
	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);

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	tg3_generate_fw_event(tp);
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}

static void tg3_link_report(struct tg3 *tp)
{
	if (!netif_carrier_ok(tp->dev)) {
		if (netif_msg_link(tp))
			printk(KERN_INFO PFX "%s: Link is down.\n",
			       tp->dev->name);
		tg3_ump_link_report(tp);
	} else if (netif_msg_link(tp)) {
		printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
		       tp->dev->name,
		       (tp->link_config.active_speed == SPEED_1000 ?
			1000 :
			(tp->link_config.active_speed == SPEED_100 ?
			 100 : 10)),
		       (tp->link_config.active_duplex == DUPLEX_FULL ?
			"full" : "half"));

		printk(KERN_INFO PFX
		       "%s: Flow control is %s for TX and %s for RX.\n",
		       tp->dev->name,
1197
		       (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
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		       "on" : "off",
1199
		       (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
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		       "on" : "off");
		tg3_ump_link_report(tp);
	}
}

static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
{
	u16 miireg;

1209
	if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
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		miireg = ADVERTISE_PAUSE_CAP;
1211
	else if (flow_ctrl & FLOW_CTRL_TX)
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		miireg = ADVERTISE_PAUSE_ASYM;
1213
	else if (flow_ctrl & FLOW_CTRL_RX)
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		miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
	else
		miireg = 0;

	return miireg;
}

static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
{
	u16 miireg;

1225
	if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
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		miireg = ADVERTISE_1000XPAUSE;
1227
	else if (flow_ctrl & FLOW_CTRL_TX)
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		miireg = ADVERTISE_1000XPSE_ASYM;
1229
	else if (flow_ctrl & FLOW_CTRL_RX)
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		miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
	else
		miireg = 0;

	return miireg;
}

static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
{
	u8 cap = 0;

	if (lcladv & ADVERTISE_1000XPAUSE) {
		if (lcladv & ADVERTISE_1000XPSE_ASYM) {
			if (rmtadv & LPA_1000XPAUSE)
1244
				cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
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			else if (rmtadv & LPA_1000XPAUSE_ASYM)
1246
				cap = FLOW_CTRL_RX;
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		} else {
			if (rmtadv & LPA_1000XPAUSE)
1249
				cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
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		}
	} else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
		if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1253
			cap = FLOW_CTRL_TX;
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	}

	return cap;
}

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static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
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{
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	u8 autoneg;
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	u8 flowctrl = 0;
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	u32 old_rx_mode = tp->rx_mode;
	u32 old_tx_mode = tp->tx_mode;

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	if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1267
		autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
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	else
		autoneg = tp->link_config.autoneg;

	if (autoneg == AUTONEG_ENABLE &&
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	    (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
		if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
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			flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
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		else
1276
			flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
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	} else
		flowctrl = tp->link_config.flowctrl;
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	tp->link_config.active_flowctrl = flowctrl;
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1282
	if (flowctrl & FLOW_CTRL_RX)
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		tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
	else
		tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;

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	if (old_rx_mode != tp->rx_mode)
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		tw32_f(MAC_RX_MODE, tp->rx_mode);

1290
	if (flowctrl & FLOW_CTRL_TX)
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		tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
	else
		tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;

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	if (old_tx_mode != tp->tx_mode)
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		tw32_f(MAC_TX_MODE, tp->tx_mode);
}

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static void tg3_adjust_link(struct net_device *dev)
{
	u8 oldflowctrl, linkmesg = 0;
	u32 mac_mode, lcl_adv, rmt_adv;
	struct tg3 *tp = netdev_priv(dev);
1304
	struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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	spin_lock(&tp->lock);

	mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
				    MAC_MODE_HALF_DUPLEX);

	oldflowctrl = tp->link_config.active_flowctrl;

	if (phydev->link) {
		lcl_adv = 0;
		rmt_adv = 0;

		if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
			mac_mode |= MAC_MODE_PORT_MODE_MII;
		else
			mac_mode |= MAC_MODE_PORT_MODE_GMII;

		if (phydev->duplex == DUPLEX_HALF)
			mac_mode |= MAC_MODE_HALF_DUPLEX;
		else {
			lcl_adv = tg3_advert_flowctrl_1000T(
				  tp->link_config.flowctrl);

			if (phydev->pause)
				rmt_adv = LPA_PAUSE_CAP;
			if (phydev->asym_pause)
				rmt_adv |= LPA_PAUSE_ASYM;
		}

		tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
	} else
		mac_mode |= MAC_MODE_PORT_MODE_GMII;

	if (mac_mode != tp->mac_mode) {
		tp->mac_mode = mac_mode;
		tw32_f(MAC_MODE, tp->mac_mode);
		udelay(40);
	}

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	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
		if (phydev->speed == SPEED_10)
			tw32(MAC_MI_STAT,
			     MAC_MI_STAT_10MBPS_MODE |
			     MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
		else
			tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
	}

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	if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
		tw32(MAC_TX_LENGTHS,
		     ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
		      (6 << TX_LENGTHS_IPG_SHIFT) |
		      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
	else
		tw32(MAC_TX_LENGTHS,
		     ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
		      (6 << TX_LENGTHS_IPG_SHIFT) |
		      (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));

	if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
	    (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
	    phydev->speed != tp->link_config.active_speed ||
	    phydev->duplex != tp->link_config.active_duplex ||
	    oldflowctrl != tp->link_config.active_flowctrl)
	    linkmesg = 1;

	tp->link_config.active_speed = phydev->speed;
	tp->link_config.active_duplex = phydev->duplex;

	spin_unlock(&tp->lock);

	if (linkmesg)
		tg3_link_report(tp);
}

static int tg3_phy_init(struct tg3 *tp)
{
	struct phy_device *phydev;

	if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
		return 0;

	/* Bring the PHY back to a known state. */
	tg3_bmcr_reset(tp);

1390
	phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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	/* Attach the MAC to the PHY. */
1393
	phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
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			     phydev->dev_flags, phydev->interface);
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	if (IS_ERR(phydev)) {
		printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
		return PTR_ERR(phydev);
	}

	/* Mask with MAC supported features. */
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	switch (phydev->interface) {
	case PHY_INTERFACE_MODE_GMII:
	case PHY_INTERFACE_MODE_RGMII:
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		if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
			phydev->supported &= (PHY_GBIT_FEATURES |
					      SUPPORTED_Pause |
					      SUPPORTED_Asym_Pause);
			break;
		}
		/* fallthru */
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	case PHY_INTERFACE_MODE_MII:
		phydev->supported &= (PHY_BASIC_FEATURES |
				      SUPPORTED_Pause |
				      SUPPORTED_Asym_Pause);
		break;
	default:
		phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
		return -EINVAL;
	}

	tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
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	phydev->advertising = phydev->supported;

	return 0;
}

static void tg3_phy_start(struct tg3 *tp)
{
	struct phy_device *phydev;

	if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
		return;

1435
	phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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	if (tp->link_config.phy_is_low_power) {
		tp->link_config.phy_is_low_power = 0;
		phydev->speed = tp->link_config.orig_speed;
		phydev->duplex = tp->link_config.orig_duplex;
		phydev->autoneg = tp->link_config.orig_autoneg;
		phydev->advertising = tp->link_config.orig_advertising;
	}

	phy_start(phydev);

	phy_start_aneg(phydev);
}

static void tg3_phy_stop(struct tg3 *tp)
{
	if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
		return;

1455
	phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
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}

static void tg3_phy_fini(struct tg3 *tp)
{
	if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1461
		phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
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		tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
	}
}

1466 1467 1468 1469 1470 1471
static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
{
	tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
	tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
}

1472 1473 1474 1475
static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
{
	u32 reg;

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	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500
		return;

	reg = MII_TG3_MISC_SHDW_WREN |
	      MII_TG3_MISC_SHDW_SCR5_SEL |
	      MII_TG3_MISC_SHDW_SCR5_LPED |
	      MII_TG3_MISC_SHDW_SCR5_DLPTLM |
	      MII_TG3_MISC_SHDW_SCR5_SDTL |
	      MII_TG3_MISC_SHDW_SCR5_C125OE;
	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
		reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;

	tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);


	reg = MII_TG3_MISC_SHDW_WREN |
	      MII_TG3_MISC_SHDW_APD_SEL |
	      MII_TG3_MISC_SHDW_APD_WKTM_84MS;
	if (enable)
		reg |= MII_TG3_MISC_SHDW_APD_ENABLE;

	tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
}

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static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
{
	u32 phy;

	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
	    (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
		return;

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
		u32 ephy;

		if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
			tg3_writephy(tp, MII_TG3_EPHY_TEST,
				     ephy | MII_TG3_EPHY_SHADOW_EN);
			if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
				if (enable)
					phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
				else
					phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
				tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
			}
			tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
		}
	} else {
		phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
		      MII_TG3_AUXCTL_SHDWSEL_MISC;
		if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
		    !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
			if (enable)
				phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
			else
				phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
			phy |= MII_TG3_AUXCTL_MISC_WREN;
			tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
		}
	}
}

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static void tg3_phy_set_wirespeed(struct tg3 *tp)
{
	u32 val;

	if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
		return;

	if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
	    !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
		tg3_writephy(tp, MII_TG3_AUX_CTRL,
			     (val | (1 << 15) | (1 << 4)));
}

1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594
static void tg3_phy_apply_otp(struct tg3 *tp)
{
	u32 otp, phy;

	if (!tp->phy_otp)
		return;

	otp = tp->phy_otp;

	/* Enable SM_DSP clock and tx 6dB coding. */
	phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
	      MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
	      MII_TG3_AUXCTL_ACTL_TX_6DB;
	tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);

	phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
	phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
	tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);

	phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
	      ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
	tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);

	phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
	phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
	tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);

	phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
	tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);

	phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
	tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);

	phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
	      ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
	tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);

	/* Turn off SM_DSP clock. */
	phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
	      MII_TG3_AUXCTL_ACTL_TX_6DB;
	tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
}

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static int tg3_wait_macro_done(struct tg3 *tp)
{
	int limit = 100;

	while (limit--) {
		u32 tmp32;

		if (!tg3_readphy(tp, 0x16, &tmp32)) {
			if ((tmp32 & 0x1000) == 0)
				break;
		}
	}
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Roel Kluin 已提交
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	if (limit < 0)
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		return -EBUSY;

	return 0;
}

static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
{
	static const u32 test_pat[4][6] = {
	{ 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
	{ 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
	{ 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
	{ 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
	};
	int chan;

	for (chan = 0; chan < 4; chan++) {
		int i;

		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
			     (chan * 0x2000) | 0x0200);
		tg3_writephy(tp, 0x16, 0x0002);

		for (i = 0; i < 6; i++)
			tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
				     test_pat[chan][i]);

		tg3_writephy(tp, 0x16, 0x0202);
		if (tg3_wait_macro_done(tp)) {
			*resetp = 1;
			return -EBUSY;
		}

		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
			     (chan * 0x2000) | 0x0200);
		tg3_writephy(tp, 0x16, 0x0082);
		if (tg3_wait_macro_done(tp)) {
			*resetp = 1;
			return -EBUSY;
		}

		tg3_writephy(tp, 0x16, 0x0802);
		if (tg3_wait_macro_done(tp)) {
			*resetp = 1;
			return -EBUSY;
		}

		for (i = 0; i < 6; i += 2) {
			u32 low, high;

			if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
			    tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
			    tg3_wait_macro_done(tp)) {
				*resetp = 1;
				return -EBUSY;
			}
			low &= 0x7fff;
			high &= 0x000f;
			if (low != test_pat[chan][i] ||
			    high != test_pat[chan][i+1]) {
				tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);

				return -EBUSY;
			}
		}
	}

	return 0;
}

static int tg3_phy_reset_chanpat(struct tg3 *tp)
{
	int chan;

	for (chan = 0; chan < 4; chan++) {
		int i;

		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
			     (chan * 0x2000) | 0x0200);
		tg3_writephy(tp, 0x16, 0x0002);
		for (i = 0; i < 6; i++)
			tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
		tg3_writephy(tp, 0x16, 0x0202);
		if (tg3_wait_macro_done(tp))
			return -EBUSY;
	}

	return 0;
}

static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
{
	u32 reg32, phy9_orig;
	int retries, do_phy_reset, err;

	retries = 10;
	do_phy_reset = 1;
	do {
		if (do_phy_reset) {
			err = tg3_bmcr_reset(tp);
			if (err)
				return err;
			do_phy_reset = 0;
		}

		/* Disable transmitter and interrupt.  */
		if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
			continue;

		reg32 |= 0x3000;
		tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);

		/* Set full-duplex, 1000 mbps.  */
		tg3_writephy(tp, MII_BMCR,
			     BMCR_FULLDPLX | TG3_BMCR_SPEED1000);

		/* Set to master mode.  */
		if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
			continue;

		tg3_writephy(tp, MII_TG3_CTRL,
			     (MII_TG3_CTRL_AS_MASTER |
			      MII_TG3_CTRL_ENABLE_AS_MASTER));

		/* Enable SM_DSP_CLOCK and 6dB.  */
		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);

		/* Block the PHY control access.  */
		tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
		tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);

		err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
		if (!err)
			break;
	} while (--retries);

	err = tg3_phy_reset_chanpat(tp);
	if (err)
		return err;

	tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
	tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);

	tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
	tg3_writephy(tp, 0x16, 0x0000);

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
		/* Set Extended packet length bit for jumbo frames */
		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
	}
	else {
		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
	}

	tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);

	if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
		reg32 &= ~0x3000;
		tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
	} else if (!err)
		err = -EBUSY;

	return err;
}

/* This will reset the tigon3 PHY if there is no valid
 * link unless the FORCE argument is non-zero.
 */
static int tg3_phy_reset(struct tg3 *tp)
{
1780
	u32 cpmuctrl;
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	u32 phy_status;
	int err;

1784 1785 1786 1787 1788 1789 1790
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
		u32 val;

		val = tr32(GRC_MISC_CFG);
		tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
		udelay(40);
	}
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	err  = tg3_readphy(tp, MII_BMSR, &phy_status);
	err |= tg3_readphy(tp, MII_BMSR, &phy_status);
	if (err != 0)
		return -EBUSY;

1796 1797 1798 1799 1800
	if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
		netif_carrier_off(tp->dev);
		tg3_link_report(tp);
	}

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Linus Torvalds 已提交
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	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
		err = tg3_phy_reset_5703_4_5(tp);
		if (err)
			return err;
		goto out;
	}

1810 1811 1812 1813 1814 1815 1816 1817 1818
	cpmuctrl = 0;
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
	    GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
		cpmuctrl = tr32(TG3_CPMU_CTRL);
		if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
			tw32(TG3_CPMU_CTRL,
			     cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
	}

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Linus Torvalds 已提交
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	err = tg3_bmcr_reset(tp);
	if (err)
		return err;

1823 1824 1825 1826 1827 1828 1829 1830 1831
	if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
		u32 phy;

		phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
		tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);

		tw32(TG3_CPMU_CTRL, cpmuctrl);
	}

1832 1833
	if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
	    GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844
		u32 val;

		val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
		if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
		    CPMU_LSPD_1000MB_MACCLK_12_5) {
			val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
			udelay(40);
			tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
		}
	}

1845 1846
	tg3_phy_apply_otp(tp);

1847 1848 1849 1850 1851
	if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
		tg3_phy_toggle_apd(tp, true);
	else
		tg3_phy_toggle_apd(tp, false);

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Linus Torvalds 已提交
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out:
	if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
		tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
		tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
		tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
		tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
	}
	if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
		tg3_writephy(tp, 0x1c, 0x8d68);
		tg3_writephy(tp, 0x1c, 0x8d68);
	}
	if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
		tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
		tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
		tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
		tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
		tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
		tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
	}
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Michael Chan 已提交
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	else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
		tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1878 1879 1880 1881 1882 1883
		if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
			tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
			tg3_writephy(tp, MII_TG3_TEST1,
				     MII_TG3_TEST1_TRIM_EN | 0x4);
		} else
			tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
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Michael Chan 已提交
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		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
	}
L
Linus Torvalds 已提交
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	/* Set Extended packet length bit (bit 14) on all chips that */
	/* support jumbo frames */
	if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
		/* Cannot do read-modify-write on 5401 */
		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1891
	} else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
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		u32 phy_reg;

		/* Set bit 14 with read-modify-write to preserve other bits */
		if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
		    !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
			tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
	}

	/* Set phy register 0x10 bit 0 to high fifo elasticity to support
	 * jumbo frames transmission.
	 */
1903
	if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
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		u32 phy_reg;

		if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
		    tg3_writephy(tp, MII_TG3_EXT_CTRL,
				 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
	}

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	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
		/* adjust output voltage */
		tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
	}

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	tg3_phy_toggle_automdix(tp, 1);
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	tg3_phy_set_wirespeed(tp);
	return 0;
}

static void tg3_frob_aux_power(struct tg3 *tp)
{
	struct tg3 *tp_peer = tp;

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	if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
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		return;

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	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
		struct net_device *dev_peer;

		dev_peer = pci_get_drvdata(tp->pdev_peer);
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		/* remove_one() may have been run on the peer. */
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		if (!dev_peer)
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			tp_peer = tp;
		else
			tp_peer = netdev_priv(dev_peer);
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	}

	if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
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	    (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
	    (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
	    (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
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		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1946 1947 1948 1949 1950 1951 1952
			tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
				    (GRC_LCLCTRL_GPIO_OE0 |
				     GRC_LCLCTRL_GPIO_OE1 |
				     GRC_LCLCTRL_GPIO_OE2 |
				     GRC_LCLCTRL_GPIO_OUTPUT0 |
				     GRC_LCLCTRL_GPIO_OUTPUT1),
				    100);
1953 1954
		} else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
			   tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
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			/* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
			u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
					     GRC_LCLCTRL_GPIO_OE1 |
					     GRC_LCLCTRL_GPIO_OE2 |
					     GRC_LCLCTRL_GPIO_OUTPUT0 |
					     GRC_LCLCTRL_GPIO_OUTPUT1 |
					     tp->grc_local_ctrl;
			tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);

			grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
			tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);

			grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
			tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
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		} else {
			u32 no_gpio2;
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			u32 grc_local_ctrl = 0;
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			if (tp_peer != tp &&
			    (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
				return;

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			/* Workaround to prevent overdrawing Amps. */
			if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
			    ASIC_REV_5714) {
				grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1981 1982
				tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
					    grc_local_ctrl, 100);
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			}

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			/* On 5753 and variants, GPIO2 cannot be used. */
			no_gpio2 = tp->nic_sram_data_cfg &
				    NIC_SRAM_DATA_CFG_NO_GPIO2;

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			grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
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					 GRC_LCLCTRL_GPIO_OE1 |
					 GRC_LCLCTRL_GPIO_OE2 |
					 GRC_LCLCTRL_GPIO_OUTPUT1 |
					 GRC_LCLCTRL_GPIO_OUTPUT2;
			if (no_gpio2) {
				grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
						    GRC_LCLCTRL_GPIO_OUTPUT2);
			}
1998 1999
			tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
						    grc_local_ctrl, 100);
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			grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;

2003 2004
			tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
						    grc_local_ctrl, 100);
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			if (!no_gpio2) {
				grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2008 2009
				tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
					    grc_local_ctrl, 100);
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			}
		}
	} else {
		if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
		    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
			if (tp_peer != tp &&
			    (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
				return;

2019 2020 2021
			tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
				    (GRC_LCLCTRL_GPIO_OE1 |
				     GRC_LCLCTRL_GPIO_OUTPUT1), 100);
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Linus Torvalds 已提交
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2023 2024
			tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
				    GRC_LCLCTRL_GPIO_OE1, 100);
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Linus Torvalds 已提交
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2026 2027 2028
			tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
				    (GRC_LCLCTRL_GPIO_OE1 |
				     GRC_LCLCTRL_GPIO_OUTPUT1), 100);
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		}
	}
}

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static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
{
	if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
		return 1;
	else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
		if (speed != SPEED_10)
			return 1;
	} else if (speed == SPEED_10)
		return 1;

	return 0;
}

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static int tg3_setup_phy(struct tg3 *, int);

#define RESET_KIND_SHUTDOWN	0
#define RESET_KIND_INIT		1
#define RESET_KIND_SUSPEND	2

static void tg3_write_sig_post_reset(struct tg3 *, int);
static int tg3_halt_cpu(struct tg3 *, u32);

2055
static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2056
{
2057 2058
	u32 val;

2059 2060 2061 2062 2063 2064 2065 2066 2067 2068
	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
			u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
			u32 serdes_cfg = tr32(MAC_SERDES_CFG);

			sg_dig_ctrl |=
				SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
			tw32(SG_DIG_CTRL, sg_dig_ctrl);
			tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
		}
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		return;
2070
	}
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2072 2073 2074 2075 2076 2077
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
		tg3_bmcr_reset(tp);
		val = tr32(GRC_MISC_CFG);
		tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
		udelay(40);
		return;
2078
	} else if (do_low_power) {
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		tg3_writephy(tp, MII_TG3_EXT_CTRL,
			     MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2081 2082 2083 2084 2085 2086

		tg3_writephy(tp, MII_TG3_AUX_CTRL,
			     MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
			     MII_TG3_AUXCTL_PCTL_100TX_LPWR |
			     MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
			     MII_TG3_AUXCTL_PCTL_VREG_11V);
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	}
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2089 2090 2091 2092 2093 2094 2095 2096
	/* The PHY should not be powered down on some chips because
	 * of bugs.
	 */
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
	     (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
		return;
2097

2098 2099
	if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
	    GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2100 2101 2102 2103 2104 2105
		val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
		val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
		val |= CPMU_LSPD_1000MB_MACCLK_12_5;
		tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
	}

2106 2107 2108
	tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
}

2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193
/* tp->lock is held. */
static int tg3_nvram_lock(struct tg3 *tp)
{
	if (tp->tg3_flags & TG3_FLAG_NVRAM) {
		int i;

		if (tp->nvram_lock_cnt == 0) {
			tw32(NVRAM_SWARB, SWARB_REQ_SET1);
			for (i = 0; i < 8000; i++) {
				if (tr32(NVRAM_SWARB) & SWARB_GNT1)
					break;
				udelay(20);
			}
			if (i == 8000) {
				tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
				return -ENODEV;
			}
		}
		tp->nvram_lock_cnt++;
	}
	return 0;
}

/* tp->lock is held. */
static void tg3_nvram_unlock(struct tg3 *tp)
{
	if (tp->tg3_flags & TG3_FLAG_NVRAM) {
		if (tp->nvram_lock_cnt > 0)
			tp->nvram_lock_cnt--;
		if (tp->nvram_lock_cnt == 0)
			tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
	}
}

/* tp->lock is held. */
static void tg3_enable_nvram_access(struct tg3 *tp)
{
	if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
	    !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
		u32 nvaccess = tr32(NVRAM_ACCESS);

		tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
	}
}

/* tp->lock is held. */
static void tg3_disable_nvram_access(struct tg3 *tp)
{
	if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
	    !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
		u32 nvaccess = tr32(NVRAM_ACCESS);

		tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
	}
}

static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
					u32 offset, u32 *val)
{
	u32 tmp;
	int i;

	if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
		return -EINVAL;

	tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
					EEPROM_ADDR_DEVID_MASK |
					EEPROM_ADDR_READ);
	tw32(GRC_EEPROM_ADDR,
	     tmp |
	     (0 << EEPROM_ADDR_DEVID_SHIFT) |
	     ((offset << EEPROM_ADDR_ADDR_SHIFT) &
	      EEPROM_ADDR_ADDR_MASK) |
	     EEPROM_ADDR_READ | EEPROM_ADDR_START);

	for (i = 0; i < 1000; i++) {
		tmp = tr32(GRC_EEPROM_ADDR);

		if (tmp & EEPROM_ADDR_COMPLETE)
			break;
		msleep(1);
	}
	if (!(tmp & EEPROM_ADDR_COMPLETE))
		return -EBUSY;

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	tmp = tr32(GRC_EEPROM_DATA);

	/*
	 * The data will always be opposite the native endian
	 * format.  Perform a blind byteswap to compensate.
	 */
	*val = swab32(tmp);

2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255
	return 0;
}

#define NVRAM_CMD_TIMEOUT 10000

static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
{
	int i;

	tw32(NVRAM_CMD, nvram_cmd);
	for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
		udelay(10);
		if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
			udelay(10);
			break;
		}
	}

	if (i == NVRAM_CMD_TIMEOUT)
		return -EBUSY;

	return 0;
}

static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
{
	if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
	    (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
	    (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
	   !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
	    (tp->nvram_jedecnum == JEDEC_ATMEL))

		addr = ((addr / tp->nvram_pagesize) <<
			ATMEL_AT45DB0X1B_PAGE_POS) +
		       (addr % tp->nvram_pagesize);

	return addr;
}

static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
{
	if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
	    (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
	    (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
	   !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
	    (tp->nvram_jedecnum == JEDEC_ATMEL))

		addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
			tp->nvram_pagesize) +
		       (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));

	return addr;
}

2256 2257 2258 2259 2260 2261
/* NOTE: Data read in from NVRAM is byteswapped according to
 * the byteswapping settings for all other register accesses.
 * tg3 devices are BE devices, so on a BE machine, the data
 * returned will be exactly as it is seen in NVRAM.  On a LE
 * machine, the 32-bit value will be byteswapped.
 */
2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284
static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
{
	int ret;

	if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
		return tg3_nvram_read_using_eeprom(tp, offset, val);

	offset = tg3_nvram_phys_addr(tp, offset);

	if (offset > NVRAM_ADDR_MSK)
		return -EINVAL;

	ret = tg3_nvram_lock(tp);
	if (ret)
		return ret;

	tg3_enable_nvram_access(tp);

	tw32(NVRAM_ADDR, offset);
	ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
		NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);

	if (ret == 0)
2285
		*val = tr32(NVRAM_RDDATA);
2286 2287 2288 2289 2290 2291 2292 2293

	tg3_disable_nvram_access(tp);

	tg3_nvram_unlock(tp);

	return ret;
}

2294 2295
/* Ensures NVRAM data is in bytestream format. */
static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2296 2297
{
	u32 v;
2298
	int res = tg3_nvram_read(tp, offset, &v);
2299
	if (!res)
2300
		*val = cpu_to_be32(v);
2301 2302 2303
	return res;
}

2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340
/* tp->lock is held. */
static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
{
	u32 addr_high, addr_low;
	int i;

	addr_high = ((tp->dev->dev_addr[0] << 8) |
		     tp->dev->dev_addr[1]);
	addr_low = ((tp->dev->dev_addr[2] << 24) |
		    (tp->dev->dev_addr[3] << 16) |
		    (tp->dev->dev_addr[4] <<  8) |
		    (tp->dev->dev_addr[5] <<  0));
	for (i = 0; i < 4; i++) {
		if (i == 1 && skip_mac_1)
			continue;
		tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
		tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
	}

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
		for (i = 0; i < 12; i++) {
			tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
			tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
		}
	}

	addr_high = (tp->dev->dev_addr[0] +
		     tp->dev->dev_addr[1] +
		     tp->dev->dev_addr[2] +
		     tp->dev->dev_addr[3] +
		     tp->dev->dev_addr[4] +
		     tp->dev->dev_addr[5]) &
		TX_BACKOFF_SEED_MASK;
	tw32(MAC_TX_BACKOFF_SEED, addr_high);
}

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static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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{
	u32 misc_host_ctrl;
2344
	bool device_should_wake, do_low_power;
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	/* Make sure register accesses (indirect or otherwise)
	 * will function correctly.
	 */
	pci_write_config_dword(tp->pdev,
			       TG3PCI_MISC_HOST_CTRL,
			       tp->misc_host_ctrl);

	switch (state) {
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	case PCI_D0:
2355 2356
		pci_enable_wake(tp->pdev, state, false);
		pci_set_power_state(tp->pdev, PCI_D0);
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		/* Switch out of Vaux if it is a NIC */
		if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2360
			tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
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		return 0;

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	case PCI_D1:
	case PCI_D2:
	case PCI_D3hot:
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		break;

	default:
2370 2371
		printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
			tp->dev->name, state);
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Linus Torvalds 已提交
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		return -EINVAL;
2373
	}
2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387

	/* Restore the CLKREQ setting. */
	if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
		u16 lnkctl;

		pci_read_config_word(tp->pdev,
				     tp->pcie_cap + PCI_EXP_LNKCTL,
				     &lnkctl);
		lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
		pci_write_config_word(tp->pdev,
				      tp->pcie_cap + PCI_EXP_LNKCTL,
				      lnkctl);
	}

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	misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
	tw32(TG3PCI_MISC_HOST_CTRL,
	     misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);

2392 2393 2394 2395
	device_should_wake = pci_pme_capable(tp->pdev, state) &&
			     device_may_wakeup(&tp->pdev->dev) &&
			     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);

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	if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2397
		do_low_power = false;
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		if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
		    !tp->link_config.phy_is_low_power) {
			struct phy_device *phydev;
2401
			u32 phyid, advertising;
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Matt Carlson 已提交
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2403
			phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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			tp->link_config.phy_is_low_power = 1;

			tp->link_config.orig_speed = phydev->speed;
			tp->link_config.orig_duplex = phydev->duplex;
			tp->link_config.orig_autoneg = phydev->autoneg;
			tp->link_config.orig_advertising = phydev->advertising;

			advertising = ADVERTISED_TP |
				      ADVERTISED_Pause |
				      ADVERTISED_Autoneg |
				      ADVERTISED_10baseT_Half;

			if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2418
			    device_should_wake) {
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				if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
					advertising |=
						ADVERTISED_100baseT_Half |
						ADVERTISED_100baseT_Full |
						ADVERTISED_10baseT_Full;
				else
					advertising |= ADVERTISED_10baseT_Full;
			}

			phydev->advertising = advertising;

			phy_start_aneg(phydev);
2431 2432 2433 2434

			phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
			if (phyid != TG3_PHY_ID_BCMAC131) {
				phyid &= TG3_PHY_OUI_MASK;
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Roel Kluin 已提交
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				if (phyid == TG3_PHY_OUI_1 ||
				    phyid == TG3_PHY_OUI_2 ||
2437 2438 2439
				    phyid == TG3_PHY_OUI_3)
					do_low_power = true;
			}
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Matt Carlson 已提交
2440
		}
M
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2441
	} else {
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		do_low_power = true;
2443

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2444 2445 2446 2447 2448 2449
		if (tp->link_config.phy_is_low_power == 0) {
			tp->link_config.phy_is_low_power = 1;
			tp->link_config.orig_speed = tp->link_config.speed;
			tp->link_config.orig_duplex = tp->link_config.duplex;
			tp->link_config.orig_autoneg = tp->link_config.autoneg;
		}
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		if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
			tp->link_config.speed = SPEED_10;
			tp->link_config.duplex = DUPLEX_HALF;
			tp->link_config.autoneg = AUTONEG_ENABLE;
			tg3_setup_phy(tp, 0);
		}
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	}

2459 2460
	__tg3_set_mac_addr(tp, 0);

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	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
		u32 val;

		val = tr32(GRC_VCPU_EXT_CTRL);
		tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
	} else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
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		int i;
		u32 val;

		for (i = 0; i < 200; i++) {
			tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
			if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
				break;
			msleep(1);
		}
	}
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	if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
		tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
						     WOL_DRV_STATE_SHUTDOWN |
						     WOL_DRV_WOL |
						     WOL_SET_MAGIC_PKT);
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2483
	if (device_should_wake) {
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		u32 mac_mode;

		if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2487
			if (do_low_power) {
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				tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
				udelay(40);
			}
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			if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
				mac_mode = MAC_MODE_PORT_MODE_GMII;
			else
				mac_mode = MAC_MODE_PORT_MODE_MII;
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			mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
			if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
			    ASIC_REV_5700) {
				u32 speed = (tp->tg3_flags &
					     TG3_FLAG_WOL_SPEED_100MB) ?
					     SPEED_100 : SPEED_10;
				if (tg3_5700_link_polarity(tp, speed))
					mac_mode |= MAC_MODE_LINK_POLARITY;
				else
					mac_mode &= ~MAC_MODE_LINK_POLARITY;
			}
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		} else {
			mac_mode = MAC_MODE_PORT_MODE_TBI;
		}

2512
		if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
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			tw32(MAC_LED_CTRL, tp->led_ctrl);

2515 2516 2517 2518 2519 2520
		mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
		if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
		    !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
		    ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
		     (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
			mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
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2522 2523 2524 2525 2526 2527 2528
		if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
			mac_mode |= tp->mac_mode &
				    (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
			if (mac_mode & MAC_MODE_APE_TX_EN)
				mac_mode |= MAC_MODE_TDE_ENABLE;
		}

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		tw32_f(MAC_MODE, mac_mode);
		udelay(100);

		tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
		udelay(10);
	}

	if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
		u32 base_val;

		base_val = tp->pci_clock_ctrl;
		base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
			     CLOCK_CTRL_TXCLK_DISABLE);

2545 2546
		tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
			    CLOCK_CTRL_PWRDOWN_PLL133, 40);
2547
	} else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2548
		   (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2549
		   (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
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		/* do nothing */
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	} else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
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		     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
		u32 newbits1, newbits2;

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
			newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
				    CLOCK_CTRL_TXCLK_DISABLE |
				    CLOCK_CTRL_ALTCLK);
			newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
		} else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
			newbits1 = CLOCK_CTRL_625_CORE;
			newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
		} else {
			newbits1 = CLOCK_CTRL_ALTCLK;
			newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
		}

2569 2570
		tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
			    40);
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2572 2573
		tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
			    40);
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		if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
			u32 newbits3;

			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
			    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
				newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
					    CLOCK_CTRL_TXCLK_DISABLE |
					    CLOCK_CTRL_44MHZ_CORE);
			} else {
				newbits3 = CLOCK_CTRL_44MHZ_CORE;
			}

2587 2588
			tw32_wait_f(TG3PCI_CLOCK_CTRL,
				    tp->pci_clock_ctrl | newbits3, 40);
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		}
	}

2592
	if (!(device_should_wake) &&
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2593
	    !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2594
		tg3_power_down_phy(tp, do_low_power);
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	tg3_frob_aux_power(tp);

	/* Workaround for unstable PLL clock */
	if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
	    (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
		u32 val = tr32(0x7d00);

		val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
		tw32(0x7d00, val);
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		if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
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			int err;

			err = tg3_nvram_lock(tp);
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			tg3_halt_cpu(tp, RX_CPU_BASE);
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			if (!err)
				tg3_nvram_unlock(tp);
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		}
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	}

2615 2616
	tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);

2617
	if (device_should_wake)
2618 2619
		pci_enable_wake(tp->pdev, state, true);

L
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2620
	/* Finally, set the new power state. */
2621
	pci_set_power_state(tp->pdev, state);
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	return 0;
}

static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
{
	switch (val & MII_TG3_AUX_STAT_SPDMASK) {
	case MII_TG3_AUX_STAT_10HALF:
		*speed = SPEED_10;
		*duplex = DUPLEX_HALF;
		break;

	case MII_TG3_AUX_STAT_10FULL:
		*speed = SPEED_10;
		*duplex = DUPLEX_FULL;
		break;

	case MII_TG3_AUX_STAT_100HALF:
		*speed = SPEED_100;
		*duplex = DUPLEX_HALF;
		break;

	case MII_TG3_AUX_STAT_100FULL:
		*speed = SPEED_100;
		*duplex = DUPLEX_FULL;
		break;

	case MII_TG3_AUX_STAT_1000HALF:
		*speed = SPEED_1000;
		*duplex = DUPLEX_HALF;
		break;

	case MII_TG3_AUX_STAT_1000FULL:
		*speed = SPEED_1000;
		*duplex = DUPLEX_FULL;
		break;

	default:
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		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
			*speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
				 SPEED_10;
			*duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
				  DUPLEX_HALF;
			break;
		}
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		*speed = SPEED_INVALID;
		*duplex = DUPLEX_INVALID;
		break;
2670
	}
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}

static void tg3_phy_copper_begin(struct tg3 *tp)
{
	u32 new_adv;
	int i;

	if (tp->link_config.phy_is_low_power) {
		/* Entering low power mode.  Disable gigabit and
		 * 100baseT advertisements.
		 */
		tg3_writephy(tp, MII_TG3_CTRL, 0);

		new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
			   ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
		if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
			new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);

		tg3_writephy(tp, MII_ADVERTISE, new_adv);
	} else if (tp->link_config.speed == SPEED_INVALID) {
		if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
			tp->link_config.advertising &=
				~(ADVERTISED_1000baseT_Half |
				  ADVERTISED_1000baseT_Full);

2696
		new_adv = ADVERTISE_CSMA;
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		if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
			new_adv |= ADVERTISE_10HALF;
		if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
			new_adv |= ADVERTISE_10FULL;
		if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
			new_adv |= ADVERTISE_100HALF;
		if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
			new_adv |= ADVERTISE_100FULL;
2705 2706 2707

		new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);

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		tg3_writephy(tp, MII_ADVERTISE, new_adv);

		if (tp->link_config.advertising &
		    (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
			new_adv = 0;
			if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
				new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
			if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
				new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
			if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
			    (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
			     tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
				new_adv |= (MII_TG3_CTRL_AS_MASTER |
					    MII_TG3_CTRL_ENABLE_AS_MASTER);
			tg3_writephy(tp, MII_TG3_CTRL, new_adv);
		} else {
			tg3_writephy(tp, MII_TG3_CTRL, 0);
		}
	} else {
2727 2728 2729
		new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
		new_adv |= ADVERTISE_CSMA;

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		/* Asking for a specific link mode. */
		if (tp->link_config.speed == SPEED_1000) {
			tg3_writephy(tp, MII_ADVERTISE, new_adv);

			if (tp->link_config.duplex == DUPLEX_FULL)
				new_adv = MII_TG3_CTRL_ADV_1000_FULL;
			else
				new_adv = MII_TG3_CTRL_ADV_1000_HALF;
			if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
			    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
				new_adv |= (MII_TG3_CTRL_AS_MASTER |
					    MII_TG3_CTRL_ENABLE_AS_MASTER);
		} else {
			if (tp->link_config.speed == SPEED_100) {
				if (tp->link_config.duplex == DUPLEX_FULL)
					new_adv |= ADVERTISE_100FULL;
				else
					new_adv |= ADVERTISE_100HALF;
			} else {
				if (tp->link_config.duplex == DUPLEX_FULL)
					new_adv |= ADVERTISE_10FULL;
				else
					new_adv |= ADVERTISE_10HALF;
			}
			tg3_writephy(tp, MII_ADVERTISE, new_adv);
2755 2756

			new_adv = 0;
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		}
2758 2759

		tg3_writephy(tp, MII_TG3_CTRL, new_adv);
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	}

	if (tp->link_config.autoneg == AUTONEG_DISABLE &&
	    tp->link_config.speed != SPEED_INVALID) {
		u32 bmcr, orig_bmcr;

		tp->link_config.active_speed = tp->link_config.speed;
		tp->link_config.active_duplex = tp->link_config.duplex;

		bmcr = 0;
		switch (tp->link_config.speed) {
		default:
		case SPEED_10:
			break;

		case SPEED_100:
			bmcr |= BMCR_SPEED100;
			break;

		case SPEED_1000:
			bmcr |= TG3_BMCR_SPEED1000;
			break;
2782
		}
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		if (tp->link_config.duplex == DUPLEX_FULL)
			bmcr |= BMCR_FULLDPLX;

		if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
		    (bmcr != orig_bmcr)) {
			tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
			for (i = 0; i < 1500; i++) {
				u32 tmp;

				udelay(10);
				if (tg3_readphy(tp, MII_BMSR, &tmp) ||
				    tg3_readphy(tp, MII_BMSR, &tmp))
					continue;
				if (!(tmp & BMSR_LSTATUS)) {
					udelay(40);
					break;
				}
			}
			tg3_writephy(tp, MII_BMCR, bmcr);
			udelay(40);
		}
	} else {
		tg3_writephy(tp, MII_BMCR,
			     BMCR_ANENABLE | BMCR_ANRESTART);
	}
}

static int tg3_init_5401phy_dsp(struct tg3 *tp)
{
	int err;

	/* Turn off tap power management. */
	/* Set Extended packet length bit */
	err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);

	err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
	err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);

	err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
	err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);

	err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
	err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);

	err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
	err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);

	err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
	err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);

	udelay(40);

	return err;
}

2839
static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
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{
2841 2842 2843 2844 2845 2846 2847 2848 2849 2850
	u32 adv_reg, all_mask = 0;

	if (mask & ADVERTISED_10baseT_Half)
		all_mask |= ADVERTISE_10HALF;
	if (mask & ADVERTISED_10baseT_Full)
		all_mask |= ADVERTISE_10FULL;
	if (mask & ADVERTISED_100baseT_Half)
		all_mask |= ADVERTISE_100HALF;
	if (mask & ADVERTISED_100baseT_Full)
		all_mask |= ADVERTISE_100FULL;
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	if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
		return 0;

	if ((adv_reg & all_mask) != all_mask)
		return 0;
	if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
		u32 tg3_ctrl;

2860 2861 2862 2863 2864 2865
		all_mask = 0;
		if (mask & ADVERTISED_1000baseT_Half)
			all_mask |= ADVERTISE_1000HALF;
		if (mask & ADVERTISED_1000baseT_Full)
			all_mask |= ADVERTISE_1000FULL;

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		if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
			return 0;

		if ((tg3_ctrl & all_mask) != all_mask)
			return 0;
	}
	return 1;
}

2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907
static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
{
	u32 curadv, reqadv;

	if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
		return 1;

	curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
	reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);

	if (tp->link_config.active_duplex == DUPLEX_FULL) {
		if (curadv != reqadv)
			return 0;

		if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
			tg3_readphy(tp, MII_LPA, rmtadv);
	} else {
		/* Reprogram the advertisement register, even if it
		 * does not affect the current link.  If the link
		 * gets renegotiated in the future, we can save an
		 * additional renegotiation cycle by advertising
		 * it correctly in the first place.
		 */
		if (curadv != reqadv) {
			*lcladv &= ~(ADVERTISE_PAUSE_CAP |
				     ADVERTISE_PAUSE_ASYM);
			tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
		}
	}

	return 1;
}

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static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
{
	int current_link_up;
	u32 bmsr, dummy;
2912
	u32 lcl_adv, rmt_adv;
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	u16 current_speed;
	u8 current_duplex;
	int i, err;

	tw32(MAC_EVENT, 0);

	tw32_f(MAC_STATUS,
	     (MAC_STATUS_SYNC_CHANGED |
	      MAC_STATUS_CFG_CHANGED |
	      MAC_STATUS_MI_COMPLETION |
	      MAC_STATUS_LNKSTATE_CHANGED));
	udelay(40);

2926 2927 2928 2929 2930
	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
		tw32_f(MAC_MI_MODE,
		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
		udelay(80);
	}
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2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994

	tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);

	/* Some third-party PHYs need to be reset on link going
	 * down.
	 */
	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
	    netif_carrier_ok(tp->dev)) {
		tg3_readphy(tp, MII_BMSR, &bmsr);
		if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
		    !(bmsr & BMSR_LSTATUS))
			force_reset = 1;
	}
	if (force_reset)
		tg3_phy_reset(tp);

	if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
		tg3_readphy(tp, MII_BMSR, &bmsr);
		if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
		    !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
			bmsr = 0;

		if (!(bmsr & BMSR_LSTATUS)) {
			err = tg3_init_5401phy_dsp(tp);
			if (err)
				return err;

			tg3_readphy(tp, MII_BMSR, &bmsr);
			for (i = 0; i < 1000; i++) {
				udelay(10);
				if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
				    (bmsr & BMSR_LSTATUS)) {
					udelay(40);
					break;
				}
			}

			if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
			    !(bmsr & BMSR_LSTATUS) &&
			    tp->link_config.active_speed == SPEED_1000) {
				err = tg3_phy_reset(tp);
				if (!err)
					err = tg3_init_5401phy_dsp(tp);
				if (err)
					return err;
			}
		}
	} else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
		   tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
		/* 5701 {A0,B0} CRC bug workaround */
		tg3_writephy(tp, 0x15, 0x0a75);
		tg3_writephy(tp, 0x1c, 0x8c68);
		tg3_writephy(tp, 0x1c, 0x8d68);
		tg3_writephy(tp, 0x1c, 0x8c68);
	}

	/* Clear pending interrupts... */
	tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
	tg3_readphy(tp, MII_TG3_ISTAT, &dummy);

	if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
		tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
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	else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
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		tg3_writephy(tp, MII_TG3_IMASK, ~0);

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
		if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
			tg3_writephy(tp, MII_TG3_EXT_CTRL,
				     MII_TG3_EXT_CTRL_LNK3_LED_MODE);
		else
			tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
	}

	current_link_up = 0;
	current_speed = SPEED_INVALID;
	current_duplex = DUPLEX_INVALID;

	if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
		u32 val;

		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
		tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
		if (!(val & (1 << 10))) {
			val |= (1 << 10);
			tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
			goto relink;
		}
	}

	bmsr = 0;
	for (i = 0; i < 100; i++) {
		tg3_readphy(tp, MII_BMSR, &bmsr);
		if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
		    (bmsr & BMSR_LSTATUS))
			break;
		udelay(40);
	}

	if (bmsr & BMSR_LSTATUS) {
		u32 aux_stat, bmcr;

		tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
		for (i = 0; i < 2000; i++) {
			udelay(10);
			if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
			    aux_stat)
				break;
		}

		tg3_aux_stat_to_speed_duplex(tp, aux_stat,
					     &current_speed,
					     &current_duplex);

		bmcr = 0;
		for (i = 0; i < 200; i++) {
			tg3_readphy(tp, MII_BMCR, &bmcr);
			if (tg3_readphy(tp, MII_BMCR, &bmcr))
				continue;
			if (bmcr && bmcr != 0x7fff)
				break;
			udelay(10);
		}

3057 3058
		lcl_adv = 0;
		rmt_adv = 0;
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Linus Torvalds 已提交
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3060 3061 3062 3063 3064 3065 3066 3067 3068 3069
		tp->link_config.active_speed = current_speed;
		tp->link_config.active_duplex = current_duplex;

		if (tp->link_config.autoneg == AUTONEG_ENABLE) {
			if ((bmcr & BMCR_ANENABLE) &&
			    tg3_copper_is_advertising_all(tp,
						tp->link_config.advertising)) {
				if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
								  &rmt_adv))
					current_link_up = 1;
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			}
		} else {
			if (!(bmcr & BMCR_ANENABLE) &&
			    tp->link_config.speed == current_speed &&
3074 3075 3076
			    tp->link_config.duplex == current_duplex &&
			    tp->link_config.flowctrl ==
			    tp->link_config.active_flowctrl) {
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Linus Torvalds 已提交
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				current_link_up = 1;
			}
		}

3081 3082 3083
		if (current_link_up == 1 &&
		    tp->link_config.active_duplex == DUPLEX_FULL)
			tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
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	}

relink:
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	if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
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		u32 tmp;

		tg3_phy_copper_begin(tp);

		tg3_readphy(tp, MII_BMSR, &tmp);
		if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
		    (tmp & BMSR_LSTATUS))
			current_link_up = 1;
	}

	tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
	if (current_link_up == 1) {
		if (tp->link_config.active_speed == SPEED_100 ||
		    tp->link_config.active_speed == SPEED_10)
			tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
		else
			tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
	} else
		tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;

	tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
	if (tp->link_config.active_duplex == DUPLEX_HALF)
		tp->mac_mode |= MAC_MODE_HALF_DUPLEX;

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
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Matt Carlson 已提交
3113 3114
		if (current_link_up == 1 &&
		    tg3_5700_link_polarity(tp, tp->link_config.active_speed))
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			tp->mac_mode |= MAC_MODE_LINK_POLARITY;
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3116 3117
		else
			tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
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	}

	/* ??? Without this setting Netgear GA302T PHY does not
	 * ??? send/receive packets...
	 */
	if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
	    tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
		tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
		tw32_f(MAC_MI_MODE, tp->mi_mode);
		udelay(80);
	}

	tw32_f(MAC_MODE, tp->mac_mode);
	udelay(40);

	if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
		/* Polled via timer. */
		tw32_f(MAC_EVENT, 0);
	} else {
		tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
	}
	udelay(40);

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
	    current_link_up == 1 &&
	    tp->link_config.active_speed == SPEED_1000 &&
	    ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
	     (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
		udelay(120);
		tw32_f(MAC_STATUS,
		     (MAC_STATUS_SYNC_CHANGED |
		      MAC_STATUS_CFG_CHANGED));
		udelay(40);
		tg3_write_mem(tp,
			      NIC_SRAM_FIRMWARE_MBOX,
			      NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
	}

3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173
	/* Prevent send BD corruption. */
	if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
		u16 oldlnkctl, newlnkctl;

		pci_read_config_word(tp->pdev,
				     tp->pcie_cap + PCI_EXP_LNKCTL,
				     &oldlnkctl);
		if (tp->link_config.active_speed == SPEED_100 ||
		    tp->link_config.active_speed == SPEED_10)
			newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
		else
			newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
		if (newlnkctl != oldlnkctl)
			pci_write_config_word(tp->pdev,
					      tp->pcie_cap + PCI_EXP_LNKCTL,
					      newlnkctl);
	}

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	if (current_link_up != netif_carrier_ok(tp->dev)) {
		if (current_link_up)
			netif_carrier_on(tp->dev);
		else
			netif_carrier_off(tp->dev);
		tg3_link_report(tp);
	}

	return 0;
}

struct tg3_fiber_aneginfo {
	int state;
#define ANEG_STATE_UNKNOWN		0
#define ANEG_STATE_AN_ENABLE		1
#define ANEG_STATE_RESTART_INIT		2
#define ANEG_STATE_RESTART		3
#define ANEG_STATE_DISABLE_LINK_OK	4
#define ANEG_STATE_ABILITY_DETECT_INIT	5
#define ANEG_STATE_ABILITY_DETECT	6
#define ANEG_STATE_ACK_DETECT_INIT	7
#define ANEG_STATE_ACK_DETECT		8
#define ANEG_STATE_COMPLETE_ACK_INIT	9
#define ANEG_STATE_COMPLETE_ACK		10
#define ANEG_STATE_IDLE_DETECT_INIT	11
#define ANEG_STATE_IDLE_DETECT		12
#define ANEG_STATE_LINK_OK		13
#define ANEG_STATE_NEXT_PAGE_WAIT_INIT	14
#define ANEG_STATE_NEXT_PAGE_WAIT	15

	u32 flags;
#define MR_AN_ENABLE		0x00000001
#define MR_RESTART_AN		0x00000002
#define MR_AN_COMPLETE		0x00000004
#define MR_PAGE_RX		0x00000008
#define MR_NP_LOADED		0x00000010
#define MR_TOGGLE_TX		0x00000020
#define MR_LP_ADV_FULL_DUPLEX	0x00000040
#define MR_LP_ADV_HALF_DUPLEX	0x00000080
#define MR_LP_ADV_SYM_PAUSE	0x00000100
#define MR_LP_ADV_ASYM_PAUSE	0x00000200
#define MR_LP_ADV_REMOTE_FAULT1	0x00000400
#define MR_LP_ADV_REMOTE_FAULT2	0x00000800
#define MR_LP_ADV_NEXT_PAGE	0x00001000
#define MR_TOGGLE_RX		0x00002000
#define MR_NP_RX		0x00004000

#define MR_LINK_OK		0x80000000

	unsigned long link_time, cur_time;

	u32 ability_match_cfg;
	int ability_match_count;

	char ability_match, idle_match, ack_match;

	u32 txconfig, rxconfig;
#define ANEG_CFG_NP		0x00000080
#define ANEG_CFG_ACK		0x00000040
#define ANEG_CFG_RF2		0x00000020
#define ANEG_CFG_RF1		0x00000010
#define ANEG_CFG_PS2		0x00000001
#define ANEG_CFG_PS1		0x00008000
#define ANEG_CFG_HD		0x00004000
#define ANEG_CFG_FD		0x00002000
#define ANEG_CFG_INVAL		0x00001f06

};
#define ANEG_OK		0
#define ANEG_DONE	1
#define ANEG_TIMER_ENAB	2
#define ANEG_FAILED	-1

#define ANEG_STATE_SETTLE_TIME	10000

static int tg3_fiber_aneg_smachine(struct tg3 *tp,
				   struct tg3_fiber_aneginfo *ap)
{
3252
	u16 flowctrl;
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	unsigned long delta;
	u32 rx_cfg_reg;
	int ret;

	if (ap->state == ANEG_STATE_UNKNOWN) {
		ap->rxconfig = 0;
		ap->link_time = 0;
		ap->cur_time = 0;
		ap->ability_match_cfg = 0;
		ap->ability_match_count = 0;
		ap->ability_match = 0;
		ap->idle_match = 0;
		ap->ack_match = 0;
	}
	ap->cur_time++;

	if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
		rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);

		if (rx_cfg_reg != ap->ability_match_cfg) {
			ap->ability_match_cfg = rx_cfg_reg;
			ap->ability_match = 0;
			ap->ability_match_count = 0;
		} else {
			if (++ap->ability_match_count > 1) {
				ap->ability_match = 1;
				ap->ability_match_cfg = rx_cfg_reg;
			}
		}
		if (rx_cfg_reg & ANEG_CFG_ACK)
			ap->ack_match = 1;
		else
			ap->ack_match = 0;

		ap->idle_match = 0;
	} else {
		ap->idle_match = 1;
		ap->ability_match_cfg = 0;
		ap->ability_match_count = 0;
		ap->ability_match = 0;
		ap->ack_match = 0;

		rx_cfg_reg = 0;
	}

	ap->rxconfig = rx_cfg_reg;
	ret = ANEG_OK;

	switch(ap->state) {
	case ANEG_STATE_UNKNOWN:
		if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
			ap->state = ANEG_STATE_AN_ENABLE;

		/* fallthru */
	case ANEG_STATE_AN_ENABLE:
		ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
		if (ap->flags & MR_AN_ENABLE) {
			ap->link_time = 0;
			ap->cur_time = 0;
			ap->ability_match_cfg = 0;
			ap->ability_match_count = 0;
			ap->ability_match = 0;
			ap->idle_match = 0;
			ap->ack_match = 0;

			ap->state = ANEG_STATE_RESTART_INIT;
		} else {
			ap->state = ANEG_STATE_DISABLE_LINK_OK;
		}
		break;

	case ANEG_STATE_RESTART_INIT:
		ap->link_time = ap->cur_time;
		ap->flags &= ~(MR_NP_LOADED);
		ap->txconfig = 0;
		tw32(MAC_TX_AUTO_NEG, 0);
		tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
		tw32_f(MAC_MODE, tp->mac_mode);
		udelay(40);

		ret = ANEG_TIMER_ENAB;
		ap->state = ANEG_STATE_RESTART;

		/* fallthru */
	case ANEG_STATE_RESTART:
		delta = ap->cur_time - ap->link_time;
		if (delta > ANEG_STATE_SETTLE_TIME) {
			ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
		} else {
			ret = ANEG_TIMER_ENAB;
		}
		break;

	case ANEG_STATE_DISABLE_LINK_OK:
		ret = ANEG_DONE;
		break;

	case ANEG_STATE_ABILITY_DETECT_INIT:
		ap->flags &= ~(MR_TOGGLE_TX);
3352 3353 3354 3355 3356 3357
		ap->txconfig = ANEG_CFG_FD;
		flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
		if (flowctrl & ADVERTISE_1000XPAUSE)
			ap->txconfig |= ANEG_CFG_PS1;
		if (flowctrl & ADVERTISE_1000XPSE_ASYM)
			ap->txconfig |= ANEG_CFG_PS2;
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Linus Torvalds 已提交
3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497
		tw32(MAC_TX_AUTO_NEG, ap->txconfig);
		tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
		tw32_f(MAC_MODE, tp->mac_mode);
		udelay(40);

		ap->state = ANEG_STATE_ABILITY_DETECT;
		break;

	case ANEG_STATE_ABILITY_DETECT:
		if (ap->ability_match != 0 && ap->rxconfig != 0) {
			ap->state = ANEG_STATE_ACK_DETECT_INIT;
		}
		break;

	case ANEG_STATE_ACK_DETECT_INIT:
		ap->txconfig |= ANEG_CFG_ACK;
		tw32(MAC_TX_AUTO_NEG, ap->txconfig);
		tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
		tw32_f(MAC_MODE, tp->mac_mode);
		udelay(40);

		ap->state = ANEG_STATE_ACK_DETECT;

		/* fallthru */
	case ANEG_STATE_ACK_DETECT:
		if (ap->ack_match != 0) {
			if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
			    (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
				ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
			} else {
				ap->state = ANEG_STATE_AN_ENABLE;
			}
		} else if (ap->ability_match != 0 &&
			   ap->rxconfig == 0) {
			ap->state = ANEG_STATE_AN_ENABLE;
		}
		break;

	case ANEG_STATE_COMPLETE_ACK_INIT:
		if (ap->rxconfig & ANEG_CFG_INVAL) {
			ret = ANEG_FAILED;
			break;
		}
		ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
			       MR_LP_ADV_HALF_DUPLEX |
			       MR_LP_ADV_SYM_PAUSE |
			       MR_LP_ADV_ASYM_PAUSE |
			       MR_LP_ADV_REMOTE_FAULT1 |
			       MR_LP_ADV_REMOTE_FAULT2 |
			       MR_LP_ADV_NEXT_PAGE |
			       MR_TOGGLE_RX |
			       MR_NP_RX);
		if (ap->rxconfig & ANEG_CFG_FD)
			ap->flags |= MR_LP_ADV_FULL_DUPLEX;
		if (ap->rxconfig & ANEG_CFG_HD)
			ap->flags |= MR_LP_ADV_HALF_DUPLEX;
		if (ap->rxconfig & ANEG_CFG_PS1)
			ap->flags |= MR_LP_ADV_SYM_PAUSE;
		if (ap->rxconfig & ANEG_CFG_PS2)
			ap->flags |= MR_LP_ADV_ASYM_PAUSE;
		if (ap->rxconfig & ANEG_CFG_RF1)
			ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
		if (ap->rxconfig & ANEG_CFG_RF2)
			ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
		if (ap->rxconfig & ANEG_CFG_NP)
			ap->flags |= MR_LP_ADV_NEXT_PAGE;

		ap->link_time = ap->cur_time;

		ap->flags ^= (MR_TOGGLE_TX);
		if (ap->rxconfig & 0x0008)
			ap->flags |= MR_TOGGLE_RX;
		if (ap->rxconfig & ANEG_CFG_NP)
			ap->flags |= MR_NP_RX;
		ap->flags |= MR_PAGE_RX;

		ap->state = ANEG_STATE_COMPLETE_ACK;
		ret = ANEG_TIMER_ENAB;
		break;

	case ANEG_STATE_COMPLETE_ACK:
		if (ap->ability_match != 0 &&
		    ap->rxconfig == 0) {
			ap->state = ANEG_STATE_AN_ENABLE;
			break;
		}
		delta = ap->cur_time - ap->link_time;
		if (delta > ANEG_STATE_SETTLE_TIME) {
			if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
				ap->state = ANEG_STATE_IDLE_DETECT_INIT;
			} else {
				if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
				    !(ap->flags & MR_NP_RX)) {
					ap->state = ANEG_STATE_IDLE_DETECT_INIT;
				} else {
					ret = ANEG_FAILED;
				}
			}
		}
		break;

	case ANEG_STATE_IDLE_DETECT_INIT:
		ap->link_time = ap->cur_time;
		tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
		tw32_f(MAC_MODE, tp->mac_mode);
		udelay(40);

		ap->state = ANEG_STATE_IDLE_DETECT;
		ret = ANEG_TIMER_ENAB;
		break;

	case ANEG_STATE_IDLE_DETECT:
		if (ap->ability_match != 0 &&
		    ap->rxconfig == 0) {
			ap->state = ANEG_STATE_AN_ENABLE;
			break;
		}
		delta = ap->cur_time - ap->link_time;
		if (delta > ANEG_STATE_SETTLE_TIME) {
			/* XXX another gem from the Broadcom driver :( */
			ap->state = ANEG_STATE_LINK_OK;
		}
		break;

	case ANEG_STATE_LINK_OK:
		ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
		ret = ANEG_DONE;
		break;

	case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
		/* ??? unimplemented */
		break;

	case ANEG_STATE_NEXT_PAGE_WAIT:
		/* ??? unimplemented */
		break;

	default:
		ret = ANEG_FAILED;
		break;
3498
	}
L
Linus Torvalds 已提交
3499 3500 3501 3502

	return ret;
}

3503
static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
L
Linus Torvalds 已提交
3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536
{
	int res = 0;
	struct tg3_fiber_aneginfo aninfo;
	int status = ANEG_FAILED;
	unsigned int tick;
	u32 tmp;

	tw32_f(MAC_TX_AUTO_NEG, 0);

	tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
	tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
	udelay(40);

	tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
	udelay(40);

	memset(&aninfo, 0, sizeof(aninfo));
	aninfo.flags |= MR_AN_ENABLE;
	aninfo.state = ANEG_STATE_UNKNOWN;
	aninfo.cur_time = 0;
	tick = 0;
	while (++tick < 195000) {
		status = tg3_fiber_aneg_smachine(tp, &aninfo);
		if (status == ANEG_DONE || status == ANEG_FAILED)
			break;

		udelay(1);
	}

	tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
	tw32_f(MAC_MODE, tp->mac_mode);
	udelay(40);

3537 3538
	*txflags = aninfo.txconfig;
	*rxflags = aninfo.flags;
L
Linus Torvalds 已提交
3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599

	if (status == ANEG_DONE &&
	    (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
			     MR_LP_ADV_FULL_DUPLEX)))
		res = 1;

	return res;
}

static void tg3_init_bcm8002(struct tg3 *tp)
{
	u32 mac_status = tr32(MAC_STATUS);
	int i;

	/* Reset when initting first time or we have a link. */
	if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
	    !(mac_status & MAC_STATUS_PCS_SYNCED))
		return;

	/* Set PLL lock range. */
	tg3_writephy(tp, 0x16, 0x8007);

	/* SW reset */
	tg3_writephy(tp, MII_BMCR, BMCR_RESET);

	/* Wait for reset to complete. */
	/* XXX schedule_timeout() ... */
	for (i = 0; i < 500; i++)
		udelay(10);

	/* Config mode; select PMA/Ch 1 regs. */
	tg3_writephy(tp, 0x10, 0x8411);

	/* Enable auto-lock and comdet, select txclk for tx. */
	tg3_writephy(tp, 0x11, 0x0a10);

	tg3_writephy(tp, 0x18, 0x00a0);
	tg3_writephy(tp, 0x16, 0x41ff);

	/* Assert and deassert POR. */
	tg3_writephy(tp, 0x13, 0x0400);
	udelay(40);
	tg3_writephy(tp, 0x13, 0x0000);

	tg3_writephy(tp, 0x11, 0x0a50);
	udelay(40);
	tg3_writephy(tp, 0x11, 0x0a10);

	/* Wait for signal to stabilize */
	/* XXX schedule_timeout() ... */
	for (i = 0; i < 15000; i++)
		udelay(10);

	/* Deselect the channel register so we can read the PHYID
	 * later.
	 */
	tg3_writephy(tp, 0x10, 0x8011);
}

static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
{
3600
	u16 flowctrl;
L
Linus Torvalds 已提交
3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625
	u32 sg_dig_ctrl, sg_dig_status;
	u32 serdes_cfg, expected_sg_dig_ctrl;
	int workaround, port_a;
	int current_link_up;

	serdes_cfg = 0;
	expected_sg_dig_ctrl = 0;
	workaround = 0;
	port_a = 1;
	current_link_up = 0;

	if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
	    tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
		workaround = 1;
		if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
			port_a = 0;

		/* preserve bits 0-11,13,14 for signal pre-emphasis */
		/* preserve bits 20-23 for voltage regulator */
		serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
	}

	sg_dig_ctrl = tr32(SG_DIG_CTRL);

	if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3626
		if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
L
Linus Torvalds 已提交
3627 3628 3629 3630 3631 3632 3633 3634 3635
			if (workaround) {
				u32 val = serdes_cfg;

				if (port_a)
					val |= 0xc010000;
				else
					val |= 0x4010000;
				tw32_f(MAC_SERDES_CFG, val);
			}
3636 3637

			tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
L
Linus Torvalds 已提交
3638 3639 3640 3641 3642 3643 3644 3645 3646
		}
		if (mac_status & MAC_STATUS_PCS_SYNCED) {
			tg3_setup_flow_control(tp, 0, 0);
			current_link_up = 1;
		}
		goto out;
	}

	/* Want auto-negotiation.  */
3647
	expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
L
Linus Torvalds 已提交
3648

3649 3650 3651 3652 3653
	flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
	if (flowctrl & ADVERTISE_1000XPAUSE)
		expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
	if (flowctrl & ADVERTISE_1000XPSE_ASYM)
		expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
L
Linus Torvalds 已提交
3654 3655

	if (sg_dig_ctrl != expected_sg_dig_ctrl) {
M
Michael Chan 已提交
3656 3657 3658 3659 3660 3661 3662 3663 3664 3665
		if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
		    tp->serdes_counter &&
		    ((mac_status & (MAC_STATUS_PCS_SYNCED |
				    MAC_STATUS_RCVD_CFG)) ==
		     MAC_STATUS_PCS_SYNCED)) {
			tp->serdes_counter--;
			current_link_up = 1;
			goto out;
		}
restart_autoneg:
L
Linus Torvalds 已提交
3666 3667
		if (workaround)
			tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3668
		tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
L
Linus Torvalds 已提交
3669 3670 3671
		udelay(5);
		tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);

M
Michael Chan 已提交
3672 3673
		tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
		tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
L
Linus Torvalds 已提交
3674 3675
	} else if (mac_status & (MAC_STATUS_PCS_SYNCED |
				 MAC_STATUS_SIGNAL_DET)) {
M
Michael Chan 已提交
3676
		sg_dig_status = tr32(SG_DIG_STATUS);
L
Linus Torvalds 已提交
3677 3678
		mac_status = tr32(MAC_STATUS);

3679
		if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
L
Linus Torvalds 已提交
3680
		    (mac_status & MAC_STATUS_PCS_SYNCED)) {
3681 3682 3683 3684 3685 3686
			u32 local_adv = 0, remote_adv = 0;

			if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
				local_adv |= ADVERTISE_1000XPAUSE;
			if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
				local_adv |= ADVERTISE_1000XPSE_ASYM;
L
Linus Torvalds 已提交
3687

3688
			if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3689
				remote_adv |= LPA_1000XPAUSE;
3690
			if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3691
				remote_adv |= LPA_1000XPAUSE_ASYM;
L
Linus Torvalds 已提交
3692 3693 3694

			tg3_setup_flow_control(tp, local_adv, remote_adv);
			current_link_up = 1;
M
Michael Chan 已提交
3695 3696
			tp->serdes_counter = 0;
			tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3697
		} else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
M
Michael Chan 已提交
3698 3699
			if (tp->serdes_counter)
				tp->serdes_counter--;
L
Linus Torvalds 已提交
3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711
			else {
				if (workaround) {
					u32 val = serdes_cfg;

					if (port_a)
						val |= 0xc010000;
					else
						val |= 0x4010000;

					tw32_f(MAC_SERDES_CFG, val);
				}

3712
				tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
L
Linus Torvalds 已提交
3713 3714 3715 3716 3717 3718 3719 3720 3721 3722
				udelay(40);

				/* Link parallel detection - link is up */
				/* only if we have PCS_SYNC and not */
				/* receiving config code words */
				mac_status = tr32(MAC_STATUS);
				if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
				    !(mac_status & MAC_STATUS_RCVD_CFG)) {
					tg3_setup_flow_control(tp, 0, 0);
					current_link_up = 1;
M
Michael Chan 已提交
3723 3724 3725 3726 3727 3728
					tp->tg3_flags2 |=
						TG3_FLG2_PARALLEL_DETECT;
					tp->serdes_counter =
						SERDES_PARALLEL_DET_TIMEOUT;
				} else
					goto restart_autoneg;
L
Linus Torvalds 已提交
3729 3730
			}
		}
M
Michael Chan 已提交
3731 3732 3733
	} else {
		tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
		tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
L
Linus Torvalds 已提交
3734 3735 3736 3737 3738 3739 3740 3741 3742 3743
	}

out:
	return current_link_up;
}

static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
{
	int current_link_up = 0;

3744
	if (!(mac_status & MAC_STATUS_PCS_SYNCED))
L
Linus Torvalds 已提交
3745 3746 3747
		goto out;

	if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3748
		u32 txflags, rxflags;
L
Linus Torvalds 已提交
3749
		int i;
3750

3751 3752
		if (fiber_autoneg(tp, &txflags, &rxflags)) {
			u32 local_adv = 0, remote_adv = 0;
L
Linus Torvalds 已提交
3753

3754 3755 3756 3757 3758 3759 3760 3761 3762
			if (txflags & ANEG_CFG_PS1)
				local_adv |= ADVERTISE_1000XPAUSE;
			if (txflags & ANEG_CFG_PS2)
				local_adv |= ADVERTISE_1000XPSE_ASYM;

			if (rxflags & MR_LP_ADV_SYM_PAUSE)
				remote_adv |= LPA_1000XPAUSE;
			if (rxflags & MR_LP_ADV_ASYM_PAUSE)
				remote_adv |= LPA_1000XPAUSE_ASYM;
L
Linus Torvalds 已提交
3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785

			tg3_setup_flow_control(tp, local_adv, remote_adv);

			current_link_up = 1;
		}
		for (i = 0; i < 30; i++) {
			udelay(20);
			tw32_f(MAC_STATUS,
			       (MAC_STATUS_SYNC_CHANGED |
				MAC_STATUS_CFG_CHANGED));
			udelay(40);
			if ((tr32(MAC_STATUS) &
			     (MAC_STATUS_SYNC_CHANGED |
			      MAC_STATUS_CFG_CHANGED)) == 0)
				break;
		}

		mac_status = tr32(MAC_STATUS);
		if (current_link_up == 0 &&
		    (mac_status & MAC_STATUS_PCS_SYNCED) &&
		    !(mac_status & MAC_STATUS_RCVD_CFG))
			current_link_up = 1;
	} else {
3786 3787
		tg3_setup_flow_control(tp, 0, 0);

L
Linus Torvalds 已提交
3788 3789 3790 3791 3792
		/* Forcing 1000FD link up. */
		current_link_up = 1;

		tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
		udelay(40);
M
Matt Carlson 已提交
3793 3794 3795

		tw32_f(MAC_MODE, tp->mac_mode);
		udelay(40);
L
Linus Torvalds 已提交
3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810
	}

out:
	return current_link_up;
}

static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
{
	u32 orig_pause_cfg;
	u16 orig_active_speed;
	u8 orig_active_duplex;
	u32 mac_status;
	int current_link_up;
	int i;

3811
	orig_pause_cfg = tp->link_config.active_flowctrl;
L
Linus Torvalds 已提交
3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861
	orig_active_speed = tp->link_config.active_speed;
	orig_active_duplex = tp->link_config.active_duplex;

	if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
	    netif_carrier_ok(tp->dev) &&
	    (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
		mac_status = tr32(MAC_STATUS);
		mac_status &= (MAC_STATUS_PCS_SYNCED |
			       MAC_STATUS_SIGNAL_DET |
			       MAC_STATUS_CFG_CHANGED |
			       MAC_STATUS_RCVD_CFG);
		if (mac_status == (MAC_STATUS_PCS_SYNCED |
				   MAC_STATUS_SIGNAL_DET)) {
			tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
					    MAC_STATUS_CFG_CHANGED));
			return 0;
		}
	}

	tw32_f(MAC_TX_AUTO_NEG, 0);

	tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
	tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
	tw32_f(MAC_MODE, tp->mac_mode);
	udelay(40);

	if (tp->phy_id == PHY_ID_BCM8002)
		tg3_init_bcm8002(tp);

	/* Enable link change event even when serdes polling.  */
	tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
	udelay(40);

	current_link_up = 0;
	mac_status = tr32(MAC_STATUS);

	if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
		current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
	else
		current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);

	tp->hw_status->status =
		(SD_STATUS_UPDATED |
		 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));

	for (i = 0; i < 100; i++) {
		tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
				    MAC_STATUS_CFG_CHANGED));
		udelay(5);
		if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
M
Michael Chan 已提交
3862 3863
					 MAC_STATUS_CFG_CHANGED |
					 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
L
Linus Torvalds 已提交
3864 3865 3866 3867 3868 3869
			break;
	}

	mac_status = tr32(MAC_STATUS);
	if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
		current_link_up = 0;
M
Michael Chan 已提交
3870 3871
		if (tp->link_config.autoneg == AUTONEG_ENABLE &&
		    tp->serdes_counter == 0) {
L
Linus Torvalds 已提交
3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899
			tw32_f(MAC_MODE, (tp->mac_mode |
					  MAC_MODE_SEND_CONFIGS));
			udelay(1);
			tw32_f(MAC_MODE, tp->mac_mode);
		}
	}

	if (current_link_up == 1) {
		tp->link_config.active_speed = SPEED_1000;
		tp->link_config.active_duplex = DUPLEX_FULL;
		tw32(MAC_LED_CTRL, (tp->led_ctrl |
				    LED_CTRL_LNKLED_OVERRIDE |
				    LED_CTRL_1000MBPS_ON));
	} else {
		tp->link_config.active_speed = SPEED_INVALID;
		tp->link_config.active_duplex = DUPLEX_INVALID;
		tw32(MAC_LED_CTRL, (tp->led_ctrl |
				    LED_CTRL_LNKLED_OVERRIDE |
				    LED_CTRL_TRAFFIC_OVERRIDE));
	}

	if (current_link_up != netif_carrier_ok(tp->dev)) {
		if (current_link_up)
			netif_carrier_on(tp->dev);
		else
			netif_carrier_off(tp->dev);
		tg3_link_report(tp);
	} else {
3900
		u32 now_pause_cfg = tp->link_config.active_flowctrl;
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Linus Torvalds 已提交
3901 3902 3903 3904 3905 3906 3907 3908 3909
		if (orig_pause_cfg != now_pause_cfg ||
		    orig_active_speed != tp->link_config.active_speed ||
		    orig_active_duplex != tp->link_config.active_duplex)
			tg3_link_report(tp);
	}

	return 0;
}

M
Michael Chan 已提交
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static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
{
	int current_link_up, err = 0;
	u32 bmsr, bmcr;
	u16 current_speed;
	u8 current_duplex;
3916
	u32 local_adv, remote_adv;
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Michael Chan 已提交
3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939

	tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
	tw32_f(MAC_MODE, tp->mac_mode);
	udelay(40);

	tw32(MAC_EVENT, 0);

	tw32_f(MAC_STATUS,
	     (MAC_STATUS_SYNC_CHANGED |
	      MAC_STATUS_CFG_CHANGED |
	      MAC_STATUS_MI_COMPLETION |
	      MAC_STATUS_LNKSTATE_CHANGED));
	udelay(40);

	if (force_reset)
		tg3_phy_reset(tp);

	current_link_up = 0;
	current_speed = SPEED_INVALID;
	current_duplex = DUPLEX_INVALID;

	err |= tg3_readphy(tp, MII_BMSR, &bmsr);
	err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3940 3941 3942 3943 3944 3945
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
		if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
			bmsr |= BMSR_LSTATUS;
		else
			bmsr &= ~BMSR_LSTATUS;
	}
M
Michael Chan 已提交
3946 3947 3948 3949

	err |= tg3_readphy(tp, MII_BMCR, &bmcr);

	if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3950
	    (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
M
Michael Chan 已提交
3951 3952 3953 3954 3955 3956 3957 3958 3959 3960
		/* do nothing, just check for link up at the end */
	} else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
		u32 adv, new_adv;

		err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
		new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
				  ADVERTISE_1000XPAUSE |
				  ADVERTISE_1000XPSE_ASYM |
				  ADVERTISE_SLCT);

3961
		new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
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Michael Chan 已提交
3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973

		if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
			new_adv |= ADVERTISE_1000XHALF;
		if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
			new_adv |= ADVERTISE_1000XFULL;

		if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
			tg3_writephy(tp, MII_ADVERTISE, new_adv);
			bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
			tg3_writephy(tp, MII_BMCR, bmcr);

			tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
M
Michael Chan 已提交
3974
			tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
M
Michael Chan 已提交
3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012
			tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;

			return err;
		}
	} else {
		u32 new_bmcr;

		bmcr &= ~BMCR_SPEED1000;
		new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);

		if (tp->link_config.duplex == DUPLEX_FULL)
			new_bmcr |= BMCR_FULLDPLX;

		if (new_bmcr != bmcr) {
			/* BMCR_SPEED1000 is a reserved bit that needs
			 * to be set on write.
			 */
			new_bmcr |= BMCR_SPEED1000;

			/* Force a linkdown */
			if (netif_carrier_ok(tp->dev)) {
				u32 adv;

				err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
				adv &= ~(ADVERTISE_1000XFULL |
					 ADVERTISE_1000XHALF |
					 ADVERTISE_SLCT);
				tg3_writephy(tp, MII_ADVERTISE, adv);
				tg3_writephy(tp, MII_BMCR, bmcr |
							   BMCR_ANRESTART |
							   BMCR_ANENABLE);
				udelay(10);
				netif_carrier_off(tp->dev);
			}
			tg3_writephy(tp, MII_BMCR, new_bmcr);
			bmcr = new_bmcr;
			err |= tg3_readphy(tp, MII_BMSR, &bmsr);
			err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4013 4014 4015 4016 4017 4018 4019
			if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
			    ASIC_REV_5714) {
				if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
					bmsr |= BMSR_LSTATUS;
				else
					bmsr &= ~BMSR_LSTATUS;
			}
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Michael Chan 已提交
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			tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
		}
	}

	if (bmsr & BMSR_LSTATUS) {
		current_speed = SPEED_1000;
		current_link_up = 1;
		if (bmcr & BMCR_FULLDPLX)
			current_duplex = DUPLEX_FULL;
		else
			current_duplex = DUPLEX_HALF;

4032 4033 4034
		local_adv = 0;
		remote_adv = 0;

M
Michael Chan 已提交
4035
		if (bmcr & BMCR_ANENABLE) {
4036
			u32 common;
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Michael Chan 已提交
4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052

			err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
			err |= tg3_readphy(tp, MII_LPA, &remote_adv);
			common = local_adv & remote_adv;
			if (common & (ADVERTISE_1000XHALF |
				      ADVERTISE_1000XFULL)) {
				if (common & ADVERTISE_1000XFULL)
					current_duplex = DUPLEX_FULL;
				else
					current_duplex = DUPLEX_HALF;
			}
			else
				current_link_up = 0;
		}
	}

4053 4054 4055
	if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
		tg3_setup_flow_control(tp, local_adv, remote_adv);

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Michael Chan 已提交
4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081
	tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
	if (tp->link_config.active_duplex == DUPLEX_HALF)
		tp->mac_mode |= MAC_MODE_HALF_DUPLEX;

	tw32_f(MAC_MODE, tp->mac_mode);
	udelay(40);

	tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);

	tp->link_config.active_speed = current_speed;
	tp->link_config.active_duplex = current_duplex;

	if (current_link_up != netif_carrier_ok(tp->dev)) {
		if (current_link_up)
			netif_carrier_on(tp->dev);
		else {
			netif_carrier_off(tp->dev);
			tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
		}
		tg3_link_report(tp);
	}
	return err;
}

static void tg3_serdes_parallel_detect(struct tg3 *tp)
{
M
Michael Chan 已提交
4082
	if (tp->serdes_counter) {
M
Michael Chan 已提交
4083
		/* Give autoneg time to complete. */
M
Michael Chan 已提交
4084
		tp->serdes_counter--;
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		return;
	}
	if (!netif_carrier_ok(tp->dev) &&
	    (tp->link_config.autoneg == AUTONEG_ENABLE)) {
		u32 bmcr;

		tg3_readphy(tp, MII_BMCR, &bmcr);
		if (bmcr & BMCR_ANENABLE) {
			u32 phy1, phy2;

			/* Select shadow register 0x1f */
			tg3_writephy(tp, 0x1c, 0x7c00);
			tg3_readphy(tp, 0x1c, &phy1);

			/* Select expansion interrupt status register */
			tg3_writephy(tp, 0x17, 0x0f01);
			tg3_readphy(tp, 0x15, &phy2);
			tg3_readphy(tp, 0x15, &phy2);

			if ((phy1 & 0x10) && !(phy2 & 0x20)) {
				/* We have signal detect and not receiving
				 * config code words, link is up by parallel
				 * detection.
				 */

				bmcr &= ~BMCR_ANENABLE;
				bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
				tg3_writephy(tp, MII_BMCR, bmcr);
				tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
			}
		}
	}
	else if (netif_carrier_ok(tp->dev) &&
		 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
		 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
		u32 phy2;

		/* Select expansion interrupt status register */
		tg3_writephy(tp, 0x17, 0x0f01);
		tg3_readphy(tp, 0x15, &phy2);
		if (phy2 & 0x20) {
			u32 bmcr;

			/* Config code words received, turn on autoneg. */
			tg3_readphy(tp, MII_BMCR, &bmcr);
			tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);

			tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;

		}
	}
}

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Linus Torvalds 已提交
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static int tg3_setup_phy(struct tg3 *tp, int force_reset)
{
	int err;

	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
		err = tg3_setup_fiber_phy(tp, force_reset);
M
Michael Chan 已提交
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	} else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
		err = tg3_setup_fiber_mii_phy(tp, force_reset);
L
Linus Torvalds 已提交
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	} else {
		err = tg3_setup_copper_phy(tp, force_reset);
	}

4150
	if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
M
Matt Carlson 已提交
4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165
		u32 val, scale;

		val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
		if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
			scale = 65;
		else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
			scale = 6;
		else
			scale = 12;

		val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
		val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
		tw32(GRC_MISC_CFG, val);
	}

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Linus Torvalds 已提交
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	if (tp->link_config.active_speed == SPEED_1000 &&
	    tp->link_config.active_duplex == DUPLEX_HALF)
		tw32(MAC_TX_LENGTHS,
		     ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
		      (6 << TX_LENGTHS_IPG_SHIFT) |
		      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
	else
		tw32(MAC_TX_LENGTHS,
		     ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
		      (6 << TX_LENGTHS_IPG_SHIFT) |
		      (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));

	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
		if (netif_carrier_ok(tp->dev)) {
			tw32(HOSTCC_STAT_COAL_TICKS,
4181
			     tp->coal.stats_block_coalesce_usecs);
L
Linus Torvalds 已提交
4182 4183 4184 4185 4186
		} else {
			tw32(HOSTCC_STAT_COAL_TICKS, 0);
		}
	}

M
Matt Carlson 已提交
4187 4188 4189 4190 4191 4192 4193 4194 4195 4196
	if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
		u32 val = tr32(PCIE_PWR_MGMT_THRESH);
		if (!netif_carrier_ok(tp->dev))
			val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
			      tp->pwrmgmt_thresh;
		else
			val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
		tw32(PCIE_PWR_MGMT_THRESH, val);
	}

L
Linus Torvalds 已提交
4197 4198 4199
	return err;
}

4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220
/* This is called whenever we suspect that the system chipset is re-
 * ordering the sequence of MMIO to the tx send mailbox. The symptom
 * is bogus tx completions. We try to recover by setting the
 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
 * in the workqueue.
 */
static void tg3_tx_recover(struct tg3 *tp)
{
	BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
	       tp->write32_tx_mbox == tg3_write_indirect_mbox);

	printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
	       "mapped I/O cycles to the network device, attempting to "
	       "recover. Please report the problem to the driver maintainer "
	       "and include system chipset information.\n", tp->dev->name);

	spin_lock(&tp->lock);
	tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
	spin_unlock(&tp->lock);
}

M
Michael Chan 已提交
4221 4222 4223 4224 4225 4226 4227
static inline u32 tg3_tx_avail(struct tg3 *tp)
{
	smp_mb();
	return (tp->tx_pending -
		((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
}

L
Linus Torvalds 已提交
4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239
/* Tigon3 never reports partial packet sends.  So we do not
 * need special logic to handle SKBs that have not had all
 * of their frags sent yet, like SunGEM does.
 */
static void tg3_tx(struct tg3 *tp)
{
	u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
	u32 sw_idx = tp->tx_cons;

	while (sw_idx != hw_idx) {
		struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
		struct sk_buff *skb = ri->skb;
4240 4241 4242 4243 4244 4245
		int i, tx_bug = 0;

		if (unlikely(skb == NULL)) {
			tg3_tx_recover(tp);
			return;
		}
L
Linus Torvalds 已提交
4246

4247
		skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
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Linus Torvalds 已提交
4248 4249 4250 4251 4252 4253 4254

		ri->skb = NULL;

		sw_idx = NEXT_TX(sw_idx);

		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
			ri = &tp->tx_buffers[sw_idx];
4255 4256
			if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
				tx_bug = 1;
L
Linus Torvalds 已提交
4257 4258 4259
			sw_idx = NEXT_TX(sw_idx);
		}

4260
		dev_kfree_skb(skb);
4261 4262 4263 4264 4265

		if (unlikely(tx_bug)) {
			tg3_tx_recover(tp);
			return;
		}
L
Linus Torvalds 已提交
4266 4267 4268 4269
	}

	tp->tx_cons = sw_idx;

M
Michael Chan 已提交
4270 4271 4272 4273 4274 4275 4276 4277
	/* Need to make the tx_cons update visible to tg3_start_xmit()
	 * before checking for netif_queue_stopped().  Without the
	 * memory barrier, there is a small possibility that tg3_start_xmit()
	 * will miss it and cause the queue to be stopped forever.
	 */
	smp_mb();

	if (unlikely(netif_queue_stopped(tp->dev) &&
4278
		     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
M
Michael Chan 已提交
4279
		netif_tx_lock(tp->dev);
4280
		if (netif_queue_stopped(tp->dev) &&
4281
		    (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4282
			netif_wake_queue(tp->dev);
M
Michael Chan 已提交
4283
		netif_tx_unlock(tp->dev);
4284
	}
L
Linus Torvalds 已提交
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}

/* Returns size of skb allocated or < 0 on error.
 *
 * We only need to fill in the address because the other members
 * of the RX descriptor are invariant, see tg3_init_rings.
 *
 * Note the purposeful assymetry of cpu vs. chip accesses.  For
 * posting buffers we only dirty the first cache line of the RX
 * descriptor (containing the address).  Whereas for the RX status
 * buffers the cpu only reads the last cacheline of the RX descriptor
 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
 */
static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
			    int src_idx, u32 dest_idx_unmasked)
{
	struct tg3_rx_buffer_desc *desc;
	struct ring_info *map, *src_map;
	struct sk_buff *skb;
	dma_addr_t mapping;
	int skb_size, dest_idx;

	src_map = NULL;
	switch (opaque_key) {
	case RXD_OPAQUE_RING_STD:
		dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
		desc = &tp->rx_std[dest_idx];
		map = &tp->rx_std_buffers[dest_idx];
		if (src_idx >= 0)
			src_map = &tp->rx_std_buffers[src_idx];
4315
		skb_size = tp->rx_pkt_buf_sz;
L
Linus Torvalds 已提交
4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328
		break;

	case RXD_OPAQUE_RING_JUMBO:
		dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
		desc = &tp->rx_jumbo[dest_idx];
		map = &tp->rx_jumbo_buffers[dest_idx];
		if (src_idx >= 0)
			src_map = &tp->rx_jumbo_buffers[src_idx];
		skb_size = RX_JUMBO_PKT_BUF_SZ;
		break;

	default:
		return -EINVAL;
4329
	}
L
Linus Torvalds 已提交
4330 4331 4332 4333 4334 4335 4336

	/* Do not overwrite any of the map or rp information
	 * until we are sure we can commit to a new buffer.
	 *
	 * Callers depend upon this behavior and assume that
	 * we leave everything unchanged if we fail.
	 */
4337
	skb = netdev_alloc_skb(tp->dev, skb_size);
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Linus Torvalds 已提交
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	if (skb == NULL)
		return -ENOMEM;

	skb_reserve(skb, tp->rx_offset);

	mapping = pci_map_single(tp->pdev, skb->data,
				 skb_size - tp->rx_offset,
				 PCI_DMA_FROMDEVICE);

	map->skb = skb;
	pci_unmap_addr_set(map, mapping, mapping);

	if (src_map != NULL)
		src_map->skb = NULL;

	desc->addr_hi = ((u64)mapping >> 32);
	desc->addr_lo = ((u64)mapping & 0xffffffff);

	return skb_size;
}

/* We only need to move over in the address because the other
 * members of the RX descriptor are invariant.  See notes above
 * tg3_alloc_rx_skb for full details.
 */
static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
			   int src_idx, u32 dest_idx_unmasked)
{
	struct tg3_rx_buffer_desc *src_desc, *dest_desc;
	struct ring_info *src_map, *dest_map;
	int dest_idx;

	switch (opaque_key) {
	case RXD_OPAQUE_RING_STD:
		dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
		dest_desc = &tp->rx_std[dest_idx];
		dest_map = &tp->rx_std_buffers[dest_idx];
		src_desc = &tp->rx_std[src_idx];
		src_map = &tp->rx_std_buffers[src_idx];
		break;

	case RXD_OPAQUE_RING_JUMBO:
		dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
		dest_desc = &tp->rx_jumbo[dest_idx];
		dest_map = &tp->rx_jumbo_buffers[dest_idx];
		src_desc = &tp->rx_jumbo[src_idx];
		src_map = &tp->rx_jumbo_buffers[src_idx];
		break;

	default:
		return;
4389
	}
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Linus Torvalds 已提交
4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402

	dest_map->skb = src_map->skb;
	pci_unmap_addr_set(dest_map, mapping,
			   pci_unmap_addr(src_map, mapping));
	dest_desc->addr_hi = src_desc->addr_hi;
	dest_desc->addr_lo = src_desc->addr_lo;

	src_map->skb = NULL;
}

#if TG3_VLAN_TAG_USED
static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
{
D
David S. Miller 已提交
4403
	return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
L
Linus Torvalds 已提交
4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432
}
#endif

/* The RX ring scheme is composed of multiple rings which post fresh
 * buffers to the chip, and one special ring the chip uses to report
 * status back to the host.
 *
 * The special ring reports the status of received packets to the
 * host.  The chip does not write into the original descriptor the
 * RX buffer was obtained from.  The chip simply takes the original
 * descriptor as provided by the host, updates the status and length
 * field, then writes this into the next status ring entry.
 *
 * Each ring the host uses to post buffers to the chip is described
 * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
 * it is first placed into the on-chip ram.  When the packet's length
 * is known, it walks down the TG3_BDINFO entries to select the ring.
 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
 * which is within the range of the new packet's length is chosen.
 *
 * The "separate ring for rx status" scheme may sound queer, but it makes
 * sense from a cache coherency perspective.  If only the host writes
 * to the buffer post rings, and only the chip writes to the rx status
 * rings, then cache lines never move beyond shared-modified state.
 * If both the host and chip were to write into the same ring, cache line
 * eviction could occur since both entities want it in an exclusive state.
 */
static int tg3_rx(struct tg3 *tp, int budget)
{
M
Michael Chan 已提交
4433
	u32 work_mask, rx_std_posted = 0;
M
Michael Chan 已提交
4434 4435
	u32 sw_idx = tp->rx_rcb_ptr;
	u16 hw_idx;
L
Linus Torvalds 已提交
4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459
	int received;

	hw_idx = tp->hw_status->idx[0].rx_producer;
	/*
	 * We need to order the read of hw_idx and the read of
	 * the opaque cookie.
	 */
	rmb();
	work_mask = 0;
	received = 0;
	while (sw_idx != hw_idx && budget > 0) {
		struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
		unsigned int len;
		struct sk_buff *skb;
		dma_addr_t dma_addr;
		u32 opaque_key, desc_idx, *post_ptr;

		desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
		opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
		if (opaque_key == RXD_OPAQUE_RING_STD) {
			dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
						  mapping);
			skb = tp->rx_std_buffers[desc_idx].skb;
			post_ptr = &tp->rx_std_ptr;
M
Michael Chan 已提交
4460
			rx_std_posted++;
L
Linus Torvalds 已提交
4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483
		} else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
			dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
						  mapping);
			skb = tp->rx_jumbo_buffers[desc_idx].skb;
			post_ptr = &tp->rx_jumbo_ptr;
		}
		else {
			goto next_pkt_nopost;
		}

		work_mask |= opaque_key;

		if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
		    (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
		drop_it:
			tg3_recycle_rx(tp, opaque_key,
				       desc_idx, *post_ptr);
		drop_it_no_recycle:
			/* Other statistics kept track of by card. */
			tp->net_stats.rx_dropped++;
			goto next_pkt;
		}

M
Matt Carlson 已提交
4484 4485
		len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
		      ETH_FCS_LEN;
L
Linus Torvalds 已提交
4486

4487
		if (len > RX_COPY_THRESHOLD
M
Matt Carlson 已提交
4488 4489 4490 4491 4492
			&& tp->rx_offset == NET_IP_ALIGN
			/* rx_offset will likely not equal NET_IP_ALIGN
			 * if this is a 5701 card running in PCI-X mode
			 * [see tg3_get_invariants()]
			 */
L
Linus Torvalds 已提交
4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511
		) {
			int skb_size;

			skb_size = tg3_alloc_rx_skb(tp, opaque_key,
						    desc_idx, *post_ptr);
			if (skb_size < 0)
				goto drop_it;

			pci_unmap_single(tp->pdev, dma_addr,
					 skb_size - tp->rx_offset,
					 PCI_DMA_FROMDEVICE);

			skb_put(skb, len);
		} else {
			struct sk_buff *copy_skb;

			tg3_recycle_rx(tp, opaque_key,
				       desc_idx, *post_ptr);

M
Matt Carlson 已提交
4512 4513
			copy_skb = netdev_alloc_skb(tp->dev,
						    len + TG3_RAW_IP_ALIGN);
L
Linus Torvalds 已提交
4514 4515 4516
			if (copy_skb == NULL)
				goto drop_it_no_recycle;

M
Matt Carlson 已提交
4517
			skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
L
Linus Torvalds 已提交
4518 4519
			skb_put(copy_skb, len);
			pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4520
			skb_copy_from_linear_data(skb, copy_skb->data, len);
L
Linus Torvalds 已提交
4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535
			pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);

			/* We'll reuse the original ring buffer. */
			skb = copy_skb;
		}

		if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
		    (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
		    (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
		      >> RXD_TCPCSUM_SHIFT) == 0xffff))
			skb->ip_summed = CHECKSUM_UNNECESSARY;
		else
			skb->ip_summed = CHECKSUM_NONE;

		skb->protocol = eth_type_trans(skb, tp->dev);
4536 4537 4538 4539 4540 4541 4542

		if (len > (tp->dev->mtu + ETH_HLEN) &&
		    skb->protocol != htons(ETH_P_8021Q)) {
			dev_kfree_skb(skb);
			goto next_pkt;
		}

L
Linus Torvalds 已提交
4543 4544 4545 4546 4547 4548 4549
#if TG3_VLAN_TAG_USED
		if (tp->vlgrp != NULL &&
		    desc->type_flags & RXD_FLAG_VLAN) {
			tg3_vlan_rx(tp, skb,
				    desc->err_vlan & RXD_VLAN_MASK);
		} else
#endif
D
David S. Miller 已提交
4550
			napi_gro_receive(&tp->napi, skb);
L
Linus Torvalds 已提交
4551 4552 4553 4554 4555 4556

		received++;
		budget--;

next_pkt:
		(*post_ptr)++;
M
Michael Chan 已提交
4557 4558 4559 4560 4561 4562 4563 4564 4565

		if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
			u32 idx = *post_ptr % TG3_RX_RING_SIZE;

			tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
				     TG3_64BIT_REG_LOW, idx);
			work_mask &= ~RXD_OPAQUE_RING_STD;
			rx_std_posted = 0;
		}
L
Linus Torvalds 已提交
4566
next_pkt_nopost:
M
Michael Chan 已提交
4567
		sw_idx++;
E
Eric Dumazet 已提交
4568
		sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4569 4570 4571 4572 4573 4574

		/* Refresh hw_idx to see if there is new work */
		if (sw_idx == hw_idx) {
			hw_idx = tp->hw_status->idx[0].rx_producer;
			rmb();
		}
L
Linus Torvalds 已提交
4575 4576 4577
	}

	/* ACK the status ring. */
M
Michael Chan 已提交
4578 4579
	tp->rx_rcb_ptr = sw_idx;
	tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
L
Linus Torvalds 已提交
4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596

	/* Refill RX ring(s). */
	if (work_mask & RXD_OPAQUE_RING_STD) {
		sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
		tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
			     sw_idx);
	}
	if (work_mask & RXD_OPAQUE_RING_JUMBO) {
		sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
		tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
			     sw_idx);
	}
	mmiowb();

	return received;
}

4597
static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
L
Linus Torvalds 已提交
4598 4599 4600 4601 4602 4603 4604 4605 4606 4607
{
	struct tg3_hw_status *sblk = tp->hw_status;

	/* handle link change and other phy events */
	if (!(tp->tg3_flags &
	      (TG3_FLAG_USE_LINKCHG_REG |
	       TG3_FLAG_POLL_SERDES))) {
		if (sblk->status & SD_STATUS_LINK_CHG) {
			sblk->status = SD_STATUS_UPDATED |
				(sblk->status & ~SD_STATUS_LINK_CHG);
4608
			spin_lock(&tp->lock);
M
Matt Carlson 已提交
4609 4610 4611 4612 4613 4614 4615 4616 4617
			if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
				tw32_f(MAC_STATUS,
				     (MAC_STATUS_SYNC_CHANGED |
				      MAC_STATUS_CFG_CHANGED |
				      MAC_STATUS_MI_COMPLETION |
				      MAC_STATUS_LNKSTATE_CHANGED));
				udelay(40);
			} else
				tg3_setup_phy(tp, 0);
4618
			spin_unlock(&tp->lock);
L
Linus Torvalds 已提交
4619 4620 4621 4622 4623 4624
		}
	}

	/* run TX completion thread */
	if (sblk->idx[0].tx_consumer != tp->tx_cons) {
		tg3_tx(tp);
4625
		if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
M
Michael Chan 已提交
4626
			return work_done;
L
Linus Torvalds 已提交
4627 4628 4629 4630
	}

	/* run RX thread, within the bounds set by NAPI.
	 * All RX "locking" is done by ensuring outside
4631
	 * code synchronizes with tg3->napi.poll()
L
Linus Torvalds 已提交
4632
	 */
4633
	if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4634
		work_done += tg3_rx(tp, budget - work_done);
L
Linus Torvalds 已提交
4635

4636 4637 4638 4639 4640 4641 4642
	return work_done;
}

static int tg3_poll(struct napi_struct *napi, int budget)
{
	struct tg3 *tp = container_of(napi, struct tg3, napi);
	int work_done = 0;
M
Michael Chan 已提交
4643
	struct tg3_hw_status *sblk = tp->hw_status;
4644 4645 4646 4647 4648 4649 4650 4651 4652 4653

	while (1) {
		work_done = tg3_poll_work(tp, work_done, budget);

		if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
			goto tx_recovery;

		if (unlikely(work_done >= budget))
			break;

M
Michael Chan 已提交
4654 4655 4656 4657 4658 4659
		if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
			/* tp->last_tag is used in tg3_restart_ints() below
			 * to tell the hw how much work has been processed,
			 * so we must read it before checking for more work.
			 */
			tp->last_tag = sblk->status_tag;
4660
			tp->last_irq_tag = tp->last_tag;
M
Michael Chan 已提交
4661 4662 4663
			rmb();
		} else
			sblk->status &= ~SD_STATUS_UPDATED;
4664

M
Michael Chan 已提交
4665
		if (likely(!tg3_has_work(tp))) {
4666
			napi_complete(napi);
4667 4668 4669
			tg3_restart_ints(tp);
			break;
		}
L
Linus Torvalds 已提交
4670 4671
	}

4672
	return work_done;
4673 4674

tx_recovery:
M
Michael Chan 已提交
4675
	/* work_done is guaranteed to be less than budget. */
4676
	napi_complete(napi);
4677
	schedule_work(&tp->reset_task);
M
Michael Chan 已提交
4678
	return work_done;
L
Linus Torvalds 已提交
4679 4680
}

4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702
static void tg3_irq_quiesce(struct tg3 *tp)
{
	BUG_ON(tp->irq_sync);

	tp->irq_sync = 1;
	smp_mb();

	synchronize_irq(tp->pdev->irq);
}

static inline int tg3_irq_sync(struct tg3 *tp)
{
	return tp->irq_sync;
}

/* Fully shutdown all tg3 driver activity elsewhere in the system.
 * If irq_sync is non-zero, then the IRQ handler must be synchronized
 * with as well.  Most of the time, this is not necessary except when
 * shutting down the device.
 */
static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
{
4703
	spin_lock_bh(&tp->lock);
4704 4705 4706 4707 4708 4709 4710 4711 4712
	if (irq_sync)
		tg3_irq_quiesce(tp);
}

static inline void tg3_full_unlock(struct tg3 *tp)
{
	spin_unlock_bh(&tp->lock);
}

4713 4714 4715
/* One-shot MSI handler - Chip automatically disables interrupt
 * after sending MSI so driver doesn't have to do it.
 */
4716
static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4717 4718 4719 4720 4721 4722 4723 4724
{
	struct net_device *dev = dev_id;
	struct tg3 *tp = netdev_priv(dev);

	prefetch(tp->hw_status);
	prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);

	if (likely(!tg3_irq_sync(tp)))
4725
		napi_schedule(&tp->napi);
4726 4727 4728 4729

	return IRQ_HANDLED;
}

M
Michael Chan 已提交
4730 4731 4732 4733
/* MSI ISR - No need to check for interrupt sharing and no need to
 * flush status block and interrupt mailbox. PCI ordering rules
 * guarantee that MSI will arrive after the status block.
 */
4734
static irqreturn_t tg3_msi(int irq, void *dev_id)
M
Michael Chan 已提交
4735 4736 4737 4738
{
	struct net_device *dev = dev_id;
	struct tg3 *tp = netdev_priv(dev);

4739 4740
	prefetch(tp->hw_status);
	prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
M
Michael Chan 已提交
4741
	/*
4742
	 * Writing any value to intr-mbox-0 clears PCI INTA# and
M
Michael Chan 已提交
4743
	 * chip-internal interrupt pending events.
4744
	 * Writing non-zero to intr-mbox-0 additional tells the
M
Michael Chan 已提交
4745 4746 4747 4748
	 * NIC to stop sending us irqs, engaging "in-intr-handler"
	 * event coalescing.
	 */
	tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4749
	if (likely(!tg3_irq_sync(tp)))
4750
		napi_schedule(&tp->napi);
4751

M
Michael Chan 已提交
4752 4753 4754
	return IRQ_RETVAL(1);
}

4755
static irqreturn_t tg3_interrupt(int irq, void *dev_id)
L
Linus Torvalds 已提交
4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766
{
	struct net_device *dev = dev_id;
	struct tg3 *tp = netdev_priv(dev);
	struct tg3_hw_status *sblk = tp->hw_status;
	unsigned int handled = 1;

	/* In INTx mode, it is possible for the interrupt to arrive at
	 * the CPU before the status block posted prior to the interrupt.
	 * Reading the PCI State register will confirm whether the
	 * interrupt is ours and will flush the status block.
	 */
4767 4768 4769 4770
	if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
		if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
		    (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
			handled = 0;
4771
			goto out;
4772
		}
4773 4774 4775 4776 4777 4778 4779 4780
	}

	/*
	 * Writing any value to intr-mbox-0 clears PCI INTA# and
	 * chip-internal interrupt pending events.
	 * Writing non-zero to intr-mbox-0 additional tells the
	 * NIC to stop sending us irqs, engaging "in-intr-handler"
	 * event coalescing.
4781 4782 4783 4784
	 *
	 * Flush the mailbox to de-assert the IRQ immediately to prevent
	 * spurious interrupts.  The flush impacts performance but
	 * excessive spurious interrupts can be worse in some cases.
4785
	 */
4786
	tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4787 4788 4789 4790 4791
	if (tg3_irq_sync(tp))
		goto out;
	sblk->status &= ~SD_STATUS_UPDATED;
	if (likely(tg3_has_work(tp))) {
		prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4792
		napi_schedule(&tp->napi);
4793 4794 4795 4796 4797 4798
	} else {
		/* No work, shared interrupt perhaps?  re-enable
		 * interrupts, and flush that PCI write
		 */
		tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
			       0x00000000);
4799
	}
4800
out:
4801 4802 4803
	return IRQ_RETVAL(handled);
}

4804
static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815
{
	struct net_device *dev = dev_id;
	struct tg3 *tp = netdev_priv(dev);
	struct tg3_hw_status *sblk = tp->hw_status;
	unsigned int handled = 1;

	/* In INTx mode, it is possible for the interrupt to arrive at
	 * the CPU before the status block posted prior to the interrupt.
	 * Reading the PCI State register will confirm whether the
	 * interrupt is ours and will flush the status block.
	 */
4816
	if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
4817 4818 4819
		if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
		    (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
			handled = 0;
4820
			goto out;
L
Linus Torvalds 已提交
4821
		}
4822 4823 4824 4825 4826 4827 4828 4829
	}

	/*
	 * writing any value to intr-mbox-0 clears PCI INTA# and
	 * chip-internal interrupt pending events.
	 * writing non-zero to intr-mbox-0 additional tells the
	 * NIC to stop sending us irqs, engaging "in-intr-handler"
	 * event coalescing.
4830 4831 4832 4833
	 *
	 * Flush the mailbox to de-assert the IRQ immediately to prevent
	 * spurious interrupts.  The flush impacts performance but
	 * excessive spurious interrupts can be worse in some cases.
4834
	 */
4835
	tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4836 4837 4838 4839 4840 4841 4842 4843 4844

	/*
	 * In a shared interrupt configuration, sometimes other devices'
	 * interrupts will scream.  We record the current status tag here
	 * so that the above check can report that the screaming interrupts
	 * are unhandled.  Eventually they will be silenced.
	 */
	tp->last_irq_tag = sblk->status_tag;

4845 4846
	if (tg3_irq_sync(tp))
		goto out;
4847 4848 4849 4850 4851

	prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);

	napi_schedule(&tp->napi);

4852
out:
L
Linus Torvalds 已提交
4853 4854 4855
	return IRQ_RETVAL(handled);
}

M
Michael Chan 已提交
4856
/* ISR for interrupt test */
4857
static irqreturn_t tg3_test_isr(int irq, void *dev_id)
M
Michael Chan 已提交
4858 4859 4860 4861 4862
{
	struct net_device *dev = dev_id;
	struct tg3 *tp = netdev_priv(dev);
	struct tg3_hw_status *sblk = tp->hw_status;

M
Michael Chan 已提交
4863 4864
	if ((sblk->status & SD_STATUS_UPDATED) ||
	    !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4865
		tg3_disable_ints(tp);
M
Michael Chan 已提交
4866 4867 4868 4869 4870
		return IRQ_RETVAL(1);
	}
	return IRQ_RETVAL(0);
}

4871
static int tg3_init_hw(struct tg3 *, int);
M
Michael Chan 已提交
4872
static int tg3_halt(struct tg3 *, int, int);
L
Linus Torvalds 已提交
4873

M
Michael Chan 已提交
4874 4875 4876 4877
/* Restart hardware after configuration changes, self-test, etc.
 * Invoked with tp->lock held.
 */
static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
E
Eric Dumazet 已提交
4878 4879
	__releases(tp->lock)
	__acquires(tp->lock)
M
Michael Chan 已提交
4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890
{
	int err;

	err = tg3_init_hw(tp, reset_phy);
	if (err) {
		printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
		       "aborting.\n", tp->dev->name);
		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
		tg3_full_unlock(tp);
		del_timer_sync(&tp->timer);
		tp->irq_sync = 0;
4891
		napi_enable(&tp->napi);
M
Michael Chan 已提交
4892 4893 4894 4895 4896 4897
		dev_close(tp->dev);
		tg3_full_lock(tp, 0);
	}
	return err;
}

L
Linus Torvalds 已提交
4898 4899 4900
#ifdef CONFIG_NET_POLL_CONTROLLER
static void tg3_poll_controller(struct net_device *dev)
{
M
Michael Chan 已提交
4901 4902
	struct tg3 *tp = netdev_priv(dev);

4903
	tg3_interrupt(tp->pdev->irq, dev);
L
Linus Torvalds 已提交
4904 4905 4906
}
#endif

D
David Howells 已提交
4907
static void tg3_reset_task(struct work_struct *work)
L
Linus Torvalds 已提交
4908
{
D
David Howells 已提交
4909
	struct tg3 *tp = container_of(work, struct tg3, reset_task);
M
Matt Carlson 已提交
4910
	int err;
L
Linus Torvalds 已提交
4911 4912
	unsigned int restart_timer;

M
Michael Chan 已提交
4913 4914 4915 4916 4917 4918 4919 4920 4921
	tg3_full_lock(tp, 0);

	if (!netif_running(tp->dev)) {
		tg3_full_unlock(tp);
		return;
	}

	tg3_full_unlock(tp);

M
Matt Carlson 已提交
4922 4923
	tg3_phy_stop(tp);

L
Linus Torvalds 已提交
4924 4925
	tg3_netif_stop(tp);

4926
	tg3_full_lock(tp, 1);
L
Linus Torvalds 已提交
4927 4928 4929 4930

	restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
	tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;

4931 4932 4933 4934 4935 4936 4937
	if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
		tp->write32_tx_mbox = tg3_write32_tx_mbox;
		tp->write32_rx_mbox = tg3_write_flush_reg32;
		tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
		tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
	}

M
Michael Chan 已提交
4938
	tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
M
Matt Carlson 已提交
4939 4940
	err = tg3_init_hw(tp, 1);
	if (err)
M
Michael Chan 已提交
4941
		goto out;
L
Linus Torvalds 已提交
4942 4943 4944 4945 4946

	tg3_netif_start(tp);

	if (restart_timer)
		mod_timer(&tp->timer, jiffies + 1);
M
Michael Chan 已提交
4947

M
Michael Chan 已提交
4948
out:
M
Michael Chan 已提交
4949
	tg3_full_unlock(tp);
M
Matt Carlson 已提交
4950 4951 4952

	if (!err)
		tg3_phy_start(tp);
L
Linus Torvalds 已提交
4953 4954
}

4955 4956 4957 4958 4959 4960 4961 4962
static void tg3_dump_short_state(struct tg3 *tp)
{
	printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
	       tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
	printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
	       tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
}

L
Linus Torvalds 已提交
4963 4964 4965 4966
static void tg3_tx_timeout(struct net_device *dev)
{
	struct tg3 *tp = netdev_priv(dev);

4967
	if (netif_msg_tx_err(tp)) {
M
Michael Chan 已提交
4968 4969
		printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
		       dev->name);
4970 4971
		tg3_dump_short_state(tp);
	}
L
Linus Torvalds 已提交
4972 4973 4974 4975

	schedule_work(&tp->reset_task);
}

4976 4977 4978 4979 4980 4981 4982 4983 4984
/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
{
	u32 base = (u32) mapping & 0xffffffff;

	return ((base > 0xffffdcc0) &&
		(base + len + 8 < base));
}

M
Michael Chan 已提交
4985 4986 4987 4988 4989
/* Test for DMA addresses > 40-bit */
static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
					  int len)
{
#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4990
	if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4991
		return (((u64) mapping + len) > DMA_BIT_MASK(40));
M
Michael Chan 已提交
4992 4993 4994 4995 4996 4997
	return 0;
#else
	return 0;
#endif
}

L
Linus Torvalds 已提交
4998 4999
static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);

M
Michael Chan 已提交
5000 5001
/* Workaround 4GB and 40-bit hardware DMA bugs. */
static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5002 5003
				       u32 last_plus_one, u32 *start,
				       u32 base_flags, u32 mss)
L
Linus Torvalds 已提交
5004
{
M
Matt Carlson 已提交
5005
	struct sk_buff *new_skb;
5006
	dma_addr_t new_addr = 0;
L
Linus Torvalds 已提交
5007
	u32 entry = *start;
5008
	int i, ret = 0;
L
Linus Torvalds 已提交
5009

M
Matt Carlson 已提交
5010 5011 5012 5013 5014 5015 5016 5017 5018 5019
	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
		new_skb = skb_copy(skb, GFP_ATOMIC);
	else {
		int more_headroom = 4 - ((unsigned long)skb->data & 3);

		new_skb = skb_copy_expand(skb,
					  skb_headroom(skb) + more_headroom,
					  skb_tailroom(skb), GFP_ATOMIC);
	}

L
Linus Torvalds 已提交
5020
	if (!new_skb) {
5021 5022 5023 5024
		ret = -1;
	} else {
		/* New SKB is guaranteed to be linear. */
		entry = *start;
5025 5026 5027
		ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
		new_addr = skb_shinfo(new_skb)->dma_maps[0];

5028 5029 5030
		/* Make sure new skb does not cross any 4G boundaries.
		 * Drop the packet if it does.
		 */
5031
		if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5032 5033 5034
			if (!ret)
				skb_dma_unmap(&tp->pdev->dev, new_skb,
					      DMA_TO_DEVICE);
5035 5036 5037 5038 5039 5040 5041 5042
			ret = -1;
			dev_kfree_skb(new_skb);
			new_skb = NULL;
		} else {
			tg3_set_txd(tp, entry, new_addr, new_skb->len,
				    base_flags, 1 | (mss << 1));
			*start = NEXT_TX(entry);
		}
L
Linus Torvalds 已提交
5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056
	}

	/* Now clean up the sw ring entries. */
	i = 0;
	while (entry != last_plus_one) {
		if (i == 0) {
			tp->tx_buffers[entry].skb = new_skb;
		} else {
			tp->tx_buffers[entry].skb = NULL;
		}
		entry = NEXT_TX(entry);
		i++;
	}

5057
	skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
L
Linus Torvalds 已提交
5058 5059
	dev_kfree_skb(skb);

5060
	return ret;
L
Linus Torvalds 已提交
5061 5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085
}

static void tg3_set_txd(struct tg3 *tp, int entry,
			dma_addr_t mapping, int len, u32 flags,
			u32 mss_and_is_end)
{
	struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
	int is_end = (mss_and_is_end & 0x1);
	u32 mss = (mss_and_is_end >> 1);
	u32 vlan_tag = 0;

	if (is_end)
		flags |= TXD_FLAG_END;
	if (flags & TXD_FLAG_VLAN) {
		vlan_tag = flags >> 16;
		flags &= 0xffff;
	}
	vlan_tag |= (mss << TXD_MSS_SHIFT);

	txd->addr_hi = ((u64) mapping >> 32);
	txd->addr_lo = ((u64) mapping & 0xffffffff);
	txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
	txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
}

M
Michael Chan 已提交
5086 5087 5088
/* hard_start_xmit for devices that don't have any bugs and
 * support TG3_FLG2_HW_TSO_2 only.
 */
L
Linus Torvalds 已提交
5089
static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
M
Michael Chan 已提交
5090 5091 5092
{
	struct tg3 *tp = netdev_priv(dev);
	u32 len, entry, base_flags, mss;
5093 5094
	struct skb_shared_info *sp;
	dma_addr_t mapping;
M
Michael Chan 已提交
5095 5096 5097

	len = skb_headlen(skb);

M
Michael Chan 已提交
5098
	/* We are running in BH disabled context with netif_tx_lock
5099
	 * and TX reclaim runs via tp->napi.poll inside of a software
M
Michael Chan 已提交
5100 5101 5102
	 * interrupt.  Furthermore, IRQ processing runs lockless so we have
	 * no IRQ context deadlocks to worry about either.  Rejoice!
	 */
M
Michael Chan 已提交
5103
	if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
M
Michael Chan 已提交
5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116
		if (!netif_queue_stopped(dev)) {
			netif_stop_queue(dev);

			/* This is a hard error, log it. */
			printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
			       "queue awake!\n", dev->name);
		}
		return NETDEV_TX_BUSY;
	}

	entry = tp->tx_prod;
	base_flags = 0;
	mss = 0;
M
Matt Carlson 已提交
5117
	if ((mss = skb_shinfo(skb)->gso_size) != 0) {
M
Michael Chan 已提交
5118 5119 5120 5121 5122 5123 5124 5125
		int tcp_opt_len, ip_tcp_len;

		if (skb_header_cloned(skb) &&
		    pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
			dev_kfree_skb(skb);
			goto out_unlock;
		}

M
Michael Chan 已提交
5126 5127 5128
		if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
			mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
		else {
5129 5130
			struct iphdr *iph = ip_hdr(skb);

5131
			tcp_opt_len = tcp_optlen(skb);
5132
			ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
M
Michael Chan 已提交
5133

5134 5135
			iph->check = 0;
			iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
M
Michael Chan 已提交
5136 5137
			mss |= (ip_tcp_len + tcp_opt_len) << 9;
		}
M
Michael Chan 已提交
5138 5139 5140 5141

		base_flags |= (TXD_FLAG_CPU_PRE_DMA |
			       TXD_FLAG_CPU_POST_DMA);

5142
		tcp_hdr(skb)->check = 0;
M
Michael Chan 已提交
5143 5144

	}
5145
	else if (skb->ip_summed == CHECKSUM_PARTIAL)
M
Michael Chan 已提交
5146 5147 5148 5149 5150 5151 5152
		base_flags |= TXD_FLAG_TCPUDP_CSUM;
#if TG3_VLAN_TAG_USED
	if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
		base_flags |= (TXD_FLAG_VLAN |
			       (vlan_tx_tag_get(skb) << 16));
#endif

5153 5154 5155 5156 5157 5158 5159 5160
	if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
		dev_kfree_skb(skb);
		goto out_unlock;
	}

	sp = skb_shinfo(skb);

	mapping = sp->dma_maps[0];
M
Michael Chan 已提交
5161 5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177

	tp->tx_buffers[entry].skb = skb;

	tg3_set_txd(tp, entry, mapping, len, base_flags,
		    (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));

	entry = NEXT_TX(entry);

	/* Now loop through additional data fragments, and queue them. */
	if (skb_shinfo(skb)->nr_frags > 0) {
		unsigned int i, last;

		last = skb_shinfo(skb)->nr_frags - 1;
		for (i = 0; i <= last; i++) {
			skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

			len = frag->size;
5178
			mapping = sp->dma_maps[i + 1];
M
Michael Chan 已提交
5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191
			tp->tx_buffers[entry].skb = NULL;

			tg3_set_txd(tp, entry, mapping, len,
				    base_flags, (i == last) | (mss << 1));

			entry = NEXT_TX(entry);
		}
	}

	/* Packets are ready, update Tx producer idx local and on card. */
	tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);

	tp->tx_prod = entry;
M
Michael Chan 已提交
5192
	if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
M
Michael Chan 已提交
5193
		netif_stop_queue(dev);
5194
		if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
M
Michael Chan 已提交
5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205
			netif_wake_queue(tp->dev);
	}

out_unlock:
    	mmiowb();

	dev->trans_start = jiffies;

	return NETDEV_TX_OK;
}

5206 5207 5208 5209 5210 5211 5212 5213 5214 5215
static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);

/* Use GSO to workaround a rare TSO bug that may be triggered when the
 * TSO header is greater than 80 bytes.
 */
static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
{
	struct sk_buff *segs, *nskb;

	/* Estimate the number of fragments in the worst case */
M
Michael Chan 已提交
5216
	if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5217
		netif_stop_queue(tp->dev);
M
Michael Chan 已提交
5218 5219 5220 5221
		if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
			return NETDEV_TX_BUSY;

		netif_wake_queue(tp->dev);
5222 5223 5224
	}

	segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5225
	if (IS_ERR(segs))
5226 5227 5228 5229 5230 5231 5232 5233 5234 5235 5236 5237 5238 5239 5240
		goto tg3_tso_bug_end;

	do {
		nskb = segs;
		segs = segs->next;
		nskb->next = NULL;
		tg3_start_xmit_dma_bug(nskb, tp->dev);
	} while (segs);

tg3_tso_bug_end:
	dev_kfree_skb(skb);

	return NETDEV_TX_OK;
}

M
Michael Chan 已提交
5241 5242 5243 5244
/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
 */
static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
L
Linus Torvalds 已提交
5245 5246 5247
{
	struct tg3 *tp = netdev_priv(dev);
	u32 len, entry, base_flags, mss;
5248
	struct skb_shared_info *sp;
L
Linus Torvalds 已提交
5249
	int would_hit_hwbug;
5250
	dma_addr_t mapping;
L
Linus Torvalds 已提交
5251 5252 5253

	len = skb_headlen(skb);

M
Michael Chan 已提交
5254
	/* We are running in BH disabled context with netif_tx_lock
5255
	 * and TX reclaim runs via tp->napi.poll inside of a software
5256 5257
	 * interrupt.  Furthermore, IRQ processing runs lockless so we have
	 * no IRQ context deadlocks to worry about either.  Rejoice!
L
Linus Torvalds 已提交
5258
	 */
M
Michael Chan 已提交
5259
	if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
S
Stephen Hemminger 已提交
5260 5261 5262 5263 5264 5265 5266
		if (!netif_queue_stopped(dev)) {
			netif_stop_queue(dev);

			/* This is a hard error, log it. */
			printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
			       "queue awake!\n", dev->name);
		}
L
Linus Torvalds 已提交
5267 5268 5269 5270 5271
		return NETDEV_TX_BUSY;
	}

	entry = tp->tx_prod;
	base_flags = 0;
5272
	if (skb->ip_summed == CHECKSUM_PARTIAL)
L
Linus Torvalds 已提交
5273 5274
		base_flags |= TXD_FLAG_TCPUDP_CSUM;
	mss = 0;
M
Matt Carlson 已提交
5275
	if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5276
		struct iphdr *iph;
5277
		int tcp_opt_len, ip_tcp_len, hdr_len;
L
Linus Torvalds 已提交
5278 5279 5280 5281 5282 5283 5284

		if (skb_header_cloned(skb) &&
		    pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
			dev_kfree_skb(skb);
			goto out_unlock;
		}

5285
		tcp_opt_len = tcp_optlen(skb);
5286
		ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
L
Linus Torvalds 已提交
5287

5288 5289
		hdr_len = ip_tcp_len + tcp_opt_len;
		if (unlikely((ETH_HLEN + hdr_len) > 80) &&
M
Michael Chan 已提交
5290
			     (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5291 5292
			return (tg3_tso_bug(tp, skb));

L
Linus Torvalds 已提交
5293 5294 5295
		base_flags |= (TXD_FLAG_CPU_PRE_DMA |
			       TXD_FLAG_CPU_POST_DMA);

5296 5297 5298
		iph = ip_hdr(skb);
		iph->check = 0;
		iph->tot_len = htons(mss + hdr_len);
L
Linus Torvalds 已提交
5299
		if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5300
			tcp_hdr(skb)->check = 0;
L
Linus Torvalds 已提交
5301
			base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5302 5303 5304 5305 5306
		} else
			tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
								 iph->daddr, 0,
								 IPPROTO_TCP,
								 0);
L
Linus Torvalds 已提交
5307 5308 5309

		if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
		    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5310
			if (tcp_opt_len || iph->ihl > 5) {
L
Linus Torvalds 已提交
5311 5312
				int tsflags;

5313
				tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
L
Linus Torvalds 已提交
5314 5315 5316
				mss |= (tsflags << 11);
			}
		} else {
5317
			if (tcp_opt_len || iph->ihl > 5) {
L
Linus Torvalds 已提交
5318 5319
				int tsflags;

5320
				tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
L
Linus Torvalds 已提交
5321 5322 5323 5324 5325 5326 5327 5328 5329 5330
				base_flags |= tsflags << 12;
			}
		}
	}
#if TG3_VLAN_TAG_USED
	if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
		base_flags |= (TXD_FLAG_VLAN |
			       (vlan_tx_tag_get(skb) << 16));
#endif

5331 5332 5333 5334 5335 5336 5337 5338
	if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
		dev_kfree_skb(skb);
		goto out_unlock;
	}

	sp = skb_shinfo(skb);

	mapping = sp->dma_maps[0];
L
Linus Torvalds 已提交
5339 5340 5341 5342 5343

	tp->tx_buffers[entry].skb = skb;

	would_hit_hwbug = 0;

M
Matt Carlson 已提交
5344 5345 5346
	if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
		would_hit_hwbug = 1;
	else if (tg3_4g_overflow_test(mapping, len))
5347
		would_hit_hwbug = 1;
L
Linus Torvalds 已提交
5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360 5361 5362

	tg3_set_txd(tp, entry, mapping, len, base_flags,
		    (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));

	entry = NEXT_TX(entry);

	/* Now loop through additional data fragments, and queue them. */
	if (skb_shinfo(skb)->nr_frags > 0) {
		unsigned int i, last;

		last = skb_shinfo(skb)->nr_frags - 1;
		for (i = 0; i <= last; i++) {
			skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

			len = frag->size;
5363
			mapping = sp->dma_maps[i + 1];
L
Linus Torvalds 已提交
5364 5365 5366

			tp->tx_buffers[entry].skb = NULL;

5367 5368
			if (tg3_4g_overflow_test(mapping, len))
				would_hit_hwbug = 1;
L
Linus Torvalds 已提交
5369

M
Michael Chan 已提交
5370 5371 5372
			if (tg3_40bit_overflow_test(tp, mapping, len))
				would_hit_hwbug = 1;

L
Linus Torvalds 已提交
5373 5374 5375 5376 5377 5378 5379 5380 5381 5382 5383 5384 5385 5386 5387
			if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
				tg3_set_txd(tp, entry, mapping, len,
					    base_flags, (i == last)|(mss << 1));
			else
				tg3_set_txd(tp, entry, mapping, len,
					    base_flags, (i == last));

			entry = NEXT_TX(entry);
		}
	}

	if (would_hit_hwbug) {
		u32 last_plus_one = entry;
		u32 start;

5388 5389
		start = entry - 1 - skb_shinfo(skb)->nr_frags;
		start &= (TG3_TX_RING_SIZE - 1);
L
Linus Torvalds 已提交
5390 5391 5392 5393

		/* If the workaround fails due to memory/mapping
		 * failure, silently drop this packet.
		 */
M
Michael Chan 已提交
5394
		if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5395
						&start, base_flags, mss))
L
Linus Torvalds 已提交
5396 5397 5398 5399 5400 5401 5402 5403 5404
			goto out_unlock;

		entry = start;
	}

	/* Packets are ready, update Tx producer idx local and on card. */
	tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);

	tp->tx_prod = entry;
M
Michael Chan 已提交
5405
	if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
L
Linus Torvalds 已提交
5406
		netif_stop_queue(dev);
5407
		if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5408 5409
			netif_wake_queue(tp->dev);
	}
L
Linus Torvalds 已提交
5410 5411 5412 5413 5414 5415 5416 5417 5418 5419 5420 5421 5422 5423

out_unlock:
    	mmiowb();

	dev->trans_start = jiffies;

	return NETDEV_TX_OK;
}

static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
			       int new_mtu)
{
	dev->mtu = new_mtu;

M
Michael Chan 已提交
5424
	if (new_mtu > ETH_DATA_LEN) {
M
Michael Chan 已提交
5425
		if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
M
Michael Chan 已提交
5426 5427 5428 5429 5430 5431
			tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
			ethtool_op_set_tso(dev, 0);
		}
		else
			tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
	} else {
M
Michael Chan 已提交
5432
		if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
M
Michael Chan 已提交
5433
			tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5434
		tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
M
Michael Chan 已提交
5435
	}
L
Linus Torvalds 已提交
5436 5437 5438 5439 5440
}

static int tg3_change_mtu(struct net_device *dev, int new_mtu)
{
	struct tg3 *tp = netdev_priv(dev);
M
Michael Chan 已提交
5441
	int err;
L
Linus Torvalds 已提交
5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5452 5453

	if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
		return -EINVAL;

	if (!netif_running(dev)) {
		/* We'll just catch it later when the
		 * device is up'd.
		 */
		tg3_set_mtu(dev, tp, new_mtu);
		return 0;
	}

M
Matt Carlson 已提交
5454 5455
	tg3_phy_stop(tp);

L
Linus Torvalds 已提交
5456
	tg3_netif_stop(tp);
5457 5458

	tg3_full_lock(tp, 1);
L
Linus Torvalds 已提交
5459

M
Michael Chan 已提交
5460
	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
L
Linus Torvalds 已提交
5461 5462 5463

	tg3_set_mtu(dev, tp, new_mtu);

M
Michael Chan 已提交
5464
	err = tg3_restart_hw(tp, 0);
L
Linus Torvalds 已提交
5465

M
Michael Chan 已提交
5466 5467
	if (!err)
		tg3_netif_start(tp);
L
Linus Torvalds 已提交
5468

5469
	tg3_full_unlock(tp);
L
Linus Torvalds 已提交
5470

M
Matt Carlson 已提交
5471 5472 5473
	if (!err)
		tg3_phy_start(tp);

M
Michael Chan 已提交
5474
	return err;
L
Linus Torvalds 已提交
5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494 5495
}

/* Free up pending packets in all rx/tx rings.
 *
 * The chip has been shut down and the driver detached from
 * the networking, so no interrupts or new tx packets will
 * end up in the driver.  tp->{tx,}lock is not held and we are not
 * in an interrupt context and thus may sleep.
 */
static void tg3_free_rings(struct tg3 *tp)
{
	struct ring_info *rxp;
	int i;

	for (i = 0; i < TG3_RX_RING_SIZE; i++) {
		rxp = &tp->rx_std_buffers[i];

		if (rxp->skb == NULL)
			continue;
		pci_unmap_single(tp->pdev,
				 pci_unmap_addr(rxp, mapping),
5496
				 tp->rx_pkt_buf_sz - tp->rx_offset,
L
Linus Torvalds 已提交
5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517 5518 5519 5520 5521 5522 5523 5524 5525 5526
				 PCI_DMA_FROMDEVICE);
		dev_kfree_skb_any(rxp->skb);
		rxp->skb = NULL;
	}

	for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
		rxp = &tp->rx_jumbo_buffers[i];

		if (rxp->skb == NULL)
			continue;
		pci_unmap_single(tp->pdev,
				 pci_unmap_addr(rxp, mapping),
				 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
				 PCI_DMA_FROMDEVICE);
		dev_kfree_skb_any(rxp->skb);
		rxp->skb = NULL;
	}

	for (i = 0; i < TG3_TX_RING_SIZE; ) {
		struct tx_ring_info *txp;
		struct sk_buff *skb;

		txp = &tp->tx_buffers[i];
		skb = txp->skb;

		if (skb == NULL) {
			i++;
			continue;
		}

5527
		skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
L
Linus Torvalds 已提交
5528

5529
		txp->skb = NULL;
L
Linus Torvalds 已提交
5530

5531
		i += skb_shinfo(skb)->nr_frags + 1;
L
Linus Torvalds 已提交
5532 5533 5534 5535 5536 5537 5538 5539 5540 5541 5542 5543

		dev_kfree_skb_any(skb);
	}
}

/* Initialize tx/rx rings for packet processing.
 *
 * The chip has been shut down and the driver detached from
 * the networking, so no interrupts or new tx packets will
 * end up in the driver.  tp->{tx,}lock are held and thus
 * we may not sleep.
 */
5544
static int tg3_init_rings(struct tg3 *tp)
L
Linus Torvalds 已提交
5545 5546 5547 5548 5549 5550 5551 5552 5553 5554 5555 5556
{
	u32 i;

	/* Free up all the SKBs. */
	tg3_free_rings(tp);

	/* Zero out all descriptors. */
	memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
	memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
	memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
	memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);

5557
	tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
M
Michael Chan 已提交
5558
	if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5559 5560 5561
	    (tp->dev->mtu > ETH_DATA_LEN))
		tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;

L
Linus Torvalds 已提交
5562 5563 5564 5565 5566 5567 5568 5569
	/* Initialize invariants of the rings, we only set this
	 * stuff once.  This works because the card does not
	 * write into the rx buffer posting rings.
	 */
	for (i = 0; i < TG3_RX_RING_SIZE; i++) {
		struct tg3_rx_buffer_desc *rxd;

		rxd = &tp->rx_std[i];
5570
		rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
L
Linus Torvalds 已提交
5571 5572 5573 5574 5575 5576
			<< RXD_LEN_SHIFT;
		rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
		rxd->opaque = (RXD_OPAQUE_RING_STD |
			       (i << RXD_OPAQUE_INDEX_SHIFT));
	}

5577
	if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
L
Linus Torvalds 已提交
5578 5579 5580 5581 5582 5583 5584 5585 5586 5587 5588 5589 5590 5591 5592
		for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
			struct tg3_rx_buffer_desc *rxd;

			rxd = &tp->rx_jumbo[i];
			rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
				<< RXD_LEN_SHIFT;
			rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
				RXD_FLAG_JUMBO;
			rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
			       (i << RXD_OPAQUE_INDEX_SHIFT));
		}
	}

	/* Now allocate fresh SKBs for each rx ring. */
	for (i = 0; i < tp->rx_pending; i++) {
5593 5594 5595 5596 5597 5598 5599 5600 5601
		if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
			printk(KERN_WARNING PFX
			       "%s: Using a smaller RX standard ring, "
			       "only %d out of %d buffers were allocated "
			       "successfully.\n",
			       tp->dev->name, i, tp->rx_pending);
			if (i == 0)
				return -ENOMEM;
			tp->rx_pending = i;
L
Linus Torvalds 已提交
5602
			break;
5603
		}
L
Linus Torvalds 已提交
5604 5605
	}

5606
	if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
L
Linus Torvalds 已提交
5607 5608
		for (i = 0; i < tp->rx_jumbo_pending; i++) {
			if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5609 5610 5611 5612 5613 5614 5615 5616 5617 5618 5619
					     -1, i) < 0) {
				printk(KERN_WARNING PFX
				       "%s: Using a smaller RX jumbo ring, "
				       "only %d out of %d buffers were "
				       "allocated successfully.\n",
				       tp->dev->name, i, tp->rx_jumbo_pending);
				if (i == 0) {
					tg3_free_rings(tp);
					return -ENOMEM;
				}
				tp->rx_jumbo_pending = i;
L
Linus Torvalds 已提交
5620
				break;
5621
			}
L
Linus Torvalds 已提交
5622 5623
		}
	}
5624
	return 0;
L
Linus Torvalds 已提交
5625 5626 5627 5628 5629 5630 5631 5632
}

/*
 * Must not be invoked with interrupt sources disabled and
 * the hardware shutdown down.
 */
static void tg3_free_consistent(struct tg3 *tp)
{
5633 5634
	kfree(tp->rx_std_buffers);
	tp->rx_std_buffers = NULL;
L
Linus Torvalds 已提交
5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656 5657 5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672
	if (tp->rx_std) {
		pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
				    tp->rx_std, tp->rx_std_mapping);
		tp->rx_std = NULL;
	}
	if (tp->rx_jumbo) {
		pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
				    tp->rx_jumbo, tp->rx_jumbo_mapping);
		tp->rx_jumbo = NULL;
	}
	if (tp->rx_rcb) {
		pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
				    tp->rx_rcb, tp->rx_rcb_mapping);
		tp->rx_rcb = NULL;
	}
	if (tp->tx_ring) {
		pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
			tp->tx_ring, tp->tx_desc_mapping);
		tp->tx_ring = NULL;
	}
	if (tp->hw_status) {
		pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
				    tp->hw_status, tp->status_mapping);
		tp->hw_status = NULL;
	}
	if (tp->hw_stats) {
		pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
				    tp->hw_stats, tp->stats_mapping);
		tp->hw_stats = NULL;
	}
}

/*
 * Must not be invoked with interrupt sources disabled and
 * the hardware shutdown down.  Can sleep.
 */
static int tg3_alloc_consistent(struct tg3 *tp)
{
5673
	tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
L
Linus Torvalds 已提交
5674 5675 5676 5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688 5689 5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703 5704 5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715 5716 5717 5718 5719 5720 5721 5722 5723 5724 5725 5726 5727 5728 5729 5730 5731 5732 5733
				      (TG3_RX_RING_SIZE +
				       TG3_RX_JUMBO_RING_SIZE)) +
				     (sizeof(struct tx_ring_info) *
				      TG3_TX_RING_SIZE),
				     GFP_KERNEL);
	if (!tp->rx_std_buffers)
		return -ENOMEM;

	tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
	tp->tx_buffers = (struct tx_ring_info *)
		&tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];

	tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
					  &tp->rx_std_mapping);
	if (!tp->rx_std)
		goto err_out;

	tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
					    &tp->rx_jumbo_mapping);

	if (!tp->rx_jumbo)
		goto err_out;

	tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
					  &tp->rx_rcb_mapping);
	if (!tp->rx_rcb)
		goto err_out;

	tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
					   &tp->tx_desc_mapping);
	if (!tp->tx_ring)
		goto err_out;

	tp->hw_status = pci_alloc_consistent(tp->pdev,
					     TG3_HW_STATUS_SIZE,
					     &tp->status_mapping);
	if (!tp->hw_status)
		goto err_out;

	tp->hw_stats = pci_alloc_consistent(tp->pdev,
					    sizeof(struct tg3_hw_stats),
					    &tp->stats_mapping);
	if (!tp->hw_stats)
		goto err_out;

	memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
	memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));

	return 0;

err_out:
	tg3_free_consistent(tp);
	return -ENOMEM;
}

#define MAX_WAIT_CNT 1000

/* To stop a block, clear the enable bit and poll till it
 * clears.  tp->lock is held.
 */
5734
static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
L
Linus Torvalds 已提交
5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752
{
	unsigned int i;
	u32 val;

	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
		switch (ofs) {
		case RCVLSC_MODE:
		case DMAC_MODE:
		case MBFREE_MODE:
		case BUFMGR_MODE:
		case MEMARB_MODE:
			/* We can't enable/disable these bits of the
			 * 5705/5750, just say success.
			 */
			return 0;

		default:
			break;
5753
		}
L
Linus Torvalds 已提交
5754 5755 5756 5757 5758 5759 5760 5761 5762 5763 5764 5765 5766
	}

	val = tr32(ofs);
	val &= ~enable_bit;
	tw32_f(ofs, val);

	for (i = 0; i < MAX_WAIT_CNT; i++) {
		udelay(100);
		val = tr32(ofs);
		if ((val & enable_bit) == 0)
			break;
	}

5767
	if (i == MAX_WAIT_CNT && !silent) {
L
Linus Torvalds 已提交
5768 5769 5770 5771 5772 5773 5774 5775 5776 5777
		printk(KERN_ERR PFX "tg3_stop_block timed out, "
		       "ofs=%lx enable_bit=%x\n",
		       ofs, enable_bit);
		return -ENODEV;
	}

	return 0;
}

/* tp->lock is held. */
5778
static int tg3_abort_hw(struct tg3 *tp, int silent)
L
Linus Torvalds 已提交
5779 5780 5781 5782 5783 5784 5785 5786 5787
{
	int i, err;

	tg3_disable_ints(tp);

	tp->rx_mode &= ~RX_MODE_ENABLE;
	tw32_f(MAC_RX_MODE, tp->rx_mode);
	udelay(10);

5788 5789 5790 5791 5792 5793 5794 5795 5796 5797 5798 5799 5800 5801
	err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
	err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
	err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
	err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
	err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
	err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);

	err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
	err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
	err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
	err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
	err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
	err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
	err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
L
Linus Torvalds 已提交
5802 5803 5804 5805 5806 5807 5808 5809 5810 5811 5812 5813 5814 5815 5816 5817 5818

	tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
	tw32_f(MAC_MODE, tp->mac_mode);
	udelay(40);

	tp->tx_mode &= ~TX_MODE_ENABLE;
	tw32_f(MAC_TX_MODE, tp->tx_mode);

	for (i = 0; i < MAX_WAIT_CNT; i++) {
		udelay(100);
		if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
			break;
	}
	if (i >= MAX_WAIT_CNT) {
		printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
		       "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
		       tp->dev->name, tr32(MAC_TX_MODE));
5819
		err |= -ENODEV;
L
Linus Torvalds 已提交
5820 5821
	}

5822
	err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5823 5824
	err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
	err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
L
Linus Torvalds 已提交
5825 5826 5827 5828

	tw32(FTQ_RESET, 0xffffffff);
	tw32(FTQ_RESET, 0x00000000);

5829 5830
	err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
	err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
L
Linus Torvalds 已提交
5831 5832 5833 5834 5835 5836 5837 5838 5839

	if (tp->hw_status)
		memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
	if (tp->hw_stats)
		memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));

	return err;
}

M
Matt Carlson 已提交
5840 5841 5842 5843 5844 5845 5846 5847 5848 5849
static void tg3_ape_send_event(struct tg3 *tp, u32 event)
{
	int i;
	u32 apedata;

	apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
	if (apedata != APE_SEG_SIG_MAGIC)
		return;

	apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
M
Matt Carlson 已提交
5850
	if (!(apedata & APE_FW_STATUS_READY))
M
Matt Carlson 已提交
5851 5852 5853 5854 5855 5856 5857 5858 5859 5860 5861 5862 5863 5864 5865 5866 5867 5868 5869 5870 5871 5872 5873 5874 5875 5876 5877 5878 5879 5880 5881 5882 5883 5884 5885 5886 5887 5888 5889 5890 5891 5892 5893 5894 5895 5896 5897 5898 5899
		return;

	/* Wait for up to 1 millisecond for APE to service previous event. */
	for (i = 0; i < 10; i++) {
		if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
			return;

		apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);

		if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
			tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
					event | APE_EVENT_STATUS_EVENT_PENDING);

		tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);

		if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
			break;

		udelay(100);
	}

	if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
		tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
}

static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
{
	u32 event;
	u32 apedata;

	if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
		return;

	switch (kind) {
		case RESET_KIND_INIT:
			tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
					APE_HOST_SEG_SIG_MAGIC);
			tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
					APE_HOST_SEG_LEN_MAGIC);
			apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
			tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
			tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
					APE_HOST_DRIVER_ID_MAGIC);
			tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
					APE_HOST_BEHAV_NO_PHYLOCK);

			event = APE_EVENT_STATUS_STATE_START;
			break;
		case RESET_KIND_SHUTDOWN:
5900 5901 5902 5903 5904 5905 5906
			/* With the interface we are currently using,
			 * APE does not track driver state.  Wiping
			 * out the HOST SEGMENT SIGNATURE forces
			 * the APE to assume OS absent status.
			 */
			tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);

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			event = APE_EVENT_STATUS_STATE_UNLOAD;
			break;
		case RESET_KIND_SUSPEND:
			event = APE_EVENT_STATUS_STATE_SUSPEND;
			break;
		default:
			return;
	}

	event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;

	tg3_ape_send_event(tp, event);
}

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/* tp->lock is held. */
static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
{
5924 5925
	tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
		      NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
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5926 5927 5928 5929 5930 5931 5932 5933 5934 5935 5936 5937 5938 5939 5940 5941 5942 5943 5944 5945

	if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
		switch (kind) {
		case RESET_KIND_INIT:
			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
				      DRV_STATE_START);
			break;

		case RESET_KIND_SHUTDOWN:
			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
				      DRV_STATE_UNLOAD);
			break;

		case RESET_KIND_SUSPEND:
			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
				      DRV_STATE_SUSPEND);
			break;

		default:
			break;
5946
		}
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Linus Torvalds 已提交
5947
	}
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5948 5949 5950 5951

	if (kind == RESET_KIND_INIT ||
	    kind == RESET_KIND_SUSPEND)
		tg3_ape_driver_state_change(tp, kind);
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5952 5953 5954 5955 5956 5957 5958 5959 5960 5961 5962 5963 5964 5965 5966 5967 5968 5969 5970
}

/* tp->lock is held. */
static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
{
	if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
		switch (kind) {
		case RESET_KIND_INIT:
			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
				      DRV_STATE_START_DONE);
			break;

		case RESET_KIND_SHUTDOWN:
			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
				      DRV_STATE_UNLOAD_DONE);
			break;

		default:
			break;
5971
		}
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	}
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	if (kind == RESET_KIND_SHUTDOWN)
		tg3_ape_driver_state_change(tp, kind);
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}

/* tp->lock is held. */
static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
{
	if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
		switch (kind) {
		case RESET_KIND_INIT:
			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
				      DRV_STATE_START);
			break;

		case RESET_KIND_SHUTDOWN:
			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
				      DRV_STATE_UNLOAD);
			break;

		case RESET_KIND_SUSPEND:
			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
				      DRV_STATE_SUSPEND);
			break;

		default:
			break;
6000
		}
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	}
}

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static int tg3_poll_fw(struct tg3 *tp)
{
	int i;
	u32 val;

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	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6010 6011
		/* Wait up to 20ms for init done. */
		for (i = 0; i < 200; i++) {
M
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6012 6013
			if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
				return 0;
6014
			udelay(100);
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6015 6016 6017 6018
		}
		return -ENODEV;
	}

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	/* Wait for firmware initialization to complete. */
	for (i = 0; i < 100000; i++) {
		tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
		if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
			break;
		udelay(10);
	}

	/* Chip might not be fitted with firmware.  Some Sun onboard
	 * parts are configured like that.  So don't signal the timeout
	 * of the above loop as an error, but do report the lack of
	 * running firmware once.
	 */
	if (i >= 100000 &&
	    !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
		tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;

		printk(KERN_INFO PFX "%s: No firmware running.\n",
		       tp->dev->name);
	}

	return 0;
}

6043 6044 6045
/* Save PCI command register before chip reset */
static void tg3_save_pci_state(struct tg3 *tp)
{
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	pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6047 6048 6049 6050 6051 6052 6053 6054 6055 6056 6057 6058 6059 6060 6061 6062
}

/* Restore PCI state after chip reset */
static void tg3_restore_pci_state(struct tg3 *tp)
{
	u32 val;

	/* Re-enable indirect register accesses. */
	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
			       tp->misc_host_ctrl);

	/* Set MAX PCI retry to zero. */
	val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
		val |= PCISTATE_RETRY_SAME_DMA;
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	/* Allow reads and writes to the APE register and memory space. */
	if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
		val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
		       PCISTATE_ALLOW_APE_SHMEM_WR;
6067 6068
	pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);

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	pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6070

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	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
		if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
			pcie_set_readrq(tp->pdev, 4096);
		else {
			pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
					      tp->pci_cacheline_sz);
			pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
					      tp->pci_lat_timer);
		}
6080
	}
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Matt Carlson 已提交
6081

6082
	/* Make sure PCI-X relaxed ordering bit is clear. */
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Matt Carlson 已提交
6083
	if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
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		u16 pcix_cmd;

		pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
				     &pcix_cmd);
		pcix_cmd &= ~PCI_X_CMD_ERO;
		pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
				      pcix_cmd);
	}
6092 6093 6094 6095 6096 6097 6098 6099 6100 6101 6102 6103 6104 6105 6106 6107 6108 6109 6110 6111 6112

	if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {

		/* Chip reset on 5780 will reset MSI enable bit,
		 * so need to restore it.
		 */
		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
			u16 ctrl;

			pci_read_config_word(tp->pdev,
					     tp->msi_cap + PCI_MSI_FLAGS,
					     &ctrl);
			pci_write_config_word(tp->pdev,
					      tp->msi_cap + PCI_MSI_FLAGS,
					      ctrl | PCI_MSI_FLAGS_ENABLE);
			val = tr32(MSGINT_MODE);
			tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
		}
	}
}

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static void tg3_stop_fw(struct tg3 *);

/* tp->lock is held. */
static int tg3_chip_reset(struct tg3 *tp)
{
	u32 val;
6119
	void (*write_op)(struct tg3 *, u32, u32);
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6120
	int err;
L
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6121

6122 6123
	tg3_nvram_lock(tp);

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6124 6125
	tg3_mdio_stop(tp);

6126 6127
	tg3_ape_lock(tp, TG3_APE_LOCK_GRC);

6128 6129 6130 6131
	/* No matching tg3_nvram_unlock() after this because
	 * chip reset below will undo the nvram lock.
	 */
	tp->nvram_lock_cnt = 0;
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Linus Torvalds 已提交
6132

6133 6134 6135 6136 6137 6138
	/* GRC_MISC_CFG core clock reset will clear the memory
	 * enable bit in PCI register 4 and the MSI enable bit
	 * on some chips, so we save relevant registers here.
	 */
	tg3_save_pci_state(tp);

6139
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
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Matt Carlson 已提交
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	    (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6141 6142
		tw32(GRC_FASTBOOT_PC, 0);

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	/*
	 * We must avoid the readl() that normally takes place.
	 * It locks machines, causes machine checks, and other
	 * fun things.  So, temporarily disable the 5701
	 * hardware workaround, while we do the reset.
	 */
6149 6150 6151
	write_op = tp->write32;
	if (write_op == tg3_write_flush_reg32)
		tp->write32 = tg3_write32;
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Linus Torvalds 已提交
6152

6153 6154 6155 6156 6157 6158 6159
	/* Prevent the irq handler from reading or writing PCI registers
	 * during chip reset when the memory enable bit in the PCI command
	 * register may be cleared.  The chip does not generate interrupt
	 * at this time, but the irq handler may still be called due to irq
	 * sharing or irqpoll.
	 */
	tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6160 6161 6162 6163
	if (tp->hw_status) {
		tp->hw_status->status = 0;
		tp->hw_status->status_tag = 0;
	}
6164
	tp->last_tag = 0;
6165
	tp->last_irq_tag = 0;
6166 6167 6168
	smp_mb();
	synchronize_irq(tp->pdev->irq);

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6169 6170 6171 6172 6173 6174 6175 6176 6177 6178 6179 6180 6181
	/* do the reset */
	val = GRC_MISC_CFG_CORECLK_RESET;

	if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
		if (tr32(0x7e2c) == 0x60) {
			tw32(0x7e2c, 0x20);
		}
		if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
			tw32(GRC_MISC_CFG, (1 << 29));
			val |= (1 << 29);
		}
	}

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	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
		tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
		tw32(GRC_VCPU_EXT_CTRL,
		     tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
	}

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	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
		val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
	tw32(GRC_MISC_CFG, val);

6192 6193
	/* restore 5701 hardware bug workaround write method */
	tp->write32 = write_op;
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6194 6195 6196 6197 6198 6199 6200 6201 6202 6203 6204 6205 6206 6207 6208 6209 6210 6211 6212 6213 6214 6215 6216 6217 6218 6219

	/* Unfortunately, we have to delay before the PCI read back.
	 * Some 575X chips even will not respond to a PCI cfg access
	 * when the reset command is given to the chip.
	 *
	 * How do these hardware designers expect things to work
	 * properly if the PCI write is posted for a long period
	 * of time?  It is always necessary to have some method by
	 * which a register read back can occur to push the write
	 * out which does the reset.
	 *
	 * For most tg3 variants the trick below was working.
	 * Ho hum...
	 */
	udelay(120);

	/* Flush PCI posted writes.  The normal MMIO registers
	 * are inaccessible at this time so this is the only
	 * way to make this reliably (actually, this is no longer
	 * the case, see above).  I tried to use indirect
	 * register read/write but this upset some 5701 variants.
	 */
	pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);

	udelay(120);

6220
	if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
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Linus Torvalds 已提交
6221 6222 6223 6224 6225 6226 6227 6228 6229 6230 6231 6232
		if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
			int i;
			u32 cfg_val;

			/* Wait for link training to complete.  */
			for (i = 0; i < 5000; i++)
				udelay(100);

			pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
			pci_write_config_dword(tp->pdev, 0xc4,
					       cfg_val | (1 << 15));
		}
6233 6234 6235 6236 6237 6238 6239 6240 6241 6242 6243 6244 6245 6246 6247 6248 6249

		/* Set PCIE max payload size to 128 bytes and
		 * clear the "no snoop" and "relaxed ordering" bits.
		 */
		pci_write_config_word(tp->pdev,
				      tp->pcie_cap + PCI_EXP_DEVCTL,
				      0);

		pcie_set_readrq(tp->pdev, 4096);

		/* Clear error status */
		pci_write_config_word(tp->pdev,
				      tp->pcie_cap + PCI_EXP_DEVSTA,
				      PCI_EXP_DEVSTA_CED |
				      PCI_EXP_DEVSTA_NFED |
				      PCI_EXP_DEVSTA_FED |
				      PCI_EXP_DEVSTA_URD);
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6250 6251
	}

6252
	tg3_restore_pci_state(tp);
L
Linus Torvalds 已提交
6253

6254 6255
	tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;

6256 6257
	val = 0;
	if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
M
Michael Chan 已提交
6258
		val = tr32(MEMARB_MODE);
6259
	tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
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6260 6261 6262 6263 6264 6265 6266 6267 6268

	if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
		tg3_stop_fw(tp);
		tw32(0x5000, 0x400);
	}

	tw32(GRC_MODE, tp->grc_mode);

	if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
A
Andy Gospodarek 已提交
6269
		val = tr32(0xc4);
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Linus Torvalds 已提交
6270 6271 6272 6273 6274 6275 6276 6277 6278 6279 6280 6281 6282 6283 6284

		tw32(0xc4, val | (1 << 15));
	}

	if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
		tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
		if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
			tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
		tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
	}

	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
		tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
		tw32_f(MAC_MODE, tp->mac_mode);
M
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	} else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
		tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
		tw32_f(MAC_MODE, tp->mac_mode);
6288 6289 6290 6291 6292
	} else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
		tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
		if (tp->mac_mode & MAC_MODE_APE_TX_EN)
			tp->mac_mode |= MAC_MODE_TDE_ENABLE;
		tw32_f(MAC_MODE, tp->mac_mode);
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6293 6294 6295 6296
	} else
		tw32_f(MAC_MODE, 0);
	udelay(40);

M
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6297 6298
	tg3_mdio_start(tp);

6299 6300
	tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);

M
Michael Chan 已提交
6301 6302 6303
	err = tg3_poll_fw(tp);
	if (err)
		return err;
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6304 6305 6306

	if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
	    tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
A
Andy Gospodarek 已提交
6307
		val = tr32(0x7c00);
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6308 6309 6310 6311 6312 6313 6314 6315 6316 6317 6318 6319 6320 6321

		tw32(0x7c00, val | (1 << 25));
	}

	/* Reprobe ASF enable state.  */
	tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
	tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
	tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
	if (val == NIC_SRAM_DATA_SIG_MAGIC) {
		u32 nic_cfg;

		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
		if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
			tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
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6322
			tp->last_event_jiffies = jiffies;
6323
			if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
L
Linus Torvalds 已提交
6324 6325 6326 6327 6328 6329 6330 6331 6332 6333
				tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
		}
	}

	return 0;
}

/* tp->lock is held. */
static void tg3_stop_fw(struct tg3 *tp)
{
M
Matt Carlson 已提交
6334 6335
	if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
	   !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6336 6337
		/* Wait for RX cpu to ACK the previous event. */
		tg3_wait_for_event_ack(tp);
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6338 6339

		tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
M
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6340 6341

		tg3_generate_fw_event(tp);
L
Linus Torvalds 已提交
6342

6343 6344
		/* Wait for RX cpu to ACK this event. */
		tg3_wait_for_event_ack(tp);
L
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6345 6346 6347 6348
	}
}

/* tp->lock is held. */
M
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6349
static int tg3_halt(struct tg3 *tp, int kind, int silent)
L
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6350 6351 6352 6353 6354
{
	int err;

	tg3_stop_fw(tp);

M
Michael Chan 已提交
6355
	tg3_write_sig_pre_reset(tp, kind);
L
Linus Torvalds 已提交
6356

6357
	tg3_abort_hw(tp, silent);
L
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6358 6359
	err = tg3_chip_reset(tp);

M
Michael Chan 已提交
6360 6361
	tg3_write_sig_legacy(tp, kind);
	tg3_write_sig_post_reset(tp, kind);
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Linus Torvalds 已提交
6362 6363 6364 6365 6366 6367 6368 6369 6370 6371 6372 6373 6374 6375 6376 6377 6378

	if (err)
		return err;

	return 0;
}

#define RX_CPU_SCRATCH_BASE	0x30000
#define RX_CPU_SCRATCH_SIZE	0x04000
#define TX_CPU_SCRATCH_BASE	0x34000
#define TX_CPU_SCRATCH_SIZE	0x04000

/* tp->lock is held. */
static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
{
	int i;

6379 6380
	BUG_ON(offset == TX_CPU_BASE &&
	    (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
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Linus Torvalds 已提交
6381

M
Michael Chan 已提交
6382 6383 6384 6385 6386 6387
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
		u32 val = tr32(GRC_VCPU_EXT_CTRL);

		tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
		return 0;
	}
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6388 6389 6390 6391 6392 6393 6394 6395 6396 6397 6398 6399 6400 6401 6402 6403 6404 6405 6406 6407 6408 6409 6410 6411 6412 6413 6414
	if (offset == RX_CPU_BASE) {
		for (i = 0; i < 10000; i++) {
			tw32(offset + CPU_STATE, 0xffffffff);
			tw32(offset + CPU_MODE,  CPU_MODE_HALT);
			if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
				break;
		}

		tw32(offset + CPU_STATE, 0xffffffff);
		tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
		udelay(10);
	} else {
		for (i = 0; i < 10000; i++) {
			tw32(offset + CPU_STATE, 0xffffffff);
			tw32(offset + CPU_MODE,  CPU_MODE_HALT);
			if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
				break;
		}
	}

	if (i >= 10000) {
		printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
		       "and %s CPU\n",
		       tp->dev->name,
		       (offset == RX_CPU_BASE ? "RX" : "TX"));
		return -ENODEV;
	}
M
Michael Chan 已提交
6415 6416 6417 6418

	/* Clear firmware's nvram arbitration. */
	if (tp->tg3_flags & TG3_FLAG_NVRAM)
		tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
L
Linus Torvalds 已提交
6419 6420 6421 6422
	return 0;
}

struct fw_info {
6423 6424 6425
	unsigned int fw_base;
	unsigned int fw_len;
	const __be32 *fw_data;
L
Linus Torvalds 已提交
6426 6427 6428 6429 6430 6431
};

/* tp->lock is held. */
static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
				 int cpu_scratch_size, struct fw_info *info)
{
M
Michael Chan 已提交
6432
	int err, lock_err, i;
L
Linus Torvalds 已提交
6433 6434 6435 6436 6437 6438 6439 6440 6441 6442 6443 6444 6445 6446 6447
	void (*write_op)(struct tg3 *, u32, u32);

	if (cpu_base == TX_CPU_BASE &&
	    (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
		printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
		       "TX cpu firmware on %s which is 5705.\n",
		       tp->dev->name);
		return -EINVAL;
	}

	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
		write_op = tg3_write_mem;
	else
		write_op = tg3_write_indirect_reg32;

6448 6449 6450
	/* It is possible that bootcode is still loading at this point.
	 * Get the nvram lock first before halting the cpu.
	 */
M
Michael Chan 已提交
6451
	lock_err = tg3_nvram_lock(tp);
L
Linus Torvalds 已提交
6452
	err = tg3_halt_cpu(tp, cpu_base);
M
Michael Chan 已提交
6453 6454
	if (!lock_err)
		tg3_nvram_unlock(tp);
L
Linus Torvalds 已提交
6455 6456 6457 6458 6459 6460 6461
	if (err)
		goto out;

	for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
		write_op(tp, cpu_scratch_base + i, 0);
	tw32(cpu_base + CPU_STATE, 0xffffffff);
	tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6462
	for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
L
Linus Torvalds 已提交
6463
		write_op(tp, (cpu_scratch_base +
6464
			      (info->fw_base & 0xffff) +
L
Linus Torvalds 已提交
6465
			      (i * sizeof(u32))),
6466
			      be32_to_cpu(info->fw_data[i]));
L
Linus Torvalds 已提交
6467 6468 6469 6470 6471 6472 6473 6474 6475 6476 6477

	err = 0;

out:
	return err;
}

/* tp->lock is held. */
static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
{
	struct fw_info info;
6478
	const __be32 *fw_data;
L
Linus Torvalds 已提交
6479 6480
	int err, i;

6481 6482 6483 6484 6485 6486 6487 6488 6489 6490 6491
	fw_data = (void *)tp->fw->data;

	/* Firmware blob starts with version numbers, followed by
	   start address and length. We are setting complete length.
	   length = end_address_of_bss - start_address_of_text.
	   Remainder is the blob to be loaded contiguously
	   from start address. */

	info.fw_base = be32_to_cpu(fw_data[1]);
	info.fw_len = tp->fw->size - 12;
	info.fw_data = &fw_data[3];
L
Linus Torvalds 已提交
6492 6493 6494 6495 6496 6497 6498 6499 6500 6501 6502 6503 6504 6505 6506

	err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
				    RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
				    &info);
	if (err)
		return err;

	err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
				    TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
				    &info);
	if (err)
		return err;

	/* Now startup only the RX cpu. */
	tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6507
	tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
L
Linus Torvalds 已提交
6508 6509

	for (i = 0; i < 5; i++) {
6510
		if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
L
Linus Torvalds 已提交
6511 6512 6513
			break;
		tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
		tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6514
		tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
L
Linus Torvalds 已提交
6515 6516 6517 6518 6519 6520
		udelay(1000);
	}
	if (i >= 5) {
		printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
		       "to set RX CPU PC, is %08x should be %08x\n",
		       tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6521
		       info.fw_base);
L
Linus Torvalds 已提交
6522 6523 6524 6525 6526 6527 6528 6529 6530 6531 6532 6533 6534 6535
		return -ENODEV;
	}
	tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
	tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);

	return 0;
}

/* 5705 needs a special version of the TSO firmware.  */

/* tp->lock is held. */
static int tg3_load_tso_firmware(struct tg3 *tp)
{
	struct fw_info info;
6536
	const __be32 *fw_data;
L
Linus Torvalds 已提交
6537 6538 6539 6540 6541 6542
	unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
	int err, i;

	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
		return 0;

6543 6544 6545 6546 6547 6548 6549 6550 6551 6552 6553 6554 6555
	fw_data = (void *)tp->fw->data;

	/* Firmware blob starts with version numbers, followed by
	   start address and length. We are setting complete length.
	   length = end_address_of_bss - start_address_of_text.
	   Remainder is the blob to be loaded contiguously
	   from start address. */

	info.fw_base = be32_to_cpu(fw_data[1]);
	cpu_scratch_size = tp->fw_len;
	info.fw_len = tp->fw->size - 12;
	info.fw_data = &fw_data[3];

L
Linus Torvalds 已提交
6556 6557 6558 6559 6560 6561 6562 6563 6564 6565 6566 6567 6568 6569 6570 6571 6572
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
		cpu_base = RX_CPU_BASE;
		cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
	} else {
		cpu_base = TX_CPU_BASE;
		cpu_scratch_base = TX_CPU_SCRATCH_BASE;
		cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
	}

	err = tg3_load_firmware_cpu(tp, cpu_base,
				    cpu_scratch_base, cpu_scratch_size,
				    &info);
	if (err)
		return err;

	/* Now startup the cpu. */
	tw32(cpu_base + CPU_STATE, 0xffffffff);
6573
	tw32_f(cpu_base + CPU_PC, info.fw_base);
L
Linus Torvalds 已提交
6574 6575

	for (i = 0; i < 5; i++) {
6576
		if (tr32(cpu_base + CPU_PC) == info.fw_base)
L
Linus Torvalds 已提交
6577 6578 6579
			break;
		tw32(cpu_base + CPU_STATE, 0xffffffff);
		tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6580
		tw32_f(cpu_base + CPU_PC, info.fw_base);
L
Linus Torvalds 已提交
6581 6582 6583 6584 6585 6586
		udelay(1000);
	}
	if (i >= 5) {
		printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
		       "to set CPU PC, is %08x should be %08x\n",
		       tp->dev->name, tr32(cpu_base + CPU_PC),
6587
		       info.fw_base);
L
Linus Torvalds 已提交
6588 6589 6590 6591 6592 6593 6594 6595 6596 6597 6598 6599
		return -ENODEV;
	}
	tw32(cpu_base + CPU_STATE, 0xffffffff);
	tw32_f(cpu_base + CPU_MODE,  0x00000000);
	return 0;
}


static int tg3_set_mac_addr(struct net_device *dev, void *p)
{
	struct tg3 *tp = netdev_priv(dev);
	struct sockaddr *addr = p;
6600
	int err = 0, skip_mac_1 = 0;
L
Linus Torvalds 已提交
6601

M
Michael Chan 已提交
6602 6603 6604
	if (!is_valid_ether_addr(addr->sa_data))
		return -EINVAL;

L
Linus Torvalds 已提交
6605 6606
	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);

6607 6608 6609
	if (!netif_running(dev))
		return 0;

6610
	if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6611
		u32 addr0_high, addr0_low, addr1_high, addr1_low;
6612

6613 6614 6615 6616 6617 6618 6619 6620 6621
		addr0_high = tr32(MAC_ADDR_0_HIGH);
		addr0_low = tr32(MAC_ADDR_0_LOW);
		addr1_high = tr32(MAC_ADDR_1_HIGH);
		addr1_low = tr32(MAC_ADDR_1_LOW);

		/* Skip MAC addr 1 if ASF is using it. */
		if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
		    !(addr1_high == 0 && addr1_low == 0))
			skip_mac_1 = 1;
6622
	}
6623 6624 6625
	spin_lock_bh(&tp->lock);
	__tg3_set_mac_addr(tp, skip_mac_1);
	spin_unlock_bh(&tp->lock);
L
Linus Torvalds 已提交
6626

M
Michael Chan 已提交
6627
	return err;
L
Linus Torvalds 已提交
6628 6629 6630 6631 6632 6633 6634 6635 6636 6637 6638 6639 6640 6641 6642 6643 6644 6645 6646 6647 6648 6649 6650 6651
}

/* tp->lock is held. */
static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
			   dma_addr_t mapping, u32 maxlen_flags,
			   u32 nic_addr)
{
	tg3_write_mem(tp,
		      (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
		      ((u64) mapping >> 32));
	tg3_write_mem(tp,
		      (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
		      ((u64) mapping & 0xffffffff));
	tg3_write_mem(tp,
		      (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
		       maxlen_flags);

	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
		tg3_write_mem(tp,
			      (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
			      nic_addr);
}

static void __tg3_set_rx_mode(struct net_device *);
M
Michael Chan 已提交
6652
static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6653 6654 6655 6656 6657 6658 6659 6660 6661 6662 6663 6664 6665 6666 6667 6668 6669 6670 6671 6672
{
	tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
	tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
	tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
	tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
		tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
		tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
	}
	tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
	tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
		u32 val = ec->stats_block_coalesce_usecs;

		if (!netif_carrier_ok(tp->dev))
			val = 0;

		tw32(HOSTCC_STAT_COAL_TICKS, val);
	}
}
L
Linus Torvalds 已提交
6673 6674

/* tp->lock is held. */
6675
static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
L
Linus Torvalds 已提交
6676 6677 6678 6679 6680 6681 6682 6683 6684 6685 6686
{
	u32 val, rdmac_mode;
	int i, err, limit;

	tg3_disable_ints(tp);

	tg3_stop_fw(tp);

	tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);

	if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6687
		tg3_abort_hw(tp, 1);
L
Linus Torvalds 已提交
6688 6689
	}

M
Matt Carlson 已提交
6690 6691
	if (reset_phy &&
	    !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6692 6693
		tg3_phy_reset(tp);

L
Linus Torvalds 已提交
6694 6695 6696 6697 6698 6699
	err = tg3_chip_reset(tp);
	if (err)
		return err;

	tg3_write_sig_legacy(tp, RESET_KIND_INIT);

6700
	if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
M
Matt Carlson 已提交
6701 6702 6703
		val = tr32(TG3_CPMU_CTRL);
		val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
		tw32(TG3_CPMU_CTRL, val);
6704 6705 6706 6707 6708 6709 6710 6711 6712 6713 6714 6715 6716 6717 6718

		val = tr32(TG3_CPMU_LSPD_10MB_CLK);
		val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
		val |= CPMU_LSPD_10MB_MACCLK_6_25;
		tw32(TG3_CPMU_LSPD_10MB_CLK, val);

		val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
		val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
		val |= CPMU_LNK_AWARE_MACCLK_6_25;
		tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);

		val = tr32(TG3_CPMU_HST_ACC);
		val &= ~CPMU_HST_ACC_MACCLK_MASK;
		val |= CPMU_HST_ACC_MACCLK_6_25;
		tw32(TG3_CPMU_HST_ACC, val);
M
Matt Carlson 已提交
6719 6720
	}

M
Matt Carlson 已提交
6721 6722 6723 6724 6725 6726 6727
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
		val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
		val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
		       PCIE_PWR_MGMT_L1_THRESH_4MS;
		tw32(PCIE_PWR_MGMT_THRESH, val);
	}

L
Linus Torvalds 已提交
6728 6729 6730
	/* This works around an issue with Athlon chipsets on
	 * B3 tigon3 silicon.  This bit has no effect on any
	 * other revision.  But do not set this on PCI Express
6731
	 * chips and don't even touch the clocks if the CPMU is present.
L
Linus Torvalds 已提交
6732
	 */
6733 6734 6735 6736 6737
	if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
		if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
			tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
		tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
	}
L
Linus Torvalds 已提交
6738 6739 6740 6741 6742 6743 6744 6745

	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
		val = tr32(TG3PCI_PCISTATE);
		val |= PCISTATE_RETRY_SAME_DMA;
		tw32(TG3PCI_PCISTATE, val);
	}

M
Matt Carlson 已提交
6746 6747 6748 6749 6750 6751 6752 6753 6754 6755
	if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
		/* Allow reads and writes to the
		 * APE register and memory space.
		 */
		val = tr32(TG3PCI_PCISTATE);
		val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
		       PCISTATE_ALLOW_APE_SHMEM_WR;
		tw32(TG3PCI_PCISTATE, val);
	}

L
Linus Torvalds 已提交
6756 6757 6758 6759 6760 6761 6762 6763 6764 6765 6766 6767
	if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
		/* Enable some hw fixes.  */
		val = tr32(TG3PCI_MSI_DATA);
		val |= (1 << 26) | (1 << 28) | (1 << 29);
		tw32(TG3PCI_MSI_DATA, val);
	}

	/* Descriptor ring init may make accesses to the
	 * NIC SRAM area to setup the TX descriptors, so we
	 * can only do this after the hardware has been
	 * successfully reset.
	 */
6768 6769 6770
	err = tg3_init_rings(tp);
	if (err)
		return err;
L
Linus Torvalds 已提交
6771

M
Matt Carlson 已提交
6772
	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
M
Matt Carlson 已提交
6773
	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
M
Matt Carlson 已提交
6774 6775 6776 6777 6778
		/* This value is determined during the probe time DMA
		 * engine test, tg3_test_dma.
		 */
		tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
	}
L
Linus Torvalds 已提交
6779 6780 6781 6782 6783 6784

	tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
			  GRC_MODE_4X_NIC_SEND_RINGS |
			  GRC_MODE_NO_TX_PHDR_CSUM |
			  GRC_MODE_NO_RX_PHDR_CSUM);
	tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6785 6786 6787 6788 6789 6790 6791 6792

	/* Pseudo-header checksum is done by hardware logic and not
	 * the offload processers, so make the chip do the pseudo-
	 * header checksums on receive.  For transmit it is more
	 * convenient to do the pseudo-header checksum in software
	 * as Linux does that on transmit for us in all cases.
	 */
	tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
L
Linus Torvalds 已提交
6793 6794 6795 6796 6797 6798 6799 6800 6801 6802 6803 6804

	tw32(GRC_MODE,
	     tp->grc_mode |
	     (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));

	/* Setup the timer prescalar register.  Clock is always 66Mhz. */
	val = tr32(GRC_MISC_CFG);
	val &= ~0xff;
	val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
	tw32(GRC_MISC_CFG, val);

	/* Initialize MBUF/DESC pool. */
6805
	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
L
Linus Torvalds 已提交
6806 6807 6808 6809 6810 6811 6812 6813 6814 6815 6816 6817 6818
		/* Do nothing.  */
	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
		tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
			tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
		else
			tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
		tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
		tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
	}
	else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
		int fw_len;

6819
		fw_len = tp->fw_len;
L
Linus Torvalds 已提交
6820 6821 6822 6823 6824 6825 6826
		fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
		tw32(BUFMGR_MB_POOL_ADDR,
		     NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
		tw32(BUFMGR_MB_POOL_SIZE,
		     NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
	}

6827
	if (tp->dev->mtu <= ETH_DATA_LEN) {
L
Linus Torvalds 已提交
6828 6829 6830 6831 6832 6833 6834 6835 6836 6837 6838 6839 6840 6841 6842 6843 6844 6845 6846 6847 6848 6849 6850 6851 6852 6853 6854 6855 6856 6857 6858 6859
		tw32(BUFMGR_MB_RDMA_LOW_WATER,
		     tp->bufmgr_config.mbuf_read_dma_low_water);
		tw32(BUFMGR_MB_MACRX_LOW_WATER,
		     tp->bufmgr_config.mbuf_mac_rx_low_water);
		tw32(BUFMGR_MB_HIGH_WATER,
		     tp->bufmgr_config.mbuf_high_water);
	} else {
		tw32(BUFMGR_MB_RDMA_LOW_WATER,
		     tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
		tw32(BUFMGR_MB_MACRX_LOW_WATER,
		     tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
		tw32(BUFMGR_MB_HIGH_WATER,
		     tp->bufmgr_config.mbuf_high_water_jumbo);
	}
	tw32(BUFMGR_DMA_LOW_WATER,
	     tp->bufmgr_config.dma_low_water);
	tw32(BUFMGR_DMA_HIGH_WATER,
	     tp->bufmgr_config.dma_high_water);

	tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
	for (i = 0; i < 2000; i++) {
		if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
			break;
		udelay(10);
	}
	if (i >= 2000) {
		printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
		       tp->dev->name);
		return -ENODEV;
	}

	/* Setup replenish threshold. */
M
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	val = tp->rx_pending / 8;
	if (val == 0)
		val = 1;
	else if (val > tp->rx_std_max_post)
		val = tp->rx_std_max_post;
M
Michael Chan 已提交
6865 6866 6867 6868 6869 6870 6871
	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
		if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
			tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);

		if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
			val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
	}
M
Michael Chan 已提交
6872 6873

	tw32(RCVBDI_STD_THRESH, val);
L
Linus Torvalds 已提交
6874 6875 6876 6877 6878 6879 6880 6881 6882 6883 6884 6885 6886 6887 6888 6889 6890 6891 6892 6893 6894 6895 6896 6897 6898 6899 6900 6901 6902 6903 6904 6905 6906 6907 6908 6909 6910 6911 6912 6913 6914

	/* Initialize TG3_BDINFO's at:
	 *  RCVDBDI_STD_BD:	standard eth size rx ring
	 *  RCVDBDI_JUMBO_BD:	jumbo frame rx ring
	 *  RCVDBDI_MINI_BD:	small frame rx ring (??? does not work)
	 *
	 * like so:
	 *  TG3_BDINFO_HOST_ADDR:	high/low parts of DMA address of ring
	 *  TG3_BDINFO_MAXLEN_FLAGS:	(rx max buffer size << 16) |
	 *                              ring attribute flags
	 *  TG3_BDINFO_NIC_ADDR:	location of descriptors in nic SRAM
	 *
	 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
	 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
	 *
	 * The size of each ring is fixed in the firmware, but the location is
	 * configurable.
	 */
	tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
	     ((u64) tp->rx_std_mapping >> 32));
	tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
	     ((u64) tp->rx_std_mapping & 0xffffffff));
	tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
	     NIC_SRAM_RX_BUFFER_DESC);

	/* Don't even try to program the JUMBO/MINI buffer descriptor
	 * configs on 5705.
	 */
	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
		tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
		     RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
	} else {
		tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
		     RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);

		tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
		     BDINFO_FLAGS_DISABLED);

		/* Setup replenish threshold. */
		tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);

6915
		if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
L
Linus Torvalds 已提交
6916 6917 6918 6919 6920 6921 6922 6923 6924 6925 6926 6927 6928 6929 6930 6931 6932 6933 6934 6935 6936 6937 6938 6939 6940 6941 6942 6943 6944 6945 6946 6947 6948 6949 6950 6951 6952 6953 6954 6955 6956 6957 6958 6959 6960 6961 6962 6963 6964 6965 6966 6967 6968 6969 6970 6971 6972 6973 6974 6975
			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
			     ((u64) tp->rx_jumbo_mapping >> 32));
			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
			     ((u64) tp->rx_jumbo_mapping & 0xffffffff));
			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
			     RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
			     NIC_SRAM_RX_JUMBO_BUFFER_DESC);
		} else {
			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
			     BDINFO_FLAGS_DISABLED);
		}

	}

	/* There is only one send ring on 5705/5750, no need to explicitly
	 * disable the others.
	 */
	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
		/* Clear out send RCB ring in SRAM. */
		for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
			tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
				      BDINFO_FLAGS_DISABLED);
	}

	tp->tx_prod = 0;
	tp->tx_cons = 0;
	tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
	tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);

	tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
		       tp->tx_desc_mapping,
		       (TG3_TX_RING_SIZE <<
			BDINFO_FLAGS_MAXLEN_SHIFT),
		       NIC_SRAM_TX_BUFFER_DESC);

	/* There is only one receive return ring on 5705/5750, no need
	 * to explicitly disable the others.
	 */
	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
		for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
		     i += TG3_BDINFO_SIZE) {
			tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
				      BDINFO_FLAGS_DISABLED);
		}
	}

	tp->rx_rcb_ptr = 0;
	tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);

	tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
		       tp->rx_rcb_mapping,
		       (TG3_RX_RCB_RING_SIZE(tp) <<
			BDINFO_FLAGS_MAXLEN_SHIFT),
		       0);

	tp->rx_std_ptr = tp->rx_pending;
	tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
		     tp->rx_std_ptr);

6976
	tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
L
Linus Torvalds 已提交
6977 6978 6979 6980 6981
						tp->rx_jumbo_pending : 0;
	tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
		     tp->rx_jumbo_ptr);

	/* Initialize MAC address and backoff seed. */
6982
	__tg3_set_mac_addr(tp, 0);
L
Linus Torvalds 已提交
6983 6984

	/* MTU + ethernet header + FCS + optional VLAN tag */
6985 6986
	tw32(MAC_RX_MTU_SIZE,
	     tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
L
Linus Torvalds 已提交
6987 6988 6989 6990 6991 6992 6993 6994 6995 6996 6997 6998 6999 7000 7001 7002 7003 7004 7005 7006 7007

	/* The slot time is changed by tg3_setup_phy if we
	 * run at gigabit with half duplex.
	 */
	tw32(MAC_TX_LENGTHS,
	     (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
	     (6 << TX_LENGTHS_IPG_SHIFT) |
	     (32 << TX_LENGTHS_SLOT_TIME_SHIFT));

	/* Receive rules. */
	tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
	tw32(RCVLPC_CONFIG, 0x0181);

	/* Calculate RDMAC_MODE setting early, we need it to determine
	 * the RCVLPC_STATE_ENABLE mask.
	 */
	rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
		      RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
		      RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
		      RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
		      RDMAC_MODE_LNGREAD_ENAB);
M
Michael Chan 已提交
7008

M
Matt Carlson 已提交
7009
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
M
Matt Carlson 已提交
7010 7011
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
M
Matt Carlson 已提交
7012 7013 7014 7015
		rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
			      RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
			      RDMAC_MODE_MBUF_SBD_CRPT_ENAB;

M
Michael Chan 已提交
7016 7017 7018 7019
	/* If statement applies to 5705 and 5750 PCI devices only */
	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
L
Linus Torvalds 已提交
7020
		if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
M
Matt Carlson 已提交
7021
		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
L
Linus Torvalds 已提交
7022 7023 7024 7025 7026 7027 7028
			rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
		} else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
			   !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
			rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
		}
	}

M
Michael Chan 已提交
7029 7030 7031
	if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
		rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;

L
Linus Torvalds 已提交
7032
	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
M
Matt Carlson 已提交
7033 7034 7035 7036 7037
		rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
		rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
L
Linus Torvalds 已提交
7038 7039

	/* Receive/send statistics. */
7040 7041 7042 7043 7044 7045
	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
		val = tr32(RCVLPC_STATS_ENABLE);
		val &= ~RCVLPC_STATSENAB_DACK_FIX;
		tw32(RCVLPC_STATS_ENABLE, val);
	} else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
		   (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
L
Linus Torvalds 已提交
7046 7047 7048 7049 7050 7051 7052 7053 7054 7055 7056 7057 7058 7059 7060 7061 7062 7063 7064 7065
		val = tr32(RCVLPC_STATS_ENABLE);
		val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
		tw32(RCVLPC_STATS_ENABLE, val);
	} else {
		tw32(RCVLPC_STATS_ENABLE, 0xffffff);
	}
	tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
	tw32(SNDDATAI_STATSENAB, 0xffffff);
	tw32(SNDDATAI_STATSCTRL,
	     (SNDDATAI_SCTRL_ENABLE |
	      SNDDATAI_SCTRL_FASTUPD));

	/* Setup host coalescing engine. */
	tw32(HOSTCC_MODE, 0);
	for (i = 0; i < 2000; i++) {
		if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
			break;
		udelay(10);
	}

M
Michael Chan 已提交
7066
	__tg3_set_coalesce(tp, &tp->coal);
L
Linus Torvalds 已提交
7067 7068 7069 7070 7071 7072 7073 7074 7075 7076 7077 7078 7079 7080 7081 7082 7083 7084 7085 7086 7087 7088 7089 7090 7091 7092 7093 7094 7095 7096 7097 7098 7099 7100 7101 7102

	/* set status block DMA address */
	tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
	     ((u64) tp->status_mapping >> 32));
	tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
	     ((u64) tp->status_mapping & 0xffffffff));

	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
		/* Status/statistics block address.  See tg3_timer,
		 * the tg3_periodic_fetch_stats call there, and
		 * tg3_get_stats to see how this works for 5705/5750 chips.
		 */
		tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
		     ((u64) tp->stats_mapping >> 32));
		tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
		     ((u64) tp->stats_mapping & 0xffffffff));
		tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
		tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
	}

	tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);

	tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
	tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
		tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);

	/* Clear statistics/status block in chip, and status block in ram. */
	for (i = NIC_SRAM_STATS_BLK;
	     i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
	     i += sizeof(u32)) {
		tg3_write_mem(tp, i, 0);
		udelay(40);
	}
	memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);

M
Michael Chan 已提交
7103 7104 7105 7106 7107 7108 7109
	if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
		tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
		/* reset to prevent losing 1st rx packet intermittently */
		tw32_f(MAC_RX_MODE, RX_MODE_RESET);
		udelay(10);
	}

7110 7111 7112 7113 7114
	if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
		tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
	else
		tp->mac_mode = 0;
	tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
L
Linus Torvalds 已提交
7115
		MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
M
Matt Carlson 已提交
7116 7117 7118 7119
	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
	    !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
		tp->mac_mode |= MAC_MODE_LINK_POLARITY;
L
Linus Torvalds 已提交
7120 7121 7122
	tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
	udelay(40);

M
Michael Chan 已提交
7123
	/* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
M
Michael Chan 已提交
7124
	 * If TG3_FLG2_IS_NIC is zero, we should read the
M
Michael Chan 已提交
7125 7126 7127 7128
	 * register to preserve the GPIO settings for LOMs. The GPIOs,
	 * whether used as inputs or outputs, are set by boot code after
	 * reset.
	 */
M
Michael Chan 已提交
7129
	if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
M
Michael Chan 已提交
7130 7131
		u32 gpio_mask;

M
Michael Chan 已提交
7132 7133 7134
		gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
			    GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
			    GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
M
Michael Chan 已提交
7135 7136 7137 7138 7139

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
			gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
				     GRC_LCLCTRL_GPIO_OUTPUT3;

M
Michael Chan 已提交
7140 7141 7142
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
			gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;

7143
		tp->grc_local_ctrl &= ~gpio_mask;
M
Michael Chan 已提交
7144 7145 7146
		tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;

		/* GPIO1 must be driven high for eeprom write protect */
M
Michael Chan 已提交
7147 7148 7149
		if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
			tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
					       GRC_LCLCTRL_GPIO_OUTPUT1);
M
Michael Chan 已提交
7150
	}
L
Linus Torvalds 已提交
7151 7152 7153
	tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
	udelay(100);

M
Michael Chan 已提交
7154
	tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
L
Linus Torvalds 已提交
7155 7156 7157 7158 7159 7160 7161 7162 7163 7164 7165 7166

	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
		tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
		udelay(40);
	}

	val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
	       WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
	       WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
	       WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
	       WDMAC_MODE_LNGREAD_ENAB);

M
Michael Chan 已提交
7167 7168 7169 7170
	/* If statement applies to 5705 and 5750 PCI devices only */
	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
L
Linus Torvalds 已提交
7171 7172 7173 7174 7175 7176 7177 7178 7179 7180 7181
		if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
		    (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
		     tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
			/* nothing */
		} else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
			   !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
			   !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
			val |= WDMAC_MODE_RX_ACCEL;
		}
	}

7182
	/* Enable host coalescing bug fix */
M
Matt Carlson 已提交
7183
	if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
M
Matt Carlson 已提交
7184
		val |= WDMAC_MODE_STATUS_TAG_FIX;
7185

L
Linus Torvalds 已提交
7186 7187 7188
	tw32_f(WDMAC_MODE, val);
	udelay(40);

M
Matt Carlson 已提交
7189 7190 7191 7192 7193
	if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
		u16 pcix_cmd;

		pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
				     &pcix_cmd);
L
Linus Torvalds 已提交
7194
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
M
Matt Carlson 已提交
7195 7196
			pcix_cmd &= ~PCI_X_CMD_MAX_READ;
			pcix_cmd |= PCI_X_CMD_READ_2K;
L
Linus Torvalds 已提交
7197
		} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
M
Matt Carlson 已提交
7198 7199
			pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
			pcix_cmd |= PCI_X_CMD_READ_2K;
L
Linus Torvalds 已提交
7200
		}
M
Matt Carlson 已提交
7201 7202
		pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
				      pcix_cmd);
L
Linus Torvalds 已提交
7203 7204 7205 7206 7207 7208 7209 7210
	}

	tw32_f(RDMAC_MODE, rdmac_mode);
	udelay(40);

	tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
		tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
M
Matt Carlson 已提交
7211 7212 7213 7214 7215 7216 7217

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
		tw32(SNDDATAC_MODE,
		     SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
	else
		tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);

L
Linus Torvalds 已提交
7218 7219 7220 7221 7222 7223 7224 7225 7226 7227 7228 7229 7230 7231 7232 7233 7234 7235 7236 7237 7238 7239 7240 7241 7242 7243
	tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
	tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
	tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
	tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
		tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
	tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
	tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);

	if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
		err = tg3_load_5701_a0_firmware_fix(tp);
		if (err)
			return err;
	}

	if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
		err = tg3_load_tso_firmware(tp);
		if (err)
			return err;
	}

	tp->tx_mode = TX_MODE_ENABLE;
	tw32_f(MAC_TX_MODE, tp->tx_mode);
	udelay(100);

	tp->rx_mode = RX_MODE_ENABLE;
M
Matt Carlson 已提交
7244
	if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
M
Michael Chan 已提交
7245 7246
		tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;

L
Linus Torvalds 已提交
7247 7248 7249 7250 7251 7252
	tw32_f(MAC_RX_MODE, tp->rx_mode);
	udelay(10);

	tw32(MAC_LED_CTRL, tp->led_ctrl);

	tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
M
Michael Chan 已提交
7253
	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
L
Linus Torvalds 已提交
7254 7255 7256 7257 7258 7259 7260 7261 7262 7263 7264 7265 7266 7267 7268 7269 7270 7271 7272 7273 7274 7275 7276 7277 7278 7279 7280 7281 7282 7283 7284
		tw32_f(MAC_RX_MODE, RX_MODE_RESET);
		udelay(10);
	}
	tw32_f(MAC_RX_MODE, tp->rx_mode);
	udelay(10);

	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
		if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
			!(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
			/* Set drive transmission level to 1.2V  */
			/* only if the signal pre-emphasis bit is not set  */
			val = tr32(MAC_SERDES_CFG);
			val &= 0xfffff000;
			val |= 0x880;
			tw32(MAC_SERDES_CFG, val);
		}
		if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
			tw32(MAC_SERDES_CFG, 0x616000);
	}

	/* Prevent chip from dropping frames when flow control
	 * is enabled.
	 */
	tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
	    (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
		/* Use hardware link auto-negotiation */
		tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
	}

7285 7286 7287 7288 7289 7290 7291 7292 7293 7294 7295
	if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
		u32 tmp;

		tmp = tr32(SERDES_RX_CTRL);
		tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
		tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
		tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
		tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
	}

M
Matt Carlson 已提交
7296 7297 7298 7299 7300 7301 7302
	if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
		if (tp->link_config.phy_is_low_power) {
			tp->link_config.phy_is_low_power = 0;
			tp->link_config.speed = tp->link_config.orig_speed;
			tp->link_config.duplex = tp->link_config.orig_duplex;
			tp->link_config.autoneg = tp->link_config.orig_autoneg;
		}
L
Linus Torvalds 已提交
7303

M
Matt Carlson 已提交
7304 7305 7306
		err = tg3_setup_phy(tp, 0);
		if (err)
			return err;
L
Linus Torvalds 已提交
7307

M
Matt Carlson 已提交
7308 7309 7310 7311 7312 7313 7314 7315 7316 7317
		if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
		    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
			u32 tmp;

			/* Clear CRC stats. */
			if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
				tg3_writephy(tp, MII_TG3_TEST1,
					     tmp | MII_TG3_TEST1_CRC_EN);
				tg3_readphy(tp, 0x14, &tmp);
			}
L
Linus Torvalds 已提交
7318 7319 7320 7321 7322 7323 7324 7325 7326 7327 7328
		}
	}

	__tg3_set_rx_mode(tp->dev);

	/* Initialize receive rules. */
	tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
	tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
	tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
	tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);

M
Michael Chan 已提交
7329
	if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
M
Michael Chan 已提交
7330
	    !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
L
Linus Torvalds 已提交
7331 7332 7333 7334 7335 7336 7337 7338 7339 7340 7341 7342 7343 7344 7345 7346 7347 7348 7349 7350 7351 7352 7353 7354 7355 7356 7357 7358 7359 7360 7361 7362 7363 7364 7365 7366 7367 7368 7369
		limit = 8;
	else
		limit = 16;
	if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
		limit -= 4;
	switch (limit) {
	case 16:
		tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
	case 15:
		tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
	case 14:
		tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
	case 13:
		tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
	case 12:
		tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
	case 11:
		tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
	case 10:
		tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
	case 9:
		tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
	case 8:
		tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
	case 7:
		tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
	case 6:
		tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
	case 5:
		tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
	case 4:
		/* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
	case 3:
		/* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
	case 2:
	case 1:

	default:
		break;
7370
	}
L
Linus Torvalds 已提交
7371

M
Matt Carlson 已提交
7372 7373 7374 7375
	if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
		/* Write our heartbeat update interval to APE. */
		tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
				APE_HOST_HEARTBEAT_INT_DISABLE);
M
Matt Carlson 已提交
7376

L
Linus Torvalds 已提交
7377 7378 7379 7380 7381 7382 7383 7384
	tg3_write_sig_post_reset(tp, RESET_KIND_INIT);

	return 0;
}

/* Called at device open time to get the chip ready for
 * packet processing.  Invoked with tp->lock held.
 */
7385
static int tg3_init_hw(struct tg3 *tp, int reset_phy)
L
Linus Torvalds 已提交
7386 7387 7388 7389 7390
{
	tg3_switch_clocks(tp);

	tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);

7391
	return tg3_reset_hw(tp, reset_phy);
L
Linus Torvalds 已提交
7392 7393 7394 7395 7396 7397 7398 7399 7400 7401 7402 7403 7404 7405 7406 7407 7408 7409 7410 7411 7412 7413 7414 7415 7416 7417 7418 7419 7420 7421 7422 7423 7424 7425 7426 7427 7428 7429 7430 7431 7432 7433 7434 7435
}

#define TG3_STAT_ADD32(PSTAT, REG) \
do {	u32 __val = tr32(REG); \
	(PSTAT)->low += __val; \
	if ((PSTAT)->low < __val) \
		(PSTAT)->high += 1; \
} while (0)

static void tg3_periodic_fetch_stats(struct tg3 *tp)
{
	struct tg3_hw_stats *sp = tp->hw_stats;

	if (!netif_carrier_ok(tp->dev))
		return;

	TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
	TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
	TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
	TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
	TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
	TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
	TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
	TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
	TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
	TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
	TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
	TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
	TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);

	TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
	TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
	TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
	TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
	TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
	TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
	TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
	TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
	TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
	TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
	TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
	TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
	TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
	TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7436 7437 7438 7439

	TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
	TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
	TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
L
Linus Torvalds 已提交
7440 7441 7442 7443 7444 7445
}

static void tg3_timer(unsigned long __opaque)
{
	struct tg3 *tp = (struct tg3 *) __opaque;

7446 7447 7448
	if (tp->irq_sync)
		goto restart_timer;

7449
	spin_lock(&tp->lock);
L
Linus Torvalds 已提交
7450

7451 7452 7453 7454 7455 7456 7457 7458 7459 7460 7461 7462
	if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
		/* All of this garbage is because when using non-tagged
		 * IRQ status the mailbox/status_block protocol the chip
		 * uses with the cpu is race prone.
		 */
		if (tp->hw_status->status & SD_STATUS_UPDATED) {
			tw32(GRC_LOCAL_CTRL,
			     tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
		} else {
			tw32(HOSTCC_MODE, tp->coalesce_mode |
			     (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
		}
L
Linus Torvalds 已提交
7463

7464 7465
		if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
			tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7466
			spin_unlock(&tp->lock);
7467 7468 7469
			schedule_work(&tp->reset_task);
			return;
		}
L
Linus Torvalds 已提交
7470 7471 7472 7473
	}

	/* This part only runs once per second. */
	if (!--tp->timer_counter) {
7474 7475 7476
		if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
			tg3_periodic_fetch_stats(tp);

L
Linus Torvalds 已提交
7477 7478 7479 7480 7481 7482 7483 7484 7485 7486 7487 7488 7489 7490 7491 7492 7493 7494 7495 7496 7497 7498 7499 7500 7501 7502 7503 7504 7505
		if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
			u32 mac_stat;
			int phy_event;

			mac_stat = tr32(MAC_STATUS);

			phy_event = 0;
			if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
				if (mac_stat & MAC_STATUS_MI_INTERRUPT)
					phy_event = 1;
			} else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
				phy_event = 1;

			if (phy_event)
				tg3_setup_phy(tp, 0);
		} else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
			u32 mac_stat = tr32(MAC_STATUS);
			int need_setup = 0;

			if (netif_carrier_ok(tp->dev) &&
			    (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
				need_setup = 1;
			}
			if (! netif_carrier_ok(tp->dev) &&
			    (mac_stat & (MAC_STATUS_PCS_SYNCED |
					 MAC_STATUS_SIGNAL_DET))) {
				need_setup = 1;
			}
			if (need_setup) {
M
Michael Chan 已提交
7506 7507 7508 7509 7510 7511 7512 7513
				if (!tp->serdes_counter) {
					tw32_f(MAC_MODE,
					     (tp->mac_mode &
					      ~MAC_MODE_PORT_MODE_MASK));
					udelay(40);
					tw32_f(MAC_MODE, tp->mac_mode);
					udelay(40);
				}
L
Linus Torvalds 已提交
7514 7515
				tg3_setup_phy(tp, 0);
			}
M
Michael Chan 已提交
7516 7517
		} else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
			tg3_serdes_parallel_detect(tp);
L
Linus Torvalds 已提交
7518 7519 7520 7521

		tp->timer_counter = tp->timer_multiplier;
	}

M
Michael Chan 已提交
7522 7523 7524 7525 7526 7527 7528 7529 7530 7531 7532 7533 7534 7535 7536 7537 7538
	/* Heartbeat is only sent once every 2 seconds.
	 *
	 * The heartbeat is to tell the ASF firmware that the host
	 * driver is still alive.  In the event that the OS crashes,
	 * ASF needs to reset the hardware to free up the FIFO space
	 * that may be filled with rx packets destined for the host.
	 * If the FIFO is full, ASF will no longer function properly.
	 *
	 * Unintended resets have been reported on real time kernels
	 * where the timer doesn't run on time.  Netpoll will also have
	 * same problem.
	 *
	 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
	 * to check the ring condition when the heartbeat is expiring
	 * before doing the reset.  This will prevent most unintended
	 * resets.
	 */
L
Linus Torvalds 已提交
7539
	if (!--tp->asf_counter) {
7540 7541
		if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
		    !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7542 7543
			tg3_wait_for_event_ack(tp);

7544
			tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
M
Michael Chan 已提交
7545
				      FWCMD_NICDRV_ALIVE3);
7546
			tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
M
Michael Chan 已提交
7547
			/* 5 seconds timeout */
7548
			tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
M
Matt Carlson 已提交
7549 7550

			tg3_generate_fw_event(tp);
L
Linus Torvalds 已提交
7551 7552 7553 7554
		}
		tp->asf_counter = tp->asf_multiplier;
	}

7555
	spin_unlock(&tp->lock);
L
Linus Torvalds 已提交
7556

7557
restart_timer:
L
Linus Torvalds 已提交
7558 7559 7560 7561
	tp->timer.expires = jiffies + tp->timer_offset;
	add_timer(&tp->timer);
}

7562
static int tg3_request_irq(struct tg3 *tp)
7563
{
7564
	irq_handler_t fn;
7565 7566 7567 7568 7569 7570 7571
	unsigned long flags;
	struct net_device *dev = tp->dev;

	if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
		fn = tg3_msi;
		if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
			fn = tg3_msi_1shot;
7572
		flags = IRQF_SAMPLE_RANDOM;
7573 7574 7575 7576
	} else {
		fn = tg3_interrupt;
		if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
			fn = tg3_interrupt_tagged;
7577
		flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7578 7579 7580 7581
	}
	return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
}

M
Michael Chan 已提交
7582 7583 7584
static int tg3_test_interrupt(struct tg3 *tp)
{
	struct net_device *dev = tp->dev;
7585
	int err, i, intr_ok = 0;
M
Michael Chan 已提交
7586

M
Michael Chan 已提交
7587 7588 7589
	if (!netif_running(dev))
		return -ENODEV;

M
Michael Chan 已提交
7590 7591 7592 7593 7594
	tg3_disable_ints(tp);

	free_irq(tp->pdev->irq, dev);

	err = request_irq(tp->pdev->irq, tg3_test_isr,
7595
			  IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
M
Michael Chan 已提交
7596 7597 7598
	if (err)
		return err;

7599
	tp->hw_status->status &= ~SD_STATUS_UPDATED;
M
Michael Chan 已提交
7600 7601 7602 7603 7604 7605
	tg3_enable_ints(tp);

	tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
	       HOSTCC_MODE_NOW);

	for (i = 0; i < 5; i++) {
7606 7607
		u32 int_mbox, misc_host_ctrl;

M
Michael Chan 已提交
7608 7609
		int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
					TG3_64BIT_REG_LOW);
7610 7611 7612 7613 7614
		misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);

		if ((int_mbox != 0) ||
		    (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
			intr_ok = 1;
M
Michael Chan 已提交
7615
			break;
7616 7617
		}

M
Michael Chan 已提交
7618 7619 7620 7621 7622 7623
		msleep(10);
	}

	tg3_disable_ints(tp);

	free_irq(tp->pdev->irq, dev);
7624

7625
	err = tg3_request_irq(tp);
M
Michael Chan 已提交
7626 7627 7628 7629

	if (err)
		return err;

7630
	if (intr_ok)
M
Michael Chan 已提交
7631 7632 7633 7634 7635 7636 7637 7638 7639 7640 7641 7642 7643 7644 7645 7646 7647 7648 7649 7650 7651 7652 7653 7654 7655 7656 7657 7658 7659 7660 7661 7662 7663 7664 7665 7666 7667 7668 7669 7670 7671 7672 7673 7674 7675 7676
		return 0;

	return -EIO;
}

/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
 * successfully restored
 */
static int tg3_test_msi(struct tg3 *tp)
{
	struct net_device *dev = tp->dev;
	int err;
	u16 pci_cmd;

	if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
		return 0;

	/* Turn off SERR reporting in case MSI terminates with Master
	 * Abort.
	 */
	pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
	pci_write_config_word(tp->pdev, PCI_COMMAND,
			      pci_cmd & ~PCI_COMMAND_SERR);

	err = tg3_test_interrupt(tp);

	pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);

	if (!err)
		return 0;

	/* other failures */
	if (err != -EIO)
		return err;

	/* MSI test failed, go back to INTx mode */
	printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
	       "switching to INTx mode. Please report this failure to "
	       "the PCI maintainer and include system chipset information.\n",
		       tp->dev->name);

	free_irq(tp->pdev->irq, dev);
	pci_disable_msi(tp->pdev);

	tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;

7677
	err = tg3_request_irq(tp);
M
Michael Chan 已提交
7678 7679 7680 7681 7682 7683
	if (err)
		return err;

	/* Need to reset the chip because the MSI cycle may have terminated
	 * with Master Abort.
	 */
7684
	tg3_full_lock(tp, 1);
M
Michael Chan 已提交
7685

M
Michael Chan 已提交
7686
	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7687
	err = tg3_init_hw(tp, 1);
M
Michael Chan 已提交
7688

7689
	tg3_full_unlock(tp);
M
Michael Chan 已提交
7690 7691 7692 7693 7694 7695 7696

	if (err)
		free_irq(tp->pdev->irq, dev);

	return err;
}

M
Matt Carlson 已提交
7697 7698 7699 7700 7701 7702 7703 7704 7705 7706 7707 7708 7709 7710 7711 7712 7713 7714 7715 7716 7717 7718 7719 7720 7721 7722 7723 7724 7725 7726 7727
static int tg3_request_firmware(struct tg3 *tp)
{
	const __be32 *fw_data;

	if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
		printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
		       tp->dev->name, tp->fw_needed);
		return -ENOENT;
	}

	fw_data = (void *)tp->fw->data;

	/* Firmware blob starts with version numbers, followed by
	 * start address and _full_ length including BSS sections
	 * (which must be longer than the actual data, of course
	 */

	tp->fw_len = be32_to_cpu(fw_data[2]);	/* includes bss */
	if (tp->fw_len < (tp->fw->size - 12)) {
		printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
		       tp->dev->name, tp->fw_len, tp->fw_needed);
		release_firmware(tp->fw);
		tp->fw = NULL;
		return -EINVAL;
	}

	/* We no longer need firmware; we have it. */
	tp->fw_needed = NULL;
	return 0;
}

L
Linus Torvalds 已提交
7728 7729 7730 7731 7732
static int tg3_open(struct net_device *dev)
{
	struct tg3 *tp = netdev_priv(dev);
	int err;

M
Matt Carlson 已提交
7733 7734 7735 7736 7737 7738 7739 7740 7741 7742 7743 7744 7745 7746 7747 7748
	if (tp->fw_needed) {
		err = tg3_request_firmware(tp);
		if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
			if (err)
				return err;
		} else if (err) {
			printk(KERN_WARNING "%s: TSO capability disabled.\n",
			       tp->dev->name);
			tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
		} else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
			printk(KERN_NOTICE "%s: TSO capability restored.\n",
			       tp->dev->name);
			tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
		}
	}

7749 7750
	netif_carrier_off(tp->dev);

M
Michael Chan 已提交
7751
	err = tg3_set_power_state(tp, PCI_D0);
7752
	if (err)
M
Michael Chan 已提交
7753
		return err;
7754 7755

	tg3_full_lock(tp, 0);
M
Michael Chan 已提交
7756

L
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7757 7758 7759
	tg3_disable_ints(tp);
	tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;

7760
	tg3_full_unlock(tp);
L
Linus Torvalds 已提交
7761 7762 7763 7764 7765 7766 7767 7768

	/* The placement of this call is tied
	 * to the setup and use of Host TX descriptors.
	 */
	err = tg3_alloc_consistent(tp);
	if (err)
		return err;

7769
	if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7770 7771 7772 7773 7774 7775 7776
		/* All MSI supporting chips should support tagged
		 * status.  Assert that this is the case.
		 */
		if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
			printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
			       "Not using MSI.\n", tp->dev->name);
		} else if (pci_enable_msi(tp->pdev) == 0) {
M
Michael Chan 已提交
7777 7778 7779 7780 7781 7782 7783
			u32 msi_mode;

			msi_mode = tr32(MSGINT_MODE);
			tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
			tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
		}
	}
7784
	err = tg3_request_irq(tp);
L
Linus Torvalds 已提交
7785 7786

	if (err) {
M
Michael Chan 已提交
7787 7788 7789 7790
		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
			pci_disable_msi(tp->pdev);
			tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
		}
L
Linus Torvalds 已提交
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		tg3_free_consistent(tp);
		return err;
	}

7795 7796
	napi_enable(&tp->napi);

7797
	tg3_full_lock(tp, 0);
L
Linus Torvalds 已提交
7798

7799
	err = tg3_init_hw(tp, 1);
L
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7800
	if (err) {
M
Michael Chan 已提交
7801
		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
L
Linus Torvalds 已提交
7802 7803
		tg3_free_rings(tp);
	} else {
7804 7805 7806 7807 7808 7809 7810 7811 7812
		if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
			tp->timer_offset = HZ;
		else
			tp->timer_offset = HZ / 10;

		BUG_ON(tp->timer_offset > HZ);
		tp->timer_counter = tp->timer_multiplier =
			(HZ / tp->timer_offset);
		tp->asf_counter = tp->asf_multiplier =
M
Michael Chan 已提交
7813
			((HZ / tp->timer_offset) * 2);
L
Linus Torvalds 已提交
7814 7815 7816 7817 7818 7819 7820

		init_timer(&tp->timer);
		tp->timer.expires = jiffies + tp->timer_offset;
		tp->timer.data = (unsigned long) tp;
		tp->timer.function = tg3_timer;
	}

7821
	tg3_full_unlock(tp);
L
Linus Torvalds 已提交
7822 7823

	if (err) {
7824
		napi_disable(&tp->napi);
M
Michael Chan 已提交
7825 7826 7827 7828 7829
		free_irq(tp->pdev->irq, dev);
		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
			pci_disable_msi(tp->pdev);
			tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
		}
L
Linus Torvalds 已提交
7830 7831 7832 7833
		tg3_free_consistent(tp);
		return err;
	}

M
Michael Chan 已提交
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	if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
		err = tg3_test_msi(tp);
7836

M
Michael Chan 已提交
7837
		if (err) {
7838
			tg3_full_lock(tp, 0);
M
Michael Chan 已提交
7839 7840 7841 7842 7843

			if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
				pci_disable_msi(tp->pdev);
				tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
			}
M
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7844
			tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
M
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7845 7846 7847
			tg3_free_rings(tp);
			tg3_free_consistent(tp);

7848
			tg3_full_unlock(tp);
M
Michael Chan 已提交
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7850 7851
			napi_disable(&tp->napi);

M
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7852 7853
			return err;
		}
7854 7855 7856

		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
			if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
M
Michael Chan 已提交
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				u32 val = tr32(PCIE_TRANSACTION_CFG);
7858

M
Michael Chan 已提交
7859 7860
				tw32(PCIE_TRANSACTION_CFG,
				     val | PCIE_TRANS_CFG_1SHOT_MSI);
7861 7862
			}
		}
M
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	}

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	tg3_phy_start(tp);

7867
	tg3_full_lock(tp, 0);
L
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7868

M
Michael Chan 已提交
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	add_timer(&tp->timer);
	tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
L
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7871 7872
	tg3_enable_ints(tp);

7873
	tg3_full_unlock(tp);
L
Linus Torvalds 已提交
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	netif_start_queue(dev);

	return 0;
}

#if 0
/*static*/ void tg3_dump_state(struct tg3 *tp)
{
	u32 val32, val32_2, val32_3, val32_4, val32_5;
	u16 val16;
	int i;

	pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
	printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
	       val16, val32);

	/* MAC block */
	printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
	       tr32(MAC_MODE), tr32(MAC_STATUS));
	printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
	       tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
	printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
	       tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
	printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
	       tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));

	/* Send data initiator control block */
	printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
	       tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
	printk("       SNDDATAI_STATSCTRL[%08x]\n",
	       tr32(SNDDATAI_STATSCTRL));

	/* Send data completion control block */
	printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));

	/* Send BD ring selector block */
	printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
	       tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));

	/* Send BD initiator control block */
	printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
	       tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));

	/* Send BD completion control block */
	printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));

	/* Receive list placement control block */
	printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
	       tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
	printk("       RCVLPC_STATSCTRL[%08x]\n",
	       tr32(RCVLPC_STATSCTRL));

	/* Receive data and receive BD initiator control block */
	printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
	       tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));

	/* Receive data completion control block */
	printk("DEBUG: RCVDCC_MODE[%08x]\n",
	       tr32(RCVDCC_MODE));

	/* Receive BD initiator control block */
	printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
	       tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));

	/* Receive BD completion control block */
	printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
	       tr32(RCVCC_MODE), tr32(RCVCC_STATUS));

	/* Receive list selector control block */
	printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
	       tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));

	/* Mbuf cluster free block */
	printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
	       tr32(MBFREE_MODE), tr32(MBFREE_STATUS));

	/* Host coalescing control block */
	printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
	       tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
	printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
	       tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
	       tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
	printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
	       tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
	       tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
	printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
	       tr32(HOSTCC_STATS_BLK_NIC_ADDR));
	printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
	       tr32(HOSTCC_STATUS_BLK_NIC_ADDR));

	/* Memory arbiter control block */
	printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
	       tr32(MEMARB_MODE), tr32(MEMARB_STATUS));

	/* Buffer manager control block */
	printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
	       tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
	printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
	       tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
	printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
	       "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
	       tr32(BUFMGR_DMA_DESC_POOL_ADDR),
	       tr32(BUFMGR_DMA_DESC_POOL_SIZE));

	/* Read DMA control block */
	printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
	       tr32(RDMAC_MODE), tr32(RDMAC_STATUS));

	/* Write DMA control block */
	printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
	       tr32(WDMAC_MODE), tr32(WDMAC_STATUS));

	/* DMA completion block */
	printk("DEBUG: DMAC_MODE[%08x]\n",
	       tr32(DMAC_MODE));

	/* GRC block */
	printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
	       tr32(GRC_MODE), tr32(GRC_MISC_CFG));
	printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
	       tr32(GRC_LOCAL_CTRL));

	/* TG3_BDINFOs */
	printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
	       tr32(RCVDBDI_JUMBO_BD + 0x0),
	       tr32(RCVDBDI_JUMBO_BD + 0x4),
	       tr32(RCVDBDI_JUMBO_BD + 0x8),
	       tr32(RCVDBDI_JUMBO_BD + 0xc));
	printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
	       tr32(RCVDBDI_STD_BD + 0x0),
	       tr32(RCVDBDI_STD_BD + 0x4),
	       tr32(RCVDBDI_STD_BD + 0x8),
	       tr32(RCVDBDI_STD_BD + 0xc));
	printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
	       tr32(RCVDBDI_MINI_BD + 0x0),
	       tr32(RCVDBDI_MINI_BD + 0x4),
	       tr32(RCVDBDI_MINI_BD + 0x8),
	       tr32(RCVDBDI_MINI_BD + 0xc));

	tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
	tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
	tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
	tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
	printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
	       val32, val32_2, val32_3, val32_4);

	tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
	tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
	tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
	tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
	printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
	       val32, val32_2, val32_3, val32_4);

	tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
	tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
	tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
	tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
	tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
	printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
	       val32, val32_2, val32_3, val32_4, val32_5);

	/* SW status block */
	printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
	       tp->hw_status->status,
	       tp->hw_status->status_tag,
	       tp->hw_status->rx_jumbo_consumer,
	       tp->hw_status->rx_consumer,
	       tp->hw_status->rx_mini_consumer,
	       tp->hw_status->idx[0].rx_producer,
	       tp->hw_status->idx[0].tx_consumer);

	/* SW statistics block */
	printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
	       ((u32 *)tp->hw_stats)[0],
	       ((u32 *)tp->hw_stats)[1],
	       ((u32 *)tp->hw_stats)[2],
	       ((u32 *)tp->hw_stats)[3]);

	/* Mailboxes */
	printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
M
Michael Chan 已提交
8056 8057 8058 8059
	       tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
	       tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
	       tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
	       tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
L
Linus Torvalds 已提交
8060 8061 8062 8063 8064 8065 8066 8067 8068 8069 8070 8071 8072 8073 8074 8075 8076 8077 8078 8079 8080 8081 8082 8083 8084 8085 8086 8087 8088 8089 8090 8091 8092 8093 8094 8095 8096 8097 8098 8099 8100 8101 8102 8103 8104 8105 8106 8107 8108 8109 8110 8111 8112 8113 8114

	/* NIC side send descriptors. */
	for (i = 0; i < 6; i++) {
		unsigned long txd;

		txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
			+ (i * sizeof(struct tg3_tx_buffer_desc));
		printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
		       i,
		       readl(txd + 0x0), readl(txd + 0x4),
		       readl(txd + 0x8), readl(txd + 0xc));
	}

	/* NIC side RX descriptors. */
	for (i = 0; i < 6; i++) {
		unsigned long rxd;

		rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
			+ (i * sizeof(struct tg3_rx_buffer_desc));
		printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
		       i,
		       readl(rxd + 0x0), readl(rxd + 0x4),
		       readl(rxd + 0x8), readl(rxd + 0xc));
		rxd += (4 * sizeof(u32));
		printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
		       i,
		       readl(rxd + 0x0), readl(rxd + 0x4),
		       readl(rxd + 0x8), readl(rxd + 0xc));
	}

	for (i = 0; i < 6; i++) {
		unsigned long rxd;

		rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
			+ (i * sizeof(struct tg3_rx_buffer_desc));
		printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
		       i,
		       readl(rxd + 0x0), readl(rxd + 0x4),
		       readl(rxd + 0x8), readl(rxd + 0xc));
		rxd += (4 * sizeof(u32));
		printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
		       i,
		       readl(rxd + 0x0), readl(rxd + 0x4),
		       readl(rxd + 0x8), readl(rxd + 0xc));
	}
}
#endif

static struct net_device_stats *tg3_get_stats(struct net_device *);
static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);

static int tg3_close(struct net_device *dev)
{
	struct tg3 *tp = netdev_priv(dev);

8115
	napi_disable(&tp->napi);
8116
	cancel_work_sync(&tp->reset_task);
M
Michael Chan 已提交
8117

L
Linus Torvalds 已提交
8118 8119 8120 8121
	netif_stop_queue(dev);

	del_timer_sync(&tp->timer);

8122
	tg3_full_lock(tp, 1);
L
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8123 8124 8125 8126 8127 8128
#if 0
	tg3_dump_state(tp);
#endif

	tg3_disable_ints(tp);

M
Michael Chan 已提交
8129
	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
L
Linus Torvalds 已提交
8130
	tg3_free_rings(tp);
8131
	tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
L
Linus Torvalds 已提交
8132

8133
	tg3_full_unlock(tp);
L
Linus Torvalds 已提交
8134

M
Michael Chan 已提交
8135 8136 8137 8138 8139
	free_irq(tp->pdev->irq, dev);
	if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
		pci_disable_msi(tp->pdev);
		tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
	}
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	memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
	       sizeof(tp->net_stats_prev));
	memcpy(&tp->estats_prev, tg3_get_estats(tp),
	       sizeof(tp->estats_prev));

	tg3_free_consistent(tp);

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	tg3_set_power_state(tp, PCI_D3hot);

	netif_carrier_off(tp->dev);

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	return 0;
}

static inline unsigned long get_stat64(tg3_stat64_t *val)
{
	unsigned long ret;

#if (BITS_PER_LONG == 32)
	ret = val->low;
#else
	ret = ((u64)val->high << 32) | ((u64)val->low);
#endif
	return ret;
}

8167 8168 8169 8170 8171
static inline u64 get_estat64(tg3_stat64_t *val)
{
       return ((u64)val->high << 32) | ((u64)val->low);
}

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static unsigned long calc_crc_errors(struct tg3 *tp)
{
	struct tg3_hw_stats *hw_stats = tp->hw_stats;

	if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
		u32 val;

8181
		spin_lock_bh(&tp->lock);
8182 8183 8184
		if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
			tg3_writephy(tp, MII_TG3_TEST1,
				     val | MII_TG3_TEST1_CRC_EN);
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			tg3_readphy(tp, 0x14, &val);
		} else
			val = 0;
8188
		spin_unlock_bh(&tp->lock);
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		tp->phy_crc_errors += val;

		return tp->phy_crc_errors;
	}

	return get_stat64(&hw_stats->rx_fcs_errors);
}

#define ESTAT_ADD(member) \
	estats->member =	old_estats->member + \
8200
				get_estat64(&hw_stats->member)
L
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static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
{
	struct tg3_ethtool_stats *estats = &tp->estats;
	struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
	struct tg3_hw_stats *hw_stats = tp->hw_stats;

	if (!hw_stats)
		return old_estats;

	ESTAT_ADD(rx_octets);
	ESTAT_ADD(rx_fragments);
	ESTAT_ADD(rx_ucast_packets);
	ESTAT_ADD(rx_mcast_packets);
	ESTAT_ADD(rx_bcast_packets);
	ESTAT_ADD(rx_fcs_errors);
	ESTAT_ADD(rx_align_errors);
	ESTAT_ADD(rx_xon_pause_rcvd);
	ESTAT_ADD(rx_xoff_pause_rcvd);
	ESTAT_ADD(rx_mac_ctrl_rcvd);
	ESTAT_ADD(rx_xoff_entered);
	ESTAT_ADD(rx_frame_too_long_errors);
	ESTAT_ADD(rx_jabbers);
	ESTAT_ADD(rx_undersize_packets);
	ESTAT_ADD(rx_in_length_errors);
	ESTAT_ADD(rx_out_length_errors);
	ESTAT_ADD(rx_64_or_less_octet_packets);
	ESTAT_ADD(rx_65_to_127_octet_packets);
	ESTAT_ADD(rx_128_to_255_octet_packets);
	ESTAT_ADD(rx_256_to_511_octet_packets);
	ESTAT_ADD(rx_512_to_1023_octet_packets);
	ESTAT_ADD(rx_1024_to_1522_octet_packets);
	ESTAT_ADD(rx_1523_to_2047_octet_packets);
	ESTAT_ADD(rx_2048_to_4095_octet_packets);
	ESTAT_ADD(rx_4096_to_8191_octet_packets);
	ESTAT_ADD(rx_8192_to_9022_octet_packets);

	ESTAT_ADD(tx_octets);
	ESTAT_ADD(tx_collisions);
	ESTAT_ADD(tx_xon_sent);
	ESTAT_ADD(tx_xoff_sent);
	ESTAT_ADD(tx_flow_control);
	ESTAT_ADD(tx_mac_errors);
	ESTAT_ADD(tx_single_collisions);
	ESTAT_ADD(tx_mult_collisions);
	ESTAT_ADD(tx_deferred);
	ESTAT_ADD(tx_excessive_collisions);
	ESTAT_ADD(tx_late_collisions);
	ESTAT_ADD(tx_collide_2times);
	ESTAT_ADD(tx_collide_3times);
	ESTAT_ADD(tx_collide_4times);
	ESTAT_ADD(tx_collide_5times);
	ESTAT_ADD(tx_collide_6times);
	ESTAT_ADD(tx_collide_7times);
	ESTAT_ADD(tx_collide_8times);
	ESTAT_ADD(tx_collide_9times);
	ESTAT_ADD(tx_collide_10times);
	ESTAT_ADD(tx_collide_11times);
	ESTAT_ADD(tx_collide_12times);
	ESTAT_ADD(tx_collide_13times);
	ESTAT_ADD(tx_collide_14times);
	ESTAT_ADD(tx_collide_15times);
	ESTAT_ADD(tx_ucast_packets);
	ESTAT_ADD(tx_mcast_packets);
	ESTAT_ADD(tx_bcast_packets);
	ESTAT_ADD(tx_carrier_sense_errors);
	ESTAT_ADD(tx_discards);
	ESTAT_ADD(tx_errors);

	ESTAT_ADD(dma_writeq_full);
	ESTAT_ADD(dma_write_prioq_full);
	ESTAT_ADD(rxbds_empty);
	ESTAT_ADD(rx_discards);
	ESTAT_ADD(rx_errors);
	ESTAT_ADD(rx_threshold_hit);

	ESTAT_ADD(dma_readq_full);
	ESTAT_ADD(dma_read_prioq_full);
	ESTAT_ADD(tx_comp_queue_full);

	ESTAT_ADD(ring_set_send_prod_index);
	ESTAT_ADD(ring_status_update);
	ESTAT_ADD(nic_irqs);
	ESTAT_ADD(nic_avoided_irqs);
	ESTAT_ADD(nic_tx_threshold_hit);

	return estats;
}

static struct net_device_stats *tg3_get_stats(struct net_device *dev)
{
	struct tg3 *tp = netdev_priv(dev);
	struct net_device_stats *stats = &tp->net_stats;
	struct net_device_stats *old_stats = &tp->net_stats_prev;
	struct tg3_hw_stats *hw_stats = tp->hw_stats;

	if (!hw_stats)
		return old_stats;

	stats->rx_packets = old_stats->rx_packets +
		get_stat64(&hw_stats->rx_ucast_packets) +
		get_stat64(&hw_stats->rx_mcast_packets) +
		get_stat64(&hw_stats->rx_bcast_packets);
8304

L
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8305 8306 8307 8308 8309 8310 8311 8312 8313 8314 8315
	stats->tx_packets = old_stats->tx_packets +
		get_stat64(&hw_stats->tx_ucast_packets) +
		get_stat64(&hw_stats->tx_mcast_packets) +
		get_stat64(&hw_stats->tx_bcast_packets);

	stats->rx_bytes = old_stats->rx_bytes +
		get_stat64(&hw_stats->rx_octets);
	stats->tx_bytes = old_stats->tx_bytes +
		get_stat64(&hw_stats->tx_octets);

	stats->rx_errors = old_stats->rx_errors +
8316
		get_stat64(&hw_stats->rx_errors);
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8317 8318 8319 8320 8321 8322 8323 8324 8325 8326 8327 8328 8329 8330 8331 8332 8333 8334 8335 8336 8337 8338 8339 8340 8341 8342 8343
	stats->tx_errors = old_stats->tx_errors +
		get_stat64(&hw_stats->tx_errors) +
		get_stat64(&hw_stats->tx_mac_errors) +
		get_stat64(&hw_stats->tx_carrier_sense_errors) +
		get_stat64(&hw_stats->tx_discards);

	stats->multicast = old_stats->multicast +
		get_stat64(&hw_stats->rx_mcast_packets);
	stats->collisions = old_stats->collisions +
		get_stat64(&hw_stats->tx_collisions);

	stats->rx_length_errors = old_stats->rx_length_errors +
		get_stat64(&hw_stats->rx_frame_too_long_errors) +
		get_stat64(&hw_stats->rx_undersize_packets);

	stats->rx_over_errors = old_stats->rx_over_errors +
		get_stat64(&hw_stats->rxbds_empty);
	stats->rx_frame_errors = old_stats->rx_frame_errors +
		get_stat64(&hw_stats->rx_align_errors);
	stats->tx_aborted_errors = old_stats->tx_aborted_errors +
		get_stat64(&hw_stats->tx_discards);
	stats->tx_carrier_errors = old_stats->tx_carrier_errors +
		get_stat64(&hw_stats->tx_carrier_sense_errors);

	stats->rx_crc_errors = old_stats->rx_crc_errors +
		calc_crc_errors(tp);

8344 8345 8346
	stats->rx_missed_errors = old_stats->rx_missed_errors +
		get_stat64(&hw_stats->rx_discards);

L
Linus Torvalds 已提交
8347 8348 8349 8350 8351 8352 8353 8354 8355 8356 8357 8358 8359 8360 8361 8362 8363 8364 8365 8366 8367 8368 8369 8370 8371 8372 8373 8374 8375 8376 8377 8378 8379 8380 8381 8382 8383 8384 8385 8386 8387 8388 8389 8390 8391 8392 8393 8394 8395 8396 8397 8398 8399 8400 8401 8402 8403 8404 8405 8406 8407 8408 8409 8410 8411 8412 8413 8414 8415 8416 8417 8418 8419 8420 8421 8422 8423 8424 8425 8426 8427 8428 8429 8430 8431 8432 8433 8434 8435 8436 8437 8438 8439 8440 8441 8442 8443 8444 8445 8446 8447 8448 8449 8450 8451
	return stats;
}

static inline u32 calc_crc(unsigned char *buf, int len)
{
	u32 reg;
	u32 tmp;
	int j, k;

	reg = 0xffffffff;

	for (j = 0; j < len; j++) {
		reg ^= buf[j];

		for (k = 0; k < 8; k++) {
			tmp = reg & 0x01;

			reg >>= 1;

			if (tmp) {
				reg ^= 0xedb88320;
			}
		}
	}

	return ~reg;
}

static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
{
	/* accept or reject all multicast frames */
	tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
	tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
	tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
	tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
}

static void __tg3_set_rx_mode(struct net_device *dev)
{
	struct tg3 *tp = netdev_priv(dev);
	u32 rx_mode;

	rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
				  RX_MODE_KEEP_VLAN_TAG);

	/* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
	 * flag clear.
	 */
#if TG3_VLAN_TAG_USED
	if (!tp->vlgrp &&
	    !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
		rx_mode |= RX_MODE_KEEP_VLAN_TAG;
#else
	/* By definition, VLAN is disabled always in this
	 * case.
	 */
	if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
		rx_mode |= RX_MODE_KEEP_VLAN_TAG;
#endif

	if (dev->flags & IFF_PROMISC) {
		/* Promiscuous mode. */
		rx_mode |= RX_MODE_PROMISC;
	} else if (dev->flags & IFF_ALLMULTI) {
		/* Accept all multicast. */
		tg3_set_multi (tp, 1);
	} else if (dev->mc_count < 1) {
		/* Reject all multicast. */
		tg3_set_multi (tp, 0);
	} else {
		/* Accept one or more multicast(s). */
		struct dev_mc_list *mclist;
		unsigned int i;
		u32 mc_filter[4] = { 0, };
		u32 regidx;
		u32 bit;
		u32 crc;

		for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
		     i++, mclist = mclist->next) {

			crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
			bit = ~crc & 0x7f;
			regidx = (bit & 0x60) >> 5;
			bit &= 0x1f;
			mc_filter[regidx] |= (1 << bit);
		}

		tw32(MAC_HASH_REG_0, mc_filter[0]);
		tw32(MAC_HASH_REG_1, mc_filter[1]);
		tw32(MAC_HASH_REG_2, mc_filter[2]);
		tw32(MAC_HASH_REG_3, mc_filter[3]);
	}

	if (rx_mode != tp->rx_mode) {
		tp->rx_mode = rx_mode;
		tw32_f(MAC_RX_MODE, rx_mode);
		udelay(10);
	}
}

static void tg3_set_rx_mode(struct net_device *dev)
{
	struct tg3 *tp = netdev_priv(dev);

8452 8453 8454
	if (!netif_running(dev))
		return;

8455
	tg3_full_lock(tp, 0);
L
Linus Torvalds 已提交
8456
	__tg3_set_rx_mode(dev);
8457
	tg3_full_unlock(tp);
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}

#define TG3_REGDUMP_LEN		(32 * 1024)

static int tg3_get_regs_len(struct net_device *dev)
{
	return TG3_REGDUMP_LEN;
}

static void tg3_get_regs(struct net_device *dev,
		struct ethtool_regs *regs, void *_p)
{
	u32 *p = _p;
	struct tg3 *tp = netdev_priv(dev);
	u8 *orig_p = _p;
	int i;

	regs->version = 0;

	memset(p, 0, TG3_REGDUMP_LEN);

M
Michael Chan 已提交
8479 8480 8481
	if (tp->link_config.phy_is_low_power)
		return;

8482
	tg3_full_lock(tp, 0);
L
Linus Torvalds 已提交
8483 8484 8485 8486 8487 8488 8489 8490 8491 8492 8493 8494 8495 8496 8497 8498 8499 8500 8501 8502 8503 8504 8505 8506 8507 8508 8509 8510 8511 8512 8513 8514 8515 8516 8517

#define __GET_REG32(reg)	(*(p)++ = tr32(reg))
#define GET_REG32_LOOP(base,len)		\
do {	p = (u32 *)(orig_p + (base));		\
	for (i = 0; i < len; i += 4)		\
		__GET_REG32((base) + i);	\
} while (0)
#define GET_REG32_1(reg)			\
do {	p = (u32 *)(orig_p + (reg));		\
	__GET_REG32((reg));			\
} while (0)

	GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
	GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
	GET_REG32_LOOP(MAC_MODE, 0x4f0);
	GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
	GET_REG32_1(SNDDATAC_MODE);
	GET_REG32_LOOP(SNDBDS_MODE, 0x80);
	GET_REG32_LOOP(SNDBDI_MODE, 0x48);
	GET_REG32_1(SNDBDC_MODE);
	GET_REG32_LOOP(RCVLPC_MODE, 0x20);
	GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
	GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
	GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
	GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
	GET_REG32_1(RCVDCC_MODE);
	GET_REG32_LOOP(RCVBDI_MODE, 0x20);
	GET_REG32_LOOP(RCVCC_MODE, 0x14);
	GET_REG32_LOOP(RCVLSC_MODE, 0x08);
	GET_REG32_1(MBFREE_MODE);
	GET_REG32_LOOP(HOSTCC_MODE, 0x100);
	GET_REG32_LOOP(MEMARB_MODE, 0x10);
	GET_REG32_LOOP(BUFMGR_MODE, 0x58);
	GET_REG32_LOOP(RDMAC_MODE, 0x08);
	GET_REG32_LOOP(WDMAC_MODE, 0x08);
8518 8519 8520 8521 8522 8523 8524
	GET_REG32_1(RX_CPU_MODE);
	GET_REG32_1(RX_CPU_STATE);
	GET_REG32_1(RX_CPU_PGMCTR);
	GET_REG32_1(RX_CPU_HWBKPT);
	GET_REG32_1(TX_CPU_MODE);
	GET_REG32_1(TX_CPU_STATE);
	GET_REG32_1(TX_CPU_PGMCTR);
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Linus Torvalds 已提交
8525 8526 8527 8528 8529 8530 8531 8532 8533 8534 8535 8536
	GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
	GET_REG32_LOOP(FTQ_RESET, 0x120);
	GET_REG32_LOOP(MSGINT_MODE, 0x0c);
	GET_REG32_1(DMAC_MODE);
	GET_REG32_LOOP(GRC_MODE, 0x4c);
	if (tp->tg3_flags & TG3_FLAG_NVRAM)
		GET_REG32_LOOP(NVRAM_CMD, 0x24);

#undef __GET_REG32
#undef GET_REG32_LOOP
#undef GET_REG32_1

8537
	tg3_full_unlock(tp);
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}

static int tg3_get_eeprom_len(struct net_device *dev)
{
	struct tg3 *tp = netdev_priv(dev);

	return tp->nvram_size;
}

static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
{
	struct tg3 *tp = netdev_priv(dev);
	int ret;
	u8  *pd;
A
Al Viro 已提交
8552
	u32 i, offset, len, b_offset, b_count;
8553
	__be32 val;
L
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Matt Carlson 已提交
8555 8556 8557
	if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
		return -EINVAL;

M
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8558 8559 8560
	if (tp->link_config.phy_is_low_power)
		return -EAGAIN;

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	offset = eeprom->offset;
	len = eeprom->len;
	eeprom->len = 0;

	eeprom->magic = TG3_EEPROM_MAGIC;

	if (offset & 3) {
		/* adjustments to start on required 4 byte boundary */
		b_offset = offset & 3;
		b_count = 4 - b_offset;
		if (b_count > len) {
			/* i.e. offset=1 len=2 */
			b_count = len;
		}
8575
		ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
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Linus Torvalds 已提交
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		if (ret)
			return ret;
		memcpy(data, ((char*)&val) + b_offset, b_count);
		len -= b_count;
		offset += b_count;
	        eeprom->len += b_count;
	}

	/* read bytes upto the last 4 byte boundary */
	pd = &data[eeprom->len];
	for (i = 0; i < (len - (len & 3)); i += 4) {
8587
		ret = tg3_nvram_read_be32(tp, offset + i, &val);
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		if (ret) {
			eeprom->len += i;
			return ret;
		}
		memcpy(pd + i, &val, 4);
	}
	eeprom->len += i;

	if (len & 3) {
		/* read last bytes not ending on 4 byte boundary */
		pd = &data[eeprom->len];
		b_count = len & 3;
		b_offset = offset + len - b_count;
8601
		ret = tg3_nvram_read_be32(tp, b_offset, &val);
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		if (ret)
			return ret;
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8604
		memcpy(pd, &val, b_count);
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		eeprom->len += b_count;
	}
	return 0;
}

8610
static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
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static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
{
	struct tg3 *tp = netdev_priv(dev);
	int ret;
A
Al Viro 已提交
8616
	u32 offset, len, b_offset, odd_len;
L
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8617
	u8 *buf;
8618
	__be32 start, end;
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M
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	if (tp->link_config.phy_is_low_power)
		return -EAGAIN;

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8623 8624
	if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
	    eeprom->magic != TG3_EEPROM_MAGIC)
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		return -EINVAL;

	offset = eeprom->offset;
	len = eeprom->len;

	if ((b_offset = (offset & 3))) {
		/* adjustments to start on required 4 byte boundary */
8632
		ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
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8633 8634 8635 8636
		if (ret)
			return ret;
		len += b_offset;
		offset &= ~3;
8637 8638
		if (len < 4)
			len = 4;
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	}

	odd_len = 0;
8642
	if (len & 3) {
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8643 8644 8645
		/* adjustments to end on required 4 byte boundary */
		odd_len = 1;
		len = (len + 3) & ~3;
8646
		ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
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		if (ret)
			return ret;
	}

	buf = data;
	if (b_offset || odd_len) {
		buf = kmalloc(len, GFP_KERNEL);
A
Andy Gospodarek 已提交
8654
		if (!buf)
L
Linus Torvalds 已提交
8655 8656 8657 8658 8659 8660 8661 8662 8663 8664 8665 8666 8667 8668 8669 8670 8671 8672
			return -ENOMEM;
		if (b_offset)
			memcpy(buf, &start, 4);
		if (odd_len)
			memcpy(buf+len-4, &end, 4);
		memcpy(buf + b_offset, data, eeprom->len);
	}

	ret = tg3_nvram_write_block(tp, offset, len, buf);

	if (buf != data)
		kfree(buf);

	return ret;
}

static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
M
Matt Carlson 已提交
8673 8674 8675 8676 8677
	struct tg3 *tp = netdev_priv(dev);

	if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
		if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
			return -EAGAIN;
8678
		return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
M
Matt Carlson 已提交
8679
	}
8680

L
Linus Torvalds 已提交
8681 8682 8683 8684 8685 8686
	cmd->supported = (SUPPORTED_Autoneg);

	if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
		cmd->supported |= (SUPPORTED_1000baseT_Half |
				   SUPPORTED_1000baseT_Full);

8687
	if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
L
Linus Torvalds 已提交
8688 8689 8690 8691
		cmd->supported |= (SUPPORTED_100baseT_Half |
				  SUPPORTED_100baseT_Full |
				  SUPPORTED_10baseT_Half |
				  SUPPORTED_10baseT_Full |
M
Matt Carlson 已提交
8692
				  SUPPORTED_TP);
8693 8694
		cmd->port = PORT_TP;
	} else {
L
Linus Torvalds 已提交
8695
		cmd->supported |= SUPPORTED_FIBRE;
8696 8697
		cmd->port = PORT_FIBRE;
	}
8698

L
Linus Torvalds 已提交
8699 8700 8701 8702 8703 8704
	cmd->advertising = tp->link_config.advertising;
	if (netif_running(dev)) {
		cmd->speed = tp->link_config.active_speed;
		cmd->duplex = tp->link_config.active_duplex;
	}
	cmd->phy_address = PHY_ADDR;
8705
	cmd->transceiver = XCVR_INTERNAL;
L
Linus Torvalds 已提交
8706 8707 8708 8709 8710
	cmd->autoneg = tp->link_config.autoneg;
	cmd->maxtxpkt = 0;
	cmd->maxrxpkt = 0;
	return 0;
}
8711

L
Linus Torvalds 已提交
8712 8713 8714
static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct tg3 *tp = netdev_priv(dev);
8715

M
Matt Carlson 已提交
8716 8717 8718
	if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
		if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
			return -EAGAIN;
8719
		return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
M
Matt Carlson 已提交
8720 8721
	}

8722 8723
	if (cmd->autoneg != AUTONEG_ENABLE &&
	    cmd->autoneg != AUTONEG_DISABLE)
8724
		return -EINVAL;
8725 8726 8727 8728

	if (cmd->autoneg == AUTONEG_DISABLE &&
	    cmd->duplex != DUPLEX_FULL &&
	    cmd->duplex != DUPLEX_HALF)
8729
		return -EINVAL;
L
Linus Torvalds 已提交
8730

8731 8732 8733 8734 8735 8736 8737 8738 8739 8740 8741 8742 8743 8744 8745 8746 8747 8748 8749 8750 8751 8752 8753 8754 8755 8756 8757 8758 8759 8760 8761 8762 8763 8764 8765 8766 8767 8768 8769 8770 8771 8772 8773
	if (cmd->autoneg == AUTONEG_ENABLE) {
		u32 mask = ADVERTISED_Autoneg |
			   ADVERTISED_Pause |
			   ADVERTISED_Asym_Pause;

		if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
			mask |= ADVERTISED_1000baseT_Half |
				ADVERTISED_1000baseT_Full;

		if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
			mask |= ADVERTISED_100baseT_Half |
				ADVERTISED_100baseT_Full |
				ADVERTISED_10baseT_Half |
				ADVERTISED_10baseT_Full |
				ADVERTISED_TP;
		else
			mask |= ADVERTISED_FIBRE;

		if (cmd->advertising & ~mask)
			return -EINVAL;

		mask &= (ADVERTISED_1000baseT_Half |
			 ADVERTISED_1000baseT_Full |
			 ADVERTISED_100baseT_Half |
			 ADVERTISED_100baseT_Full |
			 ADVERTISED_10baseT_Half |
			 ADVERTISED_10baseT_Full);

		cmd->advertising &= mask;
	} else {
		if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
			if (cmd->speed != SPEED_1000)
				return -EINVAL;

			if (cmd->duplex != DUPLEX_FULL)
				return -EINVAL;
		} else {
			if (cmd->speed != SPEED_100 &&
			    cmd->speed != SPEED_10)
				return -EINVAL;
		}
	}

8774
	tg3_full_lock(tp, 0);
L
Linus Torvalds 已提交
8775 8776 8777

	tp->link_config.autoneg = cmd->autoneg;
	if (cmd->autoneg == AUTONEG_ENABLE) {
8778 8779
		tp->link_config.advertising = (cmd->advertising |
					      ADVERTISED_Autoneg);
L
Linus Torvalds 已提交
8780 8781 8782 8783 8784 8785
		tp->link_config.speed = SPEED_INVALID;
		tp->link_config.duplex = DUPLEX_INVALID;
	} else {
		tp->link_config.advertising = 0;
		tp->link_config.speed = cmd->speed;
		tp->link_config.duplex = cmd->duplex;
M
Matt Carlson 已提交
8786
	}
8787

8788 8789 8790 8791
	tp->link_config.orig_speed = tp->link_config.speed;
	tp->link_config.orig_duplex = tp->link_config.duplex;
	tp->link_config.orig_autoneg = tp->link_config.autoneg;

L
Linus Torvalds 已提交
8792 8793 8794
	if (netif_running(dev))
		tg3_setup_phy(tp, 1);

8795
	tg3_full_unlock(tp);
8796

L
Linus Torvalds 已提交
8797 8798
	return 0;
}
8799

L
Linus Torvalds 已提交
8800 8801 8802
static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
	struct tg3 *tp = netdev_priv(dev);
8803

L
Linus Torvalds 已提交
8804 8805
	strcpy(info->driver, DRV_MODULE_NAME);
	strcpy(info->version, DRV_MODULE_VERSION);
M
Michael Chan 已提交
8806
	strcpy(info->fw_version, tp->fw_ver);
L
Linus Torvalds 已提交
8807 8808
	strcpy(info->bus_info, pci_name(tp->pdev));
}
8809

L
Linus Torvalds 已提交
8810 8811 8812
static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct tg3 *tp = netdev_priv(dev);
8813

8814 8815
	if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
	    device_can_wakeup(&tp->pdev->dev))
G
Gary Zambrano 已提交
8816 8817 8818
		wol->supported = WAKE_MAGIC;
	else
		wol->supported = 0;
L
Linus Torvalds 已提交
8819
	wol->wolopts = 0;
8820 8821
	if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
	    device_can_wakeup(&tp->pdev->dev))
L
Linus Torvalds 已提交
8822 8823 8824
		wol->wolopts = WAKE_MAGIC;
	memset(&wol->sopass, 0, sizeof(wol->sopass));
}
8825

L
Linus Torvalds 已提交
8826 8827 8828
static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct tg3 *tp = netdev_priv(dev);
8829
	struct device *dp = &tp->pdev->dev;
8830

L
Linus Torvalds 已提交
8831 8832 8833
	if (wol->wolopts & ~WAKE_MAGIC)
		return -EINVAL;
	if ((wol->wolopts & WAKE_MAGIC) &&
8834
	    !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
L
Linus Torvalds 已提交
8835
		return -EINVAL;
8836

8837
	spin_lock_bh(&tp->lock);
8838
	if (wol->wolopts & WAKE_MAGIC) {
L
Linus Torvalds 已提交
8839
		tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8840 8841
		device_set_wakeup_enable(dp, true);
	} else {
L
Linus Torvalds 已提交
8842
		tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8843 8844
		device_set_wakeup_enable(dp, false);
	}
8845
	spin_unlock_bh(&tp->lock);
8846

L
Linus Torvalds 已提交
8847 8848
	return 0;
}
8849

L
Linus Torvalds 已提交
8850 8851 8852 8853 8854
static u32 tg3_get_msglevel(struct net_device *dev)
{
	struct tg3 *tp = netdev_priv(dev);
	return tp->msg_enable;
}
8855

L
Linus Torvalds 已提交
8856 8857 8858 8859 8860
static void tg3_set_msglevel(struct net_device *dev, u32 value)
{
	struct tg3 *tp = netdev_priv(dev);
	tp->msg_enable = value;
}
8861

L
Linus Torvalds 已提交
8862 8863 8864 8865 8866 8867 8868 8869 8870
static int tg3_set_tso(struct net_device *dev, u32 value)
{
	struct tg3 *tp = netdev_priv(dev);

	if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
		if (value)
			return -EINVAL;
		return 0;
	}
M
Matt Carlson 已提交
8871 8872
	if ((dev->features & NETIF_F_IPV6_CSUM) &&
	    (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
M
Matt Carlson 已提交
8873
		if (value) {
M
Michael Chan 已提交
8874
			dev->features |= NETIF_F_TSO6;
M
Matt Carlson 已提交
8875 8876 8877
			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
			    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
			     GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
M
Matt Carlson 已提交
8878 8879
			    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
			    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
M
Matt Carlson 已提交
8880 8881 8882
				dev->features |= NETIF_F_TSO_ECN;
		} else
			dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
M
Michael Chan 已提交
8883
	}
L
Linus Torvalds 已提交
8884 8885
	return ethtool_op_set_tso(dev, value);
}
8886

L
Linus Torvalds 已提交
8887 8888 8889 8890
static int tg3_nway_reset(struct net_device *dev)
{
	struct tg3 *tp = netdev_priv(dev);
	int r;
8891

L
Linus Torvalds 已提交
8892 8893 8894
	if (!netif_running(dev))
		return -EAGAIN;

M
Michael Chan 已提交
8895 8896 8897
	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
		return -EINVAL;

M
Matt Carlson 已提交
8898 8899 8900
	if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
		if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
			return -EAGAIN;
8901
		r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
M
Matt Carlson 已提交
8902 8903 8904 8905 8906 8907 8908 8909 8910 8911 8912 8913 8914 8915
	} else {
		u32 bmcr;

		spin_lock_bh(&tp->lock);
		r = -EINVAL;
		tg3_readphy(tp, MII_BMCR, &bmcr);
		if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
		    ((bmcr & BMCR_ANENABLE) ||
		     (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
			tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
						   BMCR_ANENABLE);
			r = 0;
		}
		spin_unlock_bh(&tp->lock);
L
Linus Torvalds 已提交
8916
	}
8917

L
Linus Torvalds 已提交
8918 8919
	return r;
}
8920

L
Linus Torvalds 已提交
8921 8922 8923
static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
{
	struct tg3 *tp = netdev_priv(dev);
8924

L
Linus Torvalds 已提交
8925 8926
	ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
	ering->rx_mini_max_pending = 0;
M
Michael Chan 已提交
8927 8928 8929 8930 8931 8932
	if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
		ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
	else
		ering->rx_jumbo_max_pending = 0;

	ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
L
Linus Torvalds 已提交
8933 8934 8935

	ering->rx_pending = tp->rx_pending;
	ering->rx_mini_pending = 0;
M
Michael Chan 已提交
8936 8937 8938 8939 8940
	if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
		ering->rx_jumbo_pending = tp->rx_jumbo_pending;
	else
		ering->rx_jumbo_pending = 0;

L
Linus Torvalds 已提交
8941 8942
	ering->tx_pending = tp->tx_pending;
}
8943

L
Linus Torvalds 已提交
8944 8945 8946
static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
{
	struct tg3 *tp = netdev_priv(dev);
M
Michael Chan 已提交
8947
	int irq_sync = 0, err = 0;
8948

L
Linus Torvalds 已提交
8949 8950
	if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
	    (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8951 8952
	    (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
	    (ering->tx_pending <= MAX_SKB_FRAGS) ||
M
Michael Chan 已提交
8953
	    ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8954
	     (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
L
Linus Torvalds 已提交
8955
		return -EINVAL;
8956

8957
	if (netif_running(dev)) {
M
Matt Carlson 已提交
8958
		tg3_phy_stop(tp);
L
Linus Torvalds 已提交
8959
		tg3_netif_stop(tp);
8960 8961
		irq_sync = 1;
	}
L
Linus Torvalds 已提交
8962

8963
	tg3_full_lock(tp, irq_sync);
8964

L
Linus Torvalds 已提交
8965 8966 8967 8968 8969 8970 8971 8972 8973
	tp->rx_pending = ering->rx_pending;

	if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
	    tp->rx_pending > 63)
		tp->rx_pending = 63;
	tp->rx_jumbo_pending = ering->rx_jumbo_pending;
	tp->tx_pending = ering->tx_pending;

	if (netif_running(dev)) {
M
Michael Chan 已提交
8974
		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
M
Michael Chan 已提交
8975 8976 8977
		err = tg3_restart_hw(tp, 1);
		if (!err)
			tg3_netif_start(tp);
L
Linus Torvalds 已提交
8978 8979
	}

8980
	tg3_full_unlock(tp);
8981

M
Matt Carlson 已提交
8982 8983 8984
	if (irq_sync && !err)
		tg3_phy_start(tp);

M
Michael Chan 已提交
8985
	return err;
L
Linus Torvalds 已提交
8986
}
8987

L
Linus Torvalds 已提交
8988 8989 8990
static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
{
	struct tg3 *tp = netdev_priv(dev);
8991

L
Linus Torvalds 已提交
8992
	epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8993

8994
	if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8995 8996 8997 8998
		epause->rx_pause = 1;
	else
		epause->rx_pause = 0;

8999
	if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9000 9001 9002
		epause->tx_pause = 1;
	else
		epause->tx_pause = 0;
L
Linus Torvalds 已提交
9003
}
9004

L
Linus Torvalds 已提交
9005 9006 9007
static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
{
	struct tg3 *tp = netdev_priv(dev);
M
Matt Carlson 已提交
9008
	int err = 0;
9009

M
Matt Carlson 已提交
9010 9011 9012
	if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
		if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
			return -EAGAIN;
L
Linus Torvalds 已提交
9013

M
Matt Carlson 已提交
9014 9015 9016
		if (epause->autoneg) {
			u32 newadv;
			struct phy_device *phydev;
9017

9018
			phydev = tp->mdio_bus->phy_map[PHY_ADDR];
L
Linus Torvalds 已提交
9019

M
Matt Carlson 已提交
9020 9021 9022 9023 9024 9025 9026 9027 9028 9029 9030 9031 9032 9033 9034 9035 9036 9037 9038 9039 9040 9041 9042 9043 9044 9045 9046 9047 9048 9049
			if (epause->rx_pause) {
				if (epause->tx_pause)
					newadv = ADVERTISED_Pause;
				else
					newadv = ADVERTISED_Pause |
						 ADVERTISED_Asym_Pause;
			} else if (epause->tx_pause) {
				newadv = ADVERTISED_Asym_Pause;
			} else
				newadv = 0;

			if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
				u32 oldadv = phydev->advertising &
					     (ADVERTISED_Pause |
					      ADVERTISED_Asym_Pause);
				if (oldadv != newadv) {
					phydev->advertising &=
						~(ADVERTISED_Pause |
						  ADVERTISED_Asym_Pause);
					phydev->advertising |= newadv;
					err = phy_start_aneg(phydev);
				}
			} else {
				tp->link_config.advertising &=
						~(ADVERTISED_Pause |
						  ADVERTISED_Asym_Pause);
				tp->link_config.advertising |= newadv;
			}
		} else {
			if (epause->rx_pause)
9050
				tp->link_config.flowctrl |= FLOW_CTRL_RX;
M
Matt Carlson 已提交
9051
			else
9052
				tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9053

M
Matt Carlson 已提交
9054
			if (epause->tx_pause)
9055
				tp->link_config.flowctrl |= FLOW_CTRL_TX;
M
Matt Carlson 已提交
9056
			else
9057
				tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
M
Matt Carlson 已提交
9058 9059 9060 9061 9062 9063 9064 9065 9066 9067 9068 9069 9070 9071 9072 9073 9074 9075 9076

			if (netif_running(dev))
				tg3_setup_flow_control(tp, 0, 0);
		}
	} else {
		int irq_sync = 0;

		if (netif_running(dev)) {
			tg3_netif_stop(tp);
			irq_sync = 1;
		}

		tg3_full_lock(tp, irq_sync);

		if (epause->autoneg)
			tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
		else
			tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
		if (epause->rx_pause)
9077
			tp->link_config.flowctrl |= FLOW_CTRL_RX;
M
Matt Carlson 已提交
9078
		else
9079
			tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
M
Matt Carlson 已提交
9080
		if (epause->tx_pause)
9081
			tp->link_config.flowctrl |= FLOW_CTRL_TX;
M
Matt Carlson 已提交
9082
		else
9083
			tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
M
Matt Carlson 已提交
9084 9085 9086 9087 9088 9089 9090 9091 9092 9093

		if (netif_running(dev)) {
			tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
			err = tg3_restart_hw(tp, 1);
			if (!err)
				tg3_netif_start(tp);
		}

		tg3_full_unlock(tp);
	}
9094

M
Michael Chan 已提交
9095
	return err;
L
Linus Torvalds 已提交
9096
}
9097

L
Linus Torvalds 已提交
9098 9099 9100 9101 9102
static u32 tg3_get_rx_csum(struct net_device *dev)
{
	struct tg3 *tp = netdev_priv(dev);
	return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
}
9103

L
Linus Torvalds 已提交
9104 9105 9106
static int tg3_set_rx_csum(struct net_device *dev, u32 data)
{
	struct tg3 *tp = netdev_priv(dev);
9107

L
Linus Torvalds 已提交
9108 9109 9110 9111 9112
	if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
		if (data != 0)
			return -EINVAL;
  		return 0;
  	}
9113

9114
	spin_lock_bh(&tp->lock);
L
Linus Torvalds 已提交
9115 9116 9117 9118
	if (data)
		tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
	else
		tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9119
	spin_unlock_bh(&tp->lock);
9120

L
Linus Torvalds 已提交
9121 9122
	return 0;
}
9123

L
Linus Torvalds 已提交
9124 9125 9126
static int tg3_set_tx_csum(struct net_device *dev, u32 data)
{
	struct tg3 *tp = netdev_priv(dev);
9127

L
Linus Torvalds 已提交
9128 9129 9130 9131 9132
	if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
		if (data != 0)
			return -EINVAL;
  		return 0;
  	}
9133

M
Matt Carlson 已提交
9134
	if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9135
		ethtool_op_set_tx_ipv6_csum(dev, data);
L
Linus Torvalds 已提交
9136
	else
M
Michael Chan 已提交
9137
		ethtool_op_set_tx_csum(dev, data);
L
Linus Torvalds 已提交
9138 9139 9140 9141

	return 0;
}

9142
static int tg3_get_sset_count (struct net_device *dev, int sset)
L
Linus Torvalds 已提交
9143
{
9144 9145 9146 9147 9148 9149 9150 9151
	switch (sset) {
	case ETH_SS_TEST:
		return TG3_NUM_TEST;
	case ETH_SS_STATS:
		return TG3_NUM_STATS;
	default:
		return -EOPNOTSUPP;
	}
9152 9153
}

L
Linus Torvalds 已提交
9154 9155 9156 9157 9158 9159
static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
{
	switch (stringset) {
	case ETH_SS_STATS:
		memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
		break;
9160 9161 9162
	case ETH_SS_TEST:
		memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
		break;
L
Linus Torvalds 已提交
9163 9164 9165 9166 9167 9168
	default:
		WARN_ON(1);	/* we need a WARN() */
		break;
	}
}

M
Michael Chan 已提交
9169 9170 9171 9172 9173 9174 9175 9176 9177
static int tg3_phys_id(struct net_device *dev, u32 data)
{
	struct tg3 *tp = netdev_priv(dev);
	int i;

	if (!netif_running(tp->dev))
		return -EAGAIN;

	if (data == 0)
S
Stephen Hemminger 已提交
9178
		data = UINT_MAX / 2;
M
Michael Chan 已提交
9179 9180 9181 9182 9183 9184 9185 9186 9187 9188

	for (i = 0; i < (data * 2); i++) {
		if ((i % 2) == 0)
			tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
					   LED_CTRL_1000MBPS_ON |
					   LED_CTRL_100MBPS_ON |
					   LED_CTRL_10MBPS_ON |
					   LED_CTRL_TRAFFIC_OVERRIDE |
					   LED_CTRL_TRAFFIC_BLINK |
					   LED_CTRL_TRAFFIC_LED);
9189

M
Michael Chan 已提交
9190 9191 9192 9193 9194 9195 9196 9197 9198 9199 9200
		else
			tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
					   LED_CTRL_TRAFFIC_OVERRIDE);

		if (msleep_interruptible(500))
			break;
	}
	tw32(MAC_LED_CTRL, tp->led_ctrl);
	return 0;
}

L
Linus Torvalds 已提交
9201 9202 9203 9204 9205 9206 9207
static void tg3_get_ethtool_stats (struct net_device *dev,
				   struct ethtool_stats *estats, u64 *tmp_stats)
{
	struct tg3 *tp = netdev_priv(dev);
	memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
}

M
Michael Chan 已提交
9208
#define NVRAM_TEST_SIZE 0x100
M
Matt Carlson 已提交
9209 9210 9211
#define NVRAM_SELFBOOT_FORMAT1_0_SIZE	0x14
#define NVRAM_SELFBOOT_FORMAT1_2_SIZE	0x18
#define NVRAM_SELFBOOT_FORMAT1_3_SIZE	0x1c
9212 9213
#define NVRAM_SELFBOOT_HW_SIZE 0x20
#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
M
Michael Chan 已提交
9214 9215 9216

static int tg3_test_nvram(struct tg3 *tp)
{
A
Al Viro 已提交
9217
	u32 csum, magic;
9218
	__be32 *buf;
A
Andy Gospodarek 已提交
9219
	int i, j, k, err = 0, size;
M
Michael Chan 已提交
9220

M
Matt Carlson 已提交
9221 9222 9223
	if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
		return 0;

9224
	if (tg3_nvram_read(tp, 0, &magic) != 0)
M
Michael Chan 已提交
9225 9226 9227 9228
		return -EIO;

	if (magic == TG3_EEPROM_MAGIC)
		size = NVRAM_TEST_SIZE;
9229
	else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
M
Matt Carlson 已提交
9230 9231 9232 9233 9234 9235 9236 9237 9238 9239 9240 9241 9242 9243 9244 9245
		if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
		    TG3_EEPROM_SB_FORMAT_1) {
			switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
			case TG3_EEPROM_SB_REVISION_0:
				size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
				break;
			case TG3_EEPROM_SB_REVISION_2:
				size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
				break;
			case TG3_EEPROM_SB_REVISION_3:
				size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
				break;
			default:
				return 0;
			}
		} else
M
Michael Chan 已提交
9246
			return 0;
9247 9248 9249
	} else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
		size = NVRAM_SELFBOOT_HW_SIZE;
	else
M
Michael Chan 已提交
9250 9251 9252
		return -EIO;

	buf = kmalloc(size, GFP_KERNEL);
M
Michael Chan 已提交
9253 9254 9255
	if (buf == NULL)
		return -ENOMEM;

M
Michael Chan 已提交
9256 9257
	err = -EIO;
	for (i = 0, j = 0; i < size; i += 4, j++) {
9258 9259
		err = tg3_nvram_read_be32(tp, i, &buf[j]);
		if (err)
M
Michael Chan 已提交
9260 9261
			break;
	}
M
Michael Chan 已提交
9262
	if (i < size)
M
Michael Chan 已提交
9263 9264
		goto out;

M
Michael Chan 已提交
9265
	/* Selfboot format */
9266
	magic = be32_to_cpu(buf[0]);
A
Al Viro 已提交
9267
	if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9268
	    TG3_EEPROM_MAGIC_FW) {
M
Michael Chan 已提交
9269 9270
		u8 *buf8 = (u8 *) buf, csum8 = 0;

A
Al Viro 已提交
9271
		if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
M
Matt Carlson 已提交
9272 9273 9274 9275 9276 9277 9278 9279 9280 9281
		    TG3_EEPROM_SB_REVISION_2) {
			/* For rev 2, the csum doesn't include the MBA. */
			for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
				csum8 += buf8[i];
			for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
				csum8 += buf8[i];
		} else {
			for (i = 0; i < size; i++)
				csum8 += buf8[i];
		}
M
Michael Chan 已提交
9282

A
Adrian Bunk 已提交
9283 9284 9285 9286 9287 9288 9289
		if (csum8 == 0) {
			err = 0;
			goto out;
		}

		err = -EIO;
		goto out;
M
Michael Chan 已提交
9290
	}
M
Michael Chan 已提交
9291

A
Al Viro 已提交
9292
	if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9293 9294
	    TG3_EEPROM_MAGIC_HW) {
		u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9295
		u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9296 9297 9298 9299 9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 9310 9311 9312 9313 9314 9315 9316 9317 9318 9319 9320 9321 9322 9323 9324 9325 9326 9327 9328 9329 9330 9331 9332 9333 9334 9335
		u8 *buf8 = (u8 *) buf;

		/* Separate the parity bits and the data bytes.  */
		for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
			if ((i == 0) || (i == 8)) {
				int l;
				u8 msk;

				for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
					parity[k++] = buf8[i] & msk;
				i++;
			}
			else if (i == 16) {
				int l;
				u8 msk;

				for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
					parity[k++] = buf8[i] & msk;
				i++;

				for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
					parity[k++] = buf8[i] & msk;
				i++;
			}
			data[j++] = buf8[i];
		}

		err = -EIO;
		for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
			u8 hw8 = hweight8(data[i]);

			if ((hw8 & 0x1) && parity[i])
				goto out;
			else if (!(hw8 & 0x1) && !parity[i])
				goto out;
		}
		err = 0;
		goto out;
	}

M
Michael Chan 已提交
9336 9337
	/* Bootstrap checksum at offset 0x10 */
	csum = calc_crc((unsigned char *) buf, 0x10);
9338
	if (csum != be32_to_cpu(buf[0x10/4]))
M
Michael Chan 已提交
9339 9340 9341 9342
		goto out;

	/* Manufacturing block starts at offset 0x74, checksum at 0xfc */
	csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9343 9344
	if (csum != be32_to_cpu(buf[0xfc/4]))
		goto out;
M
Michael Chan 已提交
9345 9346 9347 9348 9349 9350 9351 9352

	err = 0;

out:
	kfree(buf);
	return err;
}

M
Michael Chan 已提交
9353 9354 9355 9356 9357 9358 9359 9360 9361 9362
#define TG3_SERDES_TIMEOUT_SEC	2
#define TG3_COPPER_TIMEOUT_SEC	6

static int tg3_test_link(struct tg3 *tp)
{
	int i, max;

	if (!netif_running(tp->dev))
		return -ENODEV;

M
Michael Chan 已提交
9363
	if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
M
Michael Chan 已提交
9364 9365 9366 9367 9368 9369 9370 9371 9372 9373 9374 9375 9376 9377 9378
		max = TG3_SERDES_TIMEOUT_SEC;
	else
		max = TG3_COPPER_TIMEOUT_SEC;

	for (i = 0; i < max; i++) {
		if (netif_carrier_ok(tp->dev))
			return 0;

		if (msleep_interruptible(1000))
			break;
	}

	return -EIO;
}

M
Michael Chan 已提交
9379
/* Only test the commonly used registers */
9380
static int tg3_test_registers(struct tg3 *tp)
M
Michael Chan 已提交
9381
{
9382
	int i, is_5705, is_5750;
M
Michael Chan 已提交
9383 9384 9385 9386 9387 9388 9389
	u32 offset, read_mask, write_mask, val, save_val, read_val;
	static struct {
		u16 offset;
		u16 flags;
#define TG3_FL_5705	0x1
#define TG3_FL_NOT_5705	0x2
#define TG3_FL_NOT_5788	0x4
9390
#define TG3_FL_NOT_5750	0x8
M
Michael Chan 已提交
9391 9392 9393 9394 9395 9396 9397 9398 9399 9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 9410 9411 9412 9413 9414 9415 9416 9417 9418 9419 9420 9421 9422 9423 9424 9425 9426 9427 9428 9429 9430 9431 9432 9433 9434 9435 9436 9437 9438 9439 9440 9441 9442
		u32 read_mask;
		u32 write_mask;
	} reg_tbl[] = {
		/* MAC Control Registers */
		{ MAC_MODE, TG3_FL_NOT_5705,
			0x00000000, 0x00ef6f8c },
		{ MAC_MODE, TG3_FL_5705,
			0x00000000, 0x01ef6b8c },
		{ MAC_STATUS, TG3_FL_NOT_5705,
			0x03800107, 0x00000000 },
		{ MAC_STATUS, TG3_FL_5705,
			0x03800100, 0x00000000 },
		{ MAC_ADDR_0_HIGH, 0x0000,
			0x00000000, 0x0000ffff },
		{ MAC_ADDR_0_LOW, 0x0000,
		       	0x00000000, 0xffffffff },
		{ MAC_RX_MTU_SIZE, 0x0000,
			0x00000000, 0x0000ffff },
		{ MAC_TX_MODE, 0x0000,
			0x00000000, 0x00000070 },
		{ MAC_TX_LENGTHS, 0x0000,
			0x00000000, 0x00003fff },
		{ MAC_RX_MODE, TG3_FL_NOT_5705,
			0x00000000, 0x000007fc },
		{ MAC_RX_MODE, TG3_FL_5705,
			0x00000000, 0x000007dc },
		{ MAC_HASH_REG_0, 0x0000,
			0x00000000, 0xffffffff },
		{ MAC_HASH_REG_1, 0x0000,
			0x00000000, 0xffffffff },
		{ MAC_HASH_REG_2, 0x0000,
			0x00000000, 0xffffffff },
		{ MAC_HASH_REG_3, 0x0000,
			0x00000000, 0xffffffff },

		/* Receive Data and Receive BD Initiator Control Registers. */
		{ RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
			0x00000000, 0x00000003 },
		{ RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ RCVDBDI_STD_BD+0, 0x0000,
			0x00000000, 0xffffffff },
		{ RCVDBDI_STD_BD+4, 0x0000,
			0x00000000, 0xffffffff },
		{ RCVDBDI_STD_BD+8, 0x0000,
			0x00000000, 0xffff0002 },
		{ RCVDBDI_STD_BD+0xc, 0x0000,
			0x00000000, 0xffffffff },
9443

M
Michael Chan 已提交
9444 9445 9446 9447 9448 9449 9450
		/* Receive BD Initiator Control Registers. */
		{ RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ RCVBDI_STD_THRESH, TG3_FL_5705,
			0x00000000, 0x000003ff },
		{ RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
9451

M
Michael Chan 已提交
9452 9453 9454 9455 9456 9457 9458 9459 9460 9461 9462 9463 9464 9465 9466 9467 9468 9469 9470 9471 9472 9473 9474 9475 9476 9477 9478 9479 9480 9481 9482 9483 9484 9485 9486 9487 9488 9489 9490 9491 9492 9493 9494 9495 9496 9497 9498 9499 9500
		/* Host Coalescing Control Registers. */
		{ HOSTCC_MODE, TG3_FL_NOT_5705,
			0x00000000, 0x00000004 },
		{ HOSTCC_MODE, TG3_FL_5705,
			0x00000000, 0x000000f6 },
		{ HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ HOSTCC_RXCOL_TICKS, TG3_FL_5705,
			0x00000000, 0x000003ff },
		{ HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ HOSTCC_TXCOL_TICKS, TG3_FL_5705,
			0x00000000, 0x000003ff },
		{ HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
			0x00000000, 0x000000ff },
		{ HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
			0x00000000, 0x000000ff },
		{ HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
			0x00000000, 0x000000ff },
		{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
			0x00000000, 0x000000ff },
		{ HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
			0x00000000, 0xffffffff },
		{ HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
			0x00000000, 0xffffffff },
		{ HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
			0x00000000, 0xffffffff },
		{ HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
			0xffffffff, 0x00000000 },
		{ HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
			0xffffffff, 0x00000000 },

		/* Buffer Manager Control Registers. */
9501
		{ BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
M
Michael Chan 已提交
9502
			0x00000000, 0x007fff80 },
9503
		{ BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
M
Michael Chan 已提交
9504 9505 9506 9507 9508 9509 9510 9511 9512 9513 9514
			0x00000000, 0x007fffff },
		{ BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
			0x00000000, 0x0000003f },
		{ BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
			0x00000000, 0x000001ff },
		{ BUFMGR_MB_HIGH_WATER, 0x0000,
			0x00000000, 0x000001ff },
		{ BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
			0xffffffff, 0x00000000 },
		{ BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
			0xffffffff, 0x00000000 },
9515

M
Michael Chan 已提交
9516 9517 9518 9519 9520 9521 9522 9523 9524 9525 9526 9527 9528
		/* Mailbox Registers */
		{ GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
			0x00000000, 0x000001ff },
		{ GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
			0x00000000, 0x000001ff },
		{ GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
			0x00000000, 0x000007ff },
		{ GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
			0x00000000, 0x000001ff },

		{ 0xffff, 0x0000, 0x00000000, 0x00000000 },
	};

9529 9530
	is_5705 = is_5750 = 0;
	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
M
Michael Chan 已提交
9531
		is_5705 = 1;
9532 9533 9534
		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
			is_5750 = 1;
	}
M
Michael Chan 已提交
9535 9536 9537 9538 9539 9540 9541 9542 9543 9544 9545 9546

	for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
		if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
			continue;

		if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
			continue;

		if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
		    (reg_tbl[i].flags & TG3_FL_NOT_5788))
			continue;

9547 9548 9549
		if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
			continue;

M
Michael Chan 已提交
9550 9551 9552 9553 9554 9555 9556 9557 9558 9559 9560 9561 9562 9563 9564 9565 9566 9567 9568 9569 9570 9571 9572 9573 9574 9575 9576 9577 9578 9579 9580 9581 9582 9583 9584 9585 9586 9587 9588 9589 9590 9591 9592
		offset = (u32) reg_tbl[i].offset;
		read_mask = reg_tbl[i].read_mask;
		write_mask = reg_tbl[i].write_mask;

		/* Save the original register content */
		save_val = tr32(offset);

		/* Determine the read-only value. */
		read_val = save_val & read_mask;

		/* Write zero to the register, then make sure the read-only bits
		 * are not changed and the read/write bits are all zeros.
		 */
		tw32(offset, 0);

		val = tr32(offset);

		/* Test the read-only and read/write bits. */
		if (((val & read_mask) != read_val) || (val & write_mask))
			goto out;

		/* Write ones to all the bits defined by RdMask and WrMask, then
		 * make sure the read-only bits are not changed and the
		 * read/write bits are all ones.
		 */
		tw32(offset, read_mask | write_mask);

		val = tr32(offset);

		/* Test the read-only bits. */
		if ((val & read_mask) != read_val)
			goto out;

		/* Test the read/write bits. */
		if ((val & write_mask) != write_mask)
			goto out;

		tw32(offset, save_val);
	}

	return 0;

out:
M
Michael Chan 已提交
9593 9594 9595
	if (netif_msg_hw(tp))
		printk(KERN_ERR PFX "Register test failed at offset %x\n",
		       offset);
M
Michael Chan 已提交
9596 9597 9598 9599
	tw32(offset, save_val);
	return -EIO;
}

M
Michael Chan 已提交
9600 9601
static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
{
9602
	static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
M
Michael Chan 已提交
9603 9604 9605
	int i;
	u32 j;

9606
	for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
M
Michael Chan 已提交
9607 9608 9609 9610 9611 9612 9613 9614 9615 9616 9617 9618 9619 9620 9621 9622 9623 9624
		for (j = 0; j < len; j += 4) {
			u32 val;

			tg3_write_mem(tp, offset + j, test_pattern[i]);
			tg3_read_mem(tp, offset + j, &val);
			if (val != test_pattern[i])
				return -EIO;
		}
	}
	return 0;
}

static int tg3_test_memory(struct tg3 *tp)
{
	static struct mem_entry {
		u32 offset;
		u32 len;
	} mem_tbl_570x[] = {
M
Michael Chan 已提交
9625
		{ 0x00000000, 0x00b50},
M
Michael Chan 已提交
9626 9627 9628 9629 9630 9631 9632 9633 9634 9635
		{ 0x00002000, 0x1c000},
		{ 0xffffffff, 0x00000}
	}, mem_tbl_5705[] = {
		{ 0x00000100, 0x0000c},
		{ 0x00000200, 0x00008},
		{ 0x00004000, 0x00800},
		{ 0x00006000, 0x01000},
		{ 0x00008000, 0x02000},
		{ 0x00010000, 0x0e000},
		{ 0xffffffff, 0x00000}
M
Michael Chan 已提交
9636 9637 9638 9639 9640 9641 9642
	}, mem_tbl_5755[] = {
		{ 0x00000200, 0x00008},
		{ 0x00004000, 0x00800},
		{ 0x00006000, 0x00800},
		{ 0x00008000, 0x02000},
		{ 0x00010000, 0x0c000},
		{ 0xffffffff, 0x00000}
9643 9644 9645 9646 9647 9648 9649
	}, mem_tbl_5906[] = {
		{ 0x00000200, 0x00008},
		{ 0x00004000, 0x00400},
		{ 0x00006000, 0x00400},
		{ 0x00008000, 0x01000},
		{ 0x00010000, 0x01000},
		{ 0xffffffff, 0x00000}
M
Michael Chan 已提交
9650 9651 9652 9653 9654
	};
	struct mem_entry *mem_tbl;
	int err = 0;
	int i;

M
Matt Carlson 已提交
9655 9656 9657 9658 9659 9660 9661
	if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
		mem_tbl = mem_tbl_5755;
	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
		mem_tbl = mem_tbl_5906;
	else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
		mem_tbl = mem_tbl_5705;
	else
M
Michael Chan 已提交
9662 9663 9664 9665 9666 9667 9668
		mem_tbl = mem_tbl_570x;

	for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
		if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
		    mem_tbl[i].len)) != 0)
			break;
	}
9669

M
Michael Chan 已提交
9670 9671 9672
	return err;
}

M
Michael Chan 已提交
9673 9674 9675 9676
#define TG3_MAC_LOOPBACK	0
#define TG3_PHY_LOOPBACK	1

static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
M
Michael Chan 已提交
9677
{
M
Michael Chan 已提交
9678
	u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
M
Michael Chan 已提交
9679 9680 9681 9682 9683 9684 9685
	u32 desc_idx;
	struct sk_buff *skb, *rx_skb;
	u8 *tx_data;
	dma_addr_t map;
	int num_pkts, tx_len, rx_len, i, err;
	struct tg3_rx_buffer_desc *desc;

M
Michael Chan 已提交
9686
	if (loopback_mode == TG3_MAC_LOOPBACK) {
M
Michael Chan 已提交
9687 9688 9689 9690 9691 9692 9693
		/* HW errata - mac loopback fails in some cases on 5780.
		 * Normal traffic and PHY loopback are not affected by
		 * errata.
		 */
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
			return 0;

M
Michael Chan 已提交
9694
		mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
M
Matt Carlson 已提交
9695 9696 9697
			   MAC_MODE_PORT_INT_LPBACK;
		if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
			mac_mode |= MAC_MODE_LINK_POLARITY;
M
Michael Chan 已提交
9698 9699 9700 9701
		if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
			mac_mode |= MAC_MODE_PORT_MODE_MII;
		else
			mac_mode |= MAC_MODE_PORT_MODE_GMII;
M
Michael Chan 已提交
9702 9703
		tw32(MAC_MODE, mac_mode);
	} else if (loopback_mode == TG3_PHY_LOOPBACK) {
M
Michael Chan 已提交
9704 9705
		u32 val;

9706 9707 9708 9709 9710 9711 9712 9713 9714 9715 9716 9717
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
			u32 phytest;

			if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
				u32 phy;

				tg3_writephy(tp, MII_TG3_EPHY_TEST,
					     phytest | MII_TG3_EPHY_SHADOW_EN);
				if (!tg3_readphy(tp, 0x1b, &phy))
					tg3_writephy(tp, 0x1b, phy & ~0x20);
				tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
			}
M
Michael Chan 已提交
9718 9719 9720
			val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
		} else
			val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
M
Michael Chan 已提交
9721

M
Matt Carlson 已提交
9722 9723
		tg3_phy_toggle_automdix(tp, 0);

M
Michael Chan 已提交
9724
		tg3_writephy(tp, MII_BMCR, val);
M
Michael Chan 已提交
9725
		udelay(40);
M
Michael Chan 已提交
9726

M
Matt Carlson 已提交
9727
		mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
M
Michael Chan 已提交
9728
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9729
			tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
M
Michael Chan 已提交
9730 9731 9732
			mac_mode |= MAC_MODE_PORT_MODE_MII;
		} else
			mac_mode |= MAC_MODE_PORT_MODE_GMII;
9733

M
Michael Chan 已提交
9734 9735 9736 9737 9738 9739
		/* reset to prevent losing 1st rx packet intermittently */
		if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
			tw32_f(MAC_RX_MODE, RX_MODE_RESET);
			udelay(10);
			tw32_f(MAC_RX_MODE, tp->rx_mode);
		}
M
Matt Carlson 已提交
9740 9741 9742 9743 9744
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
			if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
				mac_mode &= ~MAC_MODE_LINK_POLARITY;
			else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
				mac_mode |= MAC_MODE_LINK_POLARITY;
M
Michael Chan 已提交
9745 9746 9747
			tg3_writephy(tp, MII_TG3_EXT_CTRL,
				     MII_TG3_EXT_CTRL_LNK3_LED_MODE);
		}
M
Michael Chan 已提交
9748 9749 9750 9751
		tw32(MAC_MODE, mac_mode);
	}
	else
		return -EINVAL;
M
Michael Chan 已提交
9752 9753 9754 9755

	err = -EIO;

	tx_len = 1514;
9756
	skb = netdev_alloc_skb(tp->dev, tx_len);
9757 9758 9759
	if (!skb)
		return -ENOMEM;

M
Michael Chan 已提交
9760 9761 9762 9763 9764 9765 9766 9767 9768 9769 9770 9771 9772 9773 9774 9775 9776 9777 9778 9779
	tx_data = skb_put(skb, tx_len);
	memcpy(tx_data, tp->dev->dev_addr, 6);
	memset(tx_data + 6, 0x0, 8);

	tw32(MAC_RX_MTU_SIZE, tx_len + 4);

	for (i = 14; i < tx_len; i++)
		tx_data[i] = (u8) (i & 0xff);

	map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);

	tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
	     HOSTCC_MODE_NOW);

	udelay(10);

	rx_start_idx = tp->hw_status->idx[0].rx_producer;

	num_pkts = 0;

M
Michael Chan 已提交
9780
	tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
M
Michael Chan 已提交
9781

M
Michael Chan 已提交
9782
	tp->tx_prod++;
M
Michael Chan 已提交
9783 9784
	num_pkts++;

M
Michael Chan 已提交
9785 9786
	tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
		     tp->tx_prod);
M
Michael Chan 已提交
9787
	tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
M
Michael Chan 已提交
9788 9789 9790

	udelay(10);

M
Michael Chan 已提交
9791 9792
	/* 250 usec to allow enough time on some 10/100 Mbps devices.  */
	for (i = 0; i < 25; i++) {
M
Michael Chan 已提交
9793 9794 9795 9796 9797 9798 9799
		tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
		       HOSTCC_MODE_NOW);

		udelay(10);

		tx_idx = tp->hw_status->idx[0].tx_consumer;
		rx_idx = tp->hw_status->idx[0].rx_producer;
M
Michael Chan 已提交
9800
		if ((tx_idx == tp->tx_prod) &&
M
Michael Chan 已提交
9801 9802 9803 9804 9805 9806 9807
		    (rx_idx == (rx_start_idx + num_pkts)))
			break;
	}

	pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
	dev_kfree_skb(skb);

M
Michael Chan 已提交
9808
	if (tx_idx != tp->tx_prod)
M
Michael Chan 已提交
9809 9810 9811 9812 9813 9814 9815 9816 9817 9818 9819 9820 9821 9822 9823 9824 9825 9826 9827 9828 9829 9830 9831 9832 9833 9834 9835 9836 9837
		goto out;

	if (rx_idx != rx_start_idx + num_pkts)
		goto out;

	desc = &tp->rx_rcb[rx_start_idx];
	desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
	opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
	if (opaque_key != RXD_OPAQUE_RING_STD)
		goto out;

	if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
	    (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
		goto out;

	rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
	if (rx_len != tx_len)
		goto out;

	rx_skb = tp->rx_std_buffers[desc_idx].skb;

	map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
	pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);

	for (i = 14; i < tx_len; i++) {
		if (*(rx_skb->data + i) != (u8) (i & 0xff))
			goto out;
	}
	err = 0;
9838

M
Michael Chan 已提交
9839 9840 9841 9842 9843
	/* tg3_free_rings will unmap and free the rx_skb */
out:
	return err;
}

M
Michael Chan 已提交
9844 9845 9846 9847 9848 9849 9850 9851
#define TG3_MAC_LOOPBACK_FAILED		1
#define TG3_PHY_LOOPBACK_FAILED		2
#define TG3_LOOPBACK_FAILED		(TG3_MAC_LOOPBACK_FAILED |	\
					 TG3_PHY_LOOPBACK_FAILED)

static int tg3_test_loopback(struct tg3 *tp)
{
	int err = 0;
M
Matt Carlson 已提交
9852
	u32 cpmuctrl = 0;
M
Michael Chan 已提交
9853 9854 9855 9856

	if (!netif_running(tp->dev))
		return TG3_LOOPBACK_FAILED;

M
Michael Chan 已提交
9857 9858 9859
	err = tg3_reset_hw(tp, 1);
	if (err)
		return TG3_LOOPBACK_FAILED;
M
Michael Chan 已提交
9860

9861 9862 9863 9864
	/* Turn off gphy autopowerdown. */
	if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
		tg3_phy_toggle_apd(tp, false);

M
Matt Carlson 已提交
9865
	if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
M
Matt Carlson 已提交
9866 9867 9868 9869 9870 9871 9872 9873 9874 9875 9876 9877 9878 9879 9880 9881
		int i;
		u32 status;

		tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);

		/* Wait for up to 40 microseconds to acquire lock. */
		for (i = 0; i < 4; i++) {
			status = tr32(TG3_CPMU_MUTEX_GNT);
			if (status == CPMU_MUTEX_GNT_DRIVER)
				break;
			udelay(10);
		}

		if (status != CPMU_MUTEX_GNT_DRIVER)
			return TG3_LOOPBACK_FAILED;

9882
		/* Turn off link-based power management. */
9883
		cpmuctrl = tr32(TG3_CPMU_CTRL);
9884 9885 9886
		tw32(TG3_CPMU_CTRL,
		     cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
				  CPMU_CTRL_LINK_AWARE_MODE));
M
Matt Carlson 已提交
9887 9888
	}

M
Michael Chan 已提交
9889 9890
	if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
		err |= TG3_MAC_LOOPBACK_FAILED;
M
Matt Carlson 已提交
9891

M
Matt Carlson 已提交
9892
	if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
M
Matt Carlson 已提交
9893 9894 9895 9896 9897 9898
		tw32(TG3_CPMU_CTRL, cpmuctrl);

		/* Release the mutex */
		tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
	}

M
Matt Carlson 已提交
9899 9900
	if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
	    !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
M
Michael Chan 已提交
9901 9902 9903 9904
		if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
			err |= TG3_PHY_LOOPBACK_FAILED;
	}

9905 9906 9907 9908
	/* Re-enable gphy autopowerdown. */
	if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
		tg3_phy_toggle_apd(tp, true);

M
Michael Chan 已提交
9909 9910 9911
	return err;
}

9912 9913 9914
static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
			  u64 *data)
{
M
Michael Chan 已提交
9915 9916
	struct tg3 *tp = netdev_priv(dev);

M
Michael Chan 已提交
9917 9918 9919
	if (tp->link_config.phy_is_low_power)
		tg3_set_power_state(tp, PCI_D0);

M
Michael Chan 已提交
9920 9921 9922 9923 9924 9925
	memset(data, 0, sizeof(u64) * TG3_NUM_TEST);

	if (tg3_test_nvram(tp) != 0) {
		etest->flags |= ETH_TEST_FL_FAILED;
		data[0] = 1;
	}
M
Michael Chan 已提交
9926 9927 9928 9929
	if (tg3_test_link(tp) != 0) {
		etest->flags |= ETH_TEST_FL_FAILED;
		data[1] = 1;
	}
M
Michael Chan 已提交
9930
	if (etest->flags & ETH_TEST_FL_OFFLINE) {
M
Matt Carlson 已提交
9931
		int err, err2 = 0, irq_sync = 0;
9932 9933

		if (netif_running(dev)) {
M
Matt Carlson 已提交
9934
			tg3_phy_stop(tp);
M
Michael Chan 已提交
9935
			tg3_netif_stop(tp);
9936 9937
			irq_sync = 1;
		}
M
Michael Chan 已提交
9938

9939
		tg3_full_lock(tp, irq_sync);
M
Michael Chan 已提交
9940 9941

		tg3_halt(tp, RESET_KIND_SUSPEND, 1);
M
Michael Chan 已提交
9942
		err = tg3_nvram_lock(tp);
M
Michael Chan 已提交
9943 9944 9945
		tg3_halt_cpu(tp, RX_CPU_BASE);
		if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
			tg3_halt_cpu(tp, TX_CPU_BASE);
M
Michael Chan 已提交
9946 9947
		if (!err)
			tg3_nvram_unlock(tp);
M
Michael Chan 已提交
9948

9949 9950 9951
		if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
			tg3_phy_reset(tp);

M
Michael Chan 已提交
9952 9953 9954 9955
		if (tg3_test_registers(tp) != 0) {
			etest->flags |= ETH_TEST_FL_FAILED;
			data[2] = 1;
		}
M
Michael Chan 已提交
9956 9957 9958 9959
		if (tg3_test_memory(tp) != 0) {
			etest->flags |= ETH_TEST_FL_FAILED;
			data[3] = 1;
		}
M
Michael Chan 已提交
9960
		if ((data[4] = tg3_test_loopback(tp)) != 0)
M
Michael Chan 已提交
9961
			etest->flags |= ETH_TEST_FL_FAILED;
M
Michael Chan 已提交
9962

9963 9964
		tg3_full_unlock(tp);

M
Michael Chan 已提交
9965 9966 9967 9968
		if (tg3_test_interrupt(tp) != 0) {
			etest->flags |= ETH_TEST_FL_FAILED;
			data[5] = 1;
		}
9969 9970

		tg3_full_lock(tp, 0);
M
Michael Chan 已提交
9971

M
Michael Chan 已提交
9972 9973 9974
		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
		if (netif_running(dev)) {
			tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
M
Matt Carlson 已提交
9975 9976
			err2 = tg3_restart_hw(tp, 1);
			if (!err2)
M
Michael Chan 已提交
9977
				tg3_netif_start(tp);
M
Michael Chan 已提交
9978
		}
9979 9980

		tg3_full_unlock(tp);
M
Matt Carlson 已提交
9981 9982 9983

		if (irq_sync && !err2)
			tg3_phy_start(tp);
M
Michael Chan 已提交
9984
	}
M
Michael Chan 已提交
9985 9986 9987
	if (tp->link_config.phy_is_low_power)
		tg3_set_power_state(tp, PCI_D3hot);

9988 9989
}

L
Linus Torvalds 已提交
9990 9991 9992 9993 9994 9995
static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
	struct mii_ioctl_data *data = if_mii(ifr);
	struct tg3 *tp = netdev_priv(dev);
	int err;

M
Matt Carlson 已提交
9996 9997 9998
	if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
		if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
			return -EAGAIN;
9999
		return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
M
Matt Carlson 已提交
10000 10001
	}

L
Linus Torvalds 已提交
10002 10003 10004 10005 10006 10007 10008 10009 10010 10011 10012
	switch(cmd) {
	case SIOCGMIIPHY:
		data->phy_id = PHY_ADDR;

		/* fallthru */
	case SIOCGMIIREG: {
		u32 mii_regval;

		if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
			break;			/* We have no PHY */

M
Michael Chan 已提交
10013 10014 10015
		if (tp->link_config.phy_is_low_power)
			return -EAGAIN;

10016
		spin_lock_bh(&tp->lock);
L
Linus Torvalds 已提交
10017
		err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10018
		spin_unlock_bh(&tp->lock);
L
Linus Torvalds 已提交
10019 10020 10021 10022 10023 10024 10025 10026 10027 10028 10029 10030 10031

		data->val_out = mii_regval;

		return err;
	}

	case SIOCSMIIREG:
		if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
			break;			/* We have no PHY */

		if (!capable(CAP_NET_ADMIN))
			return -EPERM;

M
Michael Chan 已提交
10032 10033 10034
		if (tp->link_config.phy_is_low_power)
			return -EAGAIN;

10035
		spin_lock_bh(&tp->lock);
L
Linus Torvalds 已提交
10036
		err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10037
		spin_unlock_bh(&tp->lock);
L
Linus Torvalds 已提交
10038 10039 10040 10041 10042 10043 10044 10045 10046 10047 10048 10049 10050 10051 10052

		return err;

	default:
		/* do nothing */
		break;
	}
	return -EOPNOTSUPP;
}

#if TG3_VLAN_TAG_USED
static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
{
	struct tg3 *tp = netdev_priv(dev);

10053 10054 10055 10056 10057 10058
	if (!netif_running(dev)) {
		tp->vlgrp = grp;
		return;
	}

	tg3_netif_stop(tp);
10059

10060
	tg3_full_lock(tp, 0);
L
Linus Torvalds 已提交
10061 10062 10063 10064 10065 10066

	tp->vlgrp = grp;

	/* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
	__tg3_set_rx_mode(dev);

10067
	tg3_netif_start(tp);
10068 10069

	tg3_full_unlock(tp);
L
Linus Torvalds 已提交
10070 10071 10072
}
#endif

10073 10074 10075 10076 10077 10078 10079 10080
static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
{
	struct tg3 *tp = netdev_priv(dev);

	memcpy(ec, &tp->coal, sizeof(*ec));
	return 0;
}

M
Michael Chan 已提交
10081 10082 10083 10084 10085 10086 10087 10088 10089 10090 10091 10092 10093 10094 10095 10096 10097 10098 10099 10100 10101 10102 10103 10104 10105 10106 10107 10108 10109 10110 10111 10112 10113 10114 10115 10116 10117 10118 10119 10120 10121 10122 10123 10124 10125 10126 10127 10128 10129 10130 10131 10132 10133 10134
static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
{
	struct tg3 *tp = netdev_priv(dev);
	u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
	u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;

	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
		max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
		max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
		max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
		min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
	}

	if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
	    (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
	    (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
	    (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
	    (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
	    (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
	    (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
	    (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
	    (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
	    (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
		return -EINVAL;

	/* No rx interrupts will be generated if both are zero */
	if ((ec->rx_coalesce_usecs == 0) &&
	    (ec->rx_max_coalesced_frames == 0))
		return -EINVAL;

	/* No tx interrupts will be generated if both are zero */
	if ((ec->tx_coalesce_usecs == 0) &&
	    (ec->tx_max_coalesced_frames == 0))
		return -EINVAL;

	/* Only copy relevant parameters, ignore all others. */
	tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
	tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
	tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
	tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
	tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
	tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
	tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
	tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
	tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;

	if (netif_running(dev)) {
		tg3_full_lock(tp, 0);
		__tg3_set_coalesce(tp, &tp->coal);
		tg3_full_unlock(tp);
	}
	return 0;
}

10135
static const struct ethtool_ops tg3_ethtool_ops = {
L
Linus Torvalds 已提交
10136 10137 10138 10139 10140 10141 10142 10143 10144 10145 10146 10147 10148 10149 10150 10151 10152 10153 10154 10155 10156 10157 10158
	.get_settings		= tg3_get_settings,
	.set_settings		= tg3_set_settings,
	.get_drvinfo		= tg3_get_drvinfo,
	.get_regs_len		= tg3_get_regs_len,
	.get_regs		= tg3_get_regs,
	.get_wol		= tg3_get_wol,
	.set_wol		= tg3_set_wol,
	.get_msglevel		= tg3_get_msglevel,
	.set_msglevel		= tg3_set_msglevel,
	.nway_reset		= tg3_nway_reset,
	.get_link		= ethtool_op_get_link,
	.get_eeprom_len		= tg3_get_eeprom_len,
	.get_eeprom		= tg3_get_eeprom,
	.set_eeprom		= tg3_set_eeprom,
	.get_ringparam		= tg3_get_ringparam,
	.set_ringparam		= tg3_set_ringparam,
	.get_pauseparam		= tg3_get_pauseparam,
	.set_pauseparam		= tg3_set_pauseparam,
	.get_rx_csum		= tg3_get_rx_csum,
	.set_rx_csum		= tg3_set_rx_csum,
	.set_tx_csum		= tg3_set_tx_csum,
	.set_sg			= ethtool_op_set_sg,
	.set_tso		= tg3_set_tso,
10159
	.self_test		= tg3_self_test,
L
Linus Torvalds 已提交
10160
	.get_strings		= tg3_get_strings,
M
Michael Chan 已提交
10161
	.phys_id		= tg3_phys_id,
L
Linus Torvalds 已提交
10162
	.get_ethtool_stats	= tg3_get_ethtool_stats,
10163
	.get_coalesce		= tg3_get_coalesce,
M
Michael Chan 已提交
10164
	.set_coalesce		= tg3_set_coalesce,
10165
	.get_sset_count		= tg3_get_sset_count,
L
Linus Torvalds 已提交
10166 10167 10168 10169
};

static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
{
M
Michael Chan 已提交
10170
	u32 cursize, val, magic;
L
Linus Torvalds 已提交
10171 10172 10173

	tp->nvram_size = EEPROM_CHIP_SIZE;

10174
	if (tg3_nvram_read(tp, 0, &magic) != 0)
L
Linus Torvalds 已提交
10175 10176
		return;

10177 10178 10179
	if ((magic != TG3_EEPROM_MAGIC) &&
	    ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
	    ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
L
Linus Torvalds 已提交
10180 10181 10182 10183 10184 10185 10186
		return;

	/*
	 * Size the chip by reading offsets at increasing powers of two.
	 * When we encounter our validation signature, we know the addressing
	 * has wrapped around, and thus have our chip size.
	 */
M
Michael Chan 已提交
10187
	cursize = 0x10;
L
Linus Torvalds 已提交
10188 10189

	while (cursize < tp->nvram_size) {
10190
		if (tg3_nvram_read(tp, cursize, &val) != 0)
L
Linus Torvalds 已提交
10191 10192
			return;

M
Michael Chan 已提交
10193
		if (val == magic)
L
Linus Torvalds 已提交
10194 10195 10196 10197 10198 10199 10200
			break;

		cursize <<= 1;
	}

	tp->nvram_size = cursize;
}
10201

L
Linus Torvalds 已提交
10202 10203 10204 10205
static void __devinit tg3_get_nvram_size(struct tg3 *tp)
{
	u32 val;

M
Matt Carlson 已提交
10206 10207
	if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
	    tg3_nvram_read(tp, 0, &val) != 0)
M
Michael Chan 已提交
10208 10209 10210
		return;

	/* Selfboot format */
M
Michael Chan 已提交
10211
	if (val != TG3_EEPROM_MAGIC) {
M
Michael Chan 已提交
10212 10213 10214 10215
		tg3_get_eeprom_size(tp);
		return;
	}

10216
	if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
L
Linus Torvalds 已提交
10217
		if (val != 0) {
10218 10219 10220 10221 10222 10223 10224 10225 10226 10227 10228 10229
			/* This is confusing.  We want to operate on the
			 * 16-bit value at offset 0xf2.  The tg3_nvram_read()
			 * call will read from NVRAM and byteswap the data
			 * according to the byteswapping settings for all
			 * other register accesses.  This ensures the data we
			 * want will always reside in the lower 16-bits.
			 * However, the data in NVRAM is in LE format, which
			 * means the data from the NVRAM read will always be
			 * opposite the endianness of the CPU.  The 16-bit
			 * byteswap then brings the data to CPU endianness.
			 */
			tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
L
Linus Torvalds 已提交
10230 10231 10232
			return;
		}
	}
M
Matt Carlson 已提交
10233
	tp->nvram_size = TG3_NVRAM_SIZE_512KB;
L
Linus Torvalds 已提交
10234 10235 10236 10237 10238 10239 10240 10241 10242 10243 10244 10245 10246 10247 10248
}

static void __devinit tg3_get_nvram_info(struct tg3 *tp)
{
	u32 nvcfg1;

	nvcfg1 = tr32(NVRAM_CFG1);
	if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
		tp->tg3_flags2 |= TG3_FLG2_FLASH;
	}
	else {
		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
		tw32(NVRAM_CFG1, nvcfg1);
	}

M
Michael Chan 已提交
10249
	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
M
Michael Chan 已提交
10250
	    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
L
Linus Torvalds 已提交
10251 10252 10253 10254 10255 10256 10257 10258 10259 10260 10261 10262 10263 10264 10265 10266 10267 10268 10269 10270 10271 10272 10273 10274 10275 10276 10277 10278 10279 10280 10281 10282 10283 10284 10285 10286 10287 10288
		switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
			case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
				tp->nvram_jedecnum = JEDEC_ATMEL;
				tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
				tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
				break;
			case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
				tp->nvram_jedecnum = JEDEC_ATMEL;
                         	tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
				break;
			case FLASH_VENDOR_ATMEL_EEPROM:
				tp->nvram_jedecnum = JEDEC_ATMEL;
                         	tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
				tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
				break;
			case FLASH_VENDOR_ST:
				tp->nvram_jedecnum = JEDEC_ST;
				tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
				tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
				break;
			case FLASH_VENDOR_SAIFUN:
				tp->nvram_jedecnum = JEDEC_SAIFUN;
				tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
				break;
			case FLASH_VENDOR_SST_SMALL:
			case FLASH_VENDOR_SST_LARGE:
				tp->nvram_jedecnum = JEDEC_SST;
				tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
				break;
		}
	}
	else {
		tp->nvram_jedecnum = JEDEC_ATMEL;
		tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
		tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
	}
}

10289 10290 10291 10292 10293 10294
static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
{
	u32 nvcfg1;

	nvcfg1 = tr32(NVRAM_CFG1);

10295 10296 10297 10298
	/* NVRAM protection for TPM */
	if (nvcfg1 & (1 << 27))
		tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;

10299 10300 10301 10302 10303 10304 10305 10306 10307 10308 10309 10310 10311 10312 10313 10314 10315 10316 10317 10318 10319 10320 10321 10322 10323 10324 10325 10326 10327 10328 10329 10330 10331 10332 10333 10334 10335 10336 10337 10338 10339 10340 10341 10342 10343 10344 10345 10346 10347 10348 10349
	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
		case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
		case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
			tp->nvram_jedecnum = JEDEC_ATMEL;
			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
			break;
		case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
			tp->nvram_jedecnum = JEDEC_ATMEL;
			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
			tp->tg3_flags2 |= TG3_FLG2_FLASH;
			break;
		case FLASH_5752VENDOR_ST_M45PE10:
		case FLASH_5752VENDOR_ST_M45PE20:
		case FLASH_5752VENDOR_ST_M45PE40:
			tp->nvram_jedecnum = JEDEC_ST;
			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
			tp->tg3_flags2 |= TG3_FLG2_FLASH;
			break;
	}

	if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
		switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
			case FLASH_5752PAGE_SIZE_256:
				tp->nvram_pagesize = 256;
				break;
			case FLASH_5752PAGE_SIZE_512:
				tp->nvram_pagesize = 512;
				break;
			case FLASH_5752PAGE_SIZE_1K:
				tp->nvram_pagesize = 1024;
				break;
			case FLASH_5752PAGE_SIZE_2K:
				tp->nvram_pagesize = 2048;
				break;
			case FLASH_5752PAGE_SIZE_4K:
				tp->nvram_pagesize = 4096;
				break;
			case FLASH_5752PAGE_SIZE_264:
				tp->nvram_pagesize = 264;
				break;
		}
	}
	else {
		/* For eeprom, set pagesize to maximum eeprom size */
		tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;

		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
		tw32(NVRAM_CFG1, nvcfg1);
	}
}

M
Michael Chan 已提交
10350 10351
static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
{
M
Matt Carlson 已提交
10352
	u32 nvcfg1, protect = 0;
M
Michael Chan 已提交
10353 10354 10355 10356

	nvcfg1 = tr32(NVRAM_CFG1);

	/* NVRAM protection for TPM */
M
Matt Carlson 已提交
10357
	if (nvcfg1 & (1 << 27)) {
M
Michael Chan 已提交
10358
		tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
M
Matt Carlson 已提交
10359 10360
		protect = 1;
	}
M
Michael Chan 已提交
10361

M
Matt Carlson 已提交
10362 10363
	nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
	switch (nvcfg1) {
M
Michael Chan 已提交
10364 10365 10366
		case FLASH_5755VENDOR_ATMEL_FLASH_1:
		case FLASH_5755VENDOR_ATMEL_FLASH_2:
		case FLASH_5755VENDOR_ATMEL_FLASH_3:
10367
		case FLASH_5755VENDOR_ATMEL_FLASH_5:
M
Michael Chan 已提交
10368 10369 10370 10371
			tp->nvram_jedecnum = JEDEC_ATMEL;
			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
			tp->tg3_flags2 |= TG3_FLG2_FLASH;
			tp->nvram_pagesize = 264;
10372 10373
			if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
			    nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
M
Matt Carlson 已提交
10374 10375
				tp->nvram_size = (protect ? 0x3e200 :
						  TG3_NVRAM_SIZE_512KB);
M
Matt Carlson 已提交
10376
			else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
M
Matt Carlson 已提交
10377 10378
				tp->nvram_size = (protect ? 0x1f200 :
						  TG3_NVRAM_SIZE_256KB);
M
Matt Carlson 已提交
10379
			else
M
Matt Carlson 已提交
10380 10381
				tp->nvram_size = (protect ? 0x1f200 :
						  TG3_NVRAM_SIZE_128KB);
M
Michael Chan 已提交
10382 10383 10384 10385 10386 10387 10388 10389
			break;
		case FLASH_5752VENDOR_ST_M45PE10:
		case FLASH_5752VENDOR_ST_M45PE20:
		case FLASH_5752VENDOR_ST_M45PE40:
			tp->nvram_jedecnum = JEDEC_ST;
			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
			tp->tg3_flags2 |= TG3_FLG2_FLASH;
			tp->nvram_pagesize = 256;
M
Matt Carlson 已提交
10390
			if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
M
Matt Carlson 已提交
10391 10392 10393
				tp->nvram_size = (protect ?
						  TG3_NVRAM_SIZE_64KB :
						  TG3_NVRAM_SIZE_128KB);
M
Matt Carlson 已提交
10394
			else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
M
Matt Carlson 已提交
10395 10396 10397
				tp->nvram_size = (protect ?
						  TG3_NVRAM_SIZE_64KB :
						  TG3_NVRAM_SIZE_256KB);
M
Matt Carlson 已提交
10398
			else
M
Matt Carlson 已提交
10399 10400 10401
				tp->nvram_size = (protect ?
						  TG3_NVRAM_SIZE_128KB :
						  TG3_NVRAM_SIZE_512KB);
M
Michael Chan 已提交
10402 10403 10404 10405
			break;
	}
}

M
Michael Chan 已提交
10406 10407 10408 10409 10410 10411 10412 10413 10414 10415 10416 10417 10418 10419 10420 10421 10422 10423 10424 10425 10426 10427 10428 10429 10430 10431 10432 10433 10434 10435 10436 10437 10438 10439 10440 10441 10442 10443
static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
{
	u32 nvcfg1;

	nvcfg1 = tr32(NVRAM_CFG1);

	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
		case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
		case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
		case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
		case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
			tp->nvram_jedecnum = JEDEC_ATMEL;
			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
			tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;

			nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
			tw32(NVRAM_CFG1, nvcfg1);
			break;
		case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
		case FLASH_5755VENDOR_ATMEL_FLASH_1:
		case FLASH_5755VENDOR_ATMEL_FLASH_2:
		case FLASH_5755VENDOR_ATMEL_FLASH_3:
			tp->nvram_jedecnum = JEDEC_ATMEL;
			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
			tp->tg3_flags2 |= TG3_FLG2_FLASH;
			tp->nvram_pagesize = 264;
			break;
		case FLASH_5752VENDOR_ST_M45PE10:
		case FLASH_5752VENDOR_ST_M45PE20:
		case FLASH_5752VENDOR_ST_M45PE40:
			tp->nvram_jedecnum = JEDEC_ST;
			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
			tp->tg3_flags2 |= TG3_FLG2_FLASH;
			tp->nvram_pagesize = 256;
			break;
	}
}

10444 10445 10446 10447 10448 10449 10450 10451 10452 10453 10454 10455 10456 10457 10458 10459 10460 10461 10462 10463 10464 10465 10466 10467 10468 10469 10470 10471 10472 10473 10474 10475 10476 10477 10478 10479 10480 10481 10482 10483 10484 10485 10486 10487 10488 10489 10490 10491 10492 10493 10494
static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
{
	u32 nvcfg1, protect = 0;

	nvcfg1 = tr32(NVRAM_CFG1);

	/* NVRAM protection for TPM */
	if (nvcfg1 & (1 << 27)) {
		tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
		protect = 1;
	}

	nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
	switch (nvcfg1) {
		case FLASH_5761VENDOR_ATMEL_ADB021D:
		case FLASH_5761VENDOR_ATMEL_ADB041D:
		case FLASH_5761VENDOR_ATMEL_ADB081D:
		case FLASH_5761VENDOR_ATMEL_ADB161D:
		case FLASH_5761VENDOR_ATMEL_MDB021D:
		case FLASH_5761VENDOR_ATMEL_MDB041D:
		case FLASH_5761VENDOR_ATMEL_MDB081D:
		case FLASH_5761VENDOR_ATMEL_MDB161D:
			tp->nvram_jedecnum = JEDEC_ATMEL;
			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
			tp->tg3_flags2 |= TG3_FLG2_FLASH;
			tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
			tp->nvram_pagesize = 256;
			break;
		case FLASH_5761VENDOR_ST_A_M45PE20:
		case FLASH_5761VENDOR_ST_A_M45PE40:
		case FLASH_5761VENDOR_ST_A_M45PE80:
		case FLASH_5761VENDOR_ST_A_M45PE16:
		case FLASH_5761VENDOR_ST_M_M45PE20:
		case FLASH_5761VENDOR_ST_M_M45PE40:
		case FLASH_5761VENDOR_ST_M_M45PE80:
		case FLASH_5761VENDOR_ST_M_M45PE16:
			tp->nvram_jedecnum = JEDEC_ST;
			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
			tp->tg3_flags2 |= TG3_FLG2_FLASH;
			tp->nvram_pagesize = 256;
			break;
	}

	if (protect) {
		tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
	} else {
		switch (nvcfg1) {
			case FLASH_5761VENDOR_ATMEL_ADB161D:
			case FLASH_5761VENDOR_ATMEL_MDB161D:
			case FLASH_5761VENDOR_ST_A_M45PE16:
			case FLASH_5761VENDOR_ST_M_M45PE16:
M
Matt Carlson 已提交
10495
				tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10496 10497 10498 10499 10500
				break;
			case FLASH_5761VENDOR_ATMEL_ADB081D:
			case FLASH_5761VENDOR_ATMEL_MDB081D:
			case FLASH_5761VENDOR_ST_A_M45PE80:
			case FLASH_5761VENDOR_ST_M_M45PE80:
M
Matt Carlson 已提交
10501
				tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10502 10503 10504 10505 10506
				break;
			case FLASH_5761VENDOR_ATMEL_ADB041D:
			case FLASH_5761VENDOR_ATMEL_MDB041D:
			case FLASH_5761VENDOR_ST_A_M45PE40:
			case FLASH_5761VENDOR_ST_M_M45PE40:
M
Matt Carlson 已提交
10507
				tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10508 10509 10510 10511 10512
				break;
			case FLASH_5761VENDOR_ATMEL_ADB021D:
			case FLASH_5761VENDOR_ATMEL_MDB021D:
			case FLASH_5761VENDOR_ST_A_M45PE20:
			case FLASH_5761VENDOR_ST_M_M45PE20:
M
Matt Carlson 已提交
10513
				tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10514 10515 10516 10517 10518
				break;
		}
	}
}

M
Michael Chan 已提交
10519 10520 10521 10522 10523 10524 10525
static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
{
	tp->nvram_jedecnum = JEDEC_ATMEL;
	tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
	tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
}

M
Matt Carlson 已提交
10526 10527 10528 10529 10530 10531 10532 10533 10534 10535 10536 10537 10538 10539 10540 10541 10542 10543 10544 10545 10546 10547 10548 10549 10550 10551 10552 10553 10554 10555 10556 10557 10558 10559 10560 10561 10562 10563 10564 10565 10566 10567 10568 10569 10570 10571 10572 10573 10574 10575 10576 10577 10578 10579 10580 10581 10582 10583 10584 10585 10586 10587 10588
static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
{
	u32 nvcfg1;

	nvcfg1 = tr32(NVRAM_CFG1);

	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
	case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
	case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
		tp->nvram_jedecnum = JEDEC_ATMEL;
		tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
		tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;

		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
		tw32(NVRAM_CFG1, nvcfg1);
		return;
	case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
	case FLASH_57780VENDOR_ATMEL_AT45DB011D:
	case FLASH_57780VENDOR_ATMEL_AT45DB011B:
	case FLASH_57780VENDOR_ATMEL_AT45DB021D:
	case FLASH_57780VENDOR_ATMEL_AT45DB021B:
	case FLASH_57780VENDOR_ATMEL_AT45DB041D:
	case FLASH_57780VENDOR_ATMEL_AT45DB041B:
		tp->nvram_jedecnum = JEDEC_ATMEL;
		tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
		tp->tg3_flags2 |= TG3_FLG2_FLASH;

		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
		case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
		case FLASH_57780VENDOR_ATMEL_AT45DB011D:
		case FLASH_57780VENDOR_ATMEL_AT45DB011B:
			tp->nvram_size = TG3_NVRAM_SIZE_128KB;
			break;
		case FLASH_57780VENDOR_ATMEL_AT45DB021D:
		case FLASH_57780VENDOR_ATMEL_AT45DB021B:
			tp->nvram_size = TG3_NVRAM_SIZE_256KB;
			break;
		case FLASH_57780VENDOR_ATMEL_AT45DB041D:
		case FLASH_57780VENDOR_ATMEL_AT45DB041B:
			tp->nvram_size = TG3_NVRAM_SIZE_512KB;
			break;
		}
		break;
	case FLASH_5752VENDOR_ST_M45PE10:
	case FLASH_5752VENDOR_ST_M45PE20:
	case FLASH_5752VENDOR_ST_M45PE40:
		tp->nvram_jedecnum = JEDEC_ST;
		tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
		tp->tg3_flags2 |= TG3_FLG2_FLASH;

		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
		case FLASH_5752VENDOR_ST_M45PE10:
			tp->nvram_size = TG3_NVRAM_SIZE_128KB;
			break;
		case FLASH_5752VENDOR_ST_M45PE20:
			tp->nvram_size = TG3_NVRAM_SIZE_256KB;
			break;
		case FLASH_5752VENDOR_ST_M45PE40:
			tp->nvram_size = TG3_NVRAM_SIZE_512KB;
			break;
		}
		break;
	default:
M
Matt Carlson 已提交
10589
		tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
M
Matt Carlson 已提交
10590 10591 10592 10593 10594 10595 10596 10597 10598 10599 10600 10601 10602 10603 10604 10605 10606 10607 10608 10609 10610 10611 10612 10613 10614 10615 10616 10617 10618 10619 10620 10621 10622
		return;
	}

	switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
	case FLASH_5752PAGE_SIZE_256:
		tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
		tp->nvram_pagesize = 256;
		break;
	case FLASH_5752PAGE_SIZE_512:
		tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
		tp->nvram_pagesize = 512;
		break;
	case FLASH_5752PAGE_SIZE_1K:
		tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
		tp->nvram_pagesize = 1024;
		break;
	case FLASH_5752PAGE_SIZE_2K:
		tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
		tp->nvram_pagesize = 2048;
		break;
	case FLASH_5752PAGE_SIZE_4K:
		tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
		tp->nvram_pagesize = 4096;
		break;
	case FLASH_5752PAGE_SIZE_264:
		tp->nvram_pagesize = 264;
		break;
	case FLASH_5752PAGE_SIZE_528:
		tp->nvram_pagesize = 528;
		break;
	}
}

L
Linus Torvalds 已提交
10623 10624 10625 10626 10627 10628 10629 10630
/* Chips other than 5700/5701 use the NVRAM for fetching info. */
static void __devinit tg3_nvram_init(struct tg3 *tp)
{
	tw32_f(GRC_EEPROM_ADDR,
	     (EEPROM_ADDR_FSM_RESET |
	      (EEPROM_DEFAULT_CLOCK_PERIOD <<
	       EEPROM_ADDR_CLKPERD_SHIFT)));

M
Michael Chan 已提交
10631
	msleep(1);
L
Linus Torvalds 已提交
10632 10633 10634 10635 10636 10637 10638 10639 10640 10641

	/* Enable seeprom accesses. */
	tw32_f(GRC_LOCAL_CTRL,
	     tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
	udelay(100);

	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
		tp->tg3_flags |= TG3_FLAG_NVRAM;

M
Michael Chan 已提交
10642 10643 10644 10645 10646
		if (tg3_nvram_lock(tp)) {
			printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
			       "tg3_nvram_init failed.\n", tp->dev->name);
			return;
		}
10647
		tg3_enable_nvram_access(tp);
L
Linus Torvalds 已提交
10648

M
Matt Carlson 已提交
10649 10650
		tp->nvram_size = 0;

10651 10652
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
			tg3_get_5752_nvram_info(tp);
M
Michael Chan 已提交
10653 10654
		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
			tg3_get_5755_nvram_info(tp);
M
Matt Carlson 已提交
10655
		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
M
Matt Carlson 已提交
10656 10657
			 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
			 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
M
Michael Chan 已提交
10658
			tg3_get_5787_nvram_info(tp);
10659 10660
		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
			tg3_get_5761_nvram_info(tp);
M
Michael Chan 已提交
10661 10662
		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
			tg3_get_5906_nvram_info(tp);
M
Matt Carlson 已提交
10663 10664
		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
			tg3_get_57780_nvram_info(tp);
10665 10666 10667
		else
			tg3_get_nvram_info(tp);

M
Matt Carlson 已提交
10668 10669
		if (tp->nvram_size == 0)
			tg3_get_nvram_size(tp);
L
Linus Torvalds 已提交
10670

10671
		tg3_disable_nvram_access(tp);
M
Michael Chan 已提交
10672
		tg3_nvram_unlock(tp);
L
Linus Torvalds 已提交
10673 10674 10675 10676 10677 10678 10679 10680 10681 10682 10683 10684 10685 10686 10687

	} else {
		tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);

		tg3_get_eeprom_size(tp);
	}
}

static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
				    u32 offset, u32 len, u8 *buf)
{
	int i, j, rc = 0;
	u32 val;

	for (i = 0; i < len; i += 4) {
A
Al Viro 已提交
10688
		u32 addr;
10689
		__be32 data;
L
Linus Torvalds 已提交
10690 10691 10692 10693 10694

		addr = offset + i;

		memcpy(&data, buf + i, 4);

M
Matt Carlson 已提交
10695 10696 10697 10698 10699 10700 10701
		/*
		 * The SEEPROM interface expects the data to always be opposite
		 * the native endian format.  We accomplish this by reversing
		 * all the operations that would have been performed on the
		 * data from a call to tg3_nvram_read_be32().
		 */
		tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
L
Linus Torvalds 已提交
10702 10703 10704 10705 10706 10707 10708 10709 10710 10711 10712

		val = tr32(GRC_EEPROM_ADDR);
		tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);

		val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
			EEPROM_ADDR_READ);
		tw32(GRC_EEPROM_ADDR, val |
			(0 << EEPROM_ADDR_DEVID_SHIFT) |
			(addr & EEPROM_ADDR_ADDR_MASK) |
			EEPROM_ADDR_START |
			EEPROM_ADDR_WRITE);
10713

M
Michael Chan 已提交
10714
		for (j = 0; j < 1000; j++) {
L
Linus Torvalds 已提交
10715 10716 10717 10718
			val = tr32(GRC_EEPROM_ADDR);

			if (val & EEPROM_ADDR_COMPLETE)
				break;
M
Michael Chan 已提交
10719
			msleep(1);
L
Linus Torvalds 已提交
10720 10721 10722 10723 10724 10725 10726 10727 10728 10729 10730 10731 10732 10733 10734 10735 10736 10737 10738 10739 10740 10741 10742 10743 10744 10745
		}
		if (!(val & EEPROM_ADDR_COMPLETE)) {
			rc = -EBUSY;
			break;
		}
	}

	return rc;
}

/* offset and length are dword aligned */
static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
		u8 *buf)
{
	int ret = 0;
	u32 pagesize = tp->nvram_pagesize;
	u32 pagemask = pagesize - 1;
	u32 nvram_cmd;
	u8 *tmp;

	tmp = kmalloc(pagesize, GFP_KERNEL);
	if (tmp == NULL)
		return -ENOMEM;

	while (len) {
		int j;
10746
		u32 phy_addr, page_off, size;
L
Linus Torvalds 已提交
10747 10748

		phy_addr = offset & ~pagemask;
10749

L
Linus Torvalds 已提交
10750
		for (j = 0; j < pagesize; j += 4) {
10751 10752 10753
			ret = tg3_nvram_read_be32(tp, phy_addr + j,
						  (__be32 *) (tmp + j));
			if (ret)
L
Linus Torvalds 已提交
10754 10755 10756 10757 10758 10759 10760 10761 10762 10763 10764 10765 10766 10767 10768 10769
				break;
		}
		if (ret)
			break;

	        page_off = offset & pagemask;
		size = pagesize;
		if (len < size)
			size = len;

		len -= size;

		memcpy(tmp + page_off, buf, size);

		offset = offset + (pagesize - page_off);

10770
		tg3_enable_nvram_access(tp);
L
Linus Torvalds 已提交
10771 10772 10773 10774 10775 10776 10777 10778 10779 10780 10781 10782 10783 10784 10785 10786 10787 10788 10789 10790 10791 10792 10793 10794 10795 10796

		/*
		 * Before we can erase the flash page, we need
		 * to issue a special "write enable" command.
		 */
		nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;

		if (tg3_nvram_exec_cmd(tp, nvram_cmd))
			break;

		/* Erase the target page */
		tw32(NVRAM_ADDR, phy_addr);

		nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
			NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;

	        if (tg3_nvram_exec_cmd(tp, nvram_cmd))
			break;

		/* Issue another write enable to start the write. */
		nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;

		if (tg3_nvram_exec_cmd(tp, nvram_cmd))
			break;

		for (j = 0; j < pagesize; j += 4) {
A
Al Viro 已提交
10797
			__be32 data;
L
Linus Torvalds 已提交
10798

A
Al Viro 已提交
10799
			data = *((__be32 *) (tmp + j));
10800

A
Al Viro 已提交
10801
			tw32(NVRAM_WRDATA, be32_to_cpu(data));
L
Linus Torvalds 已提交
10802 10803 10804 10805 10806 10807 10808 10809 10810 10811 10812 10813 10814 10815 10816 10817 10818 10819 10820 10821 10822 10823 10824 10825 10826 10827 10828 10829 10830 10831 10832 10833 10834

			tw32(NVRAM_ADDR, phy_addr + j);

			nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
				NVRAM_CMD_WR;

			if (j == 0)
				nvram_cmd |= NVRAM_CMD_FIRST;
			else if (j == (pagesize - 4))
				nvram_cmd |= NVRAM_CMD_LAST;

			if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
				break;
		}
		if (ret)
			break;
	}

	nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
	tg3_nvram_exec_cmd(tp, nvram_cmd);

	kfree(tmp);

	return ret;
}

/* offset and length are dword aligned */
static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
		u8 *buf)
{
	int i, ret = 0;

	for (i = 0; i < len; i += 4, offset += 4) {
A
Al Viro 已提交
10835 10836
		u32 page_off, phy_addr, nvram_cmd;
		__be32 data;
L
Linus Torvalds 已提交
10837 10838

		memcpy(&data, buf + i, 4);
A
Al Viro 已提交
10839
		tw32(NVRAM_WRDATA, be32_to_cpu(data));
L
Linus Torvalds 已提交
10840 10841 10842

	        page_off = offset % tp->nvram_pagesize;

M
Michael Chan 已提交
10843
		phy_addr = tg3_nvram_phys_addr(tp, offset);
L
Linus Torvalds 已提交
10844 10845 10846 10847 10848 10849 10850

		tw32(NVRAM_ADDR, phy_addr);

		nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;

	        if ((page_off == 0) || (i == 0))
			nvram_cmd |= NVRAM_CMD_FIRST;
M
Michael Chan 已提交
10851
		if (page_off == (tp->nvram_pagesize - 4))
L
Linus Torvalds 已提交
10852 10853 10854 10855 10856
			nvram_cmd |= NVRAM_CMD_LAST;

		if (i == (len - 4))
			nvram_cmd |= NVRAM_CMD_LAST;

M
Matt Carlson 已提交
10857 10858
		if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
		    !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
M
Michael Chan 已提交
10859 10860
		    (tp->nvram_jedecnum == JEDEC_ST) &&
		    (nvram_cmd & NVRAM_CMD_FIRST)) {
L
Linus Torvalds 已提交
10861 10862 10863 10864 10865 10866 10867 10868 10869 10870 10871 10872 10873 10874 10875 10876 10877 10878 10879 10880 10881 10882 10883 10884

			if ((ret = tg3_nvram_exec_cmd(tp,
				NVRAM_CMD_WREN | NVRAM_CMD_GO |
				NVRAM_CMD_DONE)))

				break;
		}
		if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
			/* We always do complete word writes to eeprom. */
			nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
		}

		if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
			break;
	}
	return ret;
}

/* offset and length are dword aligned */
static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
{
	int ret;

	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
M
Michael Chan 已提交
10885 10886
		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
		       ~GRC_LCLCTRL_GPIO_OUTPUT1);
L
Linus Torvalds 已提交
10887 10888 10889 10890 10891 10892 10893 10894 10895
		udelay(40);
	}

	if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
		ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
	}
	else {
		u32 grc_mode;

M
Michael Chan 已提交
10896 10897 10898
		ret = tg3_nvram_lock(tp);
		if (ret)
			return ret;
L
Linus Torvalds 已提交
10899

10900 10901 10902
		tg3_enable_nvram_access(tp);
		if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
		    !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
L
Linus Torvalds 已提交
10903 10904 10905 10906 10907 10908 10909 10910 10911 10912 10913 10914 10915 10916 10917 10918 10919 10920 10921
			tw32(NVRAM_WRITE1, 0x406);

		grc_mode = tr32(GRC_MODE);
		tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);

		if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
			!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {

			ret = tg3_nvram_write_block_buffered(tp, offset, len,
				buf);
		}
		else {
			ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
				buf);
		}

		grc_mode = tr32(GRC_MODE);
		tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);

10922
		tg3_disable_nvram_access(tp);
L
Linus Torvalds 已提交
10923 10924 10925 10926
		tg3_nvram_unlock(tp);
	}

	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
M
Michael Chan 已提交
10927
		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
L
Linus Torvalds 已提交
10928 10929 10930 10931 10932 10933 10934 10935 10936 10937 10938 10939 10940 10941 10942 10943 10944 10945 10946 10947 10948 10949 10950 10951 10952 10953 10954 10955 10956 10957 10958 10959 10960 10961 10962 10963 10964 10965 10966 10967 10968 10969 10970 10971 10972 10973 10974 10975 10976 10977 10978 10979 10980 10981 10982 10983 10984 10985 10986 10987 10988 10989 10990
		udelay(40);
	}

	return ret;
}

struct subsys_tbl_ent {
	u16 subsys_vendor, subsys_devid;
	u32 phy_id;
};

static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
	/* Broadcom boards. */
	{ PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
	{ PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
	{ PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
	{ PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },		    /* BCM95700A9 */
	{ PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
	{ PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
	{ PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },		    /* BCM95701A7 */
	{ PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
	{ PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
	{ PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
	{ PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */

	/* 3com boards. */
	{ PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
	{ PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
	{ PCI_VENDOR_ID_3COM, 0x1004, 0 },		/* 3C996SX */
	{ PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
	{ PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */

	/* DELL boards. */
	{ PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
	{ PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
	{ PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
	{ PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */

	/* Compaq boards. */
	{ PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
	{ PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
	{ PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },		  /* CHANGELING */
	{ PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
	{ PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */

	/* IBM boards. */
	{ PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
};

static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
		if ((subsys_id_to_phy_id[i].subsys_vendor ==
		     tp->pdev->subsystem_vendor) &&
		    (subsys_id_to_phy_id[i].subsys_devid ==
		     tp->pdev->subsystem_device))
			return &subsys_id_to_phy_id[i];
	}
	return NULL;
}

10991
static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
L
Linus Torvalds 已提交
10992 10993
{
	u32 val;
10994 10995 10996 10997 10998 10999 11000 11001 11002
	u16 pmcsr;

	/* On some early chips the SRAM cannot be accessed in D3hot state,
	 * so need make sure we're in D0.
	 */
	pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
	pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
	pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
	msleep(1);
11003 11004 11005 11006 11007 11008

	/* Make sure register accesses (indirect or otherwise)
	 * will function correctly.
	 */
	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
			       tp->misc_host_ctrl);
L
Linus Torvalds 已提交
11009

11010 11011 11012 11013 11014 11015 11016 11017
	/* The memory arbiter has to be enabled in order for SRAM accesses
	 * to succeed.  Normally on powerup the tg3 chip firmware will make
	 * sure it is enabled, but other entities such as system netboot
	 * code might disable it.
	 */
	val = tr32(MEMARB_MODE);
	tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);

L
Linus Torvalds 已提交
11018
	tp->phy_id = PHY_ID_INVALID;
11019 11020
	tp->led_ctrl = LED_CTRL_MODE_PHY_1;

G
Gary Zambrano 已提交
11021 11022
	/* Assume an onboard device and WOL capable by default.  */
	tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11023

M
Michael Chan 已提交
11024
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
M
Michael Chan 已提交
11025
		if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
M
Michael Chan 已提交
11026
			tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
M
Michael Chan 已提交
11027 11028
			tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
		}
M
Matt Carlson 已提交
11029 11030
		val = tr32(VCPU_CFGSHDW);
		if (val & VCPU_CFGSHDW_ASPM_DBNC)
M
Matt Carlson 已提交
11031
			tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
M
Matt Carlson 已提交
11032
		if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
M
Matt Carlson 已提交
11033
		    (val & VCPU_CFGSHDW_WOL_MAGPKT))
M
Matt Carlson 已提交
11034
			tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11035
		goto done;
M
Michael Chan 已提交
11036 11037
	}

L
Linus Torvalds 已提交
11038 11039 11040
	tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
	if (val == NIC_SRAM_DATA_SIG_MAGIC) {
		u32 nic_cfg, led_cfg;
M
Matt Carlson 已提交
11041
		u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11042
		int eeprom_phy_serdes = 0;
L
Linus Torvalds 已提交
11043 11044 11045 11046 11047 11048 11049 11050 11051 11052 11053 11054

		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
		tp->nic_sram_data_cfg = nic_cfg;

		tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
		ver >>= NIC_SRAM_DATA_VER_SHIFT;
		if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
		    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
		    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
		    (ver > 0) && (ver < 0x100))
			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);

M
Matt Carlson 已提交
11055 11056 11057
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);

L
Linus Torvalds 已提交
11058 11059 11060 11061 11062 11063 11064 11065 11066 11067 11068 11069 11070 11071 11072
		if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
		    NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
			eeprom_phy_serdes = 1;

		tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
		if (nic_phy_id != 0) {
			u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
			u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;

			eeprom_phy_id  = (id1 >> 16) << 10;
			eeprom_phy_id |= (id2 & 0xfc00) << 16;
			eeprom_phy_id |= (id2 & 0x03ff) <<  0;
		} else
			eeprom_phy_id = 0;

11073
		tp->phy_id = eeprom_phy_id;
M
Michael Chan 已提交
11074
		if (eeprom_phy_serdes) {
M
Michael Chan 已提交
11075
			if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
M
Michael Chan 已提交
11076 11077 11078 11079
				tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
			else
				tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
		}
11080

11081
		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
L
Linus Torvalds 已提交
11082 11083
			led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
				    SHASTA_EXT_LED_MODE_MASK);
11084
		else
L
Linus Torvalds 已提交
11085 11086 11087 11088 11089 11090 11091 11092 11093 11094 11095 11096 11097 11098
			led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;

		switch (led_cfg) {
		default:
		case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
			tp->led_ctrl = LED_CTRL_MODE_PHY_1;
			break;

		case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
			tp->led_ctrl = LED_CTRL_MODE_PHY_2;
			break;

		case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
			tp->led_ctrl = LED_CTRL_MODE_MAC;
M
Michael Chan 已提交
11099 11100 11101 11102 11103 11104 11105 11106 11107 11108

			/* Default to PHY_1_MODE if 0 (MAC_MODE) is
			 * read on some older 5700/5701 bootcode.
			 */
			if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
			    ASIC_REV_5700 ||
			    GET_ASIC_REV(tp->pci_chip_rev_id) ==
			    ASIC_REV_5701)
				tp->led_ctrl = LED_CTRL_MODE_PHY_1;

L
Linus Torvalds 已提交
11109 11110 11111 11112 11113 11114 11115 11116 11117 11118 11119 11120 11121 11122 11123 11124 11125 11126 11127 11128 11129
			break;

		case SHASTA_EXT_LED_SHARED:
			tp->led_ctrl = LED_CTRL_MODE_SHARED;
			if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
			    tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
				tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
						 LED_CTRL_MODE_PHY_2);
			break;

		case SHASTA_EXT_LED_MAC:
			tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
			break;

		case SHASTA_EXT_LED_COMBO:
			tp->led_ctrl = LED_CTRL_MODE_COMBO;
			if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
				tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
						 LED_CTRL_MODE_PHY_2);
			break;

11130
		}
L
Linus Torvalds 已提交
11131 11132 11133 11134 11135 11136

		if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
		     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
		    tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
			tp->led_ctrl = LED_CTRL_MODE_PHY_2;

11137 11138
		if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
			tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11139

M
Michael Chan 已提交
11140
		if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
L
Linus Torvalds 已提交
11141
			tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
M
Michael Chan 已提交
11142 11143 11144 11145 11146 11147
			if ((tp->pdev->subsystem_vendor ==
			     PCI_VENDOR_ID_ARIMA) &&
			    (tp->pdev->subsystem_device == 0x205a ||
			     tp->pdev->subsystem_device == 0x2063))
				tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
		} else {
11148
			tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
M
Michael Chan 已提交
11149 11150
			tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
		}
L
Linus Torvalds 已提交
11151 11152 11153

		if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
			tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11154
			if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
L
Linus Torvalds 已提交
11155 11156
				tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
		}
M
Matt Carlson 已提交
11157 11158 11159

		if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
			(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
M
Matt Carlson 已提交
11160
			tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
M
Matt Carlson 已提交
11161

G
Gary Zambrano 已提交
11162 11163 11164
		if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
		    !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
			tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
L
Linus Torvalds 已提交
11165

11166
		if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11167
		    (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
M
Matt Carlson 已提交
11168 11169
			tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;

L
Linus Torvalds 已提交
11170 11171 11172 11173 11174 11175 11176
		if (cfg2 & (1 << 17))
			tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;

		/* serdes signal pre-emphasis in register 0x590 set by */
		/* bootcode if bit 18 is set */
		if (cfg2 & (1 << 18))
			tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
M
Matt Carlson 已提交
11177

M
Matt Carlson 已提交
11178 11179
		if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
		      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11180 11181 11182
		    (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
			tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;

M
Matt Carlson 已提交
11183 11184 11185 11186 11187 11188 11189
		if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
			u32 cfg3;

			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
			if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
				tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
		}
M
Matt Carlson 已提交
11190 11191 11192 11193 11194 11195 11196

		if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
			tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
		if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
			tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
		if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
			tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
L
Linus Torvalds 已提交
11197
	}
11198 11199 11200 11201
done:
	device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
	device_set_wakeup_enable(&tp->pdev->dev,
				 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11202 11203
}

11204 11205 11206 11207 11208 11209 11210 11211 11212 11213 11214 11215 11216 11217 11218 11219 11220 11221 11222 11223 11224 11225 11226 11227 11228 11229 11230 11231 11232 11233 11234 11235 11236 11237 11238 11239 11240 11241 11242 11243 11244 11245 11246 11247 11248 11249 11250 11251 11252
static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
{
	int i;
	u32 val;

	tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
	tw32(OTP_CTRL, cmd);

	/* Wait for up to 1 ms for command to execute. */
	for (i = 0; i < 100; i++) {
		val = tr32(OTP_STATUS);
		if (val & OTP_STATUS_CMD_DONE)
			break;
		udelay(10);
	}

	return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
}

/* Read the gphy configuration from the OTP region of the chip.  The gphy
 * configuration is a 32-bit value that straddles the alignment boundary.
 * We do two 32-bit reads and then shift and merge the results.
 */
static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
{
	u32 bhalf_otp, thalf_otp;

	tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);

	if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
		return 0;

	tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);

	if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
		return 0;

	thalf_otp = tr32(OTP_READ_DATA);

	tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);

	if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
		return 0;

	bhalf_otp = tr32(OTP_READ_DATA);

	return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
}

11253 11254 11255 11256 11257
static int __devinit tg3_phy_probe(struct tg3 *tp)
{
	u32 hw_phy_id_1, hw_phy_id_2;
	u32 hw_phy_id, hw_phy_id_masked;
	int err;
L
Linus Torvalds 已提交
11258

M
Matt Carlson 已提交
11259 11260 11261
	if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
		return tg3_phy_init(tp);

L
Linus Torvalds 已提交
11262
	/* Reading the PHY ID register can conflict with ASF
11263
	 * firmware access to the PHY hardware.
L
Linus Torvalds 已提交
11264 11265
	 */
	err = 0;
M
Matt Carlson 已提交
11266 11267
	if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
	    (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
L
Linus Torvalds 已提交
11268 11269 11270 11271 11272 11273 11274 11275 11276 11277 11278 11279 11280 11281 11282 11283 11284 11285 11286 11287 11288
		hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
	} else {
		/* Now read the physical PHY_ID from the chip and verify
		 * that it is sane.  If it doesn't look good, we fall back
		 * to either the hard-coded table based PHY_ID and failing
		 * that the value found in the eeprom area.
		 */
		err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
		err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);

		hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
		hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
		hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;

		hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
	}

	if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
		tp->phy_id = hw_phy_id;
		if (hw_phy_id_masked == PHY_ID_BCM8002)
			tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
M
Michael Chan 已提交
11289 11290
		else
			tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
L
Linus Torvalds 已提交
11291
	} else {
11292 11293 11294 11295
		if (tp->phy_id != PHY_ID_INVALID) {
			/* Do nothing, phy ID already set up in
			 * tg3_get_eeprom_hw_cfg().
			 */
L
Linus Torvalds 已提交
11296 11297 11298 11299 11300 11301 11302 11303 11304 11305 11306 11307 11308 11309 11310 11311 11312
		} else {
			struct subsys_tbl_ent *p;

			/* No eeprom signature?  Try the hardcoded
			 * subsys device table.
			 */
			p = lookup_by_subsys(tp);
			if (!p)
				return -ENODEV;

			tp->phy_id = p->phy_id;
			if (!tp->phy_id ||
			    tp->phy_id == PHY_ID_BCM8002)
				tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
		}
	}

M
Michael Chan 已提交
11313
	if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
M
Matt Carlson 已提交
11314
	    !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
L
Linus Torvalds 已提交
11315
	    !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11316
		u32 bmsr, adv_reg, tg3_ctrl, mask;
L
Linus Torvalds 已提交
11317 11318 11319 11320 11321

		tg3_readphy(tp, MII_BMSR, &bmsr);
		if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
		    (bmsr & BMSR_LSTATUS))
			goto skip_phy_reset;
11322

L
Linus Torvalds 已提交
11323 11324 11325 11326 11327 11328 11329 11330 11331 11332 11333 11334 11335 11336 11337 11338 11339
		err = tg3_phy_reset(tp);
		if (err)
			return err;

		adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
			   ADVERTISE_100HALF | ADVERTISE_100FULL |
			   ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
		tg3_ctrl = 0;
		if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
			tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
				    MII_TG3_CTRL_ADV_1000_FULL);
			if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
			    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
				tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
					     MII_TG3_CTRL_ENABLE_AS_MASTER);
		}

11340 11341 11342 11343
		mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
			ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
			ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
		if (!tg3_copper_is_advertising_all(tp, mask)) {
L
Linus Torvalds 已提交
11344 11345 11346 11347 11348 11349 11350 11351 11352 11353 11354 11355 11356 11357 11358 11359 11360 11361 11362 11363 11364 11365 11366 11367 11368 11369
			tg3_writephy(tp, MII_ADVERTISE, adv_reg);

			if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
				tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);

			tg3_writephy(tp, MII_BMCR,
				     BMCR_ANENABLE | BMCR_ANRESTART);
		}
		tg3_phy_set_wirespeed(tp);

		tg3_writephy(tp, MII_ADVERTISE, adv_reg);
		if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
			tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
	}

skip_phy_reset:
	if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
		err = tg3_init_5401phy_dsp(tp);
		if (err)
			return err;
	}

	if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
		err = tg3_init_5401phy_dsp(tp);
	}

M
Michael Chan 已提交
11370
	if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
L
Linus Torvalds 已提交
11371 11372 11373 11374 11375 11376 11377 11378 11379 11380 11381 11382 11383 11384 11385
		tp->link_config.advertising =
			(ADVERTISED_1000baseT_Half |
			 ADVERTISED_1000baseT_Full |
			 ADVERTISED_Autoneg |
			 ADVERTISED_FIBRE);
	if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
		tp->link_config.advertising &=
			~(ADVERTISED_1000baseT_Half |
			  ADVERTISED_1000baseT_Full);

	return err;
}

static void __devinit tg3_read_partno(struct tg3 *tp)
{
11386
	unsigned char vpd_data[256];   /* in little-endian format */
11387
	unsigned int i;
M
Michael Chan 已提交
11388
	u32 magic;
L
Linus Torvalds 已提交
11389

M
Matt Carlson 已提交
11390 11391
	if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
	    tg3_nvram_read(tp, 0x0, &magic))
11392
		goto out_not_found;
L
Linus Torvalds 已提交
11393

M
Michael Chan 已提交
11394
	if (magic == TG3_EEPROM_MAGIC) {
M
Michael Chan 已提交
11395 11396
		for (i = 0; i < 256; i += 4) {
			u32 tmp;
L
Linus Torvalds 已提交
11397

11398 11399 11400 11401 11402
			/* The data is in little-endian format in NVRAM.
			 * Use the big-endian read routines to preserve
			 * the byte order as it exists in NVRAM.
			 */
			if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
M
Michael Chan 已提交
11403 11404
				goto out_not_found;

11405
			memcpy(&vpd_data[i], &tmp, sizeof(tmp));
M
Michael Chan 已提交
11406 11407 11408 11409 11410 11411 11412
		}
	} else {
		int vpd_cap;

		vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
		for (i = 0; i < 256; i += 4) {
			u32 tmp, j = 0;
A
Al Viro 已提交
11413
			__le32 v;
M
Michael Chan 已提交
11414 11415 11416 11417 11418 11419 11420 11421 11422 11423 11424
			u16 tmp16;

			pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
					      i);
			while (j++ < 100) {
				pci_read_config_word(tp->pdev, vpd_cap +
						     PCI_VPD_ADDR, &tmp16);
				if (tmp16 & 0x8000)
					break;
				msleep(1);
			}
11425 11426 11427
			if (!(tmp16 & 0x8000))
				goto out_not_found;

M
Michael Chan 已提交
11428 11429
			pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
					      &tmp);
A
Al Viro 已提交
11430
			v = cpu_to_le32(tmp);
11431
			memcpy(&vpd_data[i], &v, sizeof(v));
M
Michael Chan 已提交
11432
		}
L
Linus Torvalds 已提交
11433 11434 11435
	}

	/* Now parse and find the part number. */
11436
	for (i = 0; i < 254; ) {
L
Linus Torvalds 已提交
11437
		unsigned char val = vpd_data[i];
11438
		unsigned int block_end;
L
Linus Torvalds 已提交
11439 11440 11441 11442 11443 11444 11445 11446 11447 11448 11449 11450 11451 11452 11453

		if (val == 0x82 || val == 0x91) {
			i = (i + 3 +
			     (vpd_data[i + 1] +
			      (vpd_data[i + 2] << 8)));
			continue;
		}

		if (val != 0x90)
			goto out_not_found;

		block_end = (i + 3 +
			     (vpd_data[i + 1] +
			      (vpd_data[i + 2] << 8)));
		i += 3;
11454 11455 11456 11457 11458

		if (block_end > 256)
			goto out_not_found;

		while (i < (block_end - 2)) {
L
Linus Torvalds 已提交
11459 11460 11461 11462
			if (vpd_data[i + 0] == 'P' &&
			    vpd_data[i + 1] == 'N') {
				int partno_len = vpd_data[i + 2];

11463 11464
				i += 3;
				if (partno_len > 24 || (partno_len + i) > 256)
L
Linus Torvalds 已提交
11465 11466 11467
					goto out_not_found;

				memcpy(tp->board_part_number,
11468
				       &vpd_data[i], partno_len);
L
Linus Torvalds 已提交
11469 11470 11471 11472

				/* Success. */
				return;
			}
11473
			i += 3 + vpd_data[i + 2];
L
Linus Torvalds 已提交
11474 11475 11476 11477 11478 11479 11480
		}

		/* Part number not found. */
		goto out_not_found;
	}

out_not_found:
M
Michael Chan 已提交
11481 11482
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
		strcpy(tp->board_part_number, "BCM95906");
M
Matt Carlson 已提交
11483 11484 11485 11486 11487 11488 11489 11490 11491
	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
		 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
		strcpy(tp->board_part_number, "BCM57780");
	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
		 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
		strcpy(tp->board_part_number, "BCM57760");
	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
		 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
		strcpy(tp->board_part_number, "BCM57790");
M
Michael Chan 已提交
11492 11493
	else
		strcpy(tp->board_part_number, "none");
L
Linus Torvalds 已提交
11494 11495
}

11496 11497 11498 11499
static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
{
	u32 val;

11500
	if (tg3_nvram_read(tp, offset, &val) ||
11501
	    (val & 0xfc000000) != 0x0c000000 ||
11502
	    tg3_nvram_read(tp, offset + 4, &val) ||
11503 11504 11505 11506 11507 11508
	    val != 0)
		return 0;

	return 1;
}

11509 11510
static void __devinit tg3_read_bc_ver(struct tg3 *tp)
{
11511
	u32 val, offset, start, ver_offset;
11512
	int i;
11513
	bool newver = false;
11514 11515 11516 11517 11518 11519 11520

	if (tg3_nvram_read(tp, 0xc, &offset) ||
	    tg3_nvram_read(tp, 0x4, &start))
		return;

	offset = tg3_nvram_logical_addr(tp, offset);

11521
	if (tg3_nvram_read(tp, offset, &val))
11522 11523
		return;

11524 11525
	if ((val & 0xfc000000) == 0x0c000000) {
		if (tg3_nvram_read(tp, offset + 4, &val))
11526 11527
			return;

11528 11529 11530 11531 11532 11533 11534 11535 11536 11537 11538 11539 11540 11541 11542 11543 11544 11545 11546 11547 11548 11549 11550 11551 11552 11553
		if (val == 0)
			newver = true;
	}

	if (newver) {
		if (tg3_nvram_read(tp, offset + 8, &ver_offset))
			return;

		offset = offset + ver_offset - start;
		for (i = 0; i < 16; i += 4) {
			__be32 v;
			if (tg3_nvram_read_be32(tp, offset + i, &v))
				return;

			memcpy(tp->fw_ver + i, &v, sizeof(v));
		}
	} else {
		u32 major, minor;

		if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
			return;

		major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
			TG3_NVM_BCVER_MAJSFT;
		minor = ver_offset & TG3_NVM_BCVER_MINMSK;
		snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11554 11555 11556
	}
}

11557 11558 11559 11560 11561 11562 11563 11564 11565 11566 11567 11568 11569 11570 11571 11572
static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
{
	u32 val, major, minor;

	/* Use native endian representation */
	if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
		return;

	major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
		TG3_NVM_HWSB_CFG1_MAJSFT;
	minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
		TG3_NVM_HWSB_CFG1_MINSFT;

	snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
}

11573 11574 11575 11576 11577 11578 11579 11580 11581 11582 11583 11584 11585 11586 11587 11588 11589 11590 11591 11592 11593 11594 11595 11596 11597
static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
{
	u32 offset, major, minor, build;

	tp->fw_ver[0] = 's';
	tp->fw_ver[1] = 'b';
	tp->fw_ver[2] = '\0';

	if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
		return;

	switch (val & TG3_EEPROM_SB_REVISION_MASK) {
	case TG3_EEPROM_SB_REVISION_0:
		offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
		break;
	case TG3_EEPROM_SB_REVISION_2:
		offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
		break;
	case TG3_EEPROM_SB_REVISION_3:
		offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
		break;
	default:
		return;
	}

11598
	if (tg3_nvram_read(tp, offset, &val))
11599 11600 11601 11602 11603 11604 11605 11606 11607 11608 11609 11610 11611 11612 11613 11614 11615 11616 11617
		return;

	build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
		TG3_EEPROM_SB_EDH_BLD_SHFT;
	major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
		TG3_EEPROM_SB_EDH_MAJ_SHFT;
	minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;

	if (minor > 99 || build > 26)
		return;

	snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);

	if (build > 0) {
		tp->fw_ver[8] = 'a' + build - 1;
		tp->fw_ver[9] = '\0';
	}
}

11618
static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
M
Michael Chan 已提交
11619 11620
{
	u32 val, offset, start;
11621
	int i, vlen;
11622 11623 11624 11625

	for (offset = TG3_NVM_DIR_START;
	     offset < TG3_NVM_DIR_END;
	     offset += TG3_NVM_DIRENT_SIZE) {
11626
		if (tg3_nvram_read(tp, offset, &val))
M
Michael Chan 已提交
11627 11628
			return;

11629 11630 11631 11632 11633 11634 11635 11636 11637
		if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
			break;
	}

	if (offset == TG3_NVM_DIR_END)
		return;

	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
		start = 0x08000000;
11638
	else if (tg3_nvram_read(tp, offset - 4, &start))
11639 11640
		return;

11641
	if (tg3_nvram_read(tp, offset + 4, &offset) ||
11642
	    !tg3_fw_img_is_valid(tp, offset) ||
11643
	    tg3_nvram_read(tp, offset + 8, &val))
11644 11645 11646 11647
		return;

	offset += val - start;

11648
	vlen = strlen(tp->fw_ver);
11649

11650 11651
	tp->fw_ver[vlen++] = ',';
	tp->fw_ver[vlen++] = ' ';
11652 11653

	for (i = 0; i < 4; i++) {
11654 11655
		__be32 v;
		if (tg3_nvram_read_be32(tp, offset, &v))
M
Michael Chan 已提交
11656 11657
			return;

A
Al Viro 已提交
11658
		offset += sizeof(v);
M
Michael Chan 已提交
11659

11660 11661
		if (vlen > TG3_VER_SIZE - sizeof(v)) {
			memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
11662
			break;
M
Michael Chan 已提交
11663
		}
11664

11665 11666
		memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
		vlen += sizeof(v);
M
Michael Chan 已提交
11667
	}
11668 11669
}

11670 11671 11672 11673 11674 11675 11676 11677 11678 11679 11680 11681 11682 11683 11684 11685 11686 11687 11688 11689 11690 11691 11692 11693 11694 11695 11696 11697
static void __devinit tg3_read_dash_ver(struct tg3 *tp)
{
	int vlen;
	u32 apedata;

	if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
	    !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
		return;

	apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
	if (apedata != APE_SEG_SIG_MAGIC)
		return;

	apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
	if (!(apedata & APE_FW_STATUS_READY))
		return;

	apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);

	vlen = strlen(tp->fw_ver);

	snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
		 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
		 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
		 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
		 (apedata & APE_FW_VERSION_BLDMSK));
}

11698 11699 11700 11701
static void __devinit tg3_read_fw_ver(struct tg3 *tp)
{
	u32 val;

M
Matt Carlson 已提交
11702 11703 11704 11705 11706 11707 11708 11709
	if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
		tp->fw_ver[0] = 's';
		tp->fw_ver[1] = 'b';
		tp->fw_ver[2] = '\0';

		return;
	}

11710 11711 11712 11713 11714 11715 11716
	if (tg3_nvram_read(tp, 0, &val))
		return;

	if (val == TG3_EEPROM_MAGIC)
		tg3_read_bc_ver(tp);
	else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
		tg3_read_sb_ver(tp, val);
11717 11718
	else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
		tg3_read_hwsb_ver(tp);
11719 11720 11721 11722 11723 11724 11725 11726
	else
		return;

	if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
	     (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
		return;

	tg3_read_mgmtfw_ver(tp);
11727 11728

	tp->fw_ver[TG3_VER_SIZE - 1] = 0;
M
Michael Chan 已提交
11729 11730
}

11731 11732
static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);

L
Linus Torvalds 已提交
11733 11734 11735 11736 11737
static int __devinit tg3_get_invariants(struct tg3 *tp)
{
	static struct pci_device_id write_reorder_chipsets[] = {
		{ PCI_DEVICE(PCI_VENDOR_ID_AMD,
		             PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11738 11739
		{ PCI_DEVICE(PCI_VENDOR_ID_AMD,
		             PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11740 11741
		{ PCI_DEVICE(PCI_VENDOR_ID_VIA,
			     PCI_DEVICE_ID_VIA_8385_0) },
L
Linus Torvalds 已提交
11742 11743 11744 11745 11746 11747
		{ },
	};
	u32 misc_ctrl_reg;
	u32 pci_state_reg, grc_misc_cfg;
	u32 val;
	u16 pci_cmd;
11748
	int err;
L
Linus Torvalds 已提交
11749 11750 11751 11752 11753 11754 11755 11756 11757 11758 11759 11760 11761 11762 11763 11764 11765 11766 11767 11768 11769 11770 11771

	/* Force memory write invalidate off.  If we leave it on,
	 * then on 5700_BX chips we have to enable a workaround.
	 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
	 * to match the cacheline size.  The Broadcom driver have this
	 * workaround but turns MWI off all the times so never uses
	 * it.  This seems to suggest that the workaround is insufficient.
	 */
	pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
	pci_cmd &= ~PCI_COMMAND_INVALIDATE;
	pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);

	/* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
	 * has the register indirect write enable bit set before
	 * we try to access any of the MMIO registers.  It is also
	 * critical that the PCI-X hw workaround situation is decided
	 * before that as well.
	 */
	pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
			      &misc_ctrl_reg);

	tp->pci_chip_rev_id = (misc_ctrl_reg >>
			       MISC_HOST_CTRL_CHIPREV_SHIFT);
11772 11773 11774 11775 11776
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
		u32 prod_id_asic_rev;

		pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
				      &prod_id_asic_rev);
M
Matt Carlson 已提交
11777
		tp->pci_chip_rev_id = prod_id_asic_rev;
11778
	}
L
Linus Torvalds 已提交
11779

M
Michael Chan 已提交
11780 11781 11782 11783 11784 11785
	/* Wrong chip ID in 5752 A0. This code can be removed later
	 * as A0 is not in production.
	 */
	if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
		tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;

11786 11787 11788 11789 11790 11791 11792 11793 11794 11795 11796 11797 11798 11799 11800 11801 11802 11803 11804 11805 11806 11807 11808 11809 11810 11811 11812 11813 11814 11815 11816 11817 11818 11819 11820 11821 11822 11823 11824 11825 11826 11827 11828 11829 11830
	/* If we have 5702/03 A1 or A2 on certain ICH chipsets,
	 * we need to disable memory and use config. cycles
	 * only to access all registers. The 5702/03 chips
	 * can mistakenly decode the special cycles from the
	 * ICH chipsets as memory write cycles, causing corruption
	 * of register and memory space. Only certain ICH bridges
	 * will drive special cycles with non-zero data during the
	 * address phase which can fall within the 5703's address
	 * range. This is not an ICH bug as the PCI spec allows
	 * non-zero address during special cycles. However, only
	 * these ICH bridges are known to drive non-zero addresses
	 * during special cycles.
	 *
	 * Since special cycles do not cross PCI bridges, we only
	 * enable this workaround if the 5703 is on the secondary
	 * bus of these ICH bridges.
	 */
	if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
	    (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
		static struct tg3_dev_id {
			u32	vendor;
			u32	device;
			u32	rev;
		} ich_chipsets[] = {
			{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
			  PCI_ANY_ID },
			{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
			  PCI_ANY_ID },
			{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
			  0xa },
			{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
			  PCI_ANY_ID },
			{ },
		};
		struct tg3_dev_id *pci_id = &ich_chipsets[0];
		struct pci_dev *bridge = NULL;

		while (pci_id->vendor != 0) {
			bridge = pci_get_device(pci_id->vendor, pci_id->device,
						bridge);
			if (!bridge) {
				pci_id++;
				continue;
			}
			if (pci_id->rev != PCI_ANY_ID) {
11831
				if (bridge->revision > pci_id->rev)
11832 11833 11834 11835 11836 11837 11838 11839 11840 11841 11842 11843 11844
					continue;
			}
			if (bridge->subordinate &&
			    (bridge->subordinate->number ==
			     tp->pdev->bus->number)) {

				tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
				pci_dev_put(bridge);
				break;
			}
		}
	}

M
Matt Carlson 已提交
11845 11846 11847 11848 11849 11850 11851 11852 11853 11854 11855 11856 11857 11858 11859 11860 11861 11862 11863 11864 11865 11866 11867 11868 11869 11870 11871 11872 11873 11874 11875 11876
	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
		static struct tg3_dev_id {
			u32	vendor;
			u32	device;
		} bridge_chipsets[] = {
			{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
			{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
			{ },
		};
		struct tg3_dev_id *pci_id = &bridge_chipsets[0];
		struct pci_dev *bridge = NULL;

		while (pci_id->vendor != 0) {
			bridge = pci_get_device(pci_id->vendor,
						pci_id->device,
						bridge);
			if (!bridge) {
				pci_id++;
				continue;
			}
			if (bridge->subordinate &&
			    (bridge->subordinate->number <=
			     tp->pdev->bus->number) &&
			    (bridge->subordinate->subordinate >=
			     tp->pdev->bus->number)) {
				tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
				pci_dev_put(bridge);
				break;
			}
		}
	}

11877 11878 11879 11880 11881 11882
	/* The EPB bridge inside 5714, 5715, and 5780 cannot support
	 * DMA addresses > 40-bit. This bridge may have other additional
	 * 57xx devices behind it in some 4-port NIC designs for example.
	 * Any tg3 device found behind the bridge will also need the 40-bit
	 * DMA workaround.
	 */
M
Michael Chan 已提交
11883 11884 11885
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
		tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11886
		tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
M
Michael Chan 已提交
11887
		tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
M
Michael Chan 已提交
11888
	}
11889 11890 11891 11892 11893 11894 11895 11896 11897 11898 11899 11900 11901 11902 11903 11904 11905 11906
	else {
		struct pci_dev *bridge = NULL;

		do {
			bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
						PCI_DEVICE_ID_SERVERWORKS_EPB,
						bridge);
			if (bridge && bridge->subordinate &&
			    (bridge->subordinate->number <=
			     tp->pdev->bus->number) &&
			    (bridge->subordinate->subordinate >=
			     tp->pdev->bus->number)) {
				tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
				pci_dev_put(bridge);
				break;
			}
		} while (bridge);
	}
M
Michael Chan 已提交
11907

L
Linus Torvalds 已提交
11908 11909 11910 11911 11912 11913
	/* Initialize misc host control in PCI block. */
	tp->misc_host_ctrl |= (misc_ctrl_reg &
			       MISC_HOST_CTRL_CHIPREV);
	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
			       tp->misc_host_ctrl);

11914 11915 11916 11917
	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
		tp->pdev_peer = tg3_find_peer(tp);

M
Matt Carlson 已提交
11918 11919
	/* Intentionally exclude ASIC_REV_5906 */
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11920
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
M
Matt Carlson 已提交
11921
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
M
Matt Carlson 已提交
11922
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
M
Matt Carlson 已提交
11923
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
M
Matt Carlson 已提交
11924 11925 11926 11927 11928
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
		tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
M
Michael Chan 已提交
11929
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
M
Matt Carlson 已提交
11930
	    (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
M
Michael Chan 已提交
11931
	    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11932 11933
		tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;

11934 11935 11936 11937
	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
	    (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
		tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;

M
Matt Carlson 已提交
11938 11939 11940 11941 11942 11943 11944 11945 11946 11947 11948 11949
	/* 5700 B0 chips do not support checksumming correctly due
	 * to hardware bugs.
	 */
	if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
		tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
	else {
		tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
		tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
		if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
			tp->dev->features |= NETIF_F_IPV6_CSUM;
	}

M
Michael Chan 已提交
11950
	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11951 11952 11953 11954 11955 11956 11957 11958
		tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
		if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
		    GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
		    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
		     tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
		     tp->pdev_peer == tp->pdev))
			tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;

M
Matt Carlson 已提交
11959
		if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
M
Michael Chan 已提交
11960
		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
M
Michael Chan 已提交
11961
			tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11962
			tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
11963
		} else {
M
Michael Chan 已提交
11964
			tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
11965 11966 11967
			if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
				ASIC_REV_5750 &&
	     		    tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
M
Michael Chan 已提交
11968
				tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
11969
		}
M
Michael Chan 已提交
11970
	}
L
Linus Torvalds 已提交
11971

M
Matt Carlson 已提交
11972 11973
	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
	     (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11974 11975
		tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;

M
Matt Carlson 已提交
11976 11977 11978
	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
			      &pci_state_reg);

11979 11980 11981 11982
	tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
	if (tp->pcie_cap != 0) {
		u16 lnkctl;

L
Linus Torvalds 已提交
11983
		tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
M
Matt Carlson 已提交
11984 11985 11986

		pcie_set_readrq(tp->pdev, 4096);

11987 11988 11989 11990 11991
		pci_read_config_word(tp->pdev,
				     tp->pcie_cap + PCI_EXP_LNKCTL,
				     &lnkctl);
		if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11992
				tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11993
			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
M
Matt Carlson 已提交
11994 11995
			    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
			    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11996
				tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
11997
		}
M
Matt Carlson 已提交
11998
	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
M
Matt Carlson 已提交
11999
		tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
M
Matt Carlson 已提交
12000 12001 12002 12003 12004 12005 12006 12007 12008 12009 12010 12011
	} else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
		   (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
		tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
		if (!tp->pcix_cap) {
			printk(KERN_ERR PFX "Cannot find PCI-X "
					    "capability, aborting.\n");
			return -EIO;
		}

		if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
			tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
	}
L
Linus Torvalds 已提交
12012

12013 12014 12015 12016 12017 12018 12019 12020 12021 12022
	/* If we have an AMD 762 or VIA K8T800 chipset, write
	 * reordering to the mailbox registers done by the host
	 * controller can cause major troubles.  We read back from
	 * every mailbox register write to force the writes to be
	 * posted to the chip in order.
	 */
	if (pci_dev_present(write_reorder_chipsets) &&
	    !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
		tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;

12023 12024 12025 12026
	pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
			     &tp->pci_cacheline_sz);
	pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
			     &tp->pci_lat_timer);
L
Linus Torvalds 已提交
12027 12028 12029
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
	    tp->pci_lat_timer < 64) {
		tp->pci_lat_timer = 64;
12030 12031
		pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
				      tp->pci_lat_timer);
L
Linus Torvalds 已提交
12032 12033
	}

M
Matt Carlson 已提交
12034 12035 12036 12037 12038
	if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
		/* 5700 BX chips need to have their TX producer index
		 * mailboxes written twice to workaround a bug.
		 */
		tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
L
Linus Torvalds 已提交
12039

M
Matt Carlson 已提交
12040
		/* If we are in PCI-X mode, enable register write workaround.
L
Linus Torvalds 已提交
12041 12042 12043 12044
		 *
		 * The workaround is to use indirect register accesses
		 * for all chip writes not to mailbox registers.
		 */
M
Matt Carlson 已提交
12045
		if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
L
Linus Torvalds 已提交
12046 12047 12048 12049 12050 12051 12052 12053
			u32 pm_reg;

			tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;

			/* The chip can have it's power management PCI config
			 * space registers clobbered due to this bug.
			 * So explicitly force the chip into D0 here.
			 */
M
Matt Carlson 已提交
12054 12055
			pci_read_config_dword(tp->pdev,
					      tp->pm_cap + PCI_PM_CTRL,
L
Linus Torvalds 已提交
12056 12057 12058
					      &pm_reg);
			pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
			pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
M
Matt Carlson 已提交
12059 12060
			pci_write_config_dword(tp->pdev,
					       tp->pm_cap + PCI_PM_CTRL,
L
Linus Torvalds 已提交
12061 12062 12063 12064 12065 12066 12067 12068 12069 12070 12071 12072 12073 12074 12075 12076 12077 12078 12079 12080 12081
					       pm_reg);

			/* Also, force SERR#/PERR# in PCI command. */
			pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
			pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
			pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
		}
	}

	if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
		tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
	if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
		tp->tg3_flags |= TG3_FLAG_PCI_32BIT;

	/* Chip-specific fixup from Broadcom driver */
	if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
	    (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
		pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
		pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
	}

12082
	/* Default fast path register access methods */
12083
	tp->read32 = tg3_read32;
12084
	tp->write32 = tg3_write32;
M
Michael Chan 已提交
12085
	tp->read32_mbox = tg3_read32;
12086
	tp->write32_mbox = tg3_write32;
12087 12088 12089 12090 12091 12092
	tp->write32_tx_mbox = tg3_write32;
	tp->write32_rx_mbox = tg3_write32;

	/* Various workaround register access methods */
	if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
		tp->write32 = tg3_write_indirect_reg32;
12093 12094 12095 12096 12097 12098 12099 12100 12101 12102
	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
		 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
		  tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
		/*
		 * Back to back register writes can cause problems on these
		 * chips, the workaround is to read back all reg writes
		 * except those to mailbox regs.
		 *
		 * See tg3_write_indirect_reg32().
		 */
12103
		tp->write32 = tg3_write_flush_reg32;
12104 12105
	}

12106 12107 12108 12109 12110 12111 12112

	if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
	    (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
		tp->write32_tx_mbox = tg3_write32_tx_mbox;
		if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
			tp->write32_rx_mbox = tg3_write_flush_reg32;
	}
12113

12114 12115 12116 12117 12118 12119 12120 12121 12122
	if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
		tp->read32 = tg3_read_indirect_reg32;
		tp->write32 = tg3_write_indirect_reg32;
		tp->read32_mbox = tg3_read_indirect_mbox;
		tp->write32_mbox = tg3_write_indirect_mbox;
		tp->write32_tx_mbox = tg3_write_indirect_mbox;
		tp->write32_rx_mbox = tg3_write_indirect_mbox;

		iounmap(tp->regs);
P
Peter Hagervall 已提交
12123
		tp->regs = NULL;
12124 12125 12126 12127 12128

		pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
		pci_cmd &= ~PCI_COMMAND_MEMORY;
		pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
	}
M
Michael Chan 已提交
12129 12130 12131 12132 12133 12134
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
		tp->read32_mbox = tg3_read32_mbox_5906;
		tp->write32_mbox = tg3_write32_mbox_5906;
		tp->write32_tx_mbox = tg3_write32_mbox_5906;
		tp->write32_rx_mbox = tg3_write32_mbox_5906;
	}
12135

12136 12137 12138
	if (tp->write32 == tg3_write_indirect_reg32 ||
	    ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
	     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12139
	      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12140 12141
		tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;

12142
	/* Get eeprom hw config before calling tg3_set_power_state().
M
Michael Chan 已提交
12143
	 * In particular, the TG3_FLG2_IS_NIC flag must be
12144 12145 12146 12147 12148
	 * determined before calling tg3_set_power_state() so that
	 * we know whether or not to switch out of Vaux power.
	 * When the flag is set, it means that GPIO1 is used for eeprom
	 * write protect and also implies that it is a LOM where GPIOs
	 * are not used to switch power.
12149
	 */
12150 12151
	tg3_get_eeprom_hw_cfg(tp);

M
Matt Carlson 已提交
12152 12153 12154 12155 12156 12157 12158 12159 12160 12161
	if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
		/* Allow reads and writes to the
		 * APE register and memory space.
		 */
		pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
				 PCISTATE_ALLOW_APE_SHMEM_WR;
		pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
				       pci_state_reg);
	}

M
Matt Carlson 已提交
12162
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
M
Matt Carlson 已提交
12163
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
M
Matt Carlson 已提交
12164 12165
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
M
Matt Carlson 已提交
12166 12167
		tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;

M
Michael Chan 已提交
12168 12169 12170 12171 12172 12173 12174 12175 12176
	/* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
	 * GPIO1 driven high will bring 5700's external PHY out of reset.
	 * It is also used as eeprom write protect on LOMs.
	 */
	tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
	    (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
		tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
				       GRC_LCLCTRL_GPIO_OUTPUT1);
M
Michael Chan 已提交
12177 12178 12179 12180 12181
	/* Unused GPIO3 must be driven as output on 5752 because there
	 * are no pull-up resistors on unused GPIO pins.
	 */
	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
M
Michael Chan 已提交
12182

M
Matt Carlson 已提交
12183 12184
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
M
Michael Chan 已提交
12185 12186
		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;

12187 12188
	if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
M
Matt Carlson 已提交
12189 12190 12191 12192 12193 12194 12195 12196
		/* Turn off the debug UART. */
		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
		if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
			/* Keep VMain power. */
			tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
					      GRC_LCLCTRL_GPIO_OUTPUT0;
	}

L
Linus Torvalds 已提交
12197
	/* Force the chip into D0. */
M
Michael Chan 已提交
12198
	err = tg3_set_power_state(tp, PCI_D0);
L
Linus Torvalds 已提交
12199 12200 12201 12202 12203 12204 12205 12206 12207
	if (err) {
		printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
		       pci_name(tp->pdev));
		return err;
	}

	/* Derive initial jumbo mode from MTU assigned in
	 * ether_setup() via the alloc_etherdev() call
	 */
12208
	if (tp->dev->mtu > ETH_DATA_LEN &&
M
Michael Chan 已提交
12209
	    !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12210
		tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
L
Linus Torvalds 已提交
12211 12212 12213 12214 12215 12216 12217 12218 12219 12220 12221 12222 12223 12224 12225

	/* Determine WakeOnLan speed to use. */
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
	    tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
	    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
	    tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
		tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
	} else {
		tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
	}

	/* A few boards don't want Ethernet@WireSpeed phy feature */
	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
	    ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
	     (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
M
Michael Chan 已提交
12226
	     (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
M
Michael Chan 已提交
12227
	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
M
Michael Chan 已提交
12228
	    (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
L
Linus Torvalds 已提交
12229 12230 12231 12232 12233 12234 12235 12236
		tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;

	if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
	    GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
		tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
		tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;

M
Matt Carlson 已提交
12237 12238 12239 12240
	if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
M
Michael Chan 已提交
12241
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
M
Matt Carlson 已提交
12242
		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
M
Matt Carlson 已提交
12243 12244
		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12245 12246 12247
			if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
			    tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
				tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12248 12249
			if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
				tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
M
Matt Carlson 已提交
12250
		} else
M
Michael Chan 已提交
12251 12252
			tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
	}
L
Linus Torvalds 已提交
12253

12254 12255 12256 12257 12258 12259 12260
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
	    GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
		tp->phy_otp = tg3_read_otp_phycfg(tp);
		if (tp->phy_otp == 0)
			tp->phy_otp = TG3_OTP_DEFAULT;
	}

M
Matt Carlson 已提交
12261
	if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12262 12263 12264 12265
		tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
	else
		tp->mi_mode = MAC_MI_MODE_BASE;

L
Linus Torvalds 已提交
12266 12267 12268 12269 12270
	tp->coalesce_mode = 0;
	if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
	    GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
		tp->coalesce_mode |= HOSTCC_MODE_32BYTE;

M
Matt Carlson 已提交
12271 12272
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
M
Matt Carlson 已提交
12273 12274
		tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;

M
Matt Carlson 已提交
12275 12276 12277
	err = tg3_mdio_init(tp);
	if (err)
		return err;
L
Linus Torvalds 已提交
12278 12279 12280 12281 12282 12283 12284 12285 12286 12287 12288 12289 12290 12291 12292 12293 12294 12295 12296 12297 12298 12299 12300 12301 12302 12303 12304 12305 12306 12307 12308 12309 12310 12311 12312 12313 12314 12315 12316 12317 12318 12319 12320 12321 12322 12323 12324 12325

	/* Initialize data/descriptor byte/word swapping. */
	val = tr32(GRC_MODE);
	val &= GRC_MODE_HOST_STACKUP;
	tw32(GRC_MODE, val | tp->grc_mode);

	tg3_switch_clocks(tp);

	/* Clear this out for sanity. */
	tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);

	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
			      &pci_state_reg);
	if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
	    (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
		u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);

		if (chiprevid == CHIPREV_ID_5701_A0 ||
		    chiprevid == CHIPREV_ID_5701_B0 ||
		    chiprevid == CHIPREV_ID_5701_B2 ||
		    chiprevid == CHIPREV_ID_5701_B5) {
			void __iomem *sram_base;

			/* Write some dummy words into the SRAM status block
			 * area, see if it reads back correctly.  If the return
			 * value is bad, force enable the PCIX workaround.
			 */
			sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;

			writel(0x00000000, sram_base);
			writel(0x00000000, sram_base + 4);
			writel(0xffffffff, sram_base + 4);
			if (readl(sram_base) != 0x00000000)
				tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
		}
	}

	udelay(50);
	tg3_nvram_init(tp);

	grc_misc_cfg = tr32(GRC_MISC_CFG);
	grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
	    (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
	     grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
		tp->tg3_flags2 |= TG3_FLG2_IS_5788;

12326 12327 12328 12329 12330 12331 12332 12333 12334 12335 12336 12337
	if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
	    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
		tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
	if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
		tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
				      HOSTCC_MODE_CLRTICK_TXBD);

		tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
		pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
				       tp->misc_host_ctrl);
	}

12338 12339 12340 12341 12342 12343 12344
	/* Preserve the APE MAC_MODE bits */
	if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
		tp->mac_mode = tr32(MAC_MODE) |
			       MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
	else
		tp->mac_mode = TG3_DEF_MAC_MODE;

L
Linus Torvalds 已提交
12345 12346 12347 12348 12349 12350 12351 12352 12353 12354
	/* these are limited to 10/100 only */
	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
	     (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
	     tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
	     (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
	      tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
	      tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
	    (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
	     (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
M
Michael Chan 已提交
12355 12356
	      tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
	      tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
M
Matt Carlson 已提交
12357
	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
M
Michael Chan 已提交
12358
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
L
Linus Torvalds 已提交
12359 12360 12361 12362 12363 12364 12365
		tp->tg3_flags |= TG3_FLAG_10_100_ONLY;

	err = tg3_phy_probe(tp);
	if (err) {
		printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
		       pci_name(tp->pdev), err);
		/* ... but do not return immediately ... */
M
Matt Carlson 已提交
12366
		tg3_mdio_fini(tp);
L
Linus Torvalds 已提交
12367 12368 12369
	}

	tg3_read_partno(tp);
M
Michael Chan 已提交
12370
	tg3_read_fw_ver(tp);
L
Linus Torvalds 已提交
12371 12372 12373 12374 12375 12376 12377 12378 12379 12380 12381 12382 12383 12384 12385 12386 12387 12388 12389 12390 12391 12392 12393 12394

	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
		tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
	} else {
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
			tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
		else
			tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
	}

	/* 5700 {AX,BX} chips have a broken status block link
	 * change bit implementation, so we must use the
	 * status register in those cases.
	 */
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
		tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
	else
		tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;

	/* The led_ctrl is set during tg3_phy_probe, here we might
	 * have to force the link status polling mechanism based
	 * upon subsystem IDs.
	 */
	if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12395
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
L
Linus Torvalds 已提交
12396 12397 12398 12399 12400 12401 12402 12403 12404 12405 12406
	    !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
		tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
				  TG3_FLAG_USE_LINKCHG_REG);
	}

	/* For all SERDES we poll the MAC status register. */
	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
		tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
	else
		tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;

M
Matt Carlson 已提交
12407
	tp->rx_offset = NET_IP_ALIGN;
L
Linus Torvalds 已提交
12408 12409 12410 12411
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
		tp->rx_offset = 0;

M
Michael Chan 已提交
12412 12413 12414 12415 12416 12417 12418 12419 12420 12421
	tp->rx_std_max_post = TG3_RX_RING_SIZE;

	/* Increment the rx prod index on the rx std ring by at most
	 * 8 for these chips to workaround hw errata.
	 */
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
		tp->rx_std_max_post = 8;

M
Matt Carlson 已提交
12422 12423 12424 12425
	if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
		tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
				     PCIE_PWR_MGMT_L1_THRESH_MSK;

L
Linus Torvalds 已提交
12426 12427 12428
	return err;
}

12429
#ifdef CONFIG_SPARC
L
Linus Torvalds 已提交
12430 12431 12432 12433
static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
{
	struct net_device *dev = tp->dev;
	struct pci_dev *pdev = tp->pdev;
12434
	struct device_node *dp = pci_device_to_OF_node(pdev);
12435
	const unsigned char *addr;
12436 12437 12438 12439 12440 12441 12442
	int len;

	addr = of_get_property(dp, "local-mac-address", &len);
	if (addr && len == 6) {
		memcpy(dev->dev_addr, addr, 6);
		memcpy(dev->perm_addr, dev->dev_addr, 6);
		return 0;
L
Linus Torvalds 已提交
12443 12444 12445 12446 12447 12448 12449 12450 12451
	}
	return -ENODEV;
}

static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
{
	struct net_device *dev = tp->dev;

	memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12452
	memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
L
Linus Torvalds 已提交
12453 12454 12455 12456 12457 12458 12459 12460
	return 0;
}
#endif

static int __devinit tg3_get_device_address(struct tg3 *tp)
{
	struct net_device *dev = tp->dev;
	u32 hi, lo, mac_offset;
12461
	int addr_ok = 0;
L
Linus Torvalds 已提交
12462

12463
#ifdef CONFIG_SPARC
L
Linus Torvalds 已提交
12464 12465 12466 12467 12468
	if (!tg3_get_macaddr_sparc(tp))
		return 0;
#endif

	mac_offset = 0x7c;
12469
	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
M
Michael Chan 已提交
12470
	    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
L
Linus Torvalds 已提交
12471 12472 12473 12474 12475 12476 12477
		if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
			mac_offset = 0xcc;
		if (tg3_nvram_lock(tp))
			tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
		else
			tg3_nvram_unlock(tp);
	}
M
Michael Chan 已提交
12478 12479
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
		mac_offset = 0x10;
L
Linus Torvalds 已提交
12480 12481 12482 12483 12484 12485 12486 12487 12488 12489 12490 12491 12492

	/* First try to get it from MAC address mailbox. */
	tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
	if ((hi >> 16) == 0x484b) {
		dev->dev_addr[0] = (hi >>  8) & 0xff;
		dev->dev_addr[1] = (hi >>  0) & 0xff;

		tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
		dev->dev_addr[2] = (lo >> 24) & 0xff;
		dev->dev_addr[3] = (lo >> 16) & 0xff;
		dev->dev_addr[4] = (lo >>  8) & 0xff;
		dev->dev_addr[5] = (lo >>  0) & 0xff;

12493 12494 12495 12496 12497
		/* Some old bootcode may report a 0 MAC address in SRAM */
		addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
	}
	if (!addr_ok) {
		/* Next, try NVRAM. */
M
Matt Carlson 已提交
12498 12499
		if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
		    !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12500
		    !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
M
Matt Carlson 已提交
12501 12502
			memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
			memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12503 12504 12505 12506 12507 12508 12509 12510 12511 12512 12513 12514 12515
		}
		/* Finally just fetch it out of the MAC control regs. */
		else {
			hi = tr32(MAC_ADDR_0_HIGH);
			lo = tr32(MAC_ADDR_0_LOW);

			dev->dev_addr[5] = lo & 0xff;
			dev->dev_addr[4] = (lo >> 8) & 0xff;
			dev->dev_addr[3] = (lo >> 16) & 0xff;
			dev->dev_addr[2] = (lo >> 24) & 0xff;
			dev->dev_addr[1] = hi & 0xff;
			dev->dev_addr[0] = (hi >> 8) & 0xff;
		}
L
Linus Torvalds 已提交
12516 12517 12518
	}

	if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12519
#ifdef CONFIG_SPARC
L
Linus Torvalds 已提交
12520 12521 12522 12523 12524
		if (!tg3_get_default_macaddr_sparc(tp))
			return 0;
#endif
		return -EINVAL;
	}
12525
	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
L
Linus Torvalds 已提交
12526 12527 12528
	return 0;
}

12529 12530 12531 12532 12533 12534 12535 12536 12537 12538 12539 12540 12541 12542 12543 12544 12545 12546 12547 12548 12549 12550 12551 12552 12553 12554 12555 12556 12557 12558 12559 12560 12561 12562 12563 12564 12565 12566 12567 12568 12569 12570 12571 12572 12573 12574 12575 12576 12577 12578 12579 12580 12581 12582 12583 12584 12585 12586 12587 12588 12589 12590 12591 12592 12593 12594 12595 12596 12597 12598 12599 12600
#define BOUNDARY_SINGLE_CACHELINE	1
#define BOUNDARY_MULTI_CACHELINE	2

static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
{
	int cacheline_size;
	u8 byte;
	int goal;

	pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
	if (byte == 0)
		cacheline_size = 1024;
	else
		cacheline_size = (int) byte * 4;

	/* On 5703 and later chips, the boundary bits have no
	 * effect.
	 */
	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
	    !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
		goto out;

#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
	goal = BOUNDARY_MULTI_CACHELINE;
#else
#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
	goal = BOUNDARY_SINGLE_CACHELINE;
#else
	goal = 0;
#endif
#endif

	if (!goal)
		goto out;

	/* PCI controllers on most RISC systems tend to disconnect
	 * when a device tries to burst across a cache-line boundary.
	 * Therefore, letting tg3 do so just wastes PCI bandwidth.
	 *
	 * Unfortunately, for PCI-E there are only limited
	 * write-side controls for this, and thus for reads
	 * we will still get the disconnects.  We'll also waste
	 * these PCI cycles for both read and write for chips
	 * other than 5700 and 5701 which do not implement the
	 * boundary bits.
	 */
	if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
	    !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
		switch (cacheline_size) {
		case 16:
		case 32:
		case 64:
		case 128:
			if (goal == BOUNDARY_SINGLE_CACHELINE) {
				val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
					DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
			} else {
				val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
					DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
			}
			break;

		case 256:
			val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
				DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
			break;

		default:
			val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
				DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
			break;
12601
		}
12602 12603 12604 12605 12606 12607 12608 12609 12610 12611 12612 12613 12614 12615 12616 12617
	} else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
		switch (cacheline_size) {
		case 16:
		case 32:
		case 64:
			if (goal == BOUNDARY_SINGLE_CACHELINE) {
				val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
				val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
				break;
			}
			/* fallthrough */
		case 128:
		default:
			val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
			val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
			break;
12618
		}
12619 12620 12621 12622 12623 12624 12625 12626 12627 12628 12629 12630 12631 12632 12633 12634 12635 12636 12637 12638 12639 12640 12641 12642 12643 12644 12645 12646 12647 12648 12649 12650 12651 12652 12653 12654 12655 12656 12657 12658 12659 12660 12661
	} else {
		switch (cacheline_size) {
		case 16:
			if (goal == BOUNDARY_SINGLE_CACHELINE) {
				val |= (DMA_RWCTRL_READ_BNDRY_16 |
					DMA_RWCTRL_WRITE_BNDRY_16);
				break;
			}
			/* fallthrough */
		case 32:
			if (goal == BOUNDARY_SINGLE_CACHELINE) {
				val |= (DMA_RWCTRL_READ_BNDRY_32 |
					DMA_RWCTRL_WRITE_BNDRY_32);
				break;
			}
			/* fallthrough */
		case 64:
			if (goal == BOUNDARY_SINGLE_CACHELINE) {
				val |= (DMA_RWCTRL_READ_BNDRY_64 |
					DMA_RWCTRL_WRITE_BNDRY_64);
				break;
			}
			/* fallthrough */
		case 128:
			if (goal == BOUNDARY_SINGLE_CACHELINE) {
				val |= (DMA_RWCTRL_READ_BNDRY_128 |
					DMA_RWCTRL_WRITE_BNDRY_128);
				break;
			}
			/* fallthrough */
		case 256:
			val |= (DMA_RWCTRL_READ_BNDRY_256 |
				DMA_RWCTRL_WRITE_BNDRY_256);
			break;
		case 512:
			val |= (DMA_RWCTRL_READ_BNDRY_512 |
				DMA_RWCTRL_WRITE_BNDRY_512);
			break;
		case 1024:
		default:
			val |= (DMA_RWCTRL_READ_BNDRY_1024 |
				DMA_RWCTRL_WRITE_BNDRY_1024);
			break;
12662
		}
12663 12664 12665 12666 12667 12668
	}

out:
	return val;
}

L
Linus Torvalds 已提交
12669 12670 12671 12672 12673 12674 12675 12676 12677 12678 12679 12680 12681 12682 12683 12684 12685 12686 12687 12688 12689 12690 12691 12692 12693 12694 12695 12696 12697 12698 12699 12700 12701 12702 12703 12704 12705 12706 12707 12708 12709 12710 12711 12712 12713 12714 12715 12716 12717 12718 12719 12720 12721 12722 12723 12724 12725 12726 12727 12728 12729 12730 12731 12732 12733 12734 12735 12736 12737 12738 12739 12740 12741 12742 12743 12744 12745 12746 12747 12748 12749
static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
{
	struct tg3_internal_buffer_desc test_desc;
	u32 sram_dma_descs;
	int i, ret;

	sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;

	tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
	tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
	tw32(RDMAC_STATUS, 0);
	tw32(WDMAC_STATUS, 0);

	tw32(BUFMGR_MODE, 0);
	tw32(FTQ_RESET, 0);

	test_desc.addr_hi = ((u64) buf_dma) >> 32;
	test_desc.addr_lo = buf_dma & 0xffffffff;
	test_desc.nic_mbuf = 0x00002100;
	test_desc.len = size;

	/*
	 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
	 * the *second* time the tg3 driver was getting loaded after an
	 * initial scan.
	 *
	 * Broadcom tells me:
	 *   ...the DMA engine is connected to the GRC block and a DMA
	 *   reset may affect the GRC block in some unpredictable way...
	 *   The behavior of resets to individual blocks has not been tested.
	 *
	 * Broadcom noted the GRC reset will also reset all sub-components.
	 */
	if (to_device) {
		test_desc.cqid_sqid = (13 << 8) | 2;

		tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
		udelay(40);
	} else {
		test_desc.cqid_sqid = (16 << 8) | 7;

		tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
		udelay(40);
	}
	test_desc.flags = 0x00000005;

	for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
		u32 val;

		val = *(((u32 *)&test_desc) + i);
		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
				       sram_dma_descs + (i * sizeof(u32)));
		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
	}
	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);

	if (to_device) {
		tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
	} else {
		tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
	}

	ret = -ENODEV;
	for (i = 0; i < 40; i++) {
		u32 val;

		if (to_device)
			val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
		else
			val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
		if ((val & 0xffff) == sram_dma_descs) {
			ret = 0;
			break;
		}

		udelay(100);
	}

	return ret;
}

12750
#define TEST_BUFFER_SIZE	0x2000
L
Linus Torvalds 已提交
12751 12752 12753 12754

static int __devinit tg3_test_dma(struct tg3 *tp)
{
	dma_addr_t buf_dma;
12755
	u32 *buf, saved_dma_rwctrl;
L
Linus Torvalds 已提交
12756 12757 12758 12759 12760 12761 12762 12763 12764 12765 12766
	int ret;

	buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
	if (!buf) {
		ret = -ENOMEM;
		goto out_nofree;
	}

	tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
			  (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));

12767
	tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
L
Linus Torvalds 已提交
12768 12769 12770 12771 12772

	if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
		/* DMA read watermark not used on PCIE */
		tp->dma_rwctrl |= 0x00180000;
	} else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
M
Michael Chan 已提交
12773 12774
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
L
Linus Torvalds 已提交
12775 12776 12777 12778 12779 12780 12781
			tp->dma_rwctrl |= 0x003f0000;
		else
			tp->dma_rwctrl |= 0x003f000f;
	} else {
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
			u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12782
			u32 read_water = 0x7;
L
Linus Torvalds 已提交
12783

12784 12785 12786 12787 12788 12789 12790 12791
			/* If the 5704 is behind the EPB bridge, we can
			 * do the less restrictive ONE_DMA workaround for
			 * better performance.
			 */
			if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
			    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
				tp->dma_rwctrl |= 0x8000;
			else if (ccval == 0x6 || ccval == 0x7)
L
Linus Torvalds 已提交
12792 12793
				tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;

12794 12795
			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
				read_water = 4;
12796
			/* Set bit 23 to enable PCIX hw bug fix */
12797 12798 12799 12800
			tp->dma_rwctrl |=
				(read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
				(0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
				(1 << 23);
M
Michael Chan 已提交
12801 12802 12803
		} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
			/* 5780 always in PCIX mode */
			tp->dma_rwctrl |= 0x00144000;
M
Michael Chan 已提交
12804 12805 12806
		} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
			/* 5714 always in PCIX mode */
			tp->dma_rwctrl |= 0x00148000;
L
Linus Torvalds 已提交
12807 12808 12809 12810 12811 12812 12813 12814 12815 12816 12817 12818 12819 12820 12821 12822 12823 12824 12825 12826 12827 12828 12829 12830 12831 12832 12833 12834 12835 12836 12837 12838 12839 12840 12841 12842 12843 12844 12845
		} else {
			tp->dma_rwctrl |= 0x001b000f;
		}
	}

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
		tp->dma_rwctrl &= 0xfffffff0;

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
		/* Remove this if it causes problems for some boards. */
		tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;

		/* On 5700/5701 chips, we need to set this bit.
		 * Otherwise the chip will issue cacheline transactions
		 * to streamable DMA memory with not all the byte
		 * enables turned on.  This is an error on several
		 * RISC PCI controllers, in particular sparc64.
		 *
		 * On 5703/5704 chips, this bit has been reassigned
		 * a different meaning.  In particular, it is used
		 * on those chips to enable a PCI-X workaround.
		 */
		tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
	}

	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);

#if 0
	/* Unneeded, already done by tg3_get_invariants.  */
	tg3_switch_clocks(tp);
#endif

	ret = 0;
	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
		goto out;

12846 12847 12848 12849 12850 12851 12852
	/* It is best to perform DMA test with maximum write burst size
	 * to expose the 5700/5701 write DMA bug.
	 */
	saved_dma_rwctrl = tp->dma_rwctrl;
	tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);

L
Linus Torvalds 已提交
12853 12854 12855 12856 12857 12858 12859 12860 12861 12862 12863 12864 12865 12866 12867 12868 12869 12870 12871 12872 12873 12874 12875 12876 12877 12878 12879 12880 12881 12882 12883 12884 12885 12886 12887 12888 12889 12890
	while (1) {
		u32 *p = buf, i;

		for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
			p[i] = i;

		/* Send the buffer to the chip. */
		ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
		if (ret) {
			printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
			break;
		}

#if 0
		/* validate data reached card RAM correctly. */
		for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
			u32 val;
			tg3_read_mem(tp, 0x2100 + (i*4), &val);
			if (le32_to_cpu(val) != p[i]) {
				printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
				/* ret = -ENODEV here? */
			}
			p[i] = 0;
		}
#endif
		/* Now read it back. */
		ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
		if (ret) {
			printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);

			break;
		}

		/* Verify it. */
		for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
			if (p[i] == i)
				continue;

12891 12892 12893
			if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
			    DMA_RWCTRL_WRITE_BNDRY_16) {
				tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
L
Linus Torvalds 已提交
12894 12895 12896 12897 12898 12899 12900 12901 12902 12903 12904 12905 12906 12907 12908 12909
				tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
				tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
				break;
			} else {
				printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
				ret = -ENODEV;
				goto out;
			}
		}

		if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
			/* Success. */
			ret = 0;
			break;
		}
	}
12910 12911
	if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
	    DMA_RWCTRL_WRITE_BNDRY_16) {
12912 12913 12914 12915 12916 12917
		static struct pci_device_id dma_wait_state_chipsets[] = {
			{ PCI_DEVICE(PCI_VENDOR_ID_APPLE,
				     PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
			{ },
		};

12918
		/* DMA test passed without adjusting DMA boundary,
12919 12920
		 * now look for chipsets that are known to expose the
		 * DMA bug without failing the test.
12921
		 */
12922 12923 12924 12925 12926 12927 12928 12929
		if (pci_dev_present(dma_wait_state_chipsets)) {
			tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
			tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
		}
		else
			/* Safe to use the calculated DMA boundary. */
			tp->dma_rwctrl = saved_dma_rwctrl;

12930 12931
		tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
	}
L
Linus Torvalds 已提交
12932 12933 12934 12935 12936 12937 12938 12939 12940 12941 12942 12943 12944 12945 12946 12947 12948 12949 12950 12951 12952 12953 12954 12955 12956 12957 12958

out:
	pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
out_nofree:
	return ret;
}

static void __devinit tg3_init_link_config(struct tg3 *tp)
{
	tp->link_config.advertising =
		(ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
		 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
		 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
		 ADVERTISED_Autoneg | ADVERTISED_MII);
	tp->link_config.speed = SPEED_INVALID;
	tp->link_config.duplex = DUPLEX_INVALID;
	tp->link_config.autoneg = AUTONEG_ENABLE;
	tp->link_config.active_speed = SPEED_INVALID;
	tp->link_config.active_duplex = DUPLEX_INVALID;
	tp->link_config.phy_is_low_power = 0;
	tp->link_config.orig_speed = SPEED_INVALID;
	tp->link_config.orig_duplex = DUPLEX_INVALID;
	tp->link_config.orig_autoneg = AUTONEG_INVALID;
}

static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
{
12959 12960 12961 12962 12963 12964 12965
	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
		tp->bufmgr_config.mbuf_read_dma_low_water =
			DEFAULT_MB_RDMA_LOW_WATER_5705;
		tp->bufmgr_config.mbuf_mac_rx_low_water =
			DEFAULT_MB_MACRX_LOW_WATER_5705;
		tp->bufmgr_config.mbuf_high_water =
			DEFAULT_MB_HIGH_WATER_5705;
M
Michael Chan 已提交
12966 12967 12968 12969 12970 12971
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
			tp->bufmgr_config.mbuf_mac_rx_low_water =
				DEFAULT_MB_MACRX_LOW_WATER_5906;
			tp->bufmgr_config.mbuf_high_water =
				DEFAULT_MB_HIGH_WATER_5906;
		}
12972 12973 12974 12975 12976 12977 12978 12979 12980 12981 12982 12983 12984 12985 12986 12987 12988 12989 12990 12991 12992 12993

		tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
			DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
		tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
			DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
		tp->bufmgr_config.mbuf_high_water_jumbo =
			DEFAULT_MB_HIGH_WATER_JUMBO_5780;
	} else {
		tp->bufmgr_config.mbuf_read_dma_low_water =
			DEFAULT_MB_RDMA_LOW_WATER;
		tp->bufmgr_config.mbuf_mac_rx_low_water =
			DEFAULT_MB_MACRX_LOW_WATER;
		tp->bufmgr_config.mbuf_high_water =
			DEFAULT_MB_HIGH_WATER;

		tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
			DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
		tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
			DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
		tp->bufmgr_config.mbuf_high_water_jumbo =
			DEFAULT_MB_HIGH_WATER_JUMBO;
	}
L
Linus Torvalds 已提交
12994 12995 12996 12997 12998 12999 13000 13001 13002 13003 13004 13005 13006 13007 13008 13009

	tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
	tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
}

static char * __devinit tg3_phy_string(struct tg3 *tp)
{
	switch (tp->phy_id & PHY_ID_MASK) {
	case PHY_ID_BCM5400:	return "5400";
	case PHY_ID_BCM5401:	return "5401";
	case PHY_ID_BCM5411:	return "5411";
	case PHY_ID_BCM5701:	return "5701";
	case PHY_ID_BCM5703:	return "5703";
	case PHY_ID_BCM5704:	return "5704";
	case PHY_ID_BCM5705:	return "5705";
	case PHY_ID_BCM5750:	return "5750";
M
Michael Chan 已提交
13010
	case PHY_ID_BCM5752:	return "5752";
M
Michael Chan 已提交
13011
	case PHY_ID_BCM5714:	return "5714";
M
Michael Chan 已提交
13012
	case PHY_ID_BCM5780:	return "5780";
M
Michael Chan 已提交
13013
	case PHY_ID_BCM5755:	return "5755";
13014
	case PHY_ID_BCM5787:	return "5787";
M
Matt Carlson 已提交
13015
	case PHY_ID_BCM5784:	return "5784";
M
Michael Chan 已提交
13016
	case PHY_ID_BCM5756:	return "5722/5756";
M
Michael Chan 已提交
13017
	case PHY_ID_BCM5906:	return "5906";
M
Matt Carlson 已提交
13018
	case PHY_ID_BCM5761:	return "5761";
L
Linus Torvalds 已提交
13019 13020 13021
	case PHY_ID_BCM8002:	return "8002/serdes";
	case 0:			return "serdes";
	default:		return "unknown";
13022
	}
L
Linus Torvalds 已提交
13023 13024
}

M
Michael Chan 已提交
13025 13026 13027 13028 13029 13030 13031 13032 13033 13034 13035 13036 13037 13038 13039 13040 13041 13042 13043 13044 13045 13046 13047 13048 13049 13050 13051 13052 13053 13054 13055 13056 13057 13058 13059 13060
static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
{
	if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
		strcpy(str, "PCI Express");
		return str;
	} else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
		u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;

		strcpy(str, "PCIX:");

		if ((clock_ctrl == 7) ||
		    ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
		     GRC_MISC_CFG_BOARD_ID_5704CIOBE))
			strcat(str, "133MHz");
		else if (clock_ctrl == 0)
			strcat(str, "33MHz");
		else if (clock_ctrl == 2)
			strcat(str, "50MHz");
		else if (clock_ctrl == 4)
			strcat(str, "66MHz");
		else if (clock_ctrl == 6)
			strcat(str, "100MHz");
	} else {
		strcpy(str, "PCI:");
		if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
			strcat(str, "66MHz");
		else
			strcat(str, "33MHz");
	}
	if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
		strcat(str, ":32-bit");
	else
		strcat(str, ":64-bit");
	return str;
}

M
Michael Chan 已提交
13061
static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
L
Linus Torvalds 已提交
13062 13063 13064 13065 13066 13067 13068 13069 13070 13071
{
	struct pci_dev *peer;
	unsigned int func, devnr = tp->pdev->devfn & ~7;

	for (func = 0; func < 8; func++) {
		peer = pci_get_slot(tp->pdev->bus, devnr | func);
		if (peer && peer != tp->pdev)
			break;
		pci_dev_put(peer);
	}
M
Michael Chan 已提交
13072 13073 13074 13075 13076 13077 13078
	/* 5704 can be configured in single-port mode, set peer to
	 * tp->pdev in that case.
	 */
	if (!peer) {
		peer = tp->pdev;
		return peer;
	}
L
Linus Torvalds 已提交
13079 13080 13081 13082 13083 13084 13085 13086 13087 13088

	/*
	 * We don't need to keep the refcount elevated; there's no way
	 * to remove one half of this device without removing the other
	 */
	pci_dev_put(peer);

	return peer;
}

13089 13090 13091 13092 13093 13094 13095 13096 13097 13098 13099 13100 13101 13102 13103 13104 13105 13106 13107 13108 13109 13110 13111
static void __devinit tg3_init_coal(struct tg3 *tp)
{
	struct ethtool_coalesce *ec = &tp->coal;

	memset(ec, 0, sizeof(*ec));
	ec->cmd = ETHTOOL_GCOALESCE;
	ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
	ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
	ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
	ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
	ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
	ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
	ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
	ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
	ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;

	if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
				 HOSTCC_MODE_CLRTICK_TXBD)) {
		ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
		ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
		ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
		ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
	}
M
Michael Chan 已提交
13112 13113 13114 13115 13116 13117

	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
		ec->rx_coalesce_usecs_irq = 0;
		ec->tx_coalesce_usecs_irq = 0;
		ec->stats_block_coalesce_usecs = 0;
	}
13118 13119
}

S
Stephen Hemminger 已提交
13120 13121 13122
static const struct net_device_ops tg3_netdev_ops = {
	.ndo_open		= tg3_open,
	.ndo_stop		= tg3_close,
13123 13124 13125 13126 13127 13128 13129 13130 13131 13132 13133 13134 13135 13136 13137 13138 13139 13140 13141 13142
	.ndo_start_xmit		= tg3_start_xmit,
	.ndo_get_stats		= tg3_get_stats,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_set_multicast_list	= tg3_set_rx_mode,
	.ndo_set_mac_address	= tg3_set_mac_addr,
	.ndo_do_ioctl		= tg3_ioctl,
	.ndo_tx_timeout		= tg3_tx_timeout,
	.ndo_change_mtu		= tg3_change_mtu,
#if TG3_VLAN_TAG_USED
	.ndo_vlan_rx_register	= tg3_vlan_rx_register,
#endif
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller	= tg3_poll_controller,
#endif
};

static const struct net_device_ops tg3_netdev_ops_dma_bug = {
	.ndo_open		= tg3_open,
	.ndo_stop		= tg3_close,
	.ndo_start_xmit		= tg3_start_xmit_dma_bug,
S
Stephen Hemminger 已提交
13143 13144 13145 13146 13147 13148 13149 13150 13151 13152 13153 13154 13155 13156 13157
	.ndo_get_stats		= tg3_get_stats,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_set_multicast_list	= tg3_set_rx_mode,
	.ndo_set_mac_address	= tg3_set_mac_addr,
	.ndo_do_ioctl		= tg3_ioctl,
	.ndo_tx_timeout		= tg3_tx_timeout,
	.ndo_change_mtu		= tg3_change_mtu,
#if TG3_VLAN_TAG_USED
	.ndo_vlan_rx_register	= tg3_vlan_rx_register,
#endif
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller	= tg3_poll_controller,
#endif
};

L
Linus Torvalds 已提交
13158 13159 13160 13161 13162 13163
static int __devinit tg3_init_one(struct pci_dev *pdev,
				  const struct pci_device_id *ent)
{
	static int tg3_version_printed = 0;
	struct net_device *dev;
	struct tg3 *tp;
J
Joe Perches 已提交
13164
	int err, pm_cap;
M
Michael Chan 已提交
13165
	char str[40];
M
Michael Chan 已提交
13166
	u64 dma_mask, persist_dma_mask;
L
Linus Torvalds 已提交
13167 13168 13169 13170 13171 13172 13173 13174 13175 13176 13177 13178 13179 13180 13181 13182 13183 13184 13185 13186 13187 13188 13189 13190 13191 13192 13193 13194 13195 13196 13197 13198 13199 13200 13201 13202 13203 13204 13205 13206 13207 13208 13209 13210 13211 13212 13213 13214

	if (tg3_version_printed++ == 0)
		printk(KERN_INFO "%s", version);

	err = pci_enable_device(pdev);
	if (err) {
		printk(KERN_ERR PFX "Cannot enable PCI device, "
		       "aborting.\n");
		return err;
	}

	err = pci_request_regions(pdev, DRV_MODULE_NAME);
	if (err) {
		printk(KERN_ERR PFX "Cannot obtain PCI resources, "
		       "aborting.\n");
		goto err_out_disable_pdev;
	}

	pci_set_master(pdev);

	/* Find power-management capability. */
	pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
	if (pm_cap == 0) {
		printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
		       "aborting.\n");
		err = -EIO;
		goto err_out_free_res;
	}

	dev = alloc_etherdev(sizeof(*tp));
	if (!dev) {
		printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
		err = -ENOMEM;
		goto err_out_free_res;
	}

	SET_NETDEV_DEV(dev, &pdev->dev);

#if TG3_VLAN_TAG_USED
	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
#endif

	tp = netdev_priv(dev);
	tp->pdev = pdev;
	tp->dev = dev;
	tp->pm_cap = pm_cap;
	tp->rx_mode = TG3_DEF_RX_MODE;
	tp->tx_mode = TG3_DEF_TX_MODE;
13215

L
Linus Torvalds 已提交
13216 13217 13218 13219 13220 13221 13222 13223 13224 13225 13226 13227 13228 13229 13230 13231 13232 13233 13234 13235 13236 13237 13238 13239 13240 13241 13242 13243
	if (tg3_debug > 0)
		tp->msg_enable = tg3_debug;
	else
		tp->msg_enable = TG3_DEF_MSG_ENABLE;

	/* The word/byte swap controls here control register access byte
	 * swapping.  DMA data byte swapping is controlled in the GRC_MODE
	 * setting below.
	 */
	tp->misc_host_ctrl =
		MISC_HOST_CTRL_MASK_PCI_INT |
		MISC_HOST_CTRL_WORD_SWAP |
		MISC_HOST_CTRL_INDIR_ACCESS |
		MISC_HOST_CTRL_PCISTATE_RW;

	/* The NONFRM (non-frame) byte/word swap controls take effect
	 * on descriptor entries, anything which isn't packet data.
	 *
	 * The StrongARM chips on the board (one for tx, one for rx)
	 * are running in big-endian mode.
	 */
	tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
			GRC_MODE_WSWAP_NONFRM_DATA);
#ifdef __BIG_ENDIAN
	tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
#endif
	spin_lock_init(&tp->lock);
	spin_lock_init(&tp->indirect_lock);
D
David Howells 已提交
13244
	INIT_WORK(&tp->reset_task, tg3_reset_task);
L
Linus Torvalds 已提交
13245

M
Matt Carlson 已提交
13246
	tp->regs = pci_ioremap_bar(pdev, BAR_0);
A
Andy Gospodarek 已提交
13247
	if (!tp->regs) {
L
Linus Torvalds 已提交
13248 13249 13250 13251 13252 13253 13254 13255 13256 13257 13258 13259
		printk(KERN_ERR PFX "Cannot map device registers, "
		       "aborting.\n");
		err = -ENOMEM;
		goto err_out_free_dev;
	}

	tg3_init_link_config(tp);

	tp->rx_pending = TG3_DEF_RX_RING_PENDING;
	tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
	tp->tx_pending = TG3_DEF_TX_RING_PENDING;

13260
	netif_napi_add(dev, &tp->napi, tg3_poll, 64);
L
Linus Torvalds 已提交
13261 13262 13263 13264 13265 13266 13267 13268 13269 13270 13271
	dev->ethtool_ops = &tg3_ethtool_ops;
	dev->watchdog_timeo = TG3_TX_TIMEOUT;
	dev->irq = pdev->irq;

	err = tg3_get_invariants(tp);
	if (err) {
		printk(KERN_ERR PFX "Problem fetching invariants of chip, "
		       "aborting.\n");
		goto err_out_iounmap;
	}

M
Matt Carlson 已提交
13272
	if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13273 13274 13275 13276 13277 13278
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
		dev->netdev_ops = &tg3_netdev_ops;
	else
		dev->netdev_ops = &tg3_netdev_ops_dma_bug;


13279 13280
	/* The EPB bridge inside 5714, 5715, and 5780 and any
	 * device behind the EPB cannot support DMA addresses > 40-bit.
M
Michael Chan 已提交
13281 13282 13283 13284
	 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
	 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
	 * do DMA address check in tg3_start_xmit().
	 */
13285
	if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13286
		persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13287
	else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13288
		persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
M
Michael Chan 已提交
13289
#ifdef CONFIG_HIGHMEM
13290
		dma_mask = DMA_BIT_MASK(64);
M
Michael Chan 已提交
13291
#endif
13292
	} else
13293
		persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
M
Michael Chan 已提交
13294 13295

	/* Configure DMA attributes. */
13296
	if (dma_mask > DMA_BIT_MASK(32)) {
M
Michael Chan 已提交
13297 13298 13299 13300 13301 13302 13303 13304 13305 13306 13307 13308
		err = pci_set_dma_mask(pdev, dma_mask);
		if (!err) {
			dev->features |= NETIF_F_HIGHDMA;
			err = pci_set_consistent_dma_mask(pdev,
							  persist_dma_mask);
			if (err < 0) {
				printk(KERN_ERR PFX "Unable to obtain 64 bit "
				       "DMA for consistent allocations\n");
				goto err_out_iounmap;
			}
		}
	}
13309 13310
	if (err || dma_mask == DMA_BIT_MASK(32)) {
		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
M
Michael Chan 已提交
13311 13312 13313 13314 13315 13316 13317
		if (err) {
			printk(KERN_ERR PFX "No usable DMA configuration, "
			       "aborting.\n");
			goto err_out_iounmap;
		}
	}

13318
	tg3_init_bufmgr_config(tp);
L
Linus Torvalds 已提交
13319

13320
	if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
M
Matt Carlson 已提交
13321
		tp->fw_needed = FIRMWARE_TG3;
13322

L
Linus Torvalds 已提交
13323 13324 13325 13326 13327 13328
	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
		tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
	}
	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
	    tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13329
	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
L
Linus Torvalds 已提交
13330 13331 13332
	    (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
		tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
	} else {
M
Michael Chan 已提交
13333
		tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13334
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
M
Matt Carlson 已提交
13335
			tp->fw_needed = FIRMWARE_TG3TSO5;
13336
		else
M
Matt Carlson 已提交
13337
			tp->fw_needed = FIRMWARE_TG3TSO;
13338
	}
L
Linus Torvalds 已提交
13339

M
Michael Chan 已提交
13340 13341 13342 13343
	/* TSO is on by default on chips that support hardware TSO.
	 * Firmware TSO on older chips gives lower performance, so it
	 * is off by default, but can be enabled using ethtool.
	 */
M
Michael Chan 已提交
13344
	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
M
Matt Carlson 已提交
13345 13346 13347 13348
		if (dev->features & NETIF_F_IP_CSUM)
			dev->features |= NETIF_F_TSO;
		if ((dev->features & NETIF_F_IPV6_CSUM) &&
		    (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
M
Michael Chan 已提交
13349
			dev->features |= NETIF_F_TSO6;
M
Matt Carlson 已提交
13350 13351 13352
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
		    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
		     GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
M
Matt Carlson 已提交
13353 13354
			GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
M
Matt Carlson 已提交
13355
			dev->features |= NETIF_F_TSO_ECN;
M
Michael Chan 已提交
13356
	}
L
Linus Torvalds 已提交
13357 13358 13359 13360 13361 13362 13363 13364 13365 13366 13367 13368 13369


	if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
	    !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
	    !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
		tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
		tp->rx_pending = 63;
	}

	err = tg3_get_device_address(tp);
	if (err) {
		printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
		       "aborting.\n");
13370
		goto err_out_fw;
L
Linus Torvalds 已提交
13371 13372
	}

M
Matt Carlson 已提交
13373
	if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
M
Matt Carlson 已提交
13374
		tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
A
Al Viro 已提交
13375
		if (!tp->aperegs) {
M
Matt Carlson 已提交
13376 13377 13378
			printk(KERN_ERR PFX "Cannot map APE registers, "
			       "aborting.\n");
			err = -ENOMEM;
13379
			goto err_out_fw;
M
Matt Carlson 已提交
13380 13381 13382
		}

		tg3_ape_lock_init(tp);
13383 13384 13385

		if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
			tg3_read_dash_ver(tp);
M
Matt Carlson 已提交
13386 13387
	}

L
Linus Torvalds 已提交
13388 13389 13390 13391 13392 13393 13394 13395
	/*
	 * Reset chip in case UNDI or EFI driver did not shutdown
	 * DMA self test will enable WDMAC and we'll see (spurious)
	 * pending DMA on the PCI bus at that point.
	 */
	if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
	    (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
		tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
M
Michael Chan 已提交
13396
		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
L
Linus Torvalds 已提交
13397 13398 13399 13400 13401
	}

	err = tg3_test_dma(tp);
	if (err) {
		printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
M
Matt Carlson 已提交
13402
		goto err_out_apeunmap;
L
Linus Torvalds 已提交
13403 13404 13405 13406
	}

	/* flow control autonegotiation is default behavior */
	tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13407
	tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
L
Linus Torvalds 已提交
13408

13409 13410
	tg3_init_coal(tp);

13411 13412
	pci_set_drvdata(pdev, dev);

L
Linus Torvalds 已提交
13413 13414 13415 13416
	err = register_netdev(dev);
	if (err) {
		printk(KERN_ERR PFX "Cannot register net device, "
		       "aborting.\n");
M
Matt Carlson 已提交
13417
		goto err_out_apeunmap;
L
Linus Torvalds 已提交
13418 13419
	}

13420
	printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
L
Linus Torvalds 已提交
13421 13422 13423
	       dev->name,
	       tp->board_part_number,
	       tp->pci_chip_rev_id,
M
Michael Chan 已提交
13424
	       tg3_bus_string(tp, str),
J
Johannes Berg 已提交
13425
	       dev->dev_addr);
L
Linus Torvalds 已提交
13426

13427 13428 13429 13430 13431
	if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
		printk(KERN_INFO
		       "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
		       tp->dev->name,
		       tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13432
		       dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13433 13434 13435 13436 13437 13438 13439 13440 13441 13442
	else
		printk(KERN_INFO
		       "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
		       tp->dev->name, tg3_phy_string(tp),
		       ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
			((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
			 "10/100/1000Base-T")),
		       (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);

	printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
L
Linus Torvalds 已提交
13443 13444 13445 13446 13447 13448
	       dev->name,
	       (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
	       (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
	       (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
	       (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
	       (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13449 13450
	printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
	       dev->name, tp->dma_rwctrl,
13451
	       (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13452
	        (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
L
Linus Torvalds 已提交
13453 13454 13455

	return 0;

M
Matt Carlson 已提交
13456 13457 13458 13459 13460 13461
err_out_apeunmap:
	if (tp->aperegs) {
		iounmap(tp->aperegs);
		tp->aperegs = NULL;
	}

13462 13463 13464 13465
err_out_fw:
	if (tp->fw)
		release_firmware(tp->fw);

L
Linus Torvalds 已提交
13466
err_out_iounmap:
13467 13468
	if (tp->regs) {
		iounmap(tp->regs);
P
Peter Hagervall 已提交
13469
		tp->regs = NULL;
13470
	}
L
Linus Torvalds 已提交
13471 13472 13473 13474 13475 13476 13477 13478 13479 13480 13481 13482 13483 13484 13485 13486 13487 13488 13489 13490

err_out_free_dev:
	free_netdev(dev);

err_out_free_res:
	pci_release_regions(pdev);

err_out_disable_pdev:
	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);
	return err;
}

static void __devexit tg3_remove_one(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);

	if (dev) {
		struct tg3 *tp = netdev_priv(dev);

13491 13492 13493
		if (tp->fw)
			release_firmware(tp->fw);

M
Michael Chan 已提交
13494
		flush_scheduled_work();
M
Matt Carlson 已提交
13495

M
Matt Carlson 已提交
13496 13497
		if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
			tg3_phy_fini(tp);
M
Matt Carlson 已提交
13498
			tg3_mdio_fini(tp);
M
Matt Carlson 已提交
13499
		}
M
Matt Carlson 已提交
13500

L
Linus Torvalds 已提交
13501
		unregister_netdev(dev);
M
Matt Carlson 已提交
13502 13503 13504 13505
		if (tp->aperegs) {
			iounmap(tp->aperegs);
			tp->aperegs = NULL;
		}
13506 13507
		if (tp->regs) {
			iounmap(tp->regs);
P
Peter Hagervall 已提交
13508
			tp->regs = NULL;
13509
		}
L
Linus Torvalds 已提交
13510 13511 13512 13513 13514 13515 13516 13517 13518 13519 13520
		free_netdev(dev);
		pci_release_regions(pdev);
		pci_disable_device(pdev);
		pci_set_drvdata(pdev, NULL);
	}
}

static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct tg3 *tp = netdev_priv(dev);
13521
	pci_power_t target_state;
L
Linus Torvalds 已提交
13522 13523
	int err;

13524 13525 13526 13527 13528 13529
	/* PCI register 4 needs to be saved whether netif_running() or not.
	 * MSI address and data need to be saved if using MSI and
	 * netif_running().
	 */
	pci_save_state(pdev);

L
Linus Torvalds 已提交
13530 13531 13532
	if (!netif_running(dev))
		return 0;

M
Michael Chan 已提交
13533
	flush_scheduled_work();
M
Matt Carlson 已提交
13534
	tg3_phy_stop(tp);
L
Linus Torvalds 已提交
13535 13536 13537 13538
	tg3_netif_stop(tp);

	del_timer_sync(&tp->timer);

13539
	tg3_full_lock(tp, 1);
L
Linus Torvalds 已提交
13540
	tg3_disable_ints(tp);
13541
	tg3_full_unlock(tp);
L
Linus Torvalds 已提交
13542 13543 13544

	netif_device_detach(dev);

13545
	tg3_full_lock(tp, 0);
M
Michael Chan 已提交
13546
	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
M
Michael Chan 已提交
13547
	tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13548
	tg3_full_unlock(tp);
L
Linus Torvalds 已提交
13549

13550 13551 13552
	target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;

	err = tg3_set_power_state(tp, target_state);
L
Linus Torvalds 已提交
13553
	if (err) {
M
Matt Carlson 已提交
13554 13555
		int err2;

13556
		tg3_full_lock(tp, 0);
L
Linus Torvalds 已提交
13557

M
Michael Chan 已提交
13558
		tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
M
Matt Carlson 已提交
13559 13560
		err2 = tg3_restart_hw(tp, 1);
		if (err2)
M
Michael Chan 已提交
13561
			goto out;
L
Linus Torvalds 已提交
13562 13563 13564 13565 13566 13567 13568

		tp->timer.expires = jiffies + tp->timer_offset;
		add_timer(&tp->timer);

		netif_device_attach(dev);
		tg3_netif_start(tp);

M
Michael Chan 已提交
13569
out:
13570
		tg3_full_unlock(tp);
M
Matt Carlson 已提交
13571 13572 13573

		if (!err2)
			tg3_phy_start(tp);
L
Linus Torvalds 已提交
13574 13575 13576 13577 13578 13579 13580 13581 13582 13583 13584
	}

	return err;
}

static int tg3_resume(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct tg3 *tp = netdev_priv(dev);
	int err;

13585 13586
	pci_restore_state(tp->pdev);

L
Linus Torvalds 已提交
13587 13588 13589
	if (!netif_running(dev))
		return 0;

M
Michael Chan 已提交
13590
	err = tg3_set_power_state(tp, PCI_D0);
L
Linus Torvalds 已提交
13591 13592 13593 13594 13595
	if (err)
		return err;

	netif_device_attach(dev);

13596
	tg3_full_lock(tp, 0);
L
Linus Torvalds 已提交
13597

M
Michael Chan 已提交
13598
	tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
M
Michael Chan 已提交
13599 13600 13601
	err = tg3_restart_hw(tp, 1);
	if (err)
		goto out;
L
Linus Torvalds 已提交
13602 13603 13604 13605 13606 13607

	tp->timer.expires = jiffies + tp->timer_offset;
	add_timer(&tp->timer);

	tg3_netif_start(tp);

M
Michael Chan 已提交
13608
out:
13609
	tg3_full_unlock(tp);
L
Linus Torvalds 已提交
13610

M
Matt Carlson 已提交
13611 13612 13613
	if (!err)
		tg3_phy_start(tp);

M
Michael Chan 已提交
13614
	return err;
L
Linus Torvalds 已提交
13615 13616 13617 13618 13619 13620 13621 13622 13623 13624 13625 13626 13627
}

static struct pci_driver tg3_driver = {
	.name		= DRV_MODULE_NAME,
	.id_table	= tg3_pci_tbl,
	.probe		= tg3_init_one,
	.remove		= __devexit_p(tg3_remove_one),
	.suspend	= tg3_suspend,
	.resume		= tg3_resume
};

static int __init tg3_init(void)
{
13628
	return pci_register_driver(&tg3_driver);
L
Linus Torvalds 已提交
13629 13630 13631 13632 13633 13634 13635 13636 13637
}

static void __exit tg3_cleanup(void)
{
	pci_unregister_driver(&tg3_driver);
}

module_init(tg3_init);
module_exit(tg3_cleanup);