sh_eth.c 69.1 KB
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S
Sergei Shtylyov 已提交
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/*  SuperH Ethernet device driver
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 *
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 *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
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 *  Copyright (C) 2008-2013 Renesas Solutions Corp.
 *  Copyright (C) 2013 Cogent Embedded, Inc.
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 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms and conditions of the GNU General Public License,
 *  version 2, as published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *
 *  The full GNU General Public License is included in this distribution in
 *  the file called "COPYING".
 */

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Yoshihiro Shimoda 已提交
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#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/mdio-bitbang.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <linux/cache.h>
#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/ethtool.h>
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#include <linux/if_vlan.h>
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#include <linux/clk.h>
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#include <linux/sh_eth.h>
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#include "sh_eth.h"

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#define SH_ETH_DEF_MSG_ENABLE \
		(NETIF_MSG_LINK	| \
		NETIF_MSG_TIMER	| \
		NETIF_MSG_RX_ERR| \
		NETIF_MSG_TX_ERR)

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static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
	[EDSR]		= 0x0000,
	[EDMR]		= 0x0400,
	[EDTRR]		= 0x0408,
	[EDRRR]		= 0x0410,
	[EESR]		= 0x0428,
	[EESIPR]	= 0x0430,
	[TDLAR]		= 0x0010,
	[TDFAR]		= 0x0014,
	[TDFXR]		= 0x0018,
	[TDFFR]		= 0x001c,
	[RDLAR]		= 0x0030,
	[RDFAR]		= 0x0034,
	[RDFXR]		= 0x0038,
	[RDFFR]		= 0x003c,
	[TRSCER]	= 0x0438,
	[RMFCR]		= 0x0440,
	[TFTR]		= 0x0448,
	[FDR]		= 0x0450,
	[RMCR]		= 0x0458,
	[RPADIR]	= 0x0460,
	[FCFTR]		= 0x0468,
	[CSMR]		= 0x04E4,

	[ECMR]		= 0x0500,
	[ECSR]		= 0x0510,
	[ECSIPR]	= 0x0518,
	[PIR]		= 0x0520,
	[PSR]		= 0x0528,
	[PIPR]		= 0x052c,
	[RFLR]		= 0x0508,
	[APR]		= 0x0554,
	[MPR]		= 0x0558,
	[PFTCR]		= 0x055c,
	[PFRCR]		= 0x0560,
	[TPAUSER]	= 0x0564,
	[GECMR]		= 0x05b0,
	[BCULR]		= 0x05b4,
	[MAHR]		= 0x05c0,
	[MALR]		= 0x05c8,
	[TROCR]		= 0x0700,
	[CDCR]		= 0x0708,
	[LCCR]		= 0x0710,
	[CEFCR]		= 0x0740,
	[FRECR]		= 0x0748,
	[TSFRCR]	= 0x0750,
	[TLFRCR]	= 0x0758,
	[RFCR]		= 0x0760,
	[CERCR]		= 0x0768,
	[CEECR]		= 0x0770,
	[MAFCR]		= 0x0778,
	[RMII_MII]	= 0x0790,

	[ARSTR]		= 0x0000,
	[TSU_CTRST]	= 0x0004,
	[TSU_FWEN0]	= 0x0010,
	[TSU_FWEN1]	= 0x0014,
	[TSU_FCM]	= 0x0018,
	[TSU_BSYSL0]	= 0x0020,
	[TSU_BSYSL1]	= 0x0024,
	[TSU_PRISL0]	= 0x0028,
	[TSU_PRISL1]	= 0x002c,
	[TSU_FWSL0]	= 0x0030,
	[TSU_FWSL1]	= 0x0034,
	[TSU_FWSLC]	= 0x0038,
	[TSU_QTAG0]	= 0x0040,
	[TSU_QTAG1]	= 0x0044,
	[TSU_FWSR]	= 0x0050,
	[TSU_FWINMK]	= 0x0054,
	[TSU_ADQT0]	= 0x0048,
	[TSU_ADQT1]	= 0x004c,
	[TSU_VTAG0]	= 0x0058,
	[TSU_VTAG1]	= 0x005c,
	[TSU_ADSBSY]	= 0x0060,
	[TSU_TEN]	= 0x0064,
	[TSU_POST1]	= 0x0070,
	[TSU_POST2]	= 0x0074,
	[TSU_POST3]	= 0x0078,
	[TSU_POST4]	= 0x007c,
	[TSU_ADRH0]	= 0x0100,
	[TSU_ADRL0]	= 0x0104,
	[TSU_ADRH31]	= 0x01f8,
	[TSU_ADRL31]	= 0x01fc,

	[TXNLCR0]	= 0x0080,
	[TXALCR0]	= 0x0084,
	[RXNLCR0]	= 0x0088,
	[RXALCR0]	= 0x008c,
	[FWNLCR0]	= 0x0090,
	[FWALCR0]	= 0x0094,
	[TXNLCR1]	= 0x00a0,
	[TXALCR1]	= 0x00a0,
	[RXNLCR1]	= 0x00a8,
	[RXALCR1]	= 0x00ac,
	[FWNLCR1]	= 0x00b0,
	[FWALCR1]	= 0x00b4,
};

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Simon Horman 已提交
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static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
	[EDSR]		= 0x0000,
	[EDMR]		= 0x0400,
	[EDTRR]		= 0x0408,
	[EDRRR]		= 0x0410,
	[EESR]		= 0x0428,
	[EESIPR]	= 0x0430,
	[TDLAR]		= 0x0010,
	[TDFAR]		= 0x0014,
	[TDFXR]		= 0x0018,
	[TDFFR]		= 0x001c,
	[RDLAR]		= 0x0030,
	[RDFAR]		= 0x0034,
	[RDFXR]		= 0x0038,
	[RDFFR]		= 0x003c,
	[TRSCER]	= 0x0438,
	[RMFCR]		= 0x0440,
	[TFTR]		= 0x0448,
	[FDR]		= 0x0450,
	[RMCR]		= 0x0458,
	[RPADIR]	= 0x0460,
	[FCFTR]		= 0x0468,
	[CSMR]		= 0x04E4,

	[ECMR]		= 0x0500,
	[RFLR]		= 0x0508,
	[ECSR]		= 0x0510,
	[ECSIPR]	= 0x0518,
	[PIR]		= 0x0520,
	[APR]		= 0x0554,
	[MPR]		= 0x0558,
	[PFTCR]		= 0x055c,
	[PFRCR]		= 0x0560,
	[TPAUSER]	= 0x0564,
	[MAHR]		= 0x05c0,
	[MALR]		= 0x05c8,
	[CEFCR]		= 0x0740,
	[FRECR]		= 0x0748,
	[TSFRCR]	= 0x0750,
	[TLFRCR]	= 0x0758,
	[RFCR]		= 0x0760,
	[MAFCR]		= 0x0778,

	[ARSTR]		= 0x0000,
	[TSU_CTRST]	= 0x0004,
	[TSU_VTAG0]	= 0x0058,
	[TSU_ADSBSY]	= 0x0060,
	[TSU_TEN]	= 0x0064,
	[TSU_ADRH0]	= 0x0100,
	[TSU_ADRL0]	= 0x0104,
	[TSU_ADRH31]	= 0x01f8,
	[TSU_ADRL31]	= 0x01fc,

	[TXNLCR0]	= 0x0080,
	[TXALCR0]	= 0x0084,
	[RXNLCR0]	= 0x0088,
	[RXALCR0]	= 0x008C,
};

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static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
	[ECMR]		= 0x0300,
	[RFLR]		= 0x0308,
	[ECSR]		= 0x0310,
	[ECSIPR]	= 0x0318,
	[PIR]		= 0x0320,
	[PSR]		= 0x0328,
	[RDMLR]		= 0x0340,
	[IPGR]		= 0x0350,
	[APR]		= 0x0354,
	[MPR]		= 0x0358,
	[RFCF]		= 0x0360,
	[TPAUSER]	= 0x0364,
	[TPAUSECR]	= 0x0368,
	[MAHR]		= 0x03c0,
	[MALR]		= 0x03c8,
	[TROCR]		= 0x03d0,
	[CDCR]		= 0x03d4,
	[LCCR]		= 0x03d8,
	[CNDCR]		= 0x03dc,
	[CEFCR]		= 0x03e4,
	[FRECR]		= 0x03e8,
	[TSFRCR]	= 0x03ec,
	[TLFRCR]	= 0x03f0,
	[RFCR]		= 0x03f4,
	[MAFCR]		= 0x03f8,

	[EDMR]		= 0x0200,
	[EDTRR]		= 0x0208,
	[EDRRR]		= 0x0210,
	[TDLAR]		= 0x0218,
	[RDLAR]		= 0x0220,
	[EESR]		= 0x0228,
	[EESIPR]	= 0x0230,
	[TRSCER]	= 0x0238,
	[RMFCR]		= 0x0240,
	[TFTR]		= 0x0248,
	[FDR]		= 0x0250,
	[RMCR]		= 0x0258,
	[TFUCR]		= 0x0264,
	[RFOCR]		= 0x0268,
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	[RMIIMODE]      = 0x026c,
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	[FCFTR]		= 0x0270,
	[TRIMD]		= 0x027c,
};

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static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
	[ECMR]		= 0x0100,
	[RFLR]		= 0x0108,
	[ECSR]		= 0x0110,
	[ECSIPR]	= 0x0118,
	[PIR]		= 0x0120,
	[PSR]		= 0x0128,
	[RDMLR]		= 0x0140,
	[IPGR]		= 0x0150,
	[APR]		= 0x0154,
	[MPR]		= 0x0158,
	[TPAUSER]	= 0x0164,
	[RFCF]		= 0x0160,
	[TPAUSECR]	= 0x0168,
	[BCFRR]		= 0x016c,
	[MAHR]		= 0x01c0,
	[MALR]		= 0x01c8,
	[TROCR]		= 0x01d0,
	[CDCR]		= 0x01d4,
	[LCCR]		= 0x01d8,
	[CNDCR]		= 0x01dc,
	[CEFCR]		= 0x01e4,
	[FRECR]		= 0x01e8,
	[TSFRCR]	= 0x01ec,
	[TLFRCR]	= 0x01f0,
	[RFCR]		= 0x01f4,
	[MAFCR]		= 0x01f8,
	[RTRATE]	= 0x01fc,

	[EDMR]		= 0x0000,
	[EDTRR]		= 0x0008,
	[EDRRR]		= 0x0010,
	[TDLAR]		= 0x0018,
	[RDLAR]		= 0x0020,
	[EESR]		= 0x0028,
	[EESIPR]	= 0x0030,
	[TRSCER]	= 0x0038,
	[RMFCR]		= 0x0040,
	[TFTR]		= 0x0048,
	[FDR]		= 0x0050,
	[RMCR]		= 0x0058,
	[TFUCR]		= 0x0064,
	[RFOCR]		= 0x0068,
	[FCFTR]		= 0x0070,
	[RPADIR]	= 0x0078,
	[TRIMD]		= 0x007c,
	[RBWAR]		= 0x00c8,
	[RDFAR]		= 0x00cc,
	[TBRAR]		= 0x00d4,
	[TDFAR]		= 0x00d8,
};

static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
	[ECMR]		= 0x0160,
	[ECSR]		= 0x0164,
	[ECSIPR]	= 0x0168,
	[PIR]		= 0x016c,
	[MAHR]		= 0x0170,
	[MALR]		= 0x0174,
	[RFLR]		= 0x0178,
	[PSR]		= 0x017c,
	[TROCR]		= 0x0180,
	[CDCR]		= 0x0184,
	[LCCR]		= 0x0188,
	[CNDCR]		= 0x018c,
	[CEFCR]		= 0x0194,
	[FRECR]		= 0x0198,
	[TSFRCR]	= 0x019c,
	[TLFRCR]	= 0x01a0,
	[RFCR]		= 0x01a4,
	[MAFCR]		= 0x01a8,
	[IPGR]		= 0x01b4,
	[APR]		= 0x01b8,
	[MPR]		= 0x01bc,
	[TPAUSER]	= 0x01c4,
	[BCFR]		= 0x01cc,

	[ARSTR]		= 0x0000,
	[TSU_CTRST]	= 0x0004,
	[TSU_FWEN0]	= 0x0010,
	[TSU_FWEN1]	= 0x0014,
	[TSU_FCM]	= 0x0018,
	[TSU_BSYSL0]	= 0x0020,
	[TSU_BSYSL1]	= 0x0024,
	[TSU_PRISL0]	= 0x0028,
	[TSU_PRISL1]	= 0x002c,
	[TSU_FWSL0]	= 0x0030,
	[TSU_FWSL1]	= 0x0034,
	[TSU_FWSLC]	= 0x0038,
	[TSU_QTAGM0]	= 0x0040,
	[TSU_QTAGM1]	= 0x0044,
	[TSU_ADQT0]	= 0x0048,
	[TSU_ADQT1]	= 0x004c,
	[TSU_FWSR]	= 0x0050,
	[TSU_FWINMK]	= 0x0054,
	[TSU_ADSBSY]	= 0x0060,
	[TSU_TEN]	= 0x0064,
	[TSU_POST1]	= 0x0070,
	[TSU_POST2]	= 0x0074,
	[TSU_POST3]	= 0x0078,
	[TSU_POST4]	= 0x007c,

	[TXNLCR0]	= 0x0080,
	[TXALCR0]	= 0x0084,
	[RXNLCR0]	= 0x0088,
	[RXALCR0]	= 0x008c,
	[FWNLCR0]	= 0x0090,
	[FWALCR0]	= 0x0094,
	[TXNLCR1]	= 0x00a0,
	[TXALCR1]	= 0x00a0,
	[RXNLCR1]	= 0x00a8,
	[RXALCR1]	= 0x00ac,
	[FWNLCR1]	= 0x00b0,
	[FWALCR1]	= 0x00b4,

	[TSU_ADRH0]	= 0x0100,
	[TSU_ADRL0]	= 0x0104,
	[TSU_ADRL31]	= 0x01fc,
};

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static bool sh_eth_is_gether(struct sh_eth_private *mdp)
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{
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	return mdp->reg_offset == sh_eth_offset_gigabit;
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}

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static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
{
	return mdp->reg_offset == sh_eth_offset_fast_rz;
}

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static void sh_eth_select_mii(struct net_device *ndev)
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{
	u32 value = 0x0;
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->phy_interface) {
	case PHY_INTERFACE_MODE_GMII:
		value = 0x2;
		break;
	case PHY_INTERFACE_MODE_MII:
		value = 0x1;
		break;
	case PHY_INTERFACE_MODE_RMII:
		value = 0x0;
		break;
	default:
		pr_warn("PHY interface mode was not setup. Set to MII.\n");
		value = 0x1;
		break;
	}

	sh_eth_write(ndev, value, RMII_MII);
}

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static void sh_eth_set_duplex(struct net_device *ndev)
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{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	if (mdp->duplex) /* Full */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
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	else		/* Half */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
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}

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/* There is CPU dependent code */
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static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
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{
	struct sh_eth_private *mdp = netdev_priv(ndev);
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	switch (mdp->speed) {
	case 10: /* 10BASE */
		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
		break;
	case 100:/* 100BASE */
		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
		break;
	default:
		break;
	}
}

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/* R8A7778/9 */
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static struct sh_eth_cpu_data r8a777x_data = {
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	.set_duplex	= sh_eth_set_duplex,
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	.set_rate	= sh_eth_set_rate_r8a777x,
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	.register_type	= SH_ETH_REG_FAST_RCAR,

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	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
	.eesipr_value	= 0x01ff009f,

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
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	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
			  EESR_ECI,
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	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
};

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/* R8A7790/1 */
static struct sh_eth_cpu_data r8a779x_data = {
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	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate_r8a777x,

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	.register_type	= SH_ETH_REG_FAST_RCAR,

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	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
	.eesipr_value	= 0x01ff009f,

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
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	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
			  EESR_ECI,
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	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
	.rmiimode	= 1,
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	.shift_rd0	= 1,
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};

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static void sh_eth_set_rate_sh7724(struct net_device *ndev)
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{
	struct sh_eth_private *mdp = netdev_priv(ndev);
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	switch (mdp->speed) {
	case 10: /* 10BASE */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
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		break;
	case 100:/* 100BASE */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
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		break;
	default:
		break;
	}
}

/* SH7724 */
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static struct sh_eth_cpu_data sh7724_data = {
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	.set_duplex	= sh_eth_set_duplex,
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	.set_rate	= sh_eth_set_rate_sh7724,
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	.register_type	= SH_ETH_REG_FAST_SH4,

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	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
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	.eesipr_value	= 0x01ff009f,
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	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
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	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
			  EESR_ECI,
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	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
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	.rpadir		= 1,
	.rpadir_value	= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
516
};
517

518
static void sh_eth_set_rate_sh7757(struct net_device *ndev)
519 520 521 522 523
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
524
		sh_eth_write(ndev, 0, RTRATE);
525 526
		break;
	case 100:/* 100BASE */
527
		sh_eth_write(ndev, 1, RTRATE);
528 529 530 531 532 533 534
		break;
	default:
		break;
	}
}

/* SH7757 */
535 536 537
static struct sh_eth_cpu_data sh7757_data = {
	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate_sh7757,
538

539 540
	.register_type	= SH_ETH_REG_FAST_SH4,

541
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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542
	.rmcr_value	= RMCR_RNC,
543 544

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
545 546 547
	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
			  EESR_ECI,
548

549
	.irq_flags	= IRQF_SHARED,
550 551 552 553 554
	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
	.no_ade		= 1,
555 556
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
557
};
558

559
#define SH_GIGA_ETH_BASE	0xfee00000UL
560 561 562 563 564 565 566 567 568
#define GIGA_MALR(port)		(SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
#define GIGA_MAHR(port)		(SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
static void sh_eth_chip_reset_giga(struct net_device *ndev)
{
	int i;
	unsigned long mahr[2], malr[2];

	/* save MAHR and MALR */
	for (i = 0; i < 2; i++) {
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		malr[i] = ioread32((void *)GIGA_MALR(i));
		mahr[i] = ioread32((void *)GIGA_MAHR(i));
571 572 573
	}

	/* reset device */
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574
	iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
575 576 577 578
	mdelay(1);

	/* restore MAHR and MALR */
	for (i = 0; i < 2; i++) {
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Yoshihiro Shimoda 已提交
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		iowrite32(malr[i], (void *)GIGA_MALR(i));
		iowrite32(mahr[i], (void *)GIGA_MAHR(i));
581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603
	}
}

static void sh_eth_set_rate_giga(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
		sh_eth_write(ndev, 0x00000000, GECMR);
		break;
	case 100:/* 100BASE */
		sh_eth_write(ndev, 0x00000010, GECMR);
		break;
	case 1000: /* 1000BASE */
		sh_eth_write(ndev, 0x00000020, GECMR);
		break;
	default:
		break;
	}
}

/* SH7757(GETHERC) */
604
static struct sh_eth_cpu_data sh7757_data_giga = {
605
	.chip_reset	= sh_eth_chip_reset_giga,
606
	.set_duplex	= sh_eth_set_duplex,
607 608
	.set_rate	= sh_eth_set_rate_giga,

609 610
	.register_type	= SH_ETH_REG_GIGABIT,

611 612 613 614 615
	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
616 617 618
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
			  EESR_TDE | EESR_ECI,
619
	.fdr_value	= 0x0000072f,
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	.rmcr_value	= RMCR_RNC,
621

622
	.irq_flags	= IRQF_SHARED,
623 624 625 626 627 628 629 630 631
	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
	.no_trimd	= 1,
	.no_ade		= 1,
632
	.tsu		= 1,
633 634
};

635 636
static void sh_eth_chip_reset(struct net_device *ndev)
{
637 638
	struct sh_eth_private *mdp = netdev_priv(ndev);

639
	/* reset device */
640
	sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
641 642 643
	mdelay(1);
}

644
static void sh_eth_set_rate_gether(struct net_device *ndev)
645 646 647 648 649
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
650
		sh_eth_write(ndev, GECMR_10, GECMR);
651 652
		break;
	case 100:/* 100BASE */
653
		sh_eth_write(ndev, GECMR_100, GECMR);
654 655
		break;
	case 1000: /* 1000BASE */
656
		sh_eth_write(ndev, GECMR_1000, GECMR);
657 658 659 660 661 662
		break;
	default:
		break;
	}
}

663 664
/* SH7734 */
static struct sh_eth_cpu_data sh7734_data = {
665 666
	.chip_reset	= sh_eth_chip_reset,
	.set_duplex	= sh_eth_set_duplex,
667 668
	.set_rate	= sh_eth_set_rate_gether,

669 670
	.register_type	= SH_ETH_REG_GIGABIT,

671 672 673 674 675
	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
676 677 678
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
			  EESR_TDE | EESR_ECI,
679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.no_trimd	= 1,
	.no_ade		= 1,
	.tsu		= 1,
	.hw_crc		= 1,
	.select_mii	= 1,
};

/* SH7763 */
static struct sh_eth_cpu_data sh7763_data = {
	.chip_reset	= sh_eth_chip_reset,
	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate_gether,
697

698 699
	.register_type	= SH_ETH_REG_GIGABIT,

700 701 702 703 704
	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
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	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
707 708 709 710 711 712 713 714 715
			  EESR_ECI,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.no_trimd	= 1,
	.no_ade		= 1,
716
	.tsu		= 1,
717
	.irq_flags	= IRQF_SHARED,
718 719
};

720
static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
721 722 723 724 725 726 727
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	/* reset device */
	sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
	mdelay(1);

728
	sh_eth_select_mii(ndev);
729 730 731
}

/* R8A7740 */
732 733
static struct sh_eth_cpu_data r8a7740_data = {
	.chip_reset	= sh_eth_chip_reset_r8a7740,
734
	.set_duplex	= sh_eth_set_duplex,
735
	.set_rate	= sh_eth_set_rate_gether,
736

737 738
	.register_type	= SH_ETH_REG_GIGABIT,

739 740 741 742 743
	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
744 745 746
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
			  EESR_TDE | EESR_ECI,
747
	.fdr_value	= 0x0000070f,
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Sergei Shtylyov 已提交
748
	.rmcr_value	= RMCR_RNC,
749 750 751 752 753 754

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
755 756
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
757 758 759
	.no_trimd	= 1,
	.no_ade		= 1,
	.tsu		= 1,
760
	.select_mii	= 1,
761
	.shift_rd0	= 1,
762 763
};

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764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795
/* R7S72100 */
static struct sh_eth_cpu_data r7s72100_data = {
	.chip_reset	= sh_eth_chip_reset,
	.set_duplex	= sh_eth_set_duplex,

	.register_type	= SH_ETH_REG_FAST_RZ,

	.ecsr_value	= ECSR_ICD,
	.ecsipr_value	= ECSIPR_ICDIP,
	.eesipr_value	= 0xff7f009f,

	.tx_check	= EESR_TC1 | EESR_FTC,
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
			  EESR_TDE | EESR_ECI,
	.fdr_value	= 0x0000070f,
	.rmcr_value	= RMCR_RNC,

	.no_psr		= 1,
	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
	.no_trimd	= 1,
	.no_ade		= 1,
	.hw_crc		= 1,
	.tsu		= 1,
	.shift_rd0	= 1,
};

796
static struct sh_eth_cpu_data sh7619_data = {
797 798
	.register_type	= SH_ETH_REG_FAST_SH3_SH2,

799 800 801 802 803 804 805
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
};
806 807

static struct sh_eth_cpu_data sh771x_data = {
808 809
	.register_type	= SH_ETH_REG_FAST_SH3_SH2,

810
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
811
	.tsu		= 1,
812 813 814 815 816 817 818 819 820 821 822
};

static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
{
	if (!cd->ecsr_value)
		cd->ecsr_value = DEFAULT_ECSR_INIT;

	if (!cd->ecsipr_value)
		cd->ecsipr_value = DEFAULT_ECSIPR_INIT;

	if (!cd->fcftr_value)
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Sergei Shtylyov 已提交
823
		cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
824 825 826 827 828 829 830 831 832 833 834 835 836 837 838
				  DEFAULT_FIFO_F_D_RFD;

	if (!cd->fdr_value)
		cd->fdr_value = DEFAULT_FDR_INIT;

	if (!cd->rmcr_value)
		cd->rmcr_value = DEFAULT_RMCR_VALUE;

	if (!cd->tx_check)
		cd->tx_check = DEFAULT_TX_CHECK;

	if (!cd->eesr_err_check)
		cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
}

839 840 841 842 843 844 845 846 847 848 849
static int sh_eth_check_reset(struct net_device *ndev)
{
	int ret = 0;
	int cnt = 100;

	while (cnt > 0) {
		if (!(sh_eth_read(ndev, EDMR) & 0x3))
			break;
		mdelay(1);
		cnt--;
	}
850 851
	if (cnt <= 0) {
		pr_err("Device reset failed\n");
852 853 854
		ret = -ETIMEDOUT;
	}
	return ret;
855
}
856 857 858 859 860 861

static int sh_eth_reset(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int ret = 0;

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Simon Horman 已提交
862
	if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898
		sh_eth_write(ndev, EDSR_ENALL, EDSR);
		sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
			     EDMR);

		ret = sh_eth_check_reset(ndev);
		if (ret)
			goto out;

		/* Table Init */
		sh_eth_write(ndev, 0x0, TDLAR);
		sh_eth_write(ndev, 0x0, TDFAR);
		sh_eth_write(ndev, 0x0, TDFXR);
		sh_eth_write(ndev, 0x0, TDFFR);
		sh_eth_write(ndev, 0x0, RDLAR);
		sh_eth_write(ndev, 0x0, RDFAR);
		sh_eth_write(ndev, 0x0, RDFXR);
		sh_eth_write(ndev, 0x0, RDFFR);

		/* Reset HW CRC register */
		if (mdp->cd->hw_crc)
			sh_eth_write(ndev, 0x0, CSMR);

		/* Select MII mode */
		if (mdp->cd->select_mii)
			sh_eth_select_mii(ndev);
	} else {
		sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
			     EDMR);
		mdelay(3);
		sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
			     EDMR);
	}

out:
	return ret;
}
899

900
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916
static void sh_eth_set_receive_align(struct sk_buff *skb)
{
	int reserve;

	reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
	if (reserve)
		skb_reserve(skb, reserve);
}
#else
static void sh_eth_set_receive_align(struct sk_buff *skb)
{
	skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
}
#endif


917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939
/* CPU <-> EDMAC endian convert */
static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
{
	switch (mdp->edmac_endian) {
	case EDMAC_LITTLE_ENDIAN:
		return cpu_to_le32(x);
	case EDMAC_BIG_ENDIAN:
		return cpu_to_be32(x);
	}
	return x;
}

static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
{
	switch (mdp->edmac_endian) {
	case EDMAC_LITTLE_ENDIAN:
		return le32_to_cpu(x);
	case EDMAC_BIG_ENDIAN:
		return be32_to_cpu(x);
	}
	return x;
}

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Sergei Shtylyov 已提交
940
/* Program the hardware MAC address from dev->dev_addr. */
941 942
static void update_mac_address(struct net_device *ndev)
{
943
	sh_eth_write(ndev,
S
Sergei Shtylyov 已提交
944 945
		     (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
		     (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
946
	sh_eth_write(ndev,
S
Sergei Shtylyov 已提交
947
		     (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
948 949
}

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950
/* Get MAC address from SuperH MAC address register
951 952 953 954 955 956
 *
 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 * When you want use this device, you must set MAC address in bootloader.
 *
 */
957
static void read_mac_address(struct net_device *ndev, unsigned char *mac)
958
{
959
	if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
960
		memcpy(ndev->dev_addr, mac, ETH_ALEN);
961
	} else {
962 963 964 965 966 967
		ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
		ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
		ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
		ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
		ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
		ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
968
	}
969 970
}

971 972
static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
{
S
Simon Horman 已提交
973
	if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
974 975 976 977 978
		return EDTRR_TRNS_GETHER;
	else
		return EDTRR_TRNS_ETHER;
}

979
struct bb_info {
Y
Yoshihiro Shimoda 已提交
980
	void (*set_gate)(void *addr);
981
	struct mdiobb_ctrl ctrl;
Y
Yoshihiro Shimoda 已提交
982
	void *addr;
983 984 985 986 987 988 989
	u32 mmd_msk;/* MMD */
	u32 mdo_msk;
	u32 mdi_msk;
	u32 mdc_msk;
};

/* PHY bit set */
Y
Yoshihiro Shimoda 已提交
990
static void bb_set(void *addr, u32 msk)
991
{
Y
Yoshihiro Shimoda 已提交
992
	iowrite32(ioread32(addr) | msk, addr);
993 994 995
}

/* PHY bit clear */
Y
Yoshihiro Shimoda 已提交
996
static void bb_clr(void *addr, u32 msk)
997
{
Y
Yoshihiro Shimoda 已提交
998
	iowrite32((ioread32(addr) & ~msk), addr);
999 1000 1001
}

/* PHY bit read */
Y
Yoshihiro Shimoda 已提交
1002
static int bb_read(void *addr, u32 msk)
1003
{
Y
Yoshihiro Shimoda 已提交
1004
	return (ioread32(addr) & msk) != 0;
1005 1006 1007 1008 1009 1010
}

/* Data I/O pin control */
static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1011 1012 1013 1014

	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025
	if (bit)
		bb_set(bitbang->addr, bitbang->mmd_msk);
	else
		bb_clr(bitbang->addr, bitbang->mmd_msk);
}

/* Set bit data*/
static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);

1026 1027 1028
	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

1029 1030 1031 1032 1033 1034 1035 1036 1037 1038
	if (bit)
		bb_set(bitbang->addr, bitbang->mdo_msk);
	else
		bb_clr(bitbang->addr, bitbang->mdo_msk);
}

/* Get bit data*/
static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1039 1040 1041 1042

	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

1043 1044 1045 1046 1047 1048 1049 1050
	return bb_read(bitbang->addr, bitbang->mdi_msk);
}

/* MDC pin control */
static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);

1051 1052 1053
	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076
	if (bit)
		bb_set(bitbang->addr, bitbang->mdc_msk);
	else
		bb_clr(bitbang->addr, bitbang->mdc_msk);
}

/* mdio bus control struct */
static struct mdiobb_ops bb_ops = {
	.owner = THIS_MODULE,
	.set_mdc = sh_mdc_ctrl,
	.set_mdio_dir = sh_mmd_ctrl,
	.set_mdio_data = sh_set_mdio,
	.get_mdio_data = sh_get_mdio,
};

/* free skb and descriptor buffer */
static void sh_eth_ring_free(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i;

	/* Free Rx skb ringbuffer */
	if (mdp->rx_skbuff) {
1077
		for (i = 0; i < mdp->num_rx_ring; i++) {
1078 1079 1080 1081 1082
			if (mdp->rx_skbuff[i])
				dev_kfree_skb(mdp->rx_skbuff[i]);
		}
	}
	kfree(mdp->rx_skbuff);
1083
	mdp->rx_skbuff = NULL;
1084 1085 1086

	/* Free Tx skb ringbuffer */
	if (mdp->tx_skbuff) {
1087
		for (i = 0; i < mdp->num_tx_ring; i++) {
1088 1089 1090 1091 1092
			if (mdp->tx_skbuff[i])
				dev_kfree_skb(mdp->tx_skbuff[i]);
		}
	}
	kfree(mdp->tx_skbuff);
1093
	mdp->tx_skbuff = NULL;
1094 1095 1096 1097 1098 1099 1100 1101 1102 1103
}

/* format skb and descriptor buffer */
static void sh_eth_ring_format(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i;
	struct sk_buff *skb;
	struct sh_eth_rxdesc *rxdesc = NULL;
	struct sh_eth_txdesc *txdesc = NULL;
1104 1105
	int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
	int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1106

S
Sergei Shtylyov 已提交
1107 1108 1109 1110
	mdp->cur_rx = 0;
	mdp->cur_tx = 0;
	mdp->dirty_rx = 0;
	mdp->dirty_tx = 0;
1111 1112 1113 1114

	memset(mdp->rx_ring, 0, rx_ringsize);

	/* build Rx ring buffer */
1115
	for (i = 0; i < mdp->num_rx_ring; i++) {
1116 1117
		/* skb */
		mdp->rx_skbuff[i] = NULL;
1118
		skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1119 1120 1121
		mdp->rx_skbuff[i] = skb;
		if (skb == NULL)
			break;
1122
		dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
S
Sergei Shtylyov 已提交
1123
			       DMA_FROM_DEVICE);
1124 1125
		sh_eth_set_receive_align(skb);

1126 1127
		/* RX descriptor */
		rxdesc = &mdp->rx_ring[i];
1128
		rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1129
		rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1130 1131

		/* The size of the buffer is 16 byte boundary. */
1132
		rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1133 1134
		/* Rx descriptor address set */
		if (i == 0) {
1135
			sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
S
Simon Horman 已提交
1136 1137
			if (sh_eth_is_gether(mdp) ||
			    sh_eth_is_rz_fast_ether(mdp))
1138
				sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1139
		}
1140 1141
	}

1142
	mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1143 1144

	/* Mark the last entry as wrapping the ring. */
1145
	rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1146 1147 1148 1149

	memset(mdp->tx_ring, 0, tx_ringsize);

	/* build Tx ring buffer */
1150
	for (i = 0; i < mdp->num_tx_ring; i++) {
1151 1152
		mdp->tx_skbuff[i] = NULL;
		txdesc = &mdp->tx_ring[i];
1153
		txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1154
		txdesc->buffer_length = 0;
1155
		if (i == 0) {
1156
			/* Tx descriptor address set */
1157
			sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
S
Simon Horman 已提交
1158 1159
			if (sh_eth_is_gether(mdp) ||
			    sh_eth_is_rz_fast_ether(mdp))
1160
				sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1161
		}
1162 1163
	}

1164
	txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1165 1166 1167 1168 1169 1170 1171 1172
}

/* Get skb and descriptor buffer */
static int sh_eth_ring_init(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int rx_ringsize, tx_ringsize, ret = 0;

S
Sergei Shtylyov 已提交
1173
	/* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1174 1175 1176 1177 1178 1179
	 * card needs room to do 8 byte alignment, +2 so we can reserve
	 * the first 2 bytes, and +16 gets room for the status word from the
	 * card.
	 */
	mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
			  (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1180 1181
	if (mdp->cd->rpadir)
		mdp->rx_buf_sz += NET_IP_ALIGN;
1182 1183

	/* Allocate RX and TX skb rings */
1184 1185
	mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
				       sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1186 1187 1188 1189 1190
	if (!mdp->rx_skbuff) {
		ret = -ENOMEM;
		return ret;
	}

1191 1192
	mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
				       sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1193 1194 1195 1196 1197 1198
	if (!mdp->tx_skbuff) {
		ret = -ENOMEM;
		goto skb_ring_free;
	}

	/* Allocate all Rx descriptors. */
1199
	rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1200
	mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1201
					  GFP_KERNEL);
1202 1203 1204 1205 1206 1207 1208 1209
	if (!mdp->rx_ring) {
		ret = -ENOMEM;
		goto desc_ring_free;
	}

	mdp->dirty_rx = 0;

	/* Allocate all Tx descriptors. */
1210
	tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1211
	mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1212
					  GFP_KERNEL);
1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225
	if (!mdp->tx_ring) {
		ret = -ENOMEM;
		goto desc_ring_free;
	}
	return ret;

desc_ring_free:
	/* free DMA buffer */
	dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);

skb_ring_free:
	/* Free Rx and Tx skb ring buffer */
	sh_eth_ring_free(ndev);
1226 1227
	mdp->tx_ring = NULL;
	mdp->rx_ring = NULL;
1228 1229 1230 1231

	return ret;
}

1232 1233 1234 1235 1236
static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
{
	int ringsize;

	if (mdp->rx_ring) {
1237
		ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1238 1239 1240 1241 1242 1243
		dma_free_coherent(NULL, ringsize, mdp->rx_ring,
				  mdp->rx_desc_dma);
		mdp->rx_ring = NULL;
	}

	if (mdp->tx_ring) {
1244
		ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1245 1246 1247 1248 1249 1250
		dma_free_coherent(NULL, ringsize, mdp->tx_ring,
				  mdp->tx_desc_dma);
		mdp->tx_ring = NULL;
	}
}

1251
static int sh_eth_dev_init(struct net_device *ndev, bool start)
1252 1253 1254 1255 1256 1257
{
	int ret = 0;
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 val;

	/* Soft Reset */
1258 1259 1260
	ret = sh_eth_reset(ndev);
	if (ret)
		goto out;
1261

1262 1263 1264
	if (mdp->cd->rmiimode)
		sh_eth_write(ndev, 0x1, RMIIMODE);

1265 1266
	/* Descriptor format */
	sh_eth_ring_format(ndev);
1267
	if (mdp->cd->rpadir)
1268
		sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1269 1270

	/* all sh_eth int mask */
1271
	sh_eth_write(ndev, 0, EESIPR);
1272

1273
#if defined(__LITTLE_ENDIAN)
1274
	if (mdp->cd->hw_swap)
1275
		sh_eth_write(ndev, EDMR_EL, EDMR);
1276
	else
1277
#endif
1278
		sh_eth_write(ndev, 0, EDMR);
1279

1280
	/* FIFO size set */
1281 1282
	sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
	sh_eth_write(ndev, 0, TFTR);
1283

1284
	/* Frame recv control */
1285
	sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1286

1287
	sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1288

1289
	if (mdp->cd->bculr)
1290
		sh_eth_write(ndev, 0x800, BCULR);	/* Burst sycle set */
1291

1292
	sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1293

1294
	if (!mdp->cd->no_trimd)
1295
		sh_eth_write(ndev, 0, TRIMD);
1296

1297
	/* Recv frame limit set register */
1298 1299
	sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
		     RFLR);
1300

1301
	sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1302 1303
	if (start)
		sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1304 1305

	/* PAUSE Prohibition */
1306
	val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1307 1308
		ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;

1309
	sh_eth_write(ndev, val, ECMR);
1310

1311 1312 1313
	if (mdp->cd->set_rate)
		mdp->cd->set_rate(ndev);

1314
	/* E-MAC Status Register clear */
1315
	sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1316 1317

	/* E-MAC Interrupt Enable register */
1318 1319
	if (start)
		sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1320 1321 1322 1323 1324

	/* Set MAC address */
	update_mac_address(ndev);

	/* mask reset */
1325
	if (mdp->cd->apr)
1326
		sh_eth_write(ndev, APR_AP, APR);
1327
	if (mdp->cd->mpr)
1328
		sh_eth_write(ndev, MPR_MP, MPR);
1329
	if (mdp->cd->tpauser)
1330
		sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1331

1332 1333 1334
	if (start) {
		/* Setting the Rx mode will start the Rx process. */
		sh_eth_write(ndev, EDRRR_R, EDRRR);
1335

1336 1337
		netif_start_queue(ndev);
	}
1338

1339
out:
1340 1341 1342 1343 1344 1345 1346 1347
	return ret;
}

/* free Tx skb function */
static int sh_eth_txfree(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_txdesc *txdesc;
S
Sergei Shtylyov 已提交
1348
	int free_num = 0;
1349 1350 1351
	int entry = 0;

	for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1352
		entry = mdp->dirty_tx % mdp->num_tx_ring;
1353
		txdesc = &mdp->tx_ring[entry];
1354
		if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1355 1356 1357
			break;
		/* Free the original skb. */
		if (mdp->tx_skbuff[entry]) {
1358 1359
			dma_unmap_single(&ndev->dev, txdesc->addr,
					 txdesc->buffer_length, DMA_TO_DEVICE);
1360 1361
			dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
			mdp->tx_skbuff[entry] = NULL;
S
Sergei Shtylyov 已提交
1362
			free_num++;
1363
		}
1364
		txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1365
		if (entry >= mdp->num_tx_ring - 1)
1366
			txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1367

1368 1369
		ndev->stats.tx_packets++;
		ndev->stats.tx_bytes += txdesc->buffer_length;
1370
	}
S
Sergei Shtylyov 已提交
1371
	return free_num;
1372 1373 1374
}

/* Packet receive function */
S
Sergei Shtylyov 已提交
1375
static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1376 1377 1378 1379
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_rxdesc *rxdesc;

1380 1381
	int entry = mdp->cur_rx % mdp->num_rx_ring;
	int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1382
	struct sk_buff *skb;
S
Sergei Shtylyov 已提交
1383
	int exceeded = 0;
1384
	u16 pkt_len = 0;
1385
	u32 desc_status;
1386 1387

	rxdesc = &mdp->rx_ring[entry];
1388 1389
	while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
		desc_status = edmac_to_cpu(mdp, rxdesc->status);
1390 1391 1392 1393 1394
		pkt_len = rxdesc->frame_length;

		if (--boguscnt < 0)
			break;

S
Sergei Shtylyov 已提交
1395 1396 1397 1398 1399 1400
		if (*quota <= 0) {
			exceeded = 1;
			break;
		}
		(*quota)--;

1401
		if (!(desc_status & RDFEND))
1402
			ndev->stats.rx_length_errors++;
1403

S
Sergei Shtylyov 已提交
1404
		/* In case of almost all GETHER/ETHERs, the Receive Frame State
1405
		 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
S
Simon Horman 已提交
1406 1407 1408
		 * bit 0. However, in case of the R8A7740, R8A779x, and
		 * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
		 * driver needs right shifting by 16.
1409
		 */
1410 1411
		if (mdp->cd->shift_rd0)
			desc_status >>= 16;
1412

1413 1414
		if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
				   RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1415
			ndev->stats.rx_errors++;
1416
			if (desc_status & RD_RFS1)
1417
				ndev->stats.rx_crc_errors++;
1418
			if (desc_status & RD_RFS2)
1419
				ndev->stats.rx_frame_errors++;
1420
			if (desc_status & RD_RFS3)
1421
				ndev->stats.rx_length_errors++;
1422
			if (desc_status & RD_RFS4)
1423
				ndev->stats.rx_length_errors++;
1424
			if (desc_status & RD_RFS6)
1425
				ndev->stats.rx_missed_errors++;
1426
			if (desc_status & RD_RFS10)
1427
				ndev->stats.rx_over_errors++;
1428
		} else {
1429 1430 1431 1432
			if (!mdp->cd->hw_swap)
				sh_eth_soft_swap(
					phys_to_virt(ALIGN(rxdesc->addr, 4)),
					pkt_len + 2);
1433 1434
			skb = mdp->rx_skbuff[entry];
			mdp->rx_skbuff[entry] = NULL;
1435 1436
			if (mdp->cd->rpadir)
				skb_reserve(skb, NET_IP_ALIGN);
1437 1438 1439
			dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
						mdp->rx_buf_sz,
						DMA_FROM_DEVICE);
1440 1441
			skb_put(skb, pkt_len);
			skb->protocol = eth_type_trans(skb, ndev);
1442
			netif_receive_skb(skb);
1443 1444
			ndev->stats.rx_packets++;
			ndev->stats.rx_bytes += pkt_len;
1445
		}
1446
		rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1447
		entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1448
		rxdesc = &mdp->rx_ring[entry];
1449 1450 1451 1452
	}

	/* Refill the Rx ring buffers. */
	for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1453
		entry = mdp->dirty_rx % mdp->num_rx_ring;
1454
		rxdesc = &mdp->rx_ring[entry];
1455
		/* The size of the buffer is 16 byte boundary. */
1456
		rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1457

1458
		if (mdp->rx_skbuff[entry] == NULL) {
1459
			skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1460 1461 1462
			mdp->rx_skbuff[entry] = skb;
			if (skb == NULL)
				break;	/* Better luck next round. */
1463
			dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
S
Sergei Shtylyov 已提交
1464
				       DMA_FROM_DEVICE);
1465 1466
			sh_eth_set_receive_align(skb);

1467
			skb_checksum_none_assert(skb);
1468
			rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1469
		}
1470
		if (entry >= mdp->num_rx_ring - 1)
1471
			rxdesc->status |=
1472
				cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1473 1474
		else
			rxdesc->status |=
1475
				cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1476 1477 1478 1479
	}

	/* Restart Rx engine if stopped. */
	/* If we don't need to check status, don't. -KDU */
1480
	if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1481
		/* fix the values for the next receiving if RDE is set */
S
Sergei Shtylyov 已提交
1482 1483 1484 1485 1486 1487 1488
		if (intr_status & EESR_RDE) {
			u32 count = (sh_eth_read(ndev, RDFAR) -
				     sh_eth_read(ndev, RDLAR)) >> 4;

			mdp->cur_rx = count;
			mdp->dirty_rx = count;
		}
1489
		sh_eth_write(ndev, EDRRR_R, EDRRR);
1490
	}
1491

S
Sergei Shtylyov 已提交
1492
	return exceeded;
1493 1494
}

1495
static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1496 1497
{
	/* disable tx and rx */
1498 1499
	sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
		~(ECMR_RE | ECMR_TE), ECMR);
1500 1501
}

1502
static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1503 1504
{
	/* enable tx and rx */
1505 1506
	sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
		(ECMR_RE | ECMR_TE), ECMR);
1507 1508
}

1509 1510 1511 1512 1513
/* error control function */
static void sh_eth_error(struct net_device *ndev, int intr_status)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 felic_stat;
1514 1515
	u32 link_stat;
	u32 mask;
1516 1517

	if (intr_status & EESR_ECI) {
1518 1519
		felic_stat = sh_eth_read(ndev, ECSR);
		sh_eth_write(ndev, felic_stat, ECSR);	/* clear int */
1520
		if (felic_stat & ECSR_ICD)
1521
			ndev->stats.tx_carrier_errors++;
1522 1523
		if (felic_stat & ECSR_LCHNG) {
			/* Link Changed */
1524
			if (mdp->cd->no_psr || mdp->no_ether_link) {
1525
				goto ignore_link;
1526
			} else {
1527
				link_stat = (sh_eth_read(ndev, PSR));
1528 1529
				if (mdp->ether_link_active_low)
					link_stat = ~link_stat;
1530
			}
S
Sergei Shtylyov 已提交
1531
			if (!(link_stat & PHY_ST_LINK)) {
1532
				sh_eth_rcv_snd_disable(ndev);
S
Sergei Shtylyov 已提交
1533
			} else {
1534
				/* Link Up */
1535
				sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
S
Sergei Shtylyov 已提交
1536 1537
						   ~DMAC_M_ECI, EESIPR);
				/* clear int */
1538
				sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
S
Sergei Shtylyov 已提交
1539
					     ECSR);
1540
				sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
S
Sergei Shtylyov 已提交
1541
						   DMAC_M_ECI, EESIPR);
1542
				/* enable tx and rx */
1543
				sh_eth_rcv_snd_enable(ndev);
1544 1545 1546 1547
			}
		}
	}

1548
ignore_link:
1549
	if (intr_status & EESR_TWB) {
1550 1551
		/* Unused write back interrupt */
		if (intr_status & EESR_TABT) {	/* Transmit Abort int */
1552
			ndev->stats.tx_aborted_errors++;
1553 1554
			if (netif_msg_tx_err(mdp))
				dev_err(&ndev->dev, "Transmit Abort\n");
1555
		}
1556 1557 1558 1559 1560 1561
	}

	if (intr_status & EESR_RABT) {
		/* Receive Abort int */
		if (intr_status & EESR_RFRMER) {
			/* Receive Frame Overflow int */
1562
			ndev->stats.rx_frame_errors++;
1563 1564
			if (netif_msg_rx_err(mdp))
				dev_err(&ndev->dev, "Receive Abort\n");
1565 1566
		}
	}
1567

1568 1569
	if (intr_status & EESR_TDE) {
		/* Transmit Descriptor Empty int */
1570
		ndev->stats.tx_fifo_errors++;
1571 1572 1573 1574 1575 1576
		if (netif_msg_tx_err(mdp))
			dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
	}

	if (intr_status & EESR_TFE) {
		/* FIFO under flow */
1577
		ndev->stats.tx_fifo_errors++;
1578 1579
		if (netif_msg_tx_err(mdp))
			dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1580 1581 1582 1583
	}

	if (intr_status & EESR_RDE) {
		/* Receive Descriptor Empty int */
1584
		ndev->stats.rx_over_errors++;
1585

1586 1587
		if (netif_msg_rx_err(mdp))
			dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1588
	}
1589

1590 1591
	if (intr_status & EESR_RFE) {
		/* Receive FIFO Overflow int */
1592
		ndev->stats.rx_fifo_errors++;
1593 1594 1595 1596 1597 1598
		if (netif_msg_rx_err(mdp))
			dev_err(&ndev->dev, "Receive FIFO Overflow\n");
	}

	if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
		/* Address Error */
1599
		ndev->stats.tx_fifo_errors++;
1600 1601
		if (netif_msg_tx_err(mdp))
			dev_err(&ndev->dev, "Address Error\n");
1602
	}
1603 1604 1605 1606 1607

	mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
	if (mdp->cd->no_ade)
		mask &= ~EESR_ADE;
	if (intr_status & mask) {
1608
		/* Tx error */
1609
		u32 edtrr = sh_eth_read(ndev, EDTRR);
1610

1611
		/* dmesg */
1612 1613 1614
		dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
			intr_status, mdp->cur_tx, mdp->dirty_tx,
			(u32)ndev->state, edtrr);
1615 1616 1617 1618
		/* dirty buffer free */
		sh_eth_txfree(ndev);

		/* SH7712 BUG */
1619
		if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1620
			/* tx dma start */
1621
			sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1622 1623 1624 1625 1626 1627 1628 1629 1630 1631
		}
		/* wakeup */
		netif_wake_queue(ndev);
	}
}

static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
{
	struct net_device *ndev = netdev;
	struct sh_eth_private *mdp = netdev_priv(ndev);
1632
	struct sh_eth_cpu_data *cd = mdp->cd;
1633
	irqreturn_t ret = IRQ_NONE;
S
Sergei Shtylyov 已提交
1634
	unsigned long intr_status, intr_enable;
1635 1636 1637

	spin_lock(&mdp->lock);

1638
	/* Get interrupt status */
1639
	intr_status = sh_eth_read(ndev, EESR);
1640 1641 1642 1643 1644
	/* Mask it with the interrupt mask, forcing ECI interrupt to be always
	 * enabled since it's the one that  comes thru regardless of the mask,
	 * and we need to fully handle it in sh_eth_error() in order to quench
	 * it as it doesn't get cleared by just writing 1 to the ECI bit...
	 */
S
Sergei Shtylyov 已提交
1645 1646 1647
	intr_enable = sh_eth_read(ndev, EESIPR);
	intr_status &= intr_enable | DMAC_M_ECI;
	if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1648
		ret = IRQ_HANDLED;
S
Sergei Shtylyov 已提交
1649
	else
1650
		goto other_irq;
1651

S
Sergei Shtylyov 已提交
1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663
	if (intr_status & EESR_RX_CHECK) {
		if (napi_schedule_prep(&mdp->napi)) {
			/* Mask Rx interrupts */
			sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
				     EESIPR);
			__napi_schedule(&mdp->napi);
		} else {
			dev_warn(&ndev->dev,
				 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
				 intr_status, intr_enable);
		}
	}
1664

1665
	/* Tx Check */
1666
	if (intr_status & cd->tx_check) {
S
Sergei Shtylyov 已提交
1667 1668 1669
		/* Clear Tx interrupts */
		sh_eth_write(ndev, intr_status & cd->tx_check, EESR);

1670 1671 1672 1673
		sh_eth_txfree(ndev);
		netif_wake_queue(ndev);
	}

S
Sergei Shtylyov 已提交
1674 1675 1676 1677
	if (intr_status & cd->eesr_err_check) {
		/* Clear error interrupts */
		sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);

1678
		sh_eth_error(ndev, intr_status);
S
Sergei Shtylyov 已提交
1679
	}
1680

1681
other_irq:
1682 1683
	spin_unlock(&mdp->lock);

1684
	return ret;
1685 1686
}

S
Sergei Shtylyov 已提交
1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713
static int sh_eth_poll(struct napi_struct *napi, int budget)
{
	struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
						  napi);
	struct net_device *ndev = napi->dev;
	int quota = budget;
	unsigned long intr_status;

	for (;;) {
		intr_status = sh_eth_read(ndev, EESR);
		if (!(intr_status & EESR_RX_CHECK))
			break;
		/* Clear Rx interrupts */
		sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);

		if (sh_eth_rx(ndev, intr_status, &quota))
			goto out;
	}

	napi_complete(napi);

	/* Reenable Rx interrupts */
	sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
out:
	return budget - quota;
}

1714 1715 1716 1717 1718 1719 1720
/* PHY state control function */
static void sh_eth_adjust_link(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct phy_device *phydev = mdp->phydev;
	int new_state = 0;

1721
	if (phydev->link) {
1722 1723 1724
		if (phydev->duplex != mdp->duplex) {
			new_state = 1;
			mdp->duplex = phydev->duplex;
1725 1726
			if (mdp->cd->set_duplex)
				mdp->cd->set_duplex(ndev);
1727 1728 1729 1730 1731
		}

		if (phydev->speed != mdp->speed) {
			new_state = 1;
			mdp->speed = phydev->speed;
1732 1733
			if (mdp->cd->set_rate)
				mdp->cd->set_rate(ndev);
1734
		}
1735
		if (!mdp->link) {
1736
			sh_eth_write(ndev,
S
Sergei Shtylyov 已提交
1737 1738
				     sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
				     ECMR);
1739 1740
			new_state = 1;
			mdp->link = phydev->link;
1741 1742
			if (mdp->cd->no_psr || mdp->no_ether_link)
				sh_eth_rcv_snd_enable(ndev);
1743 1744 1745
		}
	} else if (mdp->link) {
		new_state = 1;
1746
		mdp->link = 0;
1747 1748
		mdp->speed = 0;
		mdp->duplex = -1;
1749 1750
		if (mdp->cd->no_psr || mdp->no_ether_link)
			sh_eth_rcv_snd_disable(ndev);
1751 1752
	}

1753
	if (new_state && netif_msg_link(mdp))
1754 1755 1756 1757 1758 1759 1760
		phy_print_status(phydev);
}

/* PHY init function */
static int sh_eth_phy_init(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
1761
	char phy_id[MII_BUS_ID_SIZE + 3];
1762 1763
	struct phy_device *phydev = NULL;

1764
	snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
S
Sergei Shtylyov 已提交
1765
		 mdp->mii_bus->id, mdp->phy_id);
1766

1767
	mdp->link = 0;
1768 1769 1770 1771
	mdp->speed = 0;
	mdp->duplex = -1;

	/* Try connect to PHY */
1772
	phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1773
			     mdp->phy_interface);
1774 1775 1776 1777
	if (IS_ERR(phydev)) {
		dev_err(&ndev->dev, "phy_connect failed\n");
		return PTR_ERR(phydev);
	}
1778

1779 1780
	dev_info(&ndev->dev, "attached PHY %d (IRQ %d) to driver %s\n",
		 phydev->addr, phydev->irq, phydev->drv->name);
1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801

	mdp->phydev = phydev;

	return 0;
}

/* PHY control start function */
static int sh_eth_phy_start(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int ret;

	ret = sh_eth_phy_init(ndev);
	if (ret)
		return ret;

	phy_start(mdp->phydev);

	return 0;
}

1802
static int sh_eth_get_settings(struct net_device *ndev,
S
Sergei Shtylyov 已提交
1803
			       struct ethtool_cmd *ecmd)
1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&mdp->lock, flags);
	ret = phy_ethtool_gset(mdp->phydev, ecmd);
	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

static int sh_eth_set_settings(struct net_device *ndev,
S
Sergei Shtylyov 已提交
1817
			       struct ethtool_cmd *ecmd)
1818 1819 1820 1821 1822 1823 1824 1825
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&mdp->lock, flags);

	/* disable tx and rx */
1826
	sh_eth_rcv_snd_disable(ndev);
1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843

	ret = phy_ethtool_sset(mdp->phydev, ecmd);
	if (ret)
		goto error_exit;

	if (ecmd->duplex == DUPLEX_FULL)
		mdp->duplex = 1;
	else
		mdp->duplex = 0;

	if (mdp->cd->set_duplex)
		mdp->cd->set_duplex(ndev);

error_exit:
	mdelay(1);

	/* enable tx and rx */
1844
	sh_eth_rcv_snd_enable(ndev);
1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892

	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

static int sh_eth_nway_reset(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&mdp->lock, flags);
	ret = phy_start_aneg(mdp->phydev);
	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

static u32 sh_eth_get_msglevel(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	return mdp->msg_enable;
}

static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	mdp->msg_enable = value;
}

static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
	"rx_current", "tx_current",
	"rx_dirty", "tx_dirty",
};
#define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)

static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
{
	switch (sset) {
	case ETH_SS_STATS:
		return SH_ETH_STATS_LEN;
	default:
		return -EOPNOTSUPP;
	}
}

static void sh_eth_get_ethtool_stats(struct net_device *ndev,
S
Sergei Shtylyov 已提交
1893
				     struct ethtool_stats *stats, u64 *data)
1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i = 0;

	/* device-specific stats */
	data[i++] = mdp->cur_rx;
	data[i++] = mdp->cur_tx;
	data[i++] = mdp->dirty_rx;
	data[i++] = mdp->dirty_tx;
}

static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
{
	switch (stringset) {
	case ETH_SS_STATS:
		memcpy(data, *sh_eth_gstrings_stats,
S
Sergei Shtylyov 已提交
1910
		       sizeof(sh_eth_gstrings_stats));
1911 1912 1913 1914
		break;
	}
}

1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979
static void sh_eth_get_ringparam(struct net_device *ndev,
				 struct ethtool_ringparam *ring)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	ring->rx_max_pending = RX_RING_MAX;
	ring->tx_max_pending = TX_RING_MAX;
	ring->rx_pending = mdp->num_rx_ring;
	ring->tx_pending = mdp->num_tx_ring;
}

static int sh_eth_set_ringparam(struct net_device *ndev,
				struct ethtool_ringparam *ring)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int ret;

	if (ring->tx_pending > TX_RING_MAX ||
	    ring->rx_pending > RX_RING_MAX ||
	    ring->tx_pending < TX_RING_MIN ||
	    ring->rx_pending < RX_RING_MIN)
		return -EINVAL;
	if (ring->rx_mini_pending || ring->rx_jumbo_pending)
		return -EINVAL;

	if (netif_running(ndev)) {
		netif_tx_disable(ndev);
		/* Disable interrupts by clearing the interrupt mask. */
		sh_eth_write(ndev, 0x0000, EESIPR);
		/* Stop the chip's Tx and Rx processes. */
		sh_eth_write(ndev, 0, EDTRR);
		sh_eth_write(ndev, 0, EDRRR);
		synchronize_irq(ndev->irq);
	}

	/* Free all the skbuffs in the Rx queue. */
	sh_eth_ring_free(ndev);
	/* Free DMA buffer */
	sh_eth_free_dma_buffer(mdp);

	/* Set new parameters */
	mdp->num_rx_ring = ring->rx_pending;
	mdp->num_tx_ring = ring->tx_pending;

	ret = sh_eth_ring_init(ndev);
	if (ret < 0) {
		dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
		return ret;
	}
	ret = sh_eth_dev_init(ndev, false);
	if (ret < 0) {
		dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
		return ret;
	}

	if (netif_running(ndev)) {
		sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
		/* Setting the Rx mode will start the Rx process. */
		sh_eth_write(ndev, EDRRR_R, EDRRR);
		netif_wake_queue(ndev);
	}

	return 0;
}

S
stephen hemminger 已提交
1980
static const struct ethtool_ops sh_eth_ethtool_ops = {
1981 1982
	.get_settings	= sh_eth_get_settings,
	.set_settings	= sh_eth_set_settings,
S
stephen hemminger 已提交
1983
	.nway_reset	= sh_eth_nway_reset,
1984 1985
	.get_msglevel	= sh_eth_get_msglevel,
	.set_msglevel	= sh_eth_set_msglevel,
S
stephen hemminger 已提交
1986
	.get_link	= ethtool_op_get_link,
1987 1988 1989
	.get_strings	= sh_eth_get_strings,
	.get_ethtool_stats  = sh_eth_get_ethtool_stats,
	.get_sset_count     = sh_eth_get_sset_count,
1990 1991
	.get_ringparam	= sh_eth_get_ringparam,
	.set_ringparam	= sh_eth_set_ringparam,
1992 1993
};

1994 1995 1996 1997 1998 1999
/* network device open function */
static int sh_eth_open(struct net_device *ndev)
{
	int ret = 0;
	struct sh_eth_private *mdp = netdev_priv(ndev);

2000 2001
	pm_runtime_get_sync(&mdp->pdev->dev);

2002 2003
	napi_enable(&mdp->napi);

2004
	ret = request_irq(ndev->irq, sh_eth_interrupt,
2005
			  mdp->cd->irq_flags, ndev->name, ndev);
2006
	if (ret) {
2007
		dev_err(&ndev->dev, "Can not assign IRQ number\n");
2008
		goto out_napi_off;
2009 2010 2011 2012 2013 2014 2015 2016
	}

	/* Descriptor set */
	ret = sh_eth_ring_init(ndev);
	if (ret)
		goto out_free_irq;

	/* device init */
2017
	ret = sh_eth_dev_init(ndev, true);
2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029
	if (ret)
		goto out_free_irq;

	/* PHY control start*/
	ret = sh_eth_phy_start(ndev);
	if (ret)
		goto out_free_irq;

	return ret;

out_free_irq:
	free_irq(ndev->irq, ndev);
2030 2031
out_napi_off:
	napi_disable(&mdp->napi);
2032
	pm_runtime_put_sync(&mdp->pdev->dev);
2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044
	return ret;
}

/* Timeout function */
static void sh_eth_tx_timeout(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_rxdesc *rxdesc;
	int i;

	netif_stop_queue(ndev);

S
Sergei Shtylyov 已提交
2045 2046 2047 2048
	if (netif_msg_timer(mdp)) {
		dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x, resetting...\n",
			ndev->name, (int)sh_eth_read(ndev, EESR));
	}
2049 2050

	/* tx_errors count up */
2051
	ndev->stats.tx_errors++;
2052 2053

	/* Free all the skbuffs in the Rx queue. */
2054
	for (i = 0; i < mdp->num_rx_ring; i++) {
2055 2056 2057 2058 2059 2060 2061
		rxdesc = &mdp->rx_ring[i];
		rxdesc->status = 0;
		rxdesc->addr = 0xBADF00D0;
		if (mdp->rx_skbuff[i])
			dev_kfree_skb(mdp->rx_skbuff[i]);
		mdp->rx_skbuff[i] = NULL;
	}
2062
	for (i = 0; i < mdp->num_tx_ring; i++) {
2063 2064 2065 2066 2067 2068
		if (mdp->tx_skbuff[i])
			dev_kfree_skb(mdp->tx_skbuff[i]);
		mdp->tx_skbuff[i] = NULL;
	}

	/* device init */
2069
	sh_eth_dev_init(ndev, true);
2070 2071 2072 2073 2074 2075 2076 2077
}

/* Packet transmit function */
static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_txdesc *txdesc;
	u32 entry;
2078
	unsigned long flags;
2079 2080

	spin_lock_irqsave(&mdp->lock, flags);
2081
	if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2082
		if (!sh_eth_txfree(ndev)) {
2083 2084
			if (netif_msg_tx_queued(mdp))
				dev_warn(&ndev->dev, "TxFD exhausted.\n");
2085 2086
			netif_stop_queue(ndev);
			spin_unlock_irqrestore(&mdp->lock, flags);
2087
			return NETDEV_TX_BUSY;
2088 2089 2090 2091
		}
	}
	spin_unlock_irqrestore(&mdp->lock, flags);

2092
	entry = mdp->cur_tx % mdp->num_tx_ring;
2093 2094 2095
	mdp->tx_skbuff[entry] = skb;
	txdesc = &mdp->tx_ring[entry];
	/* soft swap. */
2096 2097 2098
	if (!mdp->cd->hw_swap)
		sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
				 skb->len + 2);
2099 2100
	txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
				      DMA_TO_DEVICE);
2101 2102 2103 2104 2105
	if (skb->len < ETHERSMALL)
		txdesc->buffer_length = ETHERSMALL;
	else
		txdesc->buffer_length = skb->len;

2106
	if (entry >= mdp->num_tx_ring - 1)
2107
		txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2108
	else
2109
		txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2110 2111 2112

	mdp->cur_tx++;

2113 2114
	if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
		sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2115

2116
	return NETDEV_TX_OK;
2117 2118 2119 2120 2121 2122 2123 2124 2125 2126
}

/* device close function */
static int sh_eth_close(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	netif_stop_queue(ndev);

	/* Disable interrupts by clearing the interrupt mask. */
2127
	sh_eth_write(ndev, 0x0000, EESIPR);
2128 2129

	/* Stop the chip's Tx and Rx processes. */
2130 2131
	sh_eth_write(ndev, 0, EDTRR);
	sh_eth_write(ndev, 0, EDRRR);
2132 2133 2134 2135 2136 2137 2138 2139 2140

	/* PHY Disconnect */
	if (mdp->phydev) {
		phy_stop(mdp->phydev);
		phy_disconnect(mdp->phydev);
	}

	free_irq(ndev->irq, ndev);

2141 2142
	napi_disable(&mdp->napi);

2143 2144 2145 2146
	/* Free all the skbuffs in the Rx queue. */
	sh_eth_ring_free(ndev);

	/* free DMA buffer */
2147
	sh_eth_free_dma_buffer(mdp);
2148

2149 2150
	pm_runtime_put_sync(&mdp->pdev->dev);

2151 2152 2153 2154 2155 2156 2157
	return 0;
}

static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

S
Simon Horman 已提交
2158 2159 2160
	if (sh_eth_is_rz_fast_ether(mdp))
		return &ndev->stats;

2161 2162
	pm_runtime_get_sync(&mdp->pdev->dev);

2163
	ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2164
	sh_eth_write(ndev, 0, TROCR);	/* (write clear) */
2165
	ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2166
	sh_eth_write(ndev, 0, CDCR);	/* (write clear) */
2167
	ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2168
	sh_eth_write(ndev, 0, LCCR);	/* (write clear) */
2169
	if (sh_eth_is_gether(mdp)) {
2170
		ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2171
		sh_eth_write(ndev, 0, CERCR);	/* (write clear) */
2172
		ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2173 2174
		sh_eth_write(ndev, 0, CEECR);	/* (write clear) */
	} else {
2175
		ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2176 2177
		sh_eth_write(ndev, 0, CNDCR);	/* (write clear) */
	}
2178 2179
	pm_runtime_put_sync(&mdp->pdev->dev);

2180
	return &ndev->stats;
2181 2182
}

2183
/* ioctl to device function */
S
Sergei Shtylyov 已提交
2184
static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2185 2186 2187 2188 2189 2190 2191 2192 2193 2194
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct phy_device *phydev = mdp->phydev;

	if (!netif_running(ndev))
		return -EINVAL;

	if (!phydev)
		return -ENODEV;

2195
	return phy_mii_ioctl(phydev, rq, cmd);
2196 2197
}

2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303
/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
					    int entry)
{
	return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
}

static u32 sh_eth_tsu_get_post_mask(int entry)
{
	return 0x0f << (28 - ((entry % 8) * 4));
}

static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
{
	return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
}

static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
					     int entry)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 tmp;
	void *reg_offset;

	reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
	tmp = ioread32(reg_offset);
	iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
}

static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
					      int entry)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 post_mask, ref_mask, tmp;
	void *reg_offset;

	reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
	post_mask = sh_eth_tsu_get_post_mask(entry);
	ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;

	tmp = ioread32(reg_offset);
	iowrite32(tmp & ~post_mask, reg_offset);

	/* If other port enables, the function returns "true" */
	return tmp & ref_mask;
}

static int sh_eth_tsu_busy(struct net_device *ndev)
{
	int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
	struct sh_eth_private *mdp = netdev_priv(ndev);

	while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
		udelay(10);
		timeout--;
		if (timeout <= 0) {
			dev_err(&ndev->dev, "%s: timeout\n", __func__);
			return -ETIMEDOUT;
		}
	}

	return 0;
}

static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
				  const u8 *addr)
{
	u32 val;

	val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
	iowrite32(val, reg);
	if (sh_eth_tsu_busy(ndev) < 0)
		return -EBUSY;

	val = addr[4] << 8 | addr[5];
	iowrite32(val, reg + 4);
	if (sh_eth_tsu_busy(ndev) < 0)
		return -EBUSY;

	return 0;
}

static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
{
	u32 val;

	val = ioread32(reg);
	addr[0] = (val >> 24) & 0xff;
	addr[1] = (val >> 16) & 0xff;
	addr[2] = (val >> 8) & 0xff;
	addr[3] = val & 0xff;
	val = ioread32(reg + 4);
	addr[4] = (val >> 8) & 0xff;
	addr[5] = val & 0xff;
}


static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int i;
	u8 c_addr[ETH_ALEN];

	for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
		sh_eth_tsu_read_entry(reg_offset, c_addr);
2304
		if (ether_addr_equal(addr, c_addr))
2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429
			return i;
	}

	return -ENOENT;
}

static int sh_eth_tsu_find_empty(struct net_device *ndev)
{
	u8 blank[ETH_ALEN];
	int entry;

	memset(blank, 0, sizeof(blank));
	entry = sh_eth_tsu_find_entry(ndev, blank);
	return (entry < 0) ? -ENOMEM : entry;
}

static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
					      int entry)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int ret;
	u8 blank[ETH_ALEN];

	sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
			 ~(1 << (31 - entry)), TSU_TEN);

	memset(blank, 0, sizeof(blank));
	ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
	if (ret < 0)
		return ret;
	return 0;
}

static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int i, ret;

	if (!mdp->cd->tsu)
		return 0;

	i = sh_eth_tsu_find_entry(ndev, addr);
	if (i < 0) {
		/* No entry found, create one */
		i = sh_eth_tsu_find_empty(ndev);
		if (i < 0)
			return -ENOMEM;
		ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
		if (ret < 0)
			return ret;

		/* Enable the entry */
		sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
				 (1 << (31 - i)), TSU_TEN);
	}

	/* Entry found or created, enable POST */
	sh_eth_tsu_enable_cam_entry_post(ndev, i);

	return 0;
}

static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i, ret;

	if (!mdp->cd->tsu)
		return 0;

	i = sh_eth_tsu_find_entry(ndev, addr);
	if (i) {
		/* Entry found */
		if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
			goto done;

		/* Disable the entry if both ports was disabled */
		ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
		if (ret < 0)
			return ret;
	}
done:
	return 0;
}

static int sh_eth_tsu_purge_all(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i, ret;

	if (unlikely(!mdp->cd->tsu))
		return 0;

	for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
		if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
			continue;

		/* Disable the entry if both ports was disabled */
		ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u8 addr[ETH_ALEN];
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int i;

	if (unlikely(!mdp->cd->tsu))
		return;

	for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
		sh_eth_tsu_read_entry(reg_offset, addr);
		if (is_multicast_ether_addr(addr))
			sh_eth_tsu_del_entry(ndev, addr);
	}
}

2430 2431 2432
/* Multicast reception directions set */
static void sh_eth_set_multicast_list(struct net_device *ndev)
{
2433 2434 2435 2436 2437 2438
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 ecmr_bits;
	int mcast_all = 0;
	unsigned long flags;

	spin_lock_irqsave(&mdp->lock, flags);
S
Sergei Shtylyov 已提交
2439
	/* Initial condition is MCT = 1, PRM = 0.
2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453
	 * Depending on ndev->flags, set PRM or clear MCT
	 */
	ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;

	if (!(ndev->flags & IFF_MULTICAST)) {
		sh_eth_tsu_purge_mcast(ndev);
		mcast_all = 1;
	}
	if (ndev->flags & IFF_ALLMULTI) {
		sh_eth_tsu_purge_mcast(ndev);
		ecmr_bits &= ~ECMR_MCT;
		mcast_all = 1;
	}

2454
	if (ndev->flags & IFF_PROMISC) {
2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470
		sh_eth_tsu_purge_all(ndev);
		ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
	} else if (mdp->cd->tsu) {
		struct netdev_hw_addr *ha;
		netdev_for_each_mc_addr(ha, ndev) {
			if (mcast_all && is_multicast_ether_addr(ha->addr))
				continue;

			if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
				if (!mcast_all) {
					sh_eth_tsu_purge_mcast(ndev);
					ecmr_bits &= ~ECMR_MCT;
					mcast_all = 1;
				}
			}
		}
2471 2472
	} else {
		/* Normal, unicast/broadcast-only mode. */
2473
		ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2474
	}
2475 2476 2477 2478 2479

	/* update the ethernet mode */
	sh_eth_write(ndev, ecmr_bits, ECMR);

	spin_unlock_irqrestore(&mdp->lock, flags);
2480
}
2481 2482 2483 2484 2485 2486 2487 2488 2489

static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
{
	if (!mdp->port)
		return TSU_VTAG0;
	else
		return TSU_VTAG1;
}

2490 2491
static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
				  __be16 proto, u16 vid)
2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int vtag_reg_index = sh_eth_get_vtag_index(mdp);

	if (unlikely(!mdp->cd->tsu))
		return -EPERM;

	/* No filtering if vid = 0 */
	if (!vid)
		return 0;

	mdp->vlan_num_ids++;

S
Sergei Shtylyov 已提交
2505
	/* The controller has one VLAN tag HW filter. So, if the filter is
2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519
	 * already enabled, the driver disables it and the filte
	 */
	if (mdp->vlan_num_ids > 1) {
		/* disable VLAN filter */
		sh_eth_tsu_write(mdp, 0, vtag_reg_index);
		return 0;
	}

	sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
			 vtag_reg_index);

	return 0;
}

2520 2521
static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
				   __be16 proto, u16 vid)
2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int vtag_reg_index = sh_eth_get_vtag_index(mdp);

	if (unlikely(!mdp->cd->tsu))
		return -EPERM;

	/* No filtering if vid = 0 */
	if (!vid)
		return 0;

	mdp->vlan_num_ids--;
	sh_eth_tsu_write(mdp, 0, vtag_reg_index);

	return 0;
}
2538 2539

/* SuperH's TSU register init function */
2540
static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2541
{
S
Simon Horman 已提交
2542 2543 2544 2545 2546
	if (sh_eth_is_rz_fast_ether(mdp)) {
		sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
		return;
	}

2547 2548 2549 2550 2551 2552 2553 2554 2555 2556
	sh_eth_tsu_write(mdp, 0, TSU_FWEN0);	/* Disable forward(0->1) */
	sh_eth_tsu_write(mdp, 0, TSU_FWEN1);	/* Disable forward(1->0) */
	sh_eth_tsu_write(mdp, 0, TSU_FCM);	/* forward fifo 3k-3k */
	sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
	sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
	sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
	sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
	sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
	sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
	sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2557 2558 2559 2560 2561 2562 2563
	if (sh_eth_is_gether(mdp)) {
		sh_eth_tsu_write(mdp, 0, TSU_QTAG0);	/* Disable QTAG(0->1) */
		sh_eth_tsu_write(mdp, 0, TSU_QTAG1);	/* Disable QTAG(1->0) */
	} else {
		sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);	/* Disable QTAG(0->1) */
		sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);	/* Disable QTAG(1->0) */
	}
2564 2565 2566 2567 2568 2569 2570
	sh_eth_tsu_write(mdp, 0, TSU_FWSR);	/* all interrupt status clear */
	sh_eth_tsu_write(mdp, 0, TSU_FWINMK);	/* Disable all interrupt */
	sh_eth_tsu_write(mdp, 0, TSU_TEN);	/* Disable all CAM entry */
	sh_eth_tsu_write(mdp, 0, TSU_POST1);	/* Disable CAM entry [ 0- 7] */
	sh_eth_tsu_write(mdp, 0, TSU_POST2);	/* Disable CAM entry [ 8-15] */
	sh_eth_tsu_write(mdp, 0, TSU_POST3);	/* Disable CAM entry [16-23] */
	sh_eth_tsu_write(mdp, 0, TSU_POST4);	/* Disable CAM entry [24-31] */
2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590
}

/* MDIO bus release function */
static int sh_mdio_release(struct net_device *ndev)
{
	struct mii_bus *bus = dev_get_drvdata(&ndev->dev);

	/* unregister mdio bus */
	mdiobus_unregister(bus);

	/* remove mdio bus info from net_device */
	dev_set_drvdata(&ndev->dev, NULL);

	/* free bitbang info */
	free_mdio_bitbang(bus);

	return 0;
}

/* MDIO bus init function */
2591 2592
static int sh_mdio_init(struct net_device *ndev, int id,
			struct sh_eth_plat_data *pd)
2593 2594 2595 2596 2597 2598
{
	int ret, i;
	struct bb_info *bitbang;
	struct sh_eth_private *mdp = netdev_priv(ndev);

	/* create bit control struct for PHY */
S
Sergei Shtylyov 已提交
2599 2600
	bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
			       GFP_KERNEL);
2601 2602 2603 2604 2605 2606
	if (!bitbang) {
		ret = -ENOMEM;
		goto out;
	}

	/* bitbang init */
Y
Yoshihiro Shimoda 已提交
2607
	bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2608
	bitbang->set_gate = pd->set_mdio_gate;
S
Sergei Shtylyov 已提交
2609 2610 2611 2612
	bitbang->mdi_msk = PIR_MDI;
	bitbang->mdo_msk = PIR_MDO;
	bitbang->mmd_msk = PIR_MMD;
	bitbang->mdc_msk = PIR_MDC;
2613 2614
	bitbang->ctrl.ops = &bb_ops;

2615
	/* MII controller setting */
2616 2617 2618
	mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
	if (!mdp->mii_bus) {
		ret = -ENOMEM;
S
Sergei Shtylyov 已提交
2619
		goto out;
2620 2621 2622 2623
	}

	/* Hook up MII support for ethtool */
	mdp->mii_bus->name = "sh_mii";
2624
	mdp->mii_bus->parent = &ndev->dev;
2625
	snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
S
Sergei Shtylyov 已提交
2626
		 mdp->pdev->name, id);
2627 2628

	/* PHY IRQ */
S
Sergei Shtylyov 已提交
2629 2630 2631
	mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
					 sizeof(int) * PHY_MAX_ADDR,
					 GFP_KERNEL);
2632 2633 2634 2635 2636 2637 2638
	if (!mdp->mii_bus->irq) {
		ret = -ENOMEM;
		goto out_free_bus;
	}

	for (i = 0; i < PHY_MAX_ADDR; i++)
		mdp->mii_bus->irq[i] = PHY_POLL;
2639 2640
	if (pd->phy_irq > 0)
		mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2641

2642
	/* register mdio bus */
2643 2644
	ret = mdiobus_register(mdp->mii_bus);
	if (ret)
S
Sergei Shtylyov 已提交
2645
		goto out_free_bus;
2646 2647 2648 2649 2650 2651

	dev_set_drvdata(&ndev->dev, mdp->mii_bus);

	return 0;

out_free_bus:
2652
	free_mdio_bitbang(mdp->mii_bus);
2653 2654 2655 2656 2657

out:
	return ret;
}

2658 2659 2660 2661 2662 2663 2664 2665
static const u16 *sh_eth_get_register_offset(int register_type)
{
	const u16 *reg_offset = NULL;

	switch (register_type) {
	case SH_ETH_REG_GIGABIT:
		reg_offset = sh_eth_offset_gigabit;
		break;
S
Simon Horman 已提交
2666 2667 2668
	case SH_ETH_REG_FAST_RZ:
		reg_offset = sh_eth_offset_fast_rz;
		break;
2669 2670 2671
	case SH_ETH_REG_FAST_RCAR:
		reg_offset = sh_eth_offset_fast_rcar;
		break;
2672 2673 2674 2675 2676 2677 2678
	case SH_ETH_REG_FAST_SH4:
		reg_offset = sh_eth_offset_fast_sh4;
		break;
	case SH_ETH_REG_FAST_SH3_SH2:
		reg_offset = sh_eth_offset_fast_sh3_sh2;
		break;
	default:
2679
		pr_err("Unknown register type (%d)\n", register_type);
2680 2681 2682 2683 2684 2685
		break;
	}

	return reg_offset;
}

2686
static const struct net_device_ops sh_eth_netdev_ops = {
2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697
	.ndo_open		= sh_eth_open,
	.ndo_stop		= sh_eth_close,
	.ndo_start_xmit		= sh_eth_start_xmit,
	.ndo_get_stats		= sh_eth_get_stats,
	.ndo_tx_timeout		= sh_eth_tx_timeout,
	.ndo_do_ioctl		= sh_eth_do_ioctl,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_set_mac_address	= eth_mac_addr,
	.ndo_change_mtu		= eth_change_mtu,
};

2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712
static const struct net_device_ops sh_eth_netdev_ops_tsu = {
	.ndo_open		= sh_eth_open,
	.ndo_stop		= sh_eth_close,
	.ndo_start_xmit		= sh_eth_start_xmit,
	.ndo_get_stats		= sh_eth_get_stats,
	.ndo_set_rx_mode	= sh_eth_set_multicast_list,
	.ndo_vlan_rx_add_vid	= sh_eth_vlan_rx_add_vid,
	.ndo_vlan_rx_kill_vid	= sh_eth_vlan_rx_kill_vid,
	.ndo_tx_timeout		= sh_eth_tx_timeout,
	.ndo_do_ioctl		= sh_eth_do_ioctl,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_set_mac_address	= eth_mac_addr,
	.ndo_change_mtu		= eth_change_mtu,
};

2713 2714
static int sh_eth_drv_probe(struct platform_device *pdev)
{
2715
	int ret, devno = 0;
2716 2717
	struct resource *res;
	struct net_device *ndev = NULL;
2718
	struct sh_eth_private *mdp = NULL;
J
Jingoo Han 已提交
2719
	struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2720
	const struct platform_device_id *id = platform_get_device_id(pdev);
2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742

	/* get base addr */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(res == NULL)) {
		dev_err(&pdev->dev, "invalid resource\n");
		ret = -EINVAL;
		goto out;
	}

	ndev = alloc_etherdev(sizeof(struct sh_eth_private));
	if (!ndev) {
		ret = -ENOMEM;
		goto out;
	}

	/* The sh Ether-specific entries in the device structure. */
	ndev->base_addr = res->start;
	devno = pdev->id;
	if (devno < 0)
		devno = 0;

	ndev->dma = -1;
2743 2744
	ret = platform_get_irq(pdev, 0);
	if (ret < 0) {
2745 2746 2747
		ret = -ENODEV;
		goto out_release;
	}
2748
	ndev->irq = ret;
2749 2750 2751 2752

	SET_NETDEV_DEV(ndev, &pdev->dev);

	mdp = netdev_priv(ndev);
2753 2754
	mdp->num_tx_ring = TX_RING_SIZE;
	mdp->num_rx_ring = RX_RING_SIZE;
S
Sergei Shtylyov 已提交
2755 2756 2757
	mdp->addr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mdp->addr)) {
		ret = PTR_ERR(mdp->addr);
Y
Yoshihiro Shimoda 已提交
2758 2759 2760
		goto out_release;
	}

2761
	spin_lock_init(&mdp->lock);
2762 2763 2764
	mdp->pdev = pdev;
	pm_runtime_enable(&pdev->dev);
	pm_runtime_resume(&pdev->dev);
2765

2766 2767 2768 2769 2770 2771
	if (!pd) {
		dev_err(&pdev->dev, "no platform data\n");
		ret = -EINVAL;
		goto out_release;
	}

2772
	/* get PHY ID */
2773
	mdp->phy_id = pd->phy;
2774
	mdp->phy_interface = pd->phy_interface;
2775 2776
	/* EDMAC endian */
	mdp->edmac_endian = pd->edmac_endian;
2777 2778
	mdp->no_ether_link = pd->no_ether_link;
	mdp->ether_link_active_low = pd->ether_link_active_low;
2779

2780
	/* set cpu data */
2781
	mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2782
	mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2783 2784
	sh_eth_set_default_cpu_data(mdp->cd);

2785
	/* set function */
2786 2787 2788 2789
	if (mdp->cd->tsu)
		ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
	else
		ndev->netdev_ops = &sh_eth_netdev_ops;
2790
	SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2791 2792
	ndev->watchdog_timeo = TX_TIMEOUT;

2793 2794
	/* debug message level */
	mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2795 2796

	/* read and set MAC address */
2797
	read_mac_address(ndev, pd->mac_addr);
2798 2799 2800 2801 2802
	if (!is_valid_ether_addr(ndev->dev_addr)) {
		dev_warn(&pdev->dev,
			 "no valid MAC address supplied, using a random one.\n");
		eth_hw_addr_random(ndev);
	}
2803

2804 2805 2806 2807
	/* ioremap the TSU registers */
	if (mdp->cd->tsu) {
		struct resource *rtsu;
		rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
S
Sergei Shtylyov 已提交
2808 2809 2810
		mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
		if (IS_ERR(mdp->tsu_addr)) {
			ret = PTR_ERR(mdp->tsu_addr);
2811 2812
			goto out_release;
		}
2813
		mdp->port = devno % 2;
2814
		ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2815 2816
	}

2817 2818
	/* initialize first or needed device */
	if (!devno || pd->needs_init) {
2819 2820
		if (mdp->cd->chip_reset)
			mdp->cd->chip_reset(ndev);
2821

2822 2823 2824 2825
		if (mdp->cd->tsu) {
			/* TSU init (Init only)*/
			sh_eth_tsu_init(mdp);
		}
2826 2827
	}

S
Sergei Shtylyov 已提交
2828 2829
	netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);

2830 2831 2832
	/* network device register */
	ret = register_netdev(ndev);
	if (ret)
S
Sergei Shtylyov 已提交
2833
		goto out_napi_del;
2834 2835

	/* mdio bus init */
2836
	ret = sh_mdio_init(ndev, pdev->id, pd);
2837 2838 2839
	if (ret)
		goto out_unregister;

L
Lucas De Marchi 已提交
2840
	/* print device information */
2841
	pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
S
Sergei Shtylyov 已提交
2842
		(u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2843 2844 2845 2846 2847 2848 2849 2850

	platform_set_drvdata(pdev, ndev);

	return ret;

out_unregister:
	unregister_netdev(ndev);

S
Sergei Shtylyov 已提交
2851 2852 2853
out_napi_del:
	netif_napi_del(&mdp->napi);

2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865
out_release:
	/* net_dev free */
	if (ndev)
		free_netdev(ndev);

out:
	return ret;
}

static int sh_eth_drv_remove(struct platform_device *pdev)
{
	struct net_device *ndev = platform_get_drvdata(pdev);
S
Sergei Shtylyov 已提交
2866
	struct sh_eth_private *mdp = netdev_priv(ndev);
2867 2868 2869

	sh_mdio_release(ndev);
	unregister_netdev(ndev);
S
Sergei Shtylyov 已提交
2870
	netif_napi_del(&mdp->napi);
2871
	pm_runtime_disable(&pdev->dev);
2872 2873 2874 2875 2876
	free_netdev(ndev);

	return 0;
}

2877
#ifdef CONFIG_PM
2878 2879
static int sh_eth_runtime_nop(struct device *dev)
{
S
Sergei Shtylyov 已提交
2880
	/* Runtime PM callback shared between ->runtime_suspend()
2881 2882 2883 2884 2885 2886 2887 2888 2889
	 * and ->runtime_resume(). Simply returns success.
	 *
	 * This driver re-initializes all registers after
	 * pm_runtime_get_sync() anyway so there is no need
	 * to save and restore registers here.
	 */
	return 0;
}

2890
static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2891 2892 2893
	.runtime_suspend = sh_eth_runtime_nop,
	.runtime_resume = sh_eth_runtime_nop,
};
2894 2895 2896 2897
#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
#else
#define SH_ETH_PM_OPS NULL
#endif
2898

2899
static struct platform_device_id sh_eth_id_table[] = {
2900
	{ "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2901
	{ "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2902
	{ "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2903
	{ "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2904 2905
	{ "sh7757-ether", (kernel_ulong_t)&sh7757_data },
	{ "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2906
	{ "sh7763-gether", (kernel_ulong_t)&sh7763_data },
S
Simon Horman 已提交
2907
	{ "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
2908
	{ "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2909
	{ "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
S
Sergei Shtylyov 已提交
2910 2911
	{ "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
	{ "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
2912 2913 2914 2915
	{ }
};
MODULE_DEVICE_TABLE(platform, sh_eth_id_table);

2916 2917 2918
static struct platform_driver sh_eth_driver = {
	.probe = sh_eth_drv_probe,
	.remove = sh_eth_drv_remove,
2919
	.id_table = sh_eth_id_table,
2920 2921
	.driver = {
		   .name = CARDNAME,
2922
		   .pm = SH_ETH_PM_OPS,
2923 2924 2925
	},
};

2926
module_platform_driver(sh_eth_driver);
2927 2928 2929 2930

MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
MODULE_LICENSE("GPL v2");