hw.c 104.2 KB
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/*
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 * Copyright (c) 2008-2009 Atheros Communications Inc.
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 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/io.h>
#include <asm/unaligned.h>

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#include "hw.h"
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#include "rc.h"
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#include "initvals.h"

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#define ATH9K_CLOCK_RATE_CCK		22
#define ATH9K_CLOCK_RATE_5GHZ_OFDM	40
#define ATH9K_CLOCK_RATE_2GHZ_OFDM	44
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static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
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static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
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static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
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			      struct ar5416_eeprom_def *pEepData,
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			      u32 reg, u32 value);
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MODULE_AUTHOR("Atheros Communications");
MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
MODULE_LICENSE("Dual BSD/GPL");

static int __init ath9k_init(void)
{
	return 0;
}
module_init(ath9k_init);

static void __exit ath9k_exit(void)
{
	return;
}
module_exit(ath9k_exit);

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/********************/
/* Helper Functions */
/********************/
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static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	if (!ah->curchan) /* should really check for CCK instead */
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		return usecs *ATH9K_CLOCK_RATE_CCK;
	if (conf->channel->band == IEEE80211_BAND_2GHZ)
		return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
	return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
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}

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static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	if (conf_is_ht40(conf))
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		return ath9k_hw_mac_clks(ah, usecs) * 2;
	else
		return ath9k_hw_mac_clks(ah, usecs);
}
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bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
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{
	int i;

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	BUG_ON(timeout < AH_TIME_QUANTUM);

	for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
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		if ((REG_READ(ah, reg) & mask) == val)
			return true;

		udelay(AH_TIME_QUANTUM);
	}
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	ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
		  "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
		  timeout, reg, REG_READ(ah, reg), mask, val);
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	return false;
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}
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EXPORT_SYMBOL(ath9k_hw_wait);
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u32 ath9k_hw_reverse_bits(u32 val, u32 n)
{
	u32 retval;
	int i;

	for (i = 0, retval = 0; i < n; i++) {
		retval = (retval << 1) | (val & 1);
		val >>= 1;
	}
	return retval;
}

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bool ath9k_get_channel_edges(struct ath_hw *ah,
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			     u16 flags, u16 *low,
			     u16 *high)
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{
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	struct ath9k_hw_capabilities *pCap = &ah->caps;
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	if (flags & CHANNEL_5GHZ) {
		*low = pCap->low_5ghz_chan;
		*high = pCap->high_5ghz_chan;
		return true;
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	}
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	if ((flags & CHANNEL_2GHZ)) {
		*low = pCap->low_2ghz_chan;
		*high = pCap->high_2ghz_chan;
		return true;
	}
	return false;
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}

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u16 ath9k_hw_computetxtime(struct ath_hw *ah,
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			   u8 phy, int kbps,
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			   u32 frameLen, u16 rateix,
			   bool shortPreamble)
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{
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	u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
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	if (kbps == 0)
		return 0;
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	switch (phy) {
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	case WLAN_RC_PHY_CCK:
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		phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
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		if (shortPreamble)
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			phyTime >>= 1;
		numBits = frameLen << 3;
		txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
		break;
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	case WLAN_RC_PHY_OFDM:
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		if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_QUARTER
				+ OFDM_PREAMBLE_TIME_QUARTER
				+ (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
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		} else if (ah->curchan &&
			   IS_CHAN_HALF_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_HALF +
				OFDM_PREAMBLE_TIME_HALF
				+ (numSymbols * OFDM_SYMBOL_TIME_HALF);
		} else {
			bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
				+ (numSymbols * OFDM_SYMBOL_TIME);
		}
		break;
	default:
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		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
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			  "Unknown phy %u (rate ix %u)\n", phy, rateix);
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		txTime = 0;
		break;
	}
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	return txTime;
}
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EXPORT_SYMBOL(ath9k_hw_computetxtime);
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void ath9k_hw_get_channel_centers(struct ath_hw *ah,
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				  struct ath9k_channel *chan,
				  struct chan_centers *centers)
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{
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	int8_t extoff;
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	if (!IS_CHAN_HT40(chan)) {
		centers->ctl_center = centers->ext_center =
			centers->synth_center = chan->channel;
		return;
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	}

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	if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
	    (chan->chanmode == CHANNEL_G_HT40PLUS)) {
		centers->synth_center =
			chan->channel + HT40_CHANNEL_CENTER_SHIFT;
		extoff = 1;
	} else {
		centers->synth_center =
			chan->channel - HT40_CHANNEL_CENTER_SHIFT;
		extoff = -1;
	}
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	centers->ctl_center =
		centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
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	/* 25 MHz spacing is supported by hw but not on upper layers */
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	centers->ext_center =
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		centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
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}

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/******************/
/* Chip Revisions */
/******************/

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static void ath9k_hw_read_revisions(struct ath_hw *ah)
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{
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	u32 val;
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	val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
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	if (val == 0xFF) {
		val = REG_READ(ah, AR_SREV);
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		ah->hw_version.macVersion =
			(val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
		ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
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		ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
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	} else {
		if (!AR_SREV_9100(ah))
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			ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
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		ah->hw_version.macRev = val & AR_SREV_REVISION;
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		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
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			ah->is_pciexpress = true;
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	}
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}

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static int ath9k_hw_get_radiorev(struct ath_hw *ah)
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{
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	u32 val;
	int i;
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	REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
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	for (i = 0; i < 8; i++)
		REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
	val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
	val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
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	return ath9k_hw_reverse_bits(val, 8);
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}

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/************************************/
/* HW Attach, Detach, Init Routines */
/************************************/

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static void ath9k_hw_disablepcie(struct ath_hw *ah)
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{
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	if (AR_SREV_9100(ah))
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		return;
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	REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
	REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
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	REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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}

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static bool ath9k_hw_chip_test(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
	u32 regHold[2];
	u32 patternData[4] = { 0x55555555,
			       0xaaaaaaaa,
			       0x66666666,
			       0x99999999 };
	int i, j;
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	for (i = 0; i < 2; i++) {
		u32 addr = regAddr[i];
		u32 wrData, rdData;
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		regHold[i] = REG_READ(ah, addr);
		for (j = 0; j < 0x100; j++) {
			wrData = (j << 16) | j;
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (rdData != wrData) {
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				ath_print(common, ATH_DBG_FATAL,
					  "address test failed "
					  "addr: 0x%08x - wr:0x%08x != "
					  "rd:0x%08x\n",
					  addr, wrData, rdData);
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				return false;
			}
		}
		for (j = 0; j < 4; j++) {
			wrData = patternData[j];
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (wrData != rdData) {
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				ath_print(common, ATH_DBG_FATAL,
					  "address test failed "
					  "addr: 0x%08x - wr:0x%08x != "
					  "rd:0x%08x\n",
					  addr, wrData, rdData);
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				return false;
			}
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		}
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		REG_WRITE(ah, regAddr[i], regHold[i]);
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	}
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	udelay(100);
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	return true;
}

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static void ath9k_hw_init_config(struct ath_hw *ah)
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{
	int i;
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	ah->config.dma_beacon_response_time = 2;
	ah->config.sw_beacon_response_time = 10;
	ah->config.additional_swba_backoff = 0;
	ah->config.ack_6mb = 0x0;
	ah->config.cwm_ignore_extcca = 0;
	ah->config.pcie_powersave_enable = 0;
	ah->config.pcie_clock_req = 0;
	ah->config.pcie_waen = 0;
	ah->config.analog_shiftreg = 1;
	ah->config.ofdm_trig_low = 200;
	ah->config.ofdm_trig_high = 500;
	ah->config.cck_trig_high = 200;
	ah->config.cck_trig_low = 100;
	ah->config.enable_ani = 1;
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	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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		ah->config.spurchans[i][0] = AR_NO_SPUR;
		ah->config.spurchans[i][1] = AR_NO_SPUR;
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	}

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	if (ah->hw_version.devid != AR2427_DEVID_PCIE)
		ah->config.ht_enable = 1;
	else
		ah->config.ht_enable = 0;

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	ah->config.rx_intr_mitigation = true;
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	/*
	 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
	 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
	 * This means we use it for all AR5416 devices, and the few
	 * minor PCI AR9280 devices out there.
	 *
	 * Serialization is required because these devices do not handle
	 * well the case of two concurrent reads/writes due to the latency
	 * involved. During one read/write another read/write can be issued
	 * on another CPU while the previous read/write may still be working
	 * on our hardware, if we hit this case the hardware poops in a loop.
	 * We prevent this by serializing reads and writes.
	 *
	 * This issue is not present on PCI-Express devices or pre-AR5416
	 * devices (legacy, 802.11abg).
	 */
	if (num_possible_cpus() > 1)
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		ah->config.serialize_regmode = SER_REG_MODE_AUTO;
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}
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EXPORT_SYMBOL(ath9k_hw_init);
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static void ath9k_hw_init_defaults(struct ath_hw *ah)
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{
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	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);

	regulatory->country_code = CTRY_DEFAULT;
	regulatory->power_limit = MAX_RATE_POWER;
	regulatory->tp_scale = ATH9K_TP_SCALE_MAX;

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	ah->hw_version.magic = AR5416_MAGIC;
	ah->hw_version.subvendorid = 0;
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	ah->ah_flags = 0;
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	if (ah->hw_version.devid == AR5416_AR9100_DEVID)
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		ah->hw_version.macVersion = AR_SREV_VERSION_9100;
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	if (!AR_SREV_9100(ah))
		ah->ah_flags = AH_USE_EEPROM;

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	ah->atim_window = 0;
	ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
	ah->beacon_interval = 100;
	ah->enable_32kHz_clock = DONT_USE_32KHZ;
	ah->slottime = (u32) -1;
	ah->globaltxtimeout = (u32) -1;
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	ah->power_mode = ATH9K_PM_UNDEFINED;
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}

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static int ath9k_hw_rf_claim(struct ath_hw *ah)
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{
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	u32 val;

	REG_WRITE(ah, AR_PHY(0), 0x00000007);

	val = ath9k_hw_get_radiorev(ah);
	switch (val & AR_RADIO_SREV_MAJOR) {
	case 0:
		val = AR_RAD5133_SREV_MAJOR;
		break;
	case AR_RAD5133_SREV_MAJOR:
	case AR_RAD5122_SREV_MAJOR:
	case AR_RAD2133_SREV_MAJOR:
	case AR_RAD2122_SREV_MAJOR:
		break;
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	default:
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		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "Radio Chip Rev 0x%02X not supported\n",
			  val & AR_RADIO_SREV_MAJOR);
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		return -EOPNOTSUPP;
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	}

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	ah->hw_version.analog5GhzRev = val;
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	return 0;
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}

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static int ath9k_hw_init_macaddr(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 sum;
	int i;
	u16 eeval;

	sum = 0;
	for (i = 0; i < 3; i++) {
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		eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
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		sum += eeval;
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		common->macaddr[2 * i] = eeval >> 8;
		common->macaddr[2 * i + 1] = eeval & 0xff;
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	}
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	if (sum == 0 || sum == 0xffff * 3)
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		return -EADDRNOTAVAIL;

	return 0;
}

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static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
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{
	u32 rxgain_type;

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	if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
		rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
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		if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
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			INIT_INI_ARRAY(&ah->iniModesRxGain,
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			ar9280Modes_backoff_13db_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
		else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
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			INIT_INI_ARRAY(&ah->iniModesRxGain,
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			ar9280Modes_backoff_23db_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
		else
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			INIT_INI_ARRAY(&ah->iniModesRxGain,
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			ar9280Modes_original_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
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	} else {
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		INIT_INI_ARRAY(&ah->iniModesRxGain,
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			ar9280Modes_original_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
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	}
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}

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static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
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{
	u32 txgain_type;

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	if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
		txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
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		if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
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			INIT_INI_ARRAY(&ah->iniModesTxGain,
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			ar9280Modes_high_power_tx_gain_9280_2,
			ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
		else
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			INIT_INI_ARRAY(&ah->iniModesTxGain,
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			ar9280Modes_original_tx_gain_9280_2,
			ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
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	} else {
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		INIT_INI_ARRAY(&ah->iniModesTxGain,
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		ar9280Modes_original_tx_gain_9280_2,
		ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
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	}
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}

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static int ath9k_hw_post_init(struct ath_hw *ah)
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{
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	int ecode;
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	if (!AR_SREV_9271(ah)) {
		if (!ath9k_hw_chip_test(ah))
			return -ENODEV;
	}
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	ecode = ath9k_hw_rf_claim(ah);
	if (ecode != 0)
509 510
		return ecode;

511
	ecode = ath9k_hw_eeprom_init(ah);
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512 513
	if (ecode != 0)
		return ecode;
514

515 516 517 518
	ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
		  "Eeprom VER: %d, REV: %d\n",
		  ah->eep_ops->get_eeprom_ver(ah),
		  ah->eep_ops->get_eeprom_rev(ah));
519

520 521 522 523 524 525 526 527 528
        if (!AR_SREV_9280_10_OR_LATER(ah)) {
		ecode = ath9k_hw_rf_alloc_ext_banks(ah);
		if (ecode) {
			ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
				  "Failed allocating banks for "
				  "external radio\n");
			return ecode;
		}
	}
529

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530 531
	if (!AR_SREV_9100(ah)) {
		ath9k_hw_ani_setup(ah);
532
		ath9k_hw_ani_init(ah);
533 534 535 536 537
	}

	return 0;
}

538 539 540 541 542 543 544 545 546 547 548 549
static bool ath9k_hw_devid_supported(u16 devid)
{
	switch (devid) {
	case AR5416_DEVID_PCI:
	case AR5416_DEVID_PCIE:
	case AR5416_AR9100_DEVID:
	case AR9160_DEVID_PCI:
	case AR9280_DEVID_PCI:
	case AR9280_DEVID_PCIE:
	case AR9285_DEVID_PCIE:
	case AR5416_DEVID_AR9287_PCI:
	case AR5416_DEVID_AR9287_PCIE:
550
	case AR9271_USB:
551
	case AR2427_DEVID_PCIE:
552 553 554 555 556 557 558
		return true;
	default:
		break;
	}
	return false;
}

559 560 561 562 563 564 565 566 567 568
static bool ath9k_hw_macversion_supported(u32 macversion)
{
	switch (macversion) {
	case AR_SREV_VERSION_5416_PCI:
	case AR_SREV_VERSION_5416_PCIE:
	case AR_SREV_VERSION_9160:
	case AR_SREV_VERSION_9100:
	case AR_SREV_VERSION_9280:
	case AR_SREV_VERSION_9285:
	case AR_SREV_VERSION_9287:
569
	case AR_SREV_VERSION_9271:
570
		return true;
571 572 573 574 575 576
	default:
		break;
	}
	return false;
}

577
static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
578
{
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579 580
	if (AR_SREV_9160_10_OR_LATER(ah)) {
		if (AR_SREV_9280_10_OR_LATER(ah)) {
581 582
			ah->iq_caldata.calData = &iq_cal_single_sample;
			ah->adcgain_caldata.calData =
S
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583
				&adc_gain_cal_single_sample;
584
			ah->adcdc_caldata.calData =
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585
				&adc_dc_cal_single_sample;
586
			ah->adcdc_calinitdata.calData =
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587 588
				&adc_init_dc_cal;
		} else {
589 590
			ah->iq_caldata.calData = &iq_cal_multi_sample;
			ah->adcgain_caldata.calData =
S
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591
				&adc_gain_cal_multi_sample;
592
			ah->adcdc_caldata.calData =
S
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593
				&adc_dc_cal_multi_sample;
594
			ah->adcdc_calinitdata.calData =
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595 596
				&adc_init_dc_cal;
		}
597
		ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
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598
	}
599
}
600

601 602
static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
{
603
	if (AR_SREV_9271(ah)) {
604 605 606 607
		INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
			       ARRAY_SIZE(ar9271Modes_9271), 6);
		INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
			       ARRAY_SIZE(ar9271Common_9271), 2);
608 609 610 611 612 613
		INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
			       ar9271Common_normal_cck_fir_coeff_9271,
			       ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
		INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
			       ar9271Common_japan_2484_cck_fir_coeff_9271,
			       ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
614 615 616
		INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
			       ar9271Modes_9271_1_0_only,
			       ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
617 618 619 620 621 622 623 624
		INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
			       ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
		INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
			       ar9271Modes_high_power_tx_gain_9271,
			       ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
		INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
			       ar9271Modes_normal_power_tx_gain_9271,
			       ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
625 626 627
		return;
	}

628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657
	if (AR_SREV_9287_11_OR_LATER(ah)) {
		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
				ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
		INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
				ARRAY_SIZE(ar9287Common_9287_1_1), 2);
		if (ah->config.pcie_clock_req)
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_off_L1_9287_1_1,
			ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
		else
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
			ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
					2);
	} else if (AR_SREV_9287_10_OR_LATER(ah)) {
		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
				ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
		INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
				ARRAY_SIZE(ar9287Common_9287_1_0), 2);

		if (ah->config.pcie_clock_req)
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_off_L1_9287_1_0,
			ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
		else
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
			ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
				  2);
	} else if (AR_SREV_9285_12_OR_LATER(ah)) {
658

659

660
		INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
661
			       ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
662
		INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
663 664
			       ARRAY_SIZE(ar9285Common_9285_1_2), 2);

665 666
		if (ah->config.pcie_clock_req) {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
667 668 669
			ar9285PciePhy_clkreq_off_L1_9285_1_2,
			ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
		} else {
670
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
671 672 673 674 675
			ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
			ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
				  2);
		}
	} else if (AR_SREV_9285_10_OR_LATER(ah)) {
676
		INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
677
			       ARRAY_SIZE(ar9285Modes_9285), 6);
678
		INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
679 680
			       ARRAY_SIZE(ar9285Common_9285), 2);

681 682
		if (ah->config.pcie_clock_req) {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
683 684 685
			ar9285PciePhy_clkreq_off_L1_9285,
			ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
		} else {
686
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
687 688 689 690
			ar9285PciePhy_clkreq_always_on_L1_9285,
			ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
		}
	} else if (AR_SREV_9280_20_OR_LATER(ah)) {
691
		INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
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			       ARRAY_SIZE(ar9280Modes_9280_2), 6);
693
		INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
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			       ARRAY_SIZE(ar9280Common_9280_2), 2);
695

696 697
		if (ah->config.pcie_clock_req) {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
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698 699 700
			       ar9280PciePhy_clkreq_off_L1_9280,
			       ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
		} else {
701
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
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702 703 704
			       ar9280PciePhy_clkreq_always_on_L1_9280,
			       ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
		}
705
		INIT_INI_ARRAY(&ah->iniModesAdditional,
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706 707 708
			       ar9280Modes_fast_clock_9280_2,
			       ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
	} else if (AR_SREV_9280_10_OR_LATER(ah)) {
709
		INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
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710
			       ARRAY_SIZE(ar9280Modes_9280), 6);
711
		INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
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712 713
			       ARRAY_SIZE(ar9280Common_9280), 2);
	} else if (AR_SREV_9160_10_OR_LATER(ah)) {
714
		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
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715
			       ARRAY_SIZE(ar5416Modes_9160), 6);
716
		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
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717
			       ARRAY_SIZE(ar5416Common_9160), 2);
718
		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
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719
			       ARRAY_SIZE(ar5416Bank0_9160), 2);
720
		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
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721
			       ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
722
		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
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723
			       ARRAY_SIZE(ar5416Bank1_9160), 2);
724
		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
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725
			       ARRAY_SIZE(ar5416Bank2_9160), 2);
726
		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
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727
			       ARRAY_SIZE(ar5416Bank3_9160), 3);
728
		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
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729
			       ARRAY_SIZE(ar5416Bank6_9160), 3);
730
		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
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731
			       ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
732
		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
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733 734
			       ARRAY_SIZE(ar5416Bank7_9160), 2);
		if (AR_SREV_9160_11(ah)) {
735
			INIT_INI_ARRAY(&ah->iniAddac,
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736 737 738
				       ar5416Addac_91601_1,
				       ARRAY_SIZE(ar5416Addac_91601_1), 2);
		} else {
739
			INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
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740 741 742
				       ARRAY_SIZE(ar5416Addac_9160), 2);
		}
	} else if (AR_SREV_9100_OR_LATER(ah)) {
743
		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
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744
			       ARRAY_SIZE(ar5416Modes_9100), 6);
745
		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
S
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746
			       ARRAY_SIZE(ar5416Common_9100), 2);
747
		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
S
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748
			       ARRAY_SIZE(ar5416Bank0_9100), 2);
749
		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
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750
			       ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
751
		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
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752
			       ARRAY_SIZE(ar5416Bank1_9100), 2);
753
		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
S
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754
			       ARRAY_SIZE(ar5416Bank2_9100), 2);
755
		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
S
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756
			       ARRAY_SIZE(ar5416Bank3_9100), 3);
757
		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
S
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758
			       ARRAY_SIZE(ar5416Bank6_9100), 3);
759
		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
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760
			       ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
761
		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
S
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762
			       ARRAY_SIZE(ar5416Bank7_9100), 2);
763
		INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
S
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764 765
			       ARRAY_SIZE(ar5416Addac_9100), 2);
	} else {
766
		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
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767
			       ARRAY_SIZE(ar5416Modes), 6);
768
		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
S
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769
			       ARRAY_SIZE(ar5416Common), 2);
770
		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
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771
			       ARRAY_SIZE(ar5416Bank0), 2);
772
		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
S
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773
			       ARRAY_SIZE(ar5416BB_RfGain), 3);
774
		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
S
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775
			       ARRAY_SIZE(ar5416Bank1), 2);
776
		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
S
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777
			       ARRAY_SIZE(ar5416Bank2), 2);
778
		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
S
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779
			       ARRAY_SIZE(ar5416Bank3), 3);
780
		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
S
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781
			       ARRAY_SIZE(ar5416Bank6), 3);
782
		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
S
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783
			       ARRAY_SIZE(ar5416Bank6TPC), 3);
784
		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
S
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785
			       ARRAY_SIZE(ar5416Bank7), 2);
786
		INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
S
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787
			       ARRAY_SIZE(ar5416Addac), 2);
788
	}
789
}
790

791 792
static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
{
793
	if (AR_SREV_9287_11_OR_LATER(ah))
794 795 796 797 798 799 800 801 802 803
		INIT_INI_ARRAY(&ah->iniModesRxGain,
		ar9287Modes_rx_gain_9287_1_1,
		ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
	else if (AR_SREV_9287_10(ah))
		INIT_INI_ARRAY(&ah->iniModesRxGain,
		ar9287Modes_rx_gain_9287_1_0,
		ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
	else if (AR_SREV_9280_20(ah))
		ath9k_hw_init_rxgain_ini(ah);

804
	if (AR_SREV_9287_11_OR_LATER(ah)) {
805 806 807 808 809 810 811 812 813 814
		INIT_INI_ARRAY(&ah->iniModesTxGain,
		ar9287Modes_tx_gain_9287_1_1,
		ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
	} else if (AR_SREV_9287_10(ah)) {
		INIT_INI_ARRAY(&ah->iniModesTxGain,
		ar9287Modes_tx_gain_9287_1_0,
		ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
	} else if (AR_SREV_9280_20(ah)) {
		ath9k_hw_init_txgain_ini(ah);
	} else if (AR_SREV_9285_12_OR_LATER(ah)) {
815 816 817 818 819 820 821 822 823 824 825 826 827 828
		u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);

		/* txgain table */
		if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
			INIT_INI_ARRAY(&ah->iniModesTxGain,
			ar9285Modes_high_power_tx_gain_9285_1_2,
			ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
		} else {
			INIT_INI_ARRAY(&ah->iniModesTxGain,
			ar9285Modes_original_tx_gain_9285_1_2,
			ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
		}

	}
829
}
830

831
static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
832 833
{
	u32 i, j;
S
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834

835
	if (ah->hw_version.devid == AR9280_DEVID_PCI) {
S
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836 837

		/* EEPROM Fixup */
838 839
		for (i = 0; i < ah->iniModes.ia_rows; i++) {
			u32 reg = INI_RA(&ah->iniModes, i, 0);
840

841 842
			for (j = 1; j < ah->iniModes.ia_columns; j++) {
				u32 val = INI_RA(&ah->iniModes, i, j);
843

844
				INI_RA(&ah->iniModes, i, j) =
845
					ath9k_hw_ini_fixup(ah,
846
							   &ah->eeprom.def,
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847 848
							   reg, val);
			}
849
		}
S
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850
	}
851 852
}

853
int ath9k_hw_init(struct ath_hw *ah)
854
{
855
	struct ath_common *common = ath9k_hw_common(ah);
856
	int r = 0;
857

858 859 860 861
	if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
		ath_print(common, ATH_DBG_FATAL,
			  "Unsupported device ID: 0x%0x\n",
			  ah->hw_version.devid);
862
		return -EOPNOTSUPP;
863
	}
864 865 866 867 868

	ath9k_hw_init_defaults(ah);
	ath9k_hw_init_config(ah);

	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
869 870
		ath_print(common, ATH_DBG_FATAL,
			  "Couldn't reset chip\n");
871
		return -EIO;
872 873
	}

874
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
875
		ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
876
		return -EIO;
877 878 879 880 881 882 883 884 885 886 887 888 889
	}

	if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
		    (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
			ah->config.serialize_regmode =
				SER_REG_MODE_ON;
		} else {
			ah->config.serialize_regmode =
				SER_REG_MODE_OFF;
		}
	}

890
	ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
891 892
		ah->config.serialize_regmode);

893 894 895 896 897
	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
		ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
	else
		ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;

898
	if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
899 900 901 902
		ath_print(common, ATH_DBG_FATAL,
			  "Mac Chip Rev 0x%02x.%x is not supported by "
			  "this driver\n", ah->hw_version.macVersion,
			  ah->hw_version.macRev);
903
		return -EOPNOTSUPP;
904 905 906 907 908 909 910
	}

	if (AR_SREV_9100(ah)) {
		ah->iq_caldata.calData = &iq_cal_multi_sample;
		ah->supp_cals = IQ_MISMATCH_CAL;
		ah->is_pciexpress = false;
	}
911 912 913 914

	if (AR_SREV_9271(ah))
		ah->is_pciexpress = false;

915 916 917 918 919
	ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);

	ath9k_hw_init_cal_settings(ah);

	ah->ani_function = ATH9K_ANI_ALL;
920
	if (AR_SREV_9280_10_OR_LATER(ah)) {
921
		ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
922
		ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
923 924
		ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
	} else {
925
		ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
926 927
		ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
	}
928 929 930 931

	ath9k_hw_init_mode_regs(ah);

	if (ah->is_pciexpress)
V
Vivek Natarajan 已提交
932
		ath9k_hw_configpcipowersave(ah, 0, 0);
933 934 935
	else
		ath9k_hw_disablepcie(ah);

S
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936 937 938 939 940 941 942 943 944 945
	/* Support for Japan ch.14 (2484) spread */
	if (AR_SREV_9287_11_OR_LATER(ah)) {
		INIT_INI_ARRAY(&ah->iniCckfirNormal,
		       ar9287Common_normal_cck_fir_coeff_92871_1,
		       ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
		       ar9287Common_japan_2484_cck_fir_coeff_92871_1,
		       ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
	}

946
	r = ath9k_hw_post_init(ah);
947
	if (r)
948
		return r;
949 950

	ath9k_hw_init_mode_gain_regs(ah);
951 952 953 954
	r = ath9k_hw_fill_cap_info(ah);
	if (r)
		return r;

955
	ath9k_hw_init_eeprom_fix(ah);
956

957 958
	r = ath9k_hw_init_macaddr(ah);
	if (r) {
959 960
		ath_print(common, ATH_DBG_FATAL,
			  "Failed to initialize MAC address\n");
961
		return r;
962 963
	}

964
	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
965
		ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
S
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966
	else
967
		ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
968

S
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969
	ath9k_init_nfcal_hist_buffer(ah);
970

971 972
	common->state = ATH_HW_INITIALIZED;

973
	return 0;
974 975
}

976
static void ath9k_hw_init_bb(struct ath_hw *ah,
S
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977
			     struct ath9k_channel *chan)
978
{
S
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979
	u32 synthDelay;
980

S
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981
	synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
982
	if (IS_CHAN_B(chan))
S
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983 984 985
		synthDelay = (4 * synthDelay) / 22;
	else
		synthDelay /= 10;
986

S
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987
	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
988

S
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989
	udelay(synthDelay + BASE_ACTIVATE_DELAY);
990 991
}

992
static void ath9k_hw_init_qos(struct ath_hw *ah)
993
{
S
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994 995
	REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
	REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
996

S
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997 998 999 1000 1001 1002 1003 1004 1005 1006
	REG_WRITE(ah, AR_QOS_NO_ACK,
		  SM(2, AR_QOS_NO_ACK_TWO_BIT) |
		  SM(5, AR_QOS_NO_ACK_BIT_OFF) |
		  SM(0, AR_QOS_NO_ACK_BYTE_OFF));

	REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
	REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1007 1008
}

1009
static void ath9k_hw_init_pll(struct ath_hw *ah,
S
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1010
			      struct ath9k_channel *chan)
1011
{
S
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1012
	u32 pll;
1013

S
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1014 1015 1016
	if (AR_SREV_9100(ah)) {
		if (chan && IS_CHAN_5GHZ(chan))
			pll = 0x1450;
1017
		else
S
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1018 1019 1020 1021
			pll = 0x1458;
	} else {
		if (AR_SREV_9280_10_OR_LATER(ah)) {
			pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1022

S
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1023 1024 1025 1026
			if (chan && IS_CHAN_HALF_RATE(chan))
				pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
			else if (chan && IS_CHAN_QUARTER_RATE(chan))
				pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1027

S
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1028 1029
			if (chan && IS_CHAN_5GHZ(chan)) {
				pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1030 1031


S
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1032 1033 1034 1035 1036 1037 1038 1039 1040 1041
				if (AR_SREV_9280_20(ah)) {
					if (((chan->channel % 20) == 0)
					    || ((chan->channel % 10) == 0))
						pll = 0x2850;
					else
						pll = 0x142c;
				}
			} else {
				pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
			}
1042

S
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1043
		} else if (AR_SREV_9160_10_OR_LATER(ah)) {
1044

S
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1045
			pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1046

S
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1047 1048 1049 1050
			if (chan && IS_CHAN_HALF_RATE(chan))
				pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
			else if (chan && IS_CHAN_QUARTER_RATE(chan))
				pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1051

S
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1052 1053 1054 1055 1056 1057
			if (chan && IS_CHAN_5GHZ(chan))
				pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
			else
				pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
		} else {
			pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1058

S
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1059 1060 1061 1062
			if (chan && IS_CHAN_HALF_RATE(chan))
				pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
			else if (chan && IS_CHAN_QUARTER_RATE(chan))
				pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1063

S
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1064 1065 1066 1067 1068 1069
			if (chan && IS_CHAN_5GHZ(chan))
				pll |= SM(0xa, AR_RTC_PLL_DIV);
			else
				pll |= SM(0xb, AR_RTC_PLL_DIV);
		}
	}
1070
	REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1071

1072 1073
	/* Switch the core clock for ar9271 to 117Mhz */
	if (AR_SREV_9271(ah)) {
1074 1075
		udelay(500);
		REG_WRITE(ah, 0x50040, 0x304);
1076 1077
	}

S
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1078 1079 1080
	udelay(RTC_PLL_SETTLE_DELAY);

	REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1081 1082
}

1083
static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1084 1085 1086
{
	int rx_chainmask, tx_chainmask;

1087 1088
	rx_chainmask = ah->rxchainmask;
	tx_chainmask = ah->txchainmask;
1089 1090 1091 1092 1093 1094

	switch (rx_chainmask) {
	case 0x5:
		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
			    AR_PHY_SWAP_ALT_CHAIN);
	case 0x3:
1095
		if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119
			REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
			REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
			break;
		}
	case 0x1:
	case 0x2:
	case 0x7:
		REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
		REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
		break;
	default:
		break;
	}

	REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
	if (tx_chainmask == 0x5) {
		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
			    AR_PHY_SWAP_ALT_CHAIN);
	}
	if (AR_SREV_9100(ah))
		REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
			  REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
}

1120
static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1121
					  enum nl80211_iftype opmode)
1122
{
1123
	ah->mask_reg = AR_IMR_TXERR |
S
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1124 1125 1126 1127
		AR_IMR_TXURN |
		AR_IMR_RXERR |
		AR_IMR_RXORN |
		AR_IMR_BCNMISC;
1128

S
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1129
	if (ah->config.rx_intr_mitigation)
1130
		ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1131
	else
1132
		ah->mask_reg |= AR_IMR_RXOK;
1133

1134
	ah->mask_reg |= AR_IMR_TXOK;
1135

1136
	if (opmode == NL80211_IFTYPE_AP)
1137
		ah->mask_reg |= AR_IMR_MIB;
1138

1139
	REG_WRITE(ah, AR_IMR, ah->mask_reg);
1140 1141
	ah->imrs2_reg |= AR_IMR_S2_GTT;
	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1142

S
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1143 1144 1145 1146 1147
	if (!AR_SREV_9100(ah)) {
		REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
		REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
		REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
	}
1148 1149
}

1150
static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1151
{
1152 1153 1154
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) 0xFFFF);
	REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1155 1156
}

1157
static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1158
{
1159 1160 1161 1162 1163 1164 1165 1166 1167 1168
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
	REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
}

static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
{
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
	REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1169
}
S
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1170

1171
static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1172 1173
{
	if (tu > 0xFFFF) {
1174 1175
		ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
			  "bad global tx timeout %u\n", tu);
1176
		ah->globaltxtimeout = (u32) -1;
1177 1178 1179
		return false;
	} else {
		REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1180
		ah->globaltxtimeout = tu;
1181 1182 1183 1184
		return true;
	}
}

1185
void ath9k_hw_init_global_settings(struct ath_hw *ah)
1186
{
1187 1188
	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
	int acktimeout;
1189
	int slottime;
1190 1191
	int sifstime;

1192 1193
	ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
		  ah->misc_mode);
1194

1195
	if (ah->misc_mode != 0)
S
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1196
		REG_WRITE(ah, AR_PCU_MISC,
1197
			  REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1198 1199 1200 1201 1202 1203

	if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
		sifstime = 16;
	else
		sifstime = 10;

1204 1205 1206
	/* As defined by IEEE 802.11-2007 17.3.8.6 */
	slottime = ah->slottime + 3 * ah->coverage_class;
	acktimeout = slottime + sifstime;
1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217

	/*
	 * Workaround for early ACK timeouts, add an offset to match the
	 * initval's 64us ack timeout value.
	 * This was initially only meant to work around an issue with delayed
	 * BA frames in some implementations, but it has been found to fix ACK
	 * timeout issues in other cases as well.
	 */
	if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
		acktimeout += 64 - sifstime - ah->slottime;

1218
	ath9k_hw_setslottime(ah, slottime);
1219 1220
	ath9k_hw_set_ack_timeout(ah, acktimeout);
	ath9k_hw_set_cts_timeout(ah, acktimeout);
1221 1222
	if (ah->globaltxtimeout != (u32) -1)
		ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
S
Sujith 已提交
1223
}
1224
EXPORT_SYMBOL(ath9k_hw_init_global_settings);
S
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1225

S
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1226
void ath9k_hw_deinit(struct ath_hw *ah)
S
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1227
{
1228 1229
	struct ath_common *common = ath9k_hw_common(ah);

S
Sujith 已提交
1230
	if (common->state < ATH_HW_INITIALIZED)
1231 1232
		goto free_hw;

S
Sujith 已提交
1233
	if (!AR_SREV_9100(ah))
1234
		ath9k_hw_ani_disable(ah);
S
Sujith 已提交
1235

1236
	ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1237 1238

free_hw:
1239 1240
	if (!AR_SREV_9280_10_OR_LATER(ah))
		ath9k_hw_rf_free_ext_banks(ah);
S
Sujith 已提交
1241
}
S
Sujith 已提交
1242
EXPORT_SYMBOL(ath9k_hw_deinit);
S
Sujith 已提交
1243 1244 1245 1246 1247

/*******/
/* INI */
/*******/

1248
static void ath9k_hw_override_ini(struct ath_hw *ah,
S
Sujith 已提交
1249 1250
				  struct ath9k_channel *chan)
{
1251 1252
	u32 val;

1253 1254 1255 1256 1257 1258 1259
	/*
	 * Set the RX_ABORT and RX_DIS and clear if off only after
	 * RXE is set for MAC. This prevents frames with corrupted
	 * descriptor status.
	 */
	REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));

1260
	if (AR_SREV_9280_10_OR_LATER(ah)) {
1261 1262 1263 1264
		val = REG_READ(ah, AR_PCU_MISC_MODE2);

		if (!AR_SREV_9271(ah))
			val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1265 1266 1267 1268 1269 1270

		if (AR_SREV_9287_10_OR_LATER(ah))
			val = val & (~AR_PCU_MISC_MODE2_HWWAR2);

		REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
	}
1271

1272
	if (!AR_SREV_5416_20_OR_LATER(ah) ||
S
Sujith 已提交
1273 1274
	    AR_SREV_9280_10_OR_LATER(ah))
		return;
1275 1276 1277 1278
	/*
	 * Disable BB clock gating
	 * Necessary to avoid issues on AR5416 2.0
	 */
S
Sujith 已提交
1279
	REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1280 1281 1282 1283 1284 1285 1286 1287 1288 1289

	/*
	 * Disable RIFS search on some chips to avoid baseband
	 * hang issues.
	 */
	if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
		val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
		val &= ~AR_PHY_RIFS_INIT_DELAY;
		REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
	}
1290 1291
}

1292
static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1293
			      struct ar5416_eeprom_def *pEepData,
S
Sujith 已提交
1294
			      u32 reg, u32 value)
1295
{
S
Sujith 已提交
1296
	struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1297
	struct ath_common *common = ath9k_hw_common(ah);
1298

1299
	switch (ah->hw_version.devid) {
S
Sujith 已提交
1300 1301
	case AR9280_DEVID_PCI:
		if (reg == 0x7894) {
1302
			ath_print(common, ATH_DBG_EEPROM,
S
Sujith 已提交
1303 1304 1305 1306
				"ini VAL: %x  EEPROM: %x\n", value,
				(pBase->version & 0xff));

			if ((pBase->version & 0xff) > 0x0a) {
1307 1308 1309
				ath_print(common, ATH_DBG_EEPROM,
					  "PWDCLKIND: %d\n",
					  pBase->pwdclkind);
S
Sujith 已提交
1310 1311 1312 1313
				value &= ~AR_AN_TOP2_PWDCLKIND;
				value |= AR_AN_TOP2_PWDCLKIND &
					(pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
			} else {
1314 1315
				ath_print(common, ATH_DBG_EEPROM,
					  "PWDCLKIND Earlier Rev\n");
S
Sujith 已提交
1316 1317
			}

1318 1319
			ath_print(common, ATH_DBG_EEPROM,
				  "final ini VAL: %x\n", value);
S
Sujith 已提交
1320 1321 1322 1323 1324
		}
		break;
	}

	return value;
1325 1326
}

1327
static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1328 1329 1330
			      struct ar5416_eeprom_def *pEepData,
			      u32 reg, u32 value)
{
1331
	if (ah->eep_map == EEP_MAP_4KBITS)
1332 1333 1334 1335 1336
		return value;
	else
		return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
}

1337 1338 1339 1340
static void ath9k_olc_init(struct ath_hw *ah)
{
	u32 i;

1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355
	if (OLC_FOR_AR9287_10_LATER) {
		REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
				AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
		ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
				AR9287_AN_TXPC0_TXPCMODE,
				AR9287_AN_TXPC0_TXPCMODE_S,
				AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
		udelay(100);
	} else {
		for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
			ah->originalGain[i] =
				MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
						AR_PHY_TX_GAIN);
		ah->PDADCdelta = 0;
	}
1356 1357
}

1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372
static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
			      struct ath9k_channel *chan)
{
	u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);

	if (IS_CHAN_B(chan))
		ctl |= CTL_11B;
	else if (IS_CHAN_G(chan))
		ctl |= CTL_11G;
	else
		ctl |= CTL_11A;

	return ctl;
}

1373
static int ath9k_hw_process_ini(struct ath_hw *ah,
L
Luis R. Rodriguez 已提交
1374
				struct ath9k_channel *chan)
1375
{
1376
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1377
	int i, regWrites = 0;
1378
	struct ieee80211_channel *channel = chan->chan;
1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407
	u32 modesIndex, freqIndex;

	switch (chan->chanmode) {
	case CHANNEL_A:
	case CHANNEL_A_HT20:
		modesIndex = 1;
		freqIndex = 1;
		break;
	case CHANNEL_A_HT40PLUS:
	case CHANNEL_A_HT40MINUS:
		modesIndex = 2;
		freqIndex = 1;
		break;
	case CHANNEL_G:
	case CHANNEL_G_HT20:
	case CHANNEL_B:
		modesIndex = 4;
		freqIndex = 2;
		break;
	case CHANNEL_G_HT40PLUS:
	case CHANNEL_G_HT40MINUS:
		modesIndex = 3;
		freqIndex = 2;
		break;

	default:
		return -EINVAL;
	}

1408
	/* Set correct baseband to analog shift setting to access analog chips */
1409
	REG_WRITE(ah, AR_PHY(0), 0x00000007);
1410 1411

	/* Write ADDAC shifts */
1412
	REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
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	ah->eep_ops->set_addac(ah, chan);
1414

1415
	if (AR_SREV_5416_22_OR_LATER(ah)) {
1416
		REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1417 1418 1419
	} else {
		struct ar5416IniArray temp;
		u32 addacSize =
1420 1421
			sizeof(u32) * ah->iniAddac.ia_rows *
			ah->iniAddac.ia_columns;
1422

1423
		/* For AR5416 2.0/2.1 */
1424 1425
		memcpy(ah->addac5416_21,
		       ah->iniAddac.ia_array, addacSize);
1426

1427
		/* override CLKDRV value at [row, column] = [31, 1] */
1428
		(ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1429

1430 1431 1432
		temp.ia_array = ah->addac5416_21;
		temp.ia_columns = ah->iniAddac.ia_columns;
		temp.ia_rows = ah->iniAddac.ia_rows;
1433 1434
		REG_WRITE_ARRAY(&temp, 1, regWrites);
	}
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1436 1437
	REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);

1438 1439 1440
	for (i = 0; i < ah->iniModes.ia_rows; i++) {
		u32 reg = INI_RA(&ah->iniModes, i, 0);
		u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1441 1442 1443 1444

		REG_WRITE(ah, reg, val);

		if (reg >= 0x7800 && reg < 0x78a0
1445
		    && ah->config.analog_shiftreg) {
1446 1447 1448 1449 1450 1451
			udelay(100);
		}

		DO_DELAY(regWrites);
	}

1452
	if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1453
		REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1454

1455 1456
	if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
	    AR_SREV_9287_10_OR_LATER(ah))
1457
		REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1458

1459 1460 1461 1462 1463
	if (AR_SREV_9271_10(ah))
		REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
				modesIndex, regWrites);

	/* Write common array parameters */
1464 1465 1466
	for (i = 0; i < ah->iniCommon.ia_rows; i++) {
		u32 reg = INI_RA(&ah->iniCommon, i, 0);
		u32 val = INI_RA(&ah->iniCommon, i, 1);
1467 1468 1469 1470

		REG_WRITE(ah, reg, val);

		if (reg >= 0x7800 && reg < 0x78a0
1471
		    && ah->config.analog_shiftreg) {
1472 1473 1474 1475 1476 1477
			udelay(100);
		}

		DO_DELAY(regWrites);
	}

1478 1479 1480 1481 1482 1483 1484 1485
	if (AR_SREV_9271(ah)) {
		if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
			REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
					modesIndex, regWrites);
		else
			REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
					modesIndex, regWrites);
	}
1486

1487
	ath9k_hw_write_regs(ah, freqIndex, regWrites);
1488

1489
	if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1490
		REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1491 1492 1493 1494
				regWrites);
	}

	ath9k_hw_override_ini(ah, chan);
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	ath9k_hw_set_regs(ah, chan);
1496 1497
	ath9k_hw_init_chain_masks(ah);

1498 1499 1500
	if (OLC_FOR_AR9280_20_LATER)
		ath9k_olc_init(ah);

1501
	/* Set TX power */
1502
	ah->eep_ops->set_txpower(ah, chan,
1503
				 ath9k_regd_get_ctl(regulatory, chan),
1504 1505 1506
				 channel->max_antenna_gain * 2,
				 channel->max_power * 2,
				 min((u32) MAX_RATE_POWER,
1507
				 (u32) regulatory->power_limit));
1508

1509
	/* Write analog registers */
1510
	if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1511 1512
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "ar5416SetRfRegs failed\n");
1513 1514 1515 1516 1517 1518
		return -EIO;
	}

	return 0;
}

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/****************************************/
/* Reset and Channel Switching Routines */
/****************************************/

1523
static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1524
{
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	u32 rfMode = 0;

	if (chan == NULL)
		return;

	rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
		? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;

	if (!AR_SREV_9280_10_OR_LATER(ah))
		rfMode |= (IS_CHAN_5GHZ(chan)) ?
			AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;

	if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
		rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);

	REG_WRITE(ah, AR_PHY_MODE, rfMode);
}

1543
static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
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{
	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
}

1548
static inline void ath9k_hw_set_dma(struct ath_hw *ah)
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{
	u32 regval;

1552 1553 1554
	/*
	 * set AHB_MODE not to do cacheline prefetches
	*/
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	regval = REG_READ(ah, AR_AHB_MODE);
	REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);

1558 1559 1560
	/*
	 * let mac dma reads be in 128 byte chunks
	 */
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	regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
	REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);

1564 1565 1566 1567 1568
	/*
	 * Restore TX Trigger Level to its pre-reset value.
	 * The initial value depends on whether aggregation is enabled, and is
	 * adjusted whenever underruns are detected.
	 */
1569
	REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
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1571 1572 1573
	/*
	 * let mac dma writes be in 128 byte chunks
	 */
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	regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
	REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);

1577 1578 1579
	/*
	 * Setup receive FIFO threshold to hold off TX activities
	 */
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	REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);

1582 1583 1584 1585
	/*
	 * reduce the number of usable entries in PCU TXBUF to avoid
	 * wrap around issues.
	 */
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	if (AR_SREV_9285(ah)) {
1587 1588 1589 1590
		/* For AR9285 the number of Fifos are reduced to half.
		 * So set the usable tx buf size also to half to
		 * avoid data/delimiter underruns
		 */
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		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1593
	} else if (!AR_SREV_9271(ah)) {
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		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_PCU_TXBUF_CTRL_USABLE_SIZE);
	}
}

1599
static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
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{
	u32 val;

	val = REG_READ(ah, AR_STA_ID1);
	val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
	switch (opmode) {
1606
	case NL80211_IFTYPE_AP:
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		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
			  | AR_STA_ID1_KSRCH_MODE);
		REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1610
		break;
1611
	case NL80211_IFTYPE_ADHOC:
1612
	case NL80211_IFTYPE_MESH_POINT:
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		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
			  | AR_STA_ID1_KSRCH_MODE);
		REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1616
		break;
1617 1618
	case NL80211_IFTYPE_STATION:
	case NL80211_IFTYPE_MONITOR:
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		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1620
		break;
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	}
}

1624
static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
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						 u32 coef_scaled,
						 u32 *coef_mantissa,
						 u32 *coef_exponent)
{
	u32 coef_exp, coef_man;

	for (coef_exp = 31; coef_exp > 0; coef_exp--)
		if ((coef_scaled >> coef_exp) & 0x1)
			break;

	coef_exp = 14 - (coef_exp - COEF_SCALE_S);

	coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));

	*coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
	*coef_exponent = coef_exp - 16;
}

1643
static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
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1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676
				     struct ath9k_channel *chan)
{
	u32 coef_scaled, ds_coef_exp, ds_coef_man;
	u32 clockMhzScaled = 0x64000000;
	struct chan_centers centers;

	if (IS_CHAN_HALF_RATE(chan))
		clockMhzScaled = clockMhzScaled >> 1;
	else if (IS_CHAN_QUARTER_RATE(chan))
		clockMhzScaled = clockMhzScaled >> 2;

	ath9k_hw_get_channel_centers(ah, chan, &centers);
	coef_scaled = clockMhzScaled / centers.synth_center;

	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
				      &ds_coef_exp);

	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
		      AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
		      AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);

	coef_scaled = (9 * coef_scaled) / 10;

	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
				      &ds_coef_exp);

	REG_RMW_FIELD(ah, AR_PHY_HALFGI,
		      AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
	REG_RMW_FIELD(ah, AR_PHY_HALFGI,
		      AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
}

1677
static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
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1678 1679 1680 1681
{
	u32 rst_flags;
	u32 tmpReg;

1682 1683 1684 1685 1686 1687 1688 1689
	if (AR_SREV_9100(ah)) {
		u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
		val &= ~AR_RTC_DERIVED_CLK_PERIOD;
		val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
		REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
		(void)REG_READ(ah, AR_RTC_DERIVED_CLK);
	}

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1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

	if (AR_SREV_9100(ah)) {
		rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
			AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
	} else {
		tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
		if (tmpReg &
		    (AR_INTR_SYNC_LOCAL_TIMEOUT |
		     AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
			REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
			REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
		} else {
			REG_WRITE(ah, AR_RC, AR_RC_AHB);
		}

		rst_flags = AR_RTC_RC_MAC_WARM;
		if (type == ATH9K_RESET_COLD)
			rst_flags |= AR_RTC_RC_MAC_COLD;
	}

1712
	REG_WRITE(ah, AR_RTC_RC, rst_flags);
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1713 1714
	udelay(50);

1715
	REG_WRITE(ah, AR_RTC_RC, 0);
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1716
	if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1717 1718
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "RTC stuck in MAC reset\n");
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1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730
		return false;
	}

	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, 0);

	if (AR_SREV_9100(ah))
		udelay(50);

	return true;
}

1731
static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
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1732 1733 1734 1735
{
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

1736 1737 1738
	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, AR_RC_AHB);

1739
	REG_WRITE(ah, AR_RTC_RESET, 0);
1740
	udelay(2);
1741 1742 1743 1744

	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, 0);

1745
	REG_WRITE(ah, AR_RTC_RESET, 1);
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1746 1747 1748 1749

	if (!ath9k_hw_wait(ah,
			   AR_RTC_STATUS,
			   AR_RTC_STATUS_M,
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1750 1751
			   AR_RTC_STATUS_ON,
			   AH_WAIT_TIMEOUT)) {
1752 1753
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "RTC not waking up\n");
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1754
		return false;
1755 1756
	}

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1757 1758 1759 1760 1761
	ath9k_hw_read_revisions(ah);

	return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
}

1762
static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
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1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775
{
	REG_WRITE(ah, AR_RTC_FORCE_WAKE,
		  AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);

	switch (type) {
	case ATH9K_RESET_POWER_ON:
		return ath9k_hw_set_reset_power_on(ah);
	case ATH9K_RESET_WARM:
	case ATH9K_RESET_COLD:
		return ath9k_hw_set_reset(ah, type);
	default:
		return false;
	}
1776 1777
}

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1778
static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1779
{
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1780
	u32 phymode;
1781
	u32 enableDacFifo = 0;
1782

1783 1784 1785 1786
	if (AR_SREV_9285_10_OR_LATER(ah))
		enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
					 AR_PHY_FC_ENABLE_DAC_FIFO);

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	phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1788
		| AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
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1789 1790 1791

	if (IS_CHAN_HT40(chan)) {
		phymode |= AR_PHY_FC_DYN2040_EN;
1792

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1793 1794 1795
		if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
		    (chan->chanmode == CHANNEL_G_HT40PLUS))
			phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1796 1797

	}
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	REG_WRITE(ah, AR_PHY_TURBO, phymode);

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	ath9k_hw_set11nmac2040(ah);
1801

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1802 1803
	REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
	REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1804 1805
}

1806
static bool ath9k_hw_chip_reset(struct ath_hw *ah,
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1807
				struct ath9k_channel *chan)
1808
{
1809
	if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1810 1811 1812
		if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
			return false;
	} else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
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		return false;
1814

1815
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
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1816
		return false;
1817

1818
	ah->chip_fullsleep = false;
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1819 1820
	ath9k_hw_init_pll(ah, chan);
	ath9k_hw_set_rfmode(ah, chan);
1821

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1822
	return true;
1823 1824
}

1825
static bool ath9k_hw_channel_change(struct ath_hw *ah,
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1826
				    struct ath9k_channel *chan)
1827
{
1828
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1829
	struct ath_common *common = ath9k_hw_common(ah);
1830
	struct ieee80211_channel *channel = chan->chan;
1831
	u32 synthDelay, qnum;
1832
	int r;
1833 1834 1835

	for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
		if (ath9k_hw_numtxpending(ah, qnum)) {
1836 1837 1838
			ath_print(common, ATH_DBG_QUEUE,
				  "Transmit frames pending on "
				  "queue %d\n", qnum);
1839 1840 1841 1842 1843 1844
			return false;
		}
	}

	REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
	if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
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			   AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1846 1847
		ath_print(common, ATH_DBG_FATAL,
			  "Could not kill baseband RX\n");
1848 1849 1850
		return false;
	}

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	ath9k_hw_set_regs(ah, chan);
1852

1853
	r = ah->ath9k_hw_rf_set_freq(ah, chan);
1854 1855 1856 1857
	if (r) {
		ath_print(common, ATH_DBG_FATAL,
			  "Failed to set channel\n");
		return false;
1858 1859
	}

1860
	ah->eep_ops->set_txpower(ah, chan,
1861
			     ath9k_regd_get_ctl(regulatory, chan),
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1862 1863 1864
			     channel->max_antenna_gain * 2,
			     channel->max_power * 2,
			     min((u32) MAX_RATE_POWER,
1865
			     (u32) regulatory->power_limit));
1866 1867

	synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1868
	if (IS_CHAN_B(chan))
1869 1870 1871 1872 1873 1874 1875 1876
		synthDelay = (4 * synthDelay) / 22;
	else
		synthDelay /= 10;

	udelay(synthDelay + BASE_ACTIVATE_DELAY);

	REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);

S
Sujith 已提交
1877 1878 1879
	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

1880
	ah->ath9k_hw_spur_mitigate_freq(ah, chan);
S
Sujith 已提交
1881 1882 1883 1884 1885 1886 1887

	if (!chan->oneTimeCalsDone)
		chan->oneTimeCalsDone = true;

	return true;
}

J
Johannes Berg 已提交
1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899
static void ath9k_enable_rfkill(struct ath_hw *ah)
{
	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
		    AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);

	REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
		    AR_GPIO_INPUT_MUX2_RFSILENT);

	ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
	REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
}

1900
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1901
		    bool bChannelChange)
1902
{
1903
	struct ath_common *common = ath9k_hw_common(ah);
1904
	u32 saveLedState;
1905
	struct ath9k_channel *curchan = ah->curchan;
1906 1907
	u32 saveDefAntenna;
	u32 macStaId1;
S
Sujith 已提交
1908
	u64 tsf = 0;
1909
	int i, rx_chainmask, r;
1910

1911 1912
	ah->txchainmask = common->tx_chainmask;
	ah->rxchainmask = common->rx_chainmask;
1913

1914
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1915
		return -EIO;
1916

1917
	if (curchan && !ah->chip_fullsleep)
1918 1919 1920
		ath9k_hw_getnf(ah, curchan);

	if (bChannelChange &&
1921 1922 1923
	    (ah->chip_fullsleep != true) &&
	    (ah->curchan != NULL) &&
	    (chan->channel != ah->curchan->channel) &&
1924
	    ((chan->channelFlags & CHANNEL_ALL) ==
1925
	     (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1926 1927
	     !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
	     IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1928

L
Luis R. Rodriguez 已提交
1929
		if (ath9k_hw_channel_change(ah, chan)) {
1930
			ath9k_hw_loadnf(ah, ah->curchan);
1931
			ath9k_hw_start_nfcal(ah);
1932
			return 0;
1933 1934 1935 1936 1937 1938 1939 1940 1941
		}
	}

	saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
	if (saveDefAntenna == 0)
		saveDefAntenna = 1;

	macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;

S
Sujith 已提交
1942 1943 1944 1945
	/* For chips on which RTC reset is done, save TSF before it gets cleared */
	if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
		tsf = ath9k_hw_gettsf64(ah);

1946 1947 1948 1949 1950 1951
	saveLedState = REG_READ(ah, AR_CFG_LED) &
		(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
		 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);

	ath9k_hw_mark_phy_inactive(ah);

1952
	/* Only required on the first reset */
1953 1954 1955 1956 1957 1958 1959
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_RADIO_RF_RST);
		udelay(50);
	}

1960
	if (!ath9k_hw_chip_reset(ah, chan)) {
1961
		ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1962
		return -EINVAL;
1963 1964
	}

1965
	/* Only required on the first reset */
1966 1967 1968 1969 1970 1971 1972 1973
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		ah->htc_reset_init = false;
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_GATE_MAC_CTL);
		udelay(50);
	}

S
Sujith 已提交
1974 1975 1976 1977
	/* Restore TSF */
	if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
		ath9k_hw_settsf64(ah, tsf);

1978 1979
	if (AR_SREV_9280_10_OR_LATER(ah))
		REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1980

1981
	if (AR_SREV_9287_12_OR_LATER(ah)) {
1982 1983 1984 1985 1986 1987 1988 1989 1990
		/* Enable ASYNC FIFO */
		REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
				AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
		REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
		REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
				AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
		REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
				AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
	}
L
Luis R. Rodriguez 已提交
1991
	r = ath9k_hw_process_ini(ah, chan);
1992 1993
	if (r)
		return r;
1994

1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011
	/* Setup MFP options for CCMP */
	if (AR_SREV_9280_20_OR_LATER(ah)) {
		/* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
		 * frames when constructing CCMP AAD. */
		REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
			      0xc7ff);
		ah->sw_mgmt_crypto = false;
	} else if (AR_SREV_9160_10_OR_LATER(ah)) {
		/* Disable hardware crypto for management frames */
		REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
		ah->sw_mgmt_crypto = true;
	} else
		ah->sw_mgmt_crypto = true;

2012 2013 2014
	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

2015
	ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2016
	ah->eep_ops->set_board_values(ah, chan);
2017

2018 2019
	REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
	REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2020 2021
		  | macStaId1
		  | AR_STA_ID1_RTS_USE_DEF
2022
		  | (ah->config.
2023
		     ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2024 2025
		  | ah->sta_id1_defaults);
	ath9k_hw_set_operating_mode(ah, ah->opmode);
2026

2027
	ath_hw_setbssidmask(common);
2028 2029 2030

	REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);

2031
	ath9k_hw_write_associd(ah);
2032 2033 2034 2035 2036

	REG_WRITE(ah, AR_ISR, ~0);

	REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);

2037
	r = ah->ath9k_hw_rf_set_freq(ah, chan);
2038 2039
	if (r)
		return r;
2040 2041 2042 2043

	for (i = 0; i < AR_NUM_DCU; i++)
		REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);

2044 2045
	ah->intr_txqs = 0;
	for (i = 0; i < ah->caps.total_queues; i++)
2046 2047
		ath9k_hw_resettxqueue(ah, i);

2048
	ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2049 2050
	ath9k_hw_init_qos(ah);

2051
	if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2052
		ath9k_enable_rfkill(ah);
J
Johannes Berg 已提交
2053

2054
	ath9k_hw_init_global_settings(ah);
2055

2056
	if (AR_SREV_9287_12_OR_LATER(ah)) {
2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071
		REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
			  AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
		REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
			  AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
		REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
			  AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);

		REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
		REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);

		REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
			    AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
		REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
			      AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
	}
2072
	if (AR_SREV_9287_12_OR_LATER(ah)) {
2073 2074 2075 2076
		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
				AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
	}

2077 2078 2079 2080 2081 2082 2083
	REG_WRITE(ah, AR_STA_ID1,
		  REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);

	ath9k_hw_set_dma(ah);

	REG_WRITE(ah, AR_OBS, 8);

S
Sujith 已提交
2084
	if (ah->config.rx_intr_mitigation) {
2085 2086 2087 2088 2089 2090
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
	}

	ath9k_hw_init_bb(ah, chan);

2091
	if (!ath9k_hw_init_cal(ah, chan))
2092
		return -EIO;
2093

2094
	rx_chainmask = ah->rxchainmask;
2095 2096 2097 2098 2099 2100 2101
	if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
		REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
		REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
	}

	REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);

2102 2103 2104
	/*
	 * For big endian systems turn on swapping for descriptors
	 */
2105 2106 2107 2108
	if (AR_SREV_9100(ah)) {
		u32 mask;
		mask = REG_READ(ah, AR_CFG);
		if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2109
			ath_print(common, ATH_DBG_RESET,
S
Sujith 已提交
2110
				"CFG Byte Swap Set 0x%x\n", mask);
2111 2112 2113 2114
		} else {
			mask =
				INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
			REG_WRITE(ah, AR_CFG, mask);
2115
			ath_print(common, ATH_DBG_RESET,
S
Sujith 已提交
2116
				"Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2117 2118
		}
	} else {
2119 2120 2121
		/* Configure AR9271 target WLAN */
                if (AR_SREV_9271(ah))
			REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2122
#ifdef __BIG_ENDIAN
2123 2124
                else
			REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2125 2126 2127
#endif
	}

2128
	if (ah->btcoex_hw.enabled)
2129 2130
		ath9k_hw_btcoex_enable(ah);

2131
	return 0;
2132
}
2133
EXPORT_SYMBOL(ath9k_hw_reset);
2134

S
Sujith 已提交
2135 2136 2137
/************************/
/* Key Cache Management */
/************************/
2138

2139
bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2140
{
S
Sujith 已提交
2141
	u32 keyType;
2142

2143
	if (entry >= ah->caps.keycache_size) {
2144 2145
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "keychache entry %u out of range\n", entry);
2146 2147 2148
		return false;
	}

S
Sujith 已提交
2149
	keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2150

S
Sujith 已提交
2151 2152 2153 2154 2155 2156 2157 2158
	REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
	REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2159

S
Sujith 已提交
2160 2161
	if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
		u16 micentry = entry + 64;
2162

S
Sujith 已提交
2163 2164 2165 2166
		REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2167 2168 2169 2170 2171

	}

	return true;
}
2172
EXPORT_SYMBOL(ath9k_hw_keyreset);
2173

2174
bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2175
{
S
Sujith 已提交
2176
	u32 macHi, macLo;
2177

2178
	if (entry >= ah->caps.keycache_size) {
2179 2180
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "keychache entry %u out of range\n", entry);
S
Sujith 已提交
2181
		return false;
2182 2183
	}

S
Sujith 已提交
2184 2185 2186 2187 2188 2189 2190 2191 2192
	if (mac != NULL) {
		macHi = (mac[5] << 8) | mac[4];
		macLo = (mac[3] << 24) |
			(mac[2] << 16) |
			(mac[1] << 8) |
			mac[0];
		macLo >>= 1;
		macLo |= (macHi & 1) << 31;
		macHi >>= 1;
2193
	} else {
S
Sujith 已提交
2194
		macLo = macHi = 0;
2195
	}
S
Sujith 已提交
2196 2197
	REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
	REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2198

S
Sujith 已提交
2199
	return true;
2200
}
2201
EXPORT_SYMBOL(ath9k_hw_keysetmac);
2202

2203
bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
S
Sujith 已提交
2204
				 const struct ath9k_keyval *k,
J
Jouni Malinen 已提交
2205
				 const u8 *mac)
2206
{
2207
	const struct ath9k_hw_capabilities *pCap = &ah->caps;
2208
	struct ath_common *common = ath9k_hw_common(ah);
S
Sujith 已提交
2209 2210
	u32 key0, key1, key2, key3, key4;
	u32 keyType;
2211

S
Sujith 已提交
2212
	if (entry >= pCap->keycache_size) {
2213 2214
		ath_print(common, ATH_DBG_FATAL,
			  "keycache entry %u out of range\n", entry);
S
Sujith 已提交
2215
		return false;
2216 2217
	}

S
Sujith 已提交
2218 2219 2220 2221 2222 2223
	switch (k->kv_type) {
	case ATH9K_CIPHER_AES_OCB:
		keyType = AR_KEYTABLE_TYPE_AES;
		break;
	case ATH9K_CIPHER_AES_CCM:
		if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2224 2225 2226
			ath_print(common, ATH_DBG_ANY,
				  "AES-CCM not supported by mac rev 0x%x\n",
				  ah->hw_version.macRev);
S
Sujith 已提交
2227 2228 2229 2230 2231 2232 2233 2234
			return false;
		}
		keyType = AR_KEYTABLE_TYPE_CCM;
		break;
	case ATH9K_CIPHER_TKIP:
		keyType = AR_KEYTABLE_TYPE_TKIP;
		if (ATH9K_IS_MIC_ENABLED(ah)
		    && entry + 64 >= pCap->keycache_size) {
2235 2236
			ath_print(common, ATH_DBG_ANY,
				  "entry %u inappropriate for TKIP\n", entry);
S
Sujith 已提交
2237 2238 2239 2240
			return false;
		}
		break;
	case ATH9K_CIPHER_WEP:
2241
		if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2242 2243
			ath_print(common, ATH_DBG_ANY,
				  "WEP key length %u too small\n", k->kv_len);
S
Sujith 已提交
2244 2245
			return false;
		}
2246
		if (k->kv_len <= WLAN_KEY_LEN_WEP40)
S
Sujith 已提交
2247
			keyType = AR_KEYTABLE_TYPE_40;
2248
		else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
S
Sujith 已提交
2249 2250 2251 2252 2253 2254 2255 2256
			keyType = AR_KEYTABLE_TYPE_104;
		else
			keyType = AR_KEYTABLE_TYPE_128;
		break;
	case ATH9K_CIPHER_CLR:
		keyType = AR_KEYTABLE_TYPE_CLR;
		break;
	default:
2257 2258
		ath_print(common, ATH_DBG_FATAL,
			  "cipher %u not supported\n", k->kv_type);
S
Sujith 已提交
2259
		return false;
2260 2261
	}

J
Jouni Malinen 已提交
2262 2263 2264 2265 2266
	key0 = get_unaligned_le32(k->kv_val + 0);
	key1 = get_unaligned_le16(k->kv_val + 4);
	key2 = get_unaligned_le32(k->kv_val + 6);
	key3 = get_unaligned_le16(k->kv_val + 10);
	key4 = get_unaligned_le32(k->kv_val + 12);
2267
	if (k->kv_len <= WLAN_KEY_LEN_WEP104)
S
Sujith 已提交
2268
		key4 &= 0xff;
2269

2270 2271 2272 2273 2274 2275 2276
	/*
	 * Note: Key cache registers access special memory area that requires
	 * two 32-bit writes to actually update the values in the internal
	 * memory. Consequently, the exact order and pairs used here must be
	 * maintained.
	 */

S
Sujith 已提交
2277 2278
	if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
		u16 micentry = entry + 64;
2279

2280 2281 2282 2283 2284 2285
		/*
		 * Write inverted key[47:0] first to avoid Michael MIC errors
		 * on frames that could be sent or received at the same time.
		 * The correct key will be written in the end once everything
		 * else is ready.
		 */
S
Sujith 已提交
2286 2287
		REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2288 2289

		/* Write key[95:48] */
S
Sujith 已提交
2290 2291
		REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
		REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2292 2293

		/* Write key[127:96] and key type */
S
Sujith 已提交
2294 2295
		REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
		REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2296 2297

		/* Write MAC address for the entry */
S
Sujith 已提交
2298
		(void) ath9k_hw_keysetmac(ah, entry, mac);
2299

2300
		if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312
			/*
			 * TKIP uses two key cache entries:
			 * Michael MIC TX/RX keys in the same key cache entry
			 * (idx = main index + 64):
			 * key0 [31:0] = RX key [31:0]
			 * key1 [15:0] = TX key [31:16]
			 * key1 [31:16] = reserved
			 * key2 [31:0] = RX key [63:32]
			 * key3 [15:0] = TX key [15:0]
			 * key3 [31:16] = reserved
			 * key4 [31:0] = TX key [63:32]
			 */
S
Sujith 已提交
2313
			u32 mic0, mic1, mic2, mic3, mic4;
2314

S
Sujith 已提交
2315 2316 2317 2318 2319
			mic0 = get_unaligned_le32(k->kv_mic + 0);
			mic2 = get_unaligned_le32(k->kv_mic + 4);
			mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
			mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
			mic4 = get_unaligned_le32(k->kv_txmic + 4);
2320 2321

			/* Write RX[31:0] and TX[31:16] */
S
Sujith 已提交
2322 2323
			REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
			REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2324 2325

			/* Write RX[63:32] and TX[15:0] */
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2326 2327
			REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
			REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2328 2329

			/* Write TX[63:32] and keyType(reserved) */
S
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2330 2331 2332
			REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
			REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
				  AR_KEYTABLE_TYPE_CLR);
2333

S
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2334
		} else {
2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350
			/*
			 * TKIP uses four key cache entries (two for group
			 * keys):
			 * Michael MIC TX/RX keys are in different key cache
			 * entries (idx = main index + 64 for TX and
			 * main index + 32 + 96 for RX):
			 * key0 [31:0] = TX/RX MIC key [31:0]
			 * key1 [31:0] = reserved
			 * key2 [31:0] = TX/RX MIC key [63:32]
			 * key3 [31:0] = reserved
			 * key4 [31:0] = reserved
			 *
			 * Upper layer code will call this function separately
			 * for TX and RX keys when these registers offsets are
			 * used.
			 */
S
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2351
			u32 mic0, mic2;
2352

S
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2353 2354
			mic0 = get_unaligned_le32(k->kv_mic + 0);
			mic2 = get_unaligned_le32(k->kv_mic + 4);
2355 2356

			/* Write MIC key[31:0] */
S
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2357 2358
			REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
			REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2359 2360

			/* Write MIC key[63:32] */
S
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2361 2362
			REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
			REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2363 2364

			/* Write TX[63:32] and keyType(reserved) */
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2365 2366 2367 2368
			REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
			REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
				  AR_KEYTABLE_TYPE_CLR);
		}
2369 2370

		/* MAC address registers are reserved for the MIC entry */
S
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2371 2372
		REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2373 2374 2375 2376 2377 2378

		/*
		 * Write the correct (un-inverted) key[47:0] last to enable
		 * TKIP now that all other registers are set with correct
		 * values.
		 */
S
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2379 2380 2381
		REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
	} else {
2382
		/* Write key[47:0] */
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2383 2384
		REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2385 2386

		/* Write key[95:48] */
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2387 2388
		REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
		REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2389 2390

		/* Write key[127:96] and key type */
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2391 2392
		REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
		REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2393

2394
		/* Write MAC address for the entry */
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2395 2396
		(void) ath9k_hw_keysetmac(ah, entry, mac);
	}
2397 2398 2399

	return true;
}
2400
EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2401

2402
bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2403
{
2404
	if (entry < ah->caps.keycache_size) {
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2405 2406 2407 2408 2409
		u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
		if (val & AR_KEYTABLE_VALID)
			return true;
	}
	return false;
2410
}
2411
EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2412

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2413 2414 2415 2416
/******************************/
/* Power Management (Chipset) */
/******************************/

2417
static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2418
{
S
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2419 2420 2421 2422 2423 2424
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
		REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
			    AR_RTC_FORCE_WAKE_EN);
		if (!AR_SREV_9100(ah))
			REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2425

2426
		if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
S
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2427 2428
			REG_CLR_BIT(ah, (AR_RTC_RESET),
				    AR_RTC_RESET_EN);
S
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2429
	}
2430 2431
}

2432
static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2433
{
S
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2434 2435
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
2436
		struct ath9k_hw_capabilities *pCap = &ah->caps;
2437

S
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2438 2439 2440 2441 2442 2443
		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
			REG_WRITE(ah, AR_RTC_FORCE_WAKE,
				  AR_RTC_FORCE_WAKE_ON_INT);
		} else {
			REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
2444 2445 2446 2447
		}
	}
}

2448
static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2449
{
S
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2450 2451
	u32 val;
	int i;
2452

S
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2453 2454 2455 2456 2457 2458 2459
	if (setChip) {
		if ((REG_READ(ah, AR_RTC_STATUS) &
		     AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
			if (ath9k_hw_set_reset_reg(ah,
					   ATH9K_RESET_POWER_ON) != true) {
				return false;
			}
2460
			ath9k_hw_init_pll(ah, NULL);
S
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2461 2462 2463 2464
		}
		if (AR_SREV_9100(ah))
			REG_SET_BIT(ah, AR_RTC_RESET,
				    AR_RTC_RESET_EN);
2465

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2466 2467 2468
		REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
			    AR_RTC_FORCE_WAKE_EN);
		udelay(50);
2469

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2470 2471 2472 2473 2474 2475 2476
		for (i = POWER_UP_TIME / 50; i > 0; i--) {
			val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
			if (val == AR_RTC_STATUS_ON)
				break;
			udelay(50);
			REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
2477
		}
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2478
		if (i == 0) {
2479 2480 2481
			ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
				  "Failed to wakeup in %uus\n",
				  POWER_UP_TIME / 20);
S
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2482
			return false;
2483 2484 2485
		}
	}

S
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2486
	REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2487

S
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2488
	return true;
2489 2490
}

2491
bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2492
{
2493
	struct ath_common *common = ath9k_hw_common(ah);
2494
	int status = true, setChip = true;
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2495 2496 2497 2498 2499 2500 2501
	static const char *modes[] = {
		"AWAKE",
		"FULL-SLEEP",
		"NETWORK SLEEP",
		"UNDEFINED"
	};

2502 2503 2504
	if (ah->power_mode == mode)
		return status;

2505 2506
	ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
		  modes[ah->power_mode], modes[mode]);
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2507 2508 2509 2510 2511 2512 2513

	switch (mode) {
	case ATH9K_PM_AWAKE:
		status = ath9k_hw_set_power_awake(ah, setChip);
		break;
	case ATH9K_PM_FULL_SLEEP:
		ath9k_set_power_sleep(ah, setChip);
2514
		ah->chip_fullsleep = true;
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2515 2516 2517 2518
		break;
	case ATH9K_PM_NETWORK_SLEEP:
		ath9k_set_power_network_sleep(ah, setChip);
		break;
2519
	default:
2520 2521
		ath_print(common, ATH_DBG_FATAL,
			  "Unknown power mode %u\n", mode);
2522 2523
		return false;
	}
2524
	ah->power_mode = mode;
S
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2525 2526

	return status;
2527
}
2528
EXPORT_SYMBOL(ath9k_hw_setpower);
2529

2530 2531 2532 2533 2534 2535 2536 2537 2538
/*
 * Helper for ASPM support.
 *
 * Disable PLL when in L0s as well as receiver clock when in L1.
 * This power saving option must be enabled through the SerDes.
 *
 * Programming the SerDes must go through the same 288 bit serial shift
 * register as the other analog registers.  Hence the 9 writes.
 */
V
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2539
void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2540
{
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2541
	u8 i;
V
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2542
	u32 val;
2543

2544
	if (ah->is_pciexpress != true)
S
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2545
		return;
2546

2547
	/* Do not touch SerDes registers */
2548
	if (ah->config.pcie_powersave_enable == 2)
S
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2549 2550
		return;

2551
	/* Nothing to do on restore for 11N */
V
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2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577
	if (!restore) {
		if (AR_SREV_9280_20_OR_LATER(ah)) {
			/*
			 * AR9280 2.0 or later chips use SerDes values from the
			 * initvals.h initialized depending on chipset during
			 * ath9k_hw_init()
			 */
			for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
				REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
					  INI_RA(&ah->iniPcieSerdes, i, 1));
			}
		} else if (AR_SREV_9280(ah) &&
			   (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
			REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);

			/* RX shut off when elecidle is asserted */
			REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);

			/* Shut off CLKREQ active in L1 */
			if (ah->config.pcie_clock_req)
				REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
			else
				REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
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2578

V
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2579 2580 2581
			REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
S
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2582

V
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2583 2584
			/* Load the new settings */
			REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
S
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2585

V
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2586 2587 2588
		} else {
			REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
S
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2589

V
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2590 2591 2592 2593
			/* RX shut off when elecidle is asserted */
			REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
S
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2594

V
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2595 2596 2597 2598 2599
			/*
			 * Ignore ah->ah_config.pcie_clock_req setting for
			 * pre-AR9280 11n
			 */
			REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2600

V
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2601 2602 2603
			REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2604

V
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2605 2606 2607
			/* Load the new settings */
			REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
		}
2608

V
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2609
		udelay(1000);
2610

V
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2611 2612
		/* set bit 19 to allow forcing of pcie core into L1 state */
		REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2613

V
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2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635
		/* Several PCIe massages to ensure proper behaviour */
		if (ah->config.pcie_waen) {
			val = ah->config.pcie_waen;
			if (!power_off)
				val &= (~AR_WA_D3_L1_DISABLE);
		} else {
			if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
			    AR_SREV_9287(ah)) {
				val = AR9285_WA_DEFAULT;
				if (!power_off)
					val &= (~AR_WA_D3_L1_DISABLE);
			} else if (AR_SREV_9280(ah)) {
				/*
				 * On AR9280 chips bit 22 of 0x4004 needs to be
				 * set otherwise card may disappear.
				 */
				val = AR9280_WA_DEFAULT;
				if (!power_off)
					val &= (~AR_WA_D3_L1_DISABLE);
			} else
				val = AR_WA_DEFAULT;
		}
2636

V
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2637 2638
		REG_WRITE(ah, AR_WA, val);
	}
S
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2639

V
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2640
	if (power_off) {
2641
		/*
V
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2642 2643 2644 2645
		 * Set PCIe workaround bits
		 * bit 14 in WA register (disable L1) should only
		 * be set when device enters D3 and be cleared
		 * when device comes back to D0.
2646
		 */
V
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2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658
		if (ah->config.pcie_waen) {
			if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
				REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
		} else {
			if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
			      AR_SREV_9287(ah)) &&
			     (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
			    (AR_SREV_9280(ah) &&
			     (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
				REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
			}
		}
S
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2659
	}
2660
}
2661
EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2662

S
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2663 2664 2665 2666
/**********************/
/* Interrupt Handling */
/**********************/

2667
bool ath9k_hw_intrpend(struct ath_hw *ah)
2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684
{
	u32 host_isr;

	if (AR_SREV_9100(ah))
		return true;

	host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
	if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
		return true;

	host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
	if ((host_isr & AR_INTR_SYNC_DEFAULT)
	    && (host_isr != AR_INTR_SPURIOUS))
		return true;

	return false;
}
2685
EXPORT_SYMBOL(ath9k_hw_intrpend);
2686

2687
bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2688 2689 2690
{
	u32 isr = 0;
	u32 mask2 = 0;
2691
	struct ath9k_hw_capabilities *pCap = &ah->caps;
2692 2693
	u32 sync_cause = 0;
	bool fatal_int = false;
2694
	struct ath_common *common = ath9k_hw_common(ah);
2695 2696 2697 2698 2699 2700 2701 2702 2703

	if (!AR_SREV_9100(ah)) {
		if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
			if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
			    == AR_RTC_STATUS_ON) {
				isr = REG_READ(ah, AR_ISR);
			}
		}

S
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2704 2705
		sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
			AR_INTR_SYNC_DEFAULT;
2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731

		*masked = 0;

		if (!isr && !sync_cause)
			return false;
	} else {
		*masked = 0;
		isr = REG_READ(ah, AR_ISR);
	}

	if (isr) {
		if (isr & AR_ISR_BCNMISC) {
			u32 isr2;
			isr2 = REG_READ(ah, AR_ISR_S2);
			if (isr2 & AR_ISR_S2_TIM)
				mask2 |= ATH9K_INT_TIM;
			if (isr2 & AR_ISR_S2_DTIM)
				mask2 |= ATH9K_INT_DTIM;
			if (isr2 & AR_ISR_S2_DTIMSYNC)
				mask2 |= ATH9K_INT_DTIMSYNC;
			if (isr2 & (AR_ISR_S2_CABEND))
				mask2 |= ATH9K_INT_CABEND;
			if (isr2 & AR_ISR_S2_GTT)
				mask2 |= ATH9K_INT_GTT;
			if (isr2 & AR_ISR_S2_CST)
				mask2 |= ATH9K_INT_CST;
2732 2733
			if (isr2 & AR_ISR_S2_TSFOOR)
				mask2 |= ATH9K_INT_TSFOOR;
2734 2735 2736 2737 2738 2739 2740 2741 2742 2743
		}

		isr = REG_READ(ah, AR_ISR_RAC);
		if (isr == 0xffffffff) {
			*masked = 0;
			return false;
		}

		*masked = isr & ATH9K_INT_COMMON;

S
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2744
		if (ah->config.rx_intr_mitigation) {
2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758
			if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
				*masked |= ATH9K_INT_RX;
		}

		if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
			*masked |= ATH9K_INT_RX;
		if (isr &
		    (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
		     AR_ISR_TXEOL)) {
			u32 s0_s, s1_s;

			*masked |= ATH9K_INT_TX;

			s0_s = REG_READ(ah, AR_ISR_S0_S);
2759 2760
			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2761 2762

			s1_s = REG_READ(ah, AR_ISR_S1_S);
2763 2764
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2765 2766 2767
		}

		if (isr & AR_ISR_RXORN) {
2768 2769
			ath_print(common, ATH_DBG_INTERRUPT,
				  "receive FIFO overrun interrupt\n");
2770 2771 2772
		}

		if (!AR_SREV_9100(ah)) {
2773
			if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2774 2775 2776 2777 2778 2779 2780 2781
				u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
				if (isr5 & AR_ISR_S5_TIM_TIMER)
					*masked |= ATH9K_INT_TIM_TIMER;
			}
		}

		*masked |= mask2;
	}
S
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2782

2783 2784
	if (AR_SREV_9100(ah))
		return true;
S
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2785

2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802
	if (isr & AR_ISR_GENTMR) {
		u32 s5_s;

		s5_s = REG_READ(ah, AR_ISR_S5_S);
		if (isr & AR_ISR_GENTMR) {
			ah->intr_gen_timer_trigger =
				MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);

			ah->intr_gen_timer_thresh =
				MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);

			if (ah->intr_gen_timer_trigger)
				*masked |= ATH9K_INT_GENTIMER;

		}
	}

2803 2804 2805 2806 2807 2808 2809 2810
	if (sync_cause) {
		fatal_int =
			(sync_cause &
			 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
			? true : false;

		if (fatal_int) {
			if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2811 2812
				ath_print(common, ATH_DBG_ANY,
					  "received PCI FATAL interrupt\n");
2813 2814
			}
			if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2815 2816
				ath_print(common, ATH_DBG_ANY,
					  "received PCI PERR interrupt\n");
2817
			}
2818
			*masked |= ATH9K_INT_FATAL;
2819 2820
		}
		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2821 2822
			ath_print(common, ATH_DBG_INTERRUPT,
				  "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2823 2824 2825 2826 2827
			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
			REG_WRITE(ah, AR_RC, 0);
			*masked |= ATH9K_INT_FATAL;
		}
		if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2828 2829
			ath_print(common, ATH_DBG_INTERRUPT,
				  "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2830 2831 2832 2833 2834
		}

		REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
		(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
	}
S
Sujith 已提交
2835

2836 2837
	return true;
}
2838
EXPORT_SYMBOL(ath9k_hw_getisr);
2839

2840
enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2841
{
2842
	u32 omask = ah->mask_reg;
2843
	u32 mask, mask2;
2844
	struct ath9k_hw_capabilities *pCap = &ah->caps;
2845
	struct ath_common *common = ath9k_hw_common(ah);
2846

2847
	ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2848 2849

	if (omask & ATH9K_INT_GLOBAL) {
2850
		ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865
		REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
		(void) REG_READ(ah, AR_IER);
		if (!AR_SREV_9100(ah)) {
			REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
			(void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);

			REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
			(void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
		}
	}

	mask = ints & ATH9K_INT_COMMON;
	mask2 = 0;

	if (ints & ATH9K_INT_TX) {
2866
		if (ah->txok_interrupt_mask)
2867
			mask |= AR_IMR_TXOK;
2868
		if (ah->txdesc_interrupt_mask)
2869
			mask |= AR_IMR_TXDESC;
2870
		if (ah->txerr_interrupt_mask)
2871
			mask |= AR_IMR_TXERR;
2872
		if (ah->txeol_interrupt_mask)
2873 2874 2875 2876
			mask |= AR_IMR_TXEOL;
	}
	if (ints & ATH9K_INT_RX) {
		mask |= AR_IMR_RXERR;
S
Sujith 已提交
2877
		if (ah->config.rx_intr_mitigation)
2878 2879 2880
			mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
		else
			mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2881
		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893
			mask |= AR_IMR_GENTMR;
	}

	if (ints & (ATH9K_INT_BMISC)) {
		mask |= AR_IMR_BCNMISC;
		if (ints & ATH9K_INT_TIM)
			mask2 |= AR_IMR_S2_TIM;
		if (ints & ATH9K_INT_DTIM)
			mask2 |= AR_IMR_S2_DTIM;
		if (ints & ATH9K_INT_DTIMSYNC)
			mask2 |= AR_IMR_S2_DTIMSYNC;
		if (ints & ATH9K_INT_CABEND)
2894 2895 2896
			mask2 |= AR_IMR_S2_CABEND;
		if (ints & ATH9K_INT_TSFOOR)
			mask2 |= AR_IMR_S2_TSFOOR;
2897 2898 2899 2900 2901 2902 2903 2904 2905 2906
	}

	if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
		mask |= AR_IMR_BCNMISC;
		if (ints & ATH9K_INT_GTT)
			mask2 |= AR_IMR_S2_GTT;
		if (ints & ATH9K_INT_CST)
			mask2 |= AR_IMR_S2_CST;
	}

2907
	ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2908
	REG_WRITE(ah, AR_IMR, mask);
2909 2910 2911 2912 2913
	ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
			   AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
			   AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
	ah->imrs2_reg |= mask2;
	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2914
	ah->mask_reg = ints;
2915

2916
	if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2917 2918 2919 2920 2921 2922 2923
		if (ints & ATH9K_INT_TIM_TIMER)
			REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
		else
			REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
	}

	if (ints & ATH9K_INT_GLOBAL) {
2924
		ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936
		REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
		if (!AR_SREV_9100(ah)) {
			REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
				  AR_INTR_MAC_IRQ);
			REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);


			REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
				  AR_INTR_SYNC_DEFAULT);
			REG_WRITE(ah, AR_INTR_SYNC_MASK,
				  AR_INTR_SYNC_DEFAULT);
		}
2937 2938
		ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
			  REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2939 2940 2941 2942
	}

	return omask;
}
2943
EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2944

S
Sujith 已提交
2945 2946 2947 2948
/*******************/
/* Beacon Handling */
/*******************/

2949
void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2950 2951 2952
{
	int flags = 0;

2953
	ah->beacon_interval = beacon_period;
2954

2955
	switch (ah->opmode) {
2956 2957
	case NL80211_IFTYPE_STATION:
	case NL80211_IFTYPE_MONITOR:
2958 2959 2960 2961 2962
		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
		REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
		flags |= AR_TBTT_TIMER_EN;
		break;
2963
	case NL80211_IFTYPE_ADHOC:
2964
	case NL80211_IFTYPE_MESH_POINT:
2965 2966 2967 2968
		REG_SET_BIT(ah, AR_TXCFG,
			    AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
		REG_WRITE(ah, AR_NEXT_NDP_TIMER,
			  TU_TO_USEC(next_beacon +
2969 2970
				     (ah->atim_window ? ah->
				      atim_window : 1)));
2971
		flags |= AR_NDP_TIMER_EN;
2972
	case NL80211_IFTYPE_AP:
2973 2974 2975
		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
			  TU_TO_USEC(next_beacon -
2976
				     ah->config.
2977
				     dma_beacon_response_time));
2978 2979
		REG_WRITE(ah, AR_NEXT_SWBA,
			  TU_TO_USEC(next_beacon -
2980
				     ah->config.
2981
				     sw_beacon_response_time));
2982 2983 2984
		flags |=
			AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
		break;
2985
	default:
2986 2987 2988
		ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
			  "%s: unsupported opmode: %d\n",
			  __func__, ah->opmode);
2989 2990
		return;
		break;
2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004
	}

	REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));

	beacon_period &= ~ATH9K_BEACON_ENA;
	if (beacon_period & ATH9K_BEACON_RESET_TSF) {
		ath9k_hw_reset_tsf(ah);
	}

	REG_SET_BIT(ah, AR_TIMER_MODE, flags);
}
3005
EXPORT_SYMBOL(ath9k_hw_beaconinit);
3006

3007
void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
S
Sujith 已提交
3008
				    const struct ath9k_beacon_state *bs)
3009 3010
{
	u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3011
	struct ath9k_hw_capabilities *pCap = &ah->caps;
3012
	struct ath_common *common = ath9k_hw_common(ah);
3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037

	REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));

	REG_WRITE(ah, AR_BEACON_PERIOD,
		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));

	REG_RMW_FIELD(ah, AR_RSSI_THR,
		      AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);

	beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;

	if (bs->bs_sleepduration > beaconintval)
		beaconintval = bs->bs_sleepduration;

	dtimperiod = bs->bs_dtimperiod;
	if (bs->bs_sleepduration > dtimperiod)
		dtimperiod = bs->bs_sleepduration;

	if (beaconintval == dtimperiod)
		nextTbtt = bs->bs_nextdtim;
	else
		nextTbtt = bs->bs_nexttbtt;

3038 3039 3040 3041
	ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
	ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
	ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
	ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3042

S
Sujith 已提交
3043 3044 3045
	REG_WRITE(ah, AR_NEXT_DTIM,
		  TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
	REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3046

S
Sujith 已提交
3047 3048 3049
	REG_WRITE(ah, AR_SLEEP1,
		  SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
		  | AR_SLEEP1_ASSUME_DTIM);
3050

S
Sujith 已提交
3051 3052 3053 3054
	if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
		beacontimeout = (BEACON_TIMEOUT_VAL << 3);
	else
		beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3055

S
Sujith 已提交
3056 3057
	REG_WRITE(ah, AR_SLEEP2,
		  SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3058

S
Sujith 已提交
3059 3060
	REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
	REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3061

S
Sujith 已提交
3062 3063 3064
	REG_SET_BIT(ah, AR_TIMER_MODE,
		    AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
		    AR_DTIM_TIMER_EN);
3065

3066 3067
	/* TSF Out of Range Threshold */
	REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3068
}
3069
EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3070

S
Sujith 已提交
3071 3072 3073 3074
/*******************/
/* HW Capabilities */
/*******************/

3075
int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3076
{
3077
	struct ath9k_hw_capabilities *pCap = &ah->caps;
3078
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3079
	struct ath_common *common = ath9k_hw_common(ah);
3080
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3081

S
Sujith 已提交
3082
	u16 capField = 0, eeval;
3083

S
Sujith 已提交
3084
	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3085
	regulatory->current_rd = eeval;
3086

S
Sujith 已提交
3087
	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3088 3089
	if (AR_SREV_9285_10_OR_LATER(ah))
		eeval |= AR9285_RDEXT_DEFAULT;
3090
	regulatory->current_rd_ext = eeval;
3091

S
Sujith 已提交
3092
	capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
S
Sujith 已提交
3093

3094
	if (ah->opmode != NL80211_IFTYPE_AP &&
3095
	    ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3096 3097 3098 3099 3100
		if (regulatory->current_rd == 0x64 ||
		    regulatory->current_rd == 0x65)
			regulatory->current_rd += 5;
		else if (regulatory->current_rd == 0x41)
			regulatory->current_rd = 0x43;
3101 3102
		ath_print(common, ATH_DBG_REGULATORY,
			  "regdomain mapped to 0x%x\n", regulatory->current_rd);
S
Sujith 已提交
3103
	}
3104

S
Sujith 已提交
3105
	eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3106 3107 3108 3109 3110 3111
	if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
		ath_print(common, ATH_DBG_FATAL,
			  "no band has been marked as supported in EEPROM.\n");
		return -EINVAL;
	}

S
Sujith 已提交
3112
	bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3113

S
Sujith 已提交
3114 3115
	if (eeval & AR5416_OPFLAGS_11A) {
		set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3116
		if (ah->config.ht_enable) {
S
Sujith 已提交
3117 3118 3119 3120 3121 3122 3123 3124 3125
			if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
				set_bit(ATH9K_MODE_11NA_HT20,
					pCap->wireless_modes);
			if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
				set_bit(ATH9K_MODE_11NA_HT40PLUS,
					pCap->wireless_modes);
				set_bit(ATH9K_MODE_11NA_HT40MINUS,
					pCap->wireless_modes);
			}
3126 3127 3128
		}
	}

S
Sujith 已提交
3129 3130
	if (eeval & AR5416_OPFLAGS_11G) {
		set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3131
		if (ah->config.ht_enable) {
S
Sujith 已提交
3132 3133 3134 3135 3136 3137 3138 3139 3140 3141
			if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
				set_bit(ATH9K_MODE_11NG_HT20,
					pCap->wireless_modes);
			if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
				set_bit(ATH9K_MODE_11NG_HT40PLUS,
					pCap->wireless_modes);
				set_bit(ATH9K_MODE_11NG_HT40MINUS,
					pCap->wireless_modes);
			}
		}
3142
	}
S
Sujith 已提交
3143

S
Sujith 已提交
3144
	pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3145 3146 3147 3148
	/*
	 * For AR9271 we will temporarilly uses the rx chainmax as read from
	 * the EEPROM.
	 */
3149
	if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3150 3151 3152
	    !(eeval & AR5416_OPFLAGS_11A) &&
	    !(AR_SREV_9271(ah)))
		/* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3153 3154
		pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
	else
3155
		/* Use rx_chainmask from EEPROM. */
3156
		pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3157

3158
	if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3159
		ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3160

S
Sujith 已提交
3161 3162
	pCap->low_2ghz_chan = 2312;
	pCap->high_2ghz_chan = 2732;
3163

S
Sujith 已提交
3164 3165
	pCap->low_5ghz_chan = 4920;
	pCap->high_5ghz_chan = 6100;
3166

S
Sujith 已提交
3167 3168 3169
	pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3170

S
Sujith 已提交
3171 3172 3173
	pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3174

3175
	if (ah->config.ht_enable)
S
Sujith 已提交
3176 3177 3178
		pCap->hw_caps |= ATH9K_HW_CAP_HT;
	else
		pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3179

S
Sujith 已提交
3180 3181 3182 3183
	pCap->hw_caps |= ATH9K_HW_CAP_GTT;
	pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
	pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
	pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3184

S
Sujith 已提交
3185 3186 3187 3188 3189
	if (capField & AR_EEPROM_EEPCAP_MAXQCU)
		pCap->total_queues =
			MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
	else
		pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3190

S
Sujith 已提交
3191 3192 3193 3194 3195
	if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
		pCap->keycache_size =
			1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
	else
		pCap->keycache_size = AR_KEYTABLE_SIZE;
3196

S
Sujith 已提交
3197
	pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3198 3199 3200 3201 3202

	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
		pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
	else
		pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3203

3204 3205 3206
	if (AR_SREV_9271(ah))
		pCap->num_gpio_pins = AR9271_NUM_GPIO;
	else if (AR_SREV_9285_10_OR_LATER(ah))
3207 3208
		pCap->num_gpio_pins = AR9285_NUM_GPIO;
	else if (AR_SREV_9280_10_OR_LATER(ah))
S
Sujith 已提交
3209 3210 3211
		pCap->num_gpio_pins = AR928X_NUM_GPIO;
	else
		pCap->num_gpio_pins = AR_NUM_GPIO;
3212

S
Sujith 已提交
3213 3214 3215 3216 3217
	if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
		pCap->hw_caps |= ATH9K_HW_CAP_CST;
		pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
	} else {
		pCap->rts_aggr_limit = (8 * 1024);
3218 3219
	}

S
Sujith 已提交
3220 3221
	pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;

3222
#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3223 3224 3225 3226 3227 3228
	ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
	if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
		ah->rfkill_gpio =
			MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
		ah->rfkill_polarity =
			MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
S
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3229 3230

		pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3231
	}
S
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3232
#endif
3233

3234
	pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3235

3236
	if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
S
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3237 3238 3239
		pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
	else
		pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3240

3241
	if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
S
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3242 3243 3244 3245 3246
		pCap->reg_cap =
			AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
			AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
			AR_EEPROM_EEREGCAP_EN_KK_U2 |
			AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3247
	} else {
S
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3248 3249 3250
		pCap->reg_cap =
			AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
			AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3251 3252
	}

3253 3254 3255 3256
	/* Advertise midband for AR5416 with FCC midband set in eeprom */
	if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
	    AR_SREV_5416(ah))
		pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
S
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3257 3258

	pCap->num_antcfg_5ghz =
S
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3259
		ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
S
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3260
	pCap->num_antcfg_2ghz =
S
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3261
		ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3262

3263
	if (AR_SREV_9280_10_OR_LATER(ah) &&
3264
	    ath9k_hw_btcoex_supported(ah)) {
3265 3266
		btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
		btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3267

3268
		if (AR_SREV_9285(ah)) {
3269 3270
			btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
			btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3271
		} else {
3272
			btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3273
		}
3274
	} else {
3275
		btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3276
	}
3277 3278

	return 0;
3279 3280
}

3281
bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
S
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3282
			    u32 capability, u32 *result)
3283
{
3284
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
S
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3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302
	switch (type) {
	case ATH9K_CAP_CIPHER:
		switch (capability) {
		case ATH9K_CIPHER_AES_CCM:
		case ATH9K_CIPHER_AES_OCB:
		case ATH9K_CIPHER_TKIP:
		case ATH9K_CIPHER_WEP:
		case ATH9K_CIPHER_MIC:
		case ATH9K_CIPHER_CLR:
			return true;
		default:
			return false;
		}
	case ATH9K_CAP_TKIP_MIC:
		switch (capability) {
		case 0:
			return true;
		case 1:
3303
			return (ah->sta_id1_defaults &
S
Sujith 已提交
3304 3305 3306 3307
				AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
			false;
		}
	case ATH9K_CAP_TKIP_SPLIT:
3308
		return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
S
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3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321
			false : true;
	case ATH9K_CAP_DIVERSITY:
		return (REG_READ(ah, AR_PHY_CCK_DETECT) &
			AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
			true : false;
	case ATH9K_CAP_MCAST_KEYSRCH:
		switch (capability) {
		case 0:
			return true;
		case 1:
			if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
				return false;
			} else {
3322
				return (ah->sta_id1_defaults &
S
Sujith 已提交
3323 3324 3325 3326 3327 3328 3329 3330 3331 3332
					AR_STA_ID1_MCAST_KSRCH) ? true :
					false;
			}
		}
		return false;
	case ATH9K_CAP_TXPOW:
		switch (capability) {
		case 0:
			return 0;
		case 1:
3333
			*result = regulatory->power_limit;
S
Sujith 已提交
3334 3335
			return 0;
		case 2:
3336
			*result = regulatory->max_power_level;
S
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3337 3338
			return 0;
		case 3:
3339
			*result = regulatory->tp_scale;
S
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3340 3341 3342
			return 0;
		}
		return false;
3343 3344 3345 3346
	case ATH9K_CAP_DS:
		return (AR_SREV_9280_20_OR_LATER(ah) &&
			(ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
			? false : true;
S
Sujith 已提交
3347 3348
	default:
		return false;
3349 3350
	}
}
3351
EXPORT_SYMBOL(ath9k_hw_getcapability);
3352

3353
bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
S
Sujith 已提交
3354
			    u32 capability, u32 setting, int *status)
3355
{
S
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3356
	u32 v;
3357

S
Sujith 已提交
3358 3359 3360
	switch (type) {
	case ATH9K_CAP_TKIP_MIC:
		if (setting)
3361
			ah->sta_id1_defaults |=
S
Sujith 已提交
3362 3363
				AR_STA_ID1_CRPT_MIC_ENABLE;
		else
3364
			ah->sta_id1_defaults &=
S
Sujith 已提交
3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376
				~AR_STA_ID1_CRPT_MIC_ENABLE;
		return true;
	case ATH9K_CAP_DIVERSITY:
		v = REG_READ(ah, AR_PHY_CCK_DETECT);
		if (setting)
			v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
		else
			v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
		REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
		return true;
	case ATH9K_CAP_MCAST_KEYSRCH:
		if (setting)
3377
			ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
S
Sujith 已提交
3378
		else
3379
			ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
S
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3380 3381 3382
		return true;
	default:
		return false;
3383 3384
	}
}
3385
EXPORT_SYMBOL(ath9k_hw_setcapability);
3386

S
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3387 3388 3389
/****************************/
/* GPIO / RFKILL / Antennae */
/****************************/
3390

3391
static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
S
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3392 3393 3394 3395
					 u32 gpio, u32 type)
{
	int addr;
	u32 gpio_shift, tmp;
3396

S
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3397 3398 3399 3400 3401 3402
	if (gpio > 11)
		addr = AR_GPIO_OUTPUT_MUX3;
	else if (gpio > 5)
		addr = AR_GPIO_OUTPUT_MUX2;
	else
		addr = AR_GPIO_OUTPUT_MUX1;
3403

S
Sujith 已提交
3404
	gpio_shift = (gpio % 6) * 5;
3405

S
Sujith 已提交
3406 3407 3408 3409
	if (AR_SREV_9280_20_OR_LATER(ah)
	    || (addr != AR_GPIO_OUTPUT_MUX1)) {
		REG_RMW(ah, addr, (type << gpio_shift),
			(0x1f << gpio_shift));
3410
	} else {
S
Sujith 已提交
3411 3412 3413 3414 3415
		tmp = REG_READ(ah, addr);
		tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
		tmp &= ~(0x1f << gpio_shift);
		tmp |= (type << gpio_shift);
		REG_WRITE(ah, addr, tmp);
3416 3417 3418
	}
}

3419
void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3420
{
S
Sujith 已提交
3421
	u32 gpio_shift;
3422

3423
	BUG_ON(gpio >= ah->caps.num_gpio_pins);
3424

S
Sujith 已提交
3425
	gpio_shift = gpio << 1;
3426

S
Sujith 已提交
3427 3428 3429 3430
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
3431
}
3432
EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3433

3434
u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3435
{
3436 3437 3438
#define MS_REG_READ(x, y) \
	(MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))

3439
	if (gpio >= ah->caps.num_gpio_pins)
S
Sujith 已提交
3440
		return 0xffffffff;
3441

3442 3443 3444
	if (AR_SREV_9271(ah))
		return MS_REG_READ(AR9271, gpio) != 0;
	else if (AR_SREV_9287_10_OR_LATER(ah))
3445 3446
		return MS_REG_READ(AR9287, gpio) != 0;
	else if (AR_SREV_9285_10_OR_LATER(ah))
3447 3448 3449 3450 3451
		return MS_REG_READ(AR9285, gpio) != 0;
	else if (AR_SREV_9280_10_OR_LATER(ah))
		return MS_REG_READ(AR928X, gpio) != 0;
	else
		return MS_REG_READ(AR, gpio) != 0;
3452
}
3453
EXPORT_SYMBOL(ath9k_hw_gpio_get);
3454

3455
void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
S
Sujith 已提交
3456
			 u32 ah_signal_type)
3457
{
S
Sujith 已提交
3458
	u32 gpio_shift;
3459

S
Sujith 已提交
3460
	ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3461

S
Sujith 已提交
3462
	gpio_shift = 2 * gpio;
3463

S
Sujith 已提交
3464 3465 3466 3467
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
3468
}
3469
EXPORT_SYMBOL(ath9k_hw_cfg_output);
3470

3471
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3472
{
3473 3474 3475
	if (AR_SREV_9271(ah))
		val = ~val;

S
Sujith 已提交
3476 3477
	REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
		AR_GPIO_BIT(gpio));
3478
}
3479
EXPORT_SYMBOL(ath9k_hw_set_gpio);
3480

3481
u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3482
{
S
Sujith 已提交
3483
	return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3484
}
3485
EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3486

3487
void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3488
{
S
Sujith 已提交
3489
	REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3490
}
3491
EXPORT_SYMBOL(ath9k_hw_setantenna);
3492

S
Sujith 已提交
3493 3494 3495 3496
/*********************/
/* General Operation */
/*********************/

3497
u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3498
{
S
Sujith 已提交
3499 3500
	u32 bits = REG_READ(ah, AR_RX_FILTER);
	u32 phybits = REG_READ(ah, AR_PHY_ERR);
3501

S
Sujith 已提交
3502 3503 3504 3505
	if (phybits & AR_PHY_ERR_RADAR)
		bits |= ATH9K_RX_FILTER_PHYRADAR;
	if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
		bits |= ATH9K_RX_FILTER_PHYERR;
S
Sujith 已提交
3506

S
Sujith 已提交
3507
	return bits;
3508
}
3509
EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3510

3511
void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3512
{
S
Sujith 已提交
3513
	u32 phybits;
3514

S
Sujith 已提交
3515 3516
	REG_WRITE(ah, AR_RX_FILTER, bits);

S
Sujith 已提交
3517 3518 3519 3520 3521 3522
	phybits = 0;
	if (bits & ATH9K_RX_FILTER_PHYRADAR)
		phybits |= AR_PHY_ERR_RADAR;
	if (bits & ATH9K_RX_FILTER_PHYERR)
		phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
	REG_WRITE(ah, AR_PHY_ERR, phybits);
3523

S
Sujith 已提交
3524 3525 3526 3527 3528 3529 3530
	if (phybits)
		REG_WRITE(ah, AR_RXCFG,
			  REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
	else
		REG_WRITE(ah, AR_RXCFG,
			  REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
}
3531
EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3532

3533
bool ath9k_hw_phy_disable(struct ath_hw *ah)
S
Sujith 已提交
3534
{
3535 3536 3537 3538 3539
	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
		return false;

	ath9k_hw_init_pll(ah, NULL);
	return true;
S
Sujith 已提交
3540
}
3541
EXPORT_SYMBOL(ath9k_hw_phy_disable);
3542

3543
bool ath9k_hw_disable(struct ath_hw *ah)
S
Sujith 已提交
3544
{
3545
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
S
Sujith 已提交
3546
		return false;
3547

3548 3549 3550 3551 3552
	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
		return false;

	ath9k_hw_init_pll(ah, NULL);
	return true;
3553
}
3554
EXPORT_SYMBOL(ath9k_hw_disable);
3555

3556
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3557
{
3558
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3559
	struct ath9k_channel *chan = ah->curchan;
3560
	struct ieee80211_channel *channel = chan->chan;
3561

3562
	regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3563

3564
	ah->eep_ops->set_txpower(ah, chan,
3565
				 ath9k_regd_get_ctl(regulatory, chan),
3566 3567 3568
				 channel->max_antenna_gain * 2,
				 channel->max_power * 2,
				 min((u32) MAX_RATE_POWER,
3569
				 (u32) regulatory->power_limit));
3570
}
3571
EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3572

3573
void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3574
{
3575
	memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3576
}
3577
EXPORT_SYMBOL(ath9k_hw_setmac);
3578

3579
void ath9k_hw_setopmode(struct ath_hw *ah)
3580
{
3581
	ath9k_hw_set_operating_mode(ah, ah->opmode);
3582
}
3583
EXPORT_SYMBOL(ath9k_hw_setopmode);
3584

3585
void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3586
{
S
Sujith 已提交
3587 3588
	REG_WRITE(ah, AR_MCAST_FIL0, filter0);
	REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3589
}
3590
EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3591

3592
void ath9k_hw_write_associd(struct ath_hw *ah)
3593
{
3594 3595 3596 3597 3598
	struct ath_common *common = ath9k_hw_common(ah);

	REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
	REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
		  ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3599
}
3600
EXPORT_SYMBOL(ath9k_hw_write_associd);
3601

3602
u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3603
{
S
Sujith 已提交
3604
	u64 tsf;
3605

S
Sujith 已提交
3606 3607
	tsf = REG_READ(ah, AR_TSF_U32);
	tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3608

S
Sujith 已提交
3609 3610
	return tsf;
}
3611
EXPORT_SYMBOL(ath9k_hw_gettsf64);
3612

3613
void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3614 3615
{
	REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
A
Alina Friedrichsen 已提交
3616
	REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3617
}
3618
EXPORT_SYMBOL(ath9k_hw_settsf64);
3619

3620
void ath9k_hw_reset_tsf(struct ath_hw *ah)
S
Sujith 已提交
3621
{
3622 3623
	if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
			   AH_TSF_WRITE_TIMEOUT))
3624 3625
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3626

S
Sujith 已提交
3627 3628
	REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
}
3629
EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3630

S
Sujith 已提交
3631
void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
S
Sujith 已提交
3632 3633
{
	if (setting)
3634
		ah->misc_mode |= AR_PCU_TX_ADD_TSF;
S
Sujith 已提交
3635
	else
3636
		ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
S
Sujith 已提交
3637
}
3638
EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3639

3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654
/*
 *  Extend 15-bit time stamp from rx descriptor to
 *  a full 64-bit TSF using the current h/w TSF.
*/
u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
{
	u64 tsf;

	tsf = ath9k_hw_gettsf64(ah);
	if ((tsf & 0x7fff) < rstamp)
		tsf -= 0x8000;
	return (tsf & ~0x7fff) | rstamp;
}
EXPORT_SYMBOL(ath9k_hw_extend_tsf);

L
Luis R. Rodriguez 已提交
3655
void ath9k_hw_set11nmac2040(struct ath_hw *ah)
S
Sujith 已提交
3656
{
L
Luis R. Rodriguez 已提交
3657
	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
S
Sujith 已提交
3658 3659
	u32 macmode;

L
Luis R. Rodriguez 已提交
3660
	if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
S
Sujith 已提交
3661 3662 3663
		macmode = AR_2040_JOINED_RX_CLEAR;
	else
		macmode = 0;
3664

S
Sujith 已提交
3665
	REG_WRITE(ah, AR_2040_MODE, macmode);
3666
}
3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712

/* HW Generic timers configuration */

static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
{
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
	{AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
				AR_NDP2_TIMER_MODE, 0x0002},
	{AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
				AR_NDP2_TIMER_MODE, 0x0004},
	{AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
				AR_NDP2_TIMER_MODE, 0x0008},
	{AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
				AR_NDP2_TIMER_MODE, 0x0010},
	{AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
				AR_NDP2_TIMER_MODE, 0x0020},
	{AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
				AR_NDP2_TIMER_MODE, 0x0040},
	{AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
				AR_NDP2_TIMER_MODE, 0x0080}
};

/* HW generic timer primitives */

/* compute and clear index of rightmost 1 */
static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
{
	u32 b;

	b = *mask;
	b &= (0-b);
	*mask &= ~b;
	b *= debruijn32;
	b >>= 27;

	return timer_table->gen_timer_index[b];
}

3713
u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3714 3715 3716
{
	return REG_READ(ah, AR_TSF_L32);
}
3717
EXPORT_SYMBOL(ath9k_hw_gettsf32);
3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730

struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
					  void (*trigger)(void *),
					  void (*overflow)(void *),
					  void *arg,
					  u8 timer_index)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;

	timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);

	if (timer == NULL) {
3731 3732 3733
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "Failed to allocate memory"
			  "for hw timer[%d]\n", timer_index);
3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745
		return NULL;
	}

	/* allocate a hardware generic timer slot */
	timer_table->timers[timer_index] = timer;
	timer->index = timer_index;
	timer->trigger = trigger;
	timer->overflow = overflow;
	timer->arg = arg;

	return timer;
}
3746
EXPORT_SYMBOL(ath_gen_timer_alloc);
3747

3748 3749 3750 3751
void ath9k_hw_gen_timer_start(struct ath_hw *ah,
			      struct ath_gen_timer *timer,
			      u32 timer_next,
			      u32 timer_period)
3752 3753 3754 3755 3756 3757 3758 3759 3760 3761
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	u32 tsf;

	BUG_ON(!timer_period);

	set_bit(timer->index, &timer_table->timer_mask.timer_bits);

	tsf = ath9k_hw_gettsf32(ah);

3762 3763 3764
	ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
		  "curent tsf %x period %x"
		  "timer_next %x\n", tsf, timer_period, timer_next);
3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787

	/*
	 * Pull timer_next forward if the current TSF already passed it
	 * because of software latency
	 */
	if (timer_next < tsf)
		timer_next = tsf + timer_period;

	/*
	 * Program generic timer registers
	 */
	REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
		 timer_next);
	REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
		  timer_period);
	REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
		    gen_tmr_configuration[timer->index].mode_mask);

	/* Enable both trigger and thresh interrupt masks */
	REG_SET_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
}
3788
EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3789

3790
void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	if ((timer->index < AR_FIRST_NDP_TIMER) ||
		(timer->index >= ATH_MAX_GEN_TIMER)) {
		return;
	}

	/* Clear generic timer enable bits. */
	REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
			gen_tmr_configuration[timer->index].mode_mask);

	/* Disable both trigger and thresh interrupt masks */
	REG_CLR_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));

	clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
}
3810
EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3811 3812 3813 3814 3815 3816 3817 3818 3819

void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	/* free the hardware generic timer slot */
	timer_table->timers[timer->index] = NULL;
	kfree(timer);
}
3820
EXPORT_SYMBOL(ath_gen_timer_free);
3821 3822 3823 3824 3825 3826 3827 3828

/*
 * Generic Timer Interrupts handling
 */
void ath_gen_timer_isr(struct ath_hw *ah)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;
3829
	struct ath_common *common = ath9k_hw_common(ah);
3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843
	u32 trigger_mask, thresh_mask, index;

	/* get hardware generic timer interrupt status */
	trigger_mask = ah->intr_gen_timer_trigger;
	thresh_mask = ah->intr_gen_timer_thresh;
	trigger_mask &= timer_table->timer_mask.val;
	thresh_mask &= timer_table->timer_mask.val;

	trigger_mask &= ~thresh_mask;

	while (thresh_mask) {
		index = rightmost_index(timer_table, &thresh_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
3844 3845
		ath_print(common, ATH_DBG_HWTIMER,
			  "TSF overflow for Gen timer %d\n", index);
3846 3847 3848 3849 3850 3851 3852
		timer->overflow(timer->arg);
	}

	while (trigger_mask) {
		index = rightmost_index(timer_table, &trigger_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
3853 3854
		ath_print(common, ATH_DBG_HWTIMER,
			  "Gen timer[%d] trigger\n", index);
3855 3856 3857
		timer->trigger(timer->arg);
	}
}
3858
EXPORT_SYMBOL(ath_gen_timer_isr);
3859

3860 3861 3862 3863 3864 3865 3866 3867 3868 3869
/********/
/* HTC  */
/********/

void ath9k_hw_htc_resetinit(struct ath_hw *ah)
{
	ah->htc_reset_init = true;
}
EXPORT_SYMBOL(ath9k_hw_htc_resetinit);

3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881
static struct {
	u32 version;
	const char * name;
} ath_mac_bb_names[] = {
	/* Devices with external radios */
	{ AR_SREV_VERSION_5416_PCI,	"5416" },
	{ AR_SREV_VERSION_5416_PCIE,	"5418" },
	{ AR_SREV_VERSION_9100,		"9100" },
	{ AR_SREV_VERSION_9160,		"9160" },
	/* Single-chip solutions */
	{ AR_SREV_VERSION_9280,		"9280" },
	{ AR_SREV_VERSION_9285,		"9285" },
3882 3883
	{ AR_SREV_VERSION_9287,         "9287" },
	{ AR_SREV_VERSION_9271,         "9271" },
3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900
};

/* For devices with external radios */
static struct {
	u16 version;
	const char * name;
} ath_rf_names[] = {
	{ 0,				"5133" },
	{ AR_RAD5133_SREV_MAJOR,	"5133" },
	{ AR_RAD5122_SREV_MAJOR,	"5122" },
	{ AR_RAD2133_SREV_MAJOR,	"2133" },
	{ AR_RAD2122_SREV_MAJOR,	"2122" }
};

/*
 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
 */
3901
static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
		if (ath_mac_bb_names[i].version == mac_bb_version) {
			return ath_mac_bb_names[i].name;
		}
	}

	return "????";
}

/*
 * Return the RF name. "????" is returned if the RF is unknown.
 * Used for devices with external radios.
 */
3918
static const char *ath9k_hw_rf_name(u16 rf_version)
3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
		if (ath_rf_names[i].version == rf_version) {
			return ath_rf_names[i].name;
		}
	}

	return "????";
}
3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954

void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
{
	int used;

	/* chipsets >= AR9280 are single-chip */
	if (AR_SREV_9280_10_OR_LATER(ah)) {
		used = snprintf(hw_name, len,
			       "Atheros AR%s Rev:%x",
			       ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
			       ah->hw_version.macRev);
	}
	else {
		used = snprintf(hw_name, len,
			       "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
			       ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
			       ah->hw_version.macRev,
			       ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
						AR_RADIO_SREV_MAJOR)),
			       ah->hw_version.phyRev);
	}

	hw_name[used] = '\0';
}
EXPORT_SYMBOL(ath9k_hw_name);