spi-omap2-mcspi.c 37.8 KB
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/*
 * OMAP2 McSPI controller driver
 *
 * Copyright (C) 2005, 2006 Nokia Corporation
 * Author:	Samuel Ortiz <samuel.ortiz@nokia.com> and
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 *		Juha Yrj�l� <juha.yrjola@nokia.com>
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
#include <linux/omap-dma.h>
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#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
#include <linux/of_device.h>
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#include <linux/gcd.h>
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#include <linux/spi/spi.h>

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#include <linux/platform_data/spi-omap2-mcspi.h>
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#define OMAP2_MCSPI_MAX_FREQ		48000000
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#define OMAP2_MCSPI_MAX_DIVIDER		4096
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#define OMAP2_MCSPI_MAX_FIFODEPTH	64
#define OMAP2_MCSPI_MAX_FIFOWCNT	0xFFFF
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#define SPI_AUTOSUSPEND_TIMEOUT		2000
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#define OMAP2_MCSPI_REVISION		0x00
#define OMAP2_MCSPI_SYSSTATUS		0x14
#define OMAP2_MCSPI_IRQSTATUS		0x18
#define OMAP2_MCSPI_IRQENABLE		0x1c
#define OMAP2_MCSPI_WAKEUPENABLE	0x20
#define OMAP2_MCSPI_SYST		0x24
#define OMAP2_MCSPI_MODULCTRL		0x28
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#define OMAP2_MCSPI_XFERLEVEL		0x7c
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/* per-channel banks, 0x14 bytes each, first is: */
#define OMAP2_MCSPI_CHCONF0		0x2c
#define OMAP2_MCSPI_CHSTAT0		0x30
#define OMAP2_MCSPI_CHCTRL0		0x34
#define OMAP2_MCSPI_TX0			0x38
#define OMAP2_MCSPI_RX0			0x3c

/* per-register bitmasks: */
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#define OMAP2_MCSPI_IRQSTATUS_EOW	BIT(17)
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#define OMAP2_MCSPI_MODULCTRL_SINGLE	BIT(0)
#define OMAP2_MCSPI_MODULCTRL_MS	BIT(2)
#define OMAP2_MCSPI_MODULCTRL_STEST	BIT(3)
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#define OMAP2_MCSPI_CHCONF_PHA		BIT(0)
#define OMAP2_MCSPI_CHCONF_POL		BIT(1)
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#define OMAP2_MCSPI_CHCONF_CLKD_MASK	(0x0f << 2)
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#define OMAP2_MCSPI_CHCONF_EPOL		BIT(6)
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#define OMAP2_MCSPI_CHCONF_WL_MASK	(0x1f << 7)
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#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY	BIT(12)
#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY	BIT(13)
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#define OMAP2_MCSPI_CHCONF_TRM_MASK	(0x03 << 12)
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#define OMAP2_MCSPI_CHCONF_DMAW		BIT(14)
#define OMAP2_MCSPI_CHCONF_DMAR		BIT(15)
#define OMAP2_MCSPI_CHCONF_DPE0		BIT(16)
#define OMAP2_MCSPI_CHCONF_DPE1		BIT(17)
#define OMAP2_MCSPI_CHCONF_IS		BIT(18)
#define OMAP2_MCSPI_CHCONF_TURBO	BIT(19)
#define OMAP2_MCSPI_CHCONF_FORCE	BIT(20)
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#define OMAP2_MCSPI_CHCONF_FFET		BIT(27)
#define OMAP2_MCSPI_CHCONF_FFER		BIT(28)
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#define OMAP2_MCSPI_CHCONF_CLKG		BIT(29)
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#define OMAP2_MCSPI_CHSTAT_RXS		BIT(0)
#define OMAP2_MCSPI_CHSTAT_TXS		BIT(1)
#define OMAP2_MCSPI_CHSTAT_EOT		BIT(2)
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#define OMAP2_MCSPI_CHSTAT_TXFFE	BIT(3)
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#define OMAP2_MCSPI_CHCTRL_EN		BIT(0)
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#define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK	(0xff << 8)
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#define OMAP2_MCSPI_WAKEUPENABLE_WKEN	BIT(0)
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/* We have 2 DMA channels per CS, one for RX and one for TX */
struct omap2_mcspi_dma {
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	struct dma_chan *dma_tx;
	struct dma_chan *dma_rx;
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	int dma_tx_sync_dev;
	int dma_rx_sync_dev;

	struct completion dma_tx_completion;
	struct completion dma_rx_completion;
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	char dma_rx_ch_name[14];
	char dma_tx_ch_name[14];
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};

/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 * cache operations; better heuristics consider wordsize and bitrate.
 */
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#define DMA_MIN_BYTES			160
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/*
 * Used for context save and restore, structure members to be updated whenever
 * corresponding registers are modified.
 */
struct omap2_mcspi_regs {
	u32 modulctrl;
	u32 wakeupenable;
	struct list_head cs;
};

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struct omap2_mcspi {
	struct spi_master	*master;
	/* Virtual base address of the controller */
	void __iomem		*base;
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	unsigned long		phys;
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	/* SPI1 has 4 channels, while SPI2 has 2 */
	struct omap2_mcspi_dma	*dma_channels;
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	struct device		*dev;
	struct omap2_mcspi_regs ctx;
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	int			fifo_depth;
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	unsigned int		pin_dir:1;
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};

struct omap2_mcspi_cs {
	void __iomem		*base;
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	unsigned long		phys;
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	int			word_len;
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	struct list_head	node;
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	/* Context save and restore shadow register */
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	u32			chconf0, chctrl0;
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};

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static inline void mcspi_write_reg(struct spi_master *master,
		int idx, u32 val)
{
	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);

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	writel_relaxed(val, mcspi->base + idx);
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}

static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
{
	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);

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	return readl_relaxed(mcspi->base + idx);
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}

static inline void mcspi_write_cs_reg(const struct spi_device *spi,
		int idx, u32 val)
{
	struct omap2_mcspi_cs	*cs = spi->controller_state;

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	writel_relaxed(val, cs->base +  idx);
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}

static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
{
	struct omap2_mcspi_cs	*cs = spi->controller_state;

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	return readl_relaxed(cs->base + idx);
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}

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static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
{
	struct omap2_mcspi_cs *cs = spi->controller_state;

	return cs->chconf0;
}

static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
{
	struct omap2_mcspi_cs *cs = spi->controller_state;

	cs->chconf0 = val;
	mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
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	mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
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}

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static inline int mcspi_bytes_per_word(int word_len)
{
	if (word_len <= 8)
		return 1;
	else if (word_len <= 16)
		return 2;
	else /* word_len <= 32 */
		return 4;
}

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static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
		int is_read, int enable)
{
	u32 l, rw;

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	l = mcspi_cached_chconf0(spi);
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	if (is_read) /* 1 is read, 0 write */
		rw = OMAP2_MCSPI_CHCONF_DMAR;
	else
		rw = OMAP2_MCSPI_CHCONF_DMAW;

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	if (enable)
		l |= rw;
	else
		l &= ~rw;

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	mcspi_write_chconf0(spi, l);
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}

static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
{
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	struct omap2_mcspi_cs *cs = spi->controller_state;
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	u32 l;

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	l = cs->chctrl0;
	if (enable)
		l |= OMAP2_MCSPI_CHCTRL_EN;
	else
		l &= ~OMAP2_MCSPI_CHCTRL_EN;
	cs->chctrl0 = l;
	mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
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	/* Flash post-writes */
	mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
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}

static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
{
	u32 l;

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	l = mcspi_cached_chconf0(spi);
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	if (cs_active)
		l |= OMAP2_MCSPI_CHCONF_FORCE;
	else
		l &= ~OMAP2_MCSPI_CHCONF_FORCE;

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	mcspi_write_chconf0(spi, l);
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}

static void omap2_mcspi_set_master_mode(struct spi_master *master)
{
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	struct omap2_mcspi	*mcspi = spi_master_get_devdata(master);
	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
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	u32 l;

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	/*
	 * Setup when switching from (reset default) slave mode
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	 * to single-channel master mode
	 */
	l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
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	l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
	l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
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	mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
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	ctx->modulctrl = l;
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}

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static void omap2_mcspi_set_fifo(const struct spi_device *spi,
				struct spi_transfer *t, int enable)
{
	struct spi_master *master = spi->master;
	struct omap2_mcspi_cs *cs = spi->controller_state;
	struct omap2_mcspi *mcspi;
	unsigned int wcnt;
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	int max_fifo_depth, fifo_depth, bytes_per_word;
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	u32 chconf, xferlevel;

	mcspi = spi_master_get_devdata(master);

	chconf = mcspi_cached_chconf0(spi);
	if (enable) {
		bytes_per_word = mcspi_bytes_per_word(cs->word_len);
		if (t->len % bytes_per_word != 0)
			goto disable_fifo;

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		if (t->rx_buf != NULL && t->tx_buf != NULL)
			max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
		else
			max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;

		fifo_depth = gcd(t->len, max_fifo_depth);
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		if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
			goto disable_fifo;

		wcnt = t->len / bytes_per_word;
		if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
			goto disable_fifo;

		xferlevel = wcnt << 16;
		if (t->rx_buf != NULL) {
			chconf |= OMAP2_MCSPI_CHCONF_FFER;
			xferlevel |= (fifo_depth - 1) << 8;
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		}
		if (t->tx_buf != NULL) {
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			chconf |= OMAP2_MCSPI_CHCONF_FFET;
			xferlevel |= fifo_depth - 1;
		}

		mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
		mcspi_write_chconf0(spi, chconf);
		mcspi->fifo_depth = fifo_depth;

		return;
	}

disable_fifo:
	if (t->rx_buf != NULL)
		chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
	else
		chconf &= ~OMAP2_MCSPI_CHCONF_FFET;

	mcspi_write_chconf0(spi, chconf);
	mcspi->fifo_depth = 0;
}

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static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
{
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	struct spi_master	*spi_cntrl = mcspi->master;
	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
	struct omap2_mcspi_cs	*cs;
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	/* McSPI: context restore */
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	mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
	mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
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	list_for_each_entry(cs, &ctx->cs, node)
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		writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
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}
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static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
{
	unsigned long timeout;

	timeout = jiffies + msecs_to_jiffies(1000);
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	while (!(readl_relaxed(reg) & bit)) {
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		if (time_after(jiffies, timeout)) {
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			if (!(readl_relaxed(reg) & bit))
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				return -ETIMEDOUT;
			else
				return 0;
		}
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		cpu_relax();
	}
	return 0;
}

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static void omap2_mcspi_rx_callback(void *data)
{
	struct spi_device *spi = data;
	struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
	struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];

	/* We must disable the DMA RX request */
	omap2_mcspi_set_dma_req(spi, 1, 0);
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	complete(&mcspi_dma->dma_rx_completion);
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}

static void omap2_mcspi_tx_callback(void *data)
{
	struct spi_device *spi = data;
	struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
	struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];

	/* We must disable the DMA TX request */
	omap2_mcspi_set_dma_req(spi, 0, 0);
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	complete(&mcspi_dma->dma_tx_completion);
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}

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static void omap2_mcspi_tx_dma(struct spi_device *spi,
				struct spi_transfer *xfer,
				struct dma_slave_config cfg)
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{
	struct omap2_mcspi	*mcspi;
	struct omap2_mcspi_dma  *mcspi_dma;
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	unsigned int		count;
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	mcspi = spi_master_get_devdata(spi->master);
	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
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	count = xfer->len;
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	if (mcspi_dma->dma_tx) {
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		struct dma_async_tx_descriptor *tx;
		struct scatterlist sg;

		dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);

		sg_init_table(&sg, 1);
		sg_dma_address(&sg) = xfer->tx_dma;
		sg_dma_len(&sg) = xfer->len;

		tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
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		DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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		if (tx) {
			tx->callback = omap2_mcspi_tx_callback;
			tx->callback_param = spi;
			dmaengine_submit(tx);
		} else {
			/* FIXME: fall back to PIO? */
		}
	}
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	dma_async_issue_pending(mcspi_dma->dma_tx);
	omap2_mcspi_set_dma_req(spi, 0, 1);

}
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static unsigned
omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
				struct dma_slave_config cfg,
				unsigned es)
{
	struct omap2_mcspi	*mcspi;
	struct omap2_mcspi_dma  *mcspi_dma;
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	unsigned int		count, dma_count;
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	u32			l;
	int			elements = 0;
	int			word_len, element_count;
	struct omap2_mcspi_cs	*cs = spi->controller_state;
	mcspi = spi_master_get_devdata(spi->master);
	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
	count = xfer->len;
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	dma_count = xfer->len;

	if (mcspi->fifo_depth == 0)
		dma_count -= es;

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	word_len = cs->word_len;
	l = mcspi_cached_chconf0(spi);
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	if (word_len <= 8)
		element_count = count;
	else if (word_len <= 16)
		element_count = count >> 1;
	else /* word_len <= 32 */
		element_count = count >> 2;

	if (mcspi_dma->dma_rx) {
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		struct dma_async_tx_descriptor *tx;
		struct scatterlist sg;

		dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);

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		if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
			dma_count -= es;
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		sg_init_table(&sg, 1);
		sg_dma_address(&sg) = xfer->rx_dma;
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		sg_dma_len(&sg) = dma_count;
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		tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
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				DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
				DMA_CTRL_ACK);
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		if (tx) {
			tx->callback = omap2_mcspi_rx_callback;
			tx->callback_param = spi;
			dmaengine_submit(tx);
		} else {
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				/* FIXME: fall back to PIO? */
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		}
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	}

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	dma_async_issue_pending(mcspi_dma->dma_rx);
	omap2_mcspi_set_dma_req(spi, 1, 1);
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	wait_for_completion(&mcspi_dma->dma_rx_completion);
	dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
			 DMA_FROM_DEVICE);
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	if (mcspi->fifo_depth > 0)
		return count;

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	omap2_mcspi_set_enable(spi, 0);
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	elements = element_count - 1;
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	if (l & OMAP2_MCSPI_CHCONF_TURBO) {
		elements--;
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		if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
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				   & OMAP2_MCSPI_CHSTAT_RXS)) {
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			u32 w;

			w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
			if (word_len <= 8)
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				((u8 *)xfer->rx_buf)[elements++] = w;
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			else if (word_len <= 16)
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				((u16 *)xfer->rx_buf)[elements++] = w;
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			else /* word_len <= 32 */
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				((u32 *)xfer->rx_buf)[elements++] = w;
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		} else {
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			int bytes_per_word = mcspi_bytes_per_word(word_len);
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			dev_err(&spi->dev, "DMA RX penultimate word empty\n");
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			count -= (bytes_per_word << 1);
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			omap2_mcspi_set_enable(spi, 1);
			return count;
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		}
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	}
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	if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
				& OMAP2_MCSPI_CHSTAT_RXS)) {
		u32 w;

		w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
		if (word_len <= 8)
			((u8 *)xfer->rx_buf)[elements] = w;
		else if (word_len <= 16)
			((u16 *)xfer->rx_buf)[elements] = w;
		else /* word_len <= 32 */
			((u32 *)xfer->rx_buf)[elements] = w;
	} else {
533
		dev_err(&spi->dev, "DMA RX last word empty\n");
534
		count -= mcspi_bytes_per_word(word_len);
535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552
	}
	omap2_mcspi_set_enable(spi, 1);
	return count;
}

static unsigned
omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
{
	struct omap2_mcspi	*mcspi;
	struct omap2_mcspi_cs	*cs = spi->controller_state;
	struct omap2_mcspi_dma  *mcspi_dma;
	unsigned int		count;
	u32			l;
	u8			*rx;
	const u8		*tx;
	struct dma_slave_config	cfg;
	enum dma_slave_buswidth width;
	unsigned es;
553
	u32			burst;
554
	void __iomem		*chstat_reg;
555 556
	void __iomem            *irqstat_reg;
	int			wait_res;
557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573

	mcspi = spi_master_get_devdata(spi->master);
	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
	l = mcspi_cached_chconf0(spi);


	if (cs->word_len <= 8) {
		width = DMA_SLAVE_BUSWIDTH_1_BYTE;
		es = 1;
	} else if (cs->word_len <= 16) {
		width = DMA_SLAVE_BUSWIDTH_2_BYTES;
		es = 2;
	} else {
		width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		es = 4;
	}

574 575 576 577 578 579 580 581 582 583
	count = xfer->len;
	burst = 1;

	if (mcspi->fifo_depth > 0) {
		if (count > mcspi->fifo_depth)
			burst = mcspi->fifo_depth / es;
		else
			burst = count / es;
	}

584 585 586 587 588
	memset(&cfg, 0, sizeof(cfg));
	cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
	cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
	cfg.src_addr_width = width;
	cfg.dst_addr_width = width;
589 590
	cfg.src_maxburst = burst;
	cfg.dst_maxburst = burst;
591 592 593 594 595 596 597 598

	rx = xfer->rx_buf;
	tx = xfer->tx_buf;

	if (tx != NULL)
		omap2_mcspi_tx_dma(spi, xfer, cfg);

	if (rx != NULL)
599 600 601 602 603 604 605
		count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);

	if (tx != NULL) {
		wait_for_completion(&mcspi_dma->dma_tx_completion);
		dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
				 DMA_TO_DEVICE);

606 607 608 609 610 611 612 613 614 615 616
		if (mcspi->fifo_depth > 0) {
			irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;

			if (mcspi_wait_for_reg_bit(irqstat_reg,
						OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
				dev_err(&spi->dev, "EOW timed out\n");

			mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
					OMAP2_MCSPI_IRQSTATUS_EOW);
		}

617 618
		/* for TX_ONLY mode, be sure all words have shifted out */
		if (rx == NULL) {
619 620 621 622 623 624 625 626 627 628 629 630 631 632 633
			chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
			if (mcspi->fifo_depth > 0) {
				wait_res = mcspi_wait_for_reg_bit(chstat_reg,
						OMAP2_MCSPI_CHSTAT_TXFFE);
				if (wait_res < 0)
					dev_err(&spi->dev, "TXFFE timed out\n");
			} else {
				wait_res = mcspi_wait_for_reg_bit(chstat_reg,
						OMAP2_MCSPI_CHSTAT_TXS);
				if (wait_res < 0)
					dev_err(&spi->dev, "TXS timed out\n");
			}
			if (wait_res >= 0 &&
				(mcspi_wait_for_reg_bit(chstat_reg,
					OMAP2_MCSPI_CHSTAT_EOT) < 0))
634 635 636
				dev_err(&spi->dev, "EOT timed out\n");
		}
	}
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	return count;
}

static unsigned
omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
{
	struct omap2_mcspi	*mcspi;
	struct omap2_mcspi_cs	*cs = spi->controller_state;
	unsigned int		count, c;
	u32			l;
	void __iomem		*base = cs->base;
	void __iomem		*tx_reg;
	void __iomem		*rx_reg;
	void __iomem		*chstat_reg;
	int			word_len;

	mcspi = spi_master_get_devdata(spi->master);
	count = xfer->len;
	c = count;
	word_len = cs->word_len;

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	l = mcspi_cached_chconf0(spi);
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	/* We store the pre-calculated register addresses on stack to speed
	 * up the transfer loop. */
	tx_reg		= base + OMAP2_MCSPI_TX0;
	rx_reg		= base + OMAP2_MCSPI_RX0;
	chstat_reg	= base + OMAP2_MCSPI_CHSTAT0;

666 667 668
	if (c < (word_len>>3))
		return 0;

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	if (word_len <= 8) {
		u8		*rx;
		const u8	*tx;

		rx = xfer->rx_buf;
		tx = xfer->tx_buf;

		do {
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			c -= 1;
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			if (tx != NULL) {
				if (mcspi_wait_for_reg_bit(chstat_reg,
						OMAP2_MCSPI_CHSTAT_TXS) < 0) {
					dev_err(&spi->dev, "TXS timed out\n");
					goto out;
				}
684
				dev_vdbg(&spi->dev, "write-%d %02x\n",
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						word_len, *tx);
686
				writel_relaxed(*tx++, tx_reg);
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			}
			if (rx != NULL) {
				if (mcspi_wait_for_reg_bit(chstat_reg,
						OMAP2_MCSPI_CHSTAT_RXS) < 0) {
					dev_err(&spi->dev, "RXS timed out\n");
					goto out;
				}
694 695 696 697

				if (c == 1 && tx == NULL &&
				    (l & OMAP2_MCSPI_CHCONF_TURBO)) {
					omap2_mcspi_set_enable(spi, 0);
698
					*rx++ = readl_relaxed(rx_reg);
699
					dev_vdbg(&spi->dev, "read-%d %02x\n",
700 701 702 703 704 705 706 707 708 709 710 711
						    word_len, *(rx - 1));
					if (mcspi_wait_for_reg_bit(chstat_reg,
						OMAP2_MCSPI_CHSTAT_RXS) < 0) {
						dev_err(&spi->dev,
							"RXS timed out\n");
						goto out;
					}
					c = 0;
				} else if (c == 0 && tx == NULL) {
					omap2_mcspi_set_enable(spi, 0);
				}

712
				*rx++ = readl_relaxed(rx_reg);
713
				dev_vdbg(&spi->dev, "read-%d %02x\n",
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						word_len, *(rx - 1));
			}
716
		} while (c);
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	} else if (word_len <= 16) {
		u16		*rx;
		const u16	*tx;

		rx = xfer->rx_buf;
		tx = xfer->tx_buf;
		do {
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			c -= 2;
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			if (tx != NULL) {
				if (mcspi_wait_for_reg_bit(chstat_reg,
						OMAP2_MCSPI_CHSTAT_TXS) < 0) {
					dev_err(&spi->dev, "TXS timed out\n");
					goto out;
				}
731
				dev_vdbg(&spi->dev, "write-%d %04x\n",
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						word_len, *tx);
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				writel_relaxed(*tx++, tx_reg);
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			}
			if (rx != NULL) {
				if (mcspi_wait_for_reg_bit(chstat_reg,
						OMAP2_MCSPI_CHSTAT_RXS) < 0) {
					dev_err(&spi->dev, "RXS timed out\n");
					goto out;
				}
741 742 743 744

				if (c == 2 && tx == NULL &&
				    (l & OMAP2_MCSPI_CHCONF_TURBO)) {
					omap2_mcspi_set_enable(spi, 0);
745
					*rx++ = readl_relaxed(rx_reg);
746
					dev_vdbg(&spi->dev, "read-%d %04x\n",
747 748 749 750 751 752 753 754 755 756 757 758
						    word_len, *(rx - 1));
					if (mcspi_wait_for_reg_bit(chstat_reg,
						OMAP2_MCSPI_CHSTAT_RXS) < 0) {
						dev_err(&spi->dev,
							"RXS timed out\n");
						goto out;
					}
					c = 0;
				} else if (c == 0 && tx == NULL) {
					omap2_mcspi_set_enable(spi, 0);
				}

759
				*rx++ = readl_relaxed(rx_reg);
760
				dev_vdbg(&spi->dev, "read-%d %04x\n",
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						word_len, *(rx - 1));
			}
763
		} while (c >= 2);
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	} else if (word_len <= 32) {
		u32		*rx;
		const u32	*tx;

		rx = xfer->rx_buf;
		tx = xfer->tx_buf;
		do {
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			c -= 4;
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			if (tx != NULL) {
				if (mcspi_wait_for_reg_bit(chstat_reg,
						OMAP2_MCSPI_CHSTAT_TXS) < 0) {
					dev_err(&spi->dev, "TXS timed out\n");
					goto out;
				}
778
				dev_vdbg(&spi->dev, "write-%d %08x\n",
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						word_len, *tx);
780
				writel_relaxed(*tx++, tx_reg);
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			}
			if (rx != NULL) {
				if (mcspi_wait_for_reg_bit(chstat_reg,
						OMAP2_MCSPI_CHSTAT_RXS) < 0) {
					dev_err(&spi->dev, "RXS timed out\n");
					goto out;
				}
788 789 790 791

				if (c == 4 && tx == NULL &&
				    (l & OMAP2_MCSPI_CHCONF_TURBO)) {
					omap2_mcspi_set_enable(spi, 0);
792
					*rx++ = readl_relaxed(rx_reg);
793
					dev_vdbg(&spi->dev, "read-%d %08x\n",
794 795 796 797 798 799 800 801 802 803 804 805
						    word_len, *(rx - 1));
					if (mcspi_wait_for_reg_bit(chstat_reg,
						OMAP2_MCSPI_CHSTAT_RXS) < 0) {
						dev_err(&spi->dev,
							"RXS timed out\n");
						goto out;
					}
					c = 0;
				} else if (c == 0 && tx == NULL) {
					omap2_mcspi_set_enable(spi, 0);
				}

806
				*rx++ = readl_relaxed(rx_reg);
807
				dev_vdbg(&spi->dev, "read-%d %08x\n",
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						word_len, *(rx - 1));
			}
810
		} while (c >= 4);
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	}

	/* for TX_ONLY mode, be sure all words have shifted out */
	if (xfer->rx_buf == NULL) {
		if (mcspi_wait_for_reg_bit(chstat_reg,
				OMAP2_MCSPI_CHSTAT_TXS) < 0) {
			dev_err(&spi->dev, "TXS timed out\n");
		} else if (mcspi_wait_for_reg_bit(chstat_reg,
				OMAP2_MCSPI_CHSTAT_EOT) < 0)
			dev_err(&spi->dev, "EOT timed out\n");
821 822 823 824 825 826

		/* disable chan to purge rx datas received in TX_ONLY transfer,
		 * otherwise these rx datas will affect the direct following
		 * RX_ONLY transfer.
		 */
		omap2_mcspi_set_enable(spi, 0);
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	}
out:
829
	omap2_mcspi_set_enable(spi, 1);
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	return count - c;
}

833 834 835 836 837 838 839 840 841 842 843
static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
{
	u32 div;

	for (div = 0; div < 15; div++)
		if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
			return div;

	return 15;
}

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/* called only when no transfer is active to this device */
static int omap2_mcspi_setup_transfer(struct spi_device *spi,
		struct spi_transfer *t)
{
	struct omap2_mcspi_cs *cs = spi->controller_state;
	struct omap2_mcspi *mcspi;
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	struct spi_master *spi_cntrl;
851
	u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
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	u8 word_len = spi->bits_per_word;
853
	u32 speed_hz = spi->max_speed_hz;
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	mcspi = spi_master_get_devdata(spi->master);
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	spi_cntrl = mcspi->master;
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	if (t != NULL && t->bits_per_word)
		word_len = t->bits_per_word;

	cs->word_len = word_len;

863 864 865
	if (t && t->speed_hz)
		speed_hz = t->speed_hz;

866
	speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
867 868 869 870 871 872 873 874 875 876 877
	if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
		clkd = omap2_mcspi_calc_divisor(speed_hz);
		speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
		clkg = 0;
	} else {
		div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
		speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
		clkd = (div - 1) & 0xf;
		extclk = (div - 1) >> 4;
		clkg = OMAP2_MCSPI_CHCONF_CLKG;
	}
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	l = mcspi_cached_chconf0(spi);
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	/* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
	 * REVISIT: this controller could support SPI_3WIRE mode.
	 */
884
	if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
885 886 887 888 889 890 891 892
		l &= ~OMAP2_MCSPI_CHCONF_IS;
		l &= ~OMAP2_MCSPI_CHCONF_DPE1;
		l |= OMAP2_MCSPI_CHCONF_DPE0;
	} else {
		l |= OMAP2_MCSPI_CHCONF_IS;
		l |= OMAP2_MCSPI_CHCONF_DPE1;
		l &= ~OMAP2_MCSPI_CHCONF_DPE0;
	}
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	/* wordlength */
	l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
	l |= (word_len - 1) << 7;

	/* set chipselect polarity; manage with FORCE */
	if (!(spi->mode & SPI_CS_HIGH))
		l |= OMAP2_MCSPI_CHCONF_EPOL;	/* active-low; normal */
	else
		l &= ~OMAP2_MCSPI_CHCONF_EPOL;

	/* set clock divisor */
	l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
906 907 908 909 910 911 912 913 914 915
	l |= clkd << 2;

	/* set clock granularity */
	l &= ~OMAP2_MCSPI_CHCONF_CLKG;
	l |= clkg;
	if (clkg) {
		cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
		cs->chctrl0 |= extclk << 8;
		mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
	}
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	/* set SPI mode 0..3 */
	if (spi->mode & SPI_CPOL)
		l |= OMAP2_MCSPI_CHCONF_POL;
	else
		l &= ~OMAP2_MCSPI_CHCONF_POL;
	if (spi->mode & SPI_CPHA)
		l |= OMAP2_MCSPI_CHCONF_PHA;
	else
		l &= ~OMAP2_MCSPI_CHCONF_PHA;

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	mcspi_write_chconf0(spi, l);
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	dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
930
			speed_hz,
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			(spi->mode & SPI_CPHA) ? "trailing" : "leading",
			(spi->mode & SPI_CPOL) ? "inverted" : "normal");

	return 0;
}

937 938 939 940
/*
 * Note that we currently allow DMA only if we get a channel
 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
 */
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static int omap2_mcspi_request_dma(struct spi_device *spi)
{
	struct spi_master	*master = spi->master;
	struct omap2_mcspi	*mcspi;
	struct omap2_mcspi_dma	*mcspi_dma;
946 947
	dma_cap_mask_t mask;
	unsigned sig;
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	mcspi = spi_master_get_devdata(master);
	mcspi_dma = mcspi->dma_channels + spi->chip_select;

952 953 954 955 956 957
	init_completion(&mcspi_dma->dma_rx_completion);
	init_completion(&mcspi_dma->dma_tx_completion);

	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);
	sig = mcspi_dma->dma_rx_sync_dev;
958 959 960 961 962

	mcspi_dma->dma_rx =
		dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
						 &sig, &master->dev,
						 mcspi_dma->dma_rx_ch_name);
963 964
	if (!mcspi_dma->dma_rx)
		goto no_dma;
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966
	sig = mcspi_dma->dma_tx_sync_dev;
967 968 969 970 971
	mcspi_dma->dma_tx =
		dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
						 &sig, &master->dev,
						 mcspi_dma->dma_tx_ch_name);

972 973 974
	if (!mcspi_dma->dma_tx) {
		dma_release_channel(mcspi_dma->dma_rx);
		mcspi_dma->dma_rx = NULL;
975
		goto no_dma;
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	}

	return 0;
979 980 981 982

no_dma:
	dev_warn(&spi->dev, "not using DMA for McSPI\n");
	return -EAGAIN;
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}

static int omap2_mcspi_setup(struct spi_device *spi)
{
	int			ret;
988 989
	struct omap2_mcspi	*mcspi = spi_master_get_devdata(spi->master);
	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
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	struct omap2_mcspi_dma	*mcspi_dma;
	struct omap2_mcspi_cs	*cs = spi->controller_state;

	mcspi_dma = &mcspi->dma_channels[spi->chip_select];

	if (!cs) {
996
		cs = kzalloc(sizeof *cs, GFP_KERNEL);
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		if (!cs)
			return -ENOMEM;
		cs->base = mcspi->base + spi->chip_select * 0x14;
1000
		cs->phys = mcspi->phys + spi->chip_select * 0x14;
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		cs->chconf0 = 0;
1002
		cs->chctrl0 = 0;
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		spi->controller_state = cs;
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		/* Link this to context save list */
1005
		list_add_tail(&cs->node, &ctx->cs);
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	}

1008
	if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
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		ret = omap2_mcspi_request_dma(spi);
1010
		if (ret < 0 && ret != -EAGAIN)
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			return ret;
	}

1014
	ret = pm_runtime_get_sync(mcspi->dev);
1015 1016
	if (ret < 0)
		return ret;
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	ret = omap2_mcspi_setup_transfer(spi, NULL);
1019 1020
	pm_runtime_mark_last_busy(mcspi->dev);
	pm_runtime_put_autosuspend(mcspi->dev);
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	return ret;
}

static void omap2_mcspi_cleanup(struct spi_device *spi)
{
	struct omap2_mcspi	*mcspi;
	struct omap2_mcspi_dma	*mcspi_dma;
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	struct omap2_mcspi_cs	*cs;
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	mcspi = spi_master_get_devdata(spi->master);

1033 1034 1035 1036
	if (spi->controller_state) {
		/* Unlink controller state from context save list */
		cs = spi->controller_state;
		list_del(&cs->node);
T
Tero Kristo 已提交
1037

1038
		kfree(cs);
1039
	}
S
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1040

1041 1042 1043
	if (spi->chip_select < spi->master->num_chipselect) {
		mcspi_dma = &mcspi->dma_channels[spi->chip_select];

1044 1045 1046
		if (mcspi_dma->dma_rx) {
			dma_release_channel(mcspi_dma->dma_rx);
			mcspi_dma->dma_rx = NULL;
1047
		}
1048 1049 1050
		if (mcspi_dma->dma_tx) {
			dma_release_channel(mcspi_dma->dma_tx);
			mcspi_dma->dma_tx = NULL;
1051
		}
S
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1052 1053 1054
	}
}

1055
static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
S
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1056 1057 1058
{

	/* We only enable one channel at a time -- the one whose message is
1059
	 * -- although this controller would gladly
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1060 1061 1062 1063 1064
	 * arbitrate among multiple channels.  This corresponds to "single
	 * channel" master mode.  As a side effect, we need to manage the
	 * chipselect with the FORCE bit ... CS != channel enable.
	 */

1065 1066
	struct spi_device		*spi;
	struct spi_transfer		*t = NULL;
1067
	struct spi_master		*master;
1068
	struct omap2_mcspi_dma		*mcspi_dma;
1069 1070 1071 1072 1073 1074
	int				cs_active = 0;
	struct omap2_mcspi_cs		*cs;
	struct omap2_mcspi_device_config *cd;
	int				par_override = 0;
	int				status = 0;
	u32				chconf;
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1075

1076
	spi = m->spi;
1077
	master = spi->master;
1078
	mcspi_dma = mcspi->dma_channels + spi->chip_select;
1079 1080
	cs = spi->controller_state;
	cd = spi->controller_data;
S
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1081

1082
	omap2_mcspi_set_enable(spi, 0);
1083 1084 1085 1086 1087
	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
			status = -EINVAL;
			break;
		}
1088 1089 1090
		if (par_override ||
		    (t->speed_hz != spi->max_speed_hz) ||
		    (t->bits_per_word != spi->bits_per_word)) {
1091 1092 1093 1094
			par_override = 1;
			status = omap2_mcspi_setup_transfer(spi, t);
			if (status < 0)
				break;
1095 1096
			if (t->speed_hz == spi->max_speed_hz &&
			    t->bits_per_word == spi->bits_per_word)
1097 1098
				par_override = 0;
		}
1099 1100 1101 1102 1103 1104 1105 1106
		if (cd && cd->cs_per_word) {
			chconf = mcspi->ctx.modulctrl;
			chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
			mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
			mcspi->ctx.modulctrl =
				mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
		}

1107

1108 1109 1110 1111
		if (!cs_active) {
			omap2_mcspi_force_cs(spi, 1);
			cs_active = 1;
		}
1112

1113 1114 1115
		chconf = mcspi_cached_chconf0(spi);
		chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
		chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
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1116

1117 1118 1119 1120
		if (t->tx_buf == NULL)
			chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
		else if (t->rx_buf == NULL)
			chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
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1121

1122 1123 1124 1125 1126
		if (cd && cd->turbo_mode && t->tx_buf == NULL) {
			/* Turbo mode is for more than one word */
			if (t->len > ((cs->word_len + 7) >> 3))
				chconf |= OMAP2_MCSPI_CHCONF_TURBO;
		}
S
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1127

1128
		mcspi_write_chconf0(spi, chconf);
S
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1129

1130 1131 1132
		if (t->len) {
			unsigned	count;

1133 1134 1135 1136 1137 1138
			if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
			    (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
				omap2_mcspi_set_fifo(spi, t, 1);

			omap2_mcspi_set_enable(spi, 1);

1139 1140
			/* RX_ONLY mode needs dummy data in TX reg */
			if (t->tx_buf == NULL)
1141
				writel_relaxed(0, cs->base
1142
						+ OMAP2_MCSPI_TX0);
S
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1143

1144 1145
			if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
			    (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1146 1147 1148 1149
				count = omap2_mcspi_txrx_dma(spi, t);
			else
				count = omap2_mcspi_txrx_pio(spi, t);
			m->actual_length += count;
S
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1150

1151 1152 1153
			if (count != t->len) {
				status = -EIO;
				break;
S
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1154 1155 1156
			}
		}

1157 1158
		if (t->delay_usecs)
			udelay(t->delay_usecs);
S
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1159

1160 1161
		/* ignore the "leave it on after last xfer" hint */
		if (t->cs_change) {
S
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1162
			omap2_mcspi_force_cs(spi, 0);
1163 1164
			cs_active = 0;
		}
1165 1166 1167 1168 1169

		omap2_mcspi_set_enable(spi, 0);

		if (mcspi->fifo_depth > 0)
			omap2_mcspi_set_fifo(spi, t, 0);
1170 1171 1172 1173 1174 1175
	}
	/* Restore defaults if they were overriden */
	if (par_override) {
		par_override = 0;
		status = omap2_mcspi_setup_transfer(spi, NULL);
	}
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1176

1177 1178
	if (cs_active)
		omap2_mcspi_force_cs(spi, 0);
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1179

1180 1181 1182 1183 1184 1185 1186 1187
	if (cd && cd->cs_per_word) {
		chconf = mcspi->ctx.modulctrl;
		chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
		mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
		mcspi->ctx.modulctrl =
			mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
	}

1188
	omap2_mcspi_set_enable(spi, 0);
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1189

1190 1191
	if (mcspi->fifo_depth > 0 && t)
		omap2_mcspi_set_fifo(spi, t, 0);
1192

1193
	m->status = status;
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1194 1195
}

1196
static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1197
		struct spi_message *m)
S
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1198
{
1199
	struct spi_device	*spi;
S
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1200
	struct omap2_mcspi	*mcspi;
1201
	struct omap2_mcspi_dma	*mcspi_dma;
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1202 1203
	struct spi_transfer	*t;

1204
	spi = m->spi;
1205
	mcspi = spi_master_get_devdata(master);
1206
	mcspi_dma = mcspi->dma_channels + spi->chip_select;
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1207 1208 1209 1210 1211 1212 1213 1214
	m->actual_length = 0;
	m->status = 0;

	list_for_each_entry(t, &m->transfers, transfer_list) {
		const void	*tx_buf = t->tx_buf;
		void		*rx_buf = t->rx_buf;
		unsigned	len = t->len;

1215
		if ((len && !(rx_buf || tx_buf))) {
1216
			dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
S
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1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227
					t->speed_hz,
					len,
					tx_buf ? "tx" : "",
					rx_buf ? "rx" : "",
					t->bits_per_word);
			return -EINVAL;
		}

		if (m->is_dma_mapped || len < DMA_MIN_BYTES)
			continue;

1228
		if (mcspi_dma->dma_tx && tx_buf != NULL) {
1229
			t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
S
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1230
					len, DMA_TO_DEVICE);
1231 1232
			if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
				dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
S
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1233 1234 1235 1236
						'T', len);
				return -EINVAL;
			}
		}
1237
		if (mcspi_dma->dma_rx && rx_buf != NULL) {
1238
			t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
S
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1239
					DMA_FROM_DEVICE);
1240 1241
			if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
				dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
S
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1242 1243
						'R', len);
				if (tx_buf != NULL)
1244
					dma_unmap_single(mcspi->dev, t->tx_dma,
S
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1245 1246 1247 1248 1249 1250
							len, DMA_TO_DEVICE);
				return -EINVAL;
			}
		}
	}

1251 1252
	omap2_mcspi_work(mcspi, m);
	spi_finalize_current_message(master);
S
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1253 1254 1255
	return 0;
}

1256
static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
S
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1257 1258
{
	struct spi_master	*master = mcspi->master;
1259 1260
	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
	int			ret = 0;
S
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1261

1262
	ret = pm_runtime_get_sync(mcspi->dev);
1263 1264
	if (ret < 0)
		return ret;
1265

1266
	mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1267
			OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1268
	ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
S
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1269 1270

	omap2_mcspi_set_master_mode(master);
1271 1272
	pm_runtime_mark_last_busy(mcspi->dev);
	pm_runtime_put_autosuspend(mcspi->dev);
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1273 1274 1275
	return 0;
}

1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287
static int omap_mcspi_runtime_resume(struct device *dev)
{
	struct omap2_mcspi	*mcspi;
	struct spi_master	*master;

	master = dev_get_drvdata(dev);
	mcspi = spi_master_get_devdata(master);
	omap2_mcspi_restore_ctx(mcspi);

	return 0;
}

1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307
static struct omap2_mcspi_platform_config omap2_pdata = {
	.regs_offset = 0,
};

static struct omap2_mcspi_platform_config omap4_pdata = {
	.regs_offset = OMAP4_MCSPI_REG_OFFSET,
};

static const struct of_device_id omap_mcspi_of_match[] = {
	{
		.compatible = "ti,omap2-mcspi",
		.data = &omap2_pdata,
	},
	{
		.compatible = "ti,omap4-mcspi",
		.data = &omap4_pdata,
	},
	{ },
};
MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
G
Girish 已提交
1308

1309
static int omap2_mcspi_probe(struct platform_device *pdev)
S
Samuel Ortiz 已提交
1310 1311
{
	struct spi_master	*master;
1312
	const struct omap2_mcspi_platform_config *pdata;
S
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1313 1314 1315
	struct omap2_mcspi	*mcspi;
	struct resource		*r;
	int			status = 0, i;
1316 1317 1318 1319
	u32			regs_offset = 0;
	static int		bus_num = 1;
	struct device_node	*node = pdev->dev.of_node;
	const struct of_device_id *match;
S
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1320 1321 1322 1323 1324 1325 1326

	master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
	if (master == NULL) {
		dev_dbg(&pdev->dev, "master allocation failed\n");
		return -ENOMEM;
	}

1327 1328
	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1329
	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
S
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1330
	master->setup = omap2_mcspi_setup;
1331
	master->auto_runtime_pm = true;
1332
	master->transfer_one_message = omap2_mcspi_transfer_one_message;
S
Samuel Ortiz 已提交
1333
	master->cleanup = omap2_mcspi_cleanup;
1334
	master->dev.of_node = node;
1335 1336
	master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
	master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1337

1338
	platform_set_drvdata(pdev, master);
1339 1340 1341 1342

	mcspi = spi_master_get_devdata(master);
	mcspi->master = master;

1343 1344 1345 1346 1347 1348 1349 1350
	match = of_match_device(omap_mcspi_of_match, &pdev->dev);
	if (match) {
		u32 num_cs = 1; /* default number of chipselect */
		pdata = match->data;

		of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
		master->num_chipselect = num_cs;
		master->bus_num = bus_num++;
1351 1352
		if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
			mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1353
	} else {
J
Jingoo Han 已提交
1354
		pdata = dev_get_platdata(&pdev->dev);
1355 1356 1357
		master->num_chipselect = pdata->num_cs;
		if (pdev->id != -1)
			master->bus_num = pdev->id;
1358
		mcspi->pin_dir = pdata->pin_dir;
1359 1360
	}
	regs_offset = pdata->regs_offset;
S
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1361 1362 1363 1364

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (r == NULL) {
		status = -ENODEV;
S
Shubhrajyoti D 已提交
1365
		goto free_master;
S
Samuel Ortiz 已提交
1366
	}
1367

1368 1369
	r->start += regs_offset;
	r->end += regs_offset;
1370
	mcspi->phys = r->start;
S
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1371

1372 1373 1374
	mcspi->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(mcspi->base)) {
		status = PTR_ERR(mcspi->base);
1375
		goto free_master;
1376
	}
S
Samuel Ortiz 已提交
1377

1378
	mcspi->dev = &pdev->dev;
S
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1379

1380
	INIT_LIST_HEAD(&mcspi->ctx.cs);
S
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1381

1382 1383 1384 1385 1386
	mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
					   sizeof(struct omap2_mcspi_dma),
					   GFP_KERNEL);
	if (mcspi->dma_channels == NULL) {
		status = -ENOMEM;
1387
		goto free_master;
1388
	}
S
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1389

1390
	for (i = 0; i < master->num_chipselect; i++) {
1391 1392
		char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
		char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
1393 1394
		struct resource *dma_res;

1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406
		sprintf(dma_rx_ch_name, "rx%d", i);
		if (!pdev->dev.of_node) {
			dma_res =
				platform_get_resource_byname(pdev,
							     IORESOURCE_DMA,
							     dma_rx_ch_name);
			if (!dma_res) {
				dev_dbg(&pdev->dev,
					"cannot get DMA RX channel\n");
				status = -ENODEV;
				break;
			}
1407

1408 1409
			mcspi->dma_channels[i].dma_rx_sync_dev =
				dma_res->start;
1410
		}
1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422
		sprintf(dma_tx_ch_name, "tx%d", i);
		if (!pdev->dev.of_node) {
			dma_res =
				platform_get_resource_byname(pdev,
							     IORESOURCE_DMA,
							     dma_tx_ch_name);
			if (!dma_res) {
				dev_dbg(&pdev->dev,
					"cannot get DMA TX channel\n");
				status = -ENODEV;
				break;
			}
1423

1424 1425 1426
			mcspi->dma_channels[i].dma_tx_sync_dev =
				dma_res->start;
		}
S
Samuel Ortiz 已提交
1427 1428
	}

S
Shubhrajyoti D 已提交
1429
	if (status < 0)
1430
		goto free_master;
S
Shubhrajyoti D 已提交
1431

1432 1433
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1434 1435
	pm_runtime_enable(&pdev->dev);

1436 1437
	status = omap2_mcspi_master_setup(mcspi);
	if (status < 0)
S
Shubhrajyoti D 已提交
1438
		goto disable_pm;
S
Samuel Ortiz 已提交
1439

1440
	status = devm_spi_register_master(&pdev->dev, master);
S
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1441
	if (status < 0)
1442
		goto disable_pm;
S
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1443 1444 1445

	return status;

S
Shubhrajyoti D 已提交
1446
disable_pm:
1447
	pm_runtime_disable(&pdev->dev);
S
Shubhrajyoti D 已提交
1448
free_master:
1449
	spi_master_put(master);
S
Samuel Ortiz 已提交
1450 1451 1452
	return status;
}

1453
static int omap2_mcspi_remove(struct platform_device *pdev)
S
Samuel Ortiz 已提交
1454
{
1455 1456
	struct spi_master *master = platform_get_drvdata(pdev);
	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
S
Samuel Ortiz 已提交
1457

1458
	pm_runtime_put_sync(mcspi->dev);
1459
	pm_runtime_disable(&pdev->dev);
S
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1460 1461 1462 1463

	return 0;
}

1464 1465 1466
/* work with hotplug and coldplug */
MODULE_ALIAS("platform:omap2_mcspi");

1467 1468 1469 1470 1471 1472 1473 1474 1475 1476
#ifdef	CONFIG_SUSPEND
/*
 * When SPI wake up from off-mode, CS is in activate state. If it was in
 * unactive state when driver was suspend, then force it to unactive state at
 * wake up.
 */
static int omap2_mcspi_resume(struct device *dev)
{
	struct spi_master	*master = dev_get_drvdata(dev);
	struct omap2_mcspi	*mcspi = spi_master_get_devdata(master);
1477 1478
	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
	struct omap2_mcspi_cs	*cs;
1479

1480
	pm_runtime_get_sync(mcspi->dev);
1481
	list_for_each_entry(cs, &ctx->cs, node) {
1482 1483 1484 1485 1486
		if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
			/*
			 * We need to toggle CS state for OMAP take this
			 * change in account.
			 */
1487
			cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1488
			writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1489
			cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1490
			writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1491 1492
		}
	}
1493 1494
	pm_runtime_mark_last_busy(mcspi->dev);
	pm_runtime_put_autosuspend(mcspi->dev);
1495 1496 1497 1498 1499 1500 1501 1502
	return 0;
}
#else
#define	omap2_mcspi_resume	NULL
#endif

static const struct dev_pm_ops omap2_mcspi_pm_ops = {
	.resume = omap2_mcspi_resume,
1503
	.runtime_resume	= omap_mcspi_runtime_resume,
1504 1505
};

S
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1506 1507 1508 1509
static struct platform_driver omap2_mcspi_driver = {
	.driver = {
		.name =		"omap2_mcspi",
		.owner =	THIS_MODULE,
1510 1511
		.pm =		&omap2_mcspi_pm_ops,
		.of_match_table = omap_mcspi_of_match,
S
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1512
	},
1513
	.probe =	omap2_mcspi_probe,
1514
	.remove =	omap2_mcspi_remove,
S
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1515 1516
};

1517
module_platform_driver(omap2_mcspi_driver);
S
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1518
MODULE_LICENSE("GPL");