vector.c 24.7 KB
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/*
 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
 *
 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
 *	Moved from arch/x86/kernel/apic/io_apic.c.
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 * Jiang Liu <jiang.liu@linux.intel.com>
 *	Enable support of hierarchical irqdomains
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/compiler.h>
#include <linux/slab.h>
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#include <asm/irqdomain.h>
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#include <asm/hw_irq.h>
#include <asm/apic.h>
#include <asm/i8259.h>
#include <asm/desc.h>
#include <asm/irq_remapping.h>

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struct apic_chip_data {
	struct irq_cfg		cfg;
	cpumask_var_t		domain;
	cpumask_var_t		old_domain;
	u8			move_in_progress : 1;
};

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struct irq_domain *x86_vector_domain;
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EXPORT_SYMBOL_GPL(x86_vector_domain);
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static DEFINE_RAW_SPINLOCK(vector_lock);
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static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask;
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static struct irq_chip lapic_controller;
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#ifdef	CONFIG_X86_IO_APIC
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static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];
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#endif
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void lock_vector_lock(void)
{
	/* Used to the online set of cpus does not change
	 * during assign_irq_vector.
	 */
	raw_spin_lock(&vector_lock);
}

void unlock_vector_lock(void)
{
	raw_spin_unlock(&vector_lock);
}

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static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data)
54
{
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	if (!irq_data)
		return NULL;

	while (irq_data->parent_data)
		irq_data = irq_data->parent_data;

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	return irq_data->chip_data;
}

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struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
{
	struct apic_chip_data *data = apic_chip_data(irq_data);

	return data ? &data->cfg : NULL;
}
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EXPORT_SYMBOL_GPL(irqd_cfg);
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struct irq_cfg *irq_cfg(unsigned int irq)
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{
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	return irqd_cfg(irq_get_irq_data(irq));
}
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static struct apic_chip_data *alloc_apic_chip_data(int node)
{
	struct apic_chip_data *data;

	data = kzalloc_node(sizeof(*data), GFP_KERNEL, node);
	if (!data)
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		return NULL;
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	if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node))
		goto out_data;
	if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node))
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		goto out_domain;
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	return data;
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out_domain:
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	free_cpumask_var(data->domain);
out_data:
	kfree(data);
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	return NULL;
}

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static void free_apic_chip_data(struct apic_chip_data *data)
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{
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	if (data) {
		free_cpumask_var(data->domain);
		free_cpumask_var(data->old_domain);
		kfree(data);
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	}
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}

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static int __assign_irq_vector(int irq, struct apic_chip_data *d,
			       const struct cpumask *mask)
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{
	/*
	 * NOTE! The local APIC isn't very good at handling
	 * multiple interrupts at the same interrupt level.
	 * As the interrupt level is determined by taking the
	 * vector number and shifting that right by 4, we
	 * want to spread these out a bit so that they don't
	 * all fall in the same interrupt level.
	 *
	 * Also, we've got to be careful not to trash gate
	 * 0x80, because int 0x80 is hm, kind of importantish. ;)
	 */
	static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
	static int current_offset = VECTOR_OFFSET_START % 16;
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	int cpu, vector;
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	/*
	 * If there is still a move in progress or the previous move has not
	 * been cleaned up completely, tell the caller to come back later.
	 */
	if (d->move_in_progress ||
	    cpumask_intersects(d->old_domain, cpu_online_mask))
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		return -EBUSY;

	/* Only try and allocate irqs on cpus that are present */
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	cpumask_clear(d->old_domain);
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	cpumask_clear(searched_cpumask);
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	cpu = cpumask_first_and(mask, cpu_online_mask);
	while (cpu < nr_cpu_ids) {
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		int new_cpu, offset;
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		/* Get the possible target cpus for @mask/@cpu from the apic */
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		apic->vector_allocation_domain(cpu, vector_cpumask, mask);
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		/*
		 * Clear the offline cpus from @vector_cpumask for searching
		 * and verify whether the result overlaps with @mask. If true,
		 * then the call to apic->cpu_mask_to_apicid_and() will
		 * succeed as well. If not, no point in trying to find a
		 * vector in this mask.
		 */
		cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask);
		if (!cpumask_intersects(vector_searchmask, mask))
			goto next_cpu;

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		if (cpumask_subset(vector_cpumask, d->domain)) {
			if (cpumask_equal(vector_cpumask, d->domain))
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				goto success;
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			/*
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			 * Mark the cpus which are not longer in the mask for
			 * cleanup.
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			 */
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			cpumask_andnot(d->old_domain, d->domain, vector_cpumask);
			vector = d->cfg.vector;
			goto update;
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		}

		vector = current_vector;
		offset = current_offset;
next:
		vector += 16;
		if (vector >= first_system_vector) {
			offset = (offset + 1) % 16;
			vector = FIRST_EXTERNAL_VECTOR + offset;
		}

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		/* If the search wrapped around, try the next cpu */
		if (unlikely(current_vector == vector))
			goto next_cpu;
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		if (test_bit(vector, used_vectors))
			goto next;

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		for_each_cpu(new_cpu, vector_searchmask) {
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			if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector]))
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				goto next;
		}
		/* Found one! */
		current_vector = vector;
		current_offset = offset;
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		/* Schedule the old vector for cleanup on all cpus */
		if (d->cfg.vector)
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			cpumask_copy(d->old_domain, d->domain);
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		for_each_cpu(new_cpu, vector_searchmask)
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			per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq);
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		goto update;
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next_cpu:
		/*
		 * We exclude the current @vector_cpumask from the requested
		 * @mask and try again with the next online cpu in the
		 * result. We cannot modify @mask, so we use @vector_cpumask
		 * as a temporary buffer here as it will be reassigned when
		 * calling apic->vector_allocation_domain() above.
		 */
		cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask);
		cpumask_andnot(vector_cpumask, mask, searched_cpumask);
		cpu = cpumask_first_and(vector_cpumask, cpu_online_mask);
		continue;
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	}
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	return -ENOSPC;
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update:
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	/*
	 * Exclude offline cpus from the cleanup mask and set the
	 * move_in_progress flag when the result is not empty.
	 */
	cpumask_and(d->old_domain, d->old_domain, cpu_online_mask);
	d->move_in_progress = !cpumask_empty(d->old_domain);
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	d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0;
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	d->cfg.vector = vector;
	cpumask_copy(d->domain, vector_cpumask);
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success:
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	/*
	 * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail
	 * as we already established, that mask & d->domain & cpu_online_mask
	 * is not empty.
	 */
	BUG_ON(apic->cpu_mask_to_apicid_and(mask, d->domain,
					    &d->cfg.dest_apicid));
	return 0;
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}

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static int assign_irq_vector(int irq, struct apic_chip_data *data,
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			     const struct cpumask *mask)
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{
	int err;
	unsigned long flags;

	raw_spin_lock_irqsave(&vector_lock, flags);
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	err = __assign_irq_vector(irq, data, mask);
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	raw_spin_unlock_irqrestore(&vector_lock, flags);
	return err;
}

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static int assign_irq_vector_policy(int irq, int node,
				    struct apic_chip_data *data,
				    struct irq_alloc_info *info)
{
	if (info && info->mask)
		return assign_irq_vector(irq, data, info->mask);
	if (node != NUMA_NO_NODE &&
	    assign_irq_vector(irq, data, cpumask_of_node(node)) == 0)
		return 0;
	return assign_irq_vector(irq, data, apic->target_cpus());
}

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static void clear_irq_vector(int irq, struct apic_chip_data *data)
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{
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	struct irq_desc *desc;
	int cpu, vector;
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	BUG_ON(!data->cfg.vector);
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	vector = data->cfg.vector;
	for_each_cpu_and(cpu, data->domain, cpu_online_mask)
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		per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
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	data->cfg.vector = 0;
	cpumask_clear(data->domain);
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	/*
	 * If move is in progress or the old_domain mask is not empty,
	 * i.e. the cleanup IPI has not been processed yet, we need to remove
	 * the old references to desc from all cpus vector tables.
	 */
	if (!data->move_in_progress && cpumask_empty(data->old_domain))
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		return;

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	desc = irq_to_desc(irq);
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	for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) {
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		for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
		     vector++) {
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			if (per_cpu(vector_irq, cpu)[vector] != desc)
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				continue;
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			per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
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			break;
		}
	}
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	data->move_in_progress = 0;
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}

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void init_irq_alloc_info(struct irq_alloc_info *info,
			 const struct cpumask *mask)
{
	memset(info, 0, sizeof(*info));
	info->mask = mask;
}

void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
{
	if (src)
		*dst = *src;
	else
		memset(dst, 0, sizeof(*dst));
}

static void x86_vector_free_irqs(struct irq_domain *domain,
				 unsigned int virq, unsigned int nr_irqs)
{
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	struct apic_chip_data *apic_data;
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	struct irq_data *irq_data;
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	unsigned long flags;
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	int i;

	for (i = 0; i < nr_irqs; i++) {
		irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i);
		if (irq_data && irq_data->chip_data) {
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			raw_spin_lock_irqsave(&vector_lock, flags);
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			clear_irq_vector(virq + i, irq_data->chip_data);
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			apic_data = irq_data->chip_data;
			irq_domain_reset_irq_data(irq_data);
			raw_spin_unlock_irqrestore(&vector_lock, flags);
			free_apic_chip_data(apic_data);
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#ifdef	CONFIG_X86_IO_APIC
			if (virq + i < nr_legacy_irqs())
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				legacy_irq_data[virq + i] = NULL;
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#endif
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		}
	}
}

static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
				 unsigned int nr_irqs, void *arg)
{
	struct irq_alloc_info *info = arg;
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	struct apic_chip_data *data;
334
	struct irq_data *irq_data;
335
	int i, err, node;
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	if (disable_apic)
		return -ENXIO;

	/* Currently vector allocator can't guarantee contiguous allocations */
	if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
		return -ENOSYS;

	for (i = 0; i < nr_irqs; i++) {
		irq_data = irq_domain_get_irq_data(domain, virq + i);
		BUG_ON(!irq_data);
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		node = irq_data_get_node(irq_data);
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#ifdef	CONFIG_X86_IO_APIC
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		if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i])
			data = legacy_irq_data[virq + i];
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		else
#endif
353
			data = alloc_apic_chip_data(node);
354
		if (!data) {
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			err = -ENOMEM;
			goto error;
		}

		irq_data->chip = &lapic_controller;
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		irq_data->chip_data = data;
361
		irq_data->hwirq = virq + i;
362
		err = assign_irq_vector_policy(virq + i, node, data, info);
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		if (err)
			goto error;
	}

	return 0;

error:
	x86_vector_free_irqs(domain, virq, i + 1);
	return err;
}

T
Thomas Gleixner 已提交
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static const struct irq_domain_ops x86_vector_domain_ops = {
	.alloc	= x86_vector_alloc_irqs,
	.free	= x86_vector_free_irqs,
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};

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int __init arch_probe_nr_irqs(void)
{
	int nr;

	if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
		nr_irqs = NR_VECTORS * nr_cpu_ids;

	nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
	/*
	 * for MSI and HT dyn irq
	 */
	if (gsi_top <= NR_IRQS_LEGACY)
		nr +=  8 * nr_cpu_ids;
	else
		nr += gsi_top * 16;
#endif
	if (nr < nr_irqs)
		nr_irqs = nr;

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	/*
	 * We don't know if PIC is present at this point so we need to do
	 * probe() to get the right number of legacy IRQs.
	 */
	return legacy_pic->probe();
404 405
}

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#ifdef	CONFIG_X86_IO_APIC
static void init_legacy_irqs(void)
{
	int i, node = cpu_to_node(0);
410
	struct apic_chip_data *data;
411 412 413

	/*
	 * For legacy IRQ's, start with assigning irq0 to irq15 to
414
	 * ISA_IRQ_VECTOR(i) for all cpu's.
415 416
	 */
	for (i = 0; i < nr_legacy_irqs(); i++) {
417 418
		data = legacy_irq_data[i] = alloc_apic_chip_data(node);
		BUG_ON(!data);
419 420

		data->cfg.vector = ISA_IRQ_VECTOR(i);
421 422
		cpumask_setall(data->domain);
		irq_set_chip_data(i, data);
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	}
}
#else
static void init_legacy_irqs(void) { }
#endif

429 430
int __init arch_early_irq_init(void)
{
431 432
	init_legacy_irqs();

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	x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops,
						NULL);
	BUG_ON(x86_vector_domain == NULL);
	irq_set_default_host(x86_vector_domain);

438
	arch_init_msi_domain(x86_vector_domain);
439
	arch_init_htirq_domain(x86_vector_domain);
440

441
	BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL));
442
	BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
443
	BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL));
444

445 446 447
	return arch_early_ioapic_init();
}

448
/* Initialize vector_irq on a new cpu */
449 450
static void __setup_vector_irq(int cpu)
{
451
	struct apic_chip_data *data;
452 453
	struct irq_desc *desc;
	int irq, vector;
454 455

	/* Mark the inuse vectors */
456 457
	for_each_irq_desc(irq, desc) {
		struct irq_data *idata = irq_desc_get_irq_data(desc);
458

459 460
		data = apic_chip_data(idata);
		if (!data || !cpumask_test_cpu(cpu, data->domain))
461
			continue;
462
		vector = data->cfg.vector;
463
		per_cpu(vector_irq, cpu)[vector] = desc;
464 465 466
	}
	/* Mark the free vectors */
	for (vector = 0; vector < NR_VECTORS; ++vector) {
467 468
		desc = per_cpu(vector_irq, cpu)[vector];
		if (IS_ERR_OR_NULL(desc))
469 470
			continue;

471
		data = apic_chip_data(irq_desc_get_irq_data(desc));
472
		if (!cpumask_test_cpu(cpu, data->domain))
473
			per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
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	}
}

/*
478
 * Setup the vector to irq mappings. Must be called with vector_lock held.
479 480 481 482 483
 */
void setup_vector_irq(int cpu)
{
	int irq;

484
	lockdep_assert_held(&vector_lock);
485 486 487 488 489 490 491 492
	/*
	 * On most of the platforms, legacy PIC delivers the interrupts on the
	 * boot cpu. But there are certain platforms where PIC interrupts are
	 * delivered to multiple cpu's. If the legacy IRQ is handled by the
	 * legacy PIC, for the new cpu that is coming online, setup the static
	 * legacy vector to irq mapping:
	 */
	for (irq = 0; irq < nr_legacy_irqs(); irq++)
493
		per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq);
494 495 496 497

	__setup_vector_irq(cpu);
}

498
static int apic_retrigger_irq(struct irq_data *irq_data)
499
{
500
	struct apic_chip_data *data = apic_chip_data(irq_data);
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	unsigned long flags;
	int cpu;

	raw_spin_lock_irqsave(&vector_lock, flags);
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	cpu = cpumask_first_and(data->domain, cpu_online_mask);
	apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector);
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	raw_spin_unlock_irqrestore(&vector_lock, flags);

	return 1;
}

void apic_ack_edge(struct irq_data *data)
{
514
	irq_complete_move(irqd_cfg(data));
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	irq_move_irq(data);
	ack_APIC_irq();
}

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static int apic_set_affinity(struct irq_data *irq_data,
			     const struct cpumask *dest, bool force)
521
{
522
	struct apic_chip_data *data = irq_data->chip_data;
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	int err, irq = irq_data->irq;

	if (!config_enabled(CONFIG_SMP))
		return -EPERM;

	if (!cpumask_intersects(dest, cpu_online_mask))
		return -EINVAL;

531
	err = assign_irq_vector(irq, data, dest);
532
	return err ? err : IRQ_SET_MASK_OK;
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}

static struct irq_chip lapic_controller = {
	.irq_ack		= apic_ack_edge,
537
	.irq_set_affinity	= apic_set_affinity,
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	.irq_retrigger		= apic_retrigger_irq,
};

541
#ifdef CONFIG_SMP
542
static void __send_cleanup_vector(struct apic_chip_data *data)
543
{
544
	raw_spin_lock(&vector_lock);
545
	cpumask_and(data->old_domain, data->old_domain, cpu_online_mask);
546
	data->move_in_progress = 0;
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	if (!cpumask_empty(data->old_domain))
		apic->send_IPI_mask(data->old_domain, IRQ_MOVE_CLEANUP_VECTOR);
549
	raw_spin_unlock(&vector_lock);
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}

552 553
void send_cleanup_vector(struct irq_cfg *cfg)
{
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	struct apic_chip_data *data;

	data = container_of(cfg, struct apic_chip_data, cfg);
	if (data->move_in_progress)
		__send_cleanup_vector(data);
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}

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asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
{
	unsigned vector, me;

565
	entering_ack_irq();
566

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	/* Prevent vectors vanishing under us */
	raw_spin_lock(&vector_lock);

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	me = smp_processor_id();
	for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
572
		struct apic_chip_data *data;
573 574
		struct irq_desc *desc;
		unsigned int irr;
575

576
	retry:
577 578
		desc = __this_cpu_read(vector_irq[vector]);
		if (IS_ERR_OR_NULL(desc))
579 580
			continue;

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		if (!raw_spin_trylock(&desc->lock)) {
			raw_spin_unlock(&vector_lock);
			cpu_relax();
			raw_spin_lock(&vector_lock);
			goto retry;
		}
587

588
		data = apic_chip_data(irq_desc_get_irq_data(desc));
589
		if (!data)
590
			goto unlock;
591 592

		/*
593 594
		 * Nothing to cleanup if irq migration is in progress
		 * or this cpu is not set in the cleanup mask.
595
		 */
596 597
		if (data->move_in_progress ||
		    !cpumask_test_cpu(me, data->old_domain))
598 599
			goto unlock;

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		/*
		 * We have two cases to handle here:
		 * 1) vector is unchanged but the target mask got reduced
		 * 2) vector and the target mask has changed
		 *
		 * #1 is obvious, but in #2 we have two vectors with the same
		 * irq descriptor: the old and the new vector. So we need to
		 * make sure that we only cleanup the old vector. The new
		 * vector has the current @vector number in the config and
		 * this cpu is part of the target mask. We better leave that
		 * one alone.
		 */
612 613
		if (vector == data->cfg.vector &&
		    cpumask_test_cpu(me, data->domain))
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			goto unlock;

		irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
		/*
		 * Check if the vector that needs to be cleanedup is
		 * registered at the cpu's IRR. If so, then this is not
		 * the best time to clean it up. Lets clean it up in the
		 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
		 * to myself.
		 */
		if (irr  & (1 << (vector % 32))) {
			apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
			goto unlock;
		}
628
		__this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
629
		cpumask_clear_cpu(me, data->old_domain);
630 631 632 633
unlock:
		raw_spin_unlock(&desc->lock);
	}

634 635
	raw_spin_unlock(&vector_lock);

636
	exiting_irq();
637 638 639 640 641
}

static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
{
	unsigned me;
642
	struct apic_chip_data *data;
643

644 645
	data = container_of(cfg, struct apic_chip_data, cfg);
	if (likely(!data->move_in_progress))
646 647 648
		return;

	me = smp_processor_id();
649 650
	if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain))
		__send_cleanup_vector(data);
651 652 653 654 655 656 657
}

void irq_complete_move(struct irq_cfg *cfg)
{
	__irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
}

658
/*
659
 * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
660 661
 */
void irq_force_complete_move(struct irq_desc *desc)
662
{
663 664 665
	struct irq_data *irqdata = irq_desc_get_irq_data(desc);
	struct apic_chip_data *data = apic_chip_data(irqdata);
	struct irq_cfg *cfg = data ? &data->cfg : NULL;
666
	unsigned int cpu;
667 668 669

	if (!cfg)
		return;
670

671
	/*
672 673 674 675
	 * This is tricky. If the cleanup of @data->old_domain has not been
	 * done yet, then the following setaffinity call will fail with
	 * -EBUSY. This can leave the interrupt in a stale state.
	 *
676 677
	 * All CPUs are stuck in stop machine with interrupts disabled so
	 * calling __irq_complete_move() would be completely pointless.
678 679
	 */
	raw_spin_lock(&vector_lock);
680 681 682 683
	/*
	 * Clean out all offline cpus (including the outgoing one) from the
	 * old_domain mask.
	 */
684
	cpumask_and(data->old_domain, data->old_domain, cpu_online_mask);
685 686 687 688 689 690 691

	/*
	 * If move_in_progress is cleared and the old_domain mask is empty,
	 * then there is nothing to cleanup. fixup_irqs() will take care of
	 * the stale vectors on the outgoing cpu.
	 */
	if (!data->move_in_progress && cpumask_empty(data->old_domain)) {
692
		raw_spin_unlock(&vector_lock);
693 694 695 696 697 698 699 700 701 702 703 704
		return;
	}

	/*
	 * 1) The interrupt is in move_in_progress state. That means that we
	 *    have not seen an interrupt since the io_apic was reprogrammed to
	 *    the new vector.
	 *
	 * 2) The interrupt has fired on the new vector, but the cleanup IPIs
	 *    have not been processed yet.
	 */
	if (data->move_in_progress) {
705
		/*
706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735
		 * In theory there is a race:
		 *
		 * set_ioapic(new_vector) <-- Interrupt is raised before update
		 *			      is effective, i.e. it's raised on
		 *			      the old vector.
		 *
		 * So if the target cpu cannot handle that interrupt before
		 * the old vector is cleaned up, we get a spurious interrupt
		 * and in the worst case the ioapic irq line becomes stale.
		 *
		 * But in case of cpu hotplug this should be a non issue
		 * because if the affinity update happens right before all
		 * cpus rendevouz in stop machine, there is no way that the
		 * interrupt can be blocked on the target cpu because all cpus
		 * loops first with interrupts enabled in stop machine, so the
		 * old vector is not yet cleaned up when the interrupt fires.
		 *
		 * So the only way to run into this issue is if the delivery
		 * of the interrupt on the apic/system bus would be delayed
		 * beyond the point where the target cpu disables interrupts
		 * in stop machine. I doubt that it can happen, but at least
		 * there is a theroretical chance. Virtualization might be
		 * able to expose this, but AFAICT the IOAPIC emulation is not
		 * as stupid as the real hardware.
		 *
		 * Anyway, there is nothing we can do about that at this point
		 * w/o refactoring the whole fixup_irq() business completely.
		 * We print at least the irq number and the old vector number,
		 * so we have the necessary information when a problem in that
		 * area arises.
736
		 */
737 738
		pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
			irqdata->irq, cfg->old_vector);
739
	}
740 741 742 743 744 745 746 747 748 749
	/*
	 * If old_domain is not empty, then other cpus still have the irq
	 * descriptor set in their vector array. Clean it up.
	 */
	for_each_cpu(cpu, data->old_domain)
		per_cpu(vector_irq, cpu)[cfg->old_vector] = VECTOR_UNUSED;

	/* Cleanup the left overs of the (half finished) move */
	cpumask_clear(data->old_domain);
	data->move_in_progress = 0;
750
	raw_spin_unlock(&vector_lock);
751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770
}
#endif

static void __init print_APIC_field(int base)
{
	int i;

	printk(KERN_DEBUG);

	for (i = 0; i < 8; i++)
		pr_cont("%08x", apic_read(base + i*0x10));

	pr_cont("\n");
}

static void __init print_local_APIC(void *dummy)
{
	unsigned int i, v, ver, maxlvt;
	u64 icr;

771 772
	pr_debug("printing local APIC contents on CPU#%d/%d:\n",
		 smp_processor_id(), hard_smp_processor_id());
773
	v = apic_read(APIC_ID);
774
	pr_info("... APIC ID:      %08x (%01x)\n", v, read_apic_id());
775
	v = apic_read(APIC_LVR);
776
	pr_info("... APIC VERSION: %08x\n", v);
777 778 779 780
	ver = GET_APIC_VERSION(v);
	maxlvt = lapic_get_maxlvt();

	v = apic_read(APIC_TASKPRI);
781
	pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
782 783 784 785 786

	/* !82489DX */
	if (APIC_INTEGRATED(ver)) {
		if (!APIC_XAPIC(ver)) {
			v = apic_read(APIC_ARBPRI);
787 788
			pr_debug("... APIC ARBPRI: %08x (%02x)\n",
				 v, v & APIC_ARBPRI_MASK);
789 790
		}
		v = apic_read(APIC_PROCPRI);
791
		pr_debug("... APIC PROCPRI: %08x\n", v);
792 793 794 795 796 797 798 799
	}

	/*
	 * Remote read supported only in the 82489DX and local APIC for
	 * Pentium processors.
	 */
	if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
		v = apic_read(APIC_RRR);
800
		pr_debug("... APIC RRR: %08x\n", v);
801 802 803
	}

	v = apic_read(APIC_LDR);
804
	pr_debug("... APIC LDR: %08x\n", v);
805 806
	if (!x2apic_enabled()) {
		v = apic_read(APIC_DFR);
807
		pr_debug("... APIC DFR: %08x\n", v);
808 809
	}
	v = apic_read(APIC_SPIV);
810
	pr_debug("... APIC SPIV: %08x\n", v);
811

812
	pr_debug("... APIC ISR field:\n");
813
	print_APIC_field(APIC_ISR);
814
	pr_debug("... APIC TMR field:\n");
815
	print_APIC_field(APIC_TMR);
816
	pr_debug("... APIC IRR field:\n");
817 818 819 820 821 822 823 824 825
	print_APIC_field(APIC_IRR);

	/* !82489DX */
	if (APIC_INTEGRATED(ver)) {
		/* Due to the Pentium erratum 3AP. */
		if (maxlvt > 3)
			apic_write(APIC_ESR, 0);

		v = apic_read(APIC_ESR);
826
		pr_debug("... APIC ESR: %08x\n", v);
827 828 829
	}

	icr = apic_icr_read();
830 831
	pr_debug("... APIC ICR: %08x\n", (u32)icr);
	pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
832 833

	v = apic_read(APIC_LVTT);
834
	pr_debug("... APIC LVTT: %08x\n", v);
835 836 837 838

	if (maxlvt > 3) {
		/* PC is LVT#4. */
		v = apic_read(APIC_LVTPC);
839
		pr_debug("... APIC LVTPC: %08x\n", v);
840 841
	}
	v = apic_read(APIC_LVT0);
842
	pr_debug("... APIC LVT0: %08x\n", v);
843
	v = apic_read(APIC_LVT1);
844
	pr_debug("... APIC LVT1: %08x\n", v);
845 846 847 848

	if (maxlvt > 2) {
		/* ERR is LVT#3. */
		v = apic_read(APIC_LVTERR);
849
		pr_debug("... APIC LVTERR: %08x\n", v);
850 851 852
	}

	v = apic_read(APIC_TMICT);
853
	pr_debug("... APIC TMICT: %08x\n", v);
854
	v = apic_read(APIC_TMCCT);
855
	pr_debug("... APIC TMCCT: %08x\n", v);
856
	v = apic_read(APIC_TDCR);
857
	pr_debug("... APIC TDCR: %08x\n", v);
858 859 860 861

	if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
		v = apic_read(APIC_EFEAT);
		maxlvt = (v >> 16) & 0xff;
862
		pr_debug("... APIC EFEAT: %08x\n", v);
863
		v = apic_read(APIC_ECTRL);
864
		pr_debug("... APIC ECTRL: %08x\n", v);
865 866
		for (i = 0; i < maxlvt; i++) {
			v = apic_read(APIC_EILVTn(i));
867
			pr_debug("... APIC EILVT%d: %08x\n", i, v);
868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896
		}
	}
	pr_cont("\n");
}

static void __init print_local_APICs(int maxcpu)
{
	int cpu;

	if (!maxcpu)
		return;

	preempt_disable();
	for_each_online_cpu(cpu) {
		if (cpu >= maxcpu)
			break;
		smp_call_function_single(cpu, print_local_APIC, NULL, 1);
	}
	preempt_enable();
}

static void __init print_PIC(void)
{
	unsigned int v;
	unsigned long flags;

	if (!nr_legacy_irqs())
		return;

897
	pr_debug("\nprinting PIC contents\n");
898 899 900 901

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	v = inb(0xa1) << 8 | inb(0x21);
902
	pr_debug("... PIC  IMR: %04x\n", v);
903 904

	v = inb(0xa0) << 8 | inb(0x20);
905
	pr_debug("... PIC  IRR: %04x\n", v);
906 907 908 909 910 911 912 913 914

	outb(0x0b, 0xa0);
	outb(0x0b, 0x20);
	v = inb(0xa0) << 8 | inb(0x20);
	outb(0x0a, 0xa0);
	outb(0x0a, 0x20);

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);

915
	pr_debug("... PIC  ISR: %04x\n", v);
916 917

	v = inb(0x4d1) << 8 | inb(0x4d0);
918
	pr_debug("... PIC ELCR: %04x\n", v);
919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955
}

static int show_lapic __initdata = 1;
static __init int setup_show_lapic(char *arg)
{
	int num = -1;

	if (strcmp(arg, "all") == 0) {
		show_lapic = CONFIG_NR_CPUS;
	} else {
		get_option(&arg, &num);
		if (num >= 0)
			show_lapic = num;
	}

	return 1;
}
__setup("show_lapic=", setup_show_lapic);

static int __init print_ICs(void)
{
	if (apic_verbosity == APIC_QUIET)
		return 0;

	print_PIC();

	/* don't print out if apic is not there */
	if (!cpu_has_apic && !apic_from_smp_config())
		return 0;

	print_local_APICs(show_lapic);
	print_IO_APICs();

	return 0;
}

late_initcall(print_ICs);