vector.c 19.6 KB
Newer Older
1 2 3 4 5
/*
 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
 *
 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
 *	Moved from arch/x86/kernel/apic/io_apic.c.
6 7
 * Jiang Liu <jiang.liu@linux.intel.com>
 *	Enable support of hierarchical irqdomains
8 9 10 11 12 13 14 15 16
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/compiler.h>
#include <linux/slab.h>
17
#include <asm/irqdomain.h>
18 19 20 21 22 23
#include <asm/hw_irq.h>
#include <asm/apic.h>
#include <asm/i8259.h>
#include <asm/desc.h>
#include <asm/irq_remapping.h>

24 25 26 27 28 29 30
struct apic_chip_data {
	struct irq_cfg		cfg;
	cpumask_var_t		domain;
	cpumask_var_t		old_domain;
	u8			move_in_progress : 1;
};

31
struct irq_domain *x86_vector_domain;
32
EXPORT_SYMBOL_GPL(x86_vector_domain);
33
static DEFINE_RAW_SPINLOCK(vector_lock);
34
static cpumask_var_t vector_cpumask;
35
static struct irq_chip lapic_controller;
36
#ifdef	CONFIG_X86_IO_APIC
37
static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];
38
#endif
39 40 41 42 43 44 45 46 47 48 49 50 51 52

void lock_vector_lock(void)
{
	/* Used to the online set of cpus does not change
	 * during assign_irq_vector.
	 */
	raw_spin_lock(&vector_lock);
}

void unlock_vector_lock(void)
{
	raw_spin_unlock(&vector_lock);
}

53
static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data)
54
{
55 56 57 58 59 60
	if (!irq_data)
		return NULL;

	while (irq_data->parent_data)
		irq_data = irq_data->parent_data;

61 62 63
	return irq_data->chip_data;
}

64 65 66 67 68 69
struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
{
	struct apic_chip_data *data = apic_chip_data(irq_data);

	return data ? &data->cfg : NULL;
}
70
EXPORT_SYMBOL_GPL(irqd_cfg);
71 72

struct irq_cfg *irq_cfg(unsigned int irq)
73
{
74 75
	return irqd_cfg(irq_get_irq_data(irq));
}
76

77 78 79 80 81 82
static struct apic_chip_data *alloc_apic_chip_data(int node)
{
	struct apic_chip_data *data;

	data = kzalloc_node(sizeof(*data), GFP_KERNEL, node);
	if (!data)
83
		return NULL;
84 85 86
	if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node))
		goto out_data;
	if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node))
87
		goto out_domain;
88
	return data;
89
out_domain:
90 91 92
	free_cpumask_var(data->domain);
out_data:
	kfree(data);
93 94 95
	return NULL;
}

96
static void free_apic_chip_data(struct apic_chip_data *data)
97
{
98 99 100 101
	if (data) {
		free_cpumask_var(data->domain);
		free_cpumask_var(data->old_domain);
		kfree(data);
102
	}
103 104
}

105 106
static int __assign_irq_vector(int irq, struct apic_chip_data *d,
			       const struct cpumask *mask)
107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122
{
	/*
	 * NOTE! The local APIC isn't very good at handling
	 * multiple interrupts at the same interrupt level.
	 * As the interrupt level is determined by taking the
	 * vector number and shifting that right by 4, we
	 * want to spread these out a bit so that they don't
	 * all fall in the same interrupt level.
	 *
	 * Also, we've got to be careful not to trash gate
	 * 0x80, because int 0x80 is hm, kind of importantish. ;)
	 */
	static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
	static int current_offset = VECTOR_OFFSET_START % 16;
	int cpu, err;

123
	if (d->move_in_progress)
124 125 126 127
		return -EBUSY;

	/* Only try and allocate irqs on cpus that are present */
	err = -ENOSPC;
128
	cpumask_clear(d->old_domain);
129 130 131 132
	cpu = cpumask_first_and(mask, cpu_online_mask);
	while (cpu < nr_cpu_ids) {
		int new_cpu, vector, offset;

133
		apic->vector_allocation_domain(cpu, vector_cpumask, mask);
134

135
		if (cpumask_subset(vector_cpumask, d->domain)) {
136
			err = 0;
137
			if (cpumask_equal(vector_cpumask, d->domain))
138 139 140 141 142 143
				break;
			/*
			 * New cpumask using the vector is a proper subset of
			 * the current in use mask. So cleanup the vector
			 * allocation for the members that are not used anymore.
			 */
144 145
			cpumask_andnot(d->old_domain, d->domain,
				       vector_cpumask);
146 147
			d->move_in_progress =
			   cpumask_intersects(d->old_domain, cpu_online_mask);
148
			cpumask_and(d->domain, d->domain, vector_cpumask);
149 150 151 152 153 154 155 156 157 158 159 160 161
			break;
		}

		vector = current_vector;
		offset = current_offset;
next:
		vector += 16;
		if (vector >= first_system_vector) {
			offset = (offset + 1) % 16;
			vector = FIRST_EXTERNAL_VECTOR + offset;
		}

		if (unlikely(current_vector == vector)) {
162 163 164 165 166
			cpumask_or(d->old_domain, d->old_domain,
				   vector_cpumask);
			cpumask_andnot(vector_cpumask, mask, d->old_domain);
			cpu = cpumask_first_and(vector_cpumask,
						cpu_online_mask);
167 168 169 170 171 172
			continue;
		}

		if (test_bit(vector, used_vectors))
			goto next;

173
		for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) {
174
			if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector]))
175 176 177 178 179
				goto next;
		}
		/* Found one! */
		current_vector = vector;
		current_offset = offset;
180 181 182 183
		if (d->cfg.vector) {
			cpumask_copy(d->old_domain, d->domain);
			d->move_in_progress =
			   cpumask_intersects(d->old_domain, cpu_online_mask);
184
		}
185
		for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask)
186
			per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq);
187
		d->cfg.vector = vector;
188
		cpumask_copy(d->domain, vector_cpumask);
189 190 191 192
		err = 0;
		break;
	}

193 194
	if (!err) {
		/* cache destination APIC IDs into cfg->dest_apicid */
195 196
		err = apic->cpu_mask_to_apicid_and(mask, d->domain,
						   &d->cfg.dest_apicid);
197 198
	}

199 200 201
	return err;
}

202
static int assign_irq_vector(int irq, struct apic_chip_data *data,
203
			     const struct cpumask *mask)
204 205 206 207 208
{
	int err;
	unsigned long flags;

	raw_spin_lock_irqsave(&vector_lock, flags);
209
	err = __assign_irq_vector(irq, data, mask);
210 211 212 213
	raw_spin_unlock_irqrestore(&vector_lock, flags);
	return err;
}

214 215 216 217 218 219 220 221 222 223 224 225
static int assign_irq_vector_policy(int irq, int node,
				    struct apic_chip_data *data,
				    struct irq_alloc_info *info)
{
	if (info && info->mask)
		return assign_irq_vector(irq, data, info->mask);
	if (node != NUMA_NO_NODE &&
	    assign_irq_vector(irq, data, cpumask_of_node(node)) == 0)
		return 0;
	return assign_irq_vector(irq, data, apic->target_cpus());
}

226
static void clear_irq_vector(int irq, struct apic_chip_data *data)
227
{
228
	struct irq_desc *desc;
229
	unsigned long flags;
230
	int cpu, vector;
231 232

	raw_spin_lock_irqsave(&vector_lock, flags);
233
	BUG_ON(!data->cfg.vector);
234

235 236
	vector = data->cfg.vector;
	for_each_cpu_and(cpu, data->domain, cpu_online_mask)
237
		per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
238

239 240
	data->cfg.vector = 0;
	cpumask_clear(data->domain);
241

242
	if (likely(!data->move_in_progress)) {
243 244 245 246
		raw_spin_unlock_irqrestore(&vector_lock, flags);
		return;
	}

247
	desc = irq_to_desc(irq);
248
	for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) {
249 250
		for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
		     vector++) {
251
			if (per_cpu(vector_irq, cpu)[vector] != desc)
252
				continue;
253
			per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
254 255 256
			break;
		}
	}
257
	data->move_in_progress = 0;
258 259 260
	raw_spin_unlock_irqrestore(&vector_lock, flags);
}

261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285
void init_irq_alloc_info(struct irq_alloc_info *info,
			 const struct cpumask *mask)
{
	memset(info, 0, sizeof(*info));
	info->mask = mask;
}

void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
{
	if (src)
		*dst = *src;
	else
		memset(dst, 0, sizeof(*dst));
}

static void x86_vector_free_irqs(struct irq_domain *domain,
				 unsigned int virq, unsigned int nr_irqs)
{
	struct irq_data *irq_data;
	int i;

	for (i = 0; i < nr_irqs; i++) {
		irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i);
		if (irq_data && irq_data->chip_data) {
			clear_irq_vector(virq + i, irq_data->chip_data);
286
			free_apic_chip_data(irq_data->chip_data);
287 288
#ifdef	CONFIG_X86_IO_APIC
			if (virq + i < nr_legacy_irqs())
289
				legacy_irq_data[virq + i] = NULL;
290
#endif
291 292 293 294 295 296 297 298 299
			irq_domain_reset_irq_data(irq_data);
		}
	}
}

static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
				 unsigned int nr_irqs, void *arg)
{
	struct irq_alloc_info *info = arg;
300
	struct apic_chip_data *data;
301
	struct irq_data *irq_data;
302
	int i, err, node;
303 304 305 306 307 308 309 310 311 312 313

	if (disable_apic)
		return -ENXIO;

	/* Currently vector allocator can't guarantee contiguous allocations */
	if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
		return -ENOSYS;

	for (i = 0; i < nr_irqs; i++) {
		irq_data = irq_domain_get_irq_data(domain, virq + i);
		BUG_ON(!irq_data);
314
		node = irq_data_get_node(irq_data);
315
#ifdef	CONFIG_X86_IO_APIC
316 317
		if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i])
			data = legacy_irq_data[virq + i];
318 319
		else
#endif
320
			data = alloc_apic_chip_data(node);
321
		if (!data) {
322 323 324 325 326
			err = -ENOMEM;
			goto error;
		}

		irq_data->chip = &lapic_controller;
327
		irq_data->chip_data = data;
328
		irq_data->hwirq = virq + i;
329
		err = assign_irq_vector_policy(virq + i, node, data, info);
330 331 332 333 334 335 336 337 338 339 340
		if (err)
			goto error;
	}

	return 0;

error:
	x86_vector_free_irqs(domain, virq, i + 1);
	return err;
}

T
Thomas Gleixner 已提交
341 342 343
static const struct irq_domain_ops x86_vector_domain_ops = {
	.alloc	= x86_vector_alloc_irqs,
	.free	= x86_vector_free_irqs,
344 345
};

346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365
int __init arch_probe_nr_irqs(void)
{
	int nr;

	if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
		nr_irqs = NR_VECTORS * nr_cpu_ids;

	nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
	/*
	 * for MSI and HT dyn irq
	 */
	if (gsi_top <= NR_IRQS_LEGACY)
		nr +=  8 * nr_cpu_ids;
	else
		nr += gsi_top * 16;
#endif
	if (nr < nr_irqs)
		nr_irqs = nr;

366 367 368 369 370
	/*
	 * We don't know if PIC is present at this point so we need to do
	 * probe() to get the right number of legacy IRQs.
	 */
	return legacy_pic->probe();
371 372
}

373 374 375 376
#ifdef	CONFIG_X86_IO_APIC
static void init_legacy_irqs(void)
{
	int i, node = cpu_to_node(0);
377
	struct apic_chip_data *data;
378 379 380

	/*
	 * For legacy IRQ's, start with assigning irq0 to irq15 to
381
	 * ISA_IRQ_VECTOR(i) for all cpu's.
382 383
	 */
	for (i = 0; i < nr_legacy_irqs(); i++) {
384 385
		data = legacy_irq_data[i] = alloc_apic_chip_data(node);
		BUG_ON(!data);
386 387

		data->cfg.vector = ISA_IRQ_VECTOR(i);
388 389
		cpumask_setall(data->domain);
		irq_set_chip_data(i, data);
390 391 392 393 394 395
	}
}
#else
static void init_legacy_irqs(void) { }
#endif

396 397
int __init arch_early_irq_init(void)
{
398 399
	init_legacy_irqs();

400 401 402 403 404
	x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops,
						NULL);
	BUG_ON(x86_vector_domain == NULL);
	irq_set_default_host(x86_vector_domain);

405
	arch_init_msi_domain(x86_vector_domain);
406
	arch_init_htirq_domain(x86_vector_domain);
407

408 409
	BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL));

410 411 412
	return arch_early_ioapic_init();
}

413
/* Initialize vector_irq on a new cpu */
414 415
static void __setup_vector_irq(int cpu)
{
416
	struct apic_chip_data *data;
417 418
	struct irq_desc *desc;
	int irq, vector;
419 420

	/* Mark the inuse vectors */
421 422
	for_each_irq_desc(irq, desc) {
		struct irq_data *idata = irq_desc_get_irq_data(desc);
423

424 425
		data = apic_chip_data(idata);
		if (!data || !cpumask_test_cpu(cpu, data->domain))
426
			continue;
427
		vector = data->cfg.vector;
428
		per_cpu(vector_irq, cpu)[vector] = desc;
429 430 431
	}
	/* Mark the free vectors */
	for (vector = 0; vector < NR_VECTORS; ++vector) {
432 433
		desc = per_cpu(vector_irq, cpu)[vector];
		if (IS_ERR_OR_NULL(desc))
434 435
			continue;

436
		data = apic_chip_data(irq_desc_get_irq_data(desc));
437
		if (!cpumask_test_cpu(cpu, data->domain))
438
			per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
439 440 441 442
	}
}

/*
443
 * Setup the vector to irq mappings. Must be called with vector_lock held.
444 445 446 447 448
 */
void setup_vector_irq(int cpu)
{
	int irq;

449
	lockdep_assert_held(&vector_lock);
450 451 452 453 454 455 456 457
	/*
	 * On most of the platforms, legacy PIC delivers the interrupts on the
	 * boot cpu. But there are certain platforms where PIC interrupts are
	 * delivered to multiple cpu's. If the legacy IRQ is handled by the
	 * legacy PIC, for the new cpu that is coming online, setup the static
	 * legacy vector to irq mapping:
	 */
	for (irq = 0; irq < nr_legacy_irqs(); irq++)
458
		per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq);
459 460 461 462

	__setup_vector_irq(cpu);
}

463
static int apic_retrigger_irq(struct irq_data *irq_data)
464
{
465
	struct apic_chip_data *data = apic_chip_data(irq_data);
466 467 468 469
	unsigned long flags;
	int cpu;

	raw_spin_lock_irqsave(&vector_lock, flags);
470 471
	cpu = cpumask_first_and(data->domain, cpu_online_mask);
	apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector);
472 473 474 475 476 477 478
	raw_spin_unlock_irqrestore(&vector_lock, flags);

	return 1;
}

void apic_ack_edge(struct irq_data *data)
{
479
	irq_complete_move(irqd_cfg(data));
480 481 482 483
	irq_move_irq(data);
	ack_APIC_irq();
}

484 485
static int apic_set_affinity(struct irq_data *irq_data,
			     const struct cpumask *dest, bool force)
486
{
487
	struct apic_chip_data *data = irq_data->chip_data;
488 489 490 491 492 493 494 495
	int err, irq = irq_data->irq;

	if (!config_enabled(CONFIG_SMP))
		return -EPERM;

	if (!cpumask_intersects(dest, cpu_online_mask))
		return -EINVAL;

496
	err = assign_irq_vector(irq, data, dest);
497
	if (err) {
498
		if (assign_irq_vector(irq, data,
499
				      irq_data_get_affinity_mask(irq_data)))
500 501 502 503 504 505 506 507 508
			pr_err("Failed to recover vector for irq %d\n", irq);
		return err;
	}

	return IRQ_SET_MASK_OK;
}

static struct irq_chip lapic_controller = {
	.irq_ack		= apic_ack_edge,
509
	.irq_set_affinity	= apic_set_affinity,
510 511 512
	.irq_retrigger		= apic_retrigger_irq,
};

513
#ifdef CONFIG_SMP
514
static void __send_cleanup_vector(struct apic_chip_data *data)
515 516 517 518 519 520
{
	cpumask_var_t cleanup_mask;

	if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
		unsigned int i;

521
		for_each_cpu_and(i, data->old_domain, cpu_online_mask)
522 523 524
			apic->send_IPI_mask(cpumask_of(i),
					    IRQ_MOVE_CLEANUP_VECTOR);
	} else {
525
		cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask);
526 527 528
		apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
		free_cpumask_var(cleanup_mask);
	}
529
	data->move_in_progress = 0;
530 531
}

532 533
void send_cleanup_vector(struct irq_cfg *cfg)
{
534 535 536 537 538
	struct apic_chip_data *data;

	data = container_of(cfg, struct apic_chip_data, cfg);
	if (data->move_in_progress)
		__send_cleanup_vector(data);
539 540
}

541 542 543 544
asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
{
	unsigned vector, me;

545
	entering_ack_irq();
546

547 548 549
	/* Prevent vectors vanishing under us */
	raw_spin_lock(&vector_lock);

550 551
	me = smp_processor_id();
	for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
552
		struct apic_chip_data *data;
553 554
		struct irq_desc *desc;
		unsigned int irr;
555

556
	retry:
557 558
		desc = __this_cpu_read(vector_irq[vector]);
		if (IS_ERR_OR_NULL(desc))
559 560
			continue;

561 562 563 564 565 566
		if (!raw_spin_trylock(&desc->lock)) {
			raw_spin_unlock(&vector_lock);
			cpu_relax();
			raw_spin_lock(&vector_lock);
			goto retry;
		}
567

568
		data = apic_chip_data(irq_desc_get_irq_data(desc));
569
		if (!data)
570
			goto unlock;
571 572 573 574 575

		/*
		 * Check if the irq migration is in progress. If so, we
		 * haven't received the cleanup request yet for this irq.
		 */
576
		if (data->move_in_progress)
577 578
			goto unlock;

579 580
		if (vector == data->cfg.vector &&
		    cpumask_test_cpu(me, data->domain))
581 582 583 584 585 586 587 588 589 590 591 592 593 594
			goto unlock;

		irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
		/*
		 * Check if the vector that needs to be cleanedup is
		 * registered at the cpu's IRR. If so, then this is not
		 * the best time to clean it up. Lets clean it up in the
		 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
		 * to myself.
		 */
		if (irr  & (1 << (vector % 32))) {
			apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
			goto unlock;
		}
595
		__this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
596 597 598 599
unlock:
		raw_spin_unlock(&desc->lock);
	}

600 601
	raw_spin_unlock(&vector_lock);

602
	exiting_irq();
603 604 605 606 607
}

static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
{
	unsigned me;
608
	struct apic_chip_data *data;
609

610 611
	data = container_of(cfg, struct apic_chip_data, cfg);
	if (likely(!data->move_in_progress))
612 613 614
		return;

	me = smp_processor_id();
615 616
	if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain))
		__send_cleanup_vector(data);
617 618 619 620 621 622 623 624 625 626 627
}

void irq_complete_move(struct irq_cfg *cfg)
{
	__irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
}

void irq_force_complete_move(int irq)
{
	struct irq_cfg *cfg = irq_cfg(irq);

628 629
	if (cfg)
		__irq_complete_move(cfg, cfg->vector);
630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649
}
#endif

static void __init print_APIC_field(int base)
{
	int i;

	printk(KERN_DEBUG);

	for (i = 0; i < 8; i++)
		pr_cont("%08x", apic_read(base + i*0x10));

	pr_cont("\n");
}

static void __init print_local_APIC(void *dummy)
{
	unsigned int i, v, ver, maxlvt;
	u64 icr;

650 651
	pr_debug("printing local APIC contents on CPU#%d/%d:\n",
		 smp_processor_id(), hard_smp_processor_id());
652
	v = apic_read(APIC_ID);
653
	pr_info("... APIC ID:      %08x (%01x)\n", v, read_apic_id());
654
	v = apic_read(APIC_LVR);
655
	pr_info("... APIC VERSION: %08x\n", v);
656 657 658 659
	ver = GET_APIC_VERSION(v);
	maxlvt = lapic_get_maxlvt();

	v = apic_read(APIC_TASKPRI);
660
	pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
661 662 663 664 665

	/* !82489DX */
	if (APIC_INTEGRATED(ver)) {
		if (!APIC_XAPIC(ver)) {
			v = apic_read(APIC_ARBPRI);
666 667
			pr_debug("... APIC ARBPRI: %08x (%02x)\n",
				 v, v & APIC_ARBPRI_MASK);
668 669
		}
		v = apic_read(APIC_PROCPRI);
670
		pr_debug("... APIC PROCPRI: %08x\n", v);
671 672 673 674 675 676 677 678
	}

	/*
	 * Remote read supported only in the 82489DX and local APIC for
	 * Pentium processors.
	 */
	if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
		v = apic_read(APIC_RRR);
679
		pr_debug("... APIC RRR: %08x\n", v);
680 681 682
	}

	v = apic_read(APIC_LDR);
683
	pr_debug("... APIC LDR: %08x\n", v);
684 685
	if (!x2apic_enabled()) {
		v = apic_read(APIC_DFR);
686
		pr_debug("... APIC DFR: %08x\n", v);
687 688
	}
	v = apic_read(APIC_SPIV);
689
	pr_debug("... APIC SPIV: %08x\n", v);
690

691
	pr_debug("... APIC ISR field:\n");
692
	print_APIC_field(APIC_ISR);
693
	pr_debug("... APIC TMR field:\n");
694
	print_APIC_field(APIC_TMR);
695
	pr_debug("... APIC IRR field:\n");
696 697 698 699 700 701 702 703 704
	print_APIC_field(APIC_IRR);

	/* !82489DX */
	if (APIC_INTEGRATED(ver)) {
		/* Due to the Pentium erratum 3AP. */
		if (maxlvt > 3)
			apic_write(APIC_ESR, 0);

		v = apic_read(APIC_ESR);
705
		pr_debug("... APIC ESR: %08x\n", v);
706 707 708
	}

	icr = apic_icr_read();
709 710
	pr_debug("... APIC ICR: %08x\n", (u32)icr);
	pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
711 712

	v = apic_read(APIC_LVTT);
713
	pr_debug("... APIC LVTT: %08x\n", v);
714 715 716 717

	if (maxlvt > 3) {
		/* PC is LVT#4. */
		v = apic_read(APIC_LVTPC);
718
		pr_debug("... APIC LVTPC: %08x\n", v);
719 720
	}
	v = apic_read(APIC_LVT0);
721
	pr_debug("... APIC LVT0: %08x\n", v);
722
	v = apic_read(APIC_LVT1);
723
	pr_debug("... APIC LVT1: %08x\n", v);
724 725 726 727

	if (maxlvt > 2) {
		/* ERR is LVT#3. */
		v = apic_read(APIC_LVTERR);
728
		pr_debug("... APIC LVTERR: %08x\n", v);
729 730 731
	}

	v = apic_read(APIC_TMICT);
732
	pr_debug("... APIC TMICT: %08x\n", v);
733
	v = apic_read(APIC_TMCCT);
734
	pr_debug("... APIC TMCCT: %08x\n", v);
735
	v = apic_read(APIC_TDCR);
736
	pr_debug("... APIC TDCR: %08x\n", v);
737 738 739 740

	if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
		v = apic_read(APIC_EFEAT);
		maxlvt = (v >> 16) & 0xff;
741
		pr_debug("... APIC EFEAT: %08x\n", v);
742
		v = apic_read(APIC_ECTRL);
743
		pr_debug("... APIC ECTRL: %08x\n", v);
744 745
		for (i = 0; i < maxlvt; i++) {
			v = apic_read(APIC_EILVTn(i));
746
			pr_debug("... APIC EILVT%d: %08x\n", i, v);
747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775
		}
	}
	pr_cont("\n");
}

static void __init print_local_APICs(int maxcpu)
{
	int cpu;

	if (!maxcpu)
		return;

	preempt_disable();
	for_each_online_cpu(cpu) {
		if (cpu >= maxcpu)
			break;
		smp_call_function_single(cpu, print_local_APIC, NULL, 1);
	}
	preempt_enable();
}

static void __init print_PIC(void)
{
	unsigned int v;
	unsigned long flags;

	if (!nr_legacy_irqs())
		return;

776
	pr_debug("\nprinting PIC contents\n");
777 778 779 780

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	v = inb(0xa1) << 8 | inb(0x21);
781
	pr_debug("... PIC  IMR: %04x\n", v);
782 783

	v = inb(0xa0) << 8 | inb(0x20);
784
	pr_debug("... PIC  IRR: %04x\n", v);
785 786 787 788 789 790 791 792 793

	outb(0x0b, 0xa0);
	outb(0x0b, 0x20);
	v = inb(0xa0) << 8 | inb(0x20);
	outb(0x0a, 0xa0);
	outb(0x0a, 0x20);

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);

794
	pr_debug("... PIC  ISR: %04x\n", v);
795 796

	v = inb(0x4d1) << 8 | inb(0x4d0);
797
	pr_debug("... PIC ELCR: %04x\n", v);
798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834
}

static int show_lapic __initdata = 1;
static __init int setup_show_lapic(char *arg)
{
	int num = -1;

	if (strcmp(arg, "all") == 0) {
		show_lapic = CONFIG_NR_CPUS;
	} else {
		get_option(&arg, &num);
		if (num >= 0)
			show_lapic = num;
	}

	return 1;
}
__setup("show_lapic=", setup_show_lapic);

static int __init print_ICs(void)
{
	if (apic_verbosity == APIC_QUIET)
		return 0;

	print_PIC();

	/* don't print out if apic is not there */
	if (!cpu_has_apic && !apic_from_smp_config())
		return 0;

	print_local_APICs(show_lapic);
	print_IO_APICs();

	return 0;
}

late_initcall(print_ICs);