emulate.c 98.4 KB
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/******************************************************************************
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 * emulate.c
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 *
 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
 *
 * Copyright (c) 2005 Keir Fraser
 *
 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
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 * privileged instructions:
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 *
 * Copyright (C) 2006 Qumranet
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 * Copyright 2010 Red Hat, Inc. and/or its affilates.
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 *
 *   Avi Kivity <avi@qumranet.com>
 *   Yaniv Kamay <yaniv@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
 */

#ifndef __KERNEL__
#include <stdio.h>
#include <stdint.h>
#include <public/xen.h>
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#define DPRINTF(_f, _a ...) printf(_f , ## _a)
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#else
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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#define DPRINTF(x...) do {} while (0)
#endif
#include <linux/module.h>
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#include <asm/kvm_emulate.h>
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#include "x86.h"
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#include "tss.h"
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/*
 * Opcode effective-address decode tables.
 * Note that we only emulate instructions that have at least one memory
 * operand (excluding implicit stack references). We assume that stack
 * references and instruction fetches will never occur in special memory
 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
 * not be handled.
 */

/* Operand sizes: 8-bit operands or specified/overridden size. */
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#define ByteOp      (1<<0)	/* 8-bit operands. */
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/* Destination operand type. */
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#define ImplicitOps (1<<1)	/* Implicit in opcode. No generic decode. */
#define DstReg      (2<<1)	/* Register operand. */
#define DstMem      (3<<1)	/* Memory operand. */
#define DstAcc      (4<<1)	/* Destination Accumulator */
#define DstDI       (5<<1)	/* Destination is in ES:(E)DI */
#define DstMem64    (6<<1)	/* 64bit memory operand */
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#define DstImmUByte (7<<1)	/* 8-bit unsigned immediate operand */
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#define DstMask     (7<<1)
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/* Source operand type. */
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#define SrcNone     (0<<4)	/* No source operand. */
#define SrcReg      (1<<4)	/* Register operand. */
#define SrcMem      (2<<4)	/* Memory operand. */
#define SrcMem16    (3<<4)	/* Memory operand (16-bit). */
#define SrcMem32    (4<<4)	/* Memory operand (32-bit). */
#define SrcImm      (5<<4)	/* Immediate operand. */
#define SrcImmByte  (6<<4)	/* 8-bit sign-extended immediate operand. */
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#define SrcOne      (7<<4)	/* Implied '1' */
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#define SrcImmUByte (8<<4)      /* 8-bit unsigned immediate operand. */
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#define SrcImmU     (9<<4)      /* Immediate operand, unsigned */
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#define SrcSI       (0xa<<4)	/* Source is in the DS:RSI */
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#define SrcImmFAddr (0xb<<4)	/* Source is immediate far address */
#define SrcMemFAddr (0xc<<4)	/* Source is far address in memory */
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#define SrcAcc      (0xd<<4)	/* Source Accumulator */
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#define SrcImmU16   (0xe<<4)    /* Immediate operand, unsigned, 16 bits */
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#define SrcMask     (0xf<<4)
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/* Generic ModRM decode. */
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#define ModRM       (1<<8)
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/* Destination is only written; never read. */
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#define Mov         (1<<9)
#define BitOp       (1<<10)
#define MemAbs      (1<<11)      /* Memory operand is absolute displacement */
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#define String      (1<<12)     /* String instruction (rep capable) */
#define Stack       (1<<13)     /* Stack instruction (push/pop) */
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#define Group       (1<<14)     /* Bits 3:5 of modrm byte extend opcode */
#define GroupDual   (1<<15)     /* Alternate decoding of mod == 3 */
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/* Misc flags */
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#define NoAccess    (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
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#define Op3264      (1<<24) /* Operand is 64b in long mode, 32b otherwise */
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#define Undefined   (1<<25) /* No Such Instruction */
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#define Lock        (1<<26) /* lock prefix is allowed for the instruction */
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#define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
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#define No64	    (1<<28)
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/* Source 2 operand type */
#define Src2None    (0<<29)
#define Src2CL      (1<<29)
#define Src2ImmByte (2<<29)
#define Src2One     (3<<29)
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#define Src2Imm     (4<<29)
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#define Src2Mask    (7<<29)
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#define X2(x...) x, x
#define X3(x...) X2(x), x
#define X4(x...) X2(x), X2(x)
#define X5(x...) X4(x), x
#define X6(x...) X4(x), X2(x)
#define X7(x...) X4(x), X3(x)
#define X8(x...) X4(x), X4(x)
#define X16(x...) X8(x), X8(x)
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struct opcode {
	u32 flags;
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	union {
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		int (*execute)(struct x86_emulate_ctxt *ctxt);
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		struct opcode *group;
		struct group_dual *gdual;
	} u;
};

struct group_dual {
	struct opcode mod012[8];
	struct opcode mod3[8];
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};

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/* EFLAGS bit definitions. */
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#define EFLG_ID (1<<21)
#define EFLG_VIP (1<<20)
#define EFLG_VIF (1<<19)
#define EFLG_AC (1<<18)
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#define EFLG_VM (1<<17)
#define EFLG_RF (1<<16)
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#define EFLG_IOPL (3<<12)
#define EFLG_NT (1<<14)
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#define EFLG_OF (1<<11)
#define EFLG_DF (1<<10)
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#define EFLG_IF (1<<9)
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#define EFLG_TF (1<<8)
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#define EFLG_SF (1<<7)
#define EFLG_ZF (1<<6)
#define EFLG_AF (1<<4)
#define EFLG_PF (1<<2)
#define EFLG_CF (1<<0)

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#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
#define EFLG_RESERVED_ONE_MASK 2

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/*
 * Instruction emulation:
 * Most instructions are emulated directly via a fragment of inline assembly
 * code. This allows us to save/restore EFLAGS and thus very easily pick up
 * any modified flags.
 */

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#if defined(CONFIG_X86_64)
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#define _LO32 "k"		/* force 32-bit operand */
#define _STK  "%%rsp"		/* stack pointer */
#elif defined(__i386__)
#define _LO32 ""		/* force 32-bit operand */
#define _STK  "%%esp"		/* stack pointer */
#endif

/*
 * These EFLAGS bits are restored from saved value during emulation, and
 * any changes are written back to the saved value after emulation.
 */
#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)

/* Before executing instruction: restore necessary bits in EFLAGS. */
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#define _PRE_EFLAGS(_sav, _msk, _tmp)					\
	/* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
	"movl %"_sav",%"_LO32 _tmp"; "                                  \
	"push %"_tmp"; "                                                \
	"push %"_tmp"; "                                                \
	"movl %"_msk",%"_LO32 _tmp"; "                                  \
	"andl %"_LO32 _tmp",("_STK"); "                                 \
	"pushf; "                                                       \
	"notl %"_LO32 _tmp"; "                                          \
	"andl %"_LO32 _tmp",("_STK"); "                                 \
	"andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); "	\
	"pop  %"_tmp"; "                                                \
	"orl  %"_LO32 _tmp",("_STK"); "                                 \
	"popf; "                                                        \
	"pop  %"_sav"; "
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/* After executing instruction: write-back necessary bits in EFLAGS. */
#define _POST_EFLAGS(_sav, _msk, _tmp) \
	/* _sav |= EFLAGS & _msk; */		\
	"pushf; "				\
	"pop  %"_tmp"; "			\
	"andl %"_msk",%"_LO32 _tmp"; "		\
	"orl  %"_LO32 _tmp",%"_sav"; "

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#ifdef CONFIG_X86_64
#define ON64(x) x
#else
#define ON64(x)
#endif

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#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
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	do {								\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "4", "2")			\
			_op _suffix " %"_x"3,%1; "			\
			_POST_EFLAGS("0", "4", "2")			\
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			: "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
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			  "=&r" (_tmp)					\
			: _y ((_src).val), "i" (EFLAGS_MASK));		\
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	} while (0)
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/* Raw emulation: instruction has two explicit operands. */
#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
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	do {								\
		unsigned long _tmp;					\
									\
		switch ((_dst).bytes) {					\
		case 2:							\
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			____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
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			break;						\
		case 4:							\
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			____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
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			break;						\
		case 8:							\
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			ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
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			break;						\
		}							\
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	} while (0)

#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
	do {								     \
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		unsigned long _tmp;					     \
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		switch ((_dst).bytes) {				             \
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		case 1:							     \
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			____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
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			break;						     \
		default:						     \
			__emulate_2op_nobyte(_op, _src, _dst, _eflags,	     \
					     _wx, _wy, _lx, _ly, _qx, _qy);  \
			break;						     \
		}							     \
	} while (0)

/* Source operand is byte-sized and may be restricted to just %cl. */
#define emulate_2op_SrcB(_op, _src, _dst, _eflags)                      \
	__emulate_2op(_op, _src, _dst, _eflags,				\
		      "b", "c", "b", "c", "b", "c", "b", "c")

/* Source operand is byte, word, long or quad sized. */
#define emulate_2op_SrcV(_op, _src, _dst, _eflags)                      \
	__emulate_2op(_op, _src, _dst, _eflags,				\
		      "b", "q", "w", "r", _LO32, "r", "", "r")

/* Source operand is word, long or quad sized. */
#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags)               \
	__emulate_2op_nobyte(_op, _src, _dst, _eflags,			\
			     "w", "r", _LO32, "r", "", "r")

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/* Instruction has three operands and one operand is stored in ECX register */
#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) 	\
	do {									\
		unsigned long _tmp;						\
		_type _clv  = (_cl).val;  					\
		_type _srcv = (_src).val;    					\
		_type _dstv = (_dst).val;					\
										\
		__asm__ __volatile__ (						\
			_PRE_EFLAGS("0", "5", "2")				\
			_op _suffix " %4,%1 \n"					\
			_POST_EFLAGS("0", "5", "2")				\
			: "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp)		\
			: "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK)		\
			); 							\
										\
		(_cl).val  = (unsigned long) _clv;				\
		(_src).val = (unsigned long) _srcv;				\
		(_dst).val = (unsigned long) _dstv;				\
	} while (0)

#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags)				\
	do {									\
		switch ((_dst).bytes) {						\
		case 2:								\
			__emulate_2op_cl(_op, _cl, _src, _dst, _eflags,  	\
						"w", unsigned short);         	\
			break;							\
		case 4: 							\
			__emulate_2op_cl(_op, _cl, _src, _dst, _eflags,  	\
						"l", unsigned int);           	\
			break;							\
		case 8:								\
			ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags,	\
						"q", unsigned long));  		\
			break;							\
		}								\
	} while (0)

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#define __emulate_1op(_op, _dst, _eflags, _suffix)			\
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	do {								\
		unsigned long _tmp;					\
									\
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		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "3", "2")			\
			_op _suffix " %1; "				\
			_POST_EFLAGS("0", "3", "2")			\
			: "=m" (_eflags), "+m" ((_dst).val),		\
			  "=&r" (_tmp)					\
			: "i" (EFLAGS_MASK));				\
	} while (0)

/* Instruction has only one explicit operand (no source operand). */
#define emulate_1op(_op, _dst, _eflags)                                    \
	do {								\
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		switch ((_dst).bytes) {				        \
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		case 1:	__emulate_1op(_op, _dst, _eflags, "b"); break;	\
		case 2:	__emulate_1op(_op, _dst, _eflags, "w"); break;	\
		case 4:	__emulate_1op(_op, _dst, _eflags, "l"); break;	\
		case 8:	ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
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		}							\
	} while (0)

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#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix)		\
	do {								\
		unsigned long _tmp;					\
									\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "4", "1")			\
			_op _suffix " %5; "				\
			_POST_EFLAGS("0", "4", "1")			\
			: "=m" (_eflags), "=&r" (_tmp),			\
			  "+a" (_rax), "+d" (_rdx)			\
			: "i" (EFLAGS_MASK), "m" ((_src).val),		\
			  "a" (_rax), "d" (_rdx));			\
	} while (0)

/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags)			\
	do {									\
		switch((_src).bytes) {						\
		case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
		case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx,  _eflags, "w"); break; \
		case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
		case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
		}							\
	} while (0)

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/* Fetch next part of the instruction being emulated. */
#define insn_fetch(_type, _size, _eip)                                  \
({	unsigned long _x;						\
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	rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size));		\
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	if (rc != X86EMUL_CONTINUE)					\
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		goto done;						\
	(_eip) += (_size);						\
	(_type)_x;							\
})

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#define insn_fetch_arr(_arr, _size, _eip)                                \
({	rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size));		\
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
	(_eip) += (_size);						\
})

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static inline unsigned long ad_mask(struct decode_cache *c)
{
	return (1UL << (c->ad_bytes << 3)) - 1;
}

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/* Access/update address held in a register, based on addressing mode. */
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static inline unsigned long
address_mask(struct decode_cache *c, unsigned long reg)
{
	if (c->ad_bytes == sizeof(unsigned long))
		return reg;
	else
		return reg & ad_mask(c);
}

static inline unsigned long
register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
{
	return base + address_mask(c, reg);
}

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static inline void
register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
{
	if (c->ad_bytes == sizeof(unsigned long))
		*reg += inc;
	else
		*reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
}
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static inline void jmp_rel(struct decode_cache *c, int rel)
{
	register_address_increment(c, &c->eip, rel);
}
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static void set_seg_override(struct decode_cache *c, int seg)
{
	c->has_seg_override = true;
	c->seg_override = seg;
}

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static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
			      struct x86_emulate_ops *ops, int seg)
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{
	if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
		return 0;

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	return ops->get_cached_segment_base(seg, ctxt->vcpu);
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}

static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
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				       struct x86_emulate_ops *ops,
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				       struct decode_cache *c)
{
	if (!c->has_seg_override)
		return 0;

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	return seg_base(ctxt, ops, c->seg_override);
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}

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static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
			     struct x86_emulate_ops *ops)
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{
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	return seg_base(ctxt, ops, VCPU_SREG_ES);
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}

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static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
			     struct x86_emulate_ops *ops)
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{
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	return seg_base(ctxt, ops, VCPU_SREG_SS);
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}

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static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
				      u32 error, bool valid)
{
	ctxt->exception = vec;
	ctxt->error_code = error;
	ctxt->error_code_valid = valid;
}

static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
{
	emulate_exception(ctxt, GP_VECTOR, err, true);
}

static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
		       int err)
{
	ctxt->cr2 = addr;
	emulate_exception(ctxt, PF_VECTOR, err, true);
}

static void emulate_ud(struct x86_emulate_ctxt *ctxt)
{
	emulate_exception(ctxt, UD_VECTOR, 0, false);
}

static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
{
	emulate_exception(ctxt, TS_VECTOR, err, true);
}

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static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
			      struct x86_emulate_ops *ops,
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			      unsigned long eip, u8 *dest)
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{
	struct fetch_cache *fc = &ctxt->decode.fetch;
	int rc;
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	int size, cur_size;
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	if (eip == fc->end) {
		cur_size = fc->end - fc->start;
		size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
		rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
				size, ctxt->vcpu, NULL);
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		if (rc != X86EMUL_CONTINUE)
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			return rc;
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		fc->end += size;
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	}
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	*dest = fc->data[eip - fc->start];
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	return X86EMUL_CONTINUE;
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}

static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
			 struct x86_emulate_ops *ops,
			 unsigned long eip, void *dest, unsigned size)
{
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	int rc;
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	/* x86 instructions are limited to 15 bytes. */
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	if (eip + size - ctxt->eip > 15)
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		return X86EMUL_UNHANDLEABLE;
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	while (size--) {
		rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
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		if (rc != X86EMUL_CONTINUE)
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			return rc;
	}
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	return X86EMUL_CONTINUE;
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}

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/*
 * Given the 'reg' portion of a ModRM byte, and a register block, return a
 * pointer into the block that addresses the relevant register.
 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
 */
static void *decode_register(u8 modrm_reg, unsigned long *regs,
			     int highbyte_regs)
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509 510 511 512 513 514 515 516 517 518 519
{
	void *p;

	p = &regs[modrm_reg];
	if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
		p = (unsigned char *)&regs[modrm_reg & 3] + 1;
	return p;
}

static int read_descriptor(struct x86_emulate_ctxt *ctxt,
			   struct x86_emulate_ops *ops,
520
			   ulong addr,
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521 522 523 524 525 526 527
			   u16 *size, unsigned long *address, int op_bytes)
{
	int rc;

	if (op_bytes == 2)
		op_bytes = 3;
	*address = 0;
528
	rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL);
529
	if (rc != X86EMUL_CONTINUE)
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530
		return rc;
531
	rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL);
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532 533 534
	return rc;
}

535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569
static int test_cc(unsigned int condition, unsigned int flags)
{
	int rc = 0;

	switch ((condition & 15) >> 1) {
	case 0: /* o */
		rc |= (flags & EFLG_OF);
		break;
	case 1: /* b/c/nae */
		rc |= (flags & EFLG_CF);
		break;
	case 2: /* z/e */
		rc |= (flags & EFLG_ZF);
		break;
	case 3: /* be/na */
		rc |= (flags & (EFLG_CF|EFLG_ZF));
		break;
	case 4: /* s */
		rc |= (flags & EFLG_SF);
		break;
	case 5: /* p/pe */
		rc |= (flags & EFLG_PF);
		break;
	case 7: /* le/ng */
		rc |= (flags & EFLG_ZF);
		/* fall through */
	case 6: /* l/nge */
		rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
		break;
	}

	/* Odd condition identifiers (lsb == 1) have inverted sense. */
	return (!!rc ^ (condition & 1));
}

570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587
static void fetch_register_operand(struct operand *op)
{
	switch (op->bytes) {
	case 1:
		op->val = *(u8 *)op->addr.reg;
		break;
	case 2:
		op->val = *(u16 *)op->addr.reg;
		break;
	case 4:
		op->val = *(u32 *)op->addr.reg;
		break;
	case 8:
		op->val = *(u64 *)op->addr.reg;
		break;
	}
}

588 589 590 591
static void decode_register_operand(struct operand *op,
				    struct decode_cache *c,
				    int inhibit_bytereg)
{
592
	unsigned reg = c->modrm_reg;
593
	int highbyte_regs = c->rex_prefix == 0;
594 595 596

	if (!(c->d & ModRM))
		reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
597 598
	op->type = OP_REG;
	if ((c->d & ByteOp) && !inhibit_bytereg) {
599
		op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
600 601
		op->bytes = 1;
	} else {
602
		op->addr.reg = decode_register(reg, c->regs, 0);
603 604
		op->bytes = c->op_bytes;
	}
605
	fetch_register_operand(op);
606 607 608
	op->orig_val = op->val;
}

609
static int decode_modrm(struct x86_emulate_ctxt *ctxt,
610 611
			struct x86_emulate_ops *ops,
			struct operand *op)
612 613 614
{
	struct decode_cache *c = &ctxt->decode;
	u8 sib;
615
	int index_reg = 0, base_reg = 0, scale;
616
	int rc = X86EMUL_CONTINUE;
617
	ulong modrm_ea = 0;
618 619 620 621 622 623 624 625 626 627 628

	if (c->rex_prefix) {
		c->modrm_reg = (c->rex_prefix & 4) << 1;	/* REX.R */
		index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
		c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
	}

	c->modrm = insn_fetch(u8, 1, c->eip);
	c->modrm_mod |= (c->modrm & 0xc0) >> 6;
	c->modrm_reg |= (c->modrm & 0x38) >> 3;
	c->modrm_rm |= (c->modrm & 0x07);
629
	c->modrm_seg = VCPU_SREG_DS;
630 631

	if (c->modrm_mod == 3) {
632 633 634
		op->type = OP_REG;
		op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
		op->addr.reg = decode_register(c->modrm_rm,
635
					       c->regs, c->d & ByteOp);
636
		fetch_register_operand(op);
637 638 639
		return rc;
	}

640 641
	op->type = OP_MEM;

642 643 644 645 646 647 648 649 650 651
	if (c->ad_bytes == 2) {
		unsigned bx = c->regs[VCPU_REGS_RBX];
		unsigned bp = c->regs[VCPU_REGS_RBP];
		unsigned si = c->regs[VCPU_REGS_RSI];
		unsigned di = c->regs[VCPU_REGS_RDI];

		/* 16-bit ModR/M decode. */
		switch (c->modrm_mod) {
		case 0:
			if (c->modrm_rm == 6)
652
				modrm_ea += insn_fetch(u16, 2, c->eip);
653 654
			break;
		case 1:
655
			modrm_ea += insn_fetch(s8, 1, c->eip);
656 657
			break;
		case 2:
658
			modrm_ea += insn_fetch(u16, 2, c->eip);
659 660 661 662
			break;
		}
		switch (c->modrm_rm) {
		case 0:
663
			modrm_ea += bx + si;
664 665
			break;
		case 1:
666
			modrm_ea += bx + di;
667 668
			break;
		case 2:
669
			modrm_ea += bp + si;
670 671
			break;
		case 3:
672
			modrm_ea += bp + di;
673 674
			break;
		case 4:
675
			modrm_ea += si;
676 677
			break;
		case 5:
678
			modrm_ea += di;
679 680 681
			break;
		case 6:
			if (c->modrm_mod != 0)
682
				modrm_ea += bp;
683 684
			break;
		case 7:
685
			modrm_ea += bx;
686 687 688 689
			break;
		}
		if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
		    (c->modrm_rm == 6 && c->modrm_mod != 0))
690
			c->modrm_seg = VCPU_SREG_SS;
691
		modrm_ea = (u16)modrm_ea;
692 693
	} else {
		/* 32/64-bit ModR/M decode. */
694
		if ((c->modrm_rm & 7) == 4) {
695 696 697 698 699
			sib = insn_fetch(u8, 1, c->eip);
			index_reg |= (sib >> 3) & 7;
			base_reg |= sib & 7;
			scale = sib >> 6;

700
			if ((base_reg & 7) == 5 && c->modrm_mod == 0)
701
				modrm_ea += insn_fetch(s32, 4, c->eip);
702
			else
703
				modrm_ea += c->regs[base_reg];
704
			if (index_reg != 4)
705
				modrm_ea += c->regs[index_reg] << scale;
706 707
		} else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
			if (ctxt->mode == X86EMUL_MODE_PROT64)
708
				c->rip_relative = 1;
709
		} else
710
			modrm_ea += c->regs[c->modrm_rm];
711 712 713
		switch (c->modrm_mod) {
		case 0:
			if (c->modrm_rm == 5)
714
				modrm_ea += insn_fetch(s32, 4, c->eip);
715 716
			break;
		case 1:
717
			modrm_ea += insn_fetch(s8, 1, c->eip);
718 719
			break;
		case 2:
720
			modrm_ea += insn_fetch(s32, 4, c->eip);
721 722 723
			break;
		}
	}
724
	op->addr.mem = modrm_ea;
725 726 727 728 729
done:
	return rc;
}

static int decode_abs(struct x86_emulate_ctxt *ctxt,
730 731
		      struct x86_emulate_ops *ops,
		      struct operand *op)
732 733
{
	struct decode_cache *c = &ctxt->decode;
734
	int rc = X86EMUL_CONTINUE;
735

736
	op->type = OP_MEM;
737 738
	switch (c->ad_bytes) {
	case 2:
739
		op->addr.mem = insn_fetch(u16, 2, c->eip);
740 741
		break;
	case 4:
742
		op->addr.mem = insn_fetch(u32, 4, c->eip);
743 744
		break;
	case 8:
745
		op->addr.mem = insn_fetch(u64, 8, c->eip);
746 747 748 749 750 751
		break;
	}
done:
	return rc;
}

752 753 754 755
static void fetch_bit_operand(struct decode_cache *c)
{
	long sv, mask;

756
	if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
757 758 759 760 761 762 763 764 765
		mask = ~(c->dst.bytes * 8 - 1);

		if (c->src.bytes == 2)
			sv = (s16)c->src.val & (s16)mask;
		else if (c->src.bytes == 4)
			sv = (s32)c->src.val & (s32)mask;

		c->dst.addr.mem += (sv >> 3);
	}
766 767 768

	/* only subword offset */
	c->src.val &= (c->dst.bytes << 3) - 1;
769 770
}

771 772 773
static int read_emulated(struct x86_emulate_ctxt *ctxt,
			 struct x86_emulate_ops *ops,
			 unsigned long addr, void *dest, unsigned size)
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774
{
775 776 777
	int rc;
	struct read_cache *mc = &ctxt->decode.mem_read;
	u32 err;
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779 780 781 782 783
	while (size) {
		int n = min(size, 8u);
		size -= n;
		if (mc->pos < mc->end)
			goto read_cached;
784

785 786 787 788 789 790 791
		rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
					ctxt->vcpu);
		if (rc == X86EMUL_PROPAGATE_FAULT)
			emulate_pf(ctxt, addr, err);
		if (rc != X86EMUL_CONTINUE)
			return rc;
		mc->end += n;
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793 794 795 796 797
	read_cached:
		memcpy(dest, mc->data + mc->pos, n);
		mc->pos += n;
		dest += n;
		addr += n;
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798
	}
799 800
	return X86EMUL_CONTINUE;
}
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801

802 803 804 805 806 807
static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
			   struct x86_emulate_ops *ops,
			   unsigned int size, unsigned short port,
			   void *dest)
{
	struct read_cache *rc = &ctxt->decode.io_read;
808

809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824
	if (rc->pos == rc->end) { /* refill pio read ahead */
		struct decode_cache *c = &ctxt->decode;
		unsigned int in_page, n;
		unsigned int count = c->rep_prefix ?
			address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
		in_page = (ctxt->eflags & EFLG_DF) ?
			offset_in_page(c->regs[VCPU_REGS_RDI]) :
			PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
		n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
			count);
		if (n == 0)
			n = 1;
		rc->pos = rc->end = 0;
		if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
			return 0;
		rc->end = n * size;
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825 826
	}

827 828 829 830
	memcpy(dest, rc->data + rc->pos, size);
	rc->pos += size;
	return 1;
}
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831

832 833 834
static u32 desc_limit_scaled(struct desc_struct *desc)
{
	u32 limit = get_desc_limit(desc);
A
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835

836 837
	return desc->g ? (limit << 12) | 0xfff : limit;
}
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838

839 840 841 842 843 844 845 846 847
static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
				     struct x86_emulate_ops *ops,
				     u16 selector, struct desc_ptr *dt)
{
	if (selector & 1 << 2) {
		struct desc_struct desc;
		memset (dt, 0, sizeof *dt);
		if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
			return;
848

849 850 851 852 853
		dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
		dt->address = get_desc_base(&desc);
	} else
		ops->get_gdt(dt, ctxt->vcpu);
}
854

855 856 857 858 859 860 861 862 863 864
/* allowed just for 8 bytes segments */
static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   struct x86_emulate_ops *ops,
				   u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	int ret;
	u32 err;
	ulong addr;
865

866
	get_descriptor_table_ptr(ctxt, ops, selector, &dt);
867

868 869 870
	if (dt.size < index * 8 + 7) {
		emulate_gp(ctxt, selector & 0xfffc);
		return X86EMUL_PROPAGATE_FAULT;
871
	}
872 873 874 875
	addr = dt.address + index * 8;
	ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu,  &err);
	if (ret == X86EMUL_PROPAGATE_FAULT)
		emulate_pf(ctxt, addr, err);
876

877 878
       return ret;
}
879

880 881 882 883 884 885 886 887 888 889
/* allowed just for 8 bytes segments */
static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				    struct x86_emulate_ops *ops,
				    u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	u32 err;
	ulong addr;
	int ret;
A
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890

891
	get_descriptor_table_ptr(ctxt, ops, selector, &dt);
892

893 894 895 896
	if (dt.size < index * 8 + 7) {
		emulate_gp(ctxt, selector & 0xfffc);
		return X86EMUL_PROPAGATE_FAULT;
	}
A
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897

898 899 900 901
	addr = dt.address + index * 8;
	ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
	if (ret == X86EMUL_PROPAGATE_FAULT)
		emulate_pf(ctxt, addr, err);
902

903 904
	return ret;
}
905

906 907 908 909 910 911 912 913 914 915
static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   struct x86_emulate_ops *ops,
				   u16 selector, int seg)
{
	struct desc_struct seg_desc;
	u8 dpl, rpl, cpl;
	unsigned err_vec = GP_VECTOR;
	u32 err_code = 0;
	bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
	int ret;
916

917
	memset(&seg_desc, 0, sizeof seg_desc);
918

919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969
	if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
	    || ctxt->mode == X86EMUL_MODE_REAL) {
		/* set real mode segment descriptor */
		set_desc_base(&seg_desc, selector << 4);
		set_desc_limit(&seg_desc, 0xffff);
		seg_desc.type = 3;
		seg_desc.p = 1;
		seg_desc.s = 1;
		goto load;
	}

	/* NULL selector is not valid for TR, CS and SS */
	if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
	    && null_selector)
		goto exception;

	/* TR should be in GDT only */
	if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
		goto exception;

	if (null_selector) /* for NULL selector skip all following checks */
		goto load;

	ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
	if (ret != X86EMUL_CONTINUE)
		return ret;

	err_code = selector & 0xfffc;
	err_vec = GP_VECTOR;

	/* can't load system descriptor into segment selecor */
	if (seg <= VCPU_SREG_GS && !seg_desc.s)
		goto exception;

	if (!seg_desc.p) {
		err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
		goto exception;
	}

	rpl = selector & 3;
	dpl = seg_desc.dpl;
	cpl = ops->cpl(ctxt->vcpu);

	switch (seg) {
	case VCPU_SREG_SS:
		/*
		 * segment is not a writable data segment or segment
		 * selector's RPL != CPL or segment selector's RPL != CPL
		 */
		if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
			goto exception;
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970
		break;
971 972 973 974 975 976 977 978 979 980 981 982 983 984 985
	case VCPU_SREG_CS:
		if (!(seg_desc.type & 8))
			goto exception;

		if (seg_desc.type & 4) {
			/* conforming */
			if (dpl > cpl)
				goto exception;
		} else {
			/* nonconforming */
			if (rpl > cpl || dpl != cpl)
				goto exception;
		}
		/* CS(RPL) <- CPL */
		selector = (selector & 0xfffc) | cpl;
A
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986
		break;
987 988 989 990 991 992 993 994 995
	case VCPU_SREG_TR:
		if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
			goto exception;
		break;
	case VCPU_SREG_LDTR:
		if (seg_desc.s || seg_desc.type != 2)
			goto exception;
		break;
	default: /*  DS, ES, FS, or GS */
996
		/*
997 998 999
		 * segment is not a data or readable code segment or
		 * ((segment is a data or nonconforming code segment)
		 * and (both RPL and CPL > DPL))
1000
		 */
1001 1002 1003 1004
		if ((seg_desc.type & 0xa) == 0x8 ||
		    (((seg_desc.type & 0xc) != 0xc) &&
		     (rpl > dpl && cpl > dpl)))
			goto exception;
A
Avi Kivity 已提交
1005
		break;
1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023
	}

	if (seg_desc.s) {
		/* mark segment as accessed */
		seg_desc.type |= 1;
		ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
		if (ret != X86EMUL_CONTINUE)
			return ret;
	}
load:
	ops->set_segment_selector(selector, seg, ctxt->vcpu);
	ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
	return X86EMUL_CONTINUE;
exception:
	emulate_exception(ctxt, err_vec, err_code, true);
	return X86EMUL_PROPAGATE_FAULT;
}

1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042
static void write_register_operand(struct operand *op)
{
	/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
	switch (op->bytes) {
	case 1:
		*(u8 *)op->addr.reg = (u8)op->val;
		break;
	case 2:
		*(u16 *)op->addr.reg = (u16)op->val;
		break;
	case 4:
		*op->addr.reg = (u32)op->val;
		break;	/* 64b: zero-extend */
	case 8:
		*op->addr.reg = op->val;
		break;
	}
}

1043 1044 1045 1046 1047 1048 1049 1050 1051
static inline int writeback(struct x86_emulate_ctxt *ctxt,
			    struct x86_emulate_ops *ops)
{
	int rc;
	struct decode_cache *c = &ctxt->decode;
	u32 err;

	switch (c->dst.type) {
	case OP_REG:
1052
		write_register_operand(&c->dst);
A
Avi Kivity 已提交
1053
		break;
1054 1055 1056
	case OP_MEM:
		if (c->lock_prefix)
			rc = ops->cmpxchg_emulated(
1057
					c->dst.addr.mem,
1058 1059 1060 1061 1062
					&c->dst.orig_val,
					&c->dst.val,
					c->dst.bytes,
					&err,
					ctxt->vcpu);
1063
		else
1064
			rc = ops->write_emulated(
1065
					c->dst.addr.mem,
1066 1067 1068 1069 1070
					&c->dst.val,
					c->dst.bytes,
					&err,
					ctxt->vcpu);
		if (rc == X86EMUL_PROPAGATE_FAULT)
1071
			emulate_pf(ctxt, c->dst.addr.mem, err);
1072 1073
		if (rc != X86EMUL_CONTINUE)
			return rc;
1074
		break;
1075 1076
	case OP_NONE:
		/* no writeback */
1077
		break;
1078
	default:
1079
		break;
A
Avi Kivity 已提交
1080
	}
1081 1082
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1083

1084 1085 1086 1087
static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
				struct x86_emulate_ops *ops)
{
	struct decode_cache *c = &ctxt->decode;
1088

1089 1090 1091 1092
	c->dst.type  = OP_MEM;
	c->dst.bytes = c->op_bytes;
	c->dst.val = c->src.val;
	register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1093 1094
	c->dst.addr.mem = register_address(c, ss_base(ctxt, ops),
					   c->regs[VCPU_REGS_RSP]);
1095
}
1096

1097 1098 1099 1100 1101 1102
static int emulate_pop(struct x86_emulate_ctxt *ctxt,
		       struct x86_emulate_ops *ops,
		       void *dest, int len)
{
	struct decode_cache *c = &ctxt->decode;
	int rc;
1103

1104 1105 1106 1107 1108 1109 1110 1111
	rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
						       c->regs[VCPU_REGS_RSP]),
			   dest, len);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
	return rc;
1112 1113
}

1114 1115 1116
static int emulate_popf(struct x86_emulate_ctxt *ctxt,
		       struct x86_emulate_ops *ops,
		       void *dest, int len)
1117 1118
{
	int rc;
1119 1120 1121
	unsigned long val, change_mask;
	int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
	int cpl = ops->cpl(ctxt->vcpu);
1122

1123 1124 1125
	rc = emulate_pop(ctxt, ops, &val, len);
	if (rc != X86EMUL_CONTINUE)
		return rc;
1126

1127 1128
	change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
		| EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1129

1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148
	switch(ctxt->mode) {
	case X86EMUL_MODE_PROT64:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT16:
		if (cpl == 0)
			change_mask |= EFLG_IOPL;
		if (cpl <= iopl)
			change_mask |= EFLG_IF;
		break;
	case X86EMUL_MODE_VM86:
		if (iopl < 3) {
			emulate_gp(ctxt, 0);
			return X86EMUL_PROPAGATE_FAULT;
		}
		change_mask |= EFLG_IF;
		break;
	default: /* real mode */
		change_mask |= (EFLG_IOPL | EFLG_IF);
		break;
1149
	}
1150 1151 1152 1153 1154

	*(unsigned long *)dest =
		(ctxt->eflags & ~change_mask) | (val & change_mask);

	return rc;
1155 1156
}

1157 1158
static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
			      struct x86_emulate_ops *ops, int seg)
1159
{
1160
	struct decode_cache *c = &ctxt->decode;
1161

1162
	c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
1163

1164
	emulate_push(ctxt, ops);
1165 1166
}

1167 1168
static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
			     struct x86_emulate_ops *ops, int seg)
1169
{
1170 1171 1172
	struct decode_cache *c = &ctxt->decode;
	unsigned long selector;
	int rc;
1173

1174 1175 1176 1177 1178 1179
	rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
	return rc;
1180 1181
}

1182 1183
static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
			  struct x86_emulate_ops *ops)
1184
{
1185 1186 1187 1188
	struct decode_cache *c = &ctxt->decode;
	unsigned long old_esp = c->regs[VCPU_REGS_RSP];
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RAX;
1189

1190 1191 1192
	while (reg <= VCPU_REGS_RDI) {
		(reg == VCPU_REGS_RSP) ?
		(c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1193

1194
		emulate_push(ctxt, ops);
1195

1196 1197 1198
		rc = writeback(ctxt, ops);
		if (rc != X86EMUL_CONTINUE)
			return rc;
1199

1200
		++reg;
1201 1202
	}

1203 1204 1205 1206
	/* Disable writeback. */
	c->dst.type = OP_NONE;

	return rc;
1207 1208
}

1209 1210
static int emulate_popa(struct x86_emulate_ctxt *ctxt,
			struct x86_emulate_ops *ops)
1211
{
1212 1213 1214
	struct decode_cache *c = &ctxt->decode;
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RDI;
1215

1216 1217 1218 1219 1220 1221
	while (reg >= VCPU_REGS_RAX) {
		if (reg == VCPU_REGS_RSP) {
			register_address_increment(c, &c->regs[VCPU_REGS_RSP],
							c->op_bytes);
			--reg;
		}
1222

1223 1224 1225 1226
		rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
		if (rc != X86EMUL_CONTINUE)
			break;
		--reg;
1227
	}
1228
	return rc;
1229 1230
}

1231 1232 1233 1234
int emulate_int_real(struct x86_emulate_ctxt *ctxt,
			       struct x86_emulate_ops *ops, int irq)
{
	struct decode_cache *c = &ctxt->decode;
1235
	int rc;
1236 1237 1238 1239 1240 1241 1242 1243 1244
	struct desc_ptr dt;
	gva_t cs_addr;
	gva_t eip_addr;
	u16 cs, eip;
	u32 err;

	/* TODO: Add limit checks */
	c->src.val = ctxt->eflags;
	emulate_push(ctxt, ops);
1245 1246 1247
	rc = writeback(ctxt, ops);
	if (rc != X86EMUL_CONTINUE)
		return rc;
1248 1249 1250 1251 1252

	ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);

	c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
	emulate_push(ctxt, ops);
1253 1254 1255
	rc = writeback(ctxt, ops);
	if (rc != X86EMUL_CONTINUE)
		return rc;
1256 1257 1258

	c->src.val = c->eip;
	emulate_push(ctxt, ops);
1259 1260 1261 1262 1263
	rc = writeback(ctxt, ops);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	c->dst.type = OP_NONE;
1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302

	ops->get_idt(&dt, ctxt->vcpu);

	eip_addr = dt.address + (irq << 2);
	cs_addr = dt.address + (irq << 2) + 2;

	rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &err);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &err);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	c->eip = eip;

	return rc;
}

static int emulate_int(struct x86_emulate_ctxt *ctxt,
		       struct x86_emulate_ops *ops, int irq)
{
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
		return emulate_int_real(ctxt, ops, irq);
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
	default:
		/* Protected mode interrupts unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
	}
}

1303 1304
static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
			     struct x86_emulate_ops *ops)
1305
{
1306 1307 1308 1309 1310 1311 1312 1313 1314
	struct decode_cache *c = &ctxt->decode;
	int rc = X86EMUL_CONTINUE;
	unsigned long temp_eip = 0;
	unsigned long temp_eflags = 0;
	unsigned long cs = 0;
	unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
			     EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
			     EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
	unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1315

1316
	/* TODO: Add stack limit check */
1317

1318
	rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1319

1320 1321
	if (rc != X86EMUL_CONTINUE)
		return rc;
1322

1323 1324 1325 1326
	if (temp_eip & ~0xffff) {
		emulate_gp(ctxt, 0);
		return X86EMUL_PROPAGATE_FAULT;
	}
1327

1328
	rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1329

1330 1331
	if (rc != X86EMUL_CONTINUE)
		return rc;
1332

1333
	rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1334

1335 1336
	if (rc != X86EMUL_CONTINUE)
		return rc;
1337

1338
	rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1339

1340 1341
	if (rc != X86EMUL_CONTINUE)
		return rc;
1342

1343
	c->eip = temp_eip;
1344 1345


1346 1347 1348 1349 1350
	if (c->op_bytes == 4)
		ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
	else if (c->op_bytes == 2) {
		ctxt->eflags &= ~0xffff;
		ctxt->eflags |= temp_eflags;
1351
	}
1352 1353 1354 1355 1356

	ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
	ctxt->eflags |= EFLG_RESERVED_ONE_MASK;

	return rc;
1357 1358
}

1359 1360
static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
				    struct x86_emulate_ops* ops)
1361
{
1362 1363 1364 1365 1366 1367 1368
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
		return emulate_iret_real(ctxt, ops);
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
1369
	default:
1370 1371
		/* iret from protected mode unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
1372 1373 1374
	}
}

1375
static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1376
				struct x86_emulate_ops *ops)
1377 1378 1379
{
	struct decode_cache *c = &ctxt->decode;

1380
	return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1381 1382
}

1383
static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1384
{
1385
	struct decode_cache *c = &ctxt->decode;
1386 1387
	switch (c->modrm_reg) {
	case 0:	/* rol */
1388
		emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1389 1390
		break;
	case 1:	/* ror */
1391
		emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1392 1393
		break;
	case 2:	/* rcl */
1394
		emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1395 1396
		break;
	case 3:	/* rcr */
1397
		emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1398 1399 1400
		break;
	case 4:	/* sal/shl */
	case 6:	/* sal/shl */
1401
		emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1402 1403
		break;
	case 5:	/* shr */
1404
		emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1405 1406
		break;
	case 7:	/* sar */
1407
		emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1408 1409 1410 1411 1412
		break;
	}
}

static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1413
			       struct x86_emulate_ops *ops)
1414 1415
{
	struct decode_cache *c = &ctxt->decode;
1416 1417
	unsigned long *rax = &c->regs[VCPU_REGS_RAX];
	unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
1418 1419 1420

	switch (c->modrm_reg) {
	case 0 ... 1:	/* test */
1421
		emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1422 1423 1424 1425 1426
		break;
	case 2:	/* not */
		c->dst.val = ~c->dst.val;
		break;
	case 3:	/* neg */
1427
		emulate_1op("neg", c->dst, ctxt->eflags);
1428
		break;
1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440
	case 4: /* mul */
		emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
		break;
	case 5: /* imul */
		emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
		break;
	case 6: /* div */
		emulate_1op_rax_rdx("div", c->src, *rax, *rdx, ctxt->eflags);
		break;
	case 7: /* idiv */
		emulate_1op_rax_rdx("idiv", c->src, *rax, *rdx, ctxt->eflags);
		break;
1441
	default:
1442
		return X86EMUL_UNHANDLEABLE;
1443
	}
1444
	return X86EMUL_CONTINUE;
1445 1446 1447
}

static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1448
			       struct x86_emulate_ops *ops)
1449 1450 1451 1452 1453
{
	struct decode_cache *c = &ctxt->decode;

	switch (c->modrm_reg) {
	case 0:	/* inc */
1454
		emulate_1op("inc", c->dst, ctxt->eflags);
1455 1456
		break;
	case 1:	/* dec */
1457
		emulate_1op("dec", c->dst, ctxt->eflags);
1458
		break;
1459 1460 1461 1462 1463
	case 2: /* call near abs */ {
		long int old_eip;
		old_eip = c->eip;
		c->eip = c->src.val;
		c->src.val = old_eip;
1464
		emulate_push(ctxt, ops);
1465 1466
		break;
	}
1467
	case 4: /* jmp abs */
1468
		c->eip = c->src.val;
1469 1470
		break;
	case 6:	/* push */
1471
		emulate_push(ctxt, ops);
1472 1473
		break;
	}
1474
	return X86EMUL_CONTINUE;
1475 1476 1477
}

static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1478
			       struct x86_emulate_ops *ops)
1479 1480
{
	struct decode_cache *c = &ctxt->decode;
1481
	u64 old = c->dst.orig_val64;
1482 1483 1484 1485 1486

	if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
	    ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
		c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
		c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1487
		ctxt->eflags &= ~EFLG_ZF;
1488
	} else {
1489 1490
		c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
			(u32) c->regs[VCPU_REGS_RBX];
1491

1492
		ctxt->eflags |= EFLG_ZF;
1493
	}
1494
	return X86EMUL_CONTINUE;
1495 1496
}

1497 1498 1499 1500 1501 1502 1503 1504
static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
			   struct x86_emulate_ops *ops)
{
	struct decode_cache *c = &ctxt->decode;
	int rc;
	unsigned long cs;

	rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1505
	if (rc != X86EMUL_CONTINUE)
1506 1507 1508 1509
		return rc;
	if (c->op_bytes == 4)
		c->eip = (u32)c->eip;
	rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1510
	if (rc != X86EMUL_CONTINUE)
1511
		return rc;
1512
	rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1513 1514 1515
	return rc;
}

1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532
static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
			   struct x86_emulate_ops *ops, int seg)
{
	struct decode_cache *c = &ctxt->decode;
	unsigned short sel;
	int rc;

	memcpy(&sel, c->src.valptr + c->op_bytes, 2);

	rc = load_segment_descriptor(ctxt, ops, sel, seg);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	c->dst.val = c->src.val;
	return rc;
}

1533 1534
static inline void
setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1535 1536
			struct x86_emulate_ops *ops, struct desc_struct *cs,
			struct desc_struct *ss)
1537
{
1538 1539 1540
	memset(cs, 0, sizeof(struct desc_struct));
	ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
	memset(ss, 0, sizeof(struct desc_struct));
1541 1542

	cs->l = 0;		/* will be adjusted later */
1543
	set_desc_base(cs, 0);	/* flat segment */
1544
	cs->g = 1;		/* 4kb granularity */
1545
	set_desc_limit(cs, 0xfffff);	/* 4GB limit */
1546 1547 1548
	cs->type = 0x0b;	/* Read, Execute, Accessed */
	cs->s = 1;
	cs->dpl = 0;		/* will be adjusted later */
1549 1550
	cs->p = 1;
	cs->d = 1;
1551

1552 1553
	set_desc_base(ss, 0);	/* flat segment */
	set_desc_limit(ss, 0xfffff);	/* 4GB limit */
1554 1555 1556
	ss->g = 1;		/* 4kb granularity */
	ss->s = 1;
	ss->type = 0x03;	/* Read/Write, Accessed */
1557
	ss->d = 1;		/* 32bit stack segment */
1558
	ss->dpl = 0;
1559
	ss->p = 1;
1560 1561 1562
}

static int
1563
emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1564 1565
{
	struct decode_cache *c = &ctxt->decode;
1566
	struct desc_struct cs, ss;
1567
	u64 msr_data;
1568
	u16 cs_sel, ss_sel;
1569 1570

	/* syscall is not available in real mode */
1571 1572
	if (ctxt->mode == X86EMUL_MODE_REAL ||
	    ctxt->mode == X86EMUL_MODE_VM86) {
1573
		emulate_ud(ctxt);
1574 1575
		return X86EMUL_PROPAGATE_FAULT;
	}
1576

1577
	setup_syscalls_segments(ctxt, ops, &cs, &ss);
1578

1579
	ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1580
	msr_data >>= 32;
1581 1582
	cs_sel = (u16)(msr_data & 0xfffc);
	ss_sel = (u16)(msr_data + 8);
1583 1584

	if (is_long_mode(ctxt->vcpu)) {
1585
		cs.d = 0;
1586 1587
		cs.l = 1;
	}
1588 1589 1590 1591
	ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
	ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
	ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
	ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1592 1593 1594 1595 1596 1597

	c->regs[VCPU_REGS_RCX] = c->eip;
	if (is_long_mode(ctxt->vcpu)) {
#ifdef CONFIG_X86_64
		c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;

1598 1599 1600
		ops->get_msr(ctxt->vcpu,
			     ctxt->mode == X86EMUL_MODE_PROT64 ?
			     MSR_LSTAR : MSR_CSTAR, &msr_data);
1601 1602
		c->eip = msr_data;

1603
		ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1604 1605 1606 1607
		ctxt->eflags &= ~(msr_data | EFLG_RF);
#endif
	} else {
		/* legacy mode */
1608
		ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1609 1610 1611 1612 1613
		c->eip = (u32)msr_data;

		ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
	}

1614
	return X86EMUL_CONTINUE;
1615 1616
}

1617
static int
1618
emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1619 1620
{
	struct decode_cache *c = &ctxt->decode;
1621
	struct desc_struct cs, ss;
1622
	u64 msr_data;
1623
	u16 cs_sel, ss_sel;
1624

1625 1626
	/* inject #GP if in real mode */
	if (ctxt->mode == X86EMUL_MODE_REAL) {
1627
		emulate_gp(ctxt, 0);
1628
		return X86EMUL_PROPAGATE_FAULT;
1629 1630 1631 1632 1633
	}

	/* XXX sysenter/sysexit have not been tested in 64bit mode.
	* Therefore, we inject an #UD.
	*/
1634
	if (ctxt->mode == X86EMUL_MODE_PROT64) {
1635
		emulate_ud(ctxt);
1636 1637
		return X86EMUL_PROPAGATE_FAULT;
	}
1638

1639
	setup_syscalls_segments(ctxt, ops, &cs, &ss);
1640

1641
	ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1642 1643 1644
	switch (ctxt->mode) {
	case X86EMUL_MODE_PROT32:
		if ((msr_data & 0xfffc) == 0x0) {
1645
			emulate_gp(ctxt, 0);
1646
			return X86EMUL_PROPAGATE_FAULT;
1647 1648 1649 1650
		}
		break;
	case X86EMUL_MODE_PROT64:
		if (msr_data == 0x0) {
1651
			emulate_gp(ctxt, 0);
1652
			return X86EMUL_PROPAGATE_FAULT;
1653 1654 1655 1656 1657
		}
		break;
	}

	ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1658 1659 1660 1661
	cs_sel = (u16)msr_data;
	cs_sel &= ~SELECTOR_RPL_MASK;
	ss_sel = cs_sel + 8;
	ss_sel &= ~SELECTOR_RPL_MASK;
1662 1663
	if (ctxt->mode == X86EMUL_MODE_PROT64
		|| is_long_mode(ctxt->vcpu)) {
1664
		cs.d = 0;
1665 1666 1667
		cs.l = 1;
	}

1668 1669 1670 1671
	ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
	ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
	ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
	ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1672

1673
	ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1674 1675
	c->eip = msr_data;

1676
	ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1677 1678
	c->regs[VCPU_REGS_RSP] = msr_data;

1679
	return X86EMUL_CONTINUE;
1680 1681
}

1682
static int
1683
emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1684 1685
{
	struct decode_cache *c = &ctxt->decode;
1686
	struct desc_struct cs, ss;
1687 1688
	u64 msr_data;
	int usermode;
1689
	u16 cs_sel, ss_sel;
1690

1691 1692 1693
	/* inject #GP if in real mode or Virtual 8086 mode */
	if (ctxt->mode == X86EMUL_MODE_REAL ||
	    ctxt->mode == X86EMUL_MODE_VM86) {
1694
		emulate_gp(ctxt, 0);
1695
		return X86EMUL_PROPAGATE_FAULT;
1696 1697
	}

1698
	setup_syscalls_segments(ctxt, ops, &cs, &ss);
1699 1700 1701 1702 1703 1704 1705 1706

	if ((c->rex_prefix & 0x8) != 0x0)
		usermode = X86EMUL_MODE_PROT64;
	else
		usermode = X86EMUL_MODE_PROT32;

	cs.dpl = 3;
	ss.dpl = 3;
1707
	ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1708 1709
	switch (usermode) {
	case X86EMUL_MODE_PROT32:
1710
		cs_sel = (u16)(msr_data + 16);
1711
		if ((msr_data & 0xfffc) == 0x0) {
1712
			emulate_gp(ctxt, 0);
1713
			return X86EMUL_PROPAGATE_FAULT;
1714
		}
1715
		ss_sel = (u16)(msr_data + 24);
1716 1717
		break;
	case X86EMUL_MODE_PROT64:
1718
		cs_sel = (u16)(msr_data + 32);
1719
		if (msr_data == 0x0) {
1720
			emulate_gp(ctxt, 0);
1721
			return X86EMUL_PROPAGATE_FAULT;
1722
		}
1723 1724
		ss_sel = cs_sel + 8;
		cs.d = 0;
1725 1726 1727
		cs.l = 1;
		break;
	}
1728 1729
	cs_sel |= SELECTOR_RPL_MASK;
	ss_sel |= SELECTOR_RPL_MASK;
1730

1731 1732 1733 1734
	ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
	ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
	ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
	ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1735

1736 1737
	c->eip = c->regs[VCPU_REGS_RDX];
	c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
1738

1739
	return X86EMUL_CONTINUE;
1740 1741
}

1742 1743
static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
			      struct x86_emulate_ops *ops)
1744 1745 1746 1747 1748 1749 1750
{
	int iopl;
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return false;
	if (ctxt->mode == X86EMUL_MODE_VM86)
		return true;
	iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1751
	return ops->cpl(ctxt->vcpu) > iopl;
1752 1753 1754 1755 1756 1757
}

static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
					    struct x86_emulate_ops *ops,
					    u16 port, u16 len)
{
1758
	struct desc_struct tr_seg;
1759 1760 1761 1762 1763
	int r;
	u16 io_bitmap_ptr;
	u8 perm, bit_idx = port & 0x7;
	unsigned mask = (1 << len) - 1;

1764 1765
	ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
	if (!tr_seg.p)
1766
		return false;
1767
	if (desc_limit_scaled(&tr_seg) < 103)
1768
		return false;
1769 1770
	r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
			  ctxt->vcpu, NULL);
1771 1772
	if (r != X86EMUL_CONTINUE)
		return false;
1773
	if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
1774
		return false;
1775 1776
	r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
			  &perm, 1, ctxt->vcpu, NULL);
1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787
	if (r != X86EMUL_CONTINUE)
		return false;
	if ((perm >> bit_idx) & mask)
		return false;
	return true;
}

static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
				 struct x86_emulate_ops *ops,
				 u16 port, u16 len)
{
1788 1789 1790
	if (ctxt->perm_ok)
		return true;

1791
	if (emulator_bad_iopl(ctxt, ops))
1792 1793
		if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
			return false;
1794 1795 1796

	ctxt->perm_ok = true;

1797 1798 1799
	return true;
}

1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887
static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
				struct x86_emulate_ops *ops,
				struct tss_segment_16 *tss)
{
	struct decode_cache *c = &ctxt->decode;

	tss->ip = c->eip;
	tss->flag = ctxt->eflags;
	tss->ax = c->regs[VCPU_REGS_RAX];
	tss->cx = c->regs[VCPU_REGS_RCX];
	tss->dx = c->regs[VCPU_REGS_RDX];
	tss->bx = c->regs[VCPU_REGS_RBX];
	tss->sp = c->regs[VCPU_REGS_RSP];
	tss->bp = c->regs[VCPU_REGS_RBP];
	tss->si = c->regs[VCPU_REGS_RSI];
	tss->di = c->regs[VCPU_REGS_RDI];

	tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
	tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
	tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
	tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
	tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
}

static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
				 struct x86_emulate_ops *ops,
				 struct tss_segment_16 *tss)
{
	struct decode_cache *c = &ctxt->decode;
	int ret;

	c->eip = tss->ip;
	ctxt->eflags = tss->flag | 2;
	c->regs[VCPU_REGS_RAX] = tss->ax;
	c->regs[VCPU_REGS_RCX] = tss->cx;
	c->regs[VCPU_REGS_RDX] = tss->dx;
	c->regs[VCPU_REGS_RBX] = tss->bx;
	c->regs[VCPU_REGS_RSP] = tss->sp;
	c->regs[VCPU_REGS_RBP] = tss->bp;
	c->regs[VCPU_REGS_RSI] = tss->si;
	c->regs[VCPU_REGS_RDI] = tss->di;

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
	ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
	ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
	ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
	ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
	ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);

	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
	ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_16(struct x86_emulate_ctxt *ctxt,
			  struct x86_emulate_ops *ops,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
	struct tss_segment_16 tss_seg;
	int ret;
	u32 err, new_tss_base = get_desc_base(new_desc);

	ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
			    &err);
	if (ret == X86EMUL_PROPAGATE_FAULT) {
		/* FIXME: need to provide precise fault address */
1888
		emulate_pf(ctxt, old_tss_base, err);
1889 1890 1891 1892 1893 1894 1895 1896 1897
		return ret;
	}

	save_state_to_tss16(ctxt, ops, &tss_seg);

	ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
			     &err);
	if (ret == X86EMUL_PROPAGATE_FAULT) {
		/* FIXME: need to provide precise fault address */
1898
		emulate_pf(ctxt, old_tss_base, err);
1899 1900 1901 1902 1903 1904 1905
		return ret;
	}

	ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
			    &err);
	if (ret == X86EMUL_PROPAGATE_FAULT) {
		/* FIXME: need to provide precise fault address */
1906
		emulate_pf(ctxt, new_tss_base, err);
1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918
		return ret;
	}

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

		ret = ops->write_std(new_tss_base,
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
				     ctxt->vcpu, &err);
		if (ret == X86EMUL_PROPAGATE_FAULT) {
			/* FIXME: need to provide precise fault address */
1919
			emulate_pf(ctxt, new_tss_base, err);
1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960
			return ret;
		}
	}

	return load_state_from_tss16(ctxt, ops, &tss_seg);
}

static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
				struct x86_emulate_ops *ops,
				struct tss_segment_32 *tss)
{
	struct decode_cache *c = &ctxt->decode;

	tss->cr3 = ops->get_cr(3, ctxt->vcpu);
	tss->eip = c->eip;
	tss->eflags = ctxt->eflags;
	tss->eax = c->regs[VCPU_REGS_RAX];
	tss->ecx = c->regs[VCPU_REGS_RCX];
	tss->edx = c->regs[VCPU_REGS_RDX];
	tss->ebx = c->regs[VCPU_REGS_RBX];
	tss->esp = c->regs[VCPU_REGS_RSP];
	tss->ebp = c->regs[VCPU_REGS_RBP];
	tss->esi = c->regs[VCPU_REGS_RSI];
	tss->edi = c->regs[VCPU_REGS_RDI];

	tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
	tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
	tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
	tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
	tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
	tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
	tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
}

static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
				 struct x86_emulate_ops *ops,
				 struct tss_segment_32 *tss)
{
	struct decode_cache *c = &ctxt->decode;
	int ret;

1961
	if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
1962
		emulate_gp(ctxt, 0);
1963 1964
		return X86EMUL_PROPAGATE_FAULT;
	}
1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029
	c->eip = tss->eip;
	ctxt->eflags = tss->eflags | 2;
	c->regs[VCPU_REGS_RAX] = tss->eax;
	c->regs[VCPU_REGS_RCX] = tss->ecx;
	c->regs[VCPU_REGS_RDX] = tss->edx;
	c->regs[VCPU_REGS_RBX] = tss->ebx;
	c->regs[VCPU_REGS_RSP] = tss->esp;
	c->regs[VCPU_REGS_RBP] = tss->ebp;
	c->regs[VCPU_REGS_RSI] = tss->esi;
	c->regs[VCPU_REGS_RDI] = tss->edi;

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
	ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
	ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
	ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
	ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
	ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
	ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
	ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);

	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
	ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_32(struct x86_emulate_ctxt *ctxt,
			  struct x86_emulate_ops *ops,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
	struct tss_segment_32 tss_seg;
	int ret;
	u32 err, new_tss_base = get_desc_base(new_desc);

	ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
			    &err);
	if (ret == X86EMUL_PROPAGATE_FAULT) {
		/* FIXME: need to provide precise fault address */
2030
		emulate_pf(ctxt, old_tss_base, err);
2031 2032 2033 2034 2035 2036 2037 2038 2039
		return ret;
	}

	save_state_to_tss32(ctxt, ops, &tss_seg);

	ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
			     &err);
	if (ret == X86EMUL_PROPAGATE_FAULT) {
		/* FIXME: need to provide precise fault address */
2040
		emulate_pf(ctxt, old_tss_base, err);
2041 2042 2043 2044 2045 2046 2047
		return ret;
	}

	ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
			    &err);
	if (ret == X86EMUL_PROPAGATE_FAULT) {
		/* FIXME: need to provide precise fault address */
2048
		emulate_pf(ctxt, new_tss_base, err);
2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060
		return ret;
	}

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

		ret = ops->write_std(new_tss_base,
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
				     ctxt->vcpu, &err);
		if (ret == X86EMUL_PROPAGATE_FAULT) {
			/* FIXME: need to provide precise fault address */
2061
			emulate_pf(ctxt, new_tss_base, err);
2062 2063 2064 2065 2066 2067 2068 2069
			return ret;
		}
	}

	return load_state_from_tss32(ctxt, ops, &tss_seg);
}

static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2070 2071 2072
				   struct x86_emulate_ops *ops,
				   u16 tss_selector, int reason,
				   bool has_error_code, u32 error_code)
2073 2074 2075 2076 2077
{
	struct desc_struct curr_tss_desc, next_tss_desc;
	int ret;
	u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
	ulong old_tss_base =
2078
		ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
2079
	u32 desc_limit;
2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094

	/* FIXME: old_tss_base == ~0 ? */

	ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
	if (ret != X86EMUL_CONTINUE)
		return ret;

	/* FIXME: check that next_tss_desc is tss */

	if (reason != TASK_SWITCH_IRET) {
		if ((tss_selector & 3) > next_tss_desc.dpl ||
		    ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
2095
			emulate_gp(ctxt, 0);
2096 2097 2098 2099
			return X86EMUL_PROPAGATE_FAULT;
		}
	}

2100 2101 2102 2103
	desc_limit = desc_limit_scaled(&next_tss_desc);
	if (!next_tss_desc.p ||
	    ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
	     desc_limit < 0x2b)) {
2104
		emulate_ts(ctxt, tss_selector & 0xfffc);
2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127
		return X86EMUL_PROPAGATE_FAULT;
	}

	if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
		curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
		write_segment_descriptor(ctxt, ops, old_tss_sel,
					 &curr_tss_desc);
	}

	if (reason == TASK_SWITCH_IRET)
		ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;

	/* set back link to prev task only if NT bit is set in eflags
	   note that old_tss_sel is not used afetr this point */
	if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
		old_tss_sel = 0xffff;

	if (next_tss_desc.type & 8)
		ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
				     old_tss_base, &next_tss_desc);
	else
		ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
				     old_tss_base, &next_tss_desc);
2128 2129
	if (ret != X86EMUL_CONTINUE)
		return ret;
2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143

	if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
		ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;

	if (reason != TASK_SWITCH_IRET) {
		next_tss_desc.type |= (1 << 1); /* set busy flag */
		write_segment_descriptor(ctxt, ops, tss_selector,
					 &next_tss_desc);
	}

	ops->set_cr(0,  ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
	ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
	ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);

2144 2145 2146 2147 2148 2149
	if (has_error_code) {
		struct decode_cache *c = &ctxt->decode;

		c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
		c->lock_prefix = 0;
		c->src.val = (unsigned long) error_code;
2150
		emulate_push(ctxt, ops);
2151 2152
	}

2153 2154 2155 2156
	return ret;
}

int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2157 2158
			 u16 tss_selector, int reason,
			 bool has_error_code, u32 error_code)
2159
{
2160
	struct x86_emulate_ops *ops = ctxt->ops;
2161 2162 2163 2164
	struct decode_cache *c = &ctxt->decode;
	int rc;

	c->eip = ctxt->eip;
2165
	c->dst.type = OP_NONE;
2166

2167 2168
	rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
				     has_error_code, error_code);
2169 2170

	if (rc == X86EMUL_CONTINUE) {
2171
		rc = writeback(ctxt, ops);
2172 2173
		if (rc == X86EMUL_CONTINUE)
			ctxt->eip = c->eip;
2174 2175
	}

2176
	return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2177 2178
}

2179
static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
2180
			    int reg, struct operand *op)
2181 2182 2183 2184
{
	struct decode_cache *c = &ctxt->decode;
	int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;

2185
	register_address_increment(c, &c->regs[reg], df * op->bytes);
2186
	op->addr.mem = register_address(c,  base, c->regs[reg]);
2187 2188
}

2189 2190 2191 2192 2193 2194
static int em_push(struct x86_emulate_ctxt *ctxt)
{
	emulate_push(ctxt, ctxt->ops);
	return X86EMUL_CONTINUE;
}

2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233
static int em_das(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	u8 al, old_al;
	bool af, cf, old_cf;

	cf = ctxt->eflags & X86_EFLAGS_CF;
	al = c->dst.val;

	old_al = al;
	old_cf = cf;
	cf = false;
	af = ctxt->eflags & X86_EFLAGS_AF;
	if ((al & 0x0f) > 9 || af) {
		al -= 6;
		cf = old_cf | (al >= 250);
		af = true;
	} else {
		af = false;
	}
	if (old_al > 0x99 || old_cf) {
		al -= 0x60;
		cf = true;
	}

	c->dst.val = al;
	/* Set PF, ZF, SF */
	c->src.type = OP_IMM;
	c->src.val = 0;
	c->src.bytes = 1;
	emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
	ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
	if (cf)
		ctxt->eflags |= X86_EFLAGS_CF;
	if (af)
		ctxt->eflags |= X86_EFLAGS_AF;
	return X86EMUL_CONTINUE;
}

2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267
static int em_call_far(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	u16 sel, old_cs;
	ulong old_eip;
	int rc;

	old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
	old_eip = c->eip;

	memcpy(&sel, c->src.valptr + c->op_bytes, 2);
	if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
		return X86EMUL_CONTINUE;

	c->eip = 0;
	memcpy(&c->eip, c->src.valptr, c->op_bytes);

	c->src.val = old_cs;
	emulate_push(ctxt, ctxt->ops);
	rc = writeback(ctxt, ctxt->ops);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	c->src.val = old_eip;
	emulate_push(ctxt, ctxt->ops);
	rc = writeback(ctxt, ctxt->ops);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	c->dst.type = OP_NONE;

	return X86EMUL_CONTINUE;
}

2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282
static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	int rc;

	c->dst.type = OP_REG;
	c->dst.addr.reg = &c->eip;
	c->dst.bytes = c->op_bytes;
	rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
	return X86EMUL_CONTINUE;
}

2283
static int em_imul(struct x86_emulate_ctxt *ctxt)
2284 2285 2286 2287 2288 2289 2290
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

2291 2292 2293 2294 2295 2296 2297 2298
static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->dst.val = c->src2.val;
	return em_imul(ctxt);
}

2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310
static int em_cwd(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->dst.type = OP_REG;
	c->dst.bytes = c->src.bytes;
	c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
	c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);

	return X86EMUL_CONTINUE;
}

2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326
static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
{
	unsigned cpl = ctxt->ops->cpl(ctxt->vcpu);
	struct decode_cache *c = &ctxt->decode;
	u64 tsc = 0;

	if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD)) {
		emulate_gp(ctxt, 0);
		return X86EMUL_PROPAGATE_FAULT;
	}
	ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
	c->regs[VCPU_REGS_RAX] = (u32)tsc;
	c->regs[VCPU_REGS_RDX] = tsc >> 32;
	return X86EMUL_CONTINUE;
}

2327 2328 2329 2330 2331 2332
#define D(_y) { .flags = (_y) }
#define N    D(0)
#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }

2333 2334 2335
#define D2bv(_f)      D((_f) | ByteOp), D(_f)
#define I2bv(_f, _e)  I((_f) | ByteOp, _e), I(_f, _e)

2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346
static struct opcode group1[] = {
	X7(D(Lock)), N
};

static struct opcode group1A[] = {
	D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
};

static struct opcode group3[] = {
	D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
	D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2347
	X4(D(SrcMem | ModRM)),
2348 2349 2350 2351 2352 2353 2354 2355 2356
};

static struct opcode group4[] = {
	D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
	N, N, N, N, N, N,
};

static struct opcode group5[] = {
	D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2357 2358
	D(SrcMem | ModRM | Stack),
	I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
2359 2360 2361 2362 2363 2364 2365
	D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
	D(SrcMem | ModRM | Stack), N,
};

static struct group_dual group7 = { {
	N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
	D(SrcNone | ModRM | DstMem | Mov), N,
2366 2367
	D(SrcMem16 | ModRM | Mov | Priv),
	D(SrcMem | ModRM | ByteOp | Priv | NoAccess),
2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387
}, {
	D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
	D(SrcNone | ModRM | DstMem | Mov), N,
	D(SrcMem16 | ModRM | Mov | Priv), N,
} };

static struct opcode group8[] = {
	N, N, N, N,
	D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
	D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
};

static struct group_dual group9 = { {
	N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
}, {
	N, N, N, N, N, N, N, N,
} };

static struct opcode opcode_table[256] = {
	/* 0x00 - 0x07 */
2388 2389
	D2bv(DstMem | SrcReg | ModRM | Lock), D2bv(DstReg | SrcMem | ModRM),
	D2bv(DstAcc | SrcImm),
2390 2391
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x08 - 0x0F */
2392 2393
	D2bv(DstMem | SrcReg | ModRM | Lock), D2bv(DstReg | SrcMem | ModRM),
	D2bv(DstAcc | SrcImm),
2394 2395
	D(ImplicitOps | Stack | No64), N,
	/* 0x10 - 0x17 */
2396 2397
	D2bv(DstMem | SrcReg | ModRM | Lock), D2bv(DstReg | SrcMem | ModRM),
	D2bv(DstAcc | SrcImm),
2398 2399
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x18 - 0x1F */
2400 2401
	D2bv(DstMem | SrcReg | ModRM | Lock), D2bv(DstReg | SrcMem | ModRM),
	D2bv(DstAcc | SrcImm),
2402 2403
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x20 - 0x27 */
2404 2405
	D2bv(DstMem | SrcReg | ModRM | Lock), D2bv(DstReg | SrcMem | ModRM),
	D2bv(DstAcc | SrcImm), N, N,
2406
	/* 0x28 - 0x2F */
2407 2408
	D2bv(DstMem | SrcReg | ModRM | Lock), D2bv(DstReg | SrcMem | ModRM),
	D2bv(DstAcc | SrcImm),
2409
	N, I(ByteOp | DstAcc | No64, em_das),
2410
	/* 0x30 - 0x37 */
2411 2412
	D2bv(DstMem | SrcReg | ModRM | Lock), D2bv(DstReg | SrcMem | ModRM),
	D2bv(DstAcc | SrcImm), N, N,
2413
	/* 0x38 - 0x3F */
2414 2415
	D2bv(DstMem | SrcReg | ModRM), D2bv(DstReg | SrcMem | ModRM),
	D2bv(DstAcc | SrcImm),
2416 2417 2418 2419
	N, N,
	/* 0x40 - 0x4F */
	X16(D(DstReg)),
	/* 0x50 - 0x57 */
2420
	X8(I(SrcReg | Stack, em_push)),
2421 2422 2423 2424 2425 2426 2427
	/* 0x58 - 0x5F */
	X8(D(DstReg | Stack)),
	/* 0x60 - 0x67 */
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
	N, N, N, N,
	/* 0x68 - 0x6F */
2428 2429
	I(SrcImm | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
2430 2431
	I(SrcImmByte | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445
	D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
	D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
	/* 0x70 - 0x7F */
	X16(D(SrcImmByte)),
	/* 0x80 - 0x87 */
	G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
	G(DstMem | SrcImm | ModRM | Group, group1),
	G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
	G(DstMem | SrcImmByte | ModRM | Group, group1),
	D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
	D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
	/* 0x88 - 0x8F */
	D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
	D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
2446
	D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
2447 2448
	D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
	/* 0x90 - 0x97 */
2449
	X8(D(SrcAcc | DstReg)),
2450
	/* 0x98 - 0x9F */
2451
	D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
2452
	I(SrcImmFAddr | No64, em_call_far), N,
2453 2454 2455 2456 2457 2458 2459
	D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
	/* 0xA0 - 0xA7 */
	D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
	D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
	D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
	D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
	/* 0xA8 - 0xAF */
2460 2461
	D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm),
	D(ByteOp | SrcAcc | DstDI | Mov | String), D(SrcAcc | DstDI | Mov | String),
2462
	D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
2463
	D(ByteOp | SrcAcc | DstDI | String), D(SrcAcc | DstDI | String),
2464 2465 2466 2467 2468 2469
	/* 0xB0 - 0xB7 */
	X8(D(ByteOp | DstReg | SrcImm | Mov)),
	/* 0xB8 - 0xBF */
	X8(D(DstReg | SrcImm | Mov)),
	/* 0xC0 - 0xC7 */
	D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
2470 2471
	I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
	D(ImplicitOps | Stack),
2472
	D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
2473 2474 2475 2476 2477
	D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
	/* 0xC8 - 0xCF */
	N, N, N, D(ImplicitOps | Stack),
	D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
	/* 0xD0 - 0xD7 */
2478
	D(ByteOp | DstMem | SrcOne | ModRM), D(DstMem | SrcOne | ModRM),
A
Avi Kivity 已提交
2479
	D(ByteOp | DstMem | ModRM), D(DstMem | ModRM),
2480 2481 2482 2483
	N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
2484
	X4(D(SrcImmByte)),
2485
	D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2486
	D(ByteOp | SrcAcc | DstImmUByte), D(SrcAcc | DstImmUByte),
2487 2488 2489 2490
	/* 0xE8 - 0xEF */
	D(SrcImm | Stack), D(SrcImm | ImplicitOps),
	D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
	D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2491
	D(ByteOp | SrcAcc | ImplicitOps), D(SrcAcc | ImplicitOps),
2492 2493 2494 2495
	/* 0xF0 - 0xF7 */
	N, N, N, N,
	D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
	/* 0xF8 - 0xFF */
2496
	D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508
	D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
};

static struct opcode twobyte_table[256] = {
	/* 0x00 - 0x0F */
	N, GD(0, &group7), N, N,
	N, D(ImplicitOps), D(ImplicitOps | Priv), N,
	D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
	N, D(ImplicitOps | ModRM), N, N,
	/* 0x10 - 0x1F */
	N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
	/* 0x20 - 0x2F */
2509 2510
	D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
	D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
2511 2512 2513
	N, N, N, N,
	N, N, N, N, N, N, N, N,
	/* 0x30 - 0x3F */
2514 2515
	D(ImplicitOps | Priv), I(ImplicitOps, em_rdtsc),
	D(ImplicitOps | Priv), N,
2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528
	D(ImplicitOps), D(ImplicitOps | Priv), N, N,
	N, N, N, N, N, N, N, N,
	/* 0x40 - 0x4F */
	X16(D(DstReg | SrcMem | ModRM | Mov)),
	/* 0x50 - 0x5F */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0x60 - 0x6F */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0x70 - 0x7F */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0x80 - 0x8F */
	X16(D(SrcImm)),
	/* 0x90 - 0x9F */
2529
	X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
2530 2531 2532 2533 2534 2535 2536 2537 2538 2539
	/* 0xA0 - 0xA7 */
	D(ImplicitOps | Stack), D(ImplicitOps | Stack),
	N, D(DstMem | SrcReg | ModRM | BitOp),
	D(DstMem | SrcReg | Src2ImmByte | ModRM),
	D(DstMem | SrcReg | Src2CL | ModRM), N, N,
	/* 0xA8 - 0xAF */
	D(ImplicitOps | Stack), D(ImplicitOps | Stack),
	N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
	D(DstMem | SrcReg | Src2ImmByte | ModRM),
	D(DstMem | SrcReg | Src2CL | ModRM),
2540
	D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
2541 2542
	/* 0xB0 - 0xB7 */
	D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2543 2544 2545
	D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
	D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
	D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
2546 2547
	/* 0xB8 - 0xBF */
	N, N,
2548
	G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2549 2550
	D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
	D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
2551
	/* 0xC0 - 0xCF */
2552 2553
	D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
	N, D(DstMem | SrcReg | ModRM | Mov),
2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569
	N, N, N, GD(0, &group9),
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xDF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xEF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xFF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
};

#undef D
#undef N
#undef G
#undef GD
#undef I

2570 2571 2572
#undef D2bv
#undef I2bv

2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621
static unsigned imm_size(struct decode_cache *c)
{
	unsigned size;

	size = (c->d & ByteOp) ? 1 : c->op_bytes;
	if (size == 8)
		size = 4;
	return size;
}

static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
		      unsigned size, bool sign_extension)
{
	struct decode_cache *c = &ctxt->decode;
	struct x86_emulate_ops *ops = ctxt->ops;
	int rc = X86EMUL_CONTINUE;

	op->type = OP_IMM;
	op->bytes = size;
	op->addr.mem = c->eip;
	/* NB. Immediates are sign-extended as necessary. */
	switch (op->bytes) {
	case 1:
		op->val = insn_fetch(s8, 1, c->eip);
		break;
	case 2:
		op->val = insn_fetch(s16, 2, c->eip);
		break;
	case 4:
		op->val = insn_fetch(s32, 4, c->eip);
		break;
	}
	if (!sign_extension) {
		switch (op->bytes) {
		case 1:
			op->val &= 0xff;
			break;
		case 2:
			op->val &= 0xffff;
			break;
		case 4:
			op->val &= 0xffffffff;
			break;
		}
	}
done:
	return rc;
}

2622 2623 2624 2625 2626 2627 2628 2629 2630
int
x86_decode_insn(struct x86_emulate_ctxt *ctxt)
{
	struct x86_emulate_ops *ops = ctxt->ops;
	struct decode_cache *c = &ctxt->decode;
	int rc = X86EMUL_CONTINUE;
	int mode = ctxt->mode;
	int def_op_bytes, def_ad_bytes, dual, goffset;
	struct opcode opcode, *g_mod012, *g_mod3;
2631
	struct operand memop = { .type = OP_NONE };
2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709

	c->eip = ctxt->eip;
	c->fetch.start = c->fetch.end = c->eip;
	ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);

	switch (mode) {
	case X86EMUL_MODE_REAL:
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
		def_op_bytes = def_ad_bytes = 2;
		break;
	case X86EMUL_MODE_PROT32:
		def_op_bytes = def_ad_bytes = 4;
		break;
#ifdef CONFIG_X86_64
	case X86EMUL_MODE_PROT64:
		def_op_bytes = 4;
		def_ad_bytes = 8;
		break;
#endif
	default:
		return -1;
	}

	c->op_bytes = def_op_bytes;
	c->ad_bytes = def_ad_bytes;

	/* Legacy prefixes. */
	for (;;) {
		switch (c->b = insn_fetch(u8, 1, c->eip)) {
		case 0x66:	/* operand-size override */
			/* switch between 2/4 bytes */
			c->op_bytes = def_op_bytes ^ 6;
			break;
		case 0x67:	/* address-size override */
			if (mode == X86EMUL_MODE_PROT64)
				/* switch between 4/8 bytes */
				c->ad_bytes = def_ad_bytes ^ 12;
			else
				/* switch between 2/4 bytes */
				c->ad_bytes = def_ad_bytes ^ 6;
			break;
		case 0x26:	/* ES override */
		case 0x2e:	/* CS override */
		case 0x36:	/* SS override */
		case 0x3e:	/* DS override */
			set_seg_override(c, (c->b >> 3) & 3);
			break;
		case 0x64:	/* FS override */
		case 0x65:	/* GS override */
			set_seg_override(c, c->b & 7);
			break;
		case 0x40 ... 0x4f: /* REX */
			if (mode != X86EMUL_MODE_PROT64)
				goto done_prefixes;
			c->rex_prefix = c->b;
			continue;
		case 0xf0:	/* LOCK */
			c->lock_prefix = 1;
			break;
		case 0xf2:	/* REPNE/REPNZ */
			c->rep_prefix = REPNE_PREFIX;
			break;
		case 0xf3:	/* REP/REPE/REPZ */
			c->rep_prefix = REPE_PREFIX;
			break;
		default:
			goto done_prefixes;
		}

		/* Any legacy prefix after a REX prefix nullifies its effect. */

		c->rex_prefix = 0;
	}

done_prefixes:

	/* REX prefix. */
2710 2711
	if (c->rex_prefix & 8)
		c->op_bytes = 8;	/* REX.W */
2712 2713 2714

	/* Opcode byte(s). */
	opcode = opcode_table[c->b];
2715 2716 2717 2718 2719
	/* Two-byte opcode? */
	if (c->b == 0x0f) {
		c->twobyte = 1;
		c->b = insn_fetch(u8, 1, c->eip);
		opcode = twobyte_table[c->b];
2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755
	}
	c->d = opcode.flags;

	if (c->d & Group) {
		dual = c->d & GroupDual;
		c->modrm = insn_fetch(u8, 1, c->eip);
		--c->eip;

		if (c->d & GroupDual) {
			g_mod012 = opcode.u.gdual->mod012;
			g_mod3 = opcode.u.gdual->mod3;
		} else
			g_mod012 = g_mod3 = opcode.u.group;

		c->d &= ~(Group | GroupDual);

		goffset = (c->modrm >> 3) & 7;

		if ((c->modrm >> 6) == 3)
			opcode = g_mod3[goffset];
		else
			opcode = g_mod012[goffset];
		c->d |= opcode.flags;
	}

	c->execute = opcode.u.execute;

	/* Unrecognised? */
	if (c->d == 0 || (c->d & Undefined)) {
		DPRINTF("Cannot emulate %02x\n", c->b);
		return -1;
	}

	if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
		c->op_bytes = 8;

2756 2757 2758 2759 2760 2761 2762
	if (c->d & Op3264) {
		if (mode == X86EMUL_MODE_PROT64)
			c->op_bytes = 8;
		else
			c->op_bytes = 4;
	}

2763
	/* ModRM and SIB bytes. */
2764
	if (c->d & ModRM) {
2765
		rc = decode_modrm(ctxt, ops, &memop);
2766 2767 2768
		if (!c->has_seg_override)
			set_seg_override(c, c->modrm_seg);
	} else if (c->d & MemAbs)
2769
		rc = decode_abs(ctxt, ops, &memop);
2770 2771 2772 2773 2774 2775
	if (rc != X86EMUL_CONTINUE)
		goto done;

	if (!c->has_seg_override)
		set_seg_override(c, VCPU_SREG_DS);

2776 2777
	if (memop.type == OP_MEM && !(!c->twobyte && c->b == 0x8d))
		memop.addr.mem += seg_override_base(ctxt, ops, c);
2778

2779 2780
	if (memop.type == OP_MEM && c->ad_bytes != 8)
		memop.addr.mem = (u32)memop.addr.mem;
2781

2782 2783
	if (memop.type == OP_MEM && c->rip_relative)
		memop.addr.mem += c->eip;
2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795

	/*
	 * Decode and fetch the source operand: register, memory
	 * or immediate.
	 */
	switch (c->d & SrcMask) {
	case SrcNone:
		break;
	case SrcReg:
		decode_register_operand(&c->src, c, 0);
		break;
	case SrcMem16:
2796
		memop.bytes = 2;
2797 2798
		goto srcmem_common;
	case SrcMem32:
2799
		memop.bytes = 4;
2800 2801
		goto srcmem_common;
	case SrcMem:
2802
		memop.bytes = (c->d & ByteOp) ? 1 :
2803 2804
							   c->op_bytes;
	srcmem_common:
2805
		c->src = memop;
2806
		break;
2807
	case SrcImmU16:
2808 2809
		rc = decode_imm(ctxt, &c->src, 2, false);
		break;
2810
	case SrcImm:
2811 2812
		rc = decode_imm(ctxt, &c->src, imm_size(c), true);
		break;
2813
	case SrcImmU:
2814
		rc = decode_imm(ctxt, &c->src, imm_size(c), false);
2815 2816
		break;
	case SrcImmByte:
2817 2818
		rc = decode_imm(ctxt, &c->src, 1, true);
		break;
2819
	case SrcImmUByte:
2820
		rc = decode_imm(ctxt, &c->src, 1, false);
2821 2822 2823 2824
		break;
	case SrcAcc:
		c->src.type = OP_REG;
		c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2825
		c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
2826
		fetch_register_operand(&c->src);
2827 2828 2829 2830 2831 2832 2833 2834
		break;
	case SrcOne:
		c->src.bytes = 1;
		c->src.val = 1;
		break;
	case SrcSI:
		c->src.type = OP_MEM;
		c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2835
		c->src.addr.mem =
2836 2837 2838 2839 2840 2841
			register_address(c,  seg_override_base(ctxt, ops, c),
					 c->regs[VCPU_REGS_RSI]);
		c->src.val = 0;
		break;
	case SrcImmFAddr:
		c->src.type = OP_IMM;
2842
		c->src.addr.mem = c->eip;
2843 2844 2845 2846
		c->src.bytes = c->op_bytes + 2;
		insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
		break;
	case SrcMemFAddr:
2847 2848
		memop.bytes = c->op_bytes + 2;
		goto srcmem_common;
2849 2850 2851
		break;
	}

2852 2853 2854
	if (rc != X86EMUL_CONTINUE)
		goto done;

2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866
	/*
	 * Decode and fetch the second source operand: register, memory
	 * or immediate.
	 */
	switch (c->d & Src2Mask) {
	case Src2None:
		break;
	case Src2CL:
		c->src2.bytes = 1;
		c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
		break;
	case Src2ImmByte:
2867
		rc = decode_imm(ctxt, &c->src2, 1, true);
2868 2869 2870 2871 2872
		break;
	case Src2One:
		c->src2.bytes = 1;
		c->src2.val = 1;
		break;
2873 2874 2875
	case Src2Imm:
		rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
		break;
2876 2877
	}

2878 2879 2880
	if (rc != X86EMUL_CONTINUE)
		goto done;

2881 2882 2883 2884 2885 2886
	/* Decode and fetch the destination operand: register or memory. */
	switch (c->d & DstMask) {
	case DstReg:
		decode_register_operand(&c->dst, c,
			 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
		break;
2887 2888 2889 2890 2891 2892
	case DstImmUByte:
		c->dst.type = OP_IMM;
		c->dst.addr.mem = c->eip;
		c->dst.bytes = 1;
		c->dst.val = insn_fetch(u8, 1, c->eip);
		break;
2893 2894
	case DstMem:
	case DstMem64:
2895
		c->dst = memop;
2896 2897 2898 2899
		if ((c->d & DstMask) == DstMem64)
			c->dst.bytes = 8;
		else
			c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2900 2901
		if (c->d & BitOp)
			fetch_bit_operand(c);
2902
		c->dst.orig_val = c->dst.val;
2903 2904 2905 2906
		break;
	case DstAcc:
		c->dst.type = OP_REG;
		c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2907
		c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
2908
		fetch_register_operand(&c->dst);
2909 2910 2911 2912 2913
		c->dst.orig_val = c->dst.val;
		break;
	case DstDI:
		c->dst.type = OP_MEM;
		c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2914
		c->dst.addr.mem =
2915 2916 2917 2918
			register_address(c, es_base(ctxt, ops),
					 c->regs[VCPU_REGS_RDI]);
		c->dst.val = 0;
		break;
2919 2920 2921 2922 2923
	case ImplicitOps:
		/* Special instructions do their own operand decoding. */
	default:
		c->dst.type = OP_NONE; /* Disable writeback. */
		return 0;
2924 2925 2926 2927 2928 2929
	}

done:
	return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
}

2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951
static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	/* The second termination condition only applies for REPE
	 * and REPNE. Test if the repeat string operation prefix is
	 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
	 * corresponding termination condition according to:
	 * 	- if REPE/REPZ and ZF = 0 then done
	 * 	- if REPNE/REPNZ and ZF = 1 then done
	 */
	if (((c->b == 0xa6) || (c->b == 0xa7) ||
	     (c->b == 0xae) || (c->b == 0xaf))
	    && (((c->rep_prefix == REPE_PREFIX) &&
		 ((ctxt->eflags & EFLG_ZF) == 0))
		|| ((c->rep_prefix == REPNE_PREFIX) &&
		    ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
		return true;

	return false;
}

2952
int
2953
x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
2954
{
2955
	struct x86_emulate_ops *ops = ctxt->ops;
2956 2957
	u64 msr_data;
	struct decode_cache *c = &ctxt->decode;
2958
	int rc = X86EMUL_CONTINUE;
2959
	int saved_dst_type = c->dst.type;
2960
	int irq; /* Used for int 3, int, and into */
2961

2962
	ctxt->decode.mem_read.pos = 0;
2963

2964
	if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2965
		emulate_ud(ctxt);
2966 2967 2968
		goto done;
	}

2969
	/* LOCK prefix is allowed only with some instructions */
2970
	if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
2971
		emulate_ud(ctxt);
2972 2973 2974
		goto done;
	}

2975 2976 2977 2978 2979
	if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
		emulate_ud(ctxt);
		goto done;
	}

2980
	/* Privileged instruction can be executed only in CPL=0 */
2981
	if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
2982
		emulate_gp(ctxt, 0);
2983 2984 2985
		goto done;
	}

2986 2987
	if (c->rep_prefix && (c->d & String)) {
		/* All REP prefixes have the same first termination condition */
2988
		if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
2989
			ctxt->eip = c->eip;
2990 2991 2992 2993
			goto done;
		}
	}

2994
	if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
2995
		rc = read_emulated(ctxt, ops, c->src.addr.mem,
2996
					c->src.valptr, c->src.bytes);
2997
		if (rc != X86EMUL_CONTINUE)
2998
			goto done;
2999
		c->src.orig_val64 = c->src.val64;
3000 3001
	}

3002
	if (c->src2.type == OP_MEM) {
3003
		rc = read_emulated(ctxt, ops, c->src2.addr.mem,
3004
					&c->src2.val, c->src2.bytes);
3005 3006 3007 3008
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3009 3010 3011 3012
	if ((c->d & DstMask) == ImplicitOps)
		goto special_insn;


3013 3014
	if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
		/* optimisation - avoid slow emulated read if Mov */
3015
		rc = read_emulated(ctxt, ops, c->dst.addr.mem,
3016
				   &c->dst.val, c->dst.bytes);
3017 3018
		if (rc != X86EMUL_CONTINUE)
			goto done;
3019
	}
3020
	c->dst.orig_val = c->dst.val;
3021

3022 3023
special_insn:

3024 3025 3026 3027 3028 3029 3030
	if (c->execute) {
		rc = c->execute(ctxt);
		if (rc != X86EMUL_CONTINUE)
			goto done;
		goto writeback;
	}

3031
	if (c->twobyte)
A
Avi Kivity 已提交
3032 3033
		goto twobyte_insn;

3034
	switch (c->b) {
A
Avi Kivity 已提交
3035 3036
	case 0x00 ... 0x05:
	      add:		/* add */
3037
		emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
A
Avi Kivity 已提交
3038
		break;
3039
	case 0x06:		/* push es */
3040
		emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
3041 3042 3043
		break;
	case 0x07:		/* pop es */
		rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
3044
		if (rc != X86EMUL_CONTINUE)
3045 3046
			goto done;
		break;
A
Avi Kivity 已提交
3047 3048
	case 0x08 ... 0x0d:
	      or:		/* or */
3049
		emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
A
Avi Kivity 已提交
3050
		break;
3051
	case 0x0e:		/* push cs */
3052
		emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
3053
		break;
A
Avi Kivity 已提交
3054 3055
	case 0x10 ... 0x15:
	      adc:		/* adc */
3056
		emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
A
Avi Kivity 已提交
3057
		break;
3058
	case 0x16:		/* push ss */
3059
		emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
3060 3061 3062
		break;
	case 0x17:		/* pop ss */
		rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
3063
		if (rc != X86EMUL_CONTINUE)
3064 3065
			goto done;
		break;
A
Avi Kivity 已提交
3066 3067
	case 0x18 ... 0x1d:
	      sbb:		/* sbb */
3068
		emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
A
Avi Kivity 已提交
3069
		break;
3070
	case 0x1e:		/* push ds */
3071
		emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
3072 3073 3074
		break;
	case 0x1f:		/* pop ds */
		rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
3075
		if (rc != X86EMUL_CONTINUE)
3076 3077
			goto done;
		break;
3078
	case 0x20 ... 0x25:
A
Avi Kivity 已提交
3079
	      and:		/* and */
3080
		emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
A
Avi Kivity 已提交
3081 3082 3083
		break;
	case 0x28 ... 0x2d:
	      sub:		/* sub */
3084
		emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
A
Avi Kivity 已提交
3085 3086 3087
		break;
	case 0x30 ... 0x35:
	      xor:		/* xor */
3088
		emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
A
Avi Kivity 已提交
3089 3090 3091
		break;
	case 0x38 ... 0x3d:
	      cmp:		/* cmp */
3092
		emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
A
Avi Kivity 已提交
3093
		break;
3094 3095 3096 3097 3098 3099 3100 3101
	case 0x40 ... 0x47: /* inc r16/r32 */
		emulate_1op("inc", c->dst, ctxt->eflags);
		break;
	case 0x48 ... 0x4f: /* dec r16/r32 */
		emulate_1op("dec", c->dst, ctxt->eflags);
		break;
	case 0x58 ... 0x5f: /* pop reg */
	pop_instruction:
3102
		rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
3103
		if (rc != X86EMUL_CONTINUE)
3104 3105
			goto done;
		break;
3106
	case 0x60:	/* pusha */
3107 3108 3109
		rc = emulate_pusha(ctxt, ops);
		if (rc != X86EMUL_CONTINUE)
			goto done;
3110 3111 3112
		break;
	case 0x61:	/* popa */
		rc = emulate_popa(ctxt, ops);
3113
		if (rc != X86EMUL_CONTINUE)
3114 3115
			goto done;
		break;
A
Avi Kivity 已提交
3116
	case 0x63:		/* movsxd */
3117
		if (ctxt->mode != X86EMUL_MODE_PROT64)
A
Avi Kivity 已提交
3118
			goto cannot_emulate;
3119
		c->dst.val = (s32) c->src.val;
A
Avi Kivity 已提交
3120
		break;
3121 3122
	case 0x6c:		/* insb */
	case 0x6d:		/* insw/insd */
3123 3124
		c->src.val = c->regs[VCPU_REGS_RDX];
		goto do_io_in;
3125 3126
	case 0x6e:		/* outsb */
	case 0x6f:		/* outsw/outsd */
3127 3128
		c->dst.val = c->regs[VCPU_REGS_RDX];
		goto do_io_out;
3129
		break;
3130
	case 0x70 ... 0x7f: /* jcc (short) */
3131
		if (test_cc(c->b, ctxt->eflags))
3132
			jmp_rel(c, c->src.val);
3133
		break;
A
Avi Kivity 已提交
3134
	case 0x80 ... 0x83:	/* Grp1 */
3135
		switch (c->modrm_reg) {
A
Avi Kivity 已提交
3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154
		case 0:
			goto add;
		case 1:
			goto or;
		case 2:
			goto adc;
		case 3:
			goto sbb;
		case 4:
			goto and;
		case 5:
			goto sub;
		case 6:
			goto xor;
		case 7:
			goto cmp;
		}
		break;
	case 0x84 ... 0x85:
3155
	test:
3156
		emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
A
Avi Kivity 已提交
3157 3158
		break;
	case 0x86 ... 0x87:	/* xchg */
3159
	xchg:
A
Avi Kivity 已提交
3160
		/* Write back the register source. */
3161 3162
		c->src.val = c->dst.val;
		write_register_operand(&c->src);
A
Avi Kivity 已提交
3163 3164 3165 3166
		/*
		 * Write back the memory destination with implicit LOCK
		 * prefix.
		 */
3167
		c->dst.val = c->src.orig_val;
3168
		c->lock_prefix = 1;
A
Avi Kivity 已提交
3169 3170
		break;
	case 0x88 ... 0x8b:	/* mov */
3171
		goto mov;
3172 3173
	case 0x8c:  /* mov r/m, sreg */
		if (c->modrm_reg > VCPU_SREG_GS) {
3174
			emulate_ud(ctxt);
3175
			goto done;
3176
		}
3177
		c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
3178
		break;
N
Nitin A Kamble 已提交
3179
	case 0x8d: /* lea r16/r32, m */
3180
		c->dst.val = c->src.addr.mem;
N
Nitin A Kamble 已提交
3181
		break;
3182 3183 3184 3185
	case 0x8e: { /* mov seg, r/m16 */
		uint16_t sel;

		sel = c->src.val;
3186

3187 3188
		if (c->modrm_reg == VCPU_SREG_CS ||
		    c->modrm_reg > VCPU_SREG_GS) {
3189
			emulate_ud(ctxt);
3190 3191 3192
			goto done;
		}

3193
		if (c->modrm_reg == VCPU_SREG_SS)
3194
			ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3195

3196
		rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
3197 3198 3199 3200

		c->dst.type = OP_NONE;  /* Disable writeback. */
		break;
	}
A
Avi Kivity 已提交
3201
	case 0x8f:		/* pop (sole member of Grp1a) */
3202
		rc = emulate_grp1a(ctxt, ops);
3203
		if (rc != X86EMUL_CONTINUE)
A
Avi Kivity 已提交
3204 3205
			goto done;
		break;
3206 3207
	case 0x90 ... 0x97: /* nop / xchg reg, rax */
		if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
3208
			break;
3209
		goto xchg;
3210 3211 3212 3213 3214 3215 3216
	case 0x98: /* cbw/cwde/cdqe */
		switch (c->op_bytes) {
		case 2: c->dst.val = (s8)c->dst.val; break;
		case 4: c->dst.val = (s16)c->dst.val; break;
		case 8: c->dst.val = (s32)c->dst.val; break;
		}
		break;
N
Nitin A Kamble 已提交
3217
	case 0x9c: /* pushf */
3218
		c->src.val =  (unsigned long) ctxt->eflags;
3219
		emulate_push(ctxt, ops);
3220
		break;
N
Nitin A Kamble 已提交
3221
	case 0x9d: /* popf */
A
Avi Kivity 已提交
3222
		c->dst.type = OP_REG;
3223
		c->dst.addr.reg = &ctxt->eflags;
A
Avi Kivity 已提交
3224
		c->dst.bytes = c->op_bytes;
3225 3226 3227 3228
		rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
		if (rc != X86EMUL_CONTINUE)
			goto done;
		break;
3229
	case 0xa0 ... 0xa3:	/* mov */
A
Avi Kivity 已提交
3230
	case 0xa4 ... 0xa5:	/* movs */
3231
		goto mov;
A
Avi Kivity 已提交
3232
	case 0xa6 ... 0xa7:	/* cmps */
3233
		c->dst.type = OP_NONE; /* Disable writeback. */
3234
		DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem);
3235
		goto cmp;
3236 3237
	case 0xa8 ... 0xa9:	/* test ax, imm */
		goto test;
A
Avi Kivity 已提交
3238 3239
	case 0xaa ... 0xab:	/* stos */
	case 0xac ... 0xad:	/* lods */
3240
		goto mov;
A
Avi Kivity 已提交
3241
	case 0xae ... 0xaf:	/* scas */
3242
		goto cmp;
3243
	case 0xb0 ... 0xbf: /* mov r, imm */
3244
		goto mov;
3245 3246 3247
	case 0xc0 ... 0xc1:
		emulate_grp2(ctxt);
		break;
3248
	case 0xc3: /* ret */
A
Avi Kivity 已提交
3249
		c->dst.type = OP_REG;
3250
		c->dst.addr.reg = &c->eip;
A
Avi Kivity 已提交
3251
		c->dst.bytes = c->op_bytes;
3252
		goto pop_instruction;
3253 3254 3255 3256 3257 3258 3259 3260 3261 3262
	case 0xc4:		/* les */
		rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
		if (rc != X86EMUL_CONTINUE)
			goto done;
		break;
	case 0xc5:		/* lds */
		rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
		if (rc != X86EMUL_CONTINUE)
			goto done;
		break;
3263 3264 3265 3266
	case 0xc6 ... 0xc7:	/* mov (sole member of Grp11) */
	mov:
		c->dst.val = c->src.val;
		break;
3267 3268
	case 0xcb:		/* ret far */
		rc = emulate_ret_far(ctxt, ops);
3269 3270 3271
		if (rc != X86EMUL_CONTINUE)
			goto done;
		break;
3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287
	case 0xcc:		/* int3 */
		irq = 3;
		goto do_interrupt;
	case 0xcd:		/* int n */
		irq = c->src.val;
	do_interrupt:
		rc = emulate_int(ctxt, ops, irq);
		if (rc != X86EMUL_CONTINUE)
			goto done;
		break;
	case 0xce:		/* into */
		if (ctxt->eflags & EFLG_OF) {
			irq = 4;
			goto do_interrupt;
		}
		break;
3288 3289 3290
	case 0xcf:		/* iret */
		rc = emulate_iret(ctxt, ops);

3291
		if (rc != X86EMUL_CONTINUE)
3292 3293
			goto done;
		break;
3294 3295 3296 3297 3298 3299 3300
	case 0xd0 ... 0xd1:	/* Grp2 */
		emulate_grp2(ctxt);
		break;
	case 0xd2 ... 0xd3:	/* Grp2 */
		c->src.val = c->regs[VCPU_REGS_RCX];
		emulate_grp2(ctxt);
		break;
3301 3302 3303 3304 3305 3306
	case 0xe0 ... 0xe2:	/* loop/loopz/loopnz */
		register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
		if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
		    (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
			jmp_rel(c, c->src.val);
		break;
3307 3308 3309 3310
	case 0xe3:	/* jcxz/jecxz/jrcxz */
		if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
			jmp_rel(c, c->src.val);
		break;
3311 3312
	case 0xe4: 	/* inb */
	case 0xe5: 	/* in */
3313
		goto do_io_in;
3314 3315
	case 0xe6: /* outb */
	case 0xe7: /* out */
3316
		goto do_io_out;
3317
	case 0xe8: /* call (near) */ {
3318
		long int rel = c->src.val;
3319
		c->src.val = (unsigned long) c->eip;
3320
		jmp_rel(c, rel);
3321
		emulate_push(ctxt, ops);
3322
		break;
3323 3324
	}
	case 0xe9: /* jmp rel */
3325
		goto jmp;
3326 3327
	case 0xea: { /* jmp far */
		unsigned short sel;
3328
	jump_far:
3329 3330 3331
		memcpy(&sel, c->src.valptr + c->op_bytes, 2);

		if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
3332
			goto done;
3333

3334 3335
		c->eip = 0;
		memcpy(&c->eip, c->src.valptr, c->op_bytes);
3336
		break;
3337
	}
3338 3339
	case 0xeb:
	      jmp:		/* jmp rel short */
3340
		jmp_rel(c, c->src.val);
3341
		c->dst.type = OP_NONE; /* Disable writeback. */
3342
		break;
3343 3344
	case 0xec: /* in al,dx */
	case 0xed: /* in (e/r)ax,dx */
3345 3346 3347 3348
		c->src.val = c->regs[VCPU_REGS_RDX];
	do_io_in:
		c->dst.bytes = min(c->dst.bytes, 4u);
		if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
3349
			emulate_gp(ctxt, 0);
3350 3351
			goto done;
		}
3352 3353
		if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
				     &c->dst.val))
3354 3355
			goto done; /* IO is needed */
		break;
3356 3357
	case 0xee: /* out dx,al */
	case 0xef: /* out dx,(e/r)ax */
3358
		c->dst.val = c->regs[VCPU_REGS_RDX];
3359
	do_io_out:
3360 3361 3362
		c->src.bytes = min(c->src.bytes, 4u);
		if (!emulator_io_permited(ctxt, ops, c->dst.val,
					  c->src.bytes)) {
3363
			emulate_gp(ctxt, 0);
3364 3365
			goto done;
		}
3366 3367
		ops->pio_out_emulated(c->src.bytes, c->dst.val,
				      &c->src.val, 1, ctxt->vcpu);
3368
		c->dst.type = OP_NONE;	/* Disable writeback. */
3369
		break;
3370
	case 0xf4:              /* hlt */
3371
		ctxt->vcpu->arch.halt_request = 1;
3372
		break;
3373 3374 3375 3376
	case 0xf5:	/* cmc */
		/* complement carry flag from eflags reg */
		ctxt->eflags ^= EFLG_CF;
		break;
3377
	case 0xf6 ... 0xf7:	/* Grp3 */
3378
		if (emulate_grp3(ctxt, ops) != X86EMUL_CONTINUE)
3379
			goto cannot_emulate;
3380
		break;
3381 3382 3383
	case 0xf8: /* clc */
		ctxt->eflags &= ~EFLG_CF;
		break;
3384 3385 3386
	case 0xf9: /* stc */
		ctxt->eflags |= EFLG_CF;
		break;
3387
	case 0xfa: /* cli */
3388
		if (emulator_bad_iopl(ctxt, ops)) {
3389
			emulate_gp(ctxt, 0);
3390
			goto done;
3391
		} else
3392
			ctxt->eflags &= ~X86_EFLAGS_IF;
3393 3394
		break;
	case 0xfb: /* sti */
3395
		if (emulator_bad_iopl(ctxt, ops)) {
3396
			emulate_gp(ctxt, 0);
3397 3398
			goto done;
		} else {
3399
			ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3400 3401
			ctxt->eflags |= X86_EFLAGS_IF;
		}
3402
		break;
3403 3404 3405 3406 3407 3408
	case 0xfc: /* cld */
		ctxt->eflags &= ~EFLG_DF;
		break;
	case 0xfd: /* std */
		ctxt->eflags |= EFLG_DF;
		break;
3409 3410
	case 0xfe: /* Grp4 */
	grp45:
3411
		rc = emulate_grp45(ctxt, ops);
3412
		if (rc != X86EMUL_CONTINUE)
3413 3414
			goto done;
		break;
3415 3416 3417 3418
	case 0xff: /* Grp5 */
		if (c->modrm_reg == 5)
			goto jump_far;
		goto grp45;
3419 3420
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
3421
	}
3422 3423 3424

writeback:
	rc = writeback(ctxt, ops);
3425
	if (rc != X86EMUL_CONTINUE)
3426 3427
		goto done;

3428 3429 3430 3431 3432 3433
	/*
	 * restore dst type in case the decoding will be reused
	 * (happens for string instruction )
	 */
	c->dst.type = saved_dst_type;

3434
	if ((c->d & SrcMask) == SrcSI)
3435 3436
		string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
				VCPU_REGS_RSI, &c->src);
3437 3438

	if ((c->d & DstMask) == DstDI)
3439 3440
		string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
				&c->dst);
3441

3442
	if (c->rep_prefix && (c->d & String)) {
3443
		struct read_cache *r = &ctxt->decode.io_read;
3444
		register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3445

3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461
		if (!string_insn_completed(ctxt)) {
			/*
			 * Re-enter guest when pio read ahead buffer is empty
			 * or, if it is not used, after each 1024 iteration.
			 */
			if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
			    (r->end == 0 || r->end != r->pos)) {
				/*
				 * Reset read cache. Usually happens before
				 * decode, but since instruction is restarted
				 * we have to do it here.
				 */
				ctxt->decode.mem_read.end = 0;
				return EMULATION_RESTART;
			}
			goto done; /* skip rip writeback */
3462
		}
3463
	}
3464 3465

	ctxt->eip = c->eip;
3466 3467

done:
3468
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
A
Avi Kivity 已提交
3469 3470

twobyte_insn:
3471
	switch (c->b) {
A
Avi Kivity 已提交
3472
	case 0x01: /* lgdt, lidt, lmsw */
3473
		switch (c->modrm_reg) {
A
Avi Kivity 已提交
3474 3475 3476
			u16 size;
			unsigned long address;

3477
		case 0: /* vmcall */
3478
			if (c->modrm_mod != 3 || c->modrm_rm != 1)
3479 3480
				goto cannot_emulate;

3481
			rc = kvm_fix_hypercall(ctxt->vcpu);
3482
			if (rc != X86EMUL_CONTINUE)
3483 3484
				goto done;

3485
			/* Let the processor re-execute the fixed hypercall */
3486
			c->eip = ctxt->eip;
3487 3488
			/* Disable writeback. */
			c->dst.type = OP_NONE;
3489
			break;
A
Avi Kivity 已提交
3490
		case 2: /* lgdt */
3491
			rc = read_descriptor(ctxt, ops, c->src.addr.mem,
3492
					     &size, &address, c->op_bytes);
3493
			if (rc != X86EMUL_CONTINUE)
A
Avi Kivity 已提交
3494 3495
				goto done;
			realmode_lgdt(ctxt->vcpu, size, address);
3496 3497
			/* Disable writeback. */
			c->dst.type = OP_NONE;
A
Avi Kivity 已提交
3498
			break;
3499
		case 3: /* lidt/vmmcall */
3500 3501 3502 3503
			if (c->modrm_mod == 3) {
				switch (c->modrm_rm) {
				case 1:
					rc = kvm_fix_hypercall(ctxt->vcpu);
3504
					if (rc != X86EMUL_CONTINUE)
3505 3506 3507 3508 3509
						goto done;
					break;
				default:
					goto cannot_emulate;
				}
3510
			} else {
3511
				rc = read_descriptor(ctxt, ops, c->src.addr.mem,
3512
						     &size, &address,
3513
						     c->op_bytes);
3514
				if (rc != X86EMUL_CONTINUE)
3515 3516 3517
					goto done;
				realmode_lidt(ctxt->vcpu, size, address);
			}
3518 3519
			/* Disable writeback. */
			c->dst.type = OP_NONE;
A
Avi Kivity 已提交
3520 3521
			break;
		case 4: /* smsw */
3522
			c->dst.bytes = 2;
3523
			c->dst.val = ops->get_cr(0, ctxt->vcpu);
A
Avi Kivity 已提交
3524 3525
			break;
		case 6: /* lmsw */
3526
			ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
3527
				    (c->src.val & 0x0f), ctxt->vcpu);
3528
			c->dst.type = OP_NONE;
A
Avi Kivity 已提交
3529
			break;
3530
		case 5: /* not defined */
3531
			emulate_ud(ctxt);
3532
			goto done;
A
Avi Kivity 已提交
3533
		case 7: /* invlpg*/
3534
			emulate_invlpg(ctxt->vcpu, c->src.addr.mem);
3535 3536
			/* Disable writeback. */
			c->dst.type = OP_NONE;
A
Avi Kivity 已提交
3537 3538 3539 3540 3541
			break;
		default:
			goto cannot_emulate;
		}
		break;
3542
	case 0x05: 		/* syscall */
3543
		rc = emulate_syscall(ctxt, ops);
3544 3545
		if (rc != X86EMUL_CONTINUE)
			goto done;
3546 3547
		else
			goto writeback;
3548
		break;
3549 3550 3551 3552
	case 0x06:
		emulate_clts(ctxt->vcpu);
		break;
	case 0x09:		/* wbinvd */
3553 3554 3555
		kvm_emulate_wbinvd(ctxt->vcpu);
		break;
	case 0x08:		/* invd */
3556 3557 3558 3559
	case 0x0d:		/* GrpP (prefetch) */
	case 0x18:		/* Grp16 (prefetch/nop) */
		break;
	case 0x20: /* mov cr, reg */
3560 3561 3562 3563
		switch (c->modrm_reg) {
		case 1:
		case 5 ... 7:
		case 9 ... 15:
3564
			emulate_ud(ctxt);
3565 3566
			goto done;
		}
3567
		c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
3568
		break;
A
Avi Kivity 已提交
3569
	case 0x21: /* mov from dr to reg */
3570 3571
		if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
		    (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3572
			emulate_ud(ctxt);
3573 3574
			goto done;
		}
3575
		ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
A
Avi Kivity 已提交
3576
		break;
3577
	case 0x22: /* mov reg, cr */
3578
		if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
3579
			emulate_gp(ctxt, 0);
3580 3581
			goto done;
		}
3582 3583
		c->dst.type = OP_NONE;
		break;
A
Avi Kivity 已提交
3584
	case 0x23: /* mov from reg to dr */
3585 3586
		if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
		    (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3587
			emulate_ud(ctxt);
3588 3589
			goto done;
		}
3590

3591
		if (ops->set_dr(c->modrm_reg, c->src.val &
3592 3593 3594
				((ctxt->mode == X86EMUL_MODE_PROT64) ?
				 ~0ULL : ~0U), ctxt->vcpu) < 0) {
			/* #UD condition is already handled by the code above */
3595
			emulate_gp(ctxt, 0);
3596 3597 3598
			goto done;
		}

3599
		c->dst.type = OP_NONE;	/* no writeback */
A
Avi Kivity 已提交
3600
		break;
3601 3602 3603 3604
	case 0x30:
		/* wrmsr */
		msr_data = (u32)c->regs[VCPU_REGS_RAX]
			| ((u64)c->regs[VCPU_REGS_RDX] << 32);
3605
		if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
3606
			emulate_gp(ctxt, 0);
3607
			goto done;
3608 3609 3610 3611 3612
		}
		rc = X86EMUL_CONTINUE;
		break;
	case 0x32:
		/* rdmsr */
3613
		if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
3614
			emulate_gp(ctxt, 0);
3615
			goto done;
3616 3617 3618 3619 3620 3621
		} else {
			c->regs[VCPU_REGS_RAX] = (u32)msr_data;
			c->regs[VCPU_REGS_RDX] = msr_data >> 32;
		}
		rc = X86EMUL_CONTINUE;
		break;
3622
	case 0x34:		/* sysenter */
3623
		rc = emulate_sysenter(ctxt, ops);
3624 3625
		if (rc != X86EMUL_CONTINUE)
			goto done;
3626 3627
		else
			goto writeback;
3628 3629
		break;
	case 0x35:		/* sysexit */
3630
		rc = emulate_sysexit(ctxt, ops);
3631 3632
		if (rc != X86EMUL_CONTINUE)
			goto done;
3633 3634
		else
			goto writeback;
3635
		break;
A
Avi Kivity 已提交
3636
	case 0x40 ... 0x4f:	/* cmov */
3637
		c->dst.val = c->dst.orig_val = c->src.val;
3638 3639
		if (!test_cc(c->b, ctxt->eflags))
			c->dst.type = OP_NONE; /* no writeback */
A
Avi Kivity 已提交
3640
		break;
3641
	case 0x80 ... 0x8f: /* jnz rel, etc*/
3642
		if (test_cc(c->b, ctxt->eflags))
3643
			jmp_rel(c, c->src.val);
3644
		break;
3645 3646 3647
	case 0x90 ... 0x9f:     /* setcc r/m8 */
		c->dst.val = test_cc(c->b, ctxt->eflags);
		break;
3648
	case 0xa0:	  /* push fs */
3649
		emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
3650 3651 3652
		break;
	case 0xa1:	 /* pop fs */
		rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
3653
		if (rc != X86EMUL_CONTINUE)
3654 3655
			goto done;
		break;
3656 3657
	case 0xa3:
	      bt:		/* bt */
Q
Qing He 已提交
3658
		c->dst.type = OP_NONE;
3659 3660
		/* only subword offset */
		c->src.val &= (c->dst.bytes << 3) - 1;
3661
		emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
3662
		break;
3663 3664 3665 3666
	case 0xa4: /* shld imm8, r, r/m */
	case 0xa5: /* shld cl, r, r/m */
		emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
		break;
3667
	case 0xa8:	/* push gs */
3668
		emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
3669 3670 3671
		break;
	case 0xa9:	/* pop gs */
		rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
3672
		if (rc != X86EMUL_CONTINUE)
3673 3674
			goto done;
		break;
3675 3676
	case 0xab:
	      bts:		/* bts */
3677
		emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
3678
		break;
3679 3680 3681 3682
	case 0xac: /* shrd imm8, r, r/m */
	case 0xad: /* shrd cl, r, r/m */
		emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
		break;
3683 3684
	case 0xae:              /* clflush */
		break;
A
Avi Kivity 已提交
3685 3686 3687 3688 3689
	case 0xb0 ... 0xb1:	/* cmpxchg */
		/*
		 * Save real source value, then compare EAX against
		 * destination.
		 */
3690 3691
		c->src.orig_val = c->src.val;
		c->src.val = c->regs[VCPU_REGS_RAX];
3692 3693
		emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
		if (ctxt->eflags & EFLG_ZF) {
A
Avi Kivity 已提交
3694
			/* Success: write back to memory. */
3695
			c->dst.val = c->src.orig_val;
A
Avi Kivity 已提交
3696 3697
		} else {
			/* Failure: write the value we saw to EAX. */
3698
			c->dst.type = OP_REG;
3699
			c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
A
Avi Kivity 已提交
3700 3701
		}
		break;
3702 3703 3704 3705 3706
	case 0xb2:		/* lss */
		rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
		if (rc != X86EMUL_CONTINUE)
			goto done;
		break;
A
Avi Kivity 已提交
3707 3708
	case 0xb3:
	      btr:		/* btr */
3709
		emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
A
Avi Kivity 已提交
3710
		break;
3711 3712 3713 3714 3715 3716 3717 3718 3719 3720
	case 0xb4:		/* lfs */
		rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
		if (rc != X86EMUL_CONTINUE)
			goto done;
		break;
	case 0xb5:		/* lgs */
		rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
		if (rc != X86EMUL_CONTINUE)
			goto done;
		break;
A
Avi Kivity 已提交
3721
	case 0xb6 ... 0xb7:	/* movzx */
3722 3723 3724
		c->dst.bytes = c->op_bytes;
		c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
						       : (u16) c->src.val;
A
Avi Kivity 已提交
3725 3726
		break;
	case 0xba:		/* Grp8 */
3727
		switch (c->modrm_reg & 3) {
A
Avi Kivity 已提交
3728 3729 3730 3731 3732 3733 3734 3735 3736 3737
		case 0:
			goto bt;
		case 1:
			goto bts;
		case 2:
			goto btr;
		case 3:
			goto btc;
		}
		break;
3738 3739
	case 0xbb:
	      btc:		/* btc */
3740
		emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
3741
		break;
3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765
	case 0xbc: {		/* bsf */
		u8 zf;
		__asm__ ("bsf %2, %0; setz %1"
			 : "=r"(c->dst.val), "=q"(zf)
			 : "r"(c->src.val));
		ctxt->eflags &= ~X86_EFLAGS_ZF;
		if (zf) {
			ctxt->eflags |= X86_EFLAGS_ZF;
			c->dst.type = OP_NONE;	/* Disable writeback. */
		}
		break;
	}
	case 0xbd: {		/* bsr */
		u8 zf;
		__asm__ ("bsr %2, %0; setz %1"
			 : "=r"(c->dst.val), "=q"(zf)
			 : "r"(c->src.val));
		ctxt->eflags &= ~X86_EFLAGS_ZF;
		if (zf) {
			ctxt->eflags |= X86_EFLAGS_ZF;
			c->dst.type = OP_NONE;	/* Disable writeback. */
		}
		break;
	}
A
Avi Kivity 已提交
3766
	case 0xbe ... 0xbf:	/* movsx */
3767 3768 3769
		c->dst.bytes = c->op_bytes;
		c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
							(s16) c->src.val;
A
Avi Kivity 已提交
3770
		break;
3771 3772 3773 3774 3775 3776
	case 0xc0 ... 0xc1:	/* xadd */
		emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
		/* Write back the register source. */
		c->src.val = c->dst.orig_val;
		write_register_operand(&c->src);
		break;
3777
	case 0xc3:		/* movnti */
3778 3779 3780
		c->dst.bytes = c->op_bytes;
		c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
							(u64) c->src.val;
3781
		break;
A
Avi Kivity 已提交
3782
	case 0xc7:		/* Grp9 (cmpxchg8b) */
3783
		rc = emulate_grp9(ctxt, ops);
3784
		if (rc != X86EMUL_CONTINUE)
3785 3786
			goto done;
		break;
3787 3788
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
3789 3790 3791 3792
	}
	goto writeback;

cannot_emulate:
3793
	DPRINTF("Cannot emulate %02x\n", c->b);
A
Avi Kivity 已提交
3794 3795
	return -1;
}