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202108281102

上级 b630515c
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examples/hdl4se_riscv/de1/clk/clk100M.v
浏览文件 @ b242c25d
......@@ -2,7 +2,7 @@
// GENERATION: XML
// clk100M.v
// Generated using ACDS version 13.1 162 at 2021.08.27.17:20:30
// Generated using ACDS version 13.1 162 at 2021.08.28.11:01:41
`timescale 1 ps / 1 ps
module clk100M (
......@@ -68,7 +68,7 @@ endmodule
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="100.0" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="50.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
......
examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v
浏览文件 @ b242c25d
......@@ -22,7 +22,7 @@ module clk100M_0002(
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("100.000000 MHz"),
.output_clock_frequency0("50.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("75.000000 MHz"),
......
examples/hdl4se_riscv/de1/clk/clk100M_sim/aldec/rivierapro_setup.tcl
浏览文件 @ b242c25d
......@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.17:20:37
# ACDS 13.1 162 win32 2021.08.28.11:01:49
# ----------------------------------------
# Auto-generated simulation script
......
examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/ncsim_setup.sh
浏览文件 @ b242c25d
......@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.17:20:37
# ACDS 13.1 162 win32 2021.08.28.11:01:49
# ----------------------------------------
# ncsim - auto-generated simulation script
......
examples/hdl4se_riscv/de1/clk/clk100M_sim/clk100M.vo
浏览文件 @ b242c25d
......@@ -210,7 +210,7 @@ module clk100M
clk100m_altera_pll_altera_pll_i_1096.n_cnt_odd_div_duty_en = "false",
clk100m_altera_pll_altera_pll_i_1096.number_of_clocks = 2,
clk100m_altera_pll_altera_pll_i_1096.operation_mode = "direct",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency0 = "100.000000 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency0 = "50.000000 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency1 = "75.000000 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency10 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency11 = "0 MHz",
......
examples/hdl4se_riscv/de1/clk/clk100M_sim/mentor/msim_setup.tcl
浏览文件 @ b242c25d
......@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.17:20:37
# ACDS 13.1 162 win32 2021.08.28.11:01:49
# ----------------------------------------
# Auto-generated simulation script
......
examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcs/vcs_setup.sh
浏览文件 @ b242c25d
......@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.17:20:37
# ACDS 13.1 162 win32 2021.08.28.11:01:49
# ----------------------------------------
# vcs - auto-generated simulation script
......
examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/vcsmx_setup.sh
浏览文件 @ b242c25d
......@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.17:20:37
# ACDS 13.1 162 win32 2021.08.28.11:01:49
# ----------------------------------------
# vcsmx - auto-generated simulation script
......
examples/hdl4se_riscv/de1/clk100M.xml
浏览文件 @ b242c25d
......@@ -19,7 +19,7 @@
<generic name="gui_frac_multiply_factor" value="1" />
<generic name="gui_divide_factor_n" value="1" />
<generic name="gui_cascade_counter0" value="false" />
<generic name="gui_output_clock_frequency0" value="10.0" />
<generic name="gui_output_clock_frequency0" value="100.0" />
<generic name="gui_divide_factor_c0" value="1" />
<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
<generic name="gui_ps_units0" value="ps" />
......
examples/hdl4se_riscv/de1/de1_risc.mpf
浏览文件 @ b242c25d
......@@ -454,7 +454,7 @@ Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 co
Project_File_1 = C:/altera/13.1/quartus/eda/sim_lib/220model.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1382637203 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1630049086 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1630049086 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/suber.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629969062 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult.v
......@@ -470,9 +470,9 @@ Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 co
Project_File_9 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1630042952 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_10 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1630053824 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1630053824 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_11 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1630049096 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1630049096 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629969030 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v
......
examples/hdl4se_riscv/de1/de1_riscv.asm.rpt
浏览文件 @ b242c25d
Assembler report for de1_riscv
Fri Aug 27 17:23:28 2021
Sat Aug 28 10:56:11 2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
......@@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Fri Aug 27 17:23:28 2021 ;
; Assembler Status ; Successful - Sat Aug 28 10:56:11 2021 ;
; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ;
......@@ -92,8 +92,8 @@ applicable agreement for further details.
; Option ; Setting ;
+----------------+--------------------------------------------------------------------+
; Device ; 5CSEMA5F31C6 ;
; JTAG usercode ; 0x0122624D ;
; Checksum ; 0x0122624D ;
; JTAG usercode ; 0x0122B7FD ;
; Checksum ; 0x0122B7FD ;
+----------------+--------------------------------------------------------------------+
......@@ -103,12 +103,12 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Info: Processing started: Fri Aug 27 17:23:13 2021
Info: Processing started: Sat Aug 28 10:55:56 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 661 megabytes
Info: Processing ended: Fri Aug 27 17:23:28 2021
Info: Processing ended: Sat Aug 28 10:56:11 2021
Info: Elapsed time: 00:00:15
Info: Total CPU time (on all processors): 00:00:15
......
examples/hdl4se_riscv/de1/de1_riscv.done
浏览文件 @ b242c25d
Fri Aug 27 17:24:02 2021
Sat Aug 28 10:56:46 2021
examples/hdl4se_riscv/de1/de1_riscv.fit.summary
浏览文件 @ b242c25d
Fitter Status : Successful - Fri Aug 27 17:23:08 2021
Fitter Status : Successful - Sat Aug 28 10:55:51 2021
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : de1_riscv
Top-level Entity Name : de1_riscv
Family : Cyclone V
Device : 5CSEMA5F31C6
Timing Models : Preliminary
Logic utilization (in ALMs) : 2,468 / 32,070 ( 8 % )
Total registers : 1833
Logic utilization (in ALMs) : 2,494 / 32,070 ( 8 % )
Total registers : 1863
Total pins : 204 / 457 ( 45 % )
Total virtual pins : 0
Total block memory bits : 66,560 / 4,065,280 ( 2 % )
......
examples/hdl4se_riscv/de1/de1_riscv.flow.rpt
浏览文件 @ b242c25d
Flow report for de1_riscv
Fri Aug 27 17:24:01 2021
Sat Aug 28 11:02:31 2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
......@@ -40,25 +40,25 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+---------------------------------------------+
; Flow Status ; Successful - Fri Aug 27 17:23:28 2021 ;
; Flow Status ; Successful - Sat Aug 28 11:02:31 2021 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ;
; Device ; 5CSEMA5F31C6 ;
; Timing Models ; Preliminary ;
; Logic utilization (in ALMs) ; 2,468 / 32,070 ( 8 % ) ;
; Total registers ; 1833 ;
; Total pins ; 204 / 457 ( 45 % ) ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 1636 ;
; Total pins ; 204 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 66,560 / 4,065,280 ( 2 % ) ;
; Total DSP Blocks ; 10 / 87 ( 11 % ) ;
; Total block memory bits ; 67,296 ;
; Total DSP Blocks ; 10 ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI TX Channels ; 0 ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
; Total PLLs ; 1 ;
; Total DLLs ; 0 ;
+---------------------------------+---------------------------------------------+
......@@ -67,7 +67,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 08/27/2021 17:20:52 ;
; Start date & time ; 08/28/2021 11:02:08 ;
; Main task ; Compilation ;
; Revision Name ; de1_riscv ;
+-------------------+---------------------+
......@@ -78,7 +78,7 @@ applicable agreement for further details.
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
; COMPILER_SIGNATURE_ID ; 621136229624.163005605235460 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 621136229624.163011972824564 ; -- ; -- ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M_0002 ; -- ;
......@@ -129,38 +129,29 @@ applicable agreement for further details.
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:21 ; 1.0 ; 670 MB ; 00:00:20 ;
; Fitter ; 00:01:53 ; 1.4 ; 2325 MB ; 00:02:30 ;
; Assembler ; 00:00:15 ; 1.0 ; 661 MB ; 00:00:15 ;
; TimeQuest Timing Analyzer ; 00:00:32 ; 1.3 ; 1135 MB ; 00:00:41 ;
; Total ; 00:03:01 ; -- ; -- ; 00:03:46 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:22 ; 1.0 ; 670 MB ; 00:00:21 ;
; Total ; 00:00:22 ; -- ; -- ; 00:00:21 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
; Fitter ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
; Assembler ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
; TimeQuest Timing Analyzer ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
+-----------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
+----------------------+------------------+-----------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off de1_riscv -c de1_riscv
quartus_fit --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv
quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv
quartus_sta de1_riscv -c de1_riscv
examples/hdl4se_riscv/de1/de1_riscv.jdi
浏览文件 @ b242c25d
<sld_project_info>
<project>
<hash md5_digest_80b="ad09d8c1da314a1d4db5"/>
<hash md5_digest_80b="1756052714224fa8aed0"/>
</project>
<file_info>
<file device="5CSEMA5F31C6" path="de1_riscv.sof" usercode="0xFFFFFFFF"/>
......
examples/hdl4se_riscv/de1/de1_riscv.map.rpt
浏览文件 @ b242c25d
因为 它太大了无法显示 source diff 。你可以改为 查看blob。
examples/hdl4se_riscv/de1/de1_riscv.map.summary
浏览文件 @ b242c25d
Analysis & Synthesis Status : Successful - Fri Aug 27 17:21:13 2021
Analysis & Synthesis Status : Successful - Sat Aug 28 11:02:31 2021
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : de1_riscv
Top-level Entity Name : de1_riscv
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 1608
Total registers : 1636
Total pins : 204
Total virtual pins : 0
Total block memory bits : 67,296
......
examples/hdl4se_riscv/de1/de1_riscv.qsf
浏览文件 @ b242c25d
......@@ -488,6 +488,7 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_FILE de1_riscv_v2.v
set_global_assignment -name VERILOG_FILE ../verilog/riscv_core.v
set_global_assignment -name VERILOG_FILE uart/altera_uart.v
set_global_assignment -name VERILOG_FILE vgasig.v
......
examples/hdl4se_riscv/de1/de1_riscv.sta.rpt
浏览文件 @ b242c25d
因为 它太大了无法显示 source diff 。你可以改为 查看blob。
examples/hdl4se_riscv/de1/de1_riscv.sta.summary
浏览文件 @ b242c25d
......@@ -3,11 +3,11 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : -1.729
TNS : -126.223
Slack : -1.197
TNS : -95.783
Type : Slow 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.281
Slack : 0.266
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
......@@ -23,11 +23,11 @@ Slack : 9.670
TNS : 0.000
Type : Slow 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : -1.885
TNS : -158.135
Slack : -1.352
TNS : -121.670
Type : Slow 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.260
Slack : 0.247
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
......@@ -35,7 +35,7 @@ Slack : 1.666
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 3.753
Slack : 3.758
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
......@@ -43,11 +43,11 @@ Slack : 9.673
TNS : 0.000
Type : Fast 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 3.113
Slack : 3.503
TNS : 0.000
Type : Fast 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.163
Slack : 0.154
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
......@@ -55,7 +55,7 @@ Slack : 1.666
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 3.889
Slack : 3.888
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
......@@ -63,11 +63,11 @@ Slack : 9.336
TNS : 0.000
Type : Fast 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 3.512
Slack : 3.812
TNS : 0.000
Type : Fast 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.147
Slack : 0.141
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
......@@ -75,7 +75,7 @@ Slack : 1.666
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 3.889
Slack : 3.888
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
......
examples/hdl4se_riscv/de1/de1_riscv_v2.v 0 → 100644
浏览文件 @ b242c25d
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
`define USECLOCK50_1
module de1_riscv(
//////////// ADC //////////
output ADC_CONVST,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
//////////// Audio //////////
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
//////////// SDRAM //////////
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
//////////// I2C for Audio and Video-In //////////
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
//////////// SEG7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
//////////// IR //////////
input IRDA_RXD,
output IRDA_TXD,
//////////// KEY //////////
input [3:0] KEY,
//////////// LED //////////
output [9:0] LEDR,
//////////// PS2 //////////
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
//////////// SW //////////
input [9:0] SW,
//////////// Video-In //////////
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
//////////// VGA //////////
output VGA_BLANK_N,
output [7:0] VGA_B,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS,
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
inout [35:0] GPIO
);
wire uart_tx;
wire uart_rx;
assign GPIO[5] = uart_tx;
assign GPIO[7] = 1'bz;
assign uart_rx = GPIO[7];
`ifdef USECLOCK50
wire wClk = CLOCK_50;
`else
wire clk100MHz, clk75MHz, clklocked;
clk100M clk100(.refclk(CLOCK_50),
.rst(~KEY[3]),
.outclk_0(clk100MHz),
.outclk_1(clk75MHz),
.locked(clklocked));
wire wClk = clk100MHz;
`endif
wire nwReset = KEY[3];
wire wWrite, wRead;
wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey, bReadDataUart;
wire [3:0] bWriteMask;
assign bReadDataKey = {18'b0, KEY, SW};
reg readcmd;
reg [31:0] readaddr;
wire wRead_out = readcmd;
wire [31:0] bReadAddr_out = readaddr;
always @(posedge wClk) begin
if (!nwReset) begin
readcmd <= 1'b0;
readaddr <= 32'b0;
end else begin
readcmd <= wRead;
readaddr <= bReadAddr;
end
end
assign bReadData =
((bReadAddr_out & 32'hffffff00) == 32'hf0000000) ? bReadDataKey : (
((bReadAddr_out & 32'hffffc000) == 32'h00000000) ? bReadDataRam : (
((bReadAddr_out & 32'hffffff00) == 32'h00000100) ? bReadDataUart : (0)
)
);
wire [10:0] ramaddr;
assign ramaddr = wWrite?bWriteAddr[12:2]:bReadAddr[12:2];
wire [4:0] regno;
wire [3:0] regena;
wire [31:0] regwrdata;
wire regwren;
wire [31:0] regrddata;
wire [2:0] uartaddr;
assign uartaddr = wWrite?bWriteAddr[4:2]:bReadAddr[4:2];
altera_uart uart(
// inputs:
.address(uartaddr),
.begintransfer(SW[0]),
.chipselect((uartaddr & 32'hffffff00)==32'hf0000100),
.clk(wClk),
.read_n(~wRead),
.reset_n(nwReset),
.rxd(uart_rx),
.write_n(~wWrite),
.writedata(bWriteData),
// outputs:
.dataavailable(LEDR[0]),
.irq(LEDR[1]),
.readdata(bReadDataUart),
.readyfordata(LEDR[2]),
.txd(uart_tx)
);
regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata);
ram8kb ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hffffc000) == 0)?wWrite:1'b0, bReadDataRam);
riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData,
regno, regena, regwrdata, regwren, regrddata);
reg [6:0] led0;
reg [6:0] led1;
reg [6:0] led2;
reg [6:0] led3;
reg [6:0] led4;
reg [6:0] led5;
assign HEX0 = ~led0;
assign HEX1 = ~led1;
assign HEX2 = ~led2;
assign HEX3 = ~led3;
assign HEX4 = ~led4;
assign HEX5 = ~led5;
always @(posedge wClk) begin
if (!nwReset) begin
led0 <= 8'h3f;
led1 <= 8'h3f;
led2 <= 8'h3f;
led3 <= 8'h3f;
led4 <= 8'h3f;
led5 <= 8'h3f;
end else begin
if (SW[8]) begin
led0 <= 8'h06;
led1 <= 8'h06;
led2 <= 8'h06;
led3 <= 8'h07;
led4 <= 8'h07;
led5 <= 8'h07;
end
else if (SW[9]) begin
led0 <= 8'h3f;
led1 <= 8'h06;
led2 <= 8'h5b;
led3 <= 8'h4f;
led4 <= 8'h66;
led5 <= 8'h6d;
end
else if (wWrite && ((bWriteAddr & 32'hffffff00) == 32'hf0000000)) begin
if (bWriteAddr[7:0] == 8'h10) begin
led0 <= bWriteData[6:0];
led1 <= bWriteData[14:8];
led2 <= bWriteData[22:16];
led3 <= bWriteData[30:24];
end else if (bWriteAddr[7:0] == 8'h14) begin
led4 <= bWriteData[6:0];
led5 <= bWriteData[14:8];
end
end
end
end
endmodule
examples/hdl4se_riscv/de1/qsys/.qsys_edit/i-qsys.xml 0 → 100644
浏览文件 @ b242c25d
此差异已折叠。
examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml
浏览文件 @ b242c25d
......@@ -14,7 +14,7 @@
<frequency preferredWidth="155" />
</columns>
</clocktable>
<window width="1100" height="800" x="297" y="149" />
<window width="1936" height="1176" x="-8" y="-8" />
<library
expandedCategories="Project,Library/Interface Protocols/Serial,Library/Interface Protocols,Library" />
expandedCategories="Library/Window Bridge,Library/Peripherals/Microcontroller Peripherals,Library/Peripherals,Library/Verification,Library,Project" />
</preferences>
examples/hdl4se_riscv/de1/qsys/i-qsys.bsf 0 → 100644
浏览文件 @ b242c25d
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 496 328)
(text "i-qsys" (rect 231 -1 254 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 312 20 324)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 192 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 192 112)(line_width 1))
)
(port
(pt 0 152)
(input)
(text "vic_0_clk_clk" (rect 0 0 55 12)(font "Arial" (font_size 8)))
(text "vic_0_clk_clk" (rect 4 141 82 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 192 152)(line_width 1))
)
(port
(pt 0 192)
(input)
(text "vic_0_clk_reset_reset" (rect 0 0 90 12)(font "Arial" (font_size 8)))
(text "vic_0_clk_reset_reset" (rect 4 181 130 192)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 192 192)(line_width 1))
)
(port
(pt 0 232)
(input)
(text "vic_0_csr_access_read" (rect 0 0 99 12)(font "Arial" (font_size 8)))
(text "vic_0_csr_access_read" (rect 4 221 130 232)(font "Arial" (font_size 8)))
(line (pt 0 232)(pt 192 232)(line_width 1))
)
(port
(pt 0 248)
(input)
(text "vic_0_csr_access_write" (rect 0 0 99 12)(font "Arial" (font_size 8)))
(text "vic_0_csr_access_write" (rect 4 237 136 248)(font "Arial" (font_size 8)))
(line (pt 0 248)(pt 192 248)(line_width 1))
)
(port
(pt 0 264)
(input)
(text "vic_0_csr_access_address[7..0]" (rect 0 0 133 12)(font "Arial" (font_size 8)))
(text "vic_0_csr_access_address[7..0]" (rect 4 253 184 264)(font "Arial" (font_size 8)))
(line (pt 0 264)(pt 192 264)(line_width 3))
)
(port
(pt 0 280)
(input)
(text "vic_0_csr_access_writedata[31..0]" (rect 0 0 139 12)(font "Arial" (font_size 8)))
(text "vic_0_csr_access_writedata[31..0]" (rect 4 269 202 280)(font "Arial" (font_size 8)))
(line (pt 0 280)(pt 192 280)(line_width 3))
)
(port
(pt 0 296)
(output)
(text "vic_0_csr_access_readdata[31..0]" (rect 0 0 139 12)(font "Arial" (font_size 8)))
(text "vic_0_csr_access_readdata[31..0]" (rect 4 285 196 296)(font "Arial" (font_size 8)))
(line (pt 0 296)(pt 192 296)(line_width 3))
)
(port
(pt 496 72)
(output)
(text "vic_0_interrupt_controller_out_valid" (rect 0 0 142 12)(font "Arial" (font_size 8)))
(text "vic_0_interrupt_controller_out_valid" (rect 317 61 533 72)(font "Arial" (font_size 8)))
(line (pt 496 72)(pt 272 72)(line_width 1))
)
(port
(pt 496 88)
(output)
(text "vic_0_interrupt_controller_out_data[44..0]" (rect 0 0 168 12)(font "Arial" (font_size 8)))
(text "vic_0_interrupt_controller_out_data[44..0]" (rect 288 77 540 88)(font "Arial" (font_size 8)))
(line (pt 496 88)(pt 272 88)(line_width 3))
)
(drawing
(text "clk" (rect 177 43 372 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 197 67 412 144)(font "Arial" (color 0 0 0)))
(text "reset" (rect 163 83 356 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 197 107 436 224)(font "Arial" (color 0 0 0)))
(text "vic_0_clk" (rect 139 123 332 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 197 147 412 304)(font "Arial" (color 0 0 0)))
(text "vic_0_clk_reset" (rect 101 163 292 339)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset" (rect 197 187 424 384)(font "Arial" (color 0 0 0)))
(text "vic_0_csr_access" (rect 89 203 274 419)(font "Arial" (color 128 0 0)(font_size 9)))
(text "read" (rect 197 227 418 464)(font "Arial" (color 0 0 0)))
(text "write" (rect 197 243 424 496)(font "Arial" (color 0 0 0)))
(text "address" (rect 197 259 436 528)(font "Arial" (color 0 0 0)))
(text "writedata" (rect 197 275 448 560)(font "Arial" (color 0 0 0)))
(text "readdata" (rect 197 291 442 592)(font "Arial" (color 0 0 0)))
(text "vic_0_interrupt_controller_out" (rect 273 43 726 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "valid" (rect 249 67 528 144)(font "Arial" (color 0 0 0)))
(text "data" (rect 251 83 526 176)(font "Arial" (color 0 0 0)))
(text " i-qsys " (rect 467 312 982 634)(font "Arial" ))
(line (pt 193 52)(pt 193 76)(line_width 1))
(line (pt 194 52)(pt 194 76)(line_width 1))
(line (pt 193 92)(pt 193 116)(line_width 1))
(line (pt 194 92)(pt 194 116)(line_width 1))
(line (pt 193 132)(pt 193 156)(line_width 1))
(line (pt 194 132)(pt 194 156)(line_width 1))
(line (pt 193 172)(pt 193 196)(line_width 1))
(line (pt 194 172)(pt 194 196)(line_width 1))
(line (pt 193 212)(pt 193 300)(line_width 1))
(line (pt 194 212)(pt 194 300)(line_width 1))
(line (pt 271 52)(pt 271 92)(line_width 1))
(line (pt 270 52)(pt 270 92)(line_width 1))
(line (pt 192 32)(pt 272 32)(line_width 1))
(line (pt 272 32)(pt 272 312)(line_width 1))
(line (pt 192 312)(pt 272 312)(line_width 1))
(line (pt 192 32)(pt 192 312)(line_width 1))
(line (pt 0 0)(pt 496 0)(line_width 1))
(line (pt 496 0)(pt 496 328)(line_width 1))
(line (pt 0 328)(pt 496 328)(line_width 1))
(line (pt 0 0)(pt 0 328)(line_width 1))
)
)
examples/hdl4se_riscv/de1/qsys/i-qsys.html 0 → 100644
浏览文件 @ b242c25d
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>datasheet for i-qsys</title>
<style type="text/css">
body { font-family:arial ;}
a { text-decoration:underline ; color:#003000 ;}
a:hover { text-decoration:underline ; color:0030f0 ;}
td { padding : 5px ;}
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table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
table.blueBar { width : 100% ; border-spacing : 0px ;}
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
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table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
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table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
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table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
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table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
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<body>
<table class="topTitle">
<tr>
<td class="l">i-qsys</td>
<td class="r">
<br/>
<br/>
</td>
</tr>
</table>
<table class="blueBar">
<tr>
<td class="l">2021.08.28.08:45:04</td>
<td class="r">Datasheet</td>
</tr>
</table>
<div style="width:100% ; height:10px"> </div>
<div class="label">Overview</div>
<div class="greydiv">
<div style="display:inline-block ; text-align:left">
<table class="connectionboxes">
<tr>
<td class="lefthandwire">&#160;&#160;clk_0&#160;</td>
<td class="main" rowspan="2">i-qsys</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
</table>
</div><span style="display:inline-block ; width:28px"> </span>
<div style="display:inline-block ; text-align:left"><span>
<br/>All Components
<br/>&#160;&#160;
<a href="#module_vic_0"><b>vic_0</b>
</a> altera_vic 13.1</span>
</div>
</div>
<div style="width:100% ; height:10px"> </div>
<div class="label">Memory Map</div>
<table class="mmap">
<tr>
<td class="empty" rowspan="2"></td>
</tr>
<tr>
<td class="slavemodule">&#160;
<a href="#module_vic_0"><b>vic_0</b>
</a>
</td>
</tr>
<tr>
<td class="slaveb">csr_access&#160;</td>
</tr>
</table>
<a name="module_clk_0"> </a>
<div>
<hr/>
<h2>clk_0</h2>clock_source v13.1
<br/>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">clockFrequency</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">clockFrequencyKnown</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">inputClockFrequency</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">resetSynchronousEdges</td>
<td class="parametervalue">NONE</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>(none)</td>
</tr>
</table>
</div>
<a name="module_vic_0"> </a>
<div>
<hr/>
<h2>vic_0</h2>altera_vic v13.1
<br/>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">NUMBER_OF_INT_PORTS</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">RIL_WIDTH</td>
<td class="parametervalue">4</td>
</tr>
<tr>
<td class="parametername">DAISY_CHAIN_ENABLE</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">AUTO_DEVICE_FAMILY</td>
<td class="parametervalue">CYCLONEV</td>
</tr>
<tr>
<td class="parametername">AUTO_DEVICE</td>
<td class="parametervalue">5CSEMA5F31C6</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">Cyclone V</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>
<table>
<tr>
<td class="parametername">DAISY_CHAIN_ENABLE</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">NUMBER_OF_INT_PORTS</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">RIL_WIDTH</td>
<td class="parametervalue">4</td>
</tr>
</table>
</td>
</tr>
</table>
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0.01 seconds</td>
<td class="r">rendering took 0.02 seconds</td>
</tr>
</table>
</body>
</html>
examples/hdl4se_riscv/de1/qsys/i-qsys.qsys 0 → 100644
浏览文件 @ b242c25d
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="" />
<parameter name="bonusData"><![CDATA[bonusData
{
element clk_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element vic_0
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="5CSEMA5F31C6" />
<parameter name="deviceFamily" value="Cyclone V" />
<parameter name="deviceSpeedGrade" value="6" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
<interface name="vic_0_clk" internal="vic_0.clk" type="clock" dir="end" />
<interface
name="vic_0_clk_reset"
internal="vic_0.clk_reset"
type="reset"
dir="end" />
<interface
name="vic_0_csr_access"
internal="vic_0.csr_access"
type="avalon"
dir="end" />
<interface
name="vic_0_interrupt_controller_out"
internal="vic_0.interrupt_controller_out"
type="avalon_streaming"
dir="start" />
<module kind="clock_source" version="13.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module kind="altera_vic" version="13.1" enabled="1" name="vic_0">
<parameter name="NUMBER_OF_INT_PORTS" value="8" />
<parameter name="RIL_WIDTH" value="4" />
<parameter name="DAISY_CHAIN_ENABLE" value="0" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
<parameter name="AUTO_DEVICE" value="5CSEMA5F31C6" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
</system>
examples/hdl4se_riscv/de1/qsys/i-qsys.sopcinfo 0 → 100644
浏览文件 @ b242c25d
此差异已折叠。
examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.qip 0 → 100644
浏览文件 @ b242c25d
set_global_assignment -entity "i-qsys" -library "i-qsys" -name IP_TOOL_NAME "Qsys"
set_global_assignment -entity "i-qsys" -library "i-qsys" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "i-qsys" -library "i-qsys" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "i-qsys" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../i-qsys.sopcinfo"]
set_global_assignment -entity "i-qsys" -library "i-qsys" -name SLD_INFO "QSYS_NAME i-qsys HAS_SOPCINFO 1 GENERATION_ID 1630111504"
set_global_assignment -library "i-qsys" -name MISC_FILE [file join $::quartus(qip_path) "../../i-qsys.cmp"]
set_global_assignment -library "i-qsys" -name SLD_FILE [file join $::quartus(qip_path) "i-qsys.debuginfo"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "i-qsys" -name MISC_FILE [file join $::quartus(qip_path) "../../i-qsys.qsys"]
set_global_assignment -library "i-qsys" -name VERILOG_FILE [file join $::quartus(qip_path) "i-qsys.v"]
set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/i-qsys_irq_mapper.sv"]
set_global_assignment -library "i-qsys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/i-qsys_vic_0.v"]
set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_vector.sv"]
set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_priority.sv"]
set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_compare2.sv"]
set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_compare4.sv"]
set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_csr.sv"]
set_global_assignment -entity "i-qsys_irq_mapper" -library "i-qsys" -name IP_TOOL_NAME "altera_irq_mapper"
set_global_assignment -entity "i-qsys_irq_mapper" -library "i-qsys" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "i-qsys_irq_mapper" -library "i-qsys" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "i-qsys_vic_0" -library "i-qsys" -name IP_TOOL_NAME "altera_vic"
set_global_assignment -entity "i-qsys_vic_0" -library "i-qsys" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "i-qsys_vic_0" -library "i-qsys" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_vic_vector" -library "i-qsys" -name IP_TOOL_NAME "altera_vic_vector"
set_global_assignment -entity "altera_vic_vector" -library "i-qsys" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_vic_vector" -library "i-qsys" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_vic_priority" -library "i-qsys" -name IP_TOOL_NAME "altera_vic_priority"
set_global_assignment -entity "altera_vic_priority" -library "i-qsys" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_vic_priority" -library "i-qsys" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_vic_csr" -library "i-qsys" -name IP_TOOL_NAME "altera_vic_csr"
set_global_assignment -entity "altera_vic_csr" -library "i-qsys" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_vic_csr" -library "i-qsys" -name IP_TOOL_ENV "Qsys"
examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.v 0 → 100644
浏览文件 @ b242c25d
// i-qsys.v
// Generated using ACDS version 13.1 162 at 2021.08.28.08:45:04
`timescale 1 ps / 1 ps
module i-qsys (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
input wire vic_0_clk_clk, // vic_0_clk.clk
input wire vic_0_clk_reset_reset, // vic_0_clk_reset.reset
input wire vic_0_csr_access_read, // vic_0_csr_access.read
input wire vic_0_csr_access_write, // .write
input wire [7:0] vic_0_csr_access_address, // .address
input wire [31:0] vic_0_csr_access_writedata, // .writedata
output wire [31:0] vic_0_csr_access_readdata, // .readdata
output wire vic_0_interrupt_controller_out_valid, // vic_0_interrupt_controller_out.valid
output wire [44:0] vic_0_interrupt_controller_out_data // .data
);
wire [7:0] vic_0_irq_input_irq; // irq_mapper:sender_irq -> vic_0:irq_input_irq
i-qsys_vic_0 vic_0 (
.clk_clk (vic_0_clk_clk), // clk.clk
.clk_reset_reset (vic_0_clk_reset_reset), // clk_reset.reset
.irq_input_irq (vic_0_irq_input_irq), // irq_input.irq
.csr_access_read (vic_0_csr_access_read), // csr_access.read
.csr_access_write (vic_0_csr_access_write), // .write
.csr_access_address (vic_0_csr_access_address), // .address
.csr_access_writedata (vic_0_csr_access_writedata), // .writedata
.csr_access_readdata (vic_0_csr_access_readdata), // .readdata
.interrupt_controller_out_valid (vic_0_interrupt_controller_out_valid), // interrupt_controller_out.valid
.interrupt_controller_out_data (vic_0_interrupt_controller_out_data) // .data
);
i-qsys_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.sender_irq (vic_0_irq_input_irq) // sender.irq
);
endmodule
examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare2.sv 0 → 100644
浏览文件 @ b242c25d
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ns / 1ns
module altera_vic_compare2 #(parameter PRIORITY_WIDTH = 6,
parameter DATA_WIDTH = 20)
(
input wire int_validA,
input wire [DATA_WIDTH-1:0] int_dataA,
input wire int_validB,
input wire [DATA_WIDTH-1:0] int_dataB,
output reg int_validZ,
output reg [DATA_WIDTH-1:0] int_dataZ,
input wire clk
);
// ********************************************************************
// Module Wiring
wire [PRIORITY_WIDTH:0] LevelA;
wire [PRIORITY_WIDTH:0] LevelB;
reg [PRIORITY_WIDTH+1:0] LevelDiffZ;
// ********************************************************************
// Module Logic - 1st compare stage clocked
assign LevelA = {int_validA, int_dataA[PRIORITY_WIDTH-1:0]};
assign LevelB = {int_validB, int_dataB[PRIORITY_WIDTH-1:0]};
always @(LevelA, LevelB) begin
LevelDiffZ = (LevelA - LevelB);
end
always @(posedge clk) begin
if (LevelDiffZ[PRIORITY_WIDTH+1]) begin
int_validZ <= int_validB;
int_dataZ <= int_dataB;
end
else begin
int_validZ <= int_validA;
int_dataZ <= int_dataA;
end
end
endmodule
examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare4.sv 0 → 100644
浏览文件 @ b242c25d
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ns / 1ns
module altera_vic_compare4 #(parameter PRIORITY_WIDTH = 6,
parameter DATA_WIDTH = 20)
(
input wire int_validA,
input wire [DATA_WIDTH-1:0] int_dataA,
input wire int_validB,
input wire [DATA_WIDTH-1:0] int_dataB,
input wire int_validC,
input wire [DATA_WIDTH-1:0] int_dataC,
input wire int_validD,
input wire [DATA_WIDTH-1:0] int_dataD,
output reg int_validZ,
output reg [DATA_WIDTH-1:0] int_dataZ,
input wire clk
);
// ********************************************************************
// Module Wiring
wire [PRIORITY_WIDTH:0] LevelA;
wire [PRIORITY_WIDTH:0] LevelB;
wire [PRIORITY_WIDTH:0] LevelC;
wire [PRIORITY_WIDTH:0] LevelD;
wire [PRIORITY_WIDTH:0] LevelX;
wire [PRIORITY_WIDTH:0] LevelY;
reg [PRIORITY_WIDTH+1:0] LevelDiffX;
reg [PRIORITY_WIDTH+1:0] LevelDiffY;
reg [PRIORITY_WIDTH+1:0] LevelDiffZ;
reg int_validX;
reg [DATA_WIDTH-1:0] int_dataX;
reg int_validY;
reg [DATA_WIDTH-1:0] int_dataY;
// ********************************************************************
// Module Logic - 1st and 2nd compare stages combinational
assign LevelA = {int_validA, int_dataA[PRIORITY_WIDTH-1:0]};
assign LevelB = {int_validB, int_dataB[PRIORITY_WIDTH-1:0]};
assign LevelC = {int_validC, int_dataC[PRIORITY_WIDTH-1:0]};
assign LevelD = {int_validD, int_dataD[PRIORITY_WIDTH-1:0]};
always @(LevelA, LevelB) begin
LevelDiffX = (LevelA - LevelB);
end
always @(LevelDiffX, int_validA, int_dataA, int_validB, int_dataB) begin
if (LevelDiffX[PRIORITY_WIDTH+1]) begin
int_validX <= int_validB;
int_dataX <= int_dataB;
end
else begin
int_validX <= int_validA;
int_dataX <= int_dataA;
end
end
always @(LevelC, LevelD) begin
LevelDiffY = (LevelC - LevelD);
end
always @(LevelDiffY, int_validC, int_dataC, int_validD, int_dataD) begin
if (LevelDiffY[PRIORITY_WIDTH+1]) begin
int_validY <= int_validD;
int_dataY <= int_dataD;
end
else begin
int_validY <= int_validC;
int_dataY <= int_dataC;
end
end
// ********************************************************************
// Module Logic - 3rd compare stage clocked
assign LevelX = {int_validX, int_dataX[PRIORITY_WIDTH-1:0]};
assign LevelY = {int_validY, int_dataY[PRIORITY_WIDTH-1:0]};
always @(LevelX, LevelY) begin
LevelDiffZ = (LevelX - LevelY);
end
always @(posedge clk) begin
if (LevelDiffZ[PRIORITY_WIDTH+1]) begin
int_validZ <= int_validY;
int_dataZ <= int_dataY;
end
else begin
int_validZ <= int_validX;
int_dataZ <= int_dataX;
end
end
endmodule
examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_priority.sv 0 → 100644
浏览文件 @ b242c25d
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ns / 1ns
module altera_vic_priority #(parameter NUMBER_OF_INT_PORTS = 32,
parameter PRIORITY_WIDTH = 6,
parameter DATA_WIDTH = 19)
(
input wire in0_valid,
input wire [DATA_WIDTH-1:0] in0_data,
input wire in1_valid,
input wire [DATA_WIDTH-1:0] in1_data,
input wire in2_valid,
input wire [DATA_WIDTH-1:0] in2_data,
input wire in3_valid,
input wire [DATA_WIDTH-1:0] in3_data,
input wire in4_valid,
input wire [DATA_WIDTH-1:0] in4_data,
input wire in5_valid,
input wire [DATA_WIDTH-1:0] in5_data,
input wire in6_valid,
input wire [DATA_WIDTH-1:0] in6_data,
input wire in7_valid,
input wire [DATA_WIDTH-1:0] in7_data,
input wire in8_valid,
input wire [DATA_WIDTH-1:0] in8_data,
input wire in9_valid,
input wire [DATA_WIDTH-1:0] in9_data,
input wire in10_valid,
input wire [DATA_WIDTH-1:0] in10_data,
input wire in11_valid,
input wire [DATA_WIDTH-1:0] in11_data,
input wire in12_valid,
input wire [DATA_WIDTH-1:0] in12_data,
input wire in13_valid,
input wire [DATA_WIDTH-1:0] in13_data,
input wire in14_valid,
input wire [DATA_WIDTH-1:0] in14_data,
input wire in15_valid,
input wire [DATA_WIDTH-1:0] in15_data,
input wire in16_valid,
input wire [DATA_WIDTH-1:0] in16_data,
input wire in17_valid,
input wire [DATA_WIDTH-1:0] in17_data,
input wire in18_valid,
input wire [DATA_WIDTH-1:0] in18_data,
input wire in19_valid,
input wire [DATA_WIDTH-1:0] in19_data,
input wire in20_valid,
input wire [DATA_WIDTH-1:0] in20_data,
input wire in21_valid,
input wire [DATA_WIDTH-1:0] in21_data,
input wire in22_valid,
input wire [DATA_WIDTH-1:0] in22_data,
input wire in23_valid,
input wire [DATA_WIDTH-1:0] in23_data,
input wire in24_valid,
input wire [DATA_WIDTH-1:0] in24_data,
input wire in25_valid,
input wire [DATA_WIDTH-1:0] in25_data,
input wire in26_valid,
input wire [DATA_WIDTH-1:0] in26_data,
input wire in27_valid,
input wire [DATA_WIDTH-1:0] in27_data,
input wire in28_valid,
input wire [DATA_WIDTH-1:0] in28_data,
input wire in29_valid,
input wire [DATA_WIDTH-1:0] in29_data,
input wire in30_valid,
input wire [DATA_WIDTH-1:0] in30_data,
input wire in31_valid,
input wire [DATA_WIDTH-1:0] in31_data,
input wire in32_valid,
input wire [DATA_WIDTH-1:0] in32_data,
output wire pri_valid,
output wire [DATA_WIDTH-1:0] pri_data,
input wire reset_n,
input wire clk
);
// ********************************************************************
// Module Wiring
wire cmp_valid_A0;
wire [DATA_WIDTH-1:0] cmp_data_A0;
wire cmp_valid_A1;
wire [DATA_WIDTH-1:0] cmp_data_A1;
wire cmp_valid_A2;
wire [DATA_WIDTH-1:0] cmp_data_A2;
wire cmp_valid_A3;
wire [DATA_WIDTH-1:0] cmp_data_A3;
wire cmp_valid_A4;
wire [DATA_WIDTH-1:0] cmp_data_A4;
wire cmp_valid_A5;
wire [DATA_WIDTH-1:0] cmp_data_A5;
wire cmp_valid_A6;
wire [DATA_WIDTH-1:0] cmp_data_A6;
wire cmp_valid_A7;
wire [DATA_WIDTH-1:0] cmp_data_A7;
wire cmp_valid_A8;
wire [DATA_WIDTH-1:0] cmp_data_A8;
wire cmp_valid_B0;
wire [DATA_WIDTH-1:0] cmp_data_B0;
wire cmp_valid_B1;
wire [DATA_WIDTH-1:0] cmp_data_B1;
wire cmp_valid_B2;
wire [DATA_WIDTH-1:0] cmp_data_B2;
// ********************************************************************
// Module Logic
generate
case (NUMBER_OF_INT_PORTS)
1: begin : port1
assign pri_valid = in0_valid;
assign pri_data = in0_data;
end
2, 3, 4: begin : port2_4
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0
(in0_valid, in0_data, in1_valid, in1_data,
in2_valid, in2_data, in3_valid, in3_data,
pri_valid, pri_data, clk);
end
5, 6, 7, 8: begin : port5_8
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0
(in0_valid, in0_data, in1_valid, in1_data,
in2_valid, in2_data, in3_valid, in3_data,
cmp_valid_A0, cmp_data_A0, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A1
(in4_valid, in4_data, in5_valid, in5_data,
in6_valid, in6_data, in7_valid, in7_data,
cmp_valid_A1, cmp_data_A1, clk);
altera_vic_compare2 #(PRIORITY_WIDTH, DATA_WIDTH) B0
(cmp_valid_A0, cmp_data_A0, cmp_valid_A1, cmp_data_A1,
pri_valid, pri_data, clk);
end
9, 10, 11, 12, 13, 14, 15, 16: begin : port9_16
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0
(in0_valid, in0_data, in1_valid, in1_data,
in2_valid, in2_data, in3_valid, in3_data,
cmp_valid_A0, cmp_data_A0, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A1
(in4_valid, in4_data, in5_valid, in5_data,
in6_valid, in6_data, in7_valid, in7_data,
cmp_valid_A1, cmp_data_A1, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A2
(in8_valid, in8_data, in9_valid, in9_data,
in10_valid, in10_data, in11_valid, in11_data,
cmp_valid_A2, cmp_data_A2, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A3
(in12_valid, in12_data, in13_valid, in13_data,
in14_valid, in14_data, in15_valid, in15_data,
cmp_valid_A3, cmp_data_A3, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B0
(cmp_valid_A0, cmp_data_A0, cmp_valid_A1, cmp_data_A1,
cmp_valid_A2, cmp_data_A2, cmp_valid_A3, cmp_data_A3,
pri_valid, pri_data, clk);
end
17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32: begin : port17_32
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0
(in0_valid, in0_data, in1_valid, in1_data,
in2_valid, in2_data, in3_valid, in3_data,
cmp_valid_A0, cmp_data_A0, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A1
(in4_valid, in4_data, in5_valid, in5_data,
in6_valid, in6_data, in7_valid, in7_data,
cmp_valid_A1, cmp_data_A1, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A2
(in8_valid, in8_data, in9_valid, in9_data,
in10_valid, in10_data, in11_valid, in11_data,
cmp_valid_A2, cmp_data_A2, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A3
(in12_valid, in12_data, in13_valid, in13_data,
in14_valid, in14_data, in15_valid, in15_data,
cmp_valid_A3, cmp_data_A3, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A4
(in16_valid, in16_data, in17_valid, in17_data,
in18_valid, in18_data, in19_valid, in19_data,
cmp_valid_A4, cmp_data_A4, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A5
(in20_valid, in20_data, in21_valid, in21_data,
in22_valid, in22_data, in23_valid, in23_data,
cmp_valid_A5, cmp_data_A5, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A6
(in24_valid, in24_data, in25_valid, in25_data,
in26_valid, in26_data, in27_valid, in27_data,
cmp_valid_A6, cmp_data_A6, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A7
(in28_valid, in28_data, in29_valid, in29_data,
in30_valid, in30_data, in31_valid, in31_data,
cmp_valid_A7, cmp_data_A7, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B0
(cmp_valid_A0, cmp_data_A0, cmp_valid_A1, cmp_data_A1,
cmp_valid_A2, cmp_data_A2, cmp_valid_A3, cmp_data_A3,
cmp_valid_B0, cmp_data_B0, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B1
(cmp_valid_A4, cmp_data_A4, cmp_valid_A5, cmp_data_A5,
cmp_valid_A6, cmp_data_A6, cmp_valid_A7, cmp_data_A7,
cmp_valid_B1, cmp_data_B1, clk);
altera_vic_compare2 #(PRIORITY_WIDTH, DATA_WIDTH) C0
(cmp_valid_B0, cmp_data_B0, cmp_valid_B1, cmp_data_B1,
pri_valid, pri_data, clk);
end
default: begin : port33
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0
(in0_valid, in0_data, in1_valid, in1_data,
in2_valid, in2_data, in3_valid, in3_data,
cmp_valid_A0, cmp_data_A0, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A1
(in4_valid, in4_data, in5_valid, in5_data,
in6_valid, in6_data, in7_valid, in7_data,
cmp_valid_A1, cmp_data_A1, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A2
(in8_valid, in8_data, in9_valid, in9_data,
in10_valid, in10_data, in11_valid, in11_data,
cmp_valid_A2, cmp_data_A2, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A3
(in12_valid, in12_data, in13_valid, in13_data,
in14_valid, in14_data, in15_valid, in15_data,
cmp_valid_A3, cmp_data_A3, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A4
(in16_valid, in16_data, in17_valid, in17_data,
in18_valid, in18_data, in19_valid, in19_data,
cmp_valid_A4, cmp_data_A4, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A5
(in20_valid, in20_data, in21_valid, in21_data,
in22_valid, in22_data, in23_valid, in23_data,
cmp_valid_A5, cmp_data_A5, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A6
(in24_valid, in24_data, in25_valid, in25_data,
in26_valid, in26_data, in27_valid, in27_data,
cmp_valid_A6, cmp_data_A6, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A7
(in28_valid, in28_data, in29_valid, in29_data,
in30_valid, in30_data, in31_valid, in31_data,
cmp_valid_A7, cmp_data_A7, clk);
altera_vic_compare2 #(PRIORITY_WIDTH, DATA_WIDTH) A8
(in32_valid, in32_data, 1'b0, {DATA_WIDTH{1'b0}},
cmp_valid_A8, cmp_data_A8, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B0
(cmp_valid_A0, cmp_data_A0, cmp_valid_A1, cmp_data_A1,
cmp_valid_A2, cmp_data_A2, cmp_valid_A3, cmp_data_A3,
cmp_valid_B0, cmp_data_B0, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B1
(cmp_valid_A4, cmp_data_A4, cmp_valid_A5, cmp_data_A5,
cmp_valid_A6, cmp_data_A6, cmp_valid_A7, cmp_data_A7,
cmp_valid_B1, cmp_data_B1, clk);
altera_vic_compare2 #(PRIORITY_WIDTH, DATA_WIDTH) B2
(cmp_valid_A8, cmp_data_A8, 1'b0, {DATA_WIDTH{1'b0}},
cmp_valid_B2, cmp_data_B2, clk);
altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) C0
(cmp_valid_B0, cmp_data_B0, cmp_valid_B1, cmp_data_B1,
cmp_valid_B2, cmp_data_B2, 1'b0, {DATA_WIDTH{1'b0}},
pri_valid, pri_data, clk);
end
endcase
endgenerate
endmodule
examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_vector.sv 0 → 100644
浏览文件 @ b242c25d
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ns / 1ns
module altera_vic_vector #(parameter DAISY_CHAIN_ENABLE = 0)
(
output reg out_valid,
output reg [44:0] out_data,
output reg status_valid,
output reg [37:0] status_data,
input wire control_valid,
input wire [34:0] control_data,
input wire dc_valid,
input wire [31:0] dc_data,
input wire in_valid,
input wire [18:0] in_data,
input wire reset_n,
input wire clk
);
// ********************************************************************
// Module Wiring
wire InValid;
wire [5:0] InPortId;
wire [12:0] InConfig;
wire OutValid;
reg [5:0] OutPortId;
reg [12:0] OutConfig;
reg [2:0] VecSize;
reg [31:0] VecBaseAddr;
reg [13:0] VecOffset;
reg [31:0] VecHandAddr;
reg [31:0] DcRhaValue;
// ********************************************************************
// Module Logic
assign InValid = in_valid;
assign InPortId = in_data[18:13];
assign InConfig = in_data[12:0];
assign OutValid = InValid;
always @(posedge clk) begin
if (control_valid) begin
VecSize <= control_data[34:32];
VecBaseAddr <= control_data[31:0];
end
end
always @(posedge clk) begin
status_valid <= OutValid;
status_data <= {OutPortId, VecHandAddr};
end
always @(VecSize, InPortId) begin
case (VecSize)
3'b000: VecOffset <= {7'b0, InPortId[4:0], 2'b0};
3'b001: VecOffset <= {6'b0, InPortId[4:0], 3'b0};
3'b010: VecOffset <= {5'b0, InPortId[4:0], 4'b0};
3'b011: VecOffset <= {4'b0, InPortId[4:0], 5'b0};
3'b100: VecOffset <= {3'b0, InPortId[4:0], 6'b0};
3'b101: VecOffset <= {2'b0, InPortId[4:0], 7'b0};
3'b110: VecOffset <= {1'b0, InPortId[4:0], 8'b0};
3'b111: VecOffset <= {InPortId[4:0], 9'b0};
endcase
end
always @(dc_valid, dc_data) begin
if (dc_valid)
DcRhaValue <= dc_data;
else
DcRhaValue <= 32'h00000000;
end
always @(InValid, InPortId, DcRhaValue, VecBaseAddr, VecOffset) begin
if (InValid & InPortId[5])
VecHandAddr <= DcRhaValue;
else if (InValid & ~InPortId[5])
VecHandAddr <= VecBaseAddr + VecOffset;
else
VecHandAddr <= 32'h00000000;
end
always @(InValid, InPortId) begin
if (InValid)
OutPortId <= InPortId;
else
OutPortId <= 6'h00;
end
always @(InValid, InConfig) begin
if (InValid)
OutConfig <= InConfig;
else
OutConfig <= 13'h0000;
end
always @(posedge clk) begin
out_valid <= 1'b1;
out_data <= {VecHandAddr, OutConfig};
end
endmodule
examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_irq_mapper.sv 0 → 100644
浏览文件 @ b242c25d
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/13.1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $
// $Revision: #1 $
// $Date: 2013/08/11 $
// $Author: swbranch $
// -------------------------------------------------------
// Altera IRQ Mapper
//
// Parameters
// NUM_RCVRS : 0
// SENDER_IRW_WIDTH : 8
// IRQ_MAP :
//
// -------------------------------------------------------
`timescale 1 ns / 1 ns
module i-qsys_irq_mapper
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
// -------------------
// Command Source (Output)
// -------------------
output reg [7 : 0] sender_irq
);
initial sender_irq = 0;
always @* begin
sender_irq = 0;
end
endmodule
examples/hdl4se_riscv/test_code/main_v2.c 0 → 100644
浏览文件 @ b242c25d
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