From b242c25dd22a6f856a0e3c315fe87cf2006facc1 Mon Sep 17 00:00:00 2001 From: m0_56903617 Date: Sat, 28 Aug 2021 11:02:55 +0800 Subject: [PATCH] 202108281102 --- examples/hdl4se_riscv/de1/clk/clk100M.v | 4 +- .../de1/clk/clk100M/clk100M_0002.v | 2 +- .../clk100M_sim/aldec/rivierapro_setup.tcl | 2 +- .../clk/clk100M_sim/cadence/ncsim_setup.sh | 2 +- .../de1/clk/clk100M_sim/clk100M.vo | 2 +- .../de1/clk/clk100M_sim/mentor/msim_setup.tcl | 2 +- .../clk/clk100M_sim/synopsys/vcs/vcs_setup.sh | 2 +- .../clk100M_sim/synopsys/vcsmx/vcsmx_setup.sh | 2 +- examples/hdl4se_riscv/de1/clk100M.xml | 2 +- examples/hdl4se_riscv/de1/de1_risc.mpf | 6 +- examples/hdl4se_riscv/de1/de1_riscv.asm.rpt | 12 +- examples/hdl4se_riscv/de1/de1_riscv.done | 2 +- examples/hdl4se_riscv/de1/de1_riscv.fit.rpt | 2023 +++++++++-------- .../hdl4se_riscv/de1/de1_riscv.fit.summary | 6 +- examples/hdl4se_riscv/de1/de1_riscv.flow.rpt | 61 +- examples/hdl4se_riscv/de1/de1_riscv.jdi | 2 +- examples/hdl4se_riscv/de1/de1_riscv.map.rpt | 1297 ++++++----- .../hdl4se_riscv/de1/de1_riscv.map.summary | 4 +- examples/hdl4se_riscv/de1/de1_riscv.qsf | 1 + examples/hdl4se_riscv/de1/de1_riscv.qws | Bin 1034 -> 0 bytes examples/hdl4se_riscv/de1/de1_riscv.sof | Bin 6690262 -> 0 bytes examples/hdl4se_riscv/de1/de1_riscv.sta.rpt | 1959 +++++++++------- .../hdl4se_riscv/de1/de1_riscv.sta.summary | 26 +- examples/hdl4se_riscv/de1/de1_riscv_v2.v | 235 ++ .../de1/qsys/.qsys_edit/i-qsys.xml | 1848 +++++++++++++++ .../de1/qsys/.qsys_edit/preferences.xml | 4 +- examples/hdl4se_riscv/de1/qsys/i-qsys.bsf | 143 ++ examples/hdl4se_riscv/de1/qsys/i-qsys.cmp | 0 examples/hdl4se_riscv/de1/qsys/i-qsys.html | 231 ++ examples/hdl4se_riscv/de1/qsys/i-qsys.qsys | 80 + .../hdl4se_riscv/de1/qsys/i-qsys.sopcinfo | 1206 ++++++++++ .../qsys/i-qsys/synthesis/i-qsys.debuginfo | 1503 ++++++++++++ .../de1/qsys/i-qsys/synthesis/i-qsys.qip | 34 + .../de1/qsys/i-qsys/synthesis/i-qsys.v | 41 + .../submodules/altera_vic_compare2.sv | 65 + .../submodules/altera_vic_compare4.sv | 128 ++ .../synthesis/submodules/altera_vic_csr.sv | 800 +++++++ .../submodules/altera_vic_priority.sv | 351 +++ .../synthesis/submodules/altera_vic_vector.sv | 136 ++ .../synthesis/submodules/i-qsys_irq_mapper.sv | 58 + .../synthesis/submodules/i-qsys_vic_0.v | 229 ++ examples/hdl4se_riscv/de1/vsim.wlf | Bin 1155072 -> 1155072 bytes examples/hdl4se_riscv/test_code/main_v2.c | 74 + 43 files changed, 10135 insertions(+), 2450 deletions(-) delete mode 100644 examples/hdl4se_riscv/de1/de1_riscv.qws delete mode 100644 examples/hdl4se_riscv/de1/de1_riscv.sof create mode 100644 examples/hdl4se_riscv/de1/de1_riscv_v2.v create mode 100644 examples/hdl4se_riscv/de1/qsys/.qsys_edit/i-qsys.xml create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys.bsf create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys.cmp create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys.html create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys.qsys create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys.sopcinfo create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.debuginfo create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.qip create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.v create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare2.sv create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare4.sv create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_csr.sv create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_priority.sv create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_vector.sv create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_irq_mapper.sv create mode 100644 examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_vic_0.v create mode 100644 examples/hdl4se_riscv/test_code/main_v2.c diff --git a/examples/hdl4se_riscv/de1/clk/clk100M.v b/examples/hdl4se_riscv/de1/clk/clk100M.v index 95ee73a..2b51bd6 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M.v +++ b/examples/hdl4se_riscv/de1/clk/clk100M.v @@ -2,7 +2,7 @@ // GENERATION: XML // clk100M.v -// Generated using ACDS version 13.1 162 at 2021.08.27.17:20:30 +// Generated using ACDS version 13.1 162 at 2021.08.28.11:01:41 `timescale 1 ps / 1 ps module clk100M ( @@ -68,7 +68,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: diff --git a/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v b/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v index b3c9099..7338770 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v +++ b/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v @@ -22,7 +22,7 @@ module clk100M_0002( .reference_clock_frequency("50.0 MHz"), .operation_mode("direct"), .number_of_clocks(2), - .output_clock_frequency0("100.000000 MHz"), + .output_clock_frequency0("50.000000 MHz"), .phase_shift0("0 ps"), .duty_cycle0(50), .output_clock_frequency1("75.000000 MHz"), diff --git a/examples/hdl4se_riscv/de1/clk/clk100M_sim/aldec/rivierapro_setup.tcl b/examples/hdl4se_riscv/de1/clk/clk100M_sim/aldec/rivierapro_setup.tcl index 892bc36..ec50b3d 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M_sim/aldec/rivierapro_setup.tcl +++ b/examples/hdl4se_riscv/de1/clk/clk100M_sim/aldec/rivierapro_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 13.1 162 win32 2021.08.27.17:20:37 +# ACDS 13.1 162 win32 2021.08.28.11:01:49 # ---------------------------------------- # Auto-generated simulation script diff --git a/examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/ncsim_setup.sh b/examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/ncsim_setup.sh index 3c004a3..fc0f9bf 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/ncsim_setup.sh +++ b/examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/ncsim_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 13.1 162 win32 2021.08.27.17:20:37 +# ACDS 13.1 162 win32 2021.08.28.11:01:49 # ---------------------------------------- # ncsim - auto-generated simulation script diff --git a/examples/hdl4se_riscv/de1/clk/clk100M_sim/clk100M.vo b/examples/hdl4se_riscv/de1/clk/clk100M_sim/clk100M.vo index 6a8e7f8..9bd4953 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M_sim/clk100M.vo +++ b/examples/hdl4se_riscv/de1/clk/clk100M_sim/clk100M.vo @@ -210,7 +210,7 @@ module clk100M clk100m_altera_pll_altera_pll_i_1096.n_cnt_odd_div_duty_en = "false", clk100m_altera_pll_altera_pll_i_1096.number_of_clocks = 2, clk100m_altera_pll_altera_pll_i_1096.operation_mode = "direct", - clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency0 = "100.000000 MHz", + clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency0 = "50.000000 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency1 = "75.000000 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency10 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency11 = "0 MHz", diff --git a/examples/hdl4se_riscv/de1/clk/clk100M_sim/mentor/msim_setup.tcl b/examples/hdl4se_riscv/de1/clk/clk100M_sim/mentor/msim_setup.tcl index e81810a..c9072ba 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M_sim/mentor/msim_setup.tcl +++ b/examples/hdl4se_riscv/de1/clk/clk100M_sim/mentor/msim_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 13.1 162 win32 2021.08.27.17:20:37 +# ACDS 13.1 162 win32 2021.08.28.11:01:49 # ---------------------------------------- # Auto-generated simulation script diff --git a/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcs/vcs_setup.sh b/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcs/vcs_setup.sh index 30d306c..7a7d545 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcs/vcs_setup.sh +++ b/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcs/vcs_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 13.1 162 win32 2021.08.27.17:20:37 +# ACDS 13.1 162 win32 2021.08.28.11:01:49 # ---------------------------------------- # vcs - auto-generated simulation script diff --git a/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/vcsmx_setup.sh b/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/vcsmx_setup.sh index 63a581e..9d9eb23 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/vcsmx_setup.sh +++ b/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 13.1 162 win32 2021.08.27.17:20:37 +# ACDS 13.1 162 win32 2021.08.28.11:01:49 # ---------------------------------------- # vcsmx - auto-generated simulation script diff --git a/examples/hdl4se_riscv/de1/clk100M.xml b/examples/hdl4se_riscv/de1/clk100M.xml index 3af333a..cdabb27 100644 --- a/examples/hdl4se_riscv/de1/clk100M.xml +++ b/examples/hdl4se_riscv/de1/clk100M.xml @@ -19,7 +19,7 @@ - + diff --git a/examples/hdl4se_riscv/de1/de1_risc.mpf b/examples/hdl4se_riscv/de1/de1_risc.mpf index 137f8b6..d8edd20 100644 --- a/examples/hdl4se_riscv/de1/de1_risc.mpf +++ b/examples/hdl4se_riscv/de1/de1_risc.mpf @@ -454,7 +454,7 @@ Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 co Project_File_1 = C:/altera/13.1/quartus/eda/sim_lib/220model.v Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1382637203 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_2 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v -Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1630049086 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1630049086 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_3 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/suber.v Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629969062 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_4 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult.v @@ -470,9 +470,9 @@ Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 co Project_File_9 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1630042952 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_10 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.v -Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1630053824 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1630053824 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_11 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M.v -Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1630049096 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1630049096 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_12 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629969030 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_13 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v diff --git a/examples/hdl4se_riscv/de1/de1_riscv.asm.rpt b/examples/hdl4se_riscv/de1/de1_riscv.asm.rpt index 7763d3e..5605124 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.asm.rpt +++ b/examples/hdl4se_riscv/de1/de1_riscv.asm.rpt @@ -1,5 +1,5 @@ Assembler report for de1_riscv -Fri Aug 27 17:23:28 2021 +Sat Aug 28 10:56:11 2021 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Fri Aug 27 17:23:28 2021 ; +; Assembler Status ; Successful - Sat Aug 28 10:56:11 2021 ; ; Revision Name ; de1_riscv ; ; Top-level Entity Name ; de1_riscv ; ; Family ; Cyclone V ; @@ -92,8 +92,8 @@ applicable agreement for further details. ; Option ; Setting ; +----------------+--------------------------------------------------------------------+ ; Device ; 5CSEMA5F31C6 ; -; JTAG usercode ; 0x0122624D ; -; Checksum ; 0x0122624D ; +; JTAG usercode ; 0x0122B7FD ; +; Checksum ; 0x0122B7FD ; +----------------+--------------------------------------------------------------------+ @@ -103,12 +103,12 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 64-Bit Assembler Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version - Info: Processing started: Fri Aug 27 17:23:13 2021 + Info: Processing started: Sat Aug 28 10:55:56 2021 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv Info (115030): Assembler is generating device programming files Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 661 megabytes - Info: Processing ended: Fri Aug 27 17:23:28 2021 + Info: Processing ended: Sat Aug 28 10:56:11 2021 Info: Elapsed time: 00:00:15 Info: Total CPU time (on all processors): 00:00:15 diff --git a/examples/hdl4se_riscv/de1/de1_riscv.done b/examples/hdl4se_riscv/de1/de1_riscv.done index d673dd5..dde8582 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.done +++ b/examples/hdl4se_riscv/de1/de1_riscv.done @@ -1 +1 @@ -Fri Aug 27 17:24:02 2021 +Sat Aug 28 10:56:46 2021 diff --git a/examples/hdl4se_riscv/de1/de1_riscv.fit.rpt b/examples/hdl4se_riscv/de1/de1_riscv.fit.rpt index c3b26cd..563bfb1 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.fit.rpt +++ b/examples/hdl4se_riscv/de1/de1_riscv.fit.rpt @@ -1,5 +1,5 @@ Fitter report for de1_riscv -Fri Aug 27 17:23:09 2021 +Sat Aug 28 10:55:52 2021 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -67,15 +67,15 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+---------------------------------------------+ -; Fitter Status ; Successful - Fri Aug 27 17:23:08 2021 ; +; Fitter Status ; Successful - Sat Aug 28 10:55:51 2021 ; ; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ; ; Revision Name ; de1_riscv ; ; Top-level Entity Name ; de1_riscv ; ; Family ; Cyclone V ; ; Device ; 5CSEMA5F31C6 ; ; Timing Models ; Preliminary ; -; Logic utilization (in ALMs) ; 2,468 / 32,070 ( 8 % ) ; -; Total registers ; 1833 ; +; Logic utilization (in ALMs) ; 2,494 / 32,070 ( 8 % ) ; +; Total registers ; 1863 ; ; Total pins ; 204 / 457 ( 45 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 66,560 / 4,065,280 ( 2 % ) ; @@ -154,12 +154,12 @@ applicable agreement for further details. ; Number detected on machine ; 4 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.37 ; +; Average used ; 1.41 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 37.2% ; +; Processor 2 ; 41.2% ; ; Processors 3-4 ; 0.0% ; +----------------------------+-------------+ @@ -310,9 +310,7 @@ applicable agreement for further details. ; GPIO[2] ; Missing drive strength and slew rate ; ; GPIO[3] ; Missing drive strength and slew rate ; ; GPIO[4] ; Missing drive strength and slew rate ; -; GPIO[5] ; Missing drive strength and slew rate ; ; GPIO[6] ; Missing drive strength and slew rate ; -; GPIO[7] ; Missing drive strength and slew rate ; ; GPIO[8] ; Missing drive strength and slew rate ; ; GPIO[9] ; Missing drive strength and slew rate ; ; GPIO[10] ; Missing drive strength and slew rate ; @@ -341,6 +339,8 @@ applicable agreement for further details. ; GPIO[33] ; Missing drive strength and slew rate ; ; GPIO[34] ; Missing drive strength and slew rate ; ; GPIO[35] ; Missing drive strength and slew rate ; +; GPIO[5] ; Missing drive strength and slew rate ; +; GPIO[7] ; Missing drive strength and slew rate ; +---------------+--------------------------------------+ @@ -1118,199 +1118,201 @@ applicable agreement for further details. ; riscv_core:core|rs2[31]~_Duplicate_4 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; riscv_core:core|rs2[31]~_Duplicate_5 ; Q ; ; ; riscv_core:core|rs2[31]~_Duplicate_5 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated|Mult0~781 ; AY ; ; ; riscv_core:core|rs2[31]~_Duplicate_5 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; riscv_core:core|rs2[31]~_Duplicate_6 ; Q ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[28] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[28]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[54] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[54]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[59] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[59]~DUPLICATE ; ; ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[24] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[24]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[47] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[47]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[50] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[50]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[52] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[52]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[53] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[53]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[56] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[56]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[58] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[58]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[60] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[60]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[75] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[75]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[79] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[79]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[83] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[83]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[90] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[90]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[91] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[91]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[92] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[92]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[93] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[93]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[96] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[96]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[101] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[101]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[123] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[123]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[143] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[143]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[146] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[146]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[147] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[147]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[150] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[150]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[102] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[102]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[104] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[104]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[108] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[108]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[136] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[136]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[142] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[142]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[151] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[151]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[156] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[156]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[157] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[157]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[179] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[179]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[186] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[186]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[161] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[161]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[162] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[162]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[163] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[163]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[164] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[164]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[165] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[165]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[166] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[166]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[167] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[167]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[169] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[169]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[174] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[174]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[178] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[178]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[188] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[188]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[190] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[190]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[213] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[213]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[216] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[216]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[247] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[247]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[257] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[257]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[282] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[282]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[283] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[283]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[290] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[290]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[291] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[291]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[292] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[292]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[308] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[308]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[349] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[349]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[352] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[352]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[284] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[284]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[310] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[310]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[70] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[70]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[128] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[128]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[129] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[129]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[132] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[132]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[133] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[133]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[139] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[139]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[161] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[161]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[163] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[163]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[167] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[167]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[168] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[168]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[172] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[172]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[225] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[225]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[226] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[226]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[160] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[160]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[170] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[170]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[192] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[192]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[196] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[196]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[204] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[204]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[205] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[205]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[227] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[227]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[229] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[229]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[230] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[230]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[231] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[231]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[239] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[239]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[242] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[242]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[243] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[243]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[266] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[266]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[267] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[267]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[271] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[271]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[256] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[256]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[259] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[259]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[261] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[261]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[265] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[265]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[274] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[274]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[278] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[278]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[289] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[289]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[275] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[275]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[277] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[277]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[320] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[320]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[321] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[321]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[322] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[322]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[324] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[324]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[326] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[326]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[327] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[327]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[328] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[328]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[329] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[329]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[330] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[330]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[333] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[333]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[334] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[334]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[335] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[335]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[336] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[336]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[337] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[337]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[338] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[338]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[339] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[339]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[342] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[342]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[343] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[343]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[346] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[346]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[361] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[361]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[363] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[363]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[364] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[364]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[365] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[365]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[370] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[370]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[46] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[46]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[51] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[51]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[54] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[54]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[72] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[72]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[74] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[74]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[84] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[84]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[85] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[85]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[108] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[108]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[113] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[113]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[114] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[114]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[143] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[143]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[151] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[151]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[158] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[158]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[323] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[323]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[325] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[325]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[344] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[344]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[347] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[347]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[67] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[67]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[70] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[70]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[73] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[73]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[107] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[107]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[118] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[118]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[119] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[119]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[120] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[120]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[146] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[146]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[147] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[147]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[180] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[180]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[183] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[183]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[190] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[190]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[250] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[250]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[256] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[256]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[281] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[281]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[282] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[282]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[184] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[184]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[189] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[189]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[213] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[213]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[215] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[215]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[216] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[216]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[217] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[217]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[257] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[257]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[283] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[283]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[287] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[287]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[364] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[364]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[382] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[382]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[289] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[289]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[290] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[290]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[304] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[304]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[306] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[306]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[316] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[316]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[318] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[318]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[350] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[350]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[354] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[354]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[356] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[356]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[362] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[362]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[367] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[367]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[368] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[368]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[369] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[369]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[370] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[370]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[383] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[383]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[57] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[57]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[64] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[64]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[65] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[65]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[66] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[66]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[67] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[67]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[70] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[70]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[103] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[103]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[105] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[105]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[128] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[128]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[131] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[131]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[137] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[137]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[129] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[129]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[138] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[138]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[139] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[139]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[160] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[160]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[163] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[163]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[169] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[169]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[170] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[170]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[174] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[174]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[224] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[224]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[225] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[225]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[230] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[230]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[226] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[226]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[227] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[227]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[228] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[228]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[231] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[231]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[232] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[232]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[236] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[236]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[237] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[237]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[238] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[238]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[239] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[239]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[240] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[240]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[243] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[243]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[256] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[256]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[258] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[258]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[259] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[259]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[260] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[260]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[261] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[261]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[241] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[241]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[242] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[242]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[257] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[257]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[263] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[263]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[264] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[264]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[265] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[265]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[268] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[268]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[269] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[269]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[270] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[270]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[271] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[271]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[272] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[272]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[273] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[273]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[274] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[274]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[275] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[275]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[276] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[276]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[278] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[278]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[288] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[288]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[289] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[289]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[292] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[292]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[305] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[305]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[320] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[320]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[321] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[321]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[322] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[322]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[323] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[323]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[325] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[325]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[326] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[326]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[327] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[327]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[329] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[329]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[330] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[330]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[331] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[331]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[332] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[332]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[333] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[333]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[335] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[335]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[336] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[336]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[338] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[338]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[339] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[339]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[340] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[340]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[341] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[341]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[343] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[343]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[359] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[359]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[361] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[361]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[380] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[380]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[346] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[346]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[352] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[352]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[354] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[354]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[362] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[362]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; -; riscv_core:core|dstreg[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|dstreg[1]~DUPLICATE ; ; ; -; riscv_core:core|imm[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[1]~DUPLICATE ; ; ; -; riscv_core:core|imm[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[3]~DUPLICATE ; ; ; -; riscv_core:core|imm[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[13]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ; +; riscv_core:core|imm[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[2]~DUPLICATE ; ; ; +; riscv_core:core|imm[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[5]~DUPLICATE ; ; ; +; riscv_core:core|imm[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[12]~DUPLICATE ; ; ; +; riscv_core:core|imm[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[14]~DUPLICATE ; ; ; +; riscv_core:core|imm[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[15]~DUPLICATE ; ; ; +; riscv_core:core|imm[16] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[16]~DUPLICATE ; ; ; +; riscv_core:core|imm[17] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[17]~DUPLICATE ; ; ; +; riscv_core:core|imm[18] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[18]~DUPLICATE ; ; ; ; riscv_core:core|imm[22] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[22]~DUPLICATE ; ; ; ; riscv_core:core|imm[25] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[25]~DUPLICATE ; ; ; -; riscv_core:core|instr[20] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|instr[20]~DUPLICATE ; ; ; -; riscv_core:core|instr[23] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|instr[23]~DUPLICATE ; ; ; -; riscv_core:core|instr[24] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|instr[24]~DUPLICATE ; ; ; -; riscv_core:core|rs1[3]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[3]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs1[5]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[5]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs1[8]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[8]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|imm[31] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[31]~DUPLICATE ; ; ; +; riscv_core:core|ldaddr[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|ldaddr[0]~DUPLICATE ; ; ; +; riscv_core:core|ldaddr[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|ldaddr[1]~DUPLICATE ; ; ; ; riscv_core:core|rs1[9]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[9]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs1[10]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[10]~_Duplicate_6DUPLICATE ; ; ; ; riscv_core:core|rs1[19]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[19]~_Duplicate_6DUPLICATE ; ; ; ; riscv_core:core|rs1[28]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[28]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs1[29]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[29]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs1[31]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[31]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[0]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[0]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[1]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[1]~_Duplicate_6DUPLICATE ; ; ; ; riscv_core:core|rs2[3]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[3]~_Duplicate_6DUPLICATE ; ; ; ; riscv_core:core|rs2[4]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[4]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs2[5]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[5]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs2[11]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[11]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[7]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[7]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[10]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[10]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[13]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[13]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[17]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[17]~_Duplicate_6DUPLICATE ; ; ; ; riscv_core:core|rs2[18]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[18]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs2[30]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[30]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[28]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[28]~_Duplicate_6DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg0FITTER_CREATED_FF ; Created ; Placement ; Location assignment ; Q ; ; ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg1FITTER_CREATED_FF ; Created ; Placement ; Location assignment ; Q ; ; ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg2FITTER_CREATED_FF ; Created ; Placement ; Location assignment ; Q ; ; ; ; ; @@ -1352,8 +1354,8 @@ applicable agreement for further details. ; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; +---------------------+---------------------+----------------------------+--------------------------+ ; Placement (by node) ; ; ; ; -; -- Requested ; 0.00 % ( 0 / 5964 ) ; 0.00 % ( 0 / 5964 ) ; 0.00 % ( 0 / 5964 ) ; -; -- Achieved ; 0.00 % ( 0 / 5964 ) ; 0.00 % ( 0 / 5964 ) ; 0.00 % ( 0 / 5964 ) ; +; -- Requested ; 0.00 % ( 0 / 6036 ) ; 0.00 % ( 0 / 6036 ) ; 0.00 % ( 0 / 6036 ) ; +; -- Achieved ; 0.00 % ( 0 / 6036 ) ; 0.00 % ( 0 / 6036 ) ; 0.00 % ( 0 / 6036 ) ; ; ; ; ; ; ; Routing (by net) ; ; ; ; ; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; @@ -1376,7 +1378,7 @@ applicable agreement for further details. +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ ; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ -; Top ; 0.00 % ( 0 / 5955 ) ; N/A ; Source File ; N/A ; ; +; Top ; 0.00 % ( 0 / 6027 ) ; N/A ; Source File ; N/A ; ; ; hard_block:auto_generated_inst ; 0.00 % ( 0 / 9 ) ; N/A ; Source File ; N/A ; ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ @@ -1392,44 +1394,44 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 +-------------------------------------------------------------+--------------------+-------+ ; Resource ; Usage ; % ; +-------------------------------------------------------------+--------------------+-------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 2,468 / 32,070 ; 8 % ; -; ALMs needed [=A-B+C] ; 2,468 ; ; -; [A] ALMs used in final placement [=a+b+c+d] ; 2,567 / 32,070 ; 8 % ; -; [a] ALMs used for LUT logic and registers ; 430 ; ; -; [b] ALMs used for LUT logic ; 1,652 ; ; -; [c] ALMs used for registers ; 385 ; ; +; Logic utilization (ALMs needed / total ALMs on device) ; 2,494 / 32,070 ; 8 % ; +; ALMs needed [=A-B+C] ; 2,494 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 2,611 / 32,070 ; 8 % ; +; [a] ALMs used for LUT logic and registers ; 427 ; ; +; [b] ALMs used for LUT logic ; 1,679 ; ; +; [c] ALMs used for registers ; 405 ; ; ; [d] ALMs used for memory (up to half of total ALMs) ; 100 ; ; -; [B] Estimate of ALMs recoverable by dense packing ; 152 / 32,070 ; < 1 % ; -; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 53 / 32,070 ; < 1 % ; +; [B] Estimate of ALMs recoverable by dense packing ; 175 / 32,070 ; < 1 % ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 58 / 32,070 ; < 1 % ; ; [a] Due to location constrained logic ; 3 ; ; ; [b] Due to LAB-wide signal conflicts ; 0 ; ; -; [c] Due to LAB input limits ; 50 ; ; +; [c] Due to LAB input limits ; 55 ; ; ; [d] Due to virtual I/Os ; 0 ; ; ; ; ; ; ; Difficulty packing design ; Low ; ; ; ; ; ; -; Total LABs: partially or completely used ; 322 / 3,207 ; 10 % ; -; -- Logic LABs ; 312 ; ; +; Total LABs: partially or completely used ; 331 / 3,207 ; 10 % ; +; -- Logic LABs ; 321 ; ; ; -- Memory LABs (up to half of total LABs) ; 10 ; ; ; ; ; ; -; Combinational ALUT usage for logic ; 3,718 ; ; +; Combinational ALUT usage for logic ; 3,763 ; ; ; -- 7 input functions ; 47 ; ; -; -- 6 input functions ; 335 ; ; -; -- 5 input functions ; 468 ; ; -; -- 4 input functions ; 822 ; ; -; -- <=3 input functions ; 2,046 ; ; -; Combinational ALUT usage for route-throughs ; 519 ; ; +; -- 6 input functions ; 327 ; ; +; -- 5 input functions ; 472 ; ; +; -- 4 input functions ; 831 ; ; +; -- <=3 input functions ; 2,086 ; ; +; Combinational ALUT usage for route-throughs ; 547 ; ; ; Memory ALUT usage ; 103 ; ; ; -- 64-address deep ; 0 ; ; ; -- 32-address deep ; 103 ; ; ; ; ; ; -; Dedicated logic registers ; 1,833 ; ; +; Dedicated logic registers ; 1,863 ; ; ; -- By type: ; ; ; -; -- Primary logic registers ; 1,630 / 64,140 ; 3 % ; -; -- Secondary logic registers ; 203 / 64,140 ; < 1 % ; +; -- Primary logic registers ; 1,662 / 64,140 ; 3 % ; +; -- Secondary logic registers ; 201 / 64,140 ; < 1 % ; ; -- By function: ; ; ; -; -- Design implementation registers ; 1,640 ; ; -; -- Routing optimization registers ; 193 ; ; +; -- Design implementation registers ; 1,668 ; ; +; -- Routing optimization registers ; 195 ; ; ; ; ; ; ; Virtual pins ; 0 ; ; ; I/O pins ; 204 / 457 ; 45 % ; @@ -1482,11 +1484,11 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 ; Impedance control blocks ; 0 / 4 ; 0 % ; ; Hard Memory Controllers ; 0 / 2 ; 0 % ; ; Average interconnect usage (total/H/V) ; 2% / 2% / 2% ; ; -; Peak interconnect usage (total/H/V) ; 31% / 30% / 35% ; ; -; Maximum fan-out ; 2069 ; ; -; Highest non-global fan-out ; 238 ; ; -; Total fan-out ; 21123 ; ; -; Average fan-out ; 3.17 ; ; +; Peak interconnect usage (total/H/V) ; 30% / 31% / 27% ; ; +; Maximum fan-out ; 2099 ; ; +; Highest non-global fan-out ; 246 ; ; +; Total fan-out ; 21324 ; ; +; Average fan-out ; 3.15 ; ; +-------------------------------------------------------------+--------------------+-------+ @@ -1495,44 +1497,44 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 +-------------------------------------------------------------+-----------------------+--------------------------------+ ; Statistic ; Top ; hard_block:auto_generated_inst ; +-------------------------------------------------------------+-----------------------+--------------------------------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 2468 / 32070 ( 8 % ) ; 0 / 32070 ( 0 % ) ; -; ALMs needed [=A-B+C] ; 2468 ; 0 ; -; [A] ALMs used in final placement [=a+b+c+d] ; 2567 / 32070 ( 8 % ) ; 0 / 32070 ( 0 % ) ; -; [a] ALMs used for LUT logic and registers ; 430 ; 0 ; -; [b] ALMs used for LUT logic ; 1652 ; 0 ; -; [c] ALMs used for registers ; 385 ; 0 ; +; Logic utilization (ALMs needed / total ALMs on device) ; 2494 / 32070 ( 8 % ) ; 0 / 32070 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 2494 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 2611 / 32070 ( 8 % ) ; 0 / 32070 ( 0 % ) ; +; [a] ALMs used for LUT logic and registers ; 427 ; 0 ; +; [b] ALMs used for LUT logic ; 1679 ; 0 ; +; [c] ALMs used for registers ; 405 ; 0 ; ; [d] ALMs used for memory (up to half of total ALMs) ; 100 ; 0 ; -; [B] Estimate of ALMs recoverable by dense packing ; 152 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; -; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 53 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [B] Estimate of ALMs recoverable by dense packing ; 175 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 58 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; ; [a] Due to location constrained logic ; 3 ; 0 ; ; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; -; [c] Due to LAB input limits ; 50 ; 0 ; +; [c] Due to LAB input limits ; 55 ; 0 ; ; [d] Due to virtual I/Os ; 0 ; 0 ; ; ; ; ; ; Difficulty packing design ; Low ; Low ; ; ; ; ; -; Total LABs: partially or completely used ; 322 / 3207 ( 10 % ) ; 0 / 3207 ( 0 % ) ; -; -- Logic LABs ; 312 ; 0 ; +; Total LABs: partially or completely used ; 331 / 3207 ( 10 % ) ; 0 / 3207 ( 0 % ) ; +; -- Logic LABs ; 321 ; 0 ; ; -- Memory LABs (up to half of total LABs) ; 10 ; 0 ; ; ; ; ; -; Combinational ALUT usage for logic ; 3821 ; 0 ; +; Combinational ALUT usage for logic ; 3866 ; 0 ; ; -- 7 input functions ; 47 ; 0 ; -; -- 6 input functions ; 335 ; 0 ; -; -- 5 input functions ; 468 ; 0 ; -; -- 4 input functions ; 822 ; 0 ; -; -- <=3 input functions ; 2046 ; 0 ; -; Combinational ALUT usage for route-throughs ; 519 ; 0 ; +; -- 6 input functions ; 327 ; 0 ; +; -- 5 input functions ; 472 ; 0 ; +; -- 4 input functions ; 831 ; 0 ; +; -- <=3 input functions ; 2086 ; 0 ; +; Combinational ALUT usage for route-throughs ; 547 ; 0 ; ; Memory ALUT usage ; 103 ; 0 ; ; -- 64-address deep ; 0 ; 0 ; ; -- 32-address deep ; 103 ; 0 ; ; ; ; ; ; Dedicated logic registers ; 0 ; 0 ; ; -- By type: ; ; ; -; -- Primary logic registers ; 1630 / 64140 ( 3 % ) ; 0 / 64140 ( 0 % ) ; -; -- Secondary logic registers ; 203 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ; +; -- Primary logic registers ; 1662 / 64140 ( 3 % ) ; 0 / 64140 ( 0 % ) ; +; -- Secondary logic registers ; 201 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ; ; -- By function: ; ; ; -; -- Design implementation registers ; 1640 ; 0 ; -; -- Routing optimization registers ; 193 ; 0 ; +; -- Design implementation registers ; 1668 ; 0 ; +; -- Routing optimization registers ; 195 ; 0 ; ; ; ; ; ; ; ; ; ; Virtual pins ; 0 ; 0 ; @@ -1549,18 +1551,18 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 ; PLL Reference Clock Select Block ; 0 / 6 ( 0 % ) ; 1 / 6 ( 16 % ) ; ; ; ; ; ; Connections ; ; ; -; -- Input Connections ; 2187 ; 0 ; -; -- Registered Input Connections ; 1866 ; 0 ; -; -- Output Connections ; 60 ; 2127 ; +; -- Input Connections ; 2246 ; 0 ; +; -- Registered Input Connections ; 1925 ; 0 ; +; -- Output Connections ; 60 ; 2186 ; ; -- Registered Output Connections ; 0 ; 0 ; ; ; ; ; ; Internal Connections ; ; ; -; -- Total Connections ; 22211 ; 2161 ; -; -- Registered Connections ; 9663 ; 0 ; +; -- Total Connections ; 22412 ; 2220 ; +; -- Registered Connections ; 9803 ; 0 ; ; ; ; ; ; External Connections ; ; ; -; -- Top ; 120 ; 2127 ; -; -- hard_block:auto_generated_inst ; 2127 ; 0 ; +; -- Top ; 120 ; 2186 ; +; -- hard_block:auto_generated_inst ; 2186 ; 0 ; ; ; ; ; ; Partition Interface ; ; ; ; -- Input Ports ; 32 ; 2 ; @@ -1598,7 +1600,7 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 ; KEY[0] ; AA14 ; 3B ; 36 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; KEY[1] ; AA15 ; 3B ; 36 ; 0 ; 17 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; KEY[2] ; W15 ; 3B ; 40 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; -; KEY[3] ; Y16 ; 3B ; 40 ; 0 ; 17 ; 59 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; +; KEY[3] ; Y16 ; 3B ; 40 ; 0 ; 17 ; 88 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[0] ; AB12 ; 3A ; 12 ; 0 ; 17 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[1] ; AC12 ; 3A ; 16 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[2] ; AF9 ; 3A ; 8 ; 0 ; 34 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; @@ -1606,7 +1608,7 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 ; SW[4] ; AD11 ; 3A ; 2 ; 0 ; 40 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[5] ; AD12 ; 3A ; 16 ; 0 ; 17 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[6] ; AE11 ; 3A ; 4 ; 0 ; 34 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; -; SW[7] ; AC9 ; 3A ; 4 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; +; SW[7] ; AC9 ; 3A ; 4 ; 0 ; 0 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[8] ; AD10 ; 3A ; 4 ; 0 ; 17 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[9] ; AE12 ; 3A ; 2 ; 0 ; 57 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; TD_CLK27 ; H15 ; 8A ; 40 ; 81 ; 0 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; @@ -1799,9 +1801,9 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 ; GPIO[35] ; AJ21 ; 4A ; 62 ; 0 ; 51 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; ; GPIO[3] ; Y18 ; 4A ; 72 ; 0 ; 0 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; ; GPIO[4] ; AK16 ; 4A ; 54 ; 0 ; 51 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; -; GPIO[5] ; AK18 ; 4A ; 58 ; 0 ; 57 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; +; GPIO[5] ; AK18 ; 4A ; 58 ; 0 ; 57 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; ; GPIO[6] ; AK19 ; 4A ; 60 ; 0 ; 51 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; -; GPIO[7] ; AJ19 ; 4A ; 60 ; 0 ; 34 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; +; GPIO[7] ; AJ19 ; 4A ; 60 ; 0 ; 34 ; 1 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; ; GPIO[8] ; AJ17 ; 4A ; 58 ; 0 ; 40 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; ; GPIO[9] ; AJ16 ; 4A ; 54 ; 0 ; 34 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; ; PS2_CLK ; AD7 ; 3A ; 6 ; 0 ; 0 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; @@ -2786,85 +2788,89 @@ Note: Pin directions (input, output or bidir) are based on device operating in u +----------------------------------------------------------------------------------------------------------------+----------------------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+----------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+----------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -; |de1_riscv ; 2468.0 (60.9) ; 2566.5 (68.8) ; 151.0 (8.4) ; 52.5 (0.5) ; 100.0 (0.0) ; 3718 (91) ; 1833 (66) ; 0 (0) ; 66560 ; 9 ; 10 ; 204 ; 0 ; |de1_riscv ; work ; -; |clk100M:clk100| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100 ; clk100M ; -; |clk100M_0002:clk100m_inst| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst ; clk100M ; -; |altera_pll:altera_pll_i| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; work ; -; |ram8kb:ram| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram ; work ; -; |altsyncram:altsyncram_component| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component ; work ; -; |altsyncram_bdq1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated ; work ; -; |regfile:regs| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs ; work ; -; |altsyncram:altsyncram_component| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component ; work ; -; |altsyncram_nco1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; work ; -; |riscv_core:core| ; 2407.1 (836.3) ; 2497.7 (861.6) ; 142.6 (55.4) ; 52.0 (30.2) ; 100.0 (0.0) ; 3627 (1184) ; 1767 (310) ; 0 (0) ; 0 ; 0 ; 10 ; 0 ; 0 ; |de1_riscv|riscv_core:core ; work ; -; |adder:add| ; 11.0 (0.0) ; 11.3 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add ; work ; -; |lpm_add_sub:LPM_ADD_SUB_component| ; 11.0 (0.0) ; 11.3 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component ; work ; -; |add_sub_tih:auto_generated| ; 11.0 (11.0) ; 11.3 (11.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (33) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component|add_sub_tih:auto_generated ; work ; -; |div:div| ; 623.8 (0.0) ; 651.7 (0.0) ; 34.6 (0.0) ; 6.7 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 658 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div ; work ; -; |lpm_divide:LPM_DIVIDE_component| ; 623.8 (0.0) ; 651.7 (0.0) ; 34.6 (0.0) ; 6.7 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 658 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component ; work ; -; |lpm_divide_2jt:auto_generated| ; 623.8 (0.0) ; 651.7 (0.0) ; 34.6 (0.0) ; 6.7 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 658 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated ; work ; -; |sign_div_unsign_8ai:divider| ; 623.8 (0.0) ; 651.7 (0.0) ; 34.6 (0.0) ; 6.7 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 658 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider ; work ; -; |alt_u_div_nlf:divider| ; 623.8 (623.8) ; 651.7 (651.7) ; 34.6 (34.6) ; 6.7 (6.7) ; 0.0 (0.0) ; 1002 (1002) ; 658 (658) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider ; work ; -; |div_s:divs| ; 869.0 (0.0) ; 908.5 (0.0) ; 52.6 (0.0) ; 13.2 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 799 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs ; work ; -; |lpm_divide:LPM_DIVIDE_component| ; 869.0 (0.0) ; 908.5 (0.0) ; 52.6 (0.0) ; 13.2 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 799 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component ; work ; -; |lpm_divide_s4t:auto_generated| ; 869.0 (0.0) ; 908.5 (0.0) ; 52.6 (0.0) ; 13.2 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 799 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated ; work ; -; |sign_div_unsign_2sh:divider| ; 869.0 (80.1) ; 908.5 (79.6) ; 52.6 (5.2) ; 13.2 (5.7) ; 100.0 (0.0) ; 1278 (175) ; 799 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider ; work ; -; |alt_u_div_5eg:divider| ; 772.3 (630.3) ; 810.4 (656.0) ; 45.6 (33.1) ; 7.4 (7.4) ; 90.0 (0.0) ; 1090 (987) ; 772 (670) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider ; work ; -; |altshift_taps:DFFNumerator_rtl_0| ; 17.0 (0.0) ; 19.0 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 15 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 ; work ; -; |shift_taps_hm21:auto_generated| ; 17.0 (2.9) ; 19.0 (4.0) ; 2.0 (1.1) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (8) ; 15 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated ; work ; -; |altsyncram_9u91:altsyncram5| ; 11.1 (11.1) ; 11.5 (11.5) ; 0.4 (0.4) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 ; work ; -; |cntr_9jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_1| ; 16.5 (0.0) ; 18.5 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 ; work ; -; |shift_taps_gm21:auto_generated| ; 16.5 (2.3) ; 18.5 (3.3) ; 2.0 (1.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (7) ; 13 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated ; work ; -; |altsyncram_7u91:altsyncram5| ; 11.3 (11.3) ; 11.8 (11.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 ; work ; -; |cntr_8jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_2| ; 17.0 (0.0) ; 19.0 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 ; work ; -; |shift_taps_bl21:auto_generated| ; 17.0 (2.9) ; 19.0 (4.0) ; 2.0 (1.1) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (8) ; 16 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated ; work ; -; |altsyncram_rr91:altsyncram5| ; 11.1 (11.1) ; 11.5 (11.5) ; 0.4 (0.4) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 ; work ; -; |cntr_0if:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_3| ; 14.5 (0.0) ; 15.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 8 (0) ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 ; work ; -; |shift_taps_9l21:auto_generated| ; 14.5 (2.3) ; 15.0 (2.4) ; 0.5 (0.2) ; 0.0 (0.0) ; 10.0 (0.0) ; 8 (5) ; 11 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated ; work ; -; |altsyncram_lr91:altsyncram4| ; 10.8 (10.8) ; 11.1 (11.1) ; 0.3 (0.3) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 ; work ; -; |cntr_uhf:cntr1| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_4| ; 17.0 (0.0) ; 18.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 ; work ; -; |shift_taps_cl21:auto_generated| ; 17.0 (3.1) ; 18.5 (3.4) ; 1.5 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (7) ; 11 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated ; work ; -; |altsyncram_hr91:altsyncram5| ; 10.5 (10.5) ; 11.1 (11.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 ; work ; -; |cntr_thf:cntr1| ; 3.4 (3.4) ; 4.0 (4.0) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_5| ; 16.5 (0.0) ; 18.0 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 ; work ; -; |shift_taps_dl21:auto_generated| ; 16.5 (2.3) ; 18.0 (3.2) ; 1.5 (0.9) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (6) ; 11 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated ; work ; -; |altsyncram_mr91:altsyncram5| ; 10.6 (10.6) ; 11.0 (11.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 ; work ; -; |cntr_shf:cntr1| ; 3.7 (3.7) ; 3.8 (3.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_6| ; 17.0 (0.0) ; 18.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 12 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 ; work ; -; |shift_taps_4l21:auto_generated| ; 17.0 (3.1) ; 18.5 (3.4) ; 1.5 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (7) ; 12 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated ; work ; -; |altsyncram_dr91:altsyncram5| ; 10.5 (10.5) ; 11.1 (11.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 ; work ; -; |cntr_rhf:cntr1| ; 3.4 (3.4) ; 4.0 (4.0) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_7| ; 13.0 (0.0) ; 13.5 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 6 (0) ; 6 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 ; work ; -; |shift_taps_3l21:auto_generated| ; 13.0 (1.8) ; 13.5 (1.8) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 6 (4) ; 6 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated ; work ; -; |altsyncram_9r91:altsyncram4| ; 10.4 (10.4) ; 10.8 (10.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 ; work ; -; |cntr_phf:cntr1| ; 0.8 (0.8) ; 1.0 (1.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_8| ; 13.5 (0.0) ; 14.5 (0.0) ; 1.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 7 (0) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 ; work ; -; |shift_taps_5l21:auto_generated| ; 13.5 (0.9) ; 14.5 (1.3) ; 1.0 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 7 (2) ; 7 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated ; work ; -; |altsyncram_br91:altsyncram4| ; 10.4 (10.4) ; 10.8 (10.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 ; work ; -; |cntr_ohf:cntr1| ; 2.2 (2.2) ; 2.5 (2.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1 ; work ; -; |altshift_taps:DFF_Num_Sign_rtl_0| ; 16.6 (0.0) ; 18.5 (0.0) ; 1.9 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 ; work ; -; |shift_taps_7l21:auto_generated| ; 16.6 (2.5) ; 18.5 (3.3) ; 1.9 (0.7) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (7) ; 13 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated ; work ; -; |altsyncram_kr91:altsyncram5| ; 11.0 (11.0) ; 11.8 (11.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 ; work ; -; |cntr_8jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1 ; work ; -; |mulsu:mul_su| ; 19.2 (0.0) ; 18.7 (0.0) ; 0.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 38 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su ; work ; -; |lpm_mult:lpm_mult_component| ; 19.2 (0.0) ; 18.7 (0.0) ; 0.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 38 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component ; work ; -; |mult_61n:auto_generated| ; 19.2 (19.2) ; 18.7 (18.7) ; 0.0 (0.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 38 (38) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated ; work ; -; |mult:mul| ; 23.9 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.9 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul ; work ; -; |lpm_mult:lpm_mult_component| ; 23.9 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.9 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component ; work ; -; |mult_b8n:auto_generated| ; 23.9 (23.9) ; 23.0 (23.0) ; 0.0 (0.0) ; 0.9 (0.9) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component|mult_b8n:auto_generated ; work ; -; |mult_s:mul_s| ; 23.6 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.6 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s ; work ; -; |lpm_mult:lpm_mult_component| ; 23.6 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.6 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component ; work ; -; |mult_81n:auto_generated| ; 23.6 (23.6) ; 23.0 (23.0) ; 0.0 (0.0) ; 0.6 (0.6) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated ; work ; -+----------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |de1_riscv ; 2493.5 (64.7) ; 2609.5 (70.4) ; 173.0 (6.5) ; 57.0 (0.8) ; 100.0 (0.0) ; 3763 (95) ; 1863 (66) ; 0 (0) ; 66560 ; 9 ; 10 ; 204 ; 0 ; |de1_riscv ; work ; +; |altera_uart:uart| ; 18.5 (0.0) ; 20.5 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 36 (0) ; 29 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart ; work ; +; |altera_uart_regs:the_altera_uart_regs| ; 0.9 (0.9) ; 1.2 (1.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_regs:the_altera_uart_regs ; work ; +; |altera_uart_rx:the_altera_uart_rx| ; 17.6 (16.9) ; 19.3 (18.7) ; 1.7 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 35 (35) ; 27 (25) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx ; work ; +; |altera_std_synchronizer:the_altera_std_synchronizer| ; 0.7 (0.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; work ; +; |clk100M:clk100| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100 ; clk100M ; +; |clk100M_0002:clk100m_inst| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst ; clk100M ; +; |altera_pll:altera_pll_i| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; work ; +; |ram8kb:ram| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram ; work ; +; |altsyncram:altsyncram_component| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component ; work ; +; |altsyncram_bdq1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated ; work ; +; |regfile:regs| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs ; work ; +; |altsyncram:altsyncram_component| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component ; work ; +; |altsyncram_nco1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; work ; +; |riscv_core:core| ; 2410.3 (842.3) ; 2518.6 (868.5) ; 164.5 (60.1) ; 56.2 (33.9) ; 100.0 (0.0) ; 3632 (1189) ; 1768 (314) ; 0 (0) ; 0 ; 0 ; 10 ; 0 ; 0 ; |de1_riscv|riscv_core:core ; work ; +; |adder:add| ; 9.0 (0.0) ; 9.8 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add ; work ; +; |lpm_add_sub:LPM_ADD_SUB_component| ; 9.0 (0.0) ; 9.8 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component ; work ; +; |add_sub_tih:auto_generated| ; 9.0 (9.0) ; 9.8 (9.8) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (33) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component|add_sub_tih:auto_generated ; work ; +; |div:div| ; 622.1 (0.0) ; 657.9 (0.0) ; 43.1 (0.0) ; 7.3 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 648 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div ; work ; +; |lpm_divide:LPM_DIVIDE_component| ; 622.1 (0.0) ; 657.9 (0.0) ; 43.1 (0.0) ; 7.3 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 648 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component ; work ; +; |lpm_divide_2jt:auto_generated| ; 622.1 (0.0) ; 657.9 (0.0) ; 43.1 (0.0) ; 7.3 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 648 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated ; work ; +; |sign_div_unsign_8ai:divider| ; 622.1 (0.0) ; 657.9 (0.0) ; 43.1 (0.0) ; 7.3 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 648 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider ; work ; +; |alt_u_div_nlf:divider| ; 622.1 (622.1) ; 657.9 (657.9) ; 43.1 (43.1) ; 7.3 (7.3) ; 0.0 (0.0) ; 1002 (1002) ; 648 (648) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider ; work ; +; |div_s:divs| ; 869.4 (0.0) ; 917.4 (0.0) ; 60.4 (0.0) ; 12.5 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 806 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs ; work ; +; |lpm_divide:LPM_DIVIDE_component| ; 869.4 (0.0) ; 917.4 (0.0) ; 60.4 (0.0) ; 12.5 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 806 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component ; work ; +; |lpm_divide_s4t:auto_generated| ; 869.4 (0.0) ; 917.4 (0.0) ; 60.4 (0.0) ; 12.5 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 806 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated ; work ; +; |sign_div_unsign_2sh:divider| ; 869.4 (80.0) ; 917.4 (76.2) ; 60.4 (1.6) ; 12.5 (5.4) ; 100.0 (0.0) ; 1278 (175) ; 806 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider ; work ; +; |alt_u_div_5eg:divider| ; 772.8 (630.8) ; 822.7 (668.0) ; 57.0 (44.3) ; 7.1 (7.1) ; 90.0 (0.0) ; 1090 (987) ; 779 (682) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider ; work ; +; |altshift_taps:DFFNumerator_rtl_0| ; 17.0 (0.0) ; 19.0 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 ; work ; +; |shift_taps_hm21:auto_generated| ; 17.0 (2.9) ; 19.0 (4.0) ; 2.0 (1.1) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (8) ; 13 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated ; work ; +; |altsyncram_9u91:altsyncram5| ; 11.1 (11.1) ; 11.5 (11.5) ; 0.4 (0.4) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 ; work ; +; |cntr_9jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_1| ; 16.5 (0.0) ; 18.5 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 ; work ; +; |shift_taps_gm21:auto_generated| ; 16.5 (2.3) ; 18.5 (3.3) ; 2.0 (1.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (7) ; 14 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated ; work ; +; |altsyncram_7u91:altsyncram5| ; 11.3 (11.3) ; 11.8 (11.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 ; work ; +; |cntr_8jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_2| ; 17.0 (0.0) ; 19.0 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 ; work ; +; |shift_taps_bl21:auto_generated| ; 17.0 (2.9) ; 19.0 (4.0) ; 2.0 (1.1) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (8) ; 16 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated ; work ; +; |altsyncram_rr91:altsyncram5| ; 11.1 (11.1) ; 11.5 (11.5) ; 0.4 (0.4) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 ; work ; +; |cntr_0if:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_3| ; 14.5 (0.0) ; 15.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 8 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 ; work ; +; |shift_taps_9l21:auto_generated| ; 14.5 (2.3) ; 15.0 (2.6) ; 0.5 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 8 (5) ; 9 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated ; work ; +; |altsyncram_lr91:altsyncram4| ; 10.8 (10.8) ; 10.9 (10.9) ; 0.2 (0.2) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 ; work ; +; |cntr_uhf:cntr1| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_4| ; 17.0 (0.0) ; 18.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 ; work ; +; |shift_taps_cl21:auto_generated| ; 17.0 (3.1) ; 18.5 (3.4) ; 1.5 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (7) ; 9 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated ; work ; +; |altsyncram_hr91:altsyncram5| ; 10.5 (10.5) ; 11.1 (11.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 ; work ; +; |cntr_thf:cntr1| ; 3.4 (3.4) ; 4.0 (4.0) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_5| ; 16.5 (0.0) ; 18.2 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 ; work ; +; |shift_taps_dl21:auto_generated| ; 16.5 (2.3) ; 18.2 (3.0) ; 1.7 (0.8) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (6) ; 10 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated ; work ; +; |altsyncram_mr91:altsyncram5| ; 10.6 (10.6) ; 11.2 (11.2) ; 0.6 (0.6) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 ; work ; +; |cntr_shf:cntr1| ; 3.7 (3.7) ; 4.0 (4.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_6| ; 17.0 (0.0) ; 18.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 12 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 ; work ; +; |shift_taps_4l21:auto_generated| ; 17.0 (3.1) ; 18.5 (3.4) ; 1.5 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (7) ; 12 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated ; work ; +; |altsyncram_dr91:altsyncram5| ; 10.5 (10.5) ; 11.1 (11.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 ; work ; +; |cntr_rhf:cntr1| ; 3.4 (3.4) ; 4.0 (4.0) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_7| ; 13.0 (0.0) ; 13.5 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 6 (0) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 ; work ; +; |shift_taps_3l21:auto_generated| ; 13.0 (1.8) ; 13.5 (1.9) ; 0.5 (0.2) ; 0.0 (0.0) ; 10.0 (0.0) ; 6 (4) ; 7 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated ; work ; +; |altsyncram_9r91:altsyncram4| ; 10.4 (10.4) ; 10.6 (10.6) ; 0.2 (0.2) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 ; work ; +; |cntr_phf:cntr1| ; 0.8 (0.8) ; 1.0 (1.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_8| ; 13.5 (0.0) ; 14.5 (0.0) ; 1.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 7 (0) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 ; work ; +; |shift_taps_5l21:auto_generated| ; 13.5 (0.9) ; 14.5 (1.3) ; 1.0 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 7 (2) ; 7 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated ; work ; +; |altsyncram_br91:altsyncram4| ; 10.4 (10.4) ; 10.8 (10.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 ; work ; +; |cntr_ohf:cntr1| ; 2.2 (2.2) ; 2.5 (2.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1 ; work ; +; |altshift_taps:DFF_Num_Sign_rtl_0| ; 16.6 (0.0) ; 18.5 (0.0) ; 1.9 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 ; work ; +; |shift_taps_7l21:auto_generated| ; 16.6 (2.5) ; 18.5 (3.5) ; 1.9 (1.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (7) ; 13 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated ; work ; +; |altsyncram_kr91:altsyncram5| ; 11.0 (11.0) ; 11.5 (11.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 ; work ; +; |cntr_8jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1 ; work ; +; |mulsu:mul_su| ; 19.5 (0.0) ; 19.0 (0.0) ; 0.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 38 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su ; work ; +; |lpm_mult:lpm_mult_component| ; 19.5 (0.0) ; 19.0 (0.0) ; 0.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 38 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component ; work ; +; |mult_61n:auto_generated| ; 19.5 (19.5) ; 19.0 (19.0) ; 0.0 (0.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 38 (38) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated ; work ; +; |mult:mul| ; 24.2 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 1.2 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul ; work ; +; |lpm_mult:lpm_mult_component| ; 24.2 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 1.2 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component ; work ; +; |mult_b8n:auto_generated| ; 24.2 (24.2) ; 23.0 (23.0) ; 0.0 (0.0) ; 1.2 (1.2) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component|mult_b8n:auto_generated ; work ; +; |mult_s:mul_s| ; 23.7 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.7 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s ; work ; +; |lpm_mult:lpm_mult_component| ; 23.7 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.7 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component ; work ; +; |mult_81n:auto_generated| ; 23.7 (23.7) ; 23.0 (23.0) ; 0.0 (0.0) ; 0.7 (0.7) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated ; work ; ++----------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -3031,9 +3037,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; GPIO[2] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[3] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[4] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; GPIO[5] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[6] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; GPIO[7] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[8] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[9] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[10] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; @@ -3062,6 +3066,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; GPIO[33] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[34] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[35] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; GPIO[5] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; GPIO[7] ; Bidir ; -- ; (0) ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; KEY[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; SW[8] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ; SW[9] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; @@ -3070,9 +3076,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; SW[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; SW[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; SW[6] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; SW[4] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; SW[5] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; SW[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ; SW[7] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; KEY[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; KEY[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; @@ -3080,262 +3086,292 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+--------------------------------------------------------------------------------------------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+--------------------------------------------------------------------------------------------------------+-------------------+---------+ -; ADC_DOUT ; ; ; -; AUD_ADCDAT ; ; ; -; CLOCK2_50 ; ; ; -; CLOCK3_50 ; ; ; -; CLOCK4_50 ; ; ; -; IRDA_RXD ; ; ; -; TD_CLK27 ; ; ; -; TD_DATA[0] ; ; ; -; TD_DATA[1] ; ; ; -; TD_DATA[2] ; ; ; -; TD_DATA[3] ; ; ; -; TD_DATA[4] ; ; ; -; TD_DATA[5] ; ; ; -; TD_DATA[6] ; ; ; -; TD_DATA[7] ; ; ; -; TD_HS ; ; ; -; TD_VS ; ; ; -; AUD_ADCLRCK ; ; ; -; AUD_BCLK ; ; ; -; AUD_DACLRCK ; ; ; -; DRAM_DQ[0] ; ; ; -; DRAM_DQ[1] ; ; ; -; DRAM_DQ[2] ; ; ; -; DRAM_DQ[3] ; ; ; -; DRAM_DQ[4] ; ; ; -; DRAM_DQ[5] ; ; ; -; DRAM_DQ[6] ; ; ; -; DRAM_DQ[7] ; ; ; -; DRAM_DQ[8] ; ; ; -; DRAM_DQ[9] ; ; ; -; DRAM_DQ[10] ; ; ; -; DRAM_DQ[11] ; ; ; -; DRAM_DQ[12] ; ; ; -; DRAM_DQ[13] ; ; ; -; DRAM_DQ[14] ; ; ; -; DRAM_DQ[15] ; ; ; -; FPGA_I2C_SDAT ; ; ; -; PS2_CLK ; ; ; -; PS2_CLK2 ; ; ; -; PS2_DAT ; ; ; -; PS2_DAT2 ; ; ; -; GPIO[0] ; ; ; -; GPIO[1] ; ; ; -; GPIO[2] ; ; ; -; GPIO[3] ; ; ; -; GPIO[4] ; ; ; -; GPIO[5] ; ; ; -; GPIO[6] ; ; ; -; GPIO[7] ; ; ; -; GPIO[8] ; ; ; -; GPIO[9] ; ; ; -; GPIO[10] ; ; ; -; GPIO[11] ; ; ; -; GPIO[12] ; ; ; -; GPIO[13] ; ; ; -; GPIO[14] ; ; ; -; GPIO[15] ; ; ; -; GPIO[16] ; ; ; -; GPIO[17] ; ; ; -; GPIO[18] ; ; ; -; GPIO[19] ; ; ; -; GPIO[20] ; ; ; -; GPIO[21] ; ; ; -; GPIO[22] ; ; ; -; GPIO[23] ; ; ; -; GPIO[24] ; ; ; -; GPIO[25] ; ; ; -; GPIO[26] ; ; ; -; GPIO[27] ; ; ; -; GPIO[28] ; ; ; -; GPIO[29] ; ; ; -; GPIO[30] ; ; ; -; GPIO[31] ; ; ; -; GPIO[32] ; ; ; -; GPIO[33] ; ; ; -; GPIO[34] ; ; ; -; GPIO[35] ; ; ; -; KEY[3] ; ; ; -; - riscv_core:core|pc[22] ; 0 ; 0 ; -; - riscv_core:core|pc[23] ; 0 ; 0 ; -; - riscv_core:core|pc[24] ; 0 ; 0 ; -; - riscv_core:core|pc[25] ; 0 ; 0 ; -; - riscv_core:core|pc[3] ; 0 ; 0 ; -; - riscv_core:core|pc[26] ; 0 ; 0 ; -; - riscv_core:core|pc[20] ; 0 ; 0 ; -; - riscv_core:core|pc[27] ; 0 ; 0 ; -; - riscv_core:core|pc[13] ; 0 ; 0 ; -; - riscv_core:core|pc[30] ; 0 ; 0 ; -; - riscv_core:core|pc[10] ; 0 ; 0 ; -; - riscv_core:core|pc[28] ; 0 ; 0 ; -; - riscv_core:core|pc[14] ; 0 ; 0 ; -; - riscv_core:core|pc[15] ; 0 ; 0 ; -; - riscv_core:core|pc[16] ; 0 ; 0 ; -; - riscv_core:core|pc[17] ; 0 ; 0 ; -; - riscv_core:core|pc[18] ; 0 ; 0 ; -; - riscv_core:core|pc[29] ; 0 ; 0 ; -; - riscv_core:core|pc[11] ; 0 ; 0 ; -; - riscv_core:core|pc[9] ; 0 ; 0 ; -; - riscv_core:core|pc[7] ; 0 ; 0 ; -; - riscv_core:core|pc[12] ; 0 ; 0 ; -; - riscv_core:core|pc[19] ; 0 ; 0 ; -; - riscv_core:core|pc[21] ; 0 ; 0 ; -; - riscv_core:core|pc[8] ; 0 ; 0 ; -; - riscv_core:core|write ; 0 ; 0 ; -; - riscv_core:core|pc[0] ; 0 ; 0 ; -; - riscv_core:core|pc[1] ; 0 ; 0 ; -; - riscv_core:core|state.0110 ; 0 ; 0 ; -; - riscv_core:core|state.1010 ; 0 ; 0 ; -; - riscv_core:core|state.0010 ; 0 ; 0 ; -; - riscv_core:core|pc[31] ; 0 ; 0 ; -; - led0~0 ; 0 ; 0 ; -; - led2~0 ; 0 ; 0 ; -; - riscv_core:core|writedata[0]~2 ; 0 ; 0 ; -; - bReadData[13]~1 ; 0 ; 0 ; -; - riscv_core:core|state~25 ; 0 ; 0 ; -; - riscv_core:core|state.0000 ; 0 ; 0 ; -; - riscv_core:core|state~26 ; 0 ; 0 ; -; - readaddr~0 ; 0 ; 0 ; -; - riscv_core:core|state~27 ; 0 ; 0 ; -; - riscv_core:core|state~28 ; 0 ; 0 ; -; - riscv_core:core|state~29 ; 0 ; 0 ; -; - riscv_core:core|pc[31]~3 ; 0 ; 0 ; -; - riscv_core:core|pc~26 ; 0 ; 0 ; -; - riscv_core:core|pc~28 ; 0 ; 0 ; -; - riscv_core:core|pc~29 ; 0 ; 0 ; -; - riscv_core:core|pc~30 ; 0 ; 0 ; -; - riscv_core:core|Mux5~0 ; 0 ; 0 ; -; - riscv_core:core|Selector247~4 ; 0 ; 0 ; -; - riscv_core:core|state~30 ; 0 ; 0 ; -; - riscv_core:core|divclk[4]~0 ; 0 ; 0 ; -; - riscv_core:core|divclk[3]~1 ; 0 ; 0 ; -; - riscv_core:core|divclk[2]~2 ; 0 ; 0 ; -; - riscv_core:core|divclk[0]~3 ; 0 ; 0 ; -; - riscv_core:core|divclk[1]~4 ; 0 ; 0 ; -; - riscv_core:core|pc[0]~33 ; 0 ; 0 ; -; - KEY[3]~_wirecell ; 0 ; 0 ; -; - clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL ; 0 ; 0 ; -; SW[8] ; ; ; -; - led0~0 ; 1 ; 0 ; -; - led2~0 ; 1 ; 0 ; -; - riscv_core:core|Mux17~0 ; 1 ; 0 ; -; - riscv_core:core|Mux57~0 ; 1 ; 0 ; -; - bReadData[8]~20 ; 1 ; 0 ; -; SW[9] ; ; ; -; - led1[5]~0 ; 1 ; 0 ; -; - led1[5]~3 ; 1 ; 0 ; -; - led2~1 ; 1 ; 0 ; -; - led3~0 ; 1 ; 0 ; -; - led4[0]~0 ; 1 ; 0 ; -; - led4~1 ; 1 ; 0 ; -; - led5~0 ; 1 ; 0 ; -; - bReadData[9]~18 ; 1 ; 0 ; -; - riscv_core:core|Mux9~0 ; 1 ; 0 ; -; - riscv_core:core|Mux56~1 ; 1 ; 0 ; -; CLOCK_50 ; ; ; -; KEY[2] ; ; ; -; - bReadData[12]~0 ; 1 ; 0 ; -; - riscv_core:core|Mux6~0 ; 1 ; 0 ; -; - riscv_core:core|Selector248~4 ; 1 ; 0 ; -; SW[2] ; ; ; -; - bReadData[2]~3 ; 0 ; 0 ; -; SW[3] ; ; ; -; - bReadData[3]~4 ; 0 ; 0 ; -; SW[6] ; ; ; -; - bReadData[6]~5 ; 1 ; 0 ; -; SW[4] ; ; ; -; - bReadData[4]~6 ; 1 ; 0 ; -; SW[5] ; ; ; -; - bReadData[5]~7 ; 1 ; 0 ; -; SW[0] ; ; ; -; - riscv_core:core|Mux57~1 ; 0 ; 0 ; -; SW[7] ; ; ; -; - riscv_core:core|Mux18~1 ; 0 ; 0 ; -; - bReadData[7]~19 ; 0 ; 0 ; -; - riscv_core:core|Mux1~1 ; 0 ; 0 ; -; - riscv_core:core|Mux1~3 ; 0 ; 0 ; -; - riscv_core:core|Mux26~5 ; 0 ; 0 ; -; - riscv_core:core|Mux26~7 ; 0 ; 0 ; -; KEY[0] ; ; ; -; - bReadData[10]~27 ; 0 ; 0 ; -; - riscv_core:core|Mux8~0 ; 0 ; 0 ; -; - riscv_core:core|Selector250~4 ; 0 ; 0 ; -; KEY[1] ; ; ; -; - bReadData[11]~29 ; 1 ; 0 ; -; - riscv_core:core|Mux7~0 ; 1 ; 0 ; -; - riscv_core:core|Selector249~4 ; 1 ; 0 ; -; SW[1] ; ; ; -; - riscv_core:core|Mux56~2 ; 0 ; 0 ; -+--------------------------------------------------------------------------------------------------------+-------------------+---------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; ADC_DOUT ; ; ; +; AUD_ADCDAT ; ; ; +; CLOCK2_50 ; ; ; +; CLOCK3_50 ; ; ; +; CLOCK4_50 ; ; ; +; IRDA_RXD ; ; ; +; TD_CLK27 ; ; ; +; TD_DATA[0] ; ; ; +; TD_DATA[1] ; ; ; +; TD_DATA[2] ; ; ; +; TD_DATA[3] ; ; ; +; TD_DATA[4] ; ; ; +; TD_DATA[5] ; ; ; +; TD_DATA[6] ; ; ; +; TD_DATA[7] ; ; ; +; TD_HS ; ; ; +; TD_VS ; ; ; +; AUD_ADCLRCK ; ; ; +; AUD_BCLK ; ; ; +; AUD_DACLRCK ; ; ; +; DRAM_DQ[0] ; ; ; +; DRAM_DQ[1] ; ; ; +; DRAM_DQ[2] ; ; ; +; DRAM_DQ[3] ; ; ; +; DRAM_DQ[4] ; ; ; +; DRAM_DQ[5] ; ; ; +; DRAM_DQ[6] ; ; ; +; DRAM_DQ[7] ; ; ; +; DRAM_DQ[8] ; ; ; +; DRAM_DQ[9] ; ; ; +; DRAM_DQ[10] ; ; ; +; DRAM_DQ[11] ; ; ; +; DRAM_DQ[12] ; ; ; +; DRAM_DQ[13] ; ; ; +; DRAM_DQ[14] ; ; ; +; DRAM_DQ[15] ; ; ; +; FPGA_I2C_SDAT ; ; ; +; PS2_CLK ; ; ; +; PS2_CLK2 ; ; ; +; PS2_DAT ; ; ; +; PS2_DAT2 ; ; ; +; GPIO[0] ; ; ; +; GPIO[1] ; ; ; +; GPIO[2] ; ; ; +; GPIO[3] ; ; ; +; GPIO[4] ; ; ; +; GPIO[6] ; ; ; +; GPIO[8] ; ; ; +; GPIO[9] ; ; ; +; GPIO[10] ; ; ; +; GPIO[11] ; ; ; +; GPIO[12] ; ; ; +; GPIO[13] ; ; ; +; GPIO[14] ; ; ; +; GPIO[15] ; ; ; +; GPIO[16] ; ; ; +; GPIO[17] ; ; ; +; GPIO[18] ; ; ; +; GPIO[19] ; ; ; +; GPIO[20] ; ; ; +; GPIO[21] ; ; ; +; GPIO[22] ; ; ; +; GPIO[23] ; ; ; +; GPIO[24] ; ; ; +; GPIO[25] ; ; ; +; GPIO[26] ; ; ; +; GPIO[27] ; ; ; +; GPIO[28] ; ; ; +; GPIO[29] ; ; ; +; GPIO[30] ; ; ; +; GPIO[31] ; ; ; +; GPIO[32] ; ; ; +; GPIO[33] ; ; ; +; GPIO[34] ; ; ; +; GPIO[35] ; ; ; +; GPIO[5] ; ; ; +; GPIO[7] ; ; ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~feeder ; 0 ; 0 ; +; KEY[3] ; ; ; +; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|d1_rx_char_ready ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|d1_tx_ready ; 0 ; 0 ; +; - riscv_core:core|pc[18] ; 0 ; 0 ; +; - riscv_core:core|pc[3] ; 0 ; 0 ; +; - riscv_core:core|pc[14] ; 0 ; 0 ; +; - riscv_core:core|pc[8] ; 0 ; 0 ; +; - riscv_core:core|pc[9] ; 0 ; 0 ; +; - riscv_core:core|pc[10] ; 0 ; 0 ; +; - riscv_core:core|pc[11] ; 0 ; 0 ; +; - riscv_core:core|pc[12] ; 0 ; 0 ; +; - riscv_core:core|pc[13] ; 0 ; 0 ; +; - riscv_core:core|pc[30] ; 0 ; 0 ; +; - riscv_core:core|pc[15] ; 0 ; 0 ; +; - riscv_core:core|pc[16] ; 0 ; 0 ; +; - riscv_core:core|pc[17] ; 0 ; 0 ; +; - riscv_core:core|pc[19] ; 0 ; 0 ; +; - riscv_core:core|pc[20] ; 0 ; 0 ; +; - riscv_core:core|pc[21] ; 0 ; 0 ; +; - riscv_core:core|pc[22] ; 0 ; 0 ; +; - riscv_core:core|pc[23] ; 0 ; 0 ; +; - riscv_core:core|pc[24] ; 0 ; 0 ; +; - riscv_core:core|pc[7] ; 0 ; 0 ; +; - riscv_core:core|pc[26] ; 0 ; 0 ; +; - riscv_core:core|pc[27] ; 0 ; 0 ; +; - riscv_core:core|pc[28] ; 0 ; 0 ; +; - riscv_core:core|pc[29] ; 0 ; 0 ; +; - riscv_core:core|pc[25] ; 0 ; 0 ; +; - riscv_core:core|write ; 0 ; 0 ; +; - riscv_core:core|pc[0] ; 0 ; 0 ; +; - riscv_core:core|pc[1] ; 0 ; 0 ; +; - riscv_core:core|state.0110 ; 0 ; 0 ; +; - riscv_core:core|state.1010 ; 0 ; 0 ; +; - riscv_core:core|state.0010 ; 0 ; 0 ; +; - riscv_core:core|pc[31] ; 0 ; 0 ; +; - led0~0 ; 0 ; 0 ; +; - led2~0 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_char_ready ; 0 ; 0 ; +; - riscv_core:core|writedata[0]~2 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxrx_in_processxx3 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; 0 ; 0 ; +; - bReadData[13]~1 ; 0 ; 0 ; +; - riscv_core:core|state~25 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_clk_en ; 0 ; 0 ; +; - riscv_core:core|state.0000 ; 0 ; 0 ; +; - riscv_core:core|state~26 ; 0 ; 0 ; +; - readaddr~1 ; 0 ; 0 ; +; - riscv_core:core|state~27 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx1 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[3] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[2] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[8] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[7] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[6] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[5] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[4] ; 0 ; 0 ; +; - riscv_core:core|state~28 ; 0 ; 0 ; +; - riscv_core:core|state~29 ; 0 ; 0 ; +; - riscv_core:core|pc[31]~3 ; 0 ; 0 ; +; - riscv_core:core|pc~26 ; 0 ; 0 ; +; - riscv_core:core|pc~28 ; 0 ; 0 ; +; - riscv_core:core|pc~29 ; 0 ; 0 ; +; - riscv_core:core|pc~30 ; 0 ; 0 ; +; - riscv_core:core|Mux5~0 ; 0 ; 0 ; +; - riscv_core:core|Selector247~4 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] ; 0 ; 0 ; +; - riscv_core:core|state~30 ; 0 ; 0 ; +; - riscv_core:core|divclk[4]~0 ; 0 ; 0 ; +; - riscv_core:core|divclk[3]~1 ; 0 ; 0 ; +; - riscv_core:core|divclk[2]~2 ; 0 ; 0 ; +; - riscv_core:core|divclk[0]~3 ; 0 ; 0 ; +; - riscv_core:core|divclk[1]~4 ; 0 ; 0 ; +; - riscv_core:core|pc[0]~33 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; 0 ; 0 ; +; - KEY[3]~_wirecell ; 0 ; 0 ; +; - clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0]~DUPLICATE ; 0 ; 0 ; +; SW[8] ; ; ; +; - led0~0 ; 1 ; 0 ; +; - led2~0 ; 1 ; 0 ; +; - riscv_core:core|Mux57~2 ; 1 ; 0 ; +; - bReadData[8]~21 ; 1 ; 0 ; +; - riscv_core:core|Selector244~2 ; 1 ; 0 ; +; SW[9] ; ; ; +; - led2[3]~1 ; 1 ; 0 ; +; - led2[3]~4 ; 1 ; 0 ; +; - led2~5 ; 1 ; 0 ; +; - led3~0 ; 1 ; 0 ; +; - led4[4]~0 ; 1 ; 0 ; +; - led4~1 ; 1 ; 0 ; +; - led5~0 ; 1 ; 0 ; +; - bReadData[9]~19 ; 1 ; 0 ; +; - riscv_core:core|Mux9~0 ; 1 ; 0 ; +; - riscv_core:core|Mux56~1 ; 1 ; 0 ; +; CLOCK_50 ; ; ; +; KEY[2] ; ; ; +; - bReadData[12]~0 ; 1 ; 0 ; +; - riscv_core:core|Mux6~0 ; 1 ; 0 ; +; - riscv_core:core|Selector248~4 ; 1 ; 0 ; +; SW[2] ; ; ; +; - bReadData[2]~3 ; 0 ; 0 ; +; SW[3] ; ; ; +; - bReadData[3]~4 ; 0 ; 0 ; +; SW[6] ; ; ; +; - bReadData[6]~5 ; 1 ; 0 ; +; SW[4] ; ; ; +; - bReadData[4]~6 ; 0 ; 0 ; +; SW[5] ; ; ; +; - bReadData[5]~7 ; 0 ; 0 ; +; SW[0] ; ; ; +; - riscv_core:core|Mux57~4 ; 1 ; 0 ; +; SW[7] ; ; ; +; - riscv_core:core|Mux18~0 ; 0 ; 0 ; +; - bReadData[7]~20 ; 0 ; 0 ; +; - riscv_core:core|Mux1~3 ; 0 ; 0 ; +; - riscv_core:core|Mux1~4 ; 0 ; 0 ; +; - riscv_core:core|Mux26~4 ; 0 ; 0 ; +; KEY[0] ; ; ; +; - bReadData[10]~28 ; 0 ; 0 ; +; - riscv_core:core|Mux8~0 ; 0 ; 0 ; +; - riscv_core:core|Selector250~4 ; 0 ; 0 ; +; KEY[1] ; ; ; +; - bReadData[11]~30 ; 1 ; 0 ; +; - riscv_core:core|Mux7~0 ; 1 ; 0 ; +; - riscv_core:core|Selector249~4 ; 1 ; 0 ; +; SW[1] ; ; ; +; - riscv_core:core|Mux56~2 ; 0 ; 0 ; ++-----------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ -; KEY[3] ; PIN_Y16 ; 59 ; Sync. clear ; no ; -- ; -- ; -- ; -; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; PLLOUTPUTCOUNTER_X0_Y20_N1 ; 1956 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ; -; comb~1 ; LABCELL_X43_Y29_N27 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; led1[5]~0 ; LABCELL_X55_Y28_N27 ; 38 ; Sync. load ; no ; -- ; -- ; -- ; -; led1[5]~3 ; LABCELL_X55_Y28_N33 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; -; led4[0]~0 ; LABCELL_X55_Y28_N30 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; -; ramaddr[3]~0 ; LABCELL_X42_Y28_N57 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; readaddr~0 ; LABCELL_X55_Y25_N45 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|Selector167~1 ; LABCELL_X42_Y25_N45 ; 2 ; Write enable ; no ; -- ; -- ; -- ; -; riscv_core:core|bReadAddr[11]~0 ; LABCELL_X51_Y25_N3 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[198] ; LABCELL_X40_Y33_N18 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[297] ; LABCELL_X36_Y33_N9 ; 11 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[363] ; LABCELL_X33_Y30_N48 ; 15 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462] ; LABCELL_X29_Y29_N9 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561] ; LABCELL_X27_Y28_N24 ; 19 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[627] ; LABCELL_X30_Y31_N9 ; 30 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726] ; LABCELL_X30_Y35_N42 ; 29 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[825] ; LABCELL_X29_Y32_N18 ; 28 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[891] ; LABCELL_X30_Y40_N18 ; 47 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[990] ; LABCELL_X29_Y45_N18 ; 37 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[99] ; LABCELL_X46_Y33_N42 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|cout_actual ; LABCELL_X33_Y42_N24 ; 7 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|cout_actual ; LABCELL_X36_Y31_N24 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|cout_actual ; LABCELL_X33_Y36_N24 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[198] ; LABCELL_X36_Y34_N30 ; 13 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297] ; LABCELL_X37_Y32_N3 ; 13 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[363] ; LABCELL_X46_Y36_N18 ; 18 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462] ; LABCELL_X42_Y35_N33 ; 19 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[561] ; LABCELL_X42_Y39_N9 ; 19 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[627] ; LABCELL_X36_Y40_N21 ; 29 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726] ; MLABCELL_X34_Y39_N12 ; 35 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[825] ; LABCELL_X36_Y35_N33 ; 31 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[891] ; LABCELL_X36_Y28_N18 ; 40 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[990] ; MLABCELL_X34_Y25_N39 ; 35 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[99] ; LABCELL_X37_Y36_N21 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|cout_actual ; MLABCELL_X47_Y35_N48 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|dstvalue[24]~60 ; LABCELL_X40_Y27_N45 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|dstvalue[2]~0 ; LABCELL_X42_Y28_N42 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|dstvalue[2]~42 ; LABCELL_X53_Y29_N36 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|imm[18]~5 ; LABCELL_X48_Y29_N42 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|imm[19]~4 ; LABCELL_X40_Y27_N0 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|imm[29]~6 ; LABCELL_X40_Y27_N36 ; 13 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|imm[4]~0 ; LABCELL_X42_Y28_N15 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|imm[4]~1 ; LABCELL_X42_Y28_N21 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|pc[0]~33 ; LABCELL_X42_Y27_N39 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|pc[31]~3 ; MLABCELL_X52_Y27_N57 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|rs2[31]~_Duplicate_6 ; FF_X42_Y30_N59 ; 41 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|state.0010 ; FF_X42_Y25_N41 ; 34 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|state.0011 ; FF_X45_Y27_N38 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|state.0100 ; FF_X45_Y27_N35 ; 59 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|state.0101 ; FF_X45_Y27_N23 ; 49 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|writedata[0]~2 ; LABCELL_X42_Y28_N12 ; 69 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|writedata[22]~5 ; LABCELL_X40_Y31_N9 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|writedata[5]~0 ; LABCELL_X40_Y31_N27 ; 16 ; Sync. clear ; no ; -- ; -- ; -- ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+ +; KEY[3] ; PIN_Y16 ; 88 ; Async. clear, Sync. clear ; no ; -- ; -- ; -- ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]~0 ; LABCELL_X55_Y1_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; PLLOUTPUTCOUNTER_X0_Y20_N1 ; 1986 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ; +; comb~1 ; LABCELL_X45_Y16_N27 ; 8 ; Write enable ; no ; -- ; -- ; -- ; +; led2[3]~1 ; LABCELL_X53_Y16_N33 ; 38 ; Sync. load ; no ; -- ; -- ; -- ; +; led2[3]~4 ; LABCELL_X53_Y16_N3 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; +; led4[4]~0 ; LABCELL_X53_Y16_N0 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; +; readaddr[17]~0 ; LABCELL_X36_Y18_N21 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; readaddr~1 ; LABCELL_X40_Y14_N21 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|Selector167~1 ; LABCELL_X48_Y14_N0 ; 2 ; Write enable ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[198] ; LABCELL_X56_Y21_N12 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[297] ; MLABCELL_X47_Y22_N39 ; 11 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[363] ; MLABCELL_X39_Y22_N24 ; 17 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462] ; LABCELL_X40_Y22_N57 ; 18 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561] ; LABCELL_X40_Y24_N24 ; 23 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[627] ; LABCELL_X37_Y24_N57 ; 23 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726] ; LABCELL_X33_Y24_N12 ; 31 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[825] ; LABCELL_X29_Y25_N12 ; 27 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[891] ; LABCELL_X27_Y22_N9 ; 36 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[990] ; LABCELL_X31_Y19_N54 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[99] ; LABCELL_X53_Y21_N15 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|cout_actual ; MLABCELL_X34_Y23_N48 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|cout_actual ; LABCELL_X40_Y21_N48 ; 6 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|cout_actual ; LABCELL_X33_Y28_N18 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[198] ; LABCELL_X42_Y27_N24 ; 10 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297] ; LABCELL_X40_Y28_N9 ; 11 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[363] ; LABCELL_X40_Y31_N57 ; 15 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462] ; LABCELL_X36_Y29_N51 ; 20 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[561] ; LABCELL_X37_Y32_N54 ; 19 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[627] ; LABCELL_X45_Y30_N45 ; 34 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726] ; LABCELL_X48_Y27_N12 ; 37 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[825] ; LABCELL_X45_Y25_N24 ; 28 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[891] ; LABCELL_X48_Y22_N21 ; 44 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[990] ; MLABCELL_X52_Y24_N33 ; 35 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[99] ; LABCELL_X45_Y23_N39 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|cout_actual ; LABCELL_X35_Y20_N24 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|dstvalue[25]~59 ; MLABCELL_X34_Y13_N45 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|dstvalue[3]~0 ; LABCELL_X35_Y18_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|dstvalue[3]~47 ; LABCELL_X40_Y17_N12 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|imm[12]~5 ; LABCELL_X40_Y18_N33 ; 14 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|imm[19]~4 ; LABCELL_X42_Y18_N24 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|imm[27]~6 ; LABCELL_X42_Y18_N30 ; 13 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|imm[4]~0 ; LABCELL_X42_Y18_N45 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|imm[4]~1 ; LABCELL_X42_Y18_N42 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|pc[0]~33 ; LABCELL_X40_Y14_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|pc[31]~3 ; LABCELL_X36_Y13_N21 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|rs2[31]~_Duplicate_6 ; FF_X50_Y17_N35 ; 41 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|state.0010 ; FF_X40_Y17_N50 ; 34 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|state.0011 ; FF_X36_Y13_N59 ; 35 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|state.0100 ; FF_X36_Y13_N56 ; 55 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|state.0101 ; FF_X36_Y13_N53 ; 53 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|writedata[0]~2 ; LABCELL_X42_Y18_N48 ; 69 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|writedata[19]~5 ; LABCELL_X51_Y18_N15 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|writedata[1]~0 ; LABCELL_X51_Y18_N39 ; 16 ; Sync. clear ; no ; -- ; -- ; -- ; +; uartaddr[0]~0 ; LABCELL_X42_Y18_N36 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -3343,7 +3379,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------------------------------------------------------------------+----------------------------+---------+----------------------+------------------+---------------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; +---------------------------------------------------------------------------------+----------------------------+---------+----------------------+------------------+---------------------------+ -; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; PLLOUTPUTCOUNTER_X0_Y20_N1 ; 1956 ; Global Clock ; GCLK0 ; -- ; +; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; PLLOUTPUTCOUNTER_X0_Y20_N1 ; 1986 ; Global Clock ; GCLK0 ; -- ; +---------------------------------------------------------------------------------+----------------------------+---------+----------------------+------------------+---------------------------+ @@ -3352,172 +3388,178 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; Name ; Fan-Out ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; riscv_core:core|instr[12] ; 238 ; +; riscv_core:core|instr[12] ; 246 ; ; riscv_core:core|instr[13] ; 170 ; ; riscv_core:core|Equal0~8 ; 97 ; -; riscv_core:core|rs2[1]~_Duplicate_6 ; 91 ; -; riscv_core:core|rs2[0]~_Duplicate_6 ; 80 ; -; riscv_core:core|rs2[3]~_Duplicate_6DUPLICATE ; 75 ; -; riscv_core:core|imm[3]~DUPLICATE ; 70 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_Num_Sign[0] ; 70 ; +; KEY[3]~input ; 88 ; +; riscv_core:core|rs2[1]~_Duplicate_6DUPLICATE ; 80 ; +; riscv_core:core|imm[1] ; 79 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_Num_Sign[0] ; 71 ; +; riscv_core:core|imm[3] ; 71 ; ; riscv_core:core|writedata[0]~2 ; 69 ; ; riscv_core:core|imm[0] ; 67 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|add_sub_31_result_int[32]~1 ; 66 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[31] ; 64 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[31] ; 65 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[957] ; 61 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[957] ; 61 ; -; KEY[3]~input ; 59 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[924] ; 59 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[924] ; 59 ; -; riscv_core:core|state.0100 ; 59 ; -; riscv_core:core|rs1[31]~_Duplicate_6 ; 58 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[858] ; 55 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[858] ; 55 ; +; riscv_core:core|state.0100 ; 55 ; +; riscv_core:core|state.0101 ; 53 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[792] ; 51 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[792] ; 51 ; -; Equal1~0 ; 51 ; +; riscv_core:core|rs1[31]~_Duplicate_6DUPLICATE ; 49 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[759] ; 49 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[759] ; 49 ; -; riscv_core:core|state.0101 ; 49 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[891] ; 47 ; +; riscv_core:core|rs2[0]~_Duplicate_6DUPLICATE ; 48 ; +; Equal1~1 ; 48 ; ; riscv_core:core|instr[2] ; 47 ; -; riscv_core:core|imm[1]~DUPLICATE ; 45 ; +; riscv_core:core|rs2[3]~_Duplicate_6 ; 46 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[693] ; 45 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[693] ; 45 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[891] ; 44 ; ; riscv_core:core|state.0111 ; 44 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[660] ; 43 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[660] ; 43 ; ; riscv_core:core|rs2[2]~_Duplicate_6 ; 43 ; -; riscv_core:core|instr[14] ; 42 ; +; riscv_core:core|instr[14] ; 43 ; ; riscv_core:core|rs2[31]~_Duplicate_6 ; 41 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[891] ; 40 ; ; riscv_core:core|instr[6] ; 40 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[594] ; 39 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[594] ; 39 ; ; riscv_core:core|state.0110 ; 39 ; -; riscv_core:core|imm[2] ; 38 ; -; riscv_core:core|state.0011 ; 38 ; -; led1[5]~0 ; 38 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[990] ; 37 ; +; led2[3]~1 ; 38 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726] ; 37 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[891] ; 36 ; ; riscv_core:core|state.1010 ; 36 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[528] ; 35 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[528] ; 35 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726] ; 35 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[990] ; 35 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; 35 ; ; riscv_core:core|instr[30] ; 35 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; 34 ; -; riscv_core:core|imm[1] ; 34 ; +; riscv_core:core|state.0011 ; 35 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[627] ; 34 ; +; riscv_core:core|imm[19]~4 ; 34 ; ; riscv_core:core|state.0010 ; 34 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[495] ; 33 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[495] ; 33 ; -; Equal0~6 ; 33 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[825] ; 31 ; -; riscv_core:core|dstvalue[28]~23 ; 31 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[627] ; 30 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[990] ; 32 ; +; riscv_core:core|rs2[0]~_Duplicate_6 ; 32 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726] ; 31 ; +; riscv_core:core|dstvalue[30]~28 ; 31 ; +; Equal0~6 ; 31 ; +; riscv_core:core|rs2[3]~_Duplicate_6DUPLICATE ; 30 ; ; riscv_core:core|pc[31]~3 ; 30 ; -; riscv_core:core|pc[2]~1 ; 30 ; +; riscv_core:core|pc[18]~1 ; 30 ; +; riscv_core:core|instr[31] ; 30 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[429] ; 29 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[429] ; 29 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[627] ; 29 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726] ; 29 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[825] ; 28 ; -; riscv_core:core|dstvalue[2]~42 ; 28 ; -; riscv_core:core|ldaddr[1] ; 28 ; -; riscv_core:core|imm[19]~4 ; 28 ; -; riscv_core:core|rs1[11]~_Duplicate_6 ; 28 ; -; led1[5]~3 ; 28 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[825] ; 28 ; +; riscv_core:core|dstvalue[3]~47 ; 28 ; +; led2[3]~4 ; 28 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[396] ; 27 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[396] ; 27 ; -; riscv_core:core|dstvalue[2]~26 ; 27 ; -; riscv_core:core|dstvalue[2]~25 ; 27 ; -; riscv_core:core|rs2[4]~_Duplicate_6DUPLICATE ; 26 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[825] ; 27 ; +; riscv_core:core|dstvalue[3]~31 ; 27 ; +; riscv_core:core|dstvalue[3]~30 ; 27 ; +; riscv_core:core|rs1[11]~_Duplicate_6 ; 27 ; ; riscv_core:core|instr[5] ; 26 ; -; riscv_core:core|rs1[9]~_Duplicate_6DUPLICATE ; 25 ; -; riscv_core:core|instr[31] ; 25 ; +; riscv_core:core|rs1[29]~_Duplicate_6 ; 25 ; ; riscv_core:core|rs1[20]~_Duplicate_6 ; 25 ; -; riscv_core:core|rs1[29]~_Duplicate_6DUPLICATE ; 24 ; -; readaddr~0 ; 24 ; +; riscv_core:core|rs1[9]~_Duplicate_6DUPLICATE ; 24 ; +; riscv_core:core|rs2[4]~_Duplicate_6DUPLICATE ; 24 ; +; readaddr~1 ; 24 ; ; riscv_core:core|rs1[30]~_Duplicate_6 ; 24 ; ; riscv_core:core|imm[4] ; 24 ; ; riscv_core:core|rs1[7]~_Duplicate_6 ; 24 ; ; riscv_core:core|rs1[21]~_Duplicate_6 ; 24 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[330] ; 23 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[330] ; 23 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561] ; 23 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[627] ; 23 ; ; riscv_core:core|Selector214~5 ; 23 ; ; riscv_core:core|Selector214~4 ; 23 ; ; riscv_core:core|rs1[4]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[13]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[12]~_Duplicate_6 ; 23 ; +; riscv_core:core|rs1[10]~_Duplicate_6 ; 23 ; +; riscv_core:core|rs1[5]~_Duplicate_6 ; 23 ; +; riscv_core:core|rs1[3]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[23]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[22]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[18]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[27]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[25]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[0]~_Duplicate_6 ; 23 ; +; riscv_core:core|imm[2] ; 23 ; ; riscv_core:core|rs1[2]~_Duplicate_6 ; 23 ; -; riscv_core:core|dstvalue[5]~45 ; 22 ; -; riscv_core:core|dstvalue[5]~44 ; 22 ; -; riscv_core:core|rs1[6]~_Duplicate_6 ; 22 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462] ; 21 ; +; riscv_core:core|ldaddr[1]~DUPLICATE ; 22 ; +; riscv_core:core|rs1[19]~_Duplicate_6DUPLICATE ; 22 ; +; riscv_core:core|dstvalue[6]~50 ; 22 ; +; riscv_core:core|dstvalue[6]~49 ; 22 ; +; riscv_core:core|rs1[6]~_Duplicate_6 ; 21 ; ; riscv_core:core|rs1[24]~_Duplicate_6 ; 21 ; ; riscv_core:core|rs1[17]~_Duplicate_6 ; 21 ; ; riscv_core:core|rs1[14]~_Duplicate_6 ; 21 ; ; riscv_core:core|rs1[26]~_Duplicate_6 ; 21 ; +; riscv_core:core|rs1[8]~_Duplicate_6 ; 21 ; ; riscv_core:core|instr[3] ; 21 ; -; riscv_core:core|rs1[28]~_Duplicate_6DUPLICATE ; 20 ; -; riscv_core:core|ldaddr[0] ; 20 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462] ; 20 ; ; riscv_core:core|rs1[15]~_Duplicate_6 ; 20 ; ; riscv_core:core|rs1[1]~_Duplicate_6 ; 20 ; -; riscv_core:core|rs1[10]~_Duplicate_6DUPLICATE ; 19 ; -; riscv_core:core|rs1[8]~_Duplicate_6DUPLICATE ; 19 ; +; riscv_core:core|ldaddr[0]~DUPLICATE ; 19 ; +; riscv_core:core|rs1[28]~_Duplicate_6DUPLICATE ; 19 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[264] ; 19 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[264] ; 19 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462] ; 19 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561] ; 19 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2] ; 19 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[561] ; 19 ; ; riscv_core:core|instr[25] ; 19 ; ; riscv_core:core|rs1[16]~_Duplicate_6 ; 19 ; -; riscv_core:core|rs1[19]~_Duplicate_6DUPLICATE ; 18 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[363] ; 18 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; 18 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462] ; 18 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1] ; 18 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[231] ; 17 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[231] ; 17 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[363] ; 17 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; 17 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[1] ; 17 ; -; riscv_core:core|writedata[22]~3 ; 17 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0] ; 17 ; +; riscv_core:core|writedata[19]~3 ; 17 ; ; riscv_core:core|instr[4] ; 17 ; -; riscv_core:core|rs1[5]~_Duplicate_6DUPLICATE ; 16 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; 16 ; -; riscv_core:core|dstvalue[2]~37 ; 16 ; -; riscv_core:core|dstvalue[2]~36 ; 16 ; -; riscv_core:core|dstvalue[2]~29 ; 16 ; -; riscv_core:core|writedata[5]~0 ; 16 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[3] ; 16 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[5] ; 16 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1]~DUPLICATE ; 15 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[363] ; 15 ; -; riscv_core:core|dstvalue[2]~31 ; 15 ; -; riscv_core:core|dstvalue[2]~30 ; 15 ; +; riscv_core:core|dstvalue[3]~34 ; 16 ; +; riscv_core:core|writedata[1]~0 ; 16 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[28] ; 16 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0]~DUPLICATE ; 15 ; +; riscv_core:core|imm[2]~DUPLICATE ; 15 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[363] ; 15 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; 15 ; +; riscv_core:core|dstvalue[3]~42 ; 15 ; +; riscv_core:core|dstvalue[3]~41 ; 15 ; +; riscv_core:core|dstvalue[3]~36 ; 15 ; +; riscv_core:core|dstvalue[3]~35 ; 15 ; ; riscv_core:core|state.0001 ; 15 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3] ; 15 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[2] ; 15 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; 15 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; 15 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[28] ; 15 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[29] ; 15 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[30] ; 15 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[7] ; 15 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[1] ; 15 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[3] ; 15 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[4] ; 15 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[8] ; 15 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[9] ; 15 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[10] ; 15 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[11] ; 15 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[13] ; 15 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[17] ; 15 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[18] ; 15 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[19] ; 15 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2]~DUPLICATE ; 14 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2] ; 14 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; 14 ; -; riscv_core:core|dstvalue[2]~28 ; 14 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[0] ; 15 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; 14 ; +; riscv_core:core|imm[12]~5 ; 14 ; ; riscv_core:core|Equal7~0 ; 14 ; -; led4[0]~0 ; 14 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; 14 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; 14 ; +; led4[4]~0 ; 14 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; 14 ; ; riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated|Mult0~523 ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[15] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[22] ; 14 ; @@ -3526,33 +3568,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[25] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[26] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[27] ; 14 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[7] ; 14 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[1] ; 14 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[29] ; 14 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[30] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[2] ; 14 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[5] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[6] ; 14 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[8] ; 14 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[11] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[12] ; 14 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[13] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[14] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[16] ; 14 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[17] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[20] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[21] ; 14 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[0] ; 14 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[165] ; 13 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[165] ; 13 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[198] ; 13 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297] ; 13 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0] ; 13 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; 13 ; -; riscv_core:core|dstvalue[2]~1 ; 13 ; +; riscv_core:core|dstvalue[3]~1 ; 13 ; ; riscv_core:core|state.1000 ; 13 ; -; riscv_core:core|imm[29]~6 ; 13 ; -; ramaddr[3]~0 ; 13 ; +; riscv_core:core|imm[27]~6 ; 13 ; +; uartaddr[0]~0 ; 13 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3] ; 13 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2] ; 13 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1] ; 13 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0] ; 13 ; -; riscv_core:core|rs1[3]~_Duplicate_6DUPLICATE ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a0~portb_address_reg3FITTER_CREATED_FF ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a0~portb_address_reg2FITTER_CREATED_FF ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a0~portb_address_reg1FITTER_CREATED_FF ; 12 ; @@ -3563,46 +3600,46 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a0~portb_address_reg1FITTER_CREATED_FF ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a0~portb_address_reg0FITTER_CREATED_FF ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[2] ; 12 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[1] ; 12 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[0] ; 12 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[1] ; 12 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[0] ; 12 ; -; riscv_core:core|dstvalue[24]~60 ; 12 ; -; riscv_core:core|dstvalue[24]~56 ; 12 ; -; riscv_core:core|dstvalue[24]~55 ; 12 ; -; riscv_core:core|dstvalue[24]~54 ; 12 ; -; riscv_core:core|dstvalue[24]~53 ; 12 ; -; riscv_core:core|dstvalue[2]~40 ; 12 ; -; riscv_core:core|dstvalue[2]~38 ; 12 ; -; riscv_core:core|dstvalue[2]~34 ; 12 ; -; riscv_core:core|dstvalue[2]~32 ; 12 ; -; riscv_core:core|dstvalue[2]~12 ; 12 ; -; riscv_core:core|rs2[7]~_Duplicate_6 ; 12 ; +; riscv_core:core|dstvalue[25]~59 ; 12 ; +; riscv_core:core|dstvalue[25]~55 ; 12 ; +; riscv_core:core|dstvalue[25]~54 ; 12 ; +; riscv_core:core|dstvalue[25]~53 ; 12 ; +; riscv_core:core|dstvalue[25]~52 ; 12 ; +; riscv_core:core|dstvalue[3]~45 ; 12 ; +; riscv_core:core|dstvalue[3]~43 ; 12 ; +; riscv_core:core|dstvalue[3]~39 ; 12 ; +; riscv_core:core|dstvalue[3]~37 ; 12 ; +; riscv_core:core|dstvalue[3]~16 ; 12 ; ; riscv_core:core|rs2[6]~_Duplicate_6 ; 12 ; +; riscv_core:core|rs2[5]~_Duplicate_6 ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; 12 ; +; riscv_core:core|rs2[7]~_Duplicate_6DUPLICATE ; 11 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[0] ; 11 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[132] ; 11 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[132] ; 11 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[297] ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[1] ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[0] ; 11 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297] ; 11 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2] ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; 11 ; -; riscv_core:core|Mux26~3 ; 11 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[0] ; 11 ; ; riscv_core:core|rs2[15]~_Duplicate_6 ; 11 ; -; riscv_core:core|dstvalue[2]~0 ; 11 ; -; riscv_core:core|rs1[3]~_Duplicate_6 ; 11 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; 11 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; 11 ; ; riscv_core:core|rs2[14]~_Duplicate_6 ; 11 ; -; riscv_core:core|rs2[13]~_Duplicate_6 ; 11 ; ; riscv_core:core|rs2[12]~_Duplicate_6 ; 11 ; -; riscv_core:core|rs2[10]~_Duplicate_6 ; 11 ; +; riscv_core:core|rs2[11]~_Duplicate_6 ; 11 ; ; riscv_core:core|rs2[9]~_Duplicate_6 ; 11 ; ; riscv_core:core|rs2[8]~_Duplicate_6 ; 11 ; +; riscv_core:core|rs2[1]~_Duplicate_6 ; 11 ; ; led0~0 ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; 11 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; 11 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3] ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; 11 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0] ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; 11 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; 11 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2]~DUPLICATE ; 10 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg3FITTER_CREATED_FF ; 10 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg2FITTER_CREATED_FF ; 10 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg1FITTER_CREATED_FF ; 10 ; @@ -3624,53 +3661,56 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a0~portb_address_reg0FITTER_CREATED_FF ; 10 ; ; SW[9]~input ; 10 ; ; KEY[3]~_wirecell ; 10 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[198] ; 10 ; +; riscv_core:core|Mux26~2 ; 10 ; ; riscv_core:core|rs2[23]~_Duplicate_6 ; 10 ; +; riscv_core:core|dstvalue[3]~0 ; 10 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]~0 ; 10 ; +; riscv_core:core|rs2[30]~_Duplicate_6 ; 10 ; ; riscv_core:core|rs2[29]~_Duplicate_6 ; 10 ; ; riscv_core:core|rs2[22]~_Duplicate_6 ; 10 ; ; riscv_core:core|rs2[21]~_Duplicate_6 ; 10 ; ; riscv_core:core|rs2[20]~_Duplicate_6 ; 10 ; ; riscv_core:core|rs2[19]~_Duplicate_6 ; 10 ; -; riscv_core:core|rs2[17]~_Duplicate_6 ; 10 ; ; riscv_core:core|rs2[16]~_Duplicate_6 ; 10 ; -; riscv_core:core|writedata[22]~4 ; 10 ; -; riscv_core:core|rs2[18]~_Duplicate_6DUPLICATE ; 9 ; -; riscv_core:core|rs2[11]~_Duplicate_6DUPLICATE ; 9 ; -; riscv_core:core|imm[18]~5 ; 9 ; +; riscv_core:core|writedata[19]~4 ; 10 ; +; riscv_core:core|rs2[13]~_Duplicate_6 ; 10 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[198] ; 9 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx1 ; 9 ; ; riscv_core:core|state.0000 ; 9 ; -; riscv_core:core|rs2[28]~_Duplicate_6 ; 9 ; +; riscv_core:core|rs1[31]~_Duplicate_6 ; 9 ; ; riscv_core:core|rs2[27]~_Duplicate_6 ; 9 ; ; riscv_core:core|rs2[26]~_Duplicate_6 ; 9 ; ; riscv_core:core|rs2[25]~_Duplicate_6 ; 9 ; ; riscv_core:core|rs2[24]~_Duplicate_6 ; 9 ; -; riscv_core:core|writedata[22]~5 ; 9 ; +; riscv_core:core|writedata[19]~5 ; 9 ; ; riscv_core:core|writeaddr[1] ; 9 ; ; riscv_core:core|writeaddr[0] ; 9 ; ; riscv_core:core|write ; 9 ; -; riscv_core:core|rs2[5]~_Duplicate_6DUPLICATE ; 8 ; +; riscv_core:core|rs2[18]~_Duplicate_6DUPLICATE ; 8 ; +; riscv_core:core|rs2[10]~_Duplicate_6DUPLICATE ; 8 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[64] ; 8 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[224] ; 8 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|cout_actual ; 8 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[198] ; 8 ; -; riscv_core:core|dstvalue[8]~47 ; 8 ; -; ramaddr[10]~13 ; 8 ; -; ramaddr[9]~12 ; 8 ; -; ramaddr[8]~11 ; 8 ; -; ramaddr[7]~10 ; 8 ; -; ramaddr[6]~9 ; 8 ; -; ramaddr[5]~8 ; 8 ; -; ramaddr[4]~7 ; 8 ; -; ramaddr[3]~6 ; 8 ; -; ramaddr[2]~5 ; 8 ; -; ramaddr[1]~4 ; 8 ; -; ramaddr[0]~3 ; 8 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|Equal0~1 ; 8 ; +; ramaddr[10]~7 ; 8 ; +; ramaddr[9]~6 ; 8 ; +; ramaddr[8]~5 ; 8 ; +; ramaddr[7]~4 ; 8 ; +; ramaddr[6]~3 ; 8 ; +; ramaddr[5]~2 ; 8 ; +; ramaddr[4]~1 ; 8 ; +; ramaddr[3]~0 ; 8 ; +; uartaddr[2]~5 ; 8 ; +; uartaddr[1]~4 ; 8 ; +; uartaddr[0]~3 ; 8 ; ; comb~1 ; 8 ; -; riscv_core:core|imm[11] ; 8 ; -; riscv_core:core|writedata[31]~7 ; 8 ; -; riscv_core:core|writedata[31]~6 ; 8 ; +; riscv_core:core|writedata[27]~7 ; 8 ; +; riscv_core:core|writedata[27]~6 ; 8 ; ; riscv_core:core|Equal3~3 ; 8 ; ; led2~0 ; 8 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; 8 ; -; riscv_core:core|rs2[30]~_Duplicate_6DUPLICATE ; 7 ; +; riscv_core:core|rs2[28]~_Duplicate_6DUPLICATE ; 7 ; +; riscv_core:core|rs2[17]~_Duplicate_6DUPLICATE ; 7 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2]~DUPLICATE ; 7 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a0~portb_address_reg3FITTER_CREATED_FF ; 7 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a0~portb_address_reg2FITTER_CREATED_FF ; 7 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a0~portb_address_reg1FITTER_CREATED_FF ; 7 ; @@ -3678,34 +3718,34 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[128] ; 7 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[32] ; 7 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[160] ; 7 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|cout_actual ; 7 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[224] ; 7 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[256] ; 7 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[320] ; 7 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[66] ; 7 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[66] ; 7 ; -; riscv_core:core|imm[31] ; 7 ; -; riscv_core:core|imm[10] ; 7 ; -; riscv_core:core|imm[6] ; 7 ; -; riscv_core:core|rs1[5]~_Duplicate_6 ; 7 ; -; riscv_core:core|rs1[19]~_Duplicate_6 ; 7 ; -; riscv_core:core|imm[9] ; 7 ; -; riscv_core:core|imm[8] ; 7 ; +; riscv_core:core|Selector241~0 ; 7 ; +; riscv_core:core|Selector244~0 ; 7 ; +; riscv_core:core|imm[11] ; 7 ; +; riscv_core:core|rs2[4]~_Duplicate_6 ; 7 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|add_sub_31_result_int[32]~1 ; 7 ; ; riscv_core:core|imm[30] ; 7 ; ; riscv_core:core|imm[29] ; 7 ; ; riscv_core:core|imm[28] ; 7 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2]~DUPLICATE ; 6 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0]~DUPLICATE ; 6 ; -; SW[7]~input ; 6 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|cout_actual ; 6 ; ; riscv_core:core|Selector125~0 ; 6 ; ; riscv_core:core|Mux26~1 ; 6 ; ; riscv_core:core|Selector249~14 ; 6 ; +; riscv_core:core|dstvalue[3]~33 ; 6 ; ; riscv_core:core|Selector121~0 ; 6 ; ; riscv_core:core|always7~0 ; 6 ; -; riscv_core:core|imm[4]~1 ; 6 ; -; ramaddr[3]~2 ; 6 ; -; ramaddr[3]~1 ; 6 ; +; uartaddr[0]~2 ; 6 ; +; uartaddr[0]~1 ; 6 ; +; riscv_core:core|imm[10] ; 6 ; ; riscv_core:core|imm[7] ; 6 ; -; riscv_core:core|imm[5] ; 6 ; +; riscv_core:core|imm[6] ; 6 ; +; riscv_core:core|imm[9] ; 6 ; +; riscv_core:core|imm[8] ; 6 ; ; riscv_core:core|writedata[14] ; 6 ; ; riscv_core:core|writedata[13] ; 6 ; ; riscv_core:core|writedata[12] ; 6 ; @@ -3713,17 +3753,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|writedata[10] ; 6 ; ; riscv_core:core|writedata[9] ; 6 ; ; riscv_core:core|writedata[8] ; 6 ; -; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|q_a[23] ; 6 ; -; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|q_a[7] ; 6 ; -; riscv_core:core|imm[12] ; 6 ; +; riscv_core:core|imm[13] ; 6 ; ; riscv_core:core|imm[24] ; 6 ; ; riscv_core:core|imm[23] ; 6 ; ; riscv_core:core|imm[20] ; 6 ; -; riscv_core:core|imm[18] ; 6 ; -; riscv_core:core|imm[17] ; 6 ; -; riscv_core:core|imm[16] ; 6 ; -; riscv_core:core|imm[15] ; 6 ; -; riscv_core:core|imm[14] ; 6 ; ; riscv_core:core|imm[27] ; 6 ; ; riscv_core:core|imm[26] ; 6 ; ; riscv_core:core|imm[19] ; 6 ; @@ -3734,33 +3767,52 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|writedata[2] ; 6 ; ; riscv_core:core|writedata[1] ; 6 ; ; riscv_core:core|writedata[0] ; 6 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[256]~DUPLICATE ; 5 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2]~DUPLICATE ; 5 ; -; riscv_core:core|imm[13]~DUPLICATE ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1]~DUPLICATE ; 5 ; +; riscv_core:core|imm[5]~DUPLICATE ; 5 ; +; riscv_core:core|imm[12]~DUPLICATE ; 5 ; +; riscv_core:core|imm[15]~DUPLICATE ; 5 ; +; SW[7]~input ; 5 ; ; SW[8]~input ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[135] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[134] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[133] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[132] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[131] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[130] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[129] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[137] ; 5 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[192] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[69] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[225] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[276] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[260] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[259] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[258] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[225] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[35] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[70] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[274] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[272] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[278] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[258] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288] ; 5 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|cout_actual ; 5 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|cout_actual ; 5 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[332] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|cout_actual ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[338] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[337] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[336] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[335] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[330] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[324] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[322] ; 5 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[99] ; 5 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[99] ; 5 ; -; riscv_core:core|Mux26~6 ; 5 ; -; riscv_core:core|Mux1~0 ; 5 ; -; riscv_core:core|dstvalue[2]~41 ; 5 ; -; riscv_core:core|dstvalue[2]~35 ; 5 ; -; riscv_core:core|dstvalue[2]~27 ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[72] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[351] ; 5 ; +; riscv_core:core|dstvalue[3]~46 ; 5 ; +; riscv_core:core|dstvalue[3]~40 ; 5 ; +; riscv_core:core|dstvalue[3]~32 ; 5 ; +; bReadData[23]~18 ; 5 ; ; riscv_core:core|Equal0~7 ; 5 ; -; riscv_core:core|dstreg[4]~1 ; 5 ; +; riscv_core:core|dstreg[0]~1 ; 5 ; +; riscv_core:core|imm[4]~1 ; 5 ; +; readaddr[17]~0 ; 5 ; ; bReadData[17]~10 ; 5 ; ; bReadData[16]~9 ; 5 ; -; riscv_core:core|rs1[10]~_Duplicate_6 ; 5 ; -; riscv_core:core|rs2[4]~_Duplicate_6 ; 5 ; ; riscv_core:core|writedata[30] ; 5 ; ; riscv_core:core|writedata[29] ; 5 ; ; riscv_core:core|writedata[28] ; 5 ; @@ -3768,6 +3820,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|writedata[26] ; 5 ; ; riscv_core:core|writedata[25] ; 5 ; ; riscv_core:core|writedata[24] ; 5 ; +; riscv_core:core|Mux26~5 ; 5 ; ; riscv_core:core|imm[21] ; 5 ; ; riscv_core:core|Add0~101 ; 5 ; ; riscv_core:core|Add0~97 ; 5 ; @@ -3781,70 +3834,55 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|writedata[18] ; 5 ; ; riscv_core:core|writedata[17] ; 5 ; ; riscv_core:core|writedata[16] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288]~DUPLICATE ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0]~DUPLICATE ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3]~DUPLICATE ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1]~DUPLICATE ; 4 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[257]~DUPLICATE ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[142]~DUPLICATE ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0]~DUPLICATE ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3]~DUPLICATE ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2]~DUPLICATE ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1]~DUPLICATE ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0]~DUPLICATE ; 4 ; +; riscv_core:core|imm[22]~DUPLICATE ; 4 ; +; riscv_core:core|imm[18]~DUPLICATE ; 4 ; +; riscv_core:core|imm[17]~DUPLICATE ; 4 ; +; riscv_core:core|imm[14]~DUPLICATE ; 4 ; ; riscv_core:core|imm[25]~DUPLICATE ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[65] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[65] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[66] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[66] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[135] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[135] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[134] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[134] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[133] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[133] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[132] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[132] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[131] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[131] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[130] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[130] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[129] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[129] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[67] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[67] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[136] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[136] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[171] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[171] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[170] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[170] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[169] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[169] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[167] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[168] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[168] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[167] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[166] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[166] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[165] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[165] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[164] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[164] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[163] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[163] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[162] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[162] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[161] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[161] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[33] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[33] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[68] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[68] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[137] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[137] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[172] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[172] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[34] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[34] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[69] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[69] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[138] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[138] ; 4 ; @@ -3884,27 +3922,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[227] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[226] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[226] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[225] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[225] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[35] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[35] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[70] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[70] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[277] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[277] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[276] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[276] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[275] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[275] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[139] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[139] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[274] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[274] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[273] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[273] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[271] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[272] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[272] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[271] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[174] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[174] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[270] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[270] ; 4 ; @@ -3924,16 +3957,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[264] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[264] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[263] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[278] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[278] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[262] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[262] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[261] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[261] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[260] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[260] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[259] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[259] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[258] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[257] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[258] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[257] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[36] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[36] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[71] ; 4 ; @@ -3967,22 +4001,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[339] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[339] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[338] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[338] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[337] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[337] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[335] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[336] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[336] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[335] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[334] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[334] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[333] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[333] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[332] ; 4 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[332] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[331] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[331] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[330] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[330] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[329] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[329] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[327] ; 4 ; @@ -3994,12 +4024,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[325] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[325] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[324] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[324] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[317] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[323] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[323] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[322] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[322] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[321] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[321] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[29] ; 4 ; @@ -4011,12 +4038,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[0] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[37] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[37] ; 4 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[38] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[73] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[72] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[73] ; 4 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[72] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[141] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[141] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[142] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[142] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[177] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[176] ; 4 ; @@ -4028,10 +4054,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[246] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[280] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[280] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[349] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[349] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[350] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[350] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[351] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[1] ; 4 ; ; riscv_core:core|writedata[31] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~31 ; 4 ; @@ -4040,16 +4065,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~28 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~27 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~25 ; 4 ; +; riscv_core:core|Mux1~0 ; 4 ; ; riscv_core:core|ShiftLeft0~5 ; 4 ; ; riscv_core:core|ShiftLeft1~5 ; 4 ; ; riscv_core:core|ShiftLeft0~3 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~23 ; 4 ; ; riscv_core:core|ShiftRight0~26 ; 4 ; -; riscv_core:core|dstvalue[2]~39 ; 4 ; +; riscv_core:core|dstvalue[3]~44 ; 4 ; ; riscv_core:core|ShiftLeft1~3 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~20 ; 4 ; ; riscv_core:core|ShiftRight1~28 ; 4 ; -; riscv_core:core|dstvalue[2]~33 ; 4 ; +; riscv_core:core|dstvalue[3]~38 ; 4 ; ; riscv_core:core|ShiftLeft1~1 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~16 ; 4 ; ; riscv_core:core|ShiftRight1~17 ; 4 ; @@ -4057,29 +4083,34 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~13 ; 4 ; ; riscv_core:core|ShiftRight0~15 ; 4 ; ; riscv_core:core|dstvalue[7] ; 4 ; -; bReadData[22]~15 ; 4 ; +; bReadData[22]~17 ; 4 ; ; riscv_core:core|writedata[15] ; 4 ; -; bReadData[20]~13 ; 4 ; -; riscv_core:core|Selector252~0 ; 4 ; +; riscv_core:core|Selector252~1 ; 4 ; +; bReadData[24]~14 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~10 ; 4 ; ; riscv_core:core|ShiftRight1~6 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~4 ; 4 ; ; riscv_core:core|ShiftRight0~5 ; 4 ; ; riscv_core:core|divclk[0] ; 4 ; -; riscv_core:core|imm[1]~7 ; 4 ; +; riscv_core:core|imm[3]~7 ; 4 ; ; riscv_core:core|instr[7] ; 4 ; ; riscv_core:core|WideOr20 ; 4 ; ; bReadData[19]~12 ; 4 ; ; bReadData[18]~11 ; 4 ; ; riscv_core:core|instr[22] ; 4 ; -; Equal0~2 ; 4 ; -; riscv_core:core|rs2[5]~_Duplicate_6 ; 4 ; +; bReadData[15]~8 ; 4 ; +; riscv_core:core|instr[20] ; 4 ; +; riscv_core:core|imm[31] ; 4 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; 4 ; ; riscv_core:core|Equal2~0 ; 4 ; ; riscv_core:core|writeaddr[2] ; 4 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[1] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[2] ; 4 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; 4 ; ; riscv_core:core|writedata[7] ; 4 ; ; riscv_core:core|writedata[23] ; 4 ; +; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|q_a[23] ; 4 ; ; riscv_core:core|pc[11] ; 4 ; ; riscv_core:core|pc[10] ; 4 ; ; riscv_core:core|pc[9] ; 4 ; @@ -4112,16 +4143,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|Add0~9 ; 4 ; ; riscv_core:core|Add0~5 ; 4 ; ; riscv_core:core|Add0~1 ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[257]~DUPLICATE ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1]~DUPLICATE ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0]~DUPLICATE ; 3 ; -; riscv_core:core|instr[20]~DUPLICATE ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1]~DUPLICATE ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0]~DUPLICATE ; 3 ; -; riscv_core:core|imm[22]~DUPLICATE ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[67]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[169]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[167]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[166]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[164]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[163]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[162]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[174]~DUPLICATE ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[73]~DUPLICATE ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0]~DUPLICATE ; 3 ; +; riscv_core:core|imm[31]~DUPLICATE ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1]~DUPLICATE ; 3 ; +; riscv_core:core|imm[16]~DUPLICATE ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a5 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a6 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a1 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a2 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5|ram_block6a5 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5|ram_block6a6 ; 3 ; @@ -4130,7 +4168,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a5 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a6 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a1 ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a2 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a7 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a5 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a1 ; 3 ; @@ -4138,19 +4176,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a5 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a6 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a1 ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a2 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a7 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a5 ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a1 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a6 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a7 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a1 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a6 ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a2 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a7 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a1 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a6 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a8 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a7 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a1 ; 3 ; @@ -4161,7 +4199,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; KEY[0]~input ; 3 ; ; KEY[2]~input ; 3 ; ; led2~0_wirecell ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[57] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[100] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[100] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[99] ; 3 ; @@ -4173,11 +4210,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[96] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[58] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[58] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[101] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[101] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[59] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[59] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[102] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[102] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[165] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[161] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[103] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[103] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[206] ; 3 ; @@ -4218,7 +4257,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[105] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[209] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[209] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[256] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cmpr4_aeb_int~0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|op_2~0 ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[314] ; 3 ; @@ -4229,24 +4267,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[312] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[312] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[311] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[310] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[310] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[309] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[309] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[106] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[106] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[308] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[308] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[307] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[307] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[306] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[306] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[305] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[305] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cmpr4_aeb_int~0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|op_2~0 ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[303] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[304] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[304] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[303] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[302] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[302] ; 3 ; @@ -4270,88 +4306,88 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[294] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[293] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[293] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[292] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[292] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[291] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[291] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[290] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[290] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[289] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[289] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[33]~47 ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[315] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[315] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[316] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[316] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[317] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[317] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[318] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[318] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[319] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[2] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[3] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[22] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[27] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[21] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[20] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[28] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[26] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[18] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[15] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[38] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[38] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[51] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[58] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[47] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[53] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[52] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[42] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[40] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[72] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[61] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[43] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[41] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[297]~24 ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[76] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297]~24 ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[82] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[81] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[76] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[88] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[87] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[86] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[75] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[107] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[107] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[118] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[115] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[125] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[119] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[124] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[114] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[111] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[119] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[126] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[111] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[110] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[114] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[115] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462]~13 ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[158] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[154] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[146] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462]~13 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[152] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[148] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[157] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561]~9 ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[184] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[181] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[561]~9 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[185] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[183] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[181] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[211] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[211] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[215] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[218] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726]~3 ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[252] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[251] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[250] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726]~3 ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[249] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[255] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[251] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[281] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[349] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[281] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[286] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[284] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[350] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[352] ; 3 ; -; riscv_core:core|dstvalue[28]~66 ; 3 ; -; riscv_core:core|dstvalue[28]~65 ; 3 ; -; riscv_core:core|dstvalue[28]~64 ; 3 ; -; riscv_core:core|dstvalue[28]~63 ; 3 ; -; riscv_core:core|dstvalue[28]~62 ; 3 ; -; riscv_core:core|dstvalue[28]~61 ; 3 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|always2~0 ; 3 ; +; riscv_core:core|dstvalue[30]~65 ; 3 ; +; riscv_core:core|dstvalue[30]~64 ; 3 ; +; riscv_core:core|dstvalue[30]~63 ; 3 ; +; riscv_core:core|dstvalue[30]~62 ; 3 ; +; riscv_core:core|dstvalue[30]~61 ; 3 ; +; riscv_core:core|dstvalue[30]~60 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~33 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~32 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~26 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~24 ; 3 ; -; riscv_core:core|ShiftLeft0~22 ; 3 ; -; riscv_core:core|ShiftLeft0~21 ; 3 ; -; riscv_core:core|ShiftLeft1~22 ; 3 ; -; riscv_core:core|ShiftLeft1~21 ; 3 ; -; riscv_core:core|ShiftLeft0~19 ; 3 ; +; riscv_core:core|Mux2~0 ; 3 ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ @@ -4360,18 +4396,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+----------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+-------------------------------------------------------------------+ ; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+----------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+-------------------------------------------------------------------+ -; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 2048 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 65536 ; 2048 ; 32 ; -- ; -- ; 65536 ; 8 ; 0 ; test.mif ; M10K_X49_Y27_N0, M10K_X49_Y26_N0, M10K_X41_Y27_N0, M10K_X41_Y26_N0, M10K_X49_Y28_N0, M10K_X38_Y28_N0, M10K_X41_Y28_N0, M10K_X38_Y26_N0 ; Don't care ; New data ; New data ; No - Address Too Wide ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 32 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 1024 ; 32 ; 32 ; -- ; -- ; 1024 ; 1 ; 0 ; None ; M10K_X41_Y25_N0 ; Don't care ; New data ; New data ; No - Single Port Feed Through New Data with Unregistered Data Out ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 11 ; 10 ; 11 ; 10 ; yes ; no ; no ; yes ; 110 ; 11 ; 10 ; 11 ; 10 ; 110 ; 0 ; 10 ; None ; LAB_X34_Y42_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 10 ; 10 ; 10 ; 10 ; yes ; no ; no ; yes ; 100 ; 10 ; 10 ; 10 ; 10 ; 100 ; 0 ; 10 ; None ; LAB_X39_Y31_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 9 ; 12 ; 9 ; 12 ; yes ; no ; no ; yes ; 108 ; 9 ; 12 ; 9 ; 12 ; 108 ; 0 ; 12 ; None ; LAB_X34_Y36_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 8 ; 10 ; 8 ; 10 ; yes ; no ; no ; yes ; 80 ; 8 ; 10 ; 8 ; 10 ; 80 ; 0 ; 10 ; None ; LAB_X34_Y34_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 7 ; 10 ; 7 ; 10 ; yes ; no ; no ; yes ; 70 ; 7 ; 10 ; 7 ; 10 ; 70 ; 0 ; 10 ; None ; LAB_X47_Y33_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 6 ; 12 ; 6 ; 12 ; yes ; no ; no ; yes ; 72 ; 6 ; 12 ; 6 ; 12 ; 72 ; 0 ; 12 ; None ; LAB_X39_Y32_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 5 ; 10 ; 5 ; 10 ; yes ; no ; no ; yes ; 50 ; 5 ; 10 ; 5 ; 10 ; 50 ; 0 ; 10 ; None ; LAB_X34_Y31_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 4 ; 10 ; 4 ; 10 ; yes ; no ; no ; yes ; 40 ; 4 ; 10 ; 4 ; 10 ; 40 ; 0 ; 10 ; None ; LAB_X34_Y37_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 3 ; 12 ; 3 ; 12 ; yes ; no ; no ; yes ; 36 ; 3 ; 12 ; 3 ; 12 ; 36 ; 0 ; 12 ; None ; LAB_X34_Y32_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 10 ; 7 ; 10 ; 7 ; yes ; no ; no ; yes ; 70 ; 10 ; 7 ; 10 ; 7 ; 70 ; 0 ; 7 ; None ; LAB_X39_Y35_N0 ; ; ; ; ; +; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 2048 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 65536 ; 2048 ; 32 ; -- ; -- ; 65536 ; 8 ; 0 ; test.mif ; M10K_X38_Y16_N0, M10K_X38_Y18_N0, M10K_X41_Y15_N0, M10K_X41_Y17_N0, M10K_X41_Y16_N0, M10K_X38_Y15_N0, M10K_X38_Y17_N0, M10K_X41_Y18_N0 ; Don't care ; New data ; New data ; No - Address Too Wide ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 32 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 1024 ; 32 ; 32 ; -- ; -- ; 1024 ; 1 ; 0 ; None ; M10K_X49_Y14_N0 ; Don't care ; New data ; New data ; No - Single Port Feed Through New Data with Unregistered Data Out ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 11 ; 10 ; 11 ; 10 ; yes ; no ; no ; yes ; 110 ; 11 ; 10 ; 11 ; 10 ; 110 ; 0 ; 10 ; None ; LAB_X34_Y21_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 10 ; 10 ; 10 ; 10 ; yes ; no ; no ; yes ; 100 ; 10 ; 10 ; 10 ; 10 ; 100 ; 0 ; 10 ; None ; LAB_X39_Y21_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 9 ; 12 ; 9 ; 12 ; yes ; no ; no ; yes ; 108 ; 9 ; 12 ; 9 ; 12 ; 108 ; 0 ; 12 ; None ; LAB_X34_Y28_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 8 ; 10 ; 8 ; 10 ; yes ; no ; no ; yes ; 80 ; 8 ; 10 ; 8 ; 10 ; 80 ; 0 ; 10 ; None ; LAB_X39_Y27_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 7 ; 10 ; 7 ; 10 ; yes ; no ; no ; yes ; 70 ; 7 ; 10 ; 7 ; 10 ; 70 ; 0 ; 10 ; None ; LAB_X34_Y22_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 6 ; 12 ; 6 ; 12 ; yes ; no ; no ; yes ; 72 ; 6 ; 12 ; 6 ; 12 ; 72 ; 0 ; 12 ; None ; LAB_X39_Y29_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 5 ; 10 ; 5 ; 10 ; yes ; no ; no ; yes ; 50 ; 5 ; 10 ; 5 ; 10 ; 50 ; 0 ; 10 ; None ; LAB_X34_Y26_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 4 ; 10 ; 4 ; 10 ; yes ; no ; no ; yes ; 40 ; 4 ; 10 ; 4 ; 10 ; 40 ; 0 ; 10 ; None ; LAB_X47_Y24_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 3 ; 12 ; 3 ; 12 ; yes ; no ; no ; yes ; 36 ; 3 ; 12 ; 3 ; 12 ; 36 ; 0 ; 12 ; None ; LAB_X47_Y25_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 10 ; 7 ; 10 ; 7 ; yes ; no ; no ; yes ; 70 ; 10 ; 7 ; 10 ; 7 ; 70 ; 0 ; 7 ; None ; LAB_X34_Y20_N0 ; ; ; ; ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+----------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+-------------------------------------------------------------------+ Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. @@ -4399,14 +4435,14 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. +---------------------------------------------+-------------------------+ ; Routing Resource Type ; Usage ; +---------------------------------------------+-------------------------+ -; Block interconnects ; 8,830 / 289,320 ( 3 % ) ; -; C12 interconnects ; 268 / 13,420 ( 2 % ) ; -; C2 interconnects ; 3,408 / 119,108 ( 3 % ) ; -; C4 interconnects ; 1,823 / 56,300 ( 3 % ) ; +; Block interconnects ; 8,941 / 289,320 ( 3 % ) ; +; C12 interconnects ; 94 / 13,420 ( < 1 % ) ; +; C2 interconnects ; 3,192 / 119,108 ( 3 % ) ; +; C4 interconnects ; 1,703 / 56,300 ( 3 % ) ; ; DQS bus muxes ; 0 / 25 ( 0 % ) ; ; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ; ; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ; -; Direct links ; 790 / 289,320 ( < 1 % ) ; +; Direct links ; 917 / 289,320 ( < 1 % ) ; ; Global clocks ; 1 / 16 ( 6 % ) ; ; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ; ; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ; @@ -4462,13 +4498,13 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. ; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ; ; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ; ; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ; -; Local interconnects ; 1,555 / 84,580 ( 2 % ) ; +; Local interconnects ; 1,536 / 84,580 ( 2 % ) ; ; Quadrant clocks ; 0 / 66 ( 0 % ) ; -; R14 interconnects ; 353 / 12,676 ( 3 % ) ; -; R14/C12 interconnect drivers ; 584 / 20,720 ( 3 % ) ; -; R3 interconnects ; 4,128 / 130,992 ( 3 % ) ; -; R6 interconnects ; 6,375 / 266,960 ( 2 % ) ; -; Spine clocks ; 4 / 360 ( 1 % ) ; +; R14 interconnects ; 313 / 12,676 ( 2 % ) ; +; R14/C12 interconnect drivers ; 374 / 20,720 ( 2 % ) ; +; R3 interconnects ; 3,906 / 130,992 ( 3 % ) ; +; R6 interconnects ; 6,099 / 266,960 ( 2 % ) ; +; Spine clocks ; 5 / 360 ( 1 % ) ; ; Wire stub REs ; 0 / 15,858 ( 0 % ) ; +---------------------------------------------+-------------------------+ @@ -4527,9 +4563,9 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. +--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ ; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ; +--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ -; Total Pass ; 204 ; 0 ; 204 ; 0 ; 0 ; 204 ; 204 ; 0 ; 204 ; 204 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 60 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Pass ; 204 ; 0 ; 204 ; 0 ; 0 ; 204 ; 204 ; 0 ; 204 ; 204 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 59 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; Total Inapplicable ; 0 ; 204 ; 0 ; 204 ; 204 ; 0 ; 0 ; 204 ; 0 ; 0 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 144 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; +; Total Inapplicable ; 0 ; 204 ; 0 ; 204 ; 204 ; 0 ; 0 ; 204 ; 0 ; 0 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 145 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; ; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; ADC_CONVST ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; ADC_DIN ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; @@ -4689,9 +4725,7 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. ; GPIO[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; -; GPIO[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; -; GPIO[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; @@ -4720,6 +4754,8 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. ; GPIO[33] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[34] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[35] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; GPIO[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; GPIO[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; KEY[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; SW[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; SW[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; @@ -4782,118 +4818,118 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. +----------------------------------------------------------------------------+----------------------------------------------------------------------------+-------------------+ ; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; +----------------------------------------------------------------------------+----------------------------------------------------------------------------+-------------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 55.4 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 60.1 ; +----------------------------------------------------------------------------+----------------------------------------------------------------------------+-------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer. -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing Details ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ -; Source Register ; Destination Register ; Delay Added in ns ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.959 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.894 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.877 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.877 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|dffe3a[1] ; 0.865 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|dffe3a[1] ; 0.800 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|dffe3a[1] ; 0.758 ; -; riscv_core:core|imm[11] ; HEX0[0] ; 0.685 ; -; riscv_core:core|rs2[0]~_Duplicate_6 ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFQuotient[30] ; 0.620 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.578 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.557 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.544 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.540 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[73] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a11~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.494 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[28] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a9~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.494 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.474 ; -; riscv_core:core|rs1[12]~_Duplicate_6 ; HEX0[0] ; 0.465 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.456 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.447 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.447 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.447 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.447 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.438 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; riscv_core:core|dstvalue[12] ; 0.401 ; -; riscv_core:core|instr[20] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a15~porta_address_reg0 ; 0.400 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.399 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; riscv_core:core|dstvalue[12] ; 0.398 ; -; riscv_core:core|instr[22] ; riscv_core:core|imm[2] ; 0.383 ; -; riscv_core:core|divclk[0] ; riscv_core:core|divclk[2] ; 0.382 ; -; riscv_core:core|divclk[1] ; riscv_core:core|divclk[2] ; 0.381 ; -; riscv_core:core|rs2[12]~_Duplicate_6 ; riscv_core:core|writedata[28] ; 0.381 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.379 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.379 ; -; riscv_core:core|imm[5] ; HEX0[0] ; 0.376 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; riscv_core:core|dstvalue[12] ; 0.370 ; -; riscv_core:core|state.0111 ; riscv_core:core|dstvalue[6] ; 0.362 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; riscv_core:core|dstvalue[12] ; 0.360 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.359 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.350 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; riscv_core:core|dstvalue[12] ; 0.349 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.347 ; -; riscv_core:core|rs2[20]~_Duplicate_6 ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[20] ; 0.341 ; -; riscv_core:core|dstvalue[15] ; riscv_core:core|dstvalue[15] ; 0.338 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.335 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.335 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[324] ; 0.334 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[177] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a11~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.333 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.333 ; -; riscv_core:core|imm[4] ; HEX0[0] ; 0.333 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.330 ; -; riscv_core:core|dstvalue[7] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a7~porta_datain_reg0 ; 0.317 ; -; riscv_core:core|state.0110 ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a7~porta_datain_reg0 ; 0.317 ; -; riscv_core:core|state.0000 ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a7~porta_datain_reg0 ; 0.317 ; -; riscv_core:core|state.0001 ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a7~porta_datain_reg0 ; 0.317 ; -; riscv_core:core|dstvalue[12] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a12~porta_datain_reg0 ; 0.316 ; -; riscv_core:core|dstvalue[10] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a10~porta_datain_reg0 ; 0.316 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; 0.316 ; -; riscv_core:core|dstvalue[8] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a8~porta_datain_reg0 ; 0.315 ; -; riscv_core:core|instr[9] ; riscv_core:core|dstreg[2] ; 0.314 ; -; riscv_core:core|pc[1] ; riscv_core:core|ldaddr[1] ; 0.314 ; -; riscv_core:core|dstvalue[2] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a2~porta_datain_reg0 ; 0.314 ; -; riscv_core:core|dstvalue[5] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a5~porta_datain_reg0 ; 0.314 ; -; riscv_core:core|rs1[30]~_Duplicate_6 ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[1] ; 0.313 ; -; riscv_core:core|rs2[23]~_Duplicate_6 ; riscv_core:core|writedata[31] ; 0.313 ; -; riscv_core:core|imm[6] ; HEX0[0] ; 0.310 ; -; riscv_core:core|dstvalue[3] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a3~porta_datain_reg0 ; 0.309 ; -; riscv_core:core|dstvalue[6] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_datain_reg0 ; 0.308 ; -; riscv_core:core|dstvalue[11] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a11~porta_datain_reg0 ; 0.308 ; -; riscv_core:core|dstvalue[9] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a9~porta_datain_reg0 ; 0.307 ; -; riscv_core:core|instr[31] ; riscv_core:core|imm[31] ; 0.306 ; -; riscv_core:core|dstvalue[4] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a4~porta_datain_reg0 ; 0.306 ; -; riscv_core:core|imm[7] ; HEX0[0] ; 0.301 ; -; riscv_core:core|imm[9] ; HEX0[0] ; 0.301 ; -; riscv_core:core|imm[8] ; HEX0[0] ; 0.299 ; -; riscv_core:core|imm[3] ; HEX0[0] ; 0.297 ; -; riscv_core:core|pc[0] ; riscv_core:core|ldaddr[0] ; 0.296 ; -; riscv_core:core|state.0011 ; riscv_core:core|dstvalue[6] ; 0.294 ; -; riscv_core:core|state.0101 ; riscv_core:core|dstvalue[6] ; 0.294 ; -; riscv_core:core|instr[6] ; riscv_core:core|imm[5] ; 0.292 ; -; riscv_core:core|state.0100 ; riscv_core:core|dstvalue[6] ; 0.288 ; -; riscv_core:core|pc[2] ; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a0~porta_address_reg0 ; 0.284 ; -; riscv_core:core|instr[24] ; riscv_core:core|imm[4] ; 0.281 ; -; riscv_core:core|rs1[27]~_Duplicate_6 ; HEX0[0] ; 0.278 ; -; riscv_core:core|imm[2] ; HEX0[0] ; 0.269 ; -; riscv_core:core|divclk[2] ; riscv_core:core|dstvalue[1] ; 0.261 ; -; riscv_core:core|dstvalue[0] ; riscv_core:core|dstvalue[0] ; 0.256 ; -; riscv_core:core|divclk[4] ; riscv_core:core|dstvalue[1] ; 0.249 ; -; readaddr[14] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[27] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[22] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[21] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[20] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[18] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[17] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[16] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[15] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[19] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[24] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[23] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[25] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.864 ; +; riscv_core:core|divclk[3] ; riscv_core:core|dstvalue[31] ; 0.811 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.808 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.784 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.784 ; +; riscv_core:core|divclk[2] ; riscv_core:core|dstvalue[31] ; 0.763 ; +; riscv_core:core|divclk[1] ; riscv_core:core|dstvalue[31] ; 0.735 ; +; riscv_core:core|divclk[0] ; riscv_core:core|dstvalue[31] ; 0.719 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.708 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.674 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.629 ; +; riscv_core:core|divclk[4] ; riscv_core:core|dstvalue[31] ; 0.597 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.586 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.571 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.537 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.504 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.504 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.444 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.444 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.444 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.431 ; +; riscv_core:core|dstvalue[31] ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|instr[13] ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|state.1000 ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|state.1010 ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|instr[12] ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|instr[14] ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|state.0111 ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|state.0001 ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a7~porta_address_reg0 ; 0.409 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.402 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.402 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.402 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.402 ; +; riscv_core:core|rs1[13]~_Duplicate_6 ; riscv_core:core|dstvalue[14] ; 0.397 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.390 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; riscv_core:core|dstvalue[12] ; 0.369 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.366 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.364 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx1 ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.363 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; riscv_core:core|dstvalue[12] ; 0.363 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[3] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.352 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.351 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.349 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.349 ; +; riscv_core:core|dstvalue[15] ; riscv_core:core|dstvalue[15] ; 0.347 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.340 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.340 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.338 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.337 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.337 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; 0.335 ; +; riscv_core:core|rs2[11]~_Duplicate_6 ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[11] ; 0.335 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[324] ; 0.334 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.334 ; +; riscv_core:core|rs2[0]~_Duplicate_6 ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[30] ; 0.331 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; 0.331 ; +; riscv_core:core|rs1[14]~_Duplicate_6 ; riscv_core:core|dstvalue[14] ; 0.329 ; +; riscv_core:core|dstvalue[7] ; riscv_core:core|dstvalue[7] ; 0.327 ; +; riscv_core:core|instr[7] ; riscv_core:core|dstreg[0] ; 0.324 ; +; riscv_core:core|pc[2] ; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a0~porta_address_reg0 ; 0.320 ; +; riscv_core:core|pc[0] ; riscv_core:core|ldaddr[0] ; 0.318 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; 0.315 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[2] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.314 ; +; riscv_core:core|state.0011 ; riscv_core:core|dstvalue[31] ; 0.313 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] ; 0.312 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] ; 0.312 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] ; 0.312 ; +; riscv_core:core|pc[1] ; riscv_core:core|ldaddr[1] ; 0.311 ; +; riscv_core:core|state.0100 ; riscv_core:core|dstvalue[31] ; 0.299 ; +; riscv_core:core|state.0101 ; riscv_core:core|dstvalue[31] ; 0.299 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] ; 0.298 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] ; 0.298 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] ; 0.298 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; 0.298 ; +; riscv_core:core|readreg[1] ; riscv_core:core|dstreg[1] ; 0.298 ; +; riscv_core:core|readreg[3] ; riscv_core:core|dstreg[3] ; 0.298 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxrx_in_processxx3 ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_char_ready ; 0.295 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] ; 0.295 ; +; riscv_core:core|readreg[2] ; riscv_core:core|dstreg[2] ; 0.283 ; +; riscv_core:core|readreg[0] ; riscv_core:core|dstreg[0] ; 0.283 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a9~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.282 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.274 ; +; riscv_core:core|rs1[15]~_Duplicate_6 ; HEX0[0] ; 0.256 ; +; SW[1] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a1~porta_datain_reg0 ; riscv_core:core|dstvalue[1] ; 0.249 ; +; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a1~porta_we_reg ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[24] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[14] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[18] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[20] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[17] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[21] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[22] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[16] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[23] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[25] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[26] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[27] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[15] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[19] ; riscv_core:core|dstvalue[1] ; 0.249 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ Note: This table only shows the top 100 path(s) that have the largest delay added for hold. @@ -4912,9 +4948,12 @@ Warning (205009): Dummy RLC values generated in IBIS model files for device 5CSE Info (184020): Starting Fitter periphery placement operations Warning (205009): Dummy RLC values generated in IBIS model files for device 5CSEMA5 with package FBGA and pin count 896 Info (11191): Automatically promoted 1 clock (1 global) - Info (11162): clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 with 1878 fanout uses global clock CLKCTRL_G0 + Info (11162): clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 with 1906 fanout uses global clock CLKCTRL_G0 Warning (205009): Dummy RLC values generated in IBIS model files for device 5CSEMA5 with package FBGA and pin count 896 Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity altera_std_synchronizer + Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332104): Reading SDC File: 'de1_riscv.SDC' Warning (332049): Ignored create_clock at de1_riscv.sdc(20): Time value "1.536 MH" is not valid Info (332050): create_clock -period "1.536 MH" -name clk_audbck [get_ports AUD_BCLK] @@ -4975,17 +5014,17 @@ Warning (170052): Fitter has implemented the following 103 RAMs using MLAB locat Info (170241): For more information about RAMs, refer to the Fitter RAM Summary report. Info (170056): Fitter has implemented the following 103 RAMs using MLAB locations, which will have the same paused read capabilities as dedicated RAM locations Info (170241): For more information about RAMs, refer to the Fitter RAM Summary report. -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:05 +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:06 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:13 +Info (170192): Fitter placement operations ending: elapsed time is 00:00:14 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 2% of the available device resources - Info (170196): Router estimated peak interconnect usage is 28% of the available device resources in the region that extends from location X33_Y23 to location X44_Y34 + Info (170196): Router estimated peak interconnect usage is 28% of the available device resources in the region that extends from location X33_Y11 to location X44_Y22 Info (170194): Fitter routing operations ending: elapsed time is 00:00:16 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (11888): Total time spent on timing analysis during the Fitter is 9.48 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 10.22 seconds. Info (334003): Started post-fitting delay annotation Warning (334000): Timing characteristics of device 5CSEMA5F31C6 are preliminary Info (334004): Delay annotation completed successfully @@ -5023,9 +5062,7 @@ Warning (169064): Following 60 pins have no output enable or a GND or VCC output Info (169065): Pin GPIO[2] has a permanently disabled output enable Info (169065): Pin GPIO[3] has a permanently disabled output enable Info (169065): Pin GPIO[4] has a permanently disabled output enable - Info (169065): Pin GPIO[5] has a permanently disabled output enable Info (169065): Pin GPIO[6] has a permanently disabled output enable - Info (169065): Pin GPIO[7] has a permanently disabled output enable Info (169065): Pin GPIO[8] has a permanently disabled output enable Info (169065): Pin GPIO[9] has a permanently disabled output enable Info (169065): Pin GPIO[10] has a permanently disabled output enable @@ -5054,12 +5091,14 @@ Warning (169064): Following 60 pins have no output enable or a GND or VCC output Info (169065): Pin GPIO[33] has a permanently disabled output enable Info (169065): Pin GPIO[34] has a permanently disabled output enable Info (169065): Pin GPIO[35] has a permanently disabled output enable + Info (169065): Pin GPIO[5] has a permanently enabled output enable + Info (169065): Pin GPIO[7] has a permanently disabled output enable Info (144001): Generated suppressed messages file D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.fit.smsg Info: Quartus II 64-Bit Fitter was successful. 0 errors, 29 warnings - Info: Peak virtual memory: 2325 megabytes - Info: Processing ended: Fri Aug 27 17:23:11 2021 - Info: Elapsed time: 00:01:56 - Info: Total CPU time (on all processors): 00:02:33 + Info: Peak virtual memory: 2323 megabytes + Info: Processing ended: Sat Aug 28 10:55:54 2021 + Info: Elapsed time: 00:01:57 + Info: Total CPU time (on all processors): 00:02:34 +----------------------------+ diff --git a/examples/hdl4se_riscv/de1/de1_riscv.fit.summary b/examples/hdl4se_riscv/de1/de1_riscv.fit.summary index 3fc28c7..45b60ee 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.fit.summary +++ b/examples/hdl4se_riscv/de1/de1_riscv.fit.summary @@ -1,12 +1,12 @@ -Fitter Status : Successful - Fri Aug 27 17:23:08 2021 +Fitter Status : Successful - Sat Aug 28 10:55:51 2021 Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version Revision Name : de1_riscv Top-level Entity Name : de1_riscv Family : Cyclone V Device : 5CSEMA5F31C6 Timing Models : Preliminary -Logic utilization (in ALMs) : 2,468 / 32,070 ( 8 % ) -Total registers : 1833 +Logic utilization (in ALMs) : 2,494 / 32,070 ( 8 % ) +Total registers : 1863 Total pins : 204 / 457 ( 45 % ) Total virtual pins : 0 Total block memory bits : 66,560 / 4,065,280 ( 2 % ) diff --git a/examples/hdl4se_riscv/de1/de1_riscv.flow.rpt b/examples/hdl4se_riscv/de1/de1_riscv.flow.rpt index 0e81bb7..7ab1e81 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.flow.rpt +++ b/examples/hdl4se_riscv/de1/de1_riscv.flow.rpt @@ -1,5 +1,5 @@ Flow report for de1_riscv -Fri Aug 27 17:24:01 2021 +Sat Aug 28 11:02:31 2021 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -40,25 +40,25 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+---------------------------------------------+ -; Flow Status ; Successful - Fri Aug 27 17:23:28 2021 ; +; Flow Status ; Successful - Sat Aug 28 11:02:31 2021 ; ; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ; ; Revision Name ; de1_riscv ; ; Top-level Entity Name ; de1_riscv ; ; Family ; Cyclone V ; ; Device ; 5CSEMA5F31C6 ; ; Timing Models ; Preliminary ; -; Logic utilization (in ALMs) ; 2,468 / 32,070 ( 8 % ) ; -; Total registers ; 1833 ; -; Total pins ; 204 / 457 ( 45 % ) ; +; Logic utilization (in ALMs) ; N/A ; +; Total registers ; 1636 ; +; Total pins ; 204 ; ; Total virtual pins ; 0 ; -; Total block memory bits ; 66,560 / 4,065,280 ( 2 % ) ; -; Total DSP Blocks ; 10 / 87 ( 11 % ) ; +; Total block memory bits ; 67,296 ; +; Total DSP Blocks ; 10 ; ; Total HSSI RX PCSs ; 0 ; ; Total HSSI PMA RX Deserializers ; 0 ; ; Total HSSI TX PCSs ; 0 ; ; Total HSSI TX Channels ; 0 ; -; Total PLLs ; 1 / 6 ( 17 % ) ; -; Total DLLs ; 0 / 4 ( 0 % ) ; +; Total PLLs ; 1 ; +; Total DLLs ; 0 ; +---------------------------------+---------------------------------------------+ @@ -67,7 +67,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 08/27/2021 17:20:52 ; +; Start date & time ; 08/28/2021 11:02:08 ; ; Main task ; Compilation ; ; Revision Name ; de1_riscv ; +-------------------+---------------------+ @@ -78,7 +78,7 @@ applicable agreement for further details. +-------------------------------------+---------------------------------------+---------------+--------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+---------------------------------------+---------------+--------------+------------+ -; COMPILER_SIGNATURE_ID ; 621136229624.163005605235460 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 621136229624.163011972824564 ; -- ; -- ; -- ; ; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ; ; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ; ; IP_TOOL_ENV ; mwpim ; -- ; clk100M_0002 ; -- ; @@ -129,38 +129,29 @@ applicable agreement for further details. +-------------------------------------+---------------------------------------+---------------+--------------+------------+ -+-------------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:21 ; 1.0 ; 670 MB ; 00:00:20 ; -; Fitter ; 00:01:53 ; 1.4 ; 2325 MB ; 00:02:30 ; -; Assembler ; 00:00:15 ; 1.0 ; 661 MB ; 00:00:15 ; -; TimeQuest Timing Analyzer ; 00:00:32 ; 1.3 ; 1135 MB ; 00:00:41 ; -; Total ; 00:03:01 ; -- ; -- ; 00:03:46 ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:22 ; 1.0 ; 670 MB ; 00:00:21 ; +; Total ; 00:00:22 ; -- ; -- ; 00:00:21 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ -+----------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+---------------------------+------------------+-----------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+---------------------------+------------------+-----------+------------+----------------+ -; Analysis & Synthesis ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ; -; Fitter ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ; -; Assembler ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ; -; TimeQuest Timing Analyzer ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ; -+---------------------------+------------------+-----------+------------+----------------+ ++-----------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ; ++----------------------+------------------+-----------+------------+----------------+ ------------ ; Flow Log ; ------------ quartus_map --read_settings_files=on --write_settings_files=off de1_riscv -c de1_riscv -quartus_fit --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv -quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv -quartus_sta de1_riscv -c de1_riscv diff --git a/examples/hdl4se_riscv/de1/de1_riscv.jdi b/examples/hdl4se_riscv/de1/de1_riscv.jdi index 0dd59e7..b91d504 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.jdi +++ b/examples/hdl4se_riscv/de1/de1_riscv.jdi @@ -1,6 +1,6 @@ - + diff --git a/examples/hdl4se_riscv/de1/de1_riscv.map.rpt b/examples/hdl4se_riscv/de1/de1_riscv.map.rpt index 813b3b0..c58c872 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.map.rpt +++ b/examples/hdl4se_riscv/de1/de1_riscv.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for de1_riscv -Fri Aug 27 17:21:13 2021 +Sat Aug 28 11:02:31 2021 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -17,54 +17,60 @@ Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version 9. Analysis & Synthesis DSP Block Usage Summary 10. Analysis & Synthesis IP Cores Summary 11. State Machine - |de1_riscv|riscv_core:core|state - 12. Registers Removed During Synthesis - 13. General Register Statistics - 14. Inverted Register Statistics - 15. Registers Packed Into Inferred Megafunctions - 16. Multiplexer Restructuring Statistics (Restructuring Performed) - 17. Source assignments for regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated - 18. Source assignments for ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated - 19. Source assignments for riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider - 20. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider - 21. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 - 22. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 - 23. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 - 24. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 - 25. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 - 26. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 - 27. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 - 28. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 - 29. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 - 30. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 - 31. Parameter Settings for User Entity Instance: clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i - 32. Parameter Settings for User Entity Instance: regfile:regs|altsyncram:altsyncram_component - 33. Parameter Settings for User Entity Instance: ram8kb:ram|altsyncram:altsyncram_component - 34. Parameter Settings for User Entity Instance: riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component - 35. Parameter Settings for User Entity Instance: riscv_core:core|suber:sub|lpm_add_sub:LPM_ADD_SUB_component - 36. Parameter Settings for User Entity Instance: riscv_core:core|mult:mul|lpm_mult:lpm_mult_component - 37. Parameter Settings for User Entity Instance: riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component - 38. Parameter Settings for User Entity Instance: riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component - 39. Parameter Settings for User Entity Instance: riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component - 40. Parameter Settings for User Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component - 41. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 - 42. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 - 43. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 - 44. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 - 45. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 - 46. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 - 47. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 - 48. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 - 49. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 - 50. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 - 51. altsyncram Parameter Settings by Entity Instance - 52. lpm_mult Parameter Settings by Entity Instance - 53. altshift_taps Parameter Settings by Entity Instance - 54. Port Connectivity Checks: "riscv_core:core|mulsu:mul_su" - 55. Port Connectivity Checks: "riscv_core:core|mult:mul" - 56. Port Connectivity Checks: "riscv_core:core" - 57. Port Connectivity Checks: "clk100M:clk100" - 58. Elapsed Time Per Partition - 59. Analysis & Synthesis Messages + 12. Registers Protected by Synthesis + 13. Registers Removed During Synthesis + 14. Removed Registers Triggering Further Register Optimizations + 15. General Register Statistics + 16. Inverted Register Statistics + 17. Registers Packed Into Inferred Megafunctions + 18. Multiplexer Restructuring Statistics (Restructuring Performed) + 19. Source assignments for altera_uart:uart + 20. Source assignments for altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer + 21. Source assignments for regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated + 22. Source assignments for ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated + 23. Source assignments for riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider + 24. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider + 25. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 + 26. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 + 27. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 + 28. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 + 29. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 + 30. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 + 31. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 + 32. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 + 33. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 + 34. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 + 35. Parameter Settings for User Entity Instance: clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i + 36. Parameter Settings for User Entity Instance: altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer + 37. Parameter Settings for User Entity Instance: regfile:regs|altsyncram:altsyncram_component + 38. Parameter Settings for User Entity Instance: ram8kb:ram|altsyncram:altsyncram_component + 39. Parameter Settings for User Entity Instance: riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component + 40. Parameter Settings for User Entity Instance: riscv_core:core|suber:sub|lpm_add_sub:LPM_ADD_SUB_component + 41. Parameter Settings for User Entity Instance: riscv_core:core|mult:mul|lpm_mult:lpm_mult_component + 42. Parameter Settings for User Entity Instance: riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component + 43. Parameter Settings for User Entity Instance: riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component + 44. Parameter Settings for User Entity Instance: riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component + 45. Parameter Settings for User Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component + 46. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 + 47. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 + 48. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 + 49. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 + 50. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 + 51. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 + 52. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 + 53. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 + 54. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 + 55. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 + 56. altsyncram Parameter Settings by Entity Instance + 57. lpm_mult Parameter Settings by Entity Instance + 58. altshift_taps Parameter Settings by Entity Instance + 59. Port Connectivity Checks: "riscv_core:core|mulsu:mul_su" + 60. Port Connectivity Checks: "riscv_core:core|mult:mul" + 61. Port Connectivity Checks: "riscv_core:core" + 62. Port Connectivity Checks: "altera_uart:uart" + 63. Port Connectivity Checks: "clk100M:clk100" + 64. Elapsed Time Per Partition + 65. Analysis & Synthesis Messages @@ -90,13 +96,13 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Fri Aug 27 17:21:13 2021 ; +; Analysis & Synthesis Status ; Successful - Sat Aug 28 11:02:31 2021 ; ; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ; ; Revision Name ; de1_riscv ; ; Top-level Entity Name ; de1_riscv ; ; Family ; Cyclone V ; ; Logic utilization (in ALMs) ; N/A ; -; Total registers ; 1608 ; +; Total registers ; 1636 ; ; Total pins ; 204 ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 67,296 ; @@ -215,97 +221,99 @@ applicable agreement for further details. +----------------------------+-------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------------+---------+ -; ../verilog/riscv_core.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core.v ; ; -; ram/ram8kb.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/ram/ram8kb.v ; ; -; regfile/regfile.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v ; ; -; alu/mult.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult.v ; ; -; alu/mult_s.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult_s.v ; ; -; alu/div.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div.v ; ; -; alu/div_s.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v ; ; -; alu/adder.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v ; ; -; alu/suber.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/suber.v ; ; -; alu/mulsu.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v ; ; -; clk/clk100M.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M.v ; clk100M ; -; clk/clk100M/clk100M_0002.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v ; clk100M ; -; de1_riscv.v ; yes ; Auto-Found Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.v ; ; -; altera_pll.v ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altera_pll.v ; ; -; altsyncram.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf ; ; -; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; -; lpm_mux.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc ; ; -; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc ; ; -; aglobal131.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc ; ; -; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ; -; altrom.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altrom.inc ; ; -; altram.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altram.inc ; ; -; altdpram.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc ; ; -; db/altsyncram_nco1.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_nco1.tdf ; ; -; db/altsyncram_bdq1.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_bdq1.tdf ; ; -; test.mif ; yes ; Auto-Found Memory Initialization File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/test.mif ; ; -; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ; -; addcore.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/addcore.inc ; ; -; look_add.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/look_add.inc ; ; -; bypassff.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/bypassff.inc ; ; -; altshift.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altshift.inc ; ; -; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ; -; db/add_sub_tih.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/add_sub_tih.tdf ; ; -; db/add_sub_ujh.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/add_sub_ujh.tdf ; ; -; lpm_mult.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mult.tdf ; ; -; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; -; multcore.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/multcore.inc ; ; -; db/mult_b8n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_b8n.v ; ; -; db/mult_81n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_81n.v ; ; -; db/mult_61n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_61n.v ; ; -; lpm_divide.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_divide.tdf ; ; -; abs_divider.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/abs_divider.inc ; ; -; sign_div_unsign.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/sign_div_unsign.inc ; ; -; db/lpm_divide_2jt.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/lpm_divide_2jt.tdf ; ; -; db/sign_div_unsign_8ai.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/sign_div_unsign_8ai.tdf ; ; -; db/alt_u_div_nlf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/alt_u_div_nlf.tdf ; ; -; db/lpm_divide_s4t.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/lpm_divide_s4t.tdf ; ; -; db/sign_div_unsign_2sh.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/sign_div_unsign_2sh.tdf ; ; -; db/alt_u_div_5eg.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/alt_u_div_5eg.tdf ; ; -; altshift_taps.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altshift_taps.tdf ; ; -; lpm_counter.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.inc ; ; -; lpm_compare.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_compare.inc ; ; -; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_constant.inc ; ; -; db/shift_taps_7l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_7l21.tdf ; ; -; db/altsyncram_kr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_kr91.tdf ; ; -; db/cntr_8jf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_8jf.tdf ; ; -; db/cmpr_c9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_c9c.tdf ; ; -; db/shift_taps_hm21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_hm21.tdf ; ; -; db/altsyncram_9u91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_9u91.tdf ; ; -; db/cntr_9jf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_9jf.tdf ; ; -; db/shift_taps_gm21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_gm21.tdf ; ; -; db/altsyncram_7u91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_7u91.tdf ; ; -; db/shift_taps_bl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_bl21.tdf ; ; -; db/altsyncram_rr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_rr91.tdf ; ; -; db/cntr_0if.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_0if.tdf ; ; -; db/shift_taps_9l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_9l21.tdf ; ; -; db/altsyncram_lr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_lr91.tdf ; ; -; db/cntr_uhf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_uhf.tdf ; ; -; db/shift_taps_cl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_cl21.tdf ; ; -; db/altsyncram_hr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_hr91.tdf ; ; -; db/cntr_thf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_thf.tdf ; ; -; db/cmpr_b9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_b9c.tdf ; ; -; db/shift_taps_dl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_dl21.tdf ; ; -; db/altsyncram_mr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_mr91.tdf ; ; -; db/cntr_shf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_shf.tdf ; ; -; db/shift_taps_4l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_4l21.tdf ; ; -; db/altsyncram_dr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_dr91.tdf ; ; -; db/cntr_rhf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_rhf.tdf ; ; -; db/shift_taps_3l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_3l21.tdf ; ; -; db/altsyncram_9r91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_9r91.tdf ; ; -; db/cntr_phf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_phf.tdf ; ; -; db/shift_taps_5l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_5l21.tdf ; ; -; db/altsyncram_br91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_br91.tdf ; ; -; db/cntr_ohf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_ohf.tdf ; ; -; db/cmpr_a9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_a9c.tdf ; ; -+----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------------+---------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+---------+ +; de1_riscv_v2.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv_v2.v ; ; +; ../verilog/riscv_core.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core.v ; ; +; uart/altera_uart.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/uart/altera_uart.v ; ; +; ram/ram8kb.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/ram/ram8kb.v ; ; +; regfile/regfile.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v ; ; +; alu/mult.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult.v ; ; +; alu/mult_s.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult_s.v ; ; +; alu/div.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div.v ; ; +; alu/div_s.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v ; ; +; alu/adder.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v ; ; +; alu/suber.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/suber.v ; ; +; alu/mulsu.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v ; ; +; clk/clk100M.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M.v ; clk100M ; +; clk/clk100M/clk100M_0002.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v ; clk100M ; +; altera_pll.v ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altera_pll.v ; ; +; altera_std_synchronizer.v ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altera_std_synchronizer.v ; ; +; altsyncram.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf ; ; +; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; +; lpm_mux.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc ; ; +; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc ; ; +; aglobal131.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc ; ; +; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ; +; altrom.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altrom.inc ; ; +; altram.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altram.inc ; ; +; altdpram.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc ; ; +; db/altsyncram_nco1.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_nco1.tdf ; ; +; db/altsyncram_bdq1.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_bdq1.tdf ; ; +; test.mif ; yes ; Auto-Found Memory Initialization File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/test.mif ; ; +; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ; +; addcore.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/addcore.inc ; ; +; look_add.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/look_add.inc ; ; +; bypassff.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/bypassff.inc ; ; +; altshift.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altshift.inc ; ; +; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ; +; db/add_sub_tih.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/add_sub_tih.tdf ; ; +; db/add_sub_ujh.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/add_sub_ujh.tdf ; ; +; lpm_mult.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mult.tdf ; ; +; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; +; multcore.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/multcore.inc ; ; +; db/mult_b8n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_b8n.v ; ; +; db/mult_81n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_81n.v ; ; +; db/mult_61n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_61n.v ; ; +; lpm_divide.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_divide.tdf ; ; +; abs_divider.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/abs_divider.inc ; ; +; sign_div_unsign.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/sign_div_unsign.inc ; ; +; db/lpm_divide_2jt.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/lpm_divide_2jt.tdf ; ; +; db/sign_div_unsign_8ai.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/sign_div_unsign_8ai.tdf ; ; +; db/alt_u_div_nlf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/alt_u_div_nlf.tdf ; ; +; db/lpm_divide_s4t.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/lpm_divide_s4t.tdf ; ; +; db/sign_div_unsign_2sh.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/sign_div_unsign_2sh.tdf ; ; +; db/alt_u_div_5eg.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/alt_u_div_5eg.tdf ; ; +; altshift_taps.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altshift_taps.tdf ; ; +; lpm_counter.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.inc ; ; +; lpm_compare.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_compare.inc ; ; +; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_constant.inc ; ; +; db/shift_taps_7l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_7l21.tdf ; ; +; db/altsyncram_kr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_kr91.tdf ; ; +; db/cntr_8jf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_8jf.tdf ; ; +; db/cmpr_c9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_c9c.tdf ; ; +; db/shift_taps_hm21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_hm21.tdf ; ; +; db/altsyncram_9u91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_9u91.tdf ; ; +; db/cntr_9jf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_9jf.tdf ; ; +; db/shift_taps_gm21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_gm21.tdf ; ; +; db/altsyncram_7u91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_7u91.tdf ; ; +; db/shift_taps_bl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_bl21.tdf ; ; +; db/altsyncram_rr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_rr91.tdf ; ; +; db/cntr_0if.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_0if.tdf ; ; +; db/shift_taps_9l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_9l21.tdf ; ; +; db/altsyncram_lr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_lr91.tdf ; ; +; db/cntr_uhf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_uhf.tdf ; ; +; db/shift_taps_cl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_cl21.tdf ; ; +; db/altsyncram_hr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_hr91.tdf ; ; +; db/cntr_thf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_thf.tdf ; ; +; db/cmpr_b9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_b9c.tdf ; ; +; db/shift_taps_dl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_dl21.tdf ; ; +; db/altsyncram_mr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_mr91.tdf ; ; +; db/cntr_shf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_shf.tdf ; ; +; db/shift_taps_4l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_4l21.tdf ; ; +; db/altsyncram_dr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_dr91.tdf ; ; +; db/cntr_rhf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_rhf.tdf ; ; +; db/shift_taps_3l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_3l21.tdf ; ; +; db/altsyncram_9r91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_9r91.tdf ; ; +; db/cntr_phf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_phf.tdf ; ; +; db/shift_taps_5l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_5l21.tdf ; ; +; db/altsyncram_br91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_br91.tdf ; ; +; db/cntr_ohf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_ohf.tdf ; ; +; db/cmpr_a9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_a9c.tdf ; ; ++----------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+---------+ +-------------------------------------------------------------------------------------------------------------------------------+ @@ -313,16 +321,16 @@ applicable agreement for further details. +---------------------------------------------+---------------------------------------------------------------------------------+ ; Resource ; Usage ; +---------------------------------------------+---------------------------------------------------------------------------------+ -; Estimate of Logic utilization (ALMs needed) ; 2157 ; +; Estimate of Logic utilization (ALMs needed) ; 2177 ; ; ; ; -; Combinational ALUT usage for logic ; 3706 ; +; Combinational ALUT usage for logic ; 3750 ; ; -- 7 input functions ; 47 ; -; -- 6 input functions ; 335 ; -; -- 5 input functions ; 468 ; -; -- 4 input functions ; 822 ; -; -- <=3 input functions ; 2034 ; +; -- 6 input functions ; 327 ; +; -- 5 input functions ; 472 ; +; -- 4 input functions ; 831 ; +; -- <=3 input functions ; 2073 ; ; ; ; -; Dedicated logic registers ; 1608 ; +; Dedicated logic registers ; 1636 ; ; ; ; ; I/O pins ; 204 ; ; Total MLAB memory bits ; 0 ; @@ -332,91 +340,95 @@ applicable agreement for further details. ; -- PLLs ; 1 ; ; ; ; ; Maximum fan-out node ; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; -; Maximum fan-out ; 1776 ; -; Total fan-out ; 20815 ; -; Average fan-out ; 3.49 ; +; Maximum fan-out ; 1804 ; +; Total fan-out ; 21004 ; +; Average fan-out ; 3.48 ; +---------------------------------------------+---------------------------------------------------------------------------------+ -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+----------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+----------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -; |de1_riscv ; 3706 (79) ; 1608 (66) ; 67296 ; 10 ; 204 ; 0 ; |de1_riscv ; work ; -; |clk100M:clk100| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100 ; clk100M ; -; |clk100M_0002:clk100m_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst ; clk100M ; -; |altera_pll:altera_pll_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; work ; -; |ram8kb:ram| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram ; work ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component ; work ; -; |altsyncram_bdq1:auto_generated| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated ; work ; -; |regfile:regs| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs ; work ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component ; work ; -; |altsyncram_nco1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; work ; -; |riscv_core:core| ; 3627 (1184) ; 1542 (287) ; 736 ; 10 ; 0 ; 0 ; |de1_riscv|riscv_core:core ; work ; -; |adder:add| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add ; work ; -; |lpm_add_sub:LPM_ADD_SUB_component| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component ; work ; -; |add_sub_tih:auto_generated| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component|add_sub_tih:auto_generated ; work ; -; |div:div| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div ; work ; -; |lpm_divide:LPM_DIVIDE_component| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component ; work ; -; |lpm_divide_2jt:auto_generated| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated ; work ; -; |sign_div_unsign_8ai:divider| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider ; work ; -; |alt_u_div_nlf:divider| ; 1002 (1002) ; 583 (583) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider ; work ; -; |div_s:divs| ; 1278 (0) ; 672 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs ; work ; -; |lpm_divide:LPM_DIVIDE_component| ; 1278 (0) ; 672 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component ; work ; -; |lpm_divide_s4t:auto_generated| ; 1278 (0) ; 672 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated ; work ; -; |sign_div_unsign_2sh:divider| ; 1278 (175) ; 672 (14) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider ; work ; -; |alt_u_div_5eg:divider| ; 1090 (987) ; 650 (594) ; 666 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider ; work ; -; |altshift_taps:DFFNumerator_rtl_0| ; 14 (0) ; 8 (0) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 ; work ; -; |shift_taps_hm21:auto_generated| ; 14 (8) ; 8 (4) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated ; work ; -; |altsyncram_9u91:altsyncram5| ; 0 (0) ; 0 (0) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 ; work ; -; |cntr_9jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_1| ; 13 (0) ; 8 (0) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 ; work ; -; |shift_taps_gm21:auto_generated| ; 13 (7) ; 8 (4) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated ; work ; -; |altsyncram_7u91:altsyncram5| ; 0 (0) ; 0 (0) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 ; work ; -; |cntr_8jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_2| ; 14 (0) ; 8 (0) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 ; work ; -; |shift_taps_bl21:auto_generated| ; 14 (8) ; 8 (4) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated ; work ; -; |altsyncram_rr91:altsyncram5| ; 0 (0) ; 0 (0) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 ; work ; -; |cntr_0if:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_3| ; 8 (0) ; 6 (0) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 ; work ; -; |shift_taps_9l21:auto_generated| ; 8 (5) ; 6 (3) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated ; work ; -; |altsyncram_lr91:altsyncram4| ; 0 (0) ; 0 (0) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 ; work ; -; |cntr_uhf:cntr1| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_4| ; 14 (0) ; 6 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 ; work ; -; |shift_taps_cl21:auto_generated| ; 14 (7) ; 6 (3) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated ; work ; -; |altsyncram_hr91:altsyncram5| ; 0 (0) ; 0 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 ; work ; -; |cntr_thf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_5| ; 13 (0) ; 6 (0) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 ; work ; -; |shift_taps_dl21:auto_generated| ; 13 (6) ; 6 (3) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated ; work ; -; |altsyncram_mr91:altsyncram5| ; 0 (0) ; 0 (0) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 ; work ; -; |cntr_shf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_6| ; 14 (0) ; 6 (0) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 ; work ; -; |shift_taps_4l21:auto_generated| ; 14 (7) ; 6 (3) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated ; work ; -; |altsyncram_dr91:altsyncram5| ; 0 (0) ; 0 (0) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 ; work ; -; |cntr_rhf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_7| ; 6 (0) ; 4 (0) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 ; work ; -; |shift_taps_3l21:auto_generated| ; 6 (4) ; 4 (2) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated ; work ; -; |altsyncram_9r91:altsyncram4| ; 0 (0) ; 0 (0) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 ; work ; -; |cntr_phf:cntr1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_8| ; 7 (0) ; 4 (0) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 ; work ; -; |shift_taps_5l21:auto_generated| ; 7 (2) ; 4 (2) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated ; work ; -; |altsyncram_br91:altsyncram4| ; 0 (0) ; 0 (0) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 ; work ; -; |cntr_ohf:cntr1| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1 ; work ; -; |altshift_taps:DFF_Num_Sign_rtl_0| ; 13 (0) ; 8 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 ; work ; -; |shift_taps_7l21:auto_generated| ; 13 (7) ; 8 (4) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated ; work ; -; |altsyncram_kr91:altsyncram5| ; 0 (0) ; 0 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 ; work ; -; |cntr_8jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1 ; work ; -; |mulsu:mul_su| ; 38 (0) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su ; work ; -; |lpm_mult:lpm_mult_component| ; 38 (0) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component ; work ; -; |mult_61n:auto_generated| ; 38 (38) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated ; work ; -; |mult:mul| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul ; work ; -; |lpm_mult:lpm_mult_component| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component ; work ; -; |mult_b8n:auto_generated| ; 46 (46) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component|mult_b8n:auto_generated ; work ; -; |mult_s:mul_s| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s ; work ; -; |lpm_mult:lpm_mult_component| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component ; work ; -; |mult_81n:auto_generated| ; 46 (46) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated ; work ; -+----------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |de1_riscv ; 3750 (83) ; 1636 (66) ; 67296 ; 10 ; 204 ; 0 ; |de1_riscv ; work ; +; |altera_uart:uart| ; 35 (0) ; 28 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart ; work ; +; |altera_uart_regs:the_altera_uart_regs| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_regs:the_altera_uart_regs ; work ; +; |altera_uart_rx:the_altera_uart_rx| ; 35 (35) ; 26 (24) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx ; work ; +; |altera_std_synchronizer:the_altera_std_synchronizer| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; work ; +; |clk100M:clk100| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100 ; clk100M ; +; |clk100M_0002:clk100m_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst ; clk100M ; +; |altera_pll:altera_pll_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; work ; +; |ram8kb:ram| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component ; work ; +; |altsyncram_bdq1:auto_generated| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated ; work ; +; |regfile:regs| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component ; work ; +; |altsyncram_nco1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; work ; +; |riscv_core:core| ; 3632 (1189) ; 1542 (287) ; 736 ; 10 ; 0 ; 0 ; |de1_riscv|riscv_core:core ; work ; +; |adder:add| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add ; work ; +; |lpm_add_sub:LPM_ADD_SUB_component| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component ; work ; +; |add_sub_tih:auto_generated| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component|add_sub_tih:auto_generated ; work ; +; |div:div| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div ; work ; +; |lpm_divide:LPM_DIVIDE_component| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component ; work ; +; |lpm_divide_2jt:auto_generated| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated ; work ; +; |sign_div_unsign_8ai:divider| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider ; work ; +; |alt_u_div_nlf:divider| ; 1002 (1002) ; 583 (583) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider ; work ; +; |div_s:divs| ; 1278 (0) ; 672 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs ; work ; +; |lpm_divide:LPM_DIVIDE_component| ; 1278 (0) ; 672 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component ; work ; +; |lpm_divide_s4t:auto_generated| ; 1278 (0) ; 672 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated ; work ; +; |sign_div_unsign_2sh:divider| ; 1278 (175) ; 672 (14) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider ; work ; +; |alt_u_div_5eg:divider| ; 1090 (987) ; 650 (594) ; 666 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider ; work ; +; |altshift_taps:DFFNumerator_rtl_0| ; 14 (0) ; 8 (0) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 ; work ; +; |shift_taps_hm21:auto_generated| ; 14 (8) ; 8 (4) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated ; work ; +; |altsyncram_9u91:altsyncram5| ; 0 (0) ; 0 (0) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 ; work ; +; |cntr_9jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_1| ; 13 (0) ; 8 (0) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 ; work ; +; |shift_taps_gm21:auto_generated| ; 13 (7) ; 8 (4) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated ; work ; +; |altsyncram_7u91:altsyncram5| ; 0 (0) ; 0 (0) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 ; work ; +; |cntr_8jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_2| ; 14 (0) ; 8 (0) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 ; work ; +; |shift_taps_bl21:auto_generated| ; 14 (8) ; 8 (4) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated ; work ; +; |altsyncram_rr91:altsyncram5| ; 0 (0) ; 0 (0) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 ; work ; +; |cntr_0if:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_3| ; 8 (0) ; 6 (0) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 ; work ; +; |shift_taps_9l21:auto_generated| ; 8 (5) ; 6 (3) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated ; work ; +; |altsyncram_lr91:altsyncram4| ; 0 (0) ; 0 (0) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 ; work ; +; |cntr_uhf:cntr1| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_4| ; 14 (0) ; 6 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 ; work ; +; |shift_taps_cl21:auto_generated| ; 14 (7) ; 6 (3) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated ; work ; +; |altsyncram_hr91:altsyncram5| ; 0 (0) ; 0 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 ; work ; +; |cntr_thf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_5| ; 13 (0) ; 6 (0) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 ; work ; +; |shift_taps_dl21:auto_generated| ; 13 (6) ; 6 (3) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated ; work ; +; |altsyncram_mr91:altsyncram5| ; 0 (0) ; 0 (0) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 ; work ; +; |cntr_shf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_6| ; 14 (0) ; 6 (0) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 ; work ; +; |shift_taps_4l21:auto_generated| ; 14 (7) ; 6 (3) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated ; work ; +; |altsyncram_dr91:altsyncram5| ; 0 (0) ; 0 (0) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 ; work ; +; |cntr_rhf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_7| ; 6 (0) ; 4 (0) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 ; work ; +; |shift_taps_3l21:auto_generated| ; 6 (4) ; 4 (2) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated ; work ; +; |altsyncram_9r91:altsyncram4| ; 0 (0) ; 0 (0) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 ; work ; +; |cntr_phf:cntr1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_8| ; 7 (0) ; 4 (0) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 ; work ; +; |shift_taps_5l21:auto_generated| ; 7 (2) ; 4 (2) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated ; work ; +; |altsyncram_br91:altsyncram4| ; 0 (0) ; 0 (0) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 ; work ; +; |cntr_ohf:cntr1| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1 ; work ; +; |altshift_taps:DFF_Num_Sign_rtl_0| ; 13 (0) ; 8 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 ; work ; +; |shift_taps_7l21:auto_generated| ; 13 (7) ; 8 (4) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated ; work ; +; |altsyncram_kr91:altsyncram5| ; 0 (0) ; 0 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 ; work ; +; |cntr_8jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1 ; work ; +; |mulsu:mul_su| ; 38 (0) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su ; work ; +; |lpm_mult:lpm_mult_component| ; 38 (0) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component ; work ; +; |mult_61n:auto_generated| ; 38 (38) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated ; work ; +; |mult:mul| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul ; work ; +; |lpm_mult:lpm_mult_component| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component ; work ; +; |mult_b8n:auto_generated| ; 46 (46) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component|mult_b8n:auto_generated ; work ; +; |mult_s:mul_s| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s ; work ; +; |lpm_mult:lpm_mult_component| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component ; work ; +; |mult_81n:auto_generated| ; 46 (46) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated ; work ; ++----------------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -496,11 +508,28 @@ Encoding Type: One-Hot +------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Protected by Synthesis ; ++----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; ++----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; yes ; yes ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; yes ; yes ; ++----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ + + +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Register name ; Reason for Removal ; +----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[10..15] ; Stuck at GND due to stuck port data_in ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[0..9] ; Stuck at GND due to stuck port clock_enable ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[9] ; Stuck at GND due to stuck port data_in ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|irq ; Stuck at GND due to stuck port data_in ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[0..7] ; Stuck at GND due to stuck port clock_enable ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_ready ; Stuck at VCC due to stuck port data_in ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|do_load_shifter ; Stuck at GND due to stuck port data_in ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[31] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[11] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[63] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[10] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[95] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[9] ; @@ -513,6 +542,7 @@ Encoding Type: One-Hot ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[319] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[2] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[351] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[1] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[383] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx2 ; Merged with altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[0] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[0] ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[32] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[32] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[64] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[64] ; @@ -525,26 +555,104 @@ Encoding Type: One-Hot ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[288] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[320] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[320] ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[352] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[352] ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_overrun ; Stuck at GND due to stuck port data_in ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0..9] ; Stuck at GND due to stuck port data_in ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|pre_txd ; Stuck at VCC due to stuck port clock_enable ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|txd ; Stuck at VCC due to stuck port data_in ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_clk_en ; Lost fanout ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_shift_empty ; Stuck at VCC due to stuck port data_in ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[0..8] ; Lost fanout ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[2..6] ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[2] ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|break_detect ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[3] ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_overrun ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[4..6] ; Lost fanout ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[0,1,7,8] ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[1,7] ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|framing_error ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[0] ; Lost fanout ; ; riscv_core:core|state~10 ; Lost fanout ; ; riscv_core:core|state~11 ; Lost fanout ; ; riscv_core:core|state~12 ; Lost fanout ; ; riscv_core:core|state~13 ; Lost fanout ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[1] ; Stuck at GND due to stuck port data_in ; -; Total Number of Removed Registers = 29 ; ; +; Total Number of Removed Registers = 102 ; ; +----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++-----------------------------------------------------------------------+--------------------------------+--------------------------------------------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++-----------------------------------------------------------------------+--------------------------------+--------------------------------------------------------------------------------------------------------------------+ +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[7] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8], ; +; ; due to stuck port clock_enable ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|pre_txd, ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_clk_en, ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[8], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[7], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[6], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[5], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[4], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[3], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[2], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[1], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[0] ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[8] ; Stuck at GND ; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|irq, ; +; ; due to stuck port clock_enable ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|break_detect, ; +; ; ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_overrun, ; +; ; ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|framing_error ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[9] ; Stuck at GND ; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[9], ; +; ; due to stuck port clock_enable ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|txd ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[7] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[7] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[6] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[6] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[5] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[5] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[4] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[4] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[3] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[3] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[2] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[2] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[1] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[1] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[0] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[0] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[6] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[5] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[4] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[3] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[2] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[1] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[0] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_ready ; Stuck at VCC ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_shift_empty ; +; ; due to stuck port data_in ; ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|do_load_shifter ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; +; ; due to stuck port data_in ; ; ++-----------------------------------------------------------------------+--------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 1608 ; +; Total registers ; 1636 ; ; Number of registers using Synchronous Clear ; 95 ; ; Number of registers using Synchronous Load ; 493 ; -; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Clear ; 28 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 306 ; +; Number of registers using Clock Enable ; 316 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -554,7 +662,7 @@ Encoding Type: One-Hot +-------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; Inverted Register ; Fan out ; +-------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; 34 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; 35 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[352] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[1] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[353] ; 1 ; @@ -708,47 +816,72 @@ Encoding Type: One-Hot +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Multiplexer Restructuring Statistics (Restructuring Performed) ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+ -; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+ -; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de1_riscv|riscv_core:core|ldaddr[0] ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[8] ; -; 5:1 ; 19 bits ; 57 LEs ; 0 LEs ; 57 LEs ; Yes ; |de1_riscv|readaddr[20] ; -; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |de1_riscv|led3[6] ; -; 6:1 ; 24 bits ; 96 LEs ; 48 LEs ; 48 LEs ; Yes ; |de1_riscv|led1[5] ; -; 5:1 ; 8 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[5] ; -; 14:1 ; 6 bits ; 54 LEs ; 6 LEs ; 48 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[10] ; -; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |de1_riscv|led4[6] ; -; 7:1 ; 12 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |de1_riscv|led4[0] ; -; 7:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |de1_riscv|riscv_core:core|divclk[3] ; -; 15:1 ; 8 bits ; 80 LEs ; 0 LEs ; 80 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[18] ; -; 16:1 ; 4 bits ; 40 LEs ; 8 LEs ; 32 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[1] ; -; 10:1 ; 11 bits ; 66 LEs ; 0 LEs ; 66 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[29] ; -; 14:1 ; 2 bits ; 18 LEs ; 4 LEs ; 14 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[0] ; -; 14:1 ; 25 bits ; 225 LEs ; 50 LEs ; 175 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[22] ; -; 14:1 ; 4 bits ; 36 LEs ; 8 LEs ; 28 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[2] ; -; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[22] ; -; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[31] ; -; 22:1 ; 5 bits ; 70 LEs ; 25 LEs ; 45 LEs ; Yes ; |de1_riscv|riscv_core:core|dstreg[4] ; -; 60:1 ; 12 bits ; 480 LEs ; 276 LEs ; 204 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[24] ; -; 63:1 ; 7 bits ; 294 LEs ; 238 LEs ; 56 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[8] ; -; 64:1 ; 3 bits ; 126 LEs ; 102 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[28] ; -; 65:1 ; 3 bits ; 129 LEs ; 102 LEs ; 27 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[5] ; -; 69:1 ; 2 bits ; 92 LEs ; 72 LEs ; 20 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[2] ; -; 3:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[9] ; -; 3:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[19] ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ; -; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft0 ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft0 ; -; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight0 ; -; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|bReadAddr[11] ; -; 5:1 ; 6 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |de1_riscv|ramaddr[3] ; -; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|Selector163 ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------+ +; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; +; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de1_riscv|riscv_core:core|ldaddr[1] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[14] ; +; 5:1 ; 19 bits ; 57 LEs ; 0 LEs ; 57 LEs ; Yes ; |de1_riscv|readaddr[17] ; +; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |de1_riscv|led1[6] ; +; 6:1 ; 24 bits ; 96 LEs ; 48 LEs ; 48 LEs ; Yes ; |de1_riscv|led2[3] ; +; 5:1 ; 8 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[1] ; +; 14:1 ; 6 bits ; 54 LEs ; 6 LEs ; 48 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[5] ; +; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |de1_riscv|led4[6] ; +; 7:1 ; 12 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |de1_riscv|led4[4] ; +; 7:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |de1_riscv|riscv_core:core|divclk[1] ; +; 15:1 ; 8 bits ; 80 LEs ; 0 LEs ; 80 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[12] ; +; 16:1 ; 4 bits ; 40 LEs ; 8 LEs ; 32 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[3] ; +; 10:1 ; 11 bits ; 66 LEs ; 0 LEs ; 66 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[27] ; +; 14:1 ; 2 bits ; 18 LEs ; 4 LEs ; 14 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[0] ; +; 14:1 ; 25 bits ; 225 LEs ; 50 LEs ; 175 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[18] ; +; 14:1 ; 4 bits ; 36 LEs ; 8 LEs ; 28 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[2] ; +; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[19] ; +; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[27] ; +; 22:1 ; 5 bits ; 70 LEs ; 25 LEs ; 45 LEs ; Yes ; |de1_riscv|riscv_core:core|dstreg[0] ; +; 60:1 ; 12 bits ; 480 LEs ; 276 LEs ; 204 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[25] ; +; 63:1 ; 7 bits ; 294 LEs ; 238 LEs ; 56 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[8] ; +; 64:1 ; 3 bits ; 126 LEs ; 102 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[30] ; +; 65:1 ; 3 bits ; 129 LEs ; 102 LEs ; 27 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[6] ; +; 69:1 ; 2 bits ; 92 LEs ; 72 LEs ; 20 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[3] ; +; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[9] ; +; 3:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[23] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft1 ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft0 ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight0 ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft0 ; +; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|bReadAddr[8] ; +; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[2] ; +; 5:1 ; 6 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |de1_riscv|uartaddr[0] ; +; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|Selector162 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------+ +; Source assignments for altera_uart:uart ; ++-----------------------------+-------+------+----+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+----+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+----+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; ++-----------------------------+------------------------+------+-----------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+-----------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; +; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; +; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; +; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; +; PRESERVE_REGISTER ; ON ; - ; din_s1 ; ++-----------------------------+------------------------+------+-----------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------+ @@ -2030,226 +2163,236 @@ Encoding Type: One-Hot +---------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; -+--------------------------------------+----------------+-------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------------+----------------+-------------------------------------------------------+ -; reference_clock_frequency ; 50.0 MHz ; String ; -; fractional_vco_multiplier ; false ; String ; -; pll_type ; General ; String ; -; pll_subtype ; General ; String ; -; number_of_clocks ; 2 ; Signed Integer ; -; operation_mode ; direct ; String ; -; deserialization_factor ; 4 ; Signed Integer ; -; data_rate ; 0 ; Signed Integer ; -; sim_additional_refclk_cycles_to_lock ; 0 ; Signed Integer ; -; output_clock_frequency0 ; 100.000000 MHz ; String ; -; phase_shift0 ; 0 ps ; String ; -; duty_cycle0 ; 50 ; Signed Integer ; -; output_clock_frequency1 ; 75.000000 MHz ; String ; -; phase_shift1 ; 0 ps ; String ; -; duty_cycle1 ; 50 ; Signed Integer ; -; output_clock_frequency2 ; 0 MHz ; String ; -; phase_shift2 ; 0 ps ; String ; -; duty_cycle2 ; 50 ; Signed Integer ; -; output_clock_frequency3 ; 0 MHz ; String ; -; phase_shift3 ; 0 ps ; String ; -; duty_cycle3 ; 50 ; Signed Integer ; -; output_clock_frequency4 ; 0 MHz ; String ; -; phase_shift4 ; 0 ps ; String ; -; duty_cycle4 ; 50 ; Signed Integer ; -; output_clock_frequency5 ; 0 MHz ; String ; -; phase_shift5 ; 0 ps ; String ; -; duty_cycle5 ; 50 ; Signed Integer ; -; output_clock_frequency6 ; 0 MHz ; String ; -; phase_shift6 ; 0 ps ; String ; -; duty_cycle6 ; 50 ; Signed Integer ; -; output_clock_frequency7 ; 0 MHz ; String ; -; phase_shift7 ; 0 ps ; String ; -; duty_cycle7 ; 50 ; Signed Integer ; -; output_clock_frequency8 ; 0 MHz ; String ; -; phase_shift8 ; 0 ps ; String ; -; duty_cycle8 ; 50 ; Signed Integer ; -; output_clock_frequency9 ; 0 MHz ; String ; -; phase_shift9 ; 0 ps ; String ; -; duty_cycle9 ; 50 ; Signed Integer ; -; output_clock_frequency10 ; 0 MHz ; String ; -; phase_shift10 ; 0 ps ; String ; -; duty_cycle10 ; 50 ; Signed Integer ; -; output_clock_frequency11 ; 0 MHz ; String ; -; phase_shift11 ; 0 ps ; String ; -; duty_cycle11 ; 50 ; Signed Integer ; -; output_clock_frequency12 ; 0 MHz ; String ; -; phase_shift12 ; 0 ps ; String ; -; duty_cycle12 ; 50 ; Signed Integer ; -; output_clock_frequency13 ; 0 MHz ; String ; -; phase_shift13 ; 0 ps ; String ; -; duty_cycle13 ; 50 ; Signed Integer ; -; output_clock_frequency14 ; 0 MHz ; String ; -; phase_shift14 ; 0 ps ; String ; -; duty_cycle14 ; 50 ; Signed Integer ; -; output_clock_frequency15 ; 0 MHz ; String ; -; phase_shift15 ; 0 ps ; String ; -; duty_cycle15 ; 50 ; Signed Integer ; -; output_clock_frequency16 ; 0 MHz ; String ; -; phase_shift16 ; 0 ps ; String ; -; duty_cycle16 ; 50 ; Signed Integer ; -; output_clock_frequency17 ; 0 MHz ; String ; -; phase_shift17 ; 0 ps ; String ; -; duty_cycle17 ; 50 ; Signed Integer ; -; m_cnt_hi_div ; 1 ; Signed Integer ; -; m_cnt_lo_div ; 1 ; Signed Integer ; -; m_cnt_bypass_en ; false ; String ; -; m_cnt_odd_div_duty_en ; false ; String ; -; n_cnt_hi_div ; 1 ; Signed Integer ; -; n_cnt_lo_div ; 1 ; Signed Integer ; -; n_cnt_bypass_en ; false ; String ; -; n_cnt_odd_div_duty_en ; false ; String ; -; c_cnt_hi_div0 ; 1 ; Signed Integer ; -; c_cnt_lo_div0 ; 1 ; Signed Integer ; -; c_cnt_bypass_en0 ; false ; String ; -; c_cnt_in_src0 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en0 ; false ; String ; -; c_cnt_prst0 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst0 ; 0 ; Signed Integer ; -; c_cnt_hi_div1 ; 1 ; Signed Integer ; -; c_cnt_lo_div1 ; 1 ; Signed Integer ; -; c_cnt_bypass_en1 ; false ; String ; -; c_cnt_in_src1 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en1 ; false ; String ; -; c_cnt_prst1 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst1 ; 0 ; Signed Integer ; -; c_cnt_hi_div2 ; 1 ; Signed Integer ; -; c_cnt_lo_div2 ; 1 ; Signed Integer ; -; c_cnt_bypass_en2 ; false ; String ; -; c_cnt_in_src2 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en2 ; false ; String ; -; c_cnt_prst2 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst2 ; 0 ; Signed Integer ; -; c_cnt_hi_div3 ; 1 ; Signed Integer ; -; c_cnt_lo_div3 ; 1 ; Signed Integer ; -; c_cnt_bypass_en3 ; false ; String ; -; c_cnt_in_src3 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en3 ; false ; String ; -; c_cnt_prst3 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst3 ; 0 ; Signed Integer ; -; c_cnt_hi_div4 ; 1 ; Signed Integer ; -; c_cnt_lo_div4 ; 1 ; Signed Integer ; -; c_cnt_bypass_en4 ; false ; String ; -; c_cnt_in_src4 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en4 ; false ; String ; -; c_cnt_prst4 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst4 ; 0 ; Signed Integer ; -; c_cnt_hi_div5 ; 1 ; Signed Integer ; -; c_cnt_lo_div5 ; 1 ; Signed Integer ; -; c_cnt_bypass_en5 ; false ; String ; -; c_cnt_in_src5 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en5 ; false ; String ; -; c_cnt_prst5 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst5 ; 0 ; Signed Integer ; -; c_cnt_hi_div6 ; 1 ; Signed Integer ; -; c_cnt_lo_div6 ; 1 ; Signed Integer ; -; c_cnt_bypass_en6 ; false ; String ; -; c_cnt_in_src6 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en6 ; false ; String ; -; c_cnt_prst6 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst6 ; 0 ; Signed Integer ; -; c_cnt_hi_div7 ; 1 ; Signed Integer ; -; c_cnt_lo_div7 ; 1 ; Signed Integer ; -; c_cnt_bypass_en7 ; false ; String ; -; c_cnt_in_src7 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en7 ; false ; String ; -; c_cnt_prst7 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst7 ; 0 ; Signed Integer ; -; c_cnt_hi_div8 ; 1 ; Signed Integer ; -; c_cnt_lo_div8 ; 1 ; Signed Integer ; -; c_cnt_bypass_en8 ; false ; String ; -; c_cnt_in_src8 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en8 ; false ; String ; -; c_cnt_prst8 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst8 ; 0 ; Signed Integer ; -; c_cnt_hi_div9 ; 1 ; Signed Integer ; -; c_cnt_lo_div9 ; 1 ; Signed Integer ; -; c_cnt_bypass_en9 ; false ; String ; -; c_cnt_in_src9 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en9 ; false ; String ; -; c_cnt_prst9 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst9 ; 0 ; Signed Integer ; -; c_cnt_hi_div10 ; 1 ; Signed Integer ; -; c_cnt_lo_div10 ; 1 ; Signed Integer ; -; c_cnt_bypass_en10 ; false ; String ; -; c_cnt_in_src10 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en10 ; false ; String ; -; c_cnt_prst10 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst10 ; 0 ; Signed Integer ; -; c_cnt_hi_div11 ; 1 ; Signed Integer ; -; c_cnt_lo_div11 ; 1 ; Signed Integer ; -; c_cnt_bypass_en11 ; false ; String ; -; c_cnt_in_src11 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en11 ; false ; String ; -; c_cnt_prst11 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst11 ; 0 ; Signed Integer ; -; c_cnt_hi_div12 ; 1 ; Signed Integer ; -; c_cnt_lo_div12 ; 1 ; Signed Integer ; -; c_cnt_bypass_en12 ; false ; String ; -; c_cnt_in_src12 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en12 ; false ; String ; -; c_cnt_prst12 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst12 ; 0 ; Signed Integer ; -; c_cnt_hi_div13 ; 1 ; Signed Integer ; -; c_cnt_lo_div13 ; 1 ; Signed Integer ; -; c_cnt_bypass_en13 ; false ; String ; -; c_cnt_in_src13 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en13 ; false ; String ; -; c_cnt_prst13 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst13 ; 0 ; Signed Integer ; -; c_cnt_hi_div14 ; 1 ; Signed Integer ; -; c_cnt_lo_div14 ; 1 ; Signed Integer ; -; c_cnt_bypass_en14 ; false ; String ; -; c_cnt_in_src14 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en14 ; false ; String ; -; c_cnt_prst14 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst14 ; 0 ; Signed Integer ; -; c_cnt_hi_div15 ; 1 ; Signed Integer ; -; c_cnt_lo_div15 ; 1 ; Signed Integer ; -; c_cnt_bypass_en15 ; false ; String ; -; c_cnt_in_src15 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en15 ; false ; String ; -; c_cnt_prst15 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst15 ; 0 ; Signed Integer ; -; c_cnt_hi_div16 ; 1 ; Signed Integer ; -; c_cnt_lo_div16 ; 1 ; Signed Integer ; -; c_cnt_bypass_en16 ; false ; String ; -; c_cnt_in_src16 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en16 ; false ; String ; -; c_cnt_prst16 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst16 ; 0 ; Signed Integer ; -; c_cnt_hi_div17 ; 1 ; Signed Integer ; -; c_cnt_lo_div17 ; 1 ; Signed Integer ; -; c_cnt_bypass_en17 ; false ; String ; -; c_cnt_in_src17 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en17 ; false ; String ; -; c_cnt_prst17 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst17 ; 0 ; Signed Integer ; -; pll_vco_div ; 1 ; Signed Integer ; -; pll_output_clk_frequency ; 0 MHz ; String ; -; pll_cp_current ; 0 ; Signed Integer ; -; pll_bwctrl ; 0 ; Signed Integer ; -; pll_fractional_division ; 1 ; Signed Integer ; -; pll_fractional_cout ; 24 ; Signed Integer ; -; pll_dsm_out_sel ; 1st_order ; String ; -; mimic_fbclk_type ; gclk ; String ; -; pll_fbclk_mux_1 ; glb ; String ; -; pll_fbclk_mux_2 ; fb_1 ; String ; -; pll_m_cnt_in_src ; ph_mux_clk ; String ; -; pll_vcoph_div ; 1 ; Signed Integer ; -; refclk1_frequency ; 0 MHz ; String ; -; pll_clkin_0_src ; clk_0 ; String ; -; pll_clkin_1_src ; clk_0 ; String ; -; pll_clk_loss_sw_en ; false ; String ; -; pll_auto_clk_sw_en ; false ; String ; -; pll_manu_clk_sw_en ; false ; String ; -; pll_clk_sw_dly ; 0 ; Signed Integer ; -+--------------------------------------+----------------+-------------------------------------------------------+ ++--------------------------------------+---------------+--------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------------+---------------+--------------------------------------------------------+ +; reference_clock_frequency ; 50.0 MHz ; String ; +; fractional_vco_multiplier ; false ; String ; +; pll_type ; General ; String ; +; pll_subtype ; General ; String ; +; number_of_clocks ; 2 ; Signed Integer ; +; operation_mode ; direct ; String ; +; deserialization_factor ; 4 ; Signed Integer ; +; data_rate ; 0 ; Signed Integer ; +; sim_additional_refclk_cycles_to_lock ; 0 ; Signed Integer ; +; output_clock_frequency0 ; 50.000000 MHz ; String ; +; phase_shift0 ; 0 ps ; String ; +; duty_cycle0 ; 50 ; Signed Integer ; +; output_clock_frequency1 ; 75.000000 MHz ; String ; +; phase_shift1 ; 0 ps ; String ; +; duty_cycle1 ; 50 ; Signed Integer ; +; output_clock_frequency2 ; 0 MHz ; String ; +; phase_shift2 ; 0 ps ; String ; +; duty_cycle2 ; 50 ; Signed Integer ; +; output_clock_frequency3 ; 0 MHz ; String ; +; phase_shift3 ; 0 ps ; String ; +; duty_cycle3 ; 50 ; Signed Integer ; +; output_clock_frequency4 ; 0 MHz ; String ; +; phase_shift4 ; 0 ps ; String ; +; duty_cycle4 ; 50 ; Signed Integer ; +; output_clock_frequency5 ; 0 MHz ; String ; +; phase_shift5 ; 0 ps ; String ; +; duty_cycle5 ; 50 ; Signed Integer ; +; output_clock_frequency6 ; 0 MHz ; String ; +; phase_shift6 ; 0 ps ; String ; +; duty_cycle6 ; 50 ; Signed Integer ; +; output_clock_frequency7 ; 0 MHz ; String ; +; phase_shift7 ; 0 ps ; String ; +; duty_cycle7 ; 50 ; Signed Integer ; +; output_clock_frequency8 ; 0 MHz ; String ; +; phase_shift8 ; 0 ps ; String ; +; duty_cycle8 ; 50 ; Signed Integer ; +; output_clock_frequency9 ; 0 MHz ; String ; +; phase_shift9 ; 0 ps ; String ; +; duty_cycle9 ; 50 ; Signed Integer ; +; output_clock_frequency10 ; 0 MHz ; String ; +; phase_shift10 ; 0 ps ; String ; +; duty_cycle10 ; 50 ; Signed Integer ; +; output_clock_frequency11 ; 0 MHz ; String ; +; phase_shift11 ; 0 ps ; String ; +; duty_cycle11 ; 50 ; Signed Integer ; +; output_clock_frequency12 ; 0 MHz ; String ; +; phase_shift12 ; 0 ps ; String ; +; duty_cycle12 ; 50 ; Signed Integer ; +; output_clock_frequency13 ; 0 MHz ; String ; +; phase_shift13 ; 0 ps ; String ; +; duty_cycle13 ; 50 ; Signed Integer ; +; output_clock_frequency14 ; 0 MHz ; String ; +; phase_shift14 ; 0 ps ; String ; +; duty_cycle14 ; 50 ; Signed Integer ; +; output_clock_frequency15 ; 0 MHz ; String ; +; phase_shift15 ; 0 ps ; String ; +; duty_cycle15 ; 50 ; Signed Integer ; +; output_clock_frequency16 ; 0 MHz ; String ; +; phase_shift16 ; 0 ps ; String ; +; duty_cycle16 ; 50 ; Signed Integer ; +; output_clock_frequency17 ; 0 MHz ; String ; +; phase_shift17 ; 0 ps ; String ; +; duty_cycle17 ; 50 ; Signed Integer ; +; m_cnt_hi_div ; 1 ; Signed Integer ; +; m_cnt_lo_div ; 1 ; Signed Integer ; +; m_cnt_bypass_en ; false ; String ; +; m_cnt_odd_div_duty_en ; false ; String ; +; n_cnt_hi_div ; 1 ; Signed Integer ; +; n_cnt_lo_div ; 1 ; Signed Integer ; +; n_cnt_bypass_en ; false ; String ; +; n_cnt_odd_div_duty_en ; false ; String ; +; c_cnt_hi_div0 ; 1 ; Signed Integer ; +; c_cnt_lo_div0 ; 1 ; Signed Integer ; +; c_cnt_bypass_en0 ; false ; String ; +; c_cnt_in_src0 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en0 ; false ; String ; +; c_cnt_prst0 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst0 ; 0 ; Signed Integer ; +; c_cnt_hi_div1 ; 1 ; Signed Integer ; +; c_cnt_lo_div1 ; 1 ; Signed Integer ; +; c_cnt_bypass_en1 ; false ; String ; +; c_cnt_in_src1 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en1 ; false ; String ; +; c_cnt_prst1 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst1 ; 0 ; Signed Integer ; +; c_cnt_hi_div2 ; 1 ; Signed Integer ; +; c_cnt_lo_div2 ; 1 ; Signed Integer ; +; c_cnt_bypass_en2 ; false ; String ; +; c_cnt_in_src2 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en2 ; false ; String ; +; c_cnt_prst2 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst2 ; 0 ; Signed Integer ; +; c_cnt_hi_div3 ; 1 ; Signed Integer ; +; c_cnt_lo_div3 ; 1 ; Signed Integer ; +; c_cnt_bypass_en3 ; false ; String ; +; c_cnt_in_src3 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en3 ; false ; String ; +; c_cnt_prst3 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst3 ; 0 ; Signed Integer ; +; c_cnt_hi_div4 ; 1 ; Signed Integer ; +; c_cnt_lo_div4 ; 1 ; Signed Integer ; +; c_cnt_bypass_en4 ; false ; String ; +; c_cnt_in_src4 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en4 ; false ; String ; +; c_cnt_prst4 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst4 ; 0 ; Signed Integer ; +; c_cnt_hi_div5 ; 1 ; Signed Integer ; +; c_cnt_lo_div5 ; 1 ; Signed Integer ; +; c_cnt_bypass_en5 ; false ; String ; +; c_cnt_in_src5 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en5 ; false ; String ; +; c_cnt_prst5 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst5 ; 0 ; Signed Integer ; +; c_cnt_hi_div6 ; 1 ; Signed Integer ; +; c_cnt_lo_div6 ; 1 ; Signed Integer ; +; c_cnt_bypass_en6 ; false ; String ; +; c_cnt_in_src6 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en6 ; false ; String ; +; c_cnt_prst6 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst6 ; 0 ; Signed Integer ; +; c_cnt_hi_div7 ; 1 ; Signed Integer ; +; c_cnt_lo_div7 ; 1 ; Signed Integer ; +; c_cnt_bypass_en7 ; false ; String ; +; c_cnt_in_src7 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en7 ; false ; String ; +; c_cnt_prst7 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst7 ; 0 ; Signed Integer ; +; c_cnt_hi_div8 ; 1 ; Signed Integer ; +; c_cnt_lo_div8 ; 1 ; Signed Integer ; +; c_cnt_bypass_en8 ; false ; String ; +; c_cnt_in_src8 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en8 ; false ; String ; +; c_cnt_prst8 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst8 ; 0 ; Signed Integer ; +; c_cnt_hi_div9 ; 1 ; Signed Integer ; +; c_cnt_lo_div9 ; 1 ; Signed Integer ; +; c_cnt_bypass_en9 ; false ; String ; +; c_cnt_in_src9 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en9 ; false ; String ; +; c_cnt_prst9 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst9 ; 0 ; Signed Integer ; +; c_cnt_hi_div10 ; 1 ; Signed Integer ; +; c_cnt_lo_div10 ; 1 ; Signed Integer ; +; c_cnt_bypass_en10 ; false ; String ; +; c_cnt_in_src10 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en10 ; false ; String ; +; c_cnt_prst10 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst10 ; 0 ; Signed Integer ; +; c_cnt_hi_div11 ; 1 ; Signed Integer ; +; c_cnt_lo_div11 ; 1 ; Signed Integer ; +; c_cnt_bypass_en11 ; false ; String ; +; c_cnt_in_src11 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en11 ; false ; String ; +; c_cnt_prst11 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst11 ; 0 ; Signed Integer ; +; c_cnt_hi_div12 ; 1 ; Signed Integer ; +; c_cnt_lo_div12 ; 1 ; Signed Integer ; +; c_cnt_bypass_en12 ; false ; String ; +; c_cnt_in_src12 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en12 ; false ; String ; +; c_cnt_prst12 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst12 ; 0 ; Signed Integer ; +; c_cnt_hi_div13 ; 1 ; Signed Integer ; +; c_cnt_lo_div13 ; 1 ; Signed Integer ; +; c_cnt_bypass_en13 ; false ; String ; +; c_cnt_in_src13 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en13 ; false ; String ; +; c_cnt_prst13 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst13 ; 0 ; Signed Integer ; +; c_cnt_hi_div14 ; 1 ; Signed Integer ; +; c_cnt_lo_div14 ; 1 ; Signed Integer ; +; c_cnt_bypass_en14 ; false ; String ; +; c_cnt_in_src14 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en14 ; false ; String ; +; c_cnt_prst14 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst14 ; 0 ; Signed Integer ; +; c_cnt_hi_div15 ; 1 ; Signed Integer ; +; c_cnt_lo_div15 ; 1 ; Signed Integer ; +; c_cnt_bypass_en15 ; false ; String ; +; c_cnt_in_src15 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en15 ; false ; String ; +; c_cnt_prst15 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst15 ; 0 ; Signed Integer ; +; c_cnt_hi_div16 ; 1 ; Signed Integer ; +; c_cnt_lo_div16 ; 1 ; Signed Integer ; +; c_cnt_bypass_en16 ; false ; String ; +; c_cnt_in_src16 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en16 ; false ; String ; +; c_cnt_prst16 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst16 ; 0 ; Signed Integer ; +; c_cnt_hi_div17 ; 1 ; Signed Integer ; +; c_cnt_lo_div17 ; 1 ; Signed Integer ; +; c_cnt_bypass_en17 ; false ; String ; +; c_cnt_in_src17 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en17 ; false ; String ; +; c_cnt_prst17 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst17 ; 0 ; Signed Integer ; +; pll_vco_div ; 1 ; Signed Integer ; +; pll_output_clk_frequency ; 0 MHz ; String ; +; pll_cp_current ; 0 ; Signed Integer ; +; pll_bwctrl ; 0 ; Signed Integer ; +; pll_fractional_division ; 1 ; Signed Integer ; +; pll_fractional_cout ; 24 ; Signed Integer ; +; pll_dsm_out_sel ; 1st_order ; String ; +; mimic_fbclk_type ; gclk ; String ; +; pll_fbclk_mux_1 ; glb ; String ; +; pll_fbclk_mux_2 ; fb_1 ; String ; +; pll_m_cnt_in_src ; ph_mux_clk ; String ; +; pll_vcoph_div ; 1 ; Signed Integer ; +; refclk1_frequency ; 0 MHz ; String ; +; pll_clkin_0_src ; clk_0 ; String ; +; pll_clkin_1_src ; clk_0 ; String ; +; pll_clk_loss_sw_en ; false ; String ; +; pll_auto_clk_sw_en ; false ; String ; +; pll_manu_clk_sw_en ; false ; String ; +; pll_clk_sw_dly ; 0 ; Signed Integer ; ++--------------------------------------+---------------+--------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------+ +; depth ; 2 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". @@ -2879,11 +3022,21 @@ Note: In order to hide this table in the UI and the text report file, please set +-----------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +-----------------+--------+----------+-------------------------------------------------------------------------------------+ -; wRead ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; bReadAddr[1..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +-----------------+--------+----------+-------------------------------------------------------------------------------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "altera_uart:uart" ; ++------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; chipselect ; Input ; Info ; Stuck at GND ; +; writedata ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (16 bits) it drives. The 16 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; readdata ; Output ; Warning ; Output or bidir port (16 bits) is smaller than the port expression (32 bits) it drives. The 16 most-significant bit(s) in the port expression will be connected to GND. ; ++------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + +--------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "clk100M:clk100" ; +----------+--------+----------+-------------------------------------------------------------------------------------+ @@ -2899,7 +3052,7 @@ Note: In order to hide this table in the UI and the text report file, please set +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ -; Top ; 00:00:16 ; +; Top ; 00:00:18 ; +----------------+--------------+ @@ -2909,13 +3062,15 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version - Info: Processing started: Fri Aug 27 17:20:51 2021 + Info: Processing started: Sat Aug 28 11:02:08 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off de1_riscv -c de1_riscv Warning (125092): Tcl Script File alu/add_sub.qip not found Info (125063): set_global_assignment -name QIP_FILE alu/add_sub.qip Warning (125092): Tcl Script File alu/add_sub_s.qip not found Info (125063): set_global_assignment -name QIP_FILE alu/add_sub_s.qip Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead. +Info (12021): Found 1 design units, including 1 entities, in source file de1_riscv_v2.v + Info (12023): Found entity 1: de1_riscv Warning (10335): Unrecognized synthesis attribute "HDL4SE" at ../verilog/riscv_core.v(49) Warning (10335): Unrecognized synthesis attribute "CLSID" at ../verilog/riscv_core.v(50) Warning (10335): Unrecognized synthesis attribute "softmodule" at ../verilog/riscv_core.v(51) @@ -2953,55 +3108,53 @@ Info (12021): Found 1 design units, including 1 entities, in source file clk/clk Info (12023): Found entity 1: clk100M Info (12021): Found 1 design units, including 1 entities, in source file clk/clk100m/clk100m_0002.v Info (12023): Found entity 1: clk100M_0002 -Warning (12125): Using design file de1_riscv.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project - Info (12023): Found entity 1: de1_riscv Info (12127): Elaborating entity "de1_riscv" for the top level hierarchy -Warning (10036): Verilog HDL or VHDL warning at de1_riscv.v(118): object "wRead_out" assigned a value but never read -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(169): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(170): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(171): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(172): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(173): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(174): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(177): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(178): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(179): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(180): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(181): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(182): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(185): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(186): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(187): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(188): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(189): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(190): truncated value with size 8 to match size of target (7) -Warning (10034): Output port "DRAM_ADDR" at de1_riscv.v(31) has no driver -Warning (10034): Output port "DRAM_BA" at de1_riscv.v(32) has no driver -Warning (10034): Output port "LEDR" at de1_riscv.v(63) has no driver -Warning (10034): Output port "VGA_B" at de1_riscv.v(83) has no driver -Warning (10034): Output port "VGA_G" at de1_riscv.v(85) has no driver -Warning (10034): Output port "VGA_R" at de1_riscv.v(87) has no driver -Warning (10034): Output port "ADC_CONVST" at de1_riscv.v(11) has no driver -Warning (10034): Output port "ADC_DIN" at de1_riscv.v(12) has no driver -Warning (10034): Output port "ADC_SCLK" at de1_riscv.v(14) has no driver -Warning (10034): Output port "AUD_DACDAT" at de1_riscv.v(20) has no driver -Warning (10034): Output port "AUD_XCK" at de1_riscv.v(22) has no driver -Warning (10034): Output port "DRAM_CAS_N" at de1_riscv.v(33) has no driver -Warning (10034): Output port "DRAM_CKE" at de1_riscv.v(34) has no driver -Warning (10034): Output port "DRAM_CLK" at de1_riscv.v(35) has no driver -Warning (10034): Output port "DRAM_CS_N" at de1_riscv.v(36) has no driver -Warning (10034): Output port "DRAM_LDQM" at de1_riscv.v(38) has no driver -Warning (10034): Output port "DRAM_RAS_N" at de1_riscv.v(39) has no driver -Warning (10034): Output port "DRAM_UDQM" at de1_riscv.v(40) has no driver -Warning (10034): Output port "DRAM_WE_N" at de1_riscv.v(41) has no driver -Warning (10034): Output port "FPGA_I2C_SCLK" at de1_riscv.v(44) has no driver -Warning (10034): Output port "IRDA_TXD" at de1_riscv.v(57) has no driver -Warning (10034): Output port "TD_RESET_N" at de1_riscv.v(78) has no driver -Warning (10034): Output port "VGA_BLANK_N" at de1_riscv.v(82) has no driver -Warning (10034): Output port "VGA_CLK" at de1_riscv.v(84) has no driver -Warning (10034): Output port "VGA_HS" at de1_riscv.v(86) has no driver -Warning (10034): Output port "VGA_SYNC_N" at de1_riscv.v(88) has no driver -Warning (10034): Output port "VGA_VS" at de1_riscv.v(89) has no driver +Warning (10036): Verilog HDL or VHDL warning at de1_riscv_v2.v(124): object "wRead_out" assigned a value but never read +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(197): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(198): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(199): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(200): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(201): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(202): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(205): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(206): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(207): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(208): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(209): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(210): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(213): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(214): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(215): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(216): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(217): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(218): truncated value with size 8 to match size of target (7) +Warning (10034): Output port "DRAM_ADDR" at de1_riscv_v2.v(31) has no driver +Warning (10034): Output port "DRAM_BA" at de1_riscv_v2.v(32) has no driver +Warning (10034): Output port "LEDR[9..3]" at de1_riscv_v2.v(63) has no driver +Warning (10034): Output port "VGA_B" at de1_riscv_v2.v(83) has no driver +Warning (10034): Output port "VGA_G" at de1_riscv_v2.v(85) has no driver +Warning (10034): Output port "VGA_R" at de1_riscv_v2.v(87) has no driver +Warning (10034): Output port "ADC_CONVST" at de1_riscv_v2.v(11) has no driver +Warning (10034): Output port "ADC_DIN" at de1_riscv_v2.v(12) has no driver +Warning (10034): Output port "ADC_SCLK" at de1_riscv_v2.v(14) has no driver +Warning (10034): Output port "AUD_DACDAT" at de1_riscv_v2.v(20) has no driver +Warning (10034): Output port "AUD_XCK" at de1_riscv_v2.v(22) has no driver +Warning (10034): Output port "DRAM_CAS_N" at de1_riscv_v2.v(33) has no driver +Warning (10034): Output port "DRAM_CKE" at de1_riscv_v2.v(34) has no driver +Warning (10034): Output port "DRAM_CLK" at de1_riscv_v2.v(35) has no driver +Warning (10034): Output port "DRAM_CS_N" at de1_riscv_v2.v(36) has no driver +Warning (10034): Output port "DRAM_LDQM" at de1_riscv_v2.v(38) has no driver +Warning (10034): Output port "DRAM_RAS_N" at de1_riscv_v2.v(39) has no driver +Warning (10034): Output port "DRAM_UDQM" at de1_riscv_v2.v(40) has no driver +Warning (10034): Output port "DRAM_WE_N" at de1_riscv_v2.v(41) has no driver +Warning (10034): Output port "FPGA_I2C_SCLK" at de1_riscv_v2.v(44) has no driver +Warning (10034): Output port "IRDA_TXD" at de1_riscv_v2.v(57) has no driver +Warning (10034): Output port "TD_RESET_N" at de1_riscv_v2.v(78) has no driver +Warning (10034): Output port "VGA_BLANK_N" at de1_riscv_v2.v(82) has no driver +Warning (10034): Output port "VGA_CLK" at de1_riscv_v2.v(84) has no driver +Warning (10034): Output port "VGA_HS" at de1_riscv_v2.v(86) has no driver +Warning (10034): Output port "VGA_SYNC_N" at de1_riscv_v2.v(88) has no driver +Warning (10034): Output port "VGA_VS" at de1_riscv_v2.v(89) has no driver Info (12128): Elaborating entity "clk100M" for hierarchy "clk100M:clk100" Info (12128): Elaborating entity "clk100M_0002" for hierarchy "clk100M:clk100|clk100M_0002:clk100m_inst" Info (12128): Elaborating entity "altera_pll" for hierarchy "clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i" @@ -3016,7 +3169,7 @@ Info (12133): Instantiated megafunction "clk100M:clk100|clk100M_0002:clk100m_ins Info (12134): Parameter "reference_clock_frequency" = "50.0 MHz" Info (12134): Parameter "operation_mode" = "direct" Info (12134): Parameter "number_of_clocks" = "2" - Info (12134): Parameter "output_clock_frequency0" = "100.000000 MHz" + Info (12134): Parameter "output_clock_frequency0" = "50.000000 MHz" Info (12134): Parameter "phase_shift0" = "0 ps" Info (12134): Parameter "duty_cycle0" = "50" Info (12134): Parameter "output_clock_frequency1" = "75.000000 MHz" @@ -3072,6 +3225,15 @@ Info (12133): Instantiated megafunction "clk100M:clk100|clk100M_0002:clk100m_ins Info (12134): Parameter "duty_cycle17" = "50" Info (12134): Parameter "pll_type" = "General" Info (12134): Parameter "pll_subtype" = "General" +Info (12128): Elaborating entity "altera_uart" for hierarchy "altera_uart:uart" +Info (12128): Elaborating entity "altera_uart_tx" for hierarchy "altera_uart:uart|altera_uart_tx:the_altera_uart_tx" +Info (12128): Elaborating entity "altera_uart_rx" for hierarchy "altera_uart:uart|altera_uart_rx:the_altera_uart_rx" +Info (12128): Elaborating entity "altera_uart_rx_stimulus_source" for hierarchy "altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_uart_rx_stimulus_source:the_altera_uart_rx_stimulus_source" +Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer" +Info (12130): Elaborated megafunction instantiation "altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer" +Info (12133): Instantiated megafunction "altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer" with the following parameter: + Info (12134): Parameter "depth" = "2" +Info (12128): Elaborating entity "altera_uart_regs" for hierarchy "altera_uart:uart|altera_uart_regs:the_altera_uart_regs" Info (12128): Elaborating entity "regfile" for hierarchy "regfile:regs" Info (12128): Elaborating entity "altsyncram" for hierarchy "regfile:regs|altsyncram:altsyncram_component" Info (12130): Elaborated megafunction instantiation "regfile:regs|altsyncram:altsyncram_component" @@ -3118,14 +3280,14 @@ Info (12021): Found 1 design units, including 1 entities, in source file db/alts Info (12023): Found entity 1: altsyncram_bdq1 Info (12128): Elaborating entity "altsyncram_bdq1" for hierarchy "ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated" Info (12128): Elaborating entity "riscv_core" for hierarchy "riscv_core:core" -Warning (10762): Verilog HDL Case Statement warning at riscv_core.v(180): can't check case statement for completeness because the case expression has too many possible states -Warning (10762): Verilog HDL Case Statement warning at riscv_core.v(200): can't check case statement for completeness because the case expression has too many possible states -Warning (10230): Verilog HDL assignment warning at riscv_core.v(251): truncated value with size 32 to match size of target (5) -Warning (10230): Verilog HDL assignment warning at riscv_core.v(288): truncated value with size 32 to match size of target (1) -Info (10264): Verilog HDL Case Statement information at riscv_core.v(274): all case item expressions in this case statement are onehot -Warning (10230): Verilog HDL assignment warning at riscv_core.v(316): truncated value with size 32 to match size of target (2) -Warning (10230): Verilog HDL assignment warning at riscv_core.v(320): truncated value with size 32 to match size of target (2) -Info (10264): Verilog HDL Case Statement information at riscv_core.v(326): all case item expressions in this case statement are onehot +Warning (10762): Verilog HDL Case Statement warning at riscv_core.v(181): can't check case statement for completeness because the case expression has too many possible states +Warning (10762): Verilog HDL Case Statement warning at riscv_core.v(201): can't check case statement for completeness because the case expression has too many possible states +Warning (10230): Verilog HDL assignment warning at riscv_core.v(252): truncated value with size 32 to match size of target (5) +Warning (10230): Verilog HDL assignment warning at riscv_core.v(289): truncated value with size 32 to match size of target (1) +Info (10264): Verilog HDL Case Statement information at riscv_core.v(275): all case item expressions in this case statement are onehot +Warning (10230): Verilog HDL assignment warning at riscv_core.v(317): truncated value with size 32 to match size of target (2) +Warning (10230): Verilog HDL assignment warning at riscv_core.v(321): truncated value with size 32 to match size of target (2) +Info (10264): Verilog HDL Case Statement information at riscv_core.v(327): all case item expressions in this case statement are onehot Info (12128): Elaborating entity "adder" for hierarchy "riscv_core:core|adder:add" Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component" Info (12130): Elaborated megafunction instantiation "riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component" @@ -3408,6 +3570,7 @@ Info (12021): Found 1 design units, including 1 entities, in source file db/cntr Info (12023): Found entity 1: cntr_ohf Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_a9c.tdf Info (12023): Found entity 1: cmpr_a9c +Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder Warning (13039): The following bidir pins have no drivers Warning (13040): Bidir "AUD_ADCLRCK" has no driver Warning (13040): Bidir "AUD_BCLK" has no driver @@ -3438,9 +3601,7 @@ Warning (13039): The following bidir pins have no drivers Warning (13040): Bidir "GPIO[2]" has no driver Warning (13040): Bidir "GPIO[3]" has no driver Warning (13040): Bidir "GPIO[4]" has no driver - Warning (13040): Bidir "GPIO[5]" has no driver Warning (13040): Bidir "GPIO[6]" has no driver - Warning (13040): Bidir "GPIO[7]" has no driver Warning (13040): Bidir "GPIO[8]" has no driver Warning (13040): Bidir "GPIO[9]" has no driver Warning (13040): Bidir "GPIO[10]" has no driver @@ -3469,6 +3630,10 @@ Warning (13039): The following bidir pins have no drivers Warning (13040): Bidir "GPIO[33]" has no driver Warning (13040): Bidir "GPIO[34]" has no driver Warning (13040): Bidir "GPIO[35]" has no driver +Warning (13032): The following tri-state nodes are fed by constants + Warning (13033): The pin "GPIO[5]" is fed by VCC +Warning (13009): TRI or OPNDRN buffers permanently enabled + Warning (13010): Node "GPIO[5]~synth" Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "ADC_CONVST" is stuck at GND Warning (13410): Pin "ADC_DIN" is stuck at GND @@ -3500,9 +3665,7 @@ Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "DRAM_WE_N" is stuck at GND Warning (13410): Pin "FPGA_I2C_SCLK" is stuck at GND Warning (13410): Pin "IRDA_TXD" is stuck at GND - Warning (13410): Pin "LEDR[0]" is stuck at GND Warning (13410): Pin "LEDR[1]" is stuck at GND - Warning (13410): Pin "LEDR[2]" is stuck at GND Warning (13410): Pin "LEDR[3]" is stuck at GND Warning (13410): Pin "LEDR[4]" is stuck at GND Warning (13410): Pin "LEDR[5]" is stuck at GND @@ -3540,7 +3703,7 @@ Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "VGA_R[7]" is stuck at GND Warning (13410): Pin "VGA_SYNC_N" is stuck at GND Warning (13410): Pin "VGA_VS" is stuck at GND -Info (17049): 4 registers lost all their fanouts during netlist optimizations. +Info (17049): 34 registers lost all their fanouts during netlist optimizations. Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 5 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL Warning (21074): Design contains 17 input pin(s) that do not drive logic @@ -3561,18 +3724,18 @@ Warning (21074): Design contains 17 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "TD_DATA[7]" Warning (15610): No output dependent on input pin "TD_HS" Warning (15610): No output dependent on input pin "TD_VS" -Info (21057): Implemented 5054 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 5105 device resources after synthesis - the final resource count might be different Info (21058): Implemented 32 input pins Info (21059): Implemented 112 output pins Info (21060): Implemented 60 bidirectional pins - Info (21061): Implemented 4672 logic cells + Info (21061): Implemented 4723 logic cells Info (21064): Implemented 167 RAM segments Info (21065): Implemented 1 PLLs Info (21062): Implemented 10 DSP elements Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 215 warnings Info: Peak virtual memory: 670 megabytes - Info: Processing ended: Fri Aug 27 17:21:13 2021 - Info: Elapsed time: 00:00:22 - Info: Total CPU time (on all processors): 00:00:22 + Info: Processing ended: Sat Aug 28 11:02:31 2021 + Info: Elapsed time: 00:00:23 + Info: Total CPU time (on all processors): 00:00:23 diff --git a/examples/hdl4se_riscv/de1/de1_riscv.map.summary b/examples/hdl4se_riscv/de1/de1_riscv.map.summary index 743ccac..f9856d7 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.map.summary +++ b/examples/hdl4se_riscv/de1/de1_riscv.map.summary @@ -1,10 +1,10 @@ -Analysis & Synthesis Status : Successful - Fri Aug 27 17:21:13 2021 +Analysis & Synthesis Status : Successful - Sat Aug 28 11:02:31 2021 Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version Revision Name : de1_riscv Top-level Entity Name : de1_riscv Family : Cyclone V Logic utilization (in ALMs) : N/A -Total registers : 1608 +Total registers : 1636 Total pins : 204 Total virtual pins : 0 Total block memory bits : 67,296 diff --git a/examples/hdl4se_riscv/de1/de1_riscv.qsf b/examples/hdl4se_riscv/de1/de1_riscv.qsf index 8b651c8..eb89178 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.qsf +++ b/examples/hdl4se_riscv/de1/de1_riscv.qsf @@ -488,6 +488,7 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VERILOG_FILE de1_riscv_v2.v set_global_assignment -name VERILOG_FILE ../verilog/riscv_core.v set_global_assignment -name VERILOG_FILE uart/altera_uart.v set_global_assignment -name VERILOG_FILE vgasig.v diff --git a/examples/hdl4se_riscv/de1/de1_riscv.qws b/examples/hdl4se_riscv/de1/de1_riscv.qws deleted file mode 100644 index 237a0d14a4d22917f0f97b8e6d42ddf1875888a6..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1034 zcmbV~O)o=H5Qg7-tKutRE3s%05lMwowGtue%1Z17y+wRfsE~+l|A(cWjbCA7i{HVf z_3_N~wmvK2+{~FXb7tO|bKjXCRbvfkS8F;_S*toxNr&3OI>5J~C=LqIOFB~)Z$`5! zaw>98qoOZj9-q}ZF_F$+Sqh|}ALLi7@{Cv+Q}e5hxCQ9>Qc;0a9%kkju_Qt?TdNkn`T{JpJ-X=X>^NNa;>@g&7)<`Ni zDOuMAetTL|kd$#kK9e--bbTdhn&?SLu9F0EaLLvr$==Ee(aD^X6jZSXwF2qu3{#{O zV^m~cMDH_Lk?%)wW->>((aOYV8(pOK zDNky|&#;gU?fevEjhT#US=-vw)_*EF&43JhQwP7dN?d)K{7~PRUGHLyHJ1{Y&IAAe diff --git a/examples/hdl4se_riscv/de1/de1_riscv.sof b/examples/hdl4se_riscv/de1/de1_riscv.sof deleted file mode 100644 index 5d9ec9b874c15e7c0f5fb343f5aaf43f2a58bcc0..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6690262 zcmeFa&8}?8btbl}SYlJM+FdORMgxX{zy$|2v3RLJv;oP8Ze6R{4G2v`u;Ce#Vo@zN z*rGsEjUEQzNew*U6By+O@X+)06BsZ&Fg!Aheuy3zkmKiDUqr0<+nG1dt#j(cCYTX> z{d{Y!FCt?{X52jW=l}9gk8u6E|NlqFzx1#F&ENj;=fC{hUzmUX&&?nH{(tdLfAUN7 zCqMf)fAf={{`lwSzx(mefAN!_{k8e-@BPkqf9I|Fr+@pCpMGw>`-i`4zWeq&zx#XN z`Q5kQ{XO&N|HAy~-~RNcVtagi{CyAl2Y>SC|Mj2!lRx;=-}~;L{NeG98129P>tFul zmp}dS=f`gyf9);)?jQVzzxV(BU3L9ufA=5#Prvp*d)?vw&+vL2|Ih#Mzo!mg|L*Vp z-hcRKyo;SbIxhe2a$U;NeY{KZc~uK&xg|6l*x|NY&6@t^74Yz8(1n}N;1W?(b08Q2VL1~vnmfz7~XU^B28*bHn2 zHUpc1&A?`0Gq4%h3~UBA1Dk=(z-C}Guo>74Yz8(1n}N;1W?(b08Q2VL1~vnmfz7~X zU^B28*bHn2HUpc1&A?`0Gq4%h3~UBA1Dk=(z-C}Guo>74Yz8(1n}N;1W?(b08Q2VL z1~vnmfz7~XU^B28*bHn2HUpc1&A?`0Gq4%h3~UBA1Dk=(z-C}Guo>74Yz8(1n}N;1 zW?(b$>=fS0YPBpCe|y}w^jx#eRo~^ZSSR#_5BL?rRqcN)pc$v)I*v9&eL`-PDXyBo;$(} z{rX?_>tEuoa5JzO*bHn2HUpc1&A?`0GjJmV?wo!4#PHd|`21&~1=}sJtR0P@TF5Nu#aql`2&Wau}f6m5w&UT+Y z=j2juuleBeHP?=r`2uF>&3pDIf7AWSfhJndo?_Xf82I&Qzsz-C}G@Uj>vpB`Un=I^y=cQSV!Szl!O;;wY`dCCTB7hb-W zm-`B;8d3eoRO}V4ZYOQ?O{AYXg`$l_yYGIx;WBcB<^JCJX1@k#7!Gq4%>+B5Lz z4~}0gVS42>@1M>`hm9b`BV14m(J+q6NZk(Iw&KYdII~H7-*<<5@+w|JfX|+PlCSyT z@-^3vnfXCx=wiWn@S~xAINkJtvv%#id4tJ6sx+p$^M8=d)q*Fu>*Q(6Fo9853cjZO zuR)ESp}c*t%BQu_?*1Ln4N|}D>N}0G?>7URffvC*xfa}=uvMP=KByN@b%jvfsvOlV zfNkOOtzrd(b*XlR>AY)7^{9ex9nq|aIaoqH*b84bo9$7}$pfmxa5aI-fjC@sSJK*O zwB?!m4v0PD=WXEH5-|mEU2O~E1H8=Z10RXqMbc|NxO~mEr^)gmXQ;hvetM^SR|NIM zyf=K`&-BGXdRtsK2D(M#WD&l_=~>y<57j2MduKrdqy>m;DL3rBZ)Z```@+AMzl+|_ zIm7oVZ#!=WHUke}pm~~gKBTxh&bdXU0j@#(_i>#_%I3Xp%LL2{X;2eVETP6o)o10g z*;k-pb!Hm;T$xjd7r#yERrkabwHNX$mVNdW$3GGNH6L8Q=GrkeUcd}JF^RXyW?(b0 z8Q2VL1~vnmf#=A8dyYx%oHhfSfz7~XU^B28*bHn2HUpc1&A?`0Gq4%h3~UBA1Dk=( zz-C}Guo>74Yz8(1n}N;1W?(b08F*<7xEGM{ll_2g*Zu++`0z87zv%!wukS|+FJM~i z6gLB#fz7~X;A_Hw`rLzvkL8E-zq)KIa*fxwfm=3~UBA1Dk=(z-C}Guo>74 zYz8(1n}N;1hhyLc{PEe>{3n86bM1H&e3%)Ee}jyFdYu0Sd^$2Vr{0j-tN3r~K_xi& z`}#PKwh8^zAKe!O?^1h9u;L$2=dO6wahWeWDUreJfSbd@zW8U{t*A@DskjdCzDeny z@{<1~L-u~e2n!lg$RpON-TH*Xl~fq4BpSXpfZ*K0qh>K<%1Bq^YldM;g~QFLq&kD5 z&JslR)y(97c2E8TSti*x`R9?%Dw*cqMXF>pd)V0jIFbA*>H7#%g_e^}$G& znFd9t@iJ6m!Kn8e>B;MtlVs*-J?n7kQQk*gL4@G@rXSZbP6nl@?TolFFl97WB$auC zJ^{DHJr0LJw|H6j$o^XPHCcYo2-ns45R=-WLKvpg?c`|&FU5Hs*AW9|B6ws;Dubd> zMsGS&tF(uO$s&I-tNvrN4!-CjFA{O56zbS8q zt8~t^jn_BD>w?ZVQu~imbA^;I5Q)R3z&?{`D9R+FfXOQe!jJl)(^w`wfi@dQ(k9AX;4*S|mzJ~D*XZAeYAq)d} zg~`hPj^op8kh|iA5b$Ka>}20g4{+JIpFr@maL;>!E&&+|_PxesVM_m$mwdX(-j5hz zK|>08#B!mm-6HR#0#}fYng$S@J2=!VW=t9BYJANoN+ox=8xwN7yRWg_b*>Xrm`ij#d8jm{7nbQ|y=?)jWa$0qmcnfej=8Lk$i_7)Y-l~EC zW6454Zq9cRG^t12bWSIwq7?zB;=U0p1KQ+%+Df+a_Er4k+HV@+`tb3cWFX+-UTW{q zBId)k0j#Ug(}?dOmcRP)jp&6FNdcSc19A?>_Zk-MnSmk}x6+}a>*4g#ij<7M4VQ_pRONAl zyw~JSU_aYBt|J7B62T)&s`-)#jNI)YzRb`(XBPQeq6vZ*I0}&p@7JAEq_1J77J1C3 zW>28BPk?y_^1itDd9Ct!;t_VM_)nmJf|AS=r1>6@cy~)yTs&`jD`_vsgz6UfD7%o{Bpmp5x5dni)W1t*W$!K|jbj0fuK=rI+sJvwwiWjq0{7`<+ z2&-xerrX*JT3E=aW2xw8tKyOm13xvsM4NR$go0*C0!_YVSkMWj(sIY4f;9OvNcQAD zEpJ~=WbjN)94mgN3Hr2N^TFk7u074j4>CjFA{O56&FK-Bf!VvH@sjhq!I|Y1U@*f{ zG>dQ$={S_Psvw|1sX_2>e2f-Qi-le|Rd#d}2LoU9JbI zsl!235HKuR=*P|Z&LUDb;zlJ9?4_a=0mPnl-iXp1M!M@(vX!xZ%m^nm8P0c-hJc5A zsl7vsm=D_qu&zSl%5d^M1T!J%rb)Xfsm@@Sd8Lr}`_Q(cW#4QDHUpl4YIA`nZy*NG ztNe(Yuw|)(m!Sa5V!huGaF|(I&pKRSmA9%OLU7B_kDCM1a26RHWG_`^0b+n7Ex!y@ zi4-pI=rrWsL3xXpB_O;;RWJ%2Ivqi)htnGtDH-@l3soLB=zC4x1opG7<2phhc@f+* zX=`YY+|58DFmktp_%cKNwhv}?5J%_Hpag@)ie9_38Q2WGKn6w+j=cPxD2hw2dZsj= z&_|2Ti5U5zpn|9h0+cLzgT+qP(-TpHiGkgyN=C~Iq=U9>+=x3|qk`DvFdR`H1+5r&?nv+MM$=4JtDTPvL2T$&!$)7>8 zC--T20-nfVn`{O)1J9L#w<$4)w|jG>cPj73YjI|I1uD%>M7hxBiXOaG1wjds@71S# z*P!$l^G&yl*C97`0ueX&yiQ~hF{vdk4{dMqVvUL)%CD#3U<9uVZc$Ci^ytv` zToer`wfEyTzf@I+wx?qDp;?m3;1uK)R?>2&U7*mjpb3&ai%}OVfW)TWUgV8U-jkNr z{eI)cO@M4y4ID=slRj=K6$CF++nTz9;PYvCiI+iJ$IbadJ#PS)z4{3R5DTOg0Wh03 zE^E1m%A#Qp*=FyWpQef-P^l0!c;|d_p{(7)u~3yz-F^e8sz6+mob%k2k*>$L8$t^m z1f!Bv2HL%QuO>$R(6q=OYLA&qE4or8W6G(U98r-zIe((%q>~Rp;q`?WyTiqI|A^1(~oP% zQF@vYHwMOxb{ry-mR|;{MBq7Z5I1kM=H}2g***4efC$$%xhS9 zMR3ogt)V?~KLduGbtJyDhlO<=#1W$zEP9rs&WS+358o*g`|!bUj`$oHyE*CY@O5VZ zZz6*_xkBdU?*s$d%h5-zCZk1%_Tx@||ELF-svsb6Ww5}j=QustYfG|`n;cY#EaP~eki|ZgjF>K({1eqEwg;1&eEcvt%^%N4E)si5^dH25ek|m z2{iedVL>O9N;`UTH~BM2_T)Y-Z{bd4@Jvk{D}JU4`m|p2uT5Wb?P*4SkQw?GvG8_( zuOq$YN3i+#vGr-yH3j7#)Wz+zxlnsWuRb$%T(EfV=I#1%StT)N9YLno71nhEQ7DJC z(jFJs)`>tkZzOJUd^dN9TJd7Gj~w9(5Ar*3(Wg%%dNO`9r zUU*MqLv+jb%?ANo_EP(*VgsOZ^3MHDpI0m|mo17VDGLWZWShNfewr!28JT8{5D zH=WZ-sc1#Oskm>%%78YxpSF^%%xJ|=uKlJFt`AS&Nd^KQ?xpq)En+@w8^F2>J&m{^ zz)T2wWJz@f!^|s%#NUUu6)pQ_Gq4%(4B!cZN0}ujcwXg495rpH@iMf*vZ(eO0Ebz2 zr(37P1@@@DRRz(LkHvo69FT^cfE10mF|a5=L?kW03{;5}E&%B?N&i$yTyoVjg`cl2U`C71i75G@pn|9h0+cLz zgT+qP(-TpHiGkgyN=C~Iq=Uy&R?jQZ&f7&v0!<$0Xi+Pa z{))CL$SD8rpfpty^)+{7TA$+JhBfRI-pc5v-^zn(gtT}ll zv*=|D7p$Y0hYnA5fSb~_aO!lU2T;TtW@QCY#I>8>tT~uQPq~3?)+D5Yn`GQiAm~gq zu<7ffEWyuKYQTzElh;$2q|434Z_oR8>e^OryA^G#(CSYF>@w6q@jHrW~L}28HLiE0lgOns`JV zWRSlLe3kEv=-*TsrSav0?l)2!KiLPFi&a3mY8tQK3?6U&|F5CruWzO%i2Nns(JYCU zuh(c1(p27;sNi=`;Vz1zSwAlGh3ldjaf9?@G(bp23j!7ap^k9_5@@@@tN0S@Qldc~ zWI`j<^G1E+6KM^yOW{`4UaJbLezyTEIqy%SYe0gTnpgc8O1dhk&OkZ$Z-vs-hMIao zFrL?dQ3kpAdqD`gSkyK2U=_M@h4mm@pV;vFX?RK3$3}X~w(&}k(a%3$!}To}o3J8> z3*cd~JbAgouJ*1g2xd0hcH})C-(+vyX}sRj=NqXvS#)T+=m5!EAvFY16$BI!jTXC0 zFgkyYxKRlNKq*{WE|iLZQ^658KWlFBx`?rmF{(oBrmdjW!&x%j)Gl$SxS|9-8Bk?g z$GwW%0W%TYGiht+VFnC2>qvZQj|;5pAXj3jGC8+{L1RU)-PsIm23{Zo*hhVuQg^JN z*yK?*>NH-Kme~6k2(Whmcs8T`xRZBL%Db*00&sI_fLF(Lke+Nt+*tTCTHc(C%764o zMh3Qd^8~@9L0oTfhnFL8%}N7Ctgi>jbK@gq4m>u}Mn&7k*g6w89uo-xf4D_E|$6-=6_Eb?=A?cN$ z4r<9#D;t&*y3c~iy4nO$6$FgcV#k0qoJF=!(#t@A^h*#~Af=UW_#9k7KH;h+a4iW@5!?`AWw8F+~dn8U=h@pm-7kQ&_Kq`Ph#uXo~O4;#Dn zpY{;&8~&w5@fT*4x2hn7GhDp-ahY$-ZTT|d2I)%z0Y@rY5U>mx4fNkMIp>9JTP8bq0-l zPayFfwhUo261%JXIUxlhpilp9&?hOrNe$!4<}QgBuZEyUE~uiOM&RF@h*>?p@Le=D^eTe|SW>Hr;e~Y&TbcPAlLXyC zX{$`e{?!3?bb54(`U~N3TJ@HK{%KWhW@tU@0Lh!w-l~ECA)@7>tqa!6Ys3wz%+Z>I zOAp;8z%6421H|R=-A!JXfDkT8Z&bxiBV1RL!9yS!bVUm$Sg;shk3F<~NJ%wccAR^m z!OWBydK?!hYu>JOse^d2Aoy-$MXz<|6zOZ2sYPCDre;r|G*5te2J*hR_j#@IdEyba ztN2f#e}a-eeS$RK1G3&+I3nHhR%*N~VX*EQ2*78(6tx$$ z1kLm^)b_Jgamj~JRF5ygW*rBmf@Vn#k25gnBBgnT`prl`h|XWkIJcvlwgT2}HUpc1 z7s2<;ZO|5J+I}uFQ)#Fe>R0RQw&k+~y{H5YD-=tle5wBirlhv1p58p}he{xLN71hx$2)=Q z6L2oBKD0gOr4Jh)GQ#Tc@r{%x;AQPKEk;bIZ39?Wp;_c!24?l4t(%4t<*KAQgHv0F zI5WRI4o7PhM5d$8pA#}7Aj5rVd*FSHiBDE#2g)v=2e-7K#G6(GFAG~PD7c?B z99&6%W=x$ykKRZR@}>$pPCGz@cdnvSy8}?6nnDL<18Cq<$F)hC*Do=v#}~efriNZ+ zumDSHH8H%f4q_`ae`AuMJ1A|H$=JU-z|KyOXgum%sHo3Vy|{l`)tC`r+yRm|sJ&GM z0YF5{L)&q*QZwS_Z8FNynuAMk&?lgTANCQqJiZ&+W`)jH($jLGF?&vW7wGD0N~W9I zCGG?@s~&r3n{g+-3v{EB8onl2qQcC~)b@j1#a_AxiiVxW%hI&opB>#D1C6JhyyHS@5~QvmVsO7>09nU%ke+OsjZZ&;fMx+H zEx!yjP#_W9&6~VOy2Hy6yXGg$?-^k=oaNrOshxwsOvW8URX{@Zt`Nb@Deo2 zO@bGBx*NU1t9b&IDM`&WEqUBV*k10a>u0Otf{(npsppj?+N`rENkCx6kTXaFrL?0b zH^D3%^q@p>V+G^gYz8(1FOdOrn3y(>sJ@UI+~K6VZX2(6;$sgRyK-8U9zFt&<2^B+ zww7y;@>UfD5W~f*AD8(~BT_lyraqmF=2Fpu076eY`p|Z2Ol5u881^P6>PA)2an@0X zk8i|Qz{9=N-l0XzhiwB`SD~j7p6B7yU+mV0w!m7M$?yet$ckqiZKx8dYO`sch1u;^X$lR;7ywi~(;0uA1I#PUe9b_eIA0#^-S zEocA@^mSaDq#0Aps_}(YvK_zH(2ER;I>(55W_rsyh)upt{(4ZNSz~2Pa`)2=u+0$_ z&Yv=#cy!teW%YTg7uQE(R~Xi27SeeGByUuEs|o^$h}MU;sD2)K#Le5}mZLQXm)@XH zz%6m}@!c(67pY0o8&z@B2-nq=OgFVl-28Tsj5_UO4{aY(Qq7m^B;ATIGi8Pz#|1Vu zZ&!NOLA+QHe7CWp*Y0cvHUlq^fogNXZ4S3~rz&!^!ZK$mz}CV*fX78+M*DFGNcne+ z7PfT-QOE_}z^0DtAU)Y&uadn~`iyoQHb8zKZRpEp*~A-enQ%96@*e5bQx;%NwlzPF zF;6{`U@cy1IQiKlnAz}B)LzgMG}Fsa+s{_TB_BdjJ-!5+bsUrmnk6+n&cL9Hl;#=g zHzWNZI)5>%-*(yxSZ5j(b;k5=8*{hk`#QS!1-R4yzPR^!tx|mI5$5DuCGt4^6O?2h zm)#?fMh^~?!0o9RTvy?BaH!Oh1wNG--DkmMT|Exvttto@e2%zq=PwnP0cn`b`mYvZ zdKm~%WeFmMORK-4Kq93Jz}m)AbdMLaMJz$1+$4CBr@PTBywq?OOnXPExuzwL+X&ms z9d-R|Rb23qH#HEL1Y?Od>nutV5STIK4AMX;?dZu(FbfAgC{f&4!FV^Dfz7~6WWXFI zru|+=dS6K8?r^dDP6YO_vD-g9m191!p0zfuJzs{E*+oNjIEV^@%5d@O$7Q||XZbSX zMkNq%qGiHsvrP}Xnklq4p(SK+`LUT zIa+gY=?(e>6zJnF;+DsEV`FM`wvwKf3ypM~buLiW)s##(wM*O?EOn1Pv?c7UbAfVH zQp48_3_8rrOl?2Nl~7F(LGTuh6}@(6Gq4$Wfecie3vP3`wL4XjqZOX@mI7=o3AHb8zKZRpEp*~A-enQ%96@*WB4 z&&{E2vaR`X1j+j{iiREWQp3s59>LLum!kH9mY|tlhT49%DlYjDit6zt*sSBARM0G` z;c*5AU8FS6P`?@J2hsV9S^c)tR>0cLW?(b$A{iJxI83U>ohpj!D!dN8P6&)z* z6+e`t3Ws9m4ZM&+_LwBWCsZW;CF5n?5urk3hq$EVK(3ga#UE zM^El1e+0=00jRM8`ffG@n}L_efWZneI+#3F(-&gp4i~%cL|_jayK>r=9vEVV<2^B+ zwl=LjUmiY$iXg z@<_9G2j`>$R}Ek-XaEiLbzGaI8B@%v@r6~g9lzGliwuf7$B24nddoV9O})!8DT+7-WHH~nF<1#W;F-kiXPpL zrPQH^AvCx}))>x=2{Q|`N0wA&;1FQZATePgKR_1w>p_WOnksW}wYzvH8hcpjuG_}z zjrf?u#O`#yN~q`}O_jp5PPa_nK=5tsi2BTExPmEI-`w)aJ4=8|uc3 zj|m4iz!==tI|h+L*>7AH*WMNiK8%k;MBLpP*uazdI>_hEh#ORC3vVf0+QUIv6Cl#U zv(sfoCMjLVrWNUIEljjrK6KqO!VXyU5%3_FniVbJ9G-)w0j#riaI0DLLYNuo5sPRL zcNukHtob+QY(nk-wO6ZU;9PUgCvRmv6_)$0IP~#Y=lczx_0K(?wU>Z;Y^cM>;X6W>xO{wX##So39nrOPQ^6@v8i{;OMisW{A7?sW5Fxq zwH*Ud^0qW^?6G#m0S2qE>vSz;4n1&gaEq*wY{rC{h1nxZsxoj0uxOANW`Q?0a9HFI zwKvYC6Qh)8F!Krg+{GGI1@LAL=iz53hU=qk@gX$J({6qg&Vo4lB1QCs9a$&?lypRwgRH25qFdZ$Qa*;lvHOR5fEt5Aihixer#~C zALY-%%AOo`?|Q19G9`&u${yb5m^~bM1(@ktSw2>OU)=k=7MZ(+{(aTveF1LwcelGN zJ!DN<8h#jq{*#N3sZ&WRaU7k`=f8eZx(+fja^!lJv@%cG}l=&s?KD6aOQunm=cN_(=xr>=@K{hzccRdH%9I0P+uTR{5vDtoM5aR9CgyH3|q z=Fr0s8r&jlB%3i|W?}ZolBx_G0xTLNmX|66heiHSd*fVM(M2jb_(P8L-U*&PZ0x=f zfjLal)=d8$5#cACdA5;ZdYE#GD;$g4fHB}Kcl z8F;k}SXACT-0{>d9@%4#@|FNzd`vhvVf8V%t9%=rO(|4&rXJDyhyuB6OiBM0}x^9~&GjM)`9>X3yg=ggsRc zt#@ZLuo-xk3}AhzS4f{Jm%kHPTiPsE69>b_i~!?KUU8InT|oqpMNfSp8yy%(mD$!{6oi4m7p+SNk!6*4sCCW%R}3nyqN7HM_3K#nM2!CNndHz z&sN1<9NH3W+5tfdnk8M}Odh9TNr`za|E$0Z`$3xg8AK2QUSpMl#8-zt9_xI+6-P#e z^`NW01k{^DrFILAFLr9Xg{b#BSOeXj3(owvIj4-r=Ay>US;04n0*x%_1g%H-(vnS5`nUX$*9u zl2is0q^zoErk5M&7WqT%jf)C$7pVZtH~Y{wb1~?-!$r+I(aYIf=kEZ^uT9^Gt--+6 zr`DpKw)@W`hj(S1v5Lhngf|%)oNCL!hW7XhFZjG9`5<6y`Dwb7<$8cD{$a3#jT71mNr|5AW{>=!a46K4iSyw=6vBhZ${jx z{dWM7jl8r>J3ce=mT4XkT2^FEnb%&d(GKJ?R;RFm=3tC!j)Li?c6$nV1Xy$KYBPgd z?kGiY$E0<@YD%gzV8m%h;!CSPE;O^C2|~|uuE1&<`fH=)Kz!8|J)1wvsg_W3>z~7j5~S7QQmb05r9ip{~=+=QF@vYHwMOxmKR7-@o}IM>4j-z z%@ez^=n0x^Ykn+!?it}T4+nz?1ucv@>TqiyTL4u>9oG>CW+HfGNh$+|oOL9=w1vn@0z7_Ub1P@@V(MeFBj4v@z6L_D*z=tr1g)&Zr8po3;kpRE?#rV~@3W zI4F$zT}!b;PgPN~2>!h(%q+aJ0)k0npc|E>GMFG`RXs7h+(5U;A8K!0RFJz!1z5h> zhqjrELC+m7YTk)n&Ib3PtxTWDj2u{ZXc6Xy?c&JPVET`Ksk#qshs<|&ddFIeoT;Mrq8o)YR0a4S4J4yrC zN0wA)AQ2E~&>+50%a08X_M`kcA+zUk7zRNqy#E?@G6NsFxK}{#kkZ#&`;e6PP;l8F zU|@Y{9voc$27aa3@@BD`I2bl&1Q>Vn#8BRK1rb0NJ^kGXJncA2Pc!1iz?jkU0x2p! z4zQRwxSVP@boY2!hN$_;a*#p0Sx3Au2zhCo)Ly7&&{5X_D$eV;j(9K=!6Qpj88GCm zBk`p@EUXv#iy1d%!Oex2cyS_#V7Hrr&A`iJpnpiV4{eK)yr91iZ4Y&L$`j7Oki*ke z+I?v2N$H;qH;2x8YQ-7XSVd`i`6z8qzUAVr#lze`tZmYtd2PH5_eUR_2=M6e$Y5qd-(Te{Ns{sFs-!xDF;1yT@!=U1RSXsohP*j)t5{L?*HndlR!@w*b^n^RZg^{eO>67n0RkhkA(INyXVLjfMP z3{29ir&rwfnqY#|;H@eM1}={6IBw22STC;;H!6XEBNeR(SjG$n-wrR%|6gbe_sdJN z_47FlfCqTQ2m=kn`MsEhA36aK_fmU@mS{eEX#iCfY8u7DifJnZ-85+zC8-Q%*;6O+ z%Pv58GsiTx$upV%lp^J21*@~$fgX0eoH-;JB|&7ia1h#RCY2?Pj;Rs_tViOxwU z6!cH>&8nBOl`m_KxZ($&Q57q^sQ;FW4Tck|uorb|7Y<5Qbe_DlfOQr1G%98$%+$P^ zM9QjFNp%LlewArK%g114Ff1Z#sw>?5*l~FI~ej~M9JmXT4&E~zvE3Om4=L*Mf zrZy}c{t|GSCGqt2O0Dv~K!FOvorw6zQE{0sTo=uV8>FA3VS)5;tn3Qxng9qF4J$(W z3v;M-wwHliXgq}q#;!0%H6_!z<_;~(7!6=ug^HW`fSDTKWw>ClDyh!k6r@lp?I=i- zKPP1Nqz$von>>n!oyO}^nqu#R$GwFd;Mt7!<4)d1 z)!q&+d7E*Fh}#Sc8+aPro@_?kAbnTBNJY~6jcL*<0t%OLmlfHuO{>w_I+$oVJ{q+E zJ&A#^t|ole$(PjJp(Ps)dfW~=7^rOPxRxj|6Tv-`wua6nsSFr$){*$q9tPHR5KD|E z2tC86OSxbrx4Yd8YzAH;19*2gD8>zq?M!M^^@w)Agi>w29i%+@sNNV+emBSvEIA2K59WHj&e=dUg zirusoWP0@zh#2y3M-~K3NJV{7Z|le#d8k$eSvrXrcs~{Ouxnst9;A zliKTX5rk>$G@xXw;$k@837D9v@fG#7RnUtJrck1kiD5n#i3&2xzdI;Rl>!=Cyc>`; zf1ycpL#0a>O?jS@ah9L+y==3UU{z5cRmAtB#v0^Ob4`nd%e-j-YtFCmu37X#n1P^&mQ-g@JT%6YNPKC(vO`-t&hc@Yywp4n z^BmHt1>+plO;-2Cz0Yfrm|f`KSAA-}zi*J*-`2Mexyw(!hrqojh=YIgaKGiPWSB&~ z74YISJ05yZI|<482z3w#uYy+*akFe;15bn7lg)@5Oh{M2MA2{O?>9#T6fWZ~E3#vo zR-?0ZFwt_Mu|?=e3}p3i9)~MzRqds!udCwvKBF0y7a{e5syw43sr=E=grD zgQ70PFJ|a*7^vzX7E`jJ{&9}7ql>!QO8ix&sN1HA3{+*uLw5lI4Bh~OKL`a1_qr_D(x`{qVpFs?hYfK zwnC8IYz8(1FOq@9k)AnK)ElufM{-!4S&A8s_qeJEOs~bE?PuW$nu64agZ8j=`$BpS z%bhyZW4>5v#k}7NGQIiC(ALbrs8ffJe41eT zL_4Xy9v7MttJ8Vxp{?meXhn;X6ptUb0IeiWj4(rKt%4jbI=vHD3DQihV9;2JS7`B` z0lSQMoSGv5YP`#qP%b+#4?WR2m>a}&jie^z9` zQO`m#DyiXd1XRe?#5j&Ri2NIZoF;;xJdc!BMHf~%&;{N4i0a^vVYB6=*Bk`O`Q34a zSAE*%Ff=rqV2etSa%%PApq$?Y`%8FBK;1IKUxaX(#Ix9mHc;)@+kr=7gxs)IOq6`KnYakFe;15bn7 zlg)@5wf_!iQnpsk0~Z+r?bskuW-Vb$+)6DWWx z+d8f#2+Txq&!nxPb4e-#hMaXIzO;vdbsfYKqX|OKyuGgW&Gg)z&A?{hg)xA4ce6rb z`I8lNT9u;~UX}v2niPwU4-7L$>sbd#-b4kdD~J#f9fQTrF%AtW>2yZiSlAXIB9fL1 zrGYI7C|scEG@1K5yc_`$Yg9#!LXWm1Xlgk5ePi&j;l*DzzEYLP4f0-NDC}pe;)0L7 zxq;xGNvoilx8jQ-nQ5nk_%cI>Pi}&#Ae`F~TU&JkZqa67Gw@;=RaaJ(np({}&Tc1jPG7EimghqiQ_cGTgcJXQQ-h229&vp%$)!iv%nMa@SQ_i)kU zo%l(y>QG+P(^f$*GMGY%Qs%Y6mLWX3V^@BmJj%a$0|msUN(mEMJc*Gt;~k$wqf zmDwqluMDibFHoR@a3`YWFKunGUS1<^?mx7(%b3A{6}?U7HZ_Y^o$UqoS}ru+GQwA2 zHD|0rE`wgv;@~oG8o)Z+E4)u0+CHSDIs-G$KWT+hY4@S+8P>MVX5e)&;814sa6h$R z!P%hI8$vHWv*V%nw3CpW&kL#H8SUUzY%WB^&9a3JJPmG7HY09S0s$?G_AhM%6)wD- zy|@W<@KBuhrxACQ7GC#E+8R3NtujD_c@yFnGxRtN?CT&FQsysaoZG>`hL?CD6}dgp zBHjth`%O4z_e0$2Y3}rUU$^_>-siQ-^@&H=uHrv|{s~IL68!|p-UW&Esd;eVt#m3| z$H?%q6sRSuyXa(hx^+5v#Zf`(3Zf@Oqs1-Jw-%NX!(KmI6_;;INxq&}A|+_A;~-SfEJ^Xj zkUcDs$@53rV-SR3DhPLn5l~x6l-+IyHUlq_0d+|BMrtsJk?y)}yq@mR_OtK=O{vv~ zgZ8jY^b6@ZEO+WqkNJw-v=wA}^%IB~At&os$prz^c%rm;4umH*yP_Pnk}Zx4!}=Z9 zevvm-43SEOI(+2QL?7CQ+Us#CQHFh|0VP`%7sL5ZfW%CVuc)W3f?i}Wg%YI+GxM|K ztN*3#sqMz`vE(h&%MTtdsMKZvv(Q8%2h({|WKwzSFTDZ^hhQJtdNwc^AVrT=!RurI zEOg1+Wy?I$Vamo!+N8o@K{sezme<)@DC%jHF;SHGC&gn*0yHux>O@MtM$OFQfVaFu zkXe(z9+ZgPSmlTpbn7FkWB<}NQzVC{qoZk|FnFkg%h7+-w*a4XF(&($w#OALojkOi zaGF)C9}nwyMD`r^9Nyc~?nB!lRa>zccy$aoRNOq=^HY1xiJ?iomGR;;J05yZI|<48 z2z3w#ue_r;M8wUqg$+CnZcjENZm{8T1xys}L)*YeNlU>{zsnCb;-xt6Pa}RyZ-I*O z?Z;43gZmmf=dChO-u>GUznG!NVPIDWv5+!!fyqvdBSIv(Tv3zT1D428{bjZNabW%H1e2&tm(`f(|=PE8Ij8Ih1 ztBlqOB_fB8g68v1Wl$6<2yH91N_z}~=={ZuyTb^rt=f27vKiP6yc`A|a-{c0>NSUn z-Nl)unBjO&yr=Dx{CVVQL{Zwq#%@z(=X7!(+J>z`d`y(*xkBZr-G{bdM&23W_MNaL z6Hx9$izhK2>v=1X_71WMDLvZ0_7YHU36dmBKu4SKzK4= zcA)P!18%THF@fN0fB;tgU6+7UaV@a;CCMo-DL#8YVuS@PrQn!ZG19EvK%3%%^6b&; zxh$-+wNTV7W=sr?_$Ng%RWfeVvyhBR0yNB!R)bOtkeH#=qPNH&YHyrNE4q0;3$Q^a zrDa8YxYWyd)U+K-kxM;8fkm%Q+d+B@%Q=(U`!E12h|S$@Tnmqb9TD`~0XM>{DZI{& zn=L%X-8@)n9-i}(Hxj)KA`Gg?ypA*BLWmUd`$E8jugtiL0~a*Qs|Cam*6$sxfiC00 z4E|6&rlcwZlS58=h)*UoZ=?JzF$KX3iY`*2l@Aa}HiwBay}8YXv!3?4amzDP{%40`H*H7UI1pR>vqKTB2$;qbrQz&D`l6V&k}W@fD1P)< zO~I(F_q{gGnV{^|-qJ#tQKtb^RjfYAsqr0!spN~2R0fsn=msq}ezpc~^>7}CgIvukqCwqlK!kykKK%^JLc4H5 zXrYmo9~%r5qx_pe3HB%|R|$~aYz8(1FOdO@q?-o^7oQVV<&|i$nizm-vlB5~wyC`> z6nwtrMQ^m&<$N>fq&MP5E%5<>b#|* zpKTpihLb;u6Tu@(YItOdB84P|l1Pr;`i&yANM zjHv3(fP+5m8P084b0)Pn_Y%c3E_b_eC8>iQp=1JHmGV)MdlTD-3DkjDf5V#!df=E6)mnX7&6Sx+LZkKzD)yl*spxdf zVWM;&+IGk(Me00N)*Szqi`|CD(s$6`hqeP^+_{Bx;Qe95uleBeHP@bI*9V!Q_2we2 zGa+NqIbrkO zCLFW(M!FS%blvLsp7!^}z0Yfrs#)mYSIx=yzCh>w&3V()mRyHVdpxC~1vs+G>-jBj zrN)ax-iRAinWNv8ZcNap4bsYYVOdo48jG;!nDrTL8_(^AMghHJ0`7y&d<9#0|Zz!5?|T@ zZ-y{U5PIf~DyyW|%jbZ2~(Brh~LP7tu zsy1`9o^^oaO=@pBH{=ngx8Ql<+l1)wMuO)xN&PDpJKlFY&GB77f#7=qfV87S+gsxL z4?sx&7OyKZAsM48ZW`fwIDH5*-PR5jpQB8u)4@1pK$UGBSNPy@rU)=F4=G7yaB3+= ze3_x6KeH?8GXEz(X0RHy7#28v@uA#ieHP$}NF~As-V4f@;4Z;0Mg;4&!bkNK8$MlKcT8FZohMJ70V7U35?@-`_NgF-AWaZ@9!FzEuie=UYzAH+12|e! zM^ro+Jyp?_R_Zu&bY|I@5n$YTl0(~ZxI#1H<^r3^!R3g60)5;?T>k;6Sc1pq&@|aT za)j%{Qy+0sd!bq;{gxK}Z0oq04-_kc;>eSLqs|qI8rlo{8H`{mxx|I_CGmE7S@nBccc7K%asqRw;M+dKI92B~DhKD5nT40`4;QPUhvgIG`) zY#czg@Vtw{5T#hb~)b+I_ZtL=`8V5k+g>ct|DL(Evs0O z$+C4%XKUf2jtph;ABFqf*cT8FZohMJ70Rk)&-SqyzUJD&rdNqj`m2 ze;V=7Q;qK;SW@?)y{@0ZDNIZZnW10ZFKtg{YiZ?D&ro2|t2YA-~m>6lQdXxZ4;?Eqd@)6$EA8arNUeU^WD1 zuW=C4%R*2m5QS2>v;zWeip!1GOrB?Q1iz8F<+Y zSft-PIJlmks4qVS7ORN?m^M2R!)2S=+d{$TTe)QQSJa$u2A%Xq+|)~a1ds(%+QR`? zB{GSYRjkNl*}A8*wQ$k$_|nR@ z&%vvi1x*lo=8bCJ#!O>xpC^7h|3gF*zVz+J`w^2v!tttpe7F!Sh zg@BF7DsIj-)>+ooc;zSKVc?CW1Ev;IJ{EC5Zp0&4NFUx+1wn7Z3$9+= zB406^wk~Q5FAMWJfhbI(B>@1KHb_0#6tSl+LFr(@94dYaBn!h+4bV(9M%|$g@JigF zCF;j7Eue#O6&L?lsE8?MD9gg@R8v7OGdKmA;=97O3Np&SJ1Cth1vl(2Lc;#p9IU<< z<$k(^T}go@=KZ$u`gX8${{LYQ74r5Q4&$4!WhlV?mce@Ismn%MLrRhwyj2AO%*6RV zj>~*cMILga5(r>Y(YM2m^Z)M?5VY$n?zD`z18r-MV1beJJ5?7Q6hEw8XpBay7obTs zarbV$lYj?*sl7u>P*1N0u&zSlVjBG_Vuc9-Gc~WKp+vbVsm?&Wrmaxw!qkiJClzFr ze|J!tDvQ|PO#Qd1adEx}S^FWla8ljI>lzKd;a`695F0UB(8qARX(jypD*#<$)PppZZx&(_7P*u^JMnMKMA?T4MsSHAb%S+o=490yWLVe9{8RTU=lTZ&g81%Az+~?3gc*=FJsqdR-u>6No~oNZO-M z008FAm1@w&`&mc4n62W6^2-cG>)@rTDVX*SQgeqE4X5wrp+vwdEc$WDhnT5(rQy5x zedtjJT?j3_Kp-u59E!Il|L&kPRyy3i-wbR9UJwHYx#A(sji|e&hQ^C~R0|k9?mtbp z4pN%oe%4qj9eVIKxXs&)Lqvyc^Hp5t3)e+6;zlJ9P^2Ph4-4#?001_a7emYA+avV3OcRLP`g-7EDUS2>`t6cC$BiQw}Wkw zsfb34oq@}d4MoyxN8EIlczG;J%WwGVrTwP3;Rq>SH+h-lX``~O<664IOaz!24=Jh6Kq4@5w}bey$2$%Kvqk=5#@%6Xv*9IP zr|J>o-EIap1J9Fz`tNu+u6j58ON*oNvRoe2AG_)QagkHZyrY%;Nfazcbp_Gtjo2D2 zcXiyHuh>o7^si7lRn`dv3=7eUfN4BYeu^bJJh9mo<*=1(4+oQ)pIrM*BMdYd&W|NL zz{4$T2M2{ptcR`9fT{|Ki{aFN7f1+tWJxN6Vd|wq;(sARr+6FW-yf8wNUfDv(tyRrN=EZGQn<7O0&a@Se_(Ty7qeCTP<{zD{QbeLrqj(=e0=xsYm$Kd|%{vqxvaI;zD&}E>B}_ z0E?`+p1WJZHC`Ml3m8l|@G0OlI}r>>Uml0@Hb=S&UPZ*svWm-m;ksx>+#vlN4TrYB zmJe?a3+$SJML?)o(M{7(XKQLS*6tub)xgWbnCpirydxdC_EJ??^}7vVU4?~L!y?So z`1WHc>8hkU1LfSmbwT`Po}v8MV1vS6qx`#rl1Ck>B#iyK8Q2WGNCq6TZXO(5{!Wx- zXtP*NEDRen0*pI(#i_j=Tu?!{6VYg~Gr{QmHR7hT#LEIH?dZ$1Q^8r0J!K9fovjp=bKY=B$+o}Hp%^~s6I&&lNtd(#V=fd5blr~ye$kk z^8DcM72UWF9%q{oH!6Vu*N7Z~s6-&0HnQnFFxXS$tOO7Awor|#$exp4z40})wCu6= zmV?4(&^44>^y(@cq+l`6O_&+zvjT!ivnr|1U;Y3>kbr6}3InCLiXsaU5;z+Ns zoOGKrr^T7&1z0qjV2kRlbdC#p@KzNBC65vvDz6Xq^6@K>=FJuAQI(A5?W7`U2Zy%v zfY4rP#p63l#vSouwu&FhFJp{W11}7M&{{CwJ?WTXKMy>2l=T+ZT(SA zy?K|KJG3lgG=Oy#761*4FjG6xWw>ClDyh!k6r_Wdw4)$-Jav%l$?dhrgcZ;BW^lN zyey;Aa-pmVxG65bG`z{nNG0Mms-oacT-w$^bmrlpXvyQ&!cqcyPJV%D>4)S+aL=S2 zl~nU35g57KLHtA7!@#T#V(DB5@nU*%)V=W35D{~CHUpc1XUTv%B;%@wBfV2OH)l?k z%Y&TqVcDq<*X&_W;YXu)H0__6;*c#`y%Af}jhpioyJ;)OcbXeXUmsk0uoVH*c%t0D zv^|{vU%1pXYK}AOc@FDipP{xWnd9t(bO~38`r$abkzB~44YNO_fSYBTP=?C z3cT#o^mwp!flAKr24|Ma>=esy8C7|!3W6DrQ5{H7hkDGHQ=8zO&J{9xT_EV3PD~OgZ2+(E>c?Fi+B!JTn?5v4 zy22Y~+-c1~FHlOm4{c{`ZQW+zbunO2u70??TWH`)Bwl=cTEJBMjiWJx)vU2e`Q@R# zO;Qv)ibF*FS`LpX2UF&Y`$aS2234BEJ&N+LP4!0**)kO#lP=7rSB$$KlLQs@?4yU;&G%`tlj+AScY>lUX6*xncSKCeZ(cAL6Ynb9Z5m zuN`sIS>k1mO3TLq-f=eJyIz<^#)@oGxyGU=(AkQYmdnb|C_ONd8Fcg$$cce(rDjD- z9=F0)cex-rXjHa!TuXPDiQt||TSMn3Wu1XUVB~HG@rBysFfglwSUT51yjT!?x3Qwv z?ra7&122#PbwtHguRJ|kmF2XT#Uj$2w$+DgwpdVBF^+f1;<3N9T}BNCw;tMl-!GI4 z0?x(75*?n{>@Gbe+rz>1AtMYlIXvYvK_6I$+A*qyYMHdrfT{|Ki>Fs}oLSGSWw>DA z7A2_+PGQD3&2#vr?I&l_b=fFQFH3=_fMcM*EKF~A5kfa;icBhROp>U^evQ<#lNsH#oDr0E}icaOmFB=7L^*IC!O==Wc#Q1qq`=+rnqu735Ks zJR;4#jl|`lZJ`@?#f#ZKa)dDmLTkaaPe^L6$7P&pp=khB6)NuH(6#`c zbU~1UW=Sf82~bvD(3N%{+GcKcZ!_@P889F~Kiu6d#PE}?cyW_r0aNWaj>ZgDv&JUn zm;MQwda~azxGgppBI3UJ(`4gd%6xIZXhz(iN>jK;(LS^djFhw#4E4L*1d3P9xrJ9f zjl2+MYJ6cmZ`7xmMFw*$XkBQ(%rlf98*EVcYm`4Hq>EJm=$KIT&yM*hP9bUiPG)l6{q%guto*pPDG={&IF@)Wl)iH+7UOMC0-Ut zX}M6UrTvz;`CFe`yo?m$&>2;6(+DF2`UrT4AvG&nFj~lB&@_N5+d8f#3d}@+SVW^; zr(+m&|4BIvgRZq(^y^u+>Z3FOeL5)mP-x*gec%9lImykwh2Zwv526$P)| zERwL^_!?ST_V|HB(ZaQ-uxz@95{n*&u#W5BzVXVKFf;H0*oq%vd7LX+QUYBcM(F1Z+bTJ);%byQC~HS{8bvd%H8fl8R*N7Z^3h#5b=>OqMx zjTOK{Q~#4N%jB`QD=f#|#>;TRsV(^7B8u8Lj*$z^8}^lVT|uJ~^T&Zb2l1Y(k=A34IvK&q(@CZuL*5mz_|0sY2O+|O3U z1&d*GlP(DEnY0R;B?&ZmECv}dJB`#TEk8D>AWi-ptnA5AmnsdtI+3^N;SAV^BW}P~ z&H&!s4m5C0vA6KjcyV1YfWc}qT69hX6Qt1-)D;+c$?C^tzJ<@YE6DV+u&tN)D3rpb zJq&E?L?E0uj%v`x`&mc4nC&A+*dQ{h;n!_ZEH!s%f!nyzfDWdp!r)f3C}wJ2!Ft~G zp;?kZlgBw))LPg`J9=_+JRKYuBztn7b{t{_-*0=!6(e`HP;SWpJ;}< za@4N4sei!ah4KTe(selw@d=s)fVlDDY6ukhh-)Q&?${IS~wHt@{( zLOyRs+^8SJ1rYi9p0uMM4bB5X%Ze_i%xf>!cpb=v##7iplR;>HGZ#Rl<_;~(7!6>} zxr%!s9?V35@uhm!S(Q|0Fhj~Zi7)No7n>J)G(qTj9LmbjDRk=X#i!Jn*mJy}b+ng& zdLO6+r@JxX4q+BU5WJ0nUA<$nkoqQf9fWmU=F1Mu`i)KEY;0gxClG~=s7pYG0#dh; zO{Z+N&Usm2(fbi2tiICABgXBXkBZu*O)7(Q=1l`=VP9{!U6L9o^GH|Y3o9B8IyLkn zgR;&6o);Uagb9ADRL=r2WBz$$vx;D}0(fX1a-_$Sf!$PBGE7kQf_ds`z@aoTe2t+xW+r{13(cnB*qy3c~-O^WhX z6$A`E{4EgcxPFI$i-scTwFW|Z^%DqI4yMwM2)HROH(ED&FUq((Wa5INL?23~47 z3#QxJ5jT(906K^*b^UBrTny)N82HuWD^h}XJByM81ZE7`#exu&%A3ba`#}h%g770{ z#A~b&Vz*vPd&n%d}Yw5?LR?D?rAf=6@B#J zu(ts5DIi`PDg&6sqH`jcAmx=AK~x0+N*2A*V#j<>#LZ6;dRe&D2}Ge3F707pTN41` zym3_DG7ZIx*(!c0w}d~@ftP_P*N@CJw*+cObpqU*Xg~+Ieq8b)W)N6-oof2foICL#2!h*_a6!N!mwU*?HH=3o1wqW=g}3h zMyE$y24>UeEtNQPlJmRKnPqKe=sxKsvEoe?)GfdC=XgKsXs`Tum*qilK&Sy)%HtHvg5W)C zZwY3-2A7r2;n1t&GGBJ+(CgSF%*F;*pplyyFK$Hea&SqBWGINc4L92OhV7h}1s1&@ zF~Vx&n@6lud(DCAmZpUbpoImhs97|07qe=79o5rL4ZX;qtaFTNpu#NhcXbe#^d>d_ z)uvt^S(60eHFs^et*(b0>9J%vPermJ>)2KQJq9r=GOLp6-MpbtdDj(0t9@we=Ys`d zH9uC56=|Jy1WksM)3P|3H5g543)Kud>h_^6DEgWn+Ab%+HrNb&T^ZnFiQN~UdQ{-4 zZB8+uy&S#j{aJeQHec1zoo<~@-lWv~C0#*q$|EDoCE8AxdKvg!|eIYzAH^1EU9ry`>&LJH)G5 zCl-s&iC~5{Du}8en8~6yTI`rFF=rhICA};Js4_>(3*>?T0L&Xl^{EFIti_AjDt;)p zgg?=Nmw_pUvt+udy`*IsK?6E?^y88bF>9Wf%YdVYDoYY*@^u2z!baLrkS2cy$)4P& zja{(5y8vBg}Wi#&l+yDk6XMfAn9H6(^fG{fjXeUJLi)}njc7xh6ADuI}M

R zYkFw=<#6PmkK#4|+VnNoo@U?&nW1WP!BsRrwNJbqw3nk#y+2D&-sY=1TF*LpGltY8 zh^io9@ZoR6oxkw#m!g<&(k@;N^z`Z{5Udyp1Z7^b`f*t$kmikpnqC%yI)NyZiljXZZ0kfIoHvf@Tjr8@FyA(wu>nJq}I;`l;WkeoBR5Z{2CUxCxN$ssqSqW3rAR2;S1b8t;g9gJfZlw-+`Dv>tornE; z%8~0kvDQIwbkDU;21~zzg1^&N0{RkLvip3KC*99C#V5<`HP;SOKg0~h+uZ1ocxsCr z>OsRq)rOGYg;_Yp2T$`=9o+};QH=Ru8gErWFy`82!=1nCxUz{W43k;^)j-TNRh5k9 z7szP(5!!Hrv~5%{k-`OvPGcxT`ZswoTX+c?<@b!Rs-_~)#dLG+h1V6r zf{*-ZsUBZLv{?s4DCkiJ3^{|0l=|qP)|>W&5X{@gOAksEHdZixiOq8Al7SChosod- zh~VqrvSfC?{xy#(T+YyuV@+%JGExRRt(STZYwLRvm<$jftBmY zqD2_oV}t{qvfU43lZ(`R9olMZ$9=o8!>d8*tmu_?1bHL^zB&1)sJwhNAc7U`y#7b5 z9d=BADVwRkhpZ6rU!2(OspG!Pc$*3m(tijyj>~*$w_>KfLHbA_Lr6uN2CTwS7r1jm z+o)MFlI^b^R;E9!UD~(;qYh{?oc|??QSF1ai20OSKvRXp#c=*haKy~aD^V}$rX+!8 zAD3W7DJ}KwDaPV@tB-{ z06d(6&qj4R#=EH?8S}Heeo257i)WSZsRUfMs=UStB&(23Dc8z9F)#VQRD6+#Jlu#PgZ$v=OdGLB^6ebEUwNg zZ+TqwNPDQ5ciM2IzQ-+tk3_)Zmf>`p{}cVn>^0t|f@Jlt^smDJnIKyNbG!X*P~sf$xSPWJep2{OxnI4E6}3A9`x2WbCBT9*AyEKbl{ zvZ=kkCc! zx&-q$WY zI4acwIjed=Q$^Fopl~pg2EDQ*lYz!uaEPz7y6qdLW0${INUfl=QX^TPuu{re$H!D< zIcGbsJ8l0_xEln2Ez~>%p+N3CJUs}Zp}sm z9*G-mpYYNe+y1B=Z9J8Vc$wjB9&dLb39Z_)jd7#JI9n5!{g6R#=M}+L%&w$v)K_58 zNlS%p_72>jNG_b)8LzAILT*Th3jF9!kAXS67miiFA+ZUHX3d4ga; zJax}_F&MNX>(`>>>mjjI%Xy*$)ptGrmMyF`JSEn*CZ~LFWvO zUq}_nE`J6Qgyhy$S+K6xs{{WVI#4g0@1P#f9QeMYS~--!6>U_faYPdd^ogi5tkJ@$4Q5-%~n9#E=EY0nTOd+N@_Degmo1GYN6bWcqnH1 zbFkEtKWB)pr|Ln7i(DPJI`BR_5RQ-&oBbJ?Q&~GMz9;{*hnUF+zcW$(FO6DnQ$ex{ zT)gD3eH=b}!&CFk(%s9fH-o=0BmZ_}_kW483z_xb#L6RmxnEMr_Hf0_^haw)GnQbY zbU?#jYWXg50Z;d=y^LzD67wnT08JIJ?qUKKGo@@h=k4#Z6Apnqu}`N5icE+ z@i8dR2Okr_)r&{Co8FyZm(Y*vUtCg3$p3g&uS77L3$Ewx zkszHHhYIUn02=x!;50iC3`oBphw(NQBq;88Lb{8WiOYP8cJu0?rF}PDcz=d)<~@gg}FFwk9t7;o)b-muM?y zQ<6ZlUn?x=T%x}pN2ZBC#zDIL8ALrfY2V$Fkqf(C{#SK?6YzgkRqw4BhlKES;0hTY zNwo8tttPWY^F%ODn*h$NuzbGl7dz%l%q27HjY%M3NZ~>c59D^$g>XYy5!$vfhuUWA zCh`FJDT0o981ud9DsQQI(3Z+-%yxin6&_w)7hz`R)i{Qcu1ZR}HUr~4z6}ry^ooAQ!nhaCP7#b|4%fr!7ZRT=j7N#QRloj#lv6omq-mIXpP`EGdV! zA%<$bO$8~>(}%WxRTXu!-pmed|6g1vxjvfX#v_M37x$ZF;2-glY!6r5O@F$v;@C;F z5p_V@9@?hb%cvr57{PV2?;^3;wsB{No@kKFjF*(u_R&d#OPXe8h|#}@mFe3of5(h5 zx0An@-OGVg1T@ihd*P_^S)#qpb(mCXj`l$icQv1j04pu<18!Ylo~2u%UO`9|yIzk%AQiGRutK8FgOg71Lz9D|%mOiE{-SOMrLzJ?BI83c z9_dw0Wez=#EnKgq+B~> zZI|sUN7xJ}r%#G}&*7CKE~IO6qk5dJiOWN5X;FJ2TKGo z6(lA1I{~I9F7t(YO+3`}auBo$WT6x;RQ8YoE=UA-YvQSX#*5jS{!s1+e}aLR8P2NH z5kqPov}G3|&|sXciOYU?_?ht~+KSnfB+%^F3JW@C=yhm&qG^}O)q#)L0WL!O=;lD0Wu`B-k1cE zuM{ry@IY)E;2>QSR)lBGLtb5tvnm*6l?>24Z1@DKQ<9q7wulQnC!_;xvlWoGixCTE z=3)GjlG+RqVUj+?!BB2SJQTD1Iaq>_>@_6osnyBkx~>jf9eD2@2o4#BBVk#%vF57nxS7@50+` z+qknsPk;Cf@X(}fp?4Wbf=ep#zlfD)F)DhE><_D6pB+DMp581&3DQ=O?Rj2!gL@lS^F>o(H6dS%T)oB#B&&NdC7m7GJ`y)VBK=3aG~2d6Dn}I# zDKCk5nc?IKXL7y+K`7$t8xr~vxluUI*2G0W_~(VCL9Z;yjJm!NnQG4IgKB%YbS~ zj{!65jY%MRO5s8e54<)J2kDxyBDC!xudc>f6^yb<2525OsHT3bbhRT}ae?QAbbxKP z0@8LdV!_PJtCy72W^igH2&hgdHzOX3S^gX>_2fP+x}K^BAue)t;OfBp>_9j|PE3ya zxa#SL-+kiFdcEDDZHS?enmHV-PPR_}(so~3vY7S8B#=zAX#Y#wWV*k;iHSeFuzM=m z9A|%LWML~DXtak6fmQS9ypknE_yl#aP7Q8 zuW2=ATIfv%I-|#6Me3o%EQoh)5KKog<4kq%YueRW(TJyRUyCTPU^#!POs8z;b*Jh0 zv4Bq05M91ac$Vk$^V?so!A zOE$436Uf3O^6>>Kei<0xf<$n)CZ6hNyqK-&59N;VCm48{;jB6xF-+|o zgcIA)2- zKz?ei>AbqtaJ;g?3`;2@PKc*GfHNyBpKtrcj`=Dm(Fe?|HztAPDTNC?Jn-5Eh!n~R zVMS=rLtd=W0ex1*BO@#s&_}>iol0vDh@LN)>4brqc^DH7ZbO0wc_``Q zAZRlXDU@RpAQsBah=*d9KL<-axlfC(NChAlxjOKw4(L1SRfrePyaV9~St&<-Tyv_^ zqq#RU&U#&kwp<^Fe;#?;(QNQd%>3bn-BTIK!xh`tj4;ryL)+y5T!*$@d-z7+9L8c{ zHb~Jis589U4UrQ)84(O=C{jnI2iGQ$g`LR3wn;>U&`k(7n^9ZRKj#&IM(?&i3gU~Q z_7#pp0yI~Y+|xBbBSY=-t!9bqhj3Qd0R~vKaj{$UbQiOBd|y(MK$i^8Z6+i!=>$JG zxT9PpGcn^#6?ObJv)H9qWkb4cFGN6E9P5W>iuIC#i;;$HmoIvKN##_RU9nBC?HEb0 zsYnMjO@{DY>B(gEe%&p=k;Bz!x1uTHg4_4QH+-~Xg#gBsUU%Pc3~V>^Ie7% z<*YaI&(zSuWDe2xAL+cpq&A8G`Sdaa_+h z3QAGW;4!aW=#7IZqaBBcgw77zABlS$0f8Rz^6-)Uwd}Z5{>%s?1DzF%+Mz-irZZ$Z zK-2R!ZXgECMDWUzOa@hDx)mFs4)ljn2gv0?>zRwbk90vU)mZUEIQ z#!-p3@qWdK7qflk2%Bn#4~Ky4s$T(7w(BlU9Hj!=2 zWFT?*BgKcjSmP^4_=XfvP2Fk!*6kRyWt+JLl-f~+iQD}o4ubnOPGvBLW=ST4%5l!# zp%Oa##b%d32TMJxQI}MJo=LmC(2Y&mJGk0(%3H5PABku7Jlr8n14M;WrPz?1osQSbo=I5i$8kUTxyHw{oI*pEn1VM+g#mlUtwZGRNxkr5U&cn*M0*4~=j^li~a(83=f~m)Zwy5%VeS0NW}g zt_&yNLokyDy|Sb>gK6fCLgHVCwoO~|?--5b-Q9XFeeW){H&5s@*N*1?{^m`N0Wihz zDDw=7=aoLSI&3mvl`0C~#QKjrn~ zPS3@C&TE(L8;@|<#eW0+8+&g?Di6;b5pT zMN!eNJu4MY=Ia2pB!WyYfoT)S7*e><;|Az95eMm#NL(J@J>UiS zUKmJta{ER`!3P}R)Oegg^7L@mJ;89(r%}&240|7-e8kHW5MHw?7=;c4M$p=7qG6Si zgP%~SbljjH5!vbz&}7@j4TON12rw`&DXGmsA~5ohL428^aoY#8P5xrWxt-iXddb(R zdc^pmR|l>Ryw48I9vr&-oyeO@u6d~PL$wFUY|%LpLsuLV#8i-=WYL=}cJ(9TL}Uk> zS(S{Y3uGW{yJpL?m+BScs6^X%zhcCT*_!@P{>%uQYN}56wO4If<(qY$7UOJ9T=v7k zubo!}TQX>bfo4ep&3-Mxic(rCbhCHRO&NozC--S;bs~eyhuO+d7w>yve z?vEtgdCB?RaRW?y+9u#MI}uEfu3y@&o7IivD@Rxc!Je_^lw>s9L)&$>qP2jg3KO^c zrK&l!71Skt?9g@zCCWP(p?}(;tt7Ojx*fufgPR!Ht~vnBHYRKQq;+aywl)0*Np~9J z)yCC)6?DM?PQAtnBm@tbT?1gYBtf-EUj+*e*{XNjpRS4pl&S;`-kOgV%Gy2LDwP6F zxDL=%fw-=?qyOWY9WK?##r{4-T9Bp^m6pTE$A0jOx*BIqGBk zxpp2`uYSg+`HXuIl8rIV4A8U30Oz7B1x7Ef7u(_DwPrbWM- z`*(Qjx%9omiWo_b4KC|Jv?kT`HLC9#7=G@z2u7%K?E1QI&gL1 z<8=V*ft?a59}$(;j1}Zrm5infWFXeK z0aULTMpU&S*_ycQhl5``uL!ne&>#cNk_4K4 zT!Iy)ylI4TGh%{t`7?-ma-XK#m=hViQ zaDY><*_P)xJYaSWSVW^LkUIwBrb@#hTlH@H(^X;I$G3t8Z_P&wW$hjim1+!HNjpGO z1>(BmqH|M5x*gvNc+Li>W+j;n=0KIkObq?dw8(F-HEAxLh`%SFvJ3{&>`W2No&2?yN zy5!CMd%S(*Df1rl|B;+NbM2*X{zuw(*0q-m-tJGv$_H99ILb&kado5hh*wMk7rbUw)O{0| zj(SMiYND`8$t4@FwL=A$q?}*62^?qJ#tj5Q@*;R<(zehMd6^{VE{doAJA8{xes|ATpb=GxJ^pD{zRE;t)fm%kI^$VAPqqpE|38(vj$MTVjPud8}C<)crjbkAIhH@ z;WH11fb6Qatn$q|Pm6K3CNBHo;MdM8f-M;|!a#HK2sHb(1S?8usnE%jTXtacsg>cn zDo7{RxM*E+&qmBG;ak-lHU4%(vWbUZ=e= zr<3V9A%zQ_G+-04s3mT7e0Rc6yjbHaNBD*W&{pmApmrUE6Iok8Q-z7!9eVz+`=#w~ zv1eVCRUd!#`NrY7{a>Q`?Ra2wV7&tOM}H3)&|};Bi_5nF57oI;maks^MWyjJ6(qBN zitRY=!Fomjz-9a90^_*g75KU00A%xOVdo9|WLh zPq~3?PiDPwaOGq1IEu(ak;u3KmBEay-nwCCGm>}TvDE#kk?NL?fNGh?O|HgOnyz-~ z0l$u^jA!fs&{WZMv5E<^0OVJeWHOlL-pEUQcqWa9dYONKQ6gGFUnR}r?!v{J^mLC_ zA^W815_csbl2cdbRkl1S_qb8=k)#br$~$fuD)6*})g+^Ob^S9bLwZ4K;@wt|4350J z@R1qE)qIoj_L}v^B#>}KGbhjFWX)pEhjdV};OfrJ3jwgHQ1RHf%ixuk7!zoaGG zBW*PDCF#woSb~XC(8_R@K}c9u=0QOP8 zmDB?(s5W_&&6v*1(-M0h2LbjD09P~G&l%lC8Sl1&48YB$16~_9KzfqQdgI~GXu3HU zRs85tj2vur^8~?yAa1mH!YdHC?T^Zz8DUdR{H((;hX*UPQmN5|bCi#>HF4PwX;C}A z1Y0oyN(0T3x=~+&K_@L0dQ5`Y{Kf3R=hXsdtq|lQR|l>Re8>)rpIpb`N;UpeQCwHy zrB4U5WSNx>%L(0A!DL-!Y7)d$kT7fzqtx8CMaON19p!<#akeHd`k|W}2wZ{jL|ZYN zk^}^147q}IPzs$rxe4asUb6&_+ z{-s46UzZ(cRh&WvnhfU`aT4%!FSQTaBIZ-t0k&00Tp3P0&(i}wv*s_$OvBWQT}f>Q zwda(VnHjKUNSl$&?(*k^6oeF_`x{SnT)Z1xkujcZ?rPI1-+A#ZCfijHU%a2po@WYN zDFh*kjCWf>a&hS;UmmoLtNB8`Ca$Q}Yn(u`3dJ-|VY%StagRhqyQG|)$0J@2nDlP@ z(^audfl8pkTl3LES$lv}r6SCX=>Q!p+qk|+(f@ekia;8q3dmQah2CYbLZZ%0j3{q| z_+qJPx*`}3N@rDU(`x|i?DXhV>u#-~-SnWOcJ0a7$+y-fuPLPXm`+mNic z*Q__FQloVTml1l{fUu333=o&ccMo~p5<Bz4p-d zB_*}}^7Gs)4Q8gy(Brs4+4k*Dmo`Wg3qoW&D|+pjQ%&E)EG=}YS(?3p(!BxZ8OZ12 zKIgT|=Z#0$@8Z9K{tZg{?G4iW0Z42OkX0bkBX6b7%M%9co`V4W1h|^fe$D{tzxmyz zc()Z~0Pc4j@Y=Wm(vxJ?8xMa*JB}>+H)vLm8vxHW(V6ndH0-i%`x6-RnGrVC@O#n( z>eEYAd)1btSzeCXakeHd`ynlA$CqF$CO~PRSyI=>6&Q56r8-07W@H@1<}YTP+u6-p z0qY`H2d)l$$PSq29#=^BNHv|8T_*z2%*sZy6TxI%Jq`zJc$*56lFyLc+61ytDiS*R@(ciL;;BaZyk9Zm#cWM~D0eFqtAkhf1Y)P7gVa1|i-oiIfr4?i zCNBHo;b+E|Xe(w@l0dUxD=g@op|dAP0g z?_w2>;_yub{_vTV)3);P5i=a`aa9qo5%tCDk0XW%*}xnQqJpGyT)f6{nXf*Q^{zq?I+|zZAIA}BZGy;jwE1&FW(43~hqeda$C&u+YS;Loz!j-_ z0Vcq@EGYS=7s1QJmJ15*SA>Hr>935bbKvNW^dRr5pyQGO8oafNLG1xRm1+r{lpUah zOB>f0sjgpQ){ZZHH>8E$Wv~G&YBMpSunpoHvv}i*U^pm!mBl!|2EeXPk7zt&ZdA1A zsZl&Wt?JAOFlT@i4O(wgK>`rb_Rw}7t=7zX^R*ahwC>iV_75*22qwssukF7|RRFJ_$E z$>5$|^2LcDf{R`qxH|ChI?!$|0t?WmHbqmW^YS!p_h-j&$3WvHqdP97CPCT?G6wfM z4v=l!0O?86ZG6TFBs335q5Lw?L4ibYwX{pd-62#^&X4MHuM6^~2a*?Y8R|h_12WAfr zSE})+isHHouWp?PfH5l@mJ_!^baTE8yu~Y9F*k%%`*iY^$)-h$9WN_Rw}3rBUokYBOkDXE!o4 z|MWv!Kg+O@>rM%q8NS72yDB)?477V52ph=mMi8Q+^^VgeU#^h!s;p19@oM8TUoypN z^6H9QjmHTjt58fOr+5c14@F5tp&%X-PEMqM&dULd-fe#rq*URDp*tba;H@L3BhA_a zoQn#*>Hu3o2k4-070#a&PklP>MoD{~8pZ9A*d2zgnTK>ufE0~dZ&N`65z+q87S*pK&wBHn1fxdb27X8sWB@y3<|l5?9|2lF@*^_R#hvCAIwugQR;AW~R*0 z&K(nN-k1H_f za!YlF#?8n$h|OQj+P9sx0@fLVqRyB;ZR4Ky{87j7qX19(KNt5ouU(37J;I!PyF^~6 ze}j_z>#}_K6iB3Y0a#BwMbCIKTf`DH%3XmMdAXat!pjV2)#>OcHMeci zahqXBd7y5bt%-|%=%xk&S71ERR?Ma(0f8Aqt{@$hLT68If_XUDLCNCI3dR??I&gL1 zBX+!taa`t`akekB-k1au zP8RKdX}b-X4L;(bZLEFJmTkRX#KO!+bFwPKDbMxzfY0oEI<);G&QNR_(q<&H_HAJE z=Y*8Go!apOzqIwqe|s@Y*%JOr7pOc0ct5p!9=^%wHDClGs#@<#D*P~XCj=V2b;NX} zS$lwUQK45IU@PbV9rSHnU!;mDX3hA*s@Tq7Tj)&&Rh@H0J2RtY8^jmiE`K{H*{riF z&gnG(c6EBB))VeVd3&B3#pBbe&Wr$a21wDM^)?kG01@pEZRg=C&8#4lbj? zxB(UVoJHLF_-<}Yjm=ilvvO%89aqc^%C?%i(_QTncLht`YY%M+yJBuo&PwX~wE}|< zGgDhT4ss_{7eo-EMQ25?i@7>*b>IVbpxIn-o5QW$sfq%v@T~U~U~AzZ815Koykvl+ zM`9l4Z3S7#{f>i88#h3Dl3=f*UZzS$I}V>9{|%aW*(|$!!z~l;)KsGVD{i}rJ8W6D6XsUI_x?jFlJ?g8Kmn_vaTM7 z31TWpD145DbQdoZm-#Aau^Ya6Na^JuK>Cap#ZtIX`xONec_=Q^f5?m3n*LCZDgugG z6L=v5^;y&om0JTBZ3pP#HIB;(BWCURDjHCRWDL#8BhWCb3mw8Gp@T-~?8)8bk06SW zfI2InU*zh*)q#)L0f!Z0b})IWrte}Ej*!`JBJhXLtem!$hmV-ycu$O%)R(pAk0XW% z+0q;iUWc}&f9L~_3)A}Tvf_tE*c?87DWMcR-OGWs85c2K(hjh#!cL>V2pG(+LtAM` z*$#QRT~ggZU=vl|V#x<84}WY1+PxNpFqsfRi0almPM3VSLei_UKHbKvjmvz=6syUr zD{?g+Cy=Z{F_oO+-LL@)1^Xf4(>x)TBo-a2AB(yTqexv0>q z4zLw;fDZaLt}jx>6tiZ0VO4DBuPyW@gR0IsqMe!1vJK*kZ8AFZ72_y`(Iw;<- z0Scvt9p@oWT zDWD&a#v`%!e*OEsC-{c>edgNH)}Jv$J!0WerVn>KwYhAphPw0OV+PZ7!}vHv#NDlf4Lq4|fP776y+M_}@|MDd9s$a>0V1tD2P`XcMHvP*y~t+k zVPfU-q3e+m4#1+1fG4@sY}$gJ!*fD9z&6_ex3-H>2r~ygVi67EA;BaFP}0Xk&}JY~ zC?`Z}6)GPa0_}K|xjJxl-~)C5>w;M!`ItIYk*C#WH3=~6%m^@N zu=qs-dYA5T}bk@qV` zyxJ#F^jOqhsaDWg*F9}a6>Z!=JeY~#l_i-B7;?o(e4&Sj^(KEYArRj!YtEDekVW9*2HB$ZtyeXOSBb(Mi^+8B+%^F3JW@EsnFRkHoN>8L_PV_RGolT z1_3-C>wLfAv;Miqv-J|thz*t5aWs1dj}+FV%B1n;UV<#HdcLQyq<9o6>m?2K#sMW9$>I4y8-Jd3*gXm zhg)QgWEB%;9%ipBsmUN9z=j|(%z|j_;IPRb>S(N`RV-2gRwOSu()%WO{_vUoA_9lJ zuS47N_I>F1m2aqrypE8Y&%?%-jIcR;v}de2;&o^%)8F%LX8Lv=+RDQ4{^-BoUrIkM zqt9GBn*1IPZL3H2eCTyc&~63d#~nCf^>Mgu&D0(05eX`6y*(6FrXu2I*}(>$45)@M z7!n}UYrO5vuJU{oI%&W|akSDnTL)3N7e2}0Uq}ckGpI=WKG%{{v3nxlZ%h3Q%QJQZB~;2!_JHV zb4FJjHuSwr$)%AhbvXuPmt>bq1X?5?|=yVY|s+%s91@ zTSzbY;zSU^hogUdfQ&!$!R2SJy-dwFoT2zWE5;cglJQ{DmsB>d_RJ}8p*2Th?cti3 zVJTV%0a7&jS`5Y8RFITBFT591`NNm+)I-}-%h(Mdvnm-aE|4f(=#wH6$LR=hnR<9n4HYd1YWuPVC%>nRK1FoX`b$QsEiCd@p{URhF;K|p{F zL1Ma8IXGF@bAGeJJ>p)Ff+PYaG8GZOmUFOyCj+V>42ERZ8&p|?NZ~@UV%tP&mtn{( zWJRvn_(C?XHe2zs^78a=Hf3{UbS%Jv4-)}Ta;dp(OGv8i)d9BI1^}38#N-|H7+*FH z;vw0U)Mg+NhENnDzOcG3~0M>_gg^ZbU`8$!d zr_E+H2{7!;2ry@K#WCJ(1sOmVJ@eg&6y@hpMw(e~9E=%F7f4a@abTAAQJ799Pp>0% zs)eA-w(XCnE858W6(e5l6DWEtYOho)=&b9WHl~U;ZXh1aMDWUzOa=_OVkExM!^3)$ zznC>|y8vI^#!zrER|l>Re3TC8LO4DoYWr ztV*;nVM#?oXNR^A#pR*xLtf1Gl_PA1^UR^`sig0;8fRM^{%6h_DF9D6_P?;S^yJwi7wqhV8 zVe1`W$Bjw7(-_CqeBrw$v)*85CkZ5wUNmmNI$+T{8hLUj7-Z|jG=P~^A$CjZpe@yS z+6Hp0eb9r-Xv}(w12|Jf+eJ)(XbLkAFI7OWAP%}&NhX5@lB(L78RZVTP5w|v zkqWRPxejf$7ZWZVA#1*gUe4wQe+O88ZTdxQ9R{vFwHED?UVk1ry({yKHC_BJeUqWV zskRJ^sF&10Ux&8KZvCM0XZ()w2UGm_5Bh&(_s?8A#_ea!P>)#M!(E@+`&opIVKi*F z0tX&b+{!p$S+jizB6UGLoOMTWh-em9^M&u4%z9(?-w8xE@!+X^xgm#pza!k-9Nnaq0QV8dv-K#Gcw1CvOFK4-Zygt<+x>9TG6k%hg};a zK+62Ztn$>2Dy``C@t8k8K+2!_*QTGj_A)hp$_yPJl3jtvYk~(NhHJ-MC9BUu+pfVb> zp5g$`RMB=3{g0+F^YBsy1PkJzo0ViTSRkpYofuK>pxfjRbu_LjP&TF#0943zXxp@7 zbQ93BZ=#g5!RydAzC-mxsT^1j+9I8s(#?^n!}Op1QuR8top$zpD0G&*k9-DMgn{g{ zh(2@e7~?mZq49yMmj~ND-0{@b=d}8CoF>|C1@y^|m=3P3nYwq#DhOa>Lanz~1-L^* z+(J2M;K_h$2!kP+^~UVKlW!J9c&KI#@WVJ($lkl6@z!8?Z?hFIE0;Dh$`B1gbS&VO zQ^-S*h^ZZ_kW|~N18lPm05H>tJ4y#V#`h&9wHZhR1e%Z>KRO~0eryP^pXJX9sh-E- z801tvw0@6_-zB9T*jc_>&*qYOb%gheCnfv$o8r&P>?JMWvOmch>jKO)B$vO5UoGyu z9JLtE@nWrJw4XCFF=kKDy3oyH=jTyInptlgj2TTANKx@|U>YzA)5%y-=u`_qm+dP@ zxE;=z#iI5~wMe(9bgdm{+r|yVL$M-wX41CM5qX>eL#`N!FZA%RZi573bc01t-KSMs zH~L-7)q$%6AFc!AL$d48wi?JA`0LR2Fo&l+;Y=M0cuEPq4sByo#wWwwp|hP@dB$~C zSz2EHQnn|55Bb*PVIDW4zUa@qc3zJAqhDMG_^s?b0=}sMxT}w-c7gtf2FAOsAY1*H z*pB0BzGAnev))MhNFZT|XxD&cJW>8j7-^f_FR5gE$abskkJkRs2m=kn`5$I5svVz{52^XI+KECuSuZvz=EpsRLZFbciXy@rfKZOH!xPdVBbBrw}TjQCwH)PqDM! zbYCdQw+H(MoQTWSHa*23xX=gY;Nd%~;uJK{LN>03%~#$c9<-&h8nNOTbsqY*iU4Wu ziI^lA%v|E*RnL+lnZNEzYBQMQ)S40>o=MRJ!MCZt^2nyH60m~KN{!O)BDE|&-IG<> z+ojgTU5Sh2)YWyt<4$xF#rco}enzquQhbHZ&B$L4^d+H>9{ygWSIDKYH$!_x32`LEC$J;8S zOfK^k!{3rT$!>``dv#uaO`iXV|9veG0dLMEiq|c_^5Z)0)+8g{lg%x?#488s{S8P3!Xfalmv z?X3#AO-UK23h)lo-18=`i<;bzG$HQszjT>-RfL<@9=bGb)UOScsBd60%{7gJ4D!!r zDX<_Upsva!lq;5A(?ynanD`AX~P*{ky^kjXu*gX#LkWs+9ncnSEgK1J2PbN-myd`BS?k*LnRz%wQlZ>&?DFS?R8Q_OVq~OpDu>JH>cG{3_t}AfwD6F2%u+Xb z6iu1V>o=NW?}Nv^haBK)M*BIVyQtPXz(uzihlse%@UVfW!|h2j>kZNm6^v9Ql;3Nb z22?I{mKFKAO|P-p2AEhmJ{t7^BZ-5s9nSPwM=z;)&=xhCaNG_C7?^C^xSl956Tvf+ zwuRP`Oa=_OVkExM!@;@@;)&4(p=bJZDHp8d_M%q@t`2;}4&dG0t&mv$WCdN87O3r> zDP}bpE;{N?oB^XNjtSCMkUhC%IRLeB1Ej~f2hOZF9x#li3#6#xmo&x5!4`>BE>H}J z_WlX4K)|*?Dt~5#O*KseJt7K4Tpc&)N5oM$&ep_5KlGc&c6_yQgzcFCk%4AOX4Dz7 zM^Xt|s$V5df)LCE;qEX)S}TonaaRYf4t%^0n7`xkMJjNI6LwEKugCtl$UZ={_>F6i zq}Kkwa`?j&=euy>2$?nicM;52?3PrJ=`~IuW5~Z9*)(7oPn4d|DWoroC6#RPFD=sg zou2_B@2Xg$i4th?w~OSdBH-CfYH!Cy5SBDpK*`p`#c+NTFflXZE9xaR(3=dFP@x zQu{F%RNQ9kp=i6PnWI?oSA_!3I1k0Fq^^%Mph}MTjv^0klRwnaxT-)|q(ao=2G$-? z1$6IJ>$@|j&6%Zu!>mh6(^KwF)_C8bs7|&-v^}(S@LiKxZ;-x5>kcmU-|)1DwhzVS z@!dmS91}@zR>dPDd_T(dz@e>&%bIk6ZMJuKN3#&wuejxLCIm7wUQ$wPj1_E7b-T-_Fd1}E}B0Q&jF79()n+*L%|D)?@T&I2CcYR0g0rXYpr+Ik1LRDBf@H_IM2@N~F6NoKu4`k{i! zqW`DgZ`zL_zOvo2tmqjpC-4ExtO~JPQU`52oaNCcj;8h?@-vhRl6aYH+qj;PFcSgB zm+BScpiIyaW|zSVin&=ng^A04NQ>I>okeNn0e1$P z&pVSr<2$>NmI^&4L2UkFRz34$2x~QqddaU2Tpjob9oQV{xl=WK5i55Ths~L#nBjPj ztBSykC=P9ZKVpayq&*z;ho{?j;R2RBbEwCBvC@k9mbw9N0iZHF4uHGU z5$f-FBsKAFD@c$Wg6q&WcBAc2H&&@(+snhEcn7uDkv<%xLMxTpkGY`YHd_xxJB@U1 zVx+}i6$&`xJQTB%04-)Sm`2{sYw_OX4|T+5GyJ3L{g{eT$+GBf6JD$TB>HiOD>&PsgH__iAd>GB^AN@q0>d}*!@ zTpf5#2mCphaLz1QIWY}jx`(?ywZ(K!9aZgCAd1iIc<8-kfD~=oAOT*wqc}vw&9a9L zJRNRNl38zlEB>K^fk?LIQ8R8pYn|p@)NY8^jZ%3qsH1=&a~3bH4cEC--AZh(}}ZQc)= zS#Lb78BG^RQSl1~2U{dkxj-=>+WRNG0s-6psQj4`HpAI8&?BNy#MNhr7}aOPi}&lAe`G7(pp7f{Kt3Kb#>tCz{l!< zEcfP+?2A<44kzrMc3zt^O9996-abIIxPEDSs!fNF|4SE+3)A|Yp8+E8#wuIyUd-X6 zJXHidyUS>{hqgQ9tPd7YvNds!kj=jdsF<~fwxV5A1HH*$jRmdDYxj$on;^6NhlA2p zDWHksNsO!+@Ax$vo!V|3)=NMm1XN}-P{6S=gdA!2Qf1P3+X@m6hd{m=3P6V^^CbiQ zm`r-Zg$*rC&JGAF8aCimTn{X6wN80S@#>9SCRJ2@WxSpdw30$l11*%bJ7|jvEmw~b z7gX40>!E17sF)~9{EOl>B>@^4RCOYy5kX>(IuCA>zmBYyhIe2BKq|nBOQ7&zKWQ6a)LR;%jceNvKfXkY6fNjt3@NS1Q3Sou@y|kn@ z1BVQjMB)p5@uBS>%ix#t>cG{3ch~`UIAj$-yNCO!H5kqg)b5C*7!SsFzhO4c^jx8lKSsUe)G8MBH3>*uc}__9U70#w3u?vgrDyZE8hGFJ~`q0s}lu&&Sh<-_m<{ zJu_)rXwBPXfCy`n;#V{DI2`QTARbcYFJ_$E$-t+Vd?6LNJwXxggyr)l9J4(H-YI*- za~AHL*~_h-i~F3{F8MbeVZV$22KqNB>BST8M~lY#)IB)xRyvh!U=rq`+N~zTMMvF< zGhlSZF+ti2vL{5d#ZCj#a1fB9S#LZnDi9F~oi(6x0my)8@6onLyaEB?HLF6S(4%Jr zt$PAhDS5aFg-XW_`Vnyyjkg+j%8Yf{vH~p@HV}&h(2RM_3}0=a0~15`ZN+nwy7pC<)ul*wLs+c0x3Um0#rwPEb zsnp(%ON}z+g9VgqO5L}10u^Si+G{ufp)z?M)J#@u8sHKkd;UE=SR2VGv z7;!;`ZMGf?WQ}AM6Ge%CQM{%kKqG^yPNXyMezDK-tb!V(;X^_!0<5D~p zuVDn(W_ySG$wOOMuL<f!4{>X0XPBR_3+P*B;vHv*=VZm(kUMT?hQmV4-&l-K83K zAVAtZ-1VtF^lOBUckNatiqGtL=)GhLQiu`SAOT*wqc}vw&9a9LJRNRNl38!C6$=$i z7F~z7sUvk;st%1=K1jsN^n5&x_$|E$D#mvl!$=+OTWHPOWMI6Re8>)9ed-<@SpM9Zq5_TD5AjiKmaOrj11V9443MJE z1ZgYCz7Wk8yTAYnN>R_udgEcrXu3d(YSw^9;>IXw&?8;}$#MOjRpDs3U;=c=z|nM3 zJ5+p*(r3VQfF@fLmlFnN(x7K1t%08Pt15JmKSWZi&?7)$g4q1UjB`7?Su0>&N zaRLd$0cg_zg@XNvcnU+|PI*bT>Wy5`9|b8@RDETTQH~=N8^x=9EbA!< zg>w{maBbQF(nq?inY7-VEmdQc9me$te~=Num=-uS4lwHmsasLf!>?RTA|ixtLUbJ} zv-OM;$wr*kzu$#!0RZ@Ctx z-Dw>#XPzw)~m>DgEF<1YR$s&p2g=aXmZ^ zG9nn$NpIxqJ6CyiyC4r`lZXf_#{tWYHnv*lybcskZwKf}724N93KRj&7lDqLqXj>Z zv~3BM!JO>@+bTRv7!)MkU>M>ujTT*wptf$vFfn*cV>seIJFdeoLHkh<4}f-sjKW9W zO8OMotR@c8tQo{B5>(lGdnl^DifFdjX}$`&;AXvPm-q}Ib5!UNfQxsW!|f@;ik|Ue zjUKUPRh&v?^Tf^=QuClK+ZbGsJWShc1EgISVdkKJV$vFDecrVhAi#!5e4(=KGeI0- zx*+sCj?Ri+ACLL{{ip1!*1!L3Uz_1)t{t8HDKm6)q{lUTHM(~yaawhwV0>EDngv>~ z7$8NH)?3aEdBhnlcwYFmAO^gV;CV07_=?4j_d}*Tz8fcyd~W~{IyxB|z9c#4b)a~9I}|mk;?xMsH)%*gM@+y|40(e# zZ3#)Uy?Vg53J-*mY*0Lywe#vVB{dm14Y}X~bkYfatK^}W(F-Do=bUk;Of9@JJ4<}%9A%m@Fh$rWb>Mz z*U84ikdFxmL9^emW^{+~kO)#2#8i-+b;mW1%YbS)j9G*MI(m5sP-P7wg$u>QfM3gF z<664_tS5n@XS|p#VhI}MzQBvT+|6F$<)BAf>rU&}1Z`WyWrkej7BIkk9GBaFF@wMt zFOinJ+3OgZB?$=37;*-erK1FX8>6sh1%uREy8pv zR`iS)YxKaKRndhV2{upc>>@P}+A@M{WZl!I%{IW;3@0D(4*Dl1t%26b(`JAG8zS+A z%C^r0afIoD(DOJtD|%hb)q$%6AFu;BS~Evf&FRs$syi*rapvsIvNI#VoWZ$QG%((6 z1sQ-xiC+s|z#0b6dy$@fo%QAh07mN%E@urm6&i8l2cT*R-gX}1Zgk2L) zbts&pz=LZy0|8QQjc~srK!_#*W@g7!&243eaXkRek^-k*0gfhtB<(~VwrwI1u8C|q z`6bEPT(l^j-VTac72>y~?Z%fI@I%0pGin!FtCD(k^?+>^9?qqUL7`v<|4N}IGj3N> zo52jFkq6vKC-|+BhhmbysC8~f`v9LvkctY-ktdHcaWblgE6#fD&MeKb>k68>@8pcP zsUVqs6I*}y%$h?z<|}qf>JFFn^cp9SYyx_{Ye2@^y*Rwn(+4=RJExed%QpOlsOgWb zVhdQK$)73yRlG(A*62Z{66-1T7SL27aWR}<1W3%x_=syYZ3 zY;bP@18l}|*$*)@^J);F7mcA=l0dUxJwhk(kO<|+1_yo2`e7l^;)xZ~)fw;V@_m+~%YMY_m0S9f4pbf>)N*X26I`M&b*V zZC`*_Hw(HT^sKj+uv&(G-^$$b~Nws z8&4x1XPWWd1S{$>bkvPAIE9IcAv5&P`=#xvY(1?);T#1XT)PFwY)tKt+Y(0no04;ilV zmeCxvrLr2bJz!gfhga!hPz;#Czf!2ljN6seW-vo(gJ?2z$X%< zqJozk>Dhz8-I=91_0((@+;{4Xx2YhReG^-M_{^F^J?1NROX?1n_4FDikZi6)TkXMh zXd5SlIT^-u{F3KWe3?zHtnaME>jP3<$KGx7?%ihg_KAJw+R@#gF+ zB-Rp|B?$;JV8|7yPs*S(wEM`^PDjljL26HKuhlA{f6(jH)ctd73x96-KQ;Pit{sj4 z88g%)R`=lG@&|(z(L^_^i35r?TY*Ct)TZ_JQ1JOyFInToTJu%V1vl$WyToSzS(AmP zr8i$D5lGjB6}h!ttF_sBsI5GH>NJg*V0J_$=TB#9y3@!UXU@(nJ2L{znX`ws zX=OrDKllIB*2loN_+Pqi`8B=FjvHw(XK+{?KiX7F@Z21l?uhx7BivRKBLdt<_7?w3 z*Db$Ng}XKRO7%F~Hm>#q#fspWN!volJjNL?!4)I%g&ucUw?QOb9y*H||3ShLN4&GD zBKxB}w|{Y2_#dkN^1w#2^ZJ*-1pHg*UwxK1d{YDPzX!3~)4*-i(R!N-5|ZbpVjNfV z-N%gz}YGVbVK!xvN62W zR|l>R{M-)UsTy)rev^_`>C;!|RlVUIP_T5s)I-Y0BJSrzJd%a*@NOzddY4{sjpA1M zirJEetgXB}%-aOAu!yz|0Kk%PwT(}*rD3ZKxMdDae<~#3`mOJP=CT#)PCURH@t`eP zKY!@~1B{!v_{Tz3Off@Q9$u$N1HH}Q6l94XD%&Q=EdSx445}2|w7W5_IO6_%KfY3KFNWEbLpX%Ch1jvEdaN!l`0;Bm{~qx96}b6ZnNk{Y~C1qsaM`96=! zd{0H5_QoWTz@(yorkfD|8#f?n_gCI&xoC&B?LCqOMl$YHLv}FzVeQh!Y_xj;npBf_ z?>;&Sc=DIp2W?5}<<$YURY+V+qyJ>AG$CMS=G8KkD0d~b8Hm@CN=rkUdiniig3R(C z4oX*L75i_6|5`}M^F7J_>Vw)|^+{YUY+74pL$_H&x%E0?x{94L#D**LD| zi?r5c)|)%rkU+WZyDGE5N#g&a3P z^>fat>Q}G)jzhM`FAkP%f3$XK;|?(EfmW*V>H_dAkkK5pMIDBmS81EARMB=(XQmX3 z2EDQ*fo2~y$0>*S)vRv%7WY4SI(GRF2c@&puvj1NkZ|$5smY$}y#6XaX36?Tk>8-E znV2sqkfOy6R`50zB&95Rv&D}20%=X|P}A!ML7PApN<~7CaRUIbCU>gQHr}ro@nW{7 zKa}5AC{_nAQ%%+B=pZ!@+G64Cy*!i%c!$L}F8d*7W?otN;r$qTmcbCh3U3ey<&MMj zt;>HnD4mrJcimqdxH|BGI^d8i9@5;1hDU1Xytqg8fWhPbw{jaGr5Wy5#8Vl-!Q0_h zw;6|s4%z0LxXc%>8#3#SNg$y}MM4h`?6v_AZU`$v`WthoZMJSA50IZC=$MBwcWcG{3kJy2Lq`MUo>w>JH%i0{Zo7Kd_ur*V6;tUvFaa!*H+bUBL%@#WcmqQIjGNQBI z43>C#EDGf}eC^WyP~3Ecl&^=pT=9utWrCSi0lAouse{-)fkI_2HJi5RxK*~6?VdI! z+cvJJJIq9Ynemd6+6*KDBM%wGmp$HbIGAnn7c=e-lbcU3`8rjP7+>`2z}12G*@5=& zv;?kt5By7uqx14y9?YML8UJyPQ=R!nEA#&+(N>VHzKE^Ea@WSye8p}_<&V$U-gvBs zNFZT|XxD&cJW>9JB|1H^$%=AHCEFvwr0tK^{?G^mO@{Lq2|ud6Z;Mz@sk4Bl3W!8uZGNOa{}`YlX!BF2Z2?HpzcHC|#9;8mR|g`WA2($@z)G2|_PVm;mnALLF`a z&Nl+YD*}XM(t3M%apdcr#xQPx$5}G#4bt}&PA3XbnnWs>DJz@K1A{#^Y!&DOy*<>k zDq8Q!UAyshwDRQmf#m3VP}xjaN4W>rRuLdY7jFnVmkgJ+*Ay6J)$* zRWe$%k-~*e8t_nD{sWtbyqK-&59PO1lP=rkZuSZ<3_{?9TGS2|=Iso)$UDG0?8kAt zNPBr}m&dMaLly9p$ zwP3tK3eUxT&TEtYTaWOm`M$~VLG@dd#D(g?T;9gq0Tx+tJr9qB>%2Hr9x#}2=%;|w z>_jji{c#+|+a2Yq`YIxBmQ7sd3)c;q^#cG{357~i$th)yXm%kHbIofPi6A#1Ai~w^+SDe;6zy%eg zI}yzmJC}^kU$fo}mUvkph0eY_I~AN2`BUaFve|}-Tvq;5*bY|q2^1=Csd>1)*pCodc}sbum{5t`2;_4s4F} zxC*XH>&~1!mj`p&)*hbv!zbAMl9=W7t!V!{JwbC;@IKlKveg$sa#-%#xSB5(K`|dw zIlf~r#t9_noYTJ}-8A4_Tv{Q0-jDMvQpxrRuxk6GwWA7FwE_)5li~bDjP0Rqsy+TM zT~N_93nwp*Rwi2$_i!1YJI-v!_a!B@eGHStTXAk_oT1-EZ2LCJzZ;b7-&HB7k$Ui@ zZvl6aoSGxWyz}x!9$!WEYmvA@1pHKg;R1woht%NhVZf2+2mh!T#trZ|OJ=<>2_(2q z6cEHD0_l>-rt`pHFO5}+KG54kHLF5B7aY(+F>$o?=IlZxH|A>cfcV5`*07BB*v|-cyT}L0n_d`Ix|?Uh^I1uGrLaRQ5=r8{GX5N-%7!bWRj4zUcQ^aijQBAvfmzoD{*~aJq+bTQ&x-P=Z z>_oTWlEJQ|HiJ`;0aik1L3BKA5cTBtI%2{K=oh&ZiU3UCM)Q&Hb?Dj zH5{*OSaj5#I0HskoHj^+ZI!8rW{aJJ%b|uM8PQp921~pwqe8h*wheeFF26K<$jeD3 z;x((H>YKRq)IoIS;b7XLc9u=fH@@Ns)r-JQx$b*PM#~cobnwmBejQXzFJVWfxgjV zd}fM6wrur9Y~3)f<|}qfD#v%WHiTR6DWXd5)mP- zhKz2sUDk)8RVPI8^!BirR8jS{gHl1e@pV*qa;)9-0E1Q84OmB+2iH~+AVso@2{Q+M zQM{(4CIgQE8`93qXx#QqrlZY2D6Fcg@1c;2T5XQ>Dm?Y+I38@>ppx^u$(f}wJJsc{ zjB3111<8!Zr~yqdhkDGHQ=8xe<_;OXZV(JkC#7(qlLkB#m%q7u$cx#U{!or80*YA^ zcwrEvtyQO^yVTsa#jSyhwgbGwYaDlTXdB?XCSz!pbcZ+0xYJsJ-k=nE9onwCb?L4S ze69{SlxrXE;gL3QB@!<_K0RQX{l?Lm!D>Z(QT}mQZ&wu6j^Ypzzm~&eD!`Qa;(kMB zy+M_(a?c|DwW<9GB3q`)W5FUWH(CqRN@cTk&{=t?e73CF`g70bDo;~;t*WfXYzNq8 z>*3W-qbP)#8Q*aXBi)tMW?-Dhw;_rD&>6~)4L&L2HOrq9GGw#zqI)Z(Qt39V-{@bW z=9s+%?GX^R>k+3H*ghBcIj>E+exv_UwNAbtMLO;8Pg|Zh#1ehp;Y}?A(7Oi*-b$yk zbxd)yns^wtX6jCy0i!EU>m6WQWh$cCV&~v;sG&$kbk>`}5-)R9C?5xS$N7REMqxS` zEAmAZI*XCOW-DG+E-OEyjKDaDK41sT5fxXx`t)d5RIKCB&*Z$IW8#Ng`dT9IaxKM5ya4s&E==8)UyY-Z8j{wt`j4;sT z@RZL4dtjYv$Ea4SZPLyHnkpnNo?hK?W;?I8;gUhvlw>kEg_++p@8OrWzn)1qs8N|- zo&r$;$3cNvSl;d;glrdbjnuioY#Tk>FohOsiNxZB#$HpS|}#2kofA!v3An~^s2HOu#PehuB{?KiewcN zW)AwIcuh%71|9)6q@5Vixb2%vN1K08SXEU^HBwQl&5@oOt~eZQ>0fu1^SjBJbft27dqhqje&&Waba zedP#a5TvbDr(;4=b2~2cOe;+XXsR%AH;1+r@Pb8y3^YqJ87zQQbptE(I<(c^T-?=x z&)xxt2H1ytc%(7>WGi0Wq_u#;~z-3@nn4@yDns^wtW+ElZ zkkJ*V^$xH`1?f&iv&GIOqkJi-NCtG)o52z<3#3pklxAsvB(8qz^N5#|LIRjs6%UOt zGN6xurx;SRX$wXRSxiU=XtHhNdZNHg1c*g6+6@>7SqrU`r_CS?5PFf+D)ex$X@hur zwn3tpo;vFMJuba2=IX%Jfe+Y$mmKMFb;D7w$0Bka+8*Y(@uA~aEYa7Yt?lA;=LIi1YD zSin4i0=Om-5z=bN$fi@i+&SkZ+bnu}fKRHZ`Z~;_2-}UXqopUu4Q;8hf_DXGc8Bfy5VGcy{W%ReZrmR5Zag;dna^q6CPxNH+D%QR&7pEG;F}RxH?!R z{c~Q(R^GjQH$ko-E@r14$~W_uW)91{Cz^Ag6?xPyw5Z%1v(o4r&5ULnHxw5~PY&9vZ(*h-n%3_ zk{jEip;BF$&b8C1ckB!RmZnBEa|mc;Lro2VLqRi}8bS?)LwG~F_$*(5JAOeXch=t8 z5i-#|{ImQ65CIa&UB?mN{eemR9pihy{`KAye8c=cbM0vBTg_0eY%$IqvGfm^qELQ- z1^tqIrPlsjD?bibKPAX4+7E!!9!pzgVedm|pqM1b+7dd2KY z(iyCfs!rkyo%~|+MvpECJ&(g!{YIz6=+Z#R325|#N^pi76YdaJaRedS zIN0eOhlezh$_5B^T;@v#W@F-uxEedy=>)Q{6Ac?sp@1|b+-PGDb`66b~Rg{ADY`fHWKgq{xAz*EoS> z6<{jVegu&QJQSB3t%tmrExa63qx_i>HpAI`0ovD&xOLo+z=(JX$Jv^=7|yzl)Z^=j zwqno-1I>~I1ZE7mf|U6sbaswGFcX9yDRYp{Y86`RPBmS-JbdRL_IQ~C=kUuA&jCFb z_c^akMsGdBoP3)+8ugFX`35D0CcU>}ABZt~aQH`Z<5NJqI8+WW7znen(d}7D`1z4+mS_00`G4Q2od>6fb6L`a`)V{0RnL4yJrx z)lPFuARCHSwT++veSLC|XTm74c9CodxOgFF{z2ZWXt-HISUz9u%?JIt+I z+W5!_%OG@TtSN@6UE=aNiads-1Jv1?xHn?JOaz!2FDXf9;2Cno$dRkiS038xxO#i> z8Q1gUbtZ1aLYo^Cd%v5#x)n8ar5F zMshO~#hnOV0WKwx3I*|yaHEa=+&M1~EPB6Ugw4jcj@Y1f-2*o)%?dj}4+~VGyXfdH zW@>x`)k{W0Z!&1>oTECZFbm?H4ibvq6%t>4;p)h`B1o^5_32h!FFDd<$#R~GWK-6e zHUB*ZF>5kYNsVs4P-wh$1=;F4w2kw@qhY!~-i{U9x?%)PhLh8>Ihl1BO`(ly1)X)* zp)FeUA9`rJodB1?)q(%i4sfx=?u$=7D)7{Hr#fK00=@M9tUP(Uuj=Sdw*gZ(DSE$T zD@d+*~PO0n-6z?%(U}?7`t5Ntn+L@#@xz&7yN6n4^seVk$^xvgpkgJLXHw z6%(MOmxlmV)@XHs+%y0HYZ9nF^}vF)crjbkAId%9PcZOuFvW1To$hLH+p>*d0Rue7 zaoGze2%DtO8H-MK?sdaszk^;l9fXQrqiVcZF{IkctSl9~0!B#d3(#pKrWN-?SE#;eM9OOo{)u41% z@;Nzq>+J(*_ycQhl8IPU!tuTG{Qi$B!OnXR#?zUONH`dg9*~*&mh&4llC|yl@l3U zCRYcp4*XCD@Lv5PjEOVe-2rN@kbYu66n9>;)nvBl3{kbv@z#UWD{P>i5A!G)uc*wo z@tLy$DtdVcbOKo@g$w0EsS^RfngpsJ8GrF&wyzvvhm=rF+v)mn7_^0z%oqz8V2COl zZfzIE%*-oTugMsiB?&b9xJJub4;#?fh;a~(XMh8Pz%z?GD;R%7@^-&td|5aC^)jT7 z10;L9&se(|rJpfF?})iNJu+$aw_ho`4sA;-KHZ^he6UE(pm$D+6U^qwG~g*~&ft#& z)AoiCJS;sC5|h?I*K_FZ9dQCv;tQP|c1ya8}`J$pzKaeCkN^1Bv-ya-z_-K%K3L8w!{srU!?F zs)81CM(^djk~}=w$2k%;4ji}qC-d*#KnX{{j>D&0b-mju^aWroeLK`b{is5X=Iubuw7?4V3(YwGz;e zNZH-@n>^e7ep7t2%szANXzI_Hp?I4+8xl`#kwZNpOw?=$?LV75@C-6$bf3UyG3JAt zebE;cytsCGh;&@p#I;*9`u2>2h-sSi87(f5+4L`<=>}>0tl)R8jSCb5;wVG<4|y?L zcnKQi&y29CMl~?xbZhO1d+L4cvu}DCXKUi3A9Wk4$JY^U#h?)edX@o0t{`(uV|27O znvR1IEZXMF4oVhwRxtjEWIJ`)fuCKSlYnGI@SjgvGMWGUnr9VmXXwnak%xvKv9kw< z9~sYNOjNwObz-yV%zzuYBk#c>h^ZhccZ(hK1=5-XsOjY)&bEgwkeWeY&sTePWp+uhhXP6SGRE8CNRC-Of;;pM9V5v*wE^*>_muw(j5*-ZUC zWQBnL;>2!G9pARb+fnkpnNhV!3-BW7k^iF!#lB?&b9xCARoX{qN& zBokzo|8P*cDo@IAsA^kM^# zd}F*-1<8P)<&VQ>2Yy{rJez!>UK5wqjn_DVWEHY${f33f_@a>SYjC$B;*o5c*ejQ; zbFknbsQxraZA-VPK+CNSjWxiNM8rZHRZ=gm(CAdQ{H_W^>a$@3?BI#AURjbrvyTY1 zA|<|fCd;;OG9A18hlA2t)xdFg5#n8Xx+kl=xAT!nyOIVgN)}h=mA5=DdZay6%sXv3 zQs3j2!ABzCam#SJ&Hs*mW%e3xQ$e!&XL?!0Wxm;N_cHAb(nkUrMk?AgU>7p$eeQqL zwsT$>$+%N>*}?ROwM!dMp#n{YGf${Abfek_ZP~>L7EpR_;$j;8BjJVke=#%jDyg@Z zf!<`Wg-Zs~QWvLuob2)cCde%R;h=O?CeU()9N;+qyWHLq$+Eu{!Kv3i@yc;A{f25q)U{JIg2U~M(G20XI5_8K>-wpSjfTQnPG8^vv0=|_^G*n4Et zh4C#no7WrkEp(DiGJy4(Nc>DwO*h!LK?eC}vm96uqTfCHHdW?(dHKaH2%fBrTR_ui~Grjkl^G8(=Mp{4lQ1M(1Bx?2gP6_x+NB3aqgo(mRS#&Y zP+bfa4rbDzSC(Wls4*8D;@4TN`-bV*rRLN zF5C@*zZPnqfl#gqkfM?C{#)@w1^EV|*xL*+< zMH2@zc$*56QZ|QipI9yvm-#}yCLU^fIS6zDStu0=l`q@^T$h}O@AnN zgg?Q+%M54J>4+gU58ASe5NI&Y*2HB$Jp9b~5^cq7N)l-HYlQ`!GcPVB%J{wjB>BC09GhBBOZ!b{v538+5V%6Q}rOkMXnB99eAG|2uH|? z&HjwcsjMB>%9DTEL(JrZ-zKN3s-j(qS8AK zm>qn(7q{hW-6$AuT|vSK>7`u5xK6a^Xeefm)*c+vuhrU3d9-t|)rmm3CLFf<4cpow zYXfZPt^4DkJ|0;LxcP@SmqnRA8B|7d&=v-rFdblkA*yh=EnW1ut0N8ns-VT3(a^gL z<~WVUgO^U&zF|)1loN4#o{<6}^^@u3km z!^!EBIw3U+MO>~P$!2!ls2FE!;&#WGdVF6}k{NZrF_`Iqk;7V{f7+q#siqGKctqqL zF@C9Scq!U>u;=1F=e5h~H6x4_WdL?+zVDKJOh3rtF@WCM_o6>jVm23C&)p+QbzU4Q zta|}y=%;|w>_jji{eB$A+fd8r~_RSgedbv9AnhxOIhUxhl%nN1O0S6794qPF_)MKFN zyt>tJyt2`3fN4dZf&k8}uzbGl7dz%l%q27HjY%M3NJT;q4`kf{2seZkJ@jU<**ZkA z^00}n)aaOpaQSc;v_)Z!ZaP4nt%+Ov0WGfOcmhX-}-oZx41 zIkXKil=e0iB-_)6wmu{8US_?S9oqhHTqwCdn&ZYJhddYenB5oMLb+YdwvDxalvqMibNM^=MO45CFlHii2nHggAFJfi-Hp|~J zW6bU3@A*bWDgv6Q-d;GWJh?sNXyOZ3--x2ZG@flt2ry@W5Dh$xP^+#W=>iNQ8OC*0 ze})Ui$kEn=(+Ol@CvvdWi9om}9Jcxm+u9*(18nH6`{SUlZKPnu01e(4#^_K-n%}-0 zT@O~kMb`la_~^J8P7h@rX)~{=Uojebm%$2&Iu8yVh<7^3EPn?-H7K6K5V^L|Jazk8 zOak8l(enPXR4ub4MEv|RX?j=L3wC<0y4fkFfYt-a{45YJCKAnZGmP^Zd8r4HF4PwX^}p(CD@ADmDG*; z3Jf}V(+HjQ&E_w;=s~eoCla_!t`1xscyArxL)>gGD0h!!+n2N9XHsFtsaW&~n^O$n4=(S3`7oyy(z<0-wd6$^g!+ zu(H-it%C(uF%y>ot06rG%&a#if#fL*q|maQMul#GOSapK6(N1M^+*ObTk*2;kc{KS zDCKtiI(`PWo$hLP1<8*Ajg;>|2ZheoL#n$Ng)lSY`;wA$28e(>CL};El$#L`#VmhL z$m-dC1;u)PAqT*VTphSN@ZLM%kYG4M=H!Tqt6p<@1k*Wj)@yTS86Q2_Lw=h%M{YFN zFKwGW)HGz!~nfxI-Y!h^d))sIgd>4N_DF7(_CR z>qJjR1Vb8%)KTfd=>)Q{6FJzbL_`SPgmBpK4cj@d05p2*{!|cO3~OKEI3z%GMOjCz zjx;|9lqFgAczy_Hg&kmkg^r8i^mG?9J+EF;l0cUX+BzA%V>~371@Z1&{tkZey-KcO zLluG>ACmF($aM|_L13G@)7bH8n=zyN0GpyWIkZJn8Dz+OEz)U~&FSPF077SnwvWV( zkT|}3#H(ie$`LlhdFIfzz9G?@5xG$~&ep{3jx!;^ymCZaFw!6c&63Qh*Eiwr>+gpz?C*LNIsP=o4Qx~}6 zkRAhO)*F*R@|41bawh6T+#pIXVnt}%Ltb5tvnm*+PoPSG<{?2f?PH~@-4$DLf#-yD zfI3?N(OryKFf;S&B_-($POSt1)d}Th#6vO5pMzCBxlfC(r|Ln7i(DPJI`BR_5RQ-& zlcPSadUF1BCT(ZE-tN#g#8CRk*Hn=54P3nBl&@VFGK==VwB1E4 z`fp<9k-pq7sbqV&VrKeNYkz2jfwn!g?S5&y%$3UT!r5$fTp3R8Wl*d%=#?eeK1zlw zn&O8zL%)cTJD2}(P`s^DKoiy53rCeN++QeIFpfH3xVobd6>x@oExySJGh%8c9_rYi zbmh9Y%TdT=^{EbK%Mwki=3LN_5Cw(HPV8dkdK*{}dk&#O9B zXgFZdURP9g5}Nr`%<7CDAW`JOVHU(Y9R#~wG2={i@H>vGYS=)vFyliq9@>i8k_NWP zoW{=1EIYF$d{Ms1q3wydgWs;2^q)AieI#zQzpurnj>#)Wcy_{>V%|$&(xxrY z%*loQu6W@R|%N z*WT;RMckR=Qbr=2(awuc-{F4a5OA8!fEziGem|_YsUW#NW9D)5}4C z^cgLRlgP&xsJadOBa_=B3^!W5UoqmvY)yYCcPkXDgO?f3rqj{E)ZVtm!rA*k!8ltJ zmtFMmGviCN71NXyVFFFZ8Bo1qTvGmi9GNCw-cP&yhlA2pnGvs-s{^m=z$0(c*F}91 z65k*%!h3TVhX{B&u=xRUE(5q9lFo~5@ET^k=s-GzrcjXTx`-eSCVal_7dz%#K>;!( zv)-5llCKml^zcAzmi8zSDU=h!iqN2kyjY_H`mBmaMp!bSkASBbQnPMLNUH7C0qSf$ z0AN-p49v{DBHAi08f2jB_i51;sQ~06R|l>Re8dif zBjmK@h>GjfL+4-C>pHaM`Z)aa$meFtH!<^v7j{o&Bo9|?Uo*l$yAExa18^PMcJ1LC zfpZv(h1noQ$55T&r8h)Q^khUZq@hS1l^&c~gmGMURmL zYZ_Zw@j?iAGG8(ke82&&8jll5o*wR-ajQ_UACXXnCH+%g@IPn!F5Ig6tj|a22Gtaz$iBpgKtaoHt6!NBU@Dh z7Gb4IM)qhnw#41$mWC^)^ZG8<;Ru;E8#ldi6yqfgwI1zlDo7xnT^Pr$`7T3>a@HI9 zXLg*gY1m4dy9NmKl711bJDjk4D%r|doBq_=(Z)Suv@rjM^P4ycc)FL`2W=7aDeVAt z6?Pi&Jp?mp&?`&Q8B8-*3W?9ZoMieY)6wQX9294*RH%=2^ZWZx*ViY<`%m`88Gh#4 z(aN7PL)GTu@Ek=vuezr*4H~BNa#Ui$(EAOuV+gcfFj*+RqsvMFXT3U~4K!(#>Kg>nQ+s#KB-zC8N~^G7xjz0IFAvqY`c7 z{fZGUW^4LG`7cm2cL0T8y(baoG~In*CaW6{WOP z=IkA9JJE|~oyPw2CaGwY0HDhR&WHRXe2a-Ev zLN`BItwYSgs-DfLr&I!353fKhaf~N?JdEY z?L}q9OUGrtWR|f3SB=LBBn%IrO#>_;S2VM+g#m;DIAz1E}(SEDSr03A}OBUTG# z?H;y8gn?#$`CScfBIR!*x9mu~?s$9!3~c?q=$?QJSZFrHl)$F2Ep zf)@3xH-pnjsc6@LQ*pnDl|$R)en}-;dHb6F)Y=~!;esZ^`Asqq@N_S=585K;Q`!OQ zDkQE9C*MOblLo!AB%Q%DbES~@*P*RyOa2|Bk-WQG&!z9(rS|3tedgNH+~424$uR(? z7#?MwA@RJbk2q?2rt@;N!Lq3L8wbE)R^90~V7R~ja^fn-3~`)9m70be=7dN^Z(?=$h#N`v4peshan62p#;5KZ8`yX4EB>6B)cy zlfa7KX@W7W&wOzC6Ka2CIrtMM$@v-T7umIMUorbTzK@IdUyCf@?cSXpaTyTb5$(J- zXO?$>z^pz;N8pg%sJnyHhl5f9f*%QpStm{Jk11iBmL-n5L zRF?%IVrp**)-<-V;-%vEBFl<1Dg8hhuDlF-r^0FTxUNgdy z3sR^fRtshA9(flPdR1!~avdOg9$>AzSTSX!)%dz$2rCQ_%u3Q3G<8~_=H5(<`oUq7 zKhzPame#ORB_nw>TaKvMJ~@A)<$~!B0>6uKI6`LSwC!;D7T|Ksmt~umQ0vj&rh)|H z*@bc3n(roPQO|laIGvP=b`3Zc_lsCLv`y}pRI-(~ujx;%{h<-Q4sDlBhf-Sl28Xuc zO#I8{>cG{3ch&)4^HG}%Jb9BA&#U@~t1cbqDS?-x09y;a-w<$^d0MX+AVm`sL|2d@ zAmX>-0l@I|xaHS;ydN^?LG>CZkbGTwiI>Z->1EsiCP=#h!`=rdAMx@8gx9PJMxn!i z5j0&*G;C6G@DmDE9XIGlq;3Mo+3L7~5J+AG7?_uor28ci7AL)#sK|N+`sgKV^5~)Uim5B;^2wbc zI2ay?da-LC5v!2UInY^^j8+%O02hA2;2}UFRIeCEcD?` z2ikYZyRY@{a=tb@qN+by2Dy0kcCo_(BlSMod|?$B5|AJyR}2siWjr}TAVuh{R9|IfOdlb)wG?yera3Z zH1|#4y5m?5R`qN~U51XRk&+ybp@f$O&MuDzVkSZCV-!nWHM+x=d76+^+VGpf2bpHEv;dtN(T05wjA}beRBRp z%LUUN1b!FeaD>c`4^QQYQ><6?I<#GNr_sqsUWc|#QwFU0%f;Ws#J(e>kD^~udDFbX zq3tT{``7*c{!{c^`rd!8ug>r@*N$HPlo_fw7oNjdpV|~nna<166#FEz-vD?uqy3zz zJ1*m`E64zR-;Cq>d6ba`+m`AzP9V9u^b#+ZU(?ID0aULT#H|~xl`(Z)wz@x_hR=+! zt|mgU)3s)Y2#ty{XH4A$jY95Uw$S(m>PHCeAfAG2i579HBpnY!YPpP;UB-7I$PBckz|v4T9S zlF{k{8HhD*0M#qTQHi$ke#M9vvwh_Vn`(v+hk)#wwyg5aI!}vnwk9t7;ozs|6~UGa z8f2hZl0dVMOR%DpH;qtkMof?{e+H?Z+^5xT%!v%%sYzhP?=-=f)=&7g>ANldGuK`Q z<)_ThuZV@W`|$K=J4ZUN&6(vLh&0}u>1M5D#Hxr|NXxiitb;PWt zHLO(0m>$iRqdvAz&Yx(xV6H=3X^tF2e-}YGLT1gWwWyc$i)h{9gxymaNtw~F8R3E^ z)qImQ1U%hK?Vznn%%`*i)Ky4a=^_^dm`Q^knzWmebOzJRl|tgb$)RoYhE_p8!j1m` zNpezsfLvdl;%BbC^wPh&r6WAOxu_xW)IRkN@4Or%VHC}N1K=>L?sOY4K#B=z??YFR zJ-KBV$E^WrI0#4)dQiQ_2_$=$UOZ^xk8uMYiF+I&Bk@Z~+)YTAEn;ra{TCsJaRj-;U<4iGv{*2HB$9Q@4q5^cqx5eAwi2{ik)!h%j(DwLZM6Qs+ZL8>SB zX?6Q@B7@81>cCIxK=?^<-Z+eVWBeBWYq<${yZ_LUUOlzioLSzH0nOTsCj5=^J2-fo z3S87e6ghoXdXJKHvC4A0d7bt~Cy*cUQjyTla%h{Lky5j1%ci?g9iK4v6xj6q1`s`* z@d1x%YyLd)K4i4moI?xrBXi}Bz(Qw1_J_8yCHFnf*g-$8itlD|Smd>y4z31QLdb zb`4m@6Q$z_plza9Qpxr&Y2?#o`or2E8eyQxaB`D3svV=+s7fM>S8oAL6%rTI=zj!C z%=Ekx?V4^%5@_~ujh402(tp#|1exVO9F(p~qF&6^fvW=_vIAJt^M~fpRKO=@BO9}w zmv8L!mjz-9aMu`a*ft&G-ByrMxOR`fz6zUAoqES7ZUW&y~rEXiar%U#J! ze0U~}hkBWRfKei~g1$ecm+qzvf=sfo9)AQ>Eaci|&5j$89h#@lPw8G;hE*W-=%{ zt)^|Kyd+!xizVHkTKhvI3^WNuqcOcs47d?dv^Tq%@89Ei0PuG>#*Sve`H;^M&h%%zA_L zb2LCmMVkg}0z#eRCM2}&0k7ukj9ZHad6G#Rpr{gZfla=AV@^ju2qfInC$@D zo{y)|Jt4u&%&Tz>Bi)sxGceBMTWM*bsisj7jORUJv_Wq1UJ#Nl7j;h@tP(3%S`X6o zt52`LrI&L3;)L7M&Z|IXzxaGj*WW`XX+=&Kz|&%R@(PWe_SO|7Ghc0oahrUr<${~_ z2I)%z2?3&Q0~XP!O3#&YN!#RpNlUgz+GylU(wkMW1QVs8mEkOdm~;Z3cp1$>TatQp z^?;@dHH}<_f|)evfl12-%}O#E)R+qn@$0PCeZ$+J%fFeBwSvy7#+7$BR>~VSeungK(u7>O_RxWQTn zxf8>b$+?{jIxBiz%+-Ob10S#h*hl?VQV*=4+2m0+V>&NSOYD6d1lT(OyqeK|&eUC$ z@zxb&0B$ZF@O0b&=}9u{jfX#@)y=u6;zy5SQm2hwQ-k$#opARO3$-#dQ^4_32=iEVHsGm@Q%n8s)CQi@e;;Ug2eiv*~nnl$v#0 z>bT9YqdZVI&ep_5KkDWN0#{%>(N@f+BmsdLL#`klltO1uZi0C@*g?tS&I-mCxjOKw z4tM}@0zLrj9TrzqB|!*B;|- zDoEiR=gv4T^Ub+!UuL~Q`jSAxk%~4A*oMpo_HUY;^Fp@rw_#p0!sai`e34W}wGY}N z=2O}M>MHCs!tpA6RW(I5-(q<&HyZkvJ1tEp#{>D=q7w-mF zWQ-@9yVi8dcV2vp$#&Jl7w;#t=a~XG3PFe>8e3k21>@5yZRTjbVt^D)w701sL5OI3Xd9CC_L}tuRn}r2FMlh1&}=Q)cLK+~A`7b|;Vy z62*cL+0Keyd*)Qr_b^L~y3{Pq-azTz0P_swb8(;Z+U4`cBkXta-$4HcCH?jWY5oAD z-dqGCJ@QuSygXsf?09IrWPtR4`Q4=i(G_G2?sps@F^(uIKzfp3#HtryJp38$II`$p zpjka`06f>E&Xh-{VVAA$PhiYvM%Yxty=emV>7}W?X-m>9FGuY-TN9W4kQV9jCD@7y zP#S2K)b()%23>AxouP3vG7e(%7c}IWib&;zBR|h_12WAfr_eeEdSH;V&69H&u zWuw`NV6v_rhY4aTNKkx^gmf1#6PNiG?dH`(PcH`n(r2_NmWqVRcP9ZZNCbCl;;DYd zi`km~Q0@qSf`M1}1X|SIs&)|q4aV7;xa^0ApBZ1Gt(Z+o0?mG{u%L5>&Ys*|{tO}r z38=FI`bDk|Tpjp`9dLMdO%5i*shYlvRXB>nHxc;5XLfveisL=5D&jSwzF7Tn#1J7H zn8QI-kW`L~*ElZotxxcbIC+`$<}e8)?=1R1$MH>|#tk?Z*B;uQ^RkDHFBxHT`1nQ2 z6Y#cn-4-XNOWFbIDr^_Imw}l+v<=HpqTH3FGdQ(%$TRbg;|R1iL1a4G{5c^r0y4Y~ zZ4bPUG4a_|8NxMnMP0oB6W~@Blzh{R;N@Y<1qJsj!oijFSH{#iaP&rckatzkamfG; z-nEKB?EyfIY6+c`9iW4Yj_ZrGu3uuN#}~dEqM>&gY`}`zOpGYhLA)}HH?9bVgVI-7 zjN@wn?CSK0#xv$dg+5P>;_+!!XGVZI1Egr6y-fuPKt$U^+j+EBGwaRQVpOAb2ba-c z+<+E-$|G)jd^feN3Y)E@XXVny>bc-<(CKR0PIt9S+y!b?z4p+y;x4!wbhDDWel4&> zg_&7fI}UOedpVaEGtTW~a8ED!;zSU^MXwHA9r!362uxIOE~>mfwP`wKIxkOCy+1pK zI|dprnY!abY7#_OkTJO5ae&lu1EeQOxA7S#kkC9Jh4RZl2L%$r-I~-r(i2{R*t$Pe z{>%uQ;cWM|UF{qMW-@0SRpV?;T=qj+q{o+FD<(i`pjlEk>MJnlq@_ZSNf4XAm^CLL z5z$&9$VILWTpjq39hf~hT&c#NDvIkWyt;KF0LH9rSWf7^3MT97ahM>cf`qYK>==-S ztH>TodN~M?ehVTCq|nKsZR-NCo_LDTwuii!ExZJca#!F*UhZbE@ampGZAwzJZc81v z8FrKh>c-icxaddS+~|4biMC=kB?$=37;**apcFcLaudwM!466mcUH~BhTlc54qP30 z_Z^V0rrhCjt~jFlE{TUD2)n19*EjL;htI5>R+Wd3fa7>ijF;4N?J?e_f&}8Yc#Y#S z-(^H9XT8y8H}f6mJRi{83F6{J+*hoL(m(BNH1td2Bm4{$Cj^r{2Yf)3C@ujBe6t(an_#urw_ zcK)iNHyJc_&Jpd*jFvixFTP#=c2KfeXH}fjYXEF_M1}LGidTI)?na3|PmN-IBzA|P zHuI3K36P?Z_BItH5E1PUZBhL?@~k&si(8G>9b86(aRVNSTaWJ^@w!P(lHRO}helXe z({{S6UE{=)T?Qse?qZAVjvaqSwV-9k@F1 zQ9AJdb3bD?kAW4OTCiZAU#R2 zSE*hmeMUPDpCJDQnt0hPyL`hf6Ykce?vYMCWdYV@tNRle^O+Gg!^zJc3Dl>TruL>S zNwd5hwc~6}T=qj+q{o+FD<(i`pjlGa#}ycKxutc6#?8n$h|OQj_=zgJSu0?jAt>sM z>C-muY0n>Z3_l9+r2lhqpYz(K_|_xL$+t`7b^13b$-geUS0K$E9Ik--Q!%)%!t3Br znI#MTG-h;P1(S94IE=TcAYt%164G6~Ok4(}VKE!OdWh-eAV8HZh!if=eno*qS{H!z z#8dQ)7qdkyL8IIic#)U8*(TekIn5eqXP&B>|^r##o=13t6w>CpC%I76{zNSl$&+P8ttpA%B%c525D{LrQWaJ? zj}u5%p_oce@ow0F3I+Qi;ou_ub6yTu^w#~UAf*aF4BZKV2Jbpzb);E)fOAoyR~?`h zbbtVgPD zwCJqpbum{5t`2;R4%BCF%vWtLxXt0#?o>sAR(RHX3b3_s5Da$=G+r`5sz+iT=DLC` z<`7hAK%Vyc-8*Z6!w`Q@md z9QAhV2Kj< zn|<%_pIl1qdR$JV98D~sslrU7?*b}jW_(4xq??iintfb?6{SoJ|En0AAhXXY-PB6{ zU6lg*0ckuEd+*o3-g|;?nBQlv9c}#?Gt?s%9%c36j;A)4jnzWY!y0=^Jk;T<8&?)C~}6<2hhikt@nDu<1oM zTMrW}mk(W!jBo%JeFQworDoF>^cu6TvG>G8r)Bijnw24-e~2{$j?to!mlt z$rni~>oeD02K|qpG4|$1L;PXf*GGa|ufT;Czs0%(ZTxGyQ=#~) zt^=t_5K}<{gQ))ONynAn(VdFh{jp5`IL#!G&_pD3_M^d5k#DqWe#k}Hj1e!6iRlmJ z&y27c&Zg6S?Hq(zrj7hgew?j|%YNM8XU3OkD+Y})&@4%y*{>BAbkb6xvtMj>`7=oM z4mw-lWsLYN-?HN2$Sd%6b<;}eWHzw^)V;qlAS5PdipjzItG&^E1H80(jeusM9RXRNvN*P*SDzT^ z%lGKJWB&E-GWvN5edgNH<@a!C%SYU5me^@D_*lIn!e={hA%)1Q1W5o8*8Z< z6spiz%-If5XDc9P8gWPIfQ<2dNl7{biGV;8g7`8)_^~0tewIH6t9o+OqwA@9+LR<- zD|l|x|-<0PS=_pfEpDfb5a+iake^cAP`z4f>)N*jXHzQ8Hq3S z@UY$FFJ_!t$t|Rpd~qU(;KR{BK0wBw`QY+1*IuUPPnn_PLoyyr`cv-`d*&3l(3&GL zeYhrOSc=x6fE10s7DMqi6(l9k3-85L{_rI{>!IzbW$Xr!S(S_y7f2K?barU_P+T70 zJ>#4s#e|uM*(*y@ z83Y8_5F}QYDhG#6{!mBbT3W**l^XmdM|$4`&mTUsUqs*zm)Yyk_Q)gi&~Ik>hI+{B z2)X0ep>1x%{KcH7+H>e&`#49UMy9{#+sp*{w1>8A(ZyUH__Q7HsJwf)BThlzkExzw!N5|V0rb$~kC001+Mn7o4? z2-uowGedK>i&4TqK&*?G2*44K+$7Sd!t%GXI=NSF;(cefp{|-Vy5190lsw`L&3#d9k@F1@j5U*B;(2Gxq|FLVBkVKK5hG2V5`}QFmG~bdm?WA zq2sJdv@l^wMM7tXwhzVSq3uIn%=VQdY=-m9q3x-p@3b0cYvOJWZ3(ty&>#cNl5TKj zAD3W7iFqymtRM=tvYk~(Nh zHJ-MC9BUu+pfMV=p5g$`RH3_w2@p+T=HXQp5G;s;ZdQ`XV1ZOsdS*tsgKm>Q)X})9 zpt48>Sdm`bBIV22P(^i*`w`KaZT=m3hXRE`FE3 z$`w&Fxf_OOB9mOG{S=^d0eAi^w8?*mTAhMAc%Cz${qi&hj0ik6@?v%OqVvT+x zm$5p94YUAbRC6?)?rQg^fMN*n0q)$Gv^x#6(}CwB+qZ}geBlfeS1s`SK& zatGZef2gBzQ$b~s3a}!%4sB~MCR{i|)_fEFb!cmUmYO>w2iAkLZ0X#TT0rUfb!Zz~ zCe4_3@BJ(4R~PR#*YIvLd;7#bbM5Hv&zPYevATylp4#;}4Z{(siR!IDS|`f&YatG| z+N`=mJt6_Zn2`4NRRQi05w}nd8hA2bHH5*C%z9(?-^n+NB0RtO3qaHj@Q|(vd+&;! zUz{R6VqQkBr|XRXeb=e6^m83E=@oe#!aSC9cVi=CfG8EIy{aWH1IxprjJw0+7Sc<;kc!-1^yFGnT7udWt`Ap%2W#!*^E2DQKXDY}^c+Z@fi3 zXiH-?V#PD+JoLJX0BP=tm?Rm@T;k)^&XOXTzwS!X8O(87O^FZBq))ypgI zdtEX?YVbA{B!iI0b{@Cpo2<9jtT!fsgd-L08nBI-4E~W`Lj1q9E!}S~$u`dCGyoCc z6(bBZ4Cg;{7IEkVJl#v}gSKSz)k_CxsxZ?i7uHN$Y0yKHc2kncV3j>}5Q^HH2W zGo@rV`PT_42+_yeDx*v;^A*G2l03<7i8*_9UVlxV{~iDTwLk>CIg=<}xBSYF>$qE! zjC4;nxAYRP9Hjf>YDtrex1Zb1hNpKlH0ri09cbd5z)4_Ikd&A z`NLta8(}k?sUHB(u~qF_h1{m3j8g-6hiUG)iHonn(u5E*Gq2#hCL`#125T&6Z!OI= zje-pF&t~>*my2qvY;#EKLAv645U*d;OTN-NdiLtP3S@Fm>tMQmahar*I9>w&tIyIi zFRmIHZ(Tt$%cT_iVceQ;1zmBo-XMKRAVEO1Yrra+=z=iiL00cJT*+3xtU2$EozZII6j(7<;&5C&WdZ*TS-=L7S zKHiFmj~o-1`NDNWX1ziBHCjClVP$t<>jrEBLd}Yh{zG1@@utxzmo}b4h1VU%sHW|7 zSNrW0@C;D*{I1PvKVW9Y_f+IvNjig5kkV42+;Qyk9}Y@a<*6JlqpJf~2i|7~0@A`m z+A+(z$)jk>bY8#F6nh^$?mgrHuV%ELGj$iGy#rk8HscTxw;3Kb@N~F6NoKu4`k{f5 ziiF0EY0;VnG%jVJ8ub7piGxsAlRoRzOKKjpr5a5*ZU+MlOtw0% zCko6&@XVyu(6uC!0Yk1Bi7)hUu+~95F}fi1OrI|0f|cA}^ypxnf1m4hSBN*DXRDdRWWj~ zMIwz06a!Lw|Abc{pzcqVKQqFn8r49Lh(Zy!jvMqN;wT(vYvQ6G^_xdMzO`|L?U?|P zfo4f&)ETlzsuHxcew8!{LNF7AyTc4=t!kW$yE<@n;Nx|`{Kpr*NCob2!tQD3_1GU5 z*$0Rgzj5u6)bxLq!yleF--QcD$gKIJCd^mtmQ;}GHBKO7$iE%gG+-G|l%CHiq%Vpk zm2B}ZEziReXYUGITDDvPo`9mFzn+ht6 zRET=qz}h3KfbN}YeRt-xIkOaSm~~0j^eT5JYrJnzpn`NKqV1urOV-+IqOGNe8I2y~DdZ`i2=A^wN@a2F*ibUWvpP z`llV*`gxA8)6}Krb(rUnPAwScpdPY%F79()o5cJ^|D)-U?p1~e{nmKFKAO|P-p2AEj6w6RARNE~E(IFBPVwx;%0)mV*LE=b~Kvej`tL0~2V zj4#zI#zCo}Ye^=96%=(TeltUl!$GBkcu2V;7BkN6WZ=_FzL1LCUi9j~)q#)L0jy8m zgM-W8iJ}5+;N>YWOV(`Bq5YhxD~<`GE64y4%@(^bk22ECdgEctXmx=URkxg?0i!UT z3~{6U39mpn-JdFdW`xaf4j&F4k(;(Kml@-z7-wtZvLDhSJ+BD1Vgi%~nk99kz5;_z zS}OFI1hM&x8Fz;n&srhKMXnB99r!36aBZTSBRyr?`YHa4+_|GTY|bpj499z1RRm^4 zacKK{dV-c9`f$)6o^IcT3s~;Vp&s+aN-O4LD#-L2Cy<>}PCnMNX~4O-v_ks4ALm)5 zk}Zx4w}-ZF1xB4YeB{#v(c*J%jEt-f?P<0I2fUSIIDv%a0Jv)a%$CGc8_1ntP`sz9?oU?*?N*GS74J|@YoV;&LEEUR{g?|? zth4n{AZrX~otr3D{Hvk@&NvUntfa1wGoVIpCdP5-Ao6brYMKaw@*+}IHEgmHq{!Cu zO?^al@W-&(X!r7ihqgQTtiRJLU|`LeDJn>2H`?k`KJjF}v|BQ>-k1au21KOC9mqNn z2seZkecc!;waxYht(8kNl=JKc9lJx1YT8bBwcln~BY6j?v%SNo>mtn1pqG}UGZ-b^ z$t1qeKkd-A%j^+b>G}-F7o**z2!84OqLr*hc$Q2{;g&q#pI*2ERDU%;5lR;-iuZy`laCP7V zb^z-_w?bn1lNEGXS)dkPo&vL)3>Tg1PPYLAq^L1LbOqUSv)Bc~(~yz@GwY3qZ37}A zq5Oiu!4?f@T%Z_`+WRNG0s#?gRz;0MkDd`UGn~VRgNHlf)^Y1$DRJb+*_ycMNBx&* zdS1PxB-1a3WTpc~_6$Og0HaO*V#c|h-5ByzJ&1IXs{>aD-f0ImhqmXk{vu}XaGBkl zS&A8s_r!ZiuV30O+e4*4eCE#{+R|~!n8QatP3)m<0?~)IOIT69_Rv;P*K|`-*T*$l z*2=tg*fONeNM_|1%6R&I6D$eRy@8TJXC+>V>g@&N9p$lp?(uBB1T?}!Wp*3|9Pjav z(%4>2Cd%7ZkbpR=l37WBhFMc* zhg1b-VjKs&%`E8hM|lybsv5S=XN0arlk zFZz(0IWt8CDc~)=LHVAfVdr z;eKijhO+~;8^S0)v*V%nk|{_b=7rSoj1KT>HWwn|X4%6Ao({Js$*eaffrOSt*Dq~T zD?)lXdvOyO;9+_`o<`hJdU!oEX*G1s+hl+UYm(wOGxRtd>~#K+_; zE1k+VFfzP61!l<_E;`knZUd&SI3|d$AbUbITkL8;8V&+dH0zCrMFS!tq1|$d1~e`J z8IaohC%ggy5o=aOjY5x}5i~QL!-s>1JL1-H>tQKzWxO`hm@_Js0l%OLfKxm*@ zlIa&ij<7@~&mW=3BnZJw5bh2$ptX`H7ri=gb>Jg*;G-Sd{+^zoE_YfV4*J8h|KEiR zSng)Ov=zH07342sHBKOFQ%*jvlABX&L0VFe=RkU5lU;fwrDXf(9NMPZ^|)*kP6q!; zhqh^kV#|=8+?l-&ZQ~$g4!bnq@rpAgUEG+otl5OXv*~K_UB3dEUXuh8hyxOGig)nR ziBu@qkBFx*6z-Il^r3p|{#20C3?#-_V@A-5cc@0SP}c6CEvi!sP7jEldtf1JBwI0I zCjPH1NoUa1iIheJi8<;#xJ~|cP_kE7B~gzXSbanlm%npq7VqvLaC2rU;54iGOu0KX z#`^{ZDoA%C+WvWDxNgX-H%Pxm>kckw|54vfK&V;K*K_v8%4U1hXx&(y!iLu!#@!if zlFMig+5)#Z=>T;VcX*yWw4KLkG`o^?294vKm6<8@I<%el>e5^t_-q{rD7bsL*QfTr zC5|R~D-gwaX6yZi**DUA$rPjzBj_LjUUf%th=`kI4;y$o+@2(}-so*_2Fs%B&^GlV zj2us(GU4lIA}Oi6)8=Ap{fP+;`R=HUk^QHBiGrKmGObOqTLqS;~>7@&eu)HAc* zc$hL;T_8m@YrrFMV-zwC#cxPH&7a5P*n0Xk&hXu7B!Dn3W)GhjMEldXx%2?H}} z&@+?PK+pQs6gtQsBB@pA5uh+ZZ2n@#xt-mt6|gRHb>Qm2hwQ+0XuBOYfB0aHw3Ro_Y~RU^NxRb+@3oq)R@6BMWO^O5El(UUpm2Y4z)L4m zq2^H!PhBY7DKGmGf;;R<6|&7_up#3iEh&U*QwwG74%(tZud2t03snd}Wb2_o=}5L> z!c6>&;x#4d44OJ?t{rD4M*YyV$-jl z(`g4tAL(+!uLaP`cH`yI7%j`eMtA;DidIe56vjrb-8CKBLeJ5xBm6)j@nSB#mk2j`{ zTmRXi*e&U-Hvx@p{@J03b`4m@6Q$$qL;9jvQppw@__Q^7!3gV*13n|BG)A@eZCNIq zlpUa{!c3zt0w`u?d_}#ao00^YeO!VSC1&PP|8kNEg6Y`hZ{I)}uCqFk!8+$Q9w*D_(qWIoPTF2Ek#*N3#MoH-c1C zgSV+5xz!!lI4<+8pvi4=1<2{;A|yN3O9zA{3DlxNj)DafpkubCKa_hI zJ~G12`qWPI*hFfFO2WW%LYTxjTL(8ioW~I$M}xdJ!`+0S5zhLIGiVE)0M?o5X)zAM z2_InC4N8)CRxrNE)q$%6AF%@-Np}wpE`KMgsw>fKHQX#ZCt`$Zql0)T_nkbWK>1Tia=^&DKM0<>&TMa2`K_+D>=1OI#qVN%yqT z*#>xbU4)r~{)tIzpleAw0|eL*i7!;PeI|$_Oc#Wn$I)5Q>*F!MzyFkd)B5+H?Q1jq z%(bJFZ!<%k9w+_Fq&t=J11t&_Oy_l@vHp=&z=ZyxUvL7!BCS=kZ`TEW^Zrv`qwOjo%6y-a=UK&Q$a!rS^HY<$FIo67i}Fe*O<#jSM?w?26MIt#1QJZM@hE9gc(8O&!sxctnum$~*+ zW~km=lqYWr?~y|xn^&&A@WNImdO3Ki{f2;x8Qoz#B!a}$#M@Mmoa>Hj9G3yB;V@R$OMt zMQ#BD%*S!LmlHDxeDM-#xtqO?p;?lEz>Fbha7pf=6goS{AXtC{f>eYg@2p^ag18el zKWxG=`(dO<0oblb9e>dNxwy}HZBlg`{g0|S`F<4WyuUkddfJlf@M({?H1q&RR&_mp zW^4brdC>H^8i0&q#lXw4jw@$~4_ zbLlQ%a%y#>V0>Do4{ZajR}7G%iT0LrLmqKP3!WE#ErjM_3PM46&#kDn3V<(15`>RY22o9an~vhn^z9_&zjgHS{!t zQ%f=8%M6|UnO#Yj`QObItq4jv^fkGtqpxKlHw^K!*GzKRMsXlQ`G*2xd zKw^^|L<}@v?(2v-F^E)VmFhug4CZVPsH^aBEy;!o1T#IaUQ?3Fz}1ioEwAKF@K(uSRIfoW#9)7RUvi3T(J<+7gOg&l>&*qXIat-&=k%gMg!3@s zW5Pk8_8S5&+g`fEct`~4u->MEq(#pkM4)Om@T{njdEY$MPBY^ukdovqpfYH>(>OjE#fjmE^-SPU_Oq^t&EuI9lS_^ zF(G4UmLwoBW5@|w7JDd#@?(R8LQluK4MvbUx05|X26$iO>cG{358MHd-1Q0>gRyt5AYNj{-bY>xCM2wHsSEzX>76zC(dfVHGEqy3x#QZz8$x`GVA zqr|TT&&0hK>DgCvfH+Ga!QFr<^!lYO8nPi6r)Z@|^A5l9G~%JB8Q)E?q8>v>-8h3& zm~!MQ^cV+`beX@Hm8pf@N@rC+>mGa(mp7DWc7fcU@iYmAa};=RdNU9p<<8`TFxE>y7$*eaffdtoyJc8&%AY2n}v}LQcHWw|5r?-P*R)zR2sowb3 z4;ccUoKd^bR+ZGNs|VCocsQ3Xh6)8U_&17bGUIk7=?rElN*-`0o#3}h9*Rl+qONm0 z+6VYVf>f&DCBMVG4sFrUfL`xTt!w`moWnakeM3ujVP914aGBv@<4Z<(bHbS-vUcI}uEfj>CAH3KCS^agF0L-(yT6b`H;K|2b4mYlV zSdl>GGhWQr^oMd!_!A7g98A&Hw$okhZCkbxEMS1gI4=7kW_r83jg}3@&@4%y*{>6* z9yUVxvB5#1r(@cnl#4+;1c`K2HoA+wI&gL1qjkU|;qJk~_m)E zZM3(CqIq(QXtvnZd@JaJoAqX}#LEIH)GnuP5vEhIqG!BVqX+J+iZ1L(0JH$z^5HOO z%Lr1*IzXMRiRWM&b*VZJ!C^2%^i3VtUqnTHVIb?ZYv@zyFMV z)B5+H?Q1jq%(bJFKV^o_j;MIH0*G0uPqt{90g^ti)X2a$9qhqmzP ztlG#9H>DGvsz7efc$$R5ISM>Dy%`9Qa%+V96#+st2{41V!!5_M-DwQtdU%{Av)-5l z5?m+p2%-~#a80<;maW#>T(sx|y&V*@D#UL|f#!=5H{geByij}JgT`jU_JFzy55LmI zP*GrJ_V87|;C3bH3>H9D6~Ia-_^pzMVv@h8>)ej^0X~r+l`1fYWcK*A8m>6&wL7yk zf8clpP2G2L#@keo%)W`OKYV7*p&s)UyCrpp%X)f^6G%1zz1}q-Kq8GPp2(e$4& zL(S%bA$`dqAeA+-UI!l&4vu=i;UR??-60+lSES)MeBmUBsURuqj%ys30jnV}M{B9@?0?hCxg%iZi1UJiP+we2)&uC*hs zxXh4?+yVxekK>{rbsGtRFJ9sdj0qV-vm^n58ADFcve>8BP-kfOkx5U-nm>ZHp4?tn ztAzeRuTvBL&#f)|x#9oR=%2ZEH2!DIP>)#MgM-T-3|6Ejx>-#eP^{Ss9J)|#w6}+X z&$o8T8n37|-wL|mX1&o%d1Tia=^&DKM0<^8uD8b{rsV*$eD z!(q@Cg*CeA0Clz|t|J7@MDWC* zb>PEwV0J{sbEgv(-Dv}_8wKOjs?Ln|a|TG!z{R_B3!CWxP!V3CUyY5x)@d z8QH|G`DX3zW!4*{F9{?Vsc6@LUC6BeAF-13<$g(#?QgONmh@&-EWtzxG#So+h+M$a zz0^KviO41ojGgk_U|6d|CL1y{a2`LB>z}YGV^rBY> zt`2<64wMJq5pwqYCM7aH;UY;}h6X%t8GMwUx_oYHN=Z_Kx2Yh3xjf(JahdO_ z$kX1K1QM83^pA8C;{V4DNZS3CcUmsmp>2DQWPy>4JJpaKOn+Frv@sj)UVtXm86}I7 z*$tpNZp|0!HJSD14mTu_?nG4RyaCB}d*!(IWQO#&9?3vun*_Q)wf4tHSPy4Ln%2&^ zDTVEIOBOAlsbVyZk_=|jpjVb;GDrz-FNvS&Et;2Z>%K*C9?vHK@t{~M75?ub-=_5} zUiodC1!)~Uds(kg9VZ{j0UlShvsZe~;*!+htt&`2xs+_2*1s(AnZUE=o29##X>W7_ z8K#Irg&a4a>gSxRs$YFmeiaWnWPAJ~{<=T4c4^}f#R`E|s_|6|@GOwg9JHl63^`w= zI$Nnicd^b)DfZWb@XC?|ntiM}PC3MHX0_^D-2dcp?D8KDN@rEWVtu$n!o~AeP4-;p z^;hvROV)oE`3-8CiTQ#8DO%iM1#eS9Qp%z?TkM!Gkk;f5HN9>S=mfG*DiV5(8vuYc zxl@g{@qWdK7qd0}q5QT&u{wB}YMM?*2dR0`77J(Z<)K8tJ1oX=*$*)@^UA^x@5j)y z42BR^c!NMFcO0f~UH-#C>8xzH>;CG%)qxMx0f$`ikmgP-JW@mF#XYJA3?BEtmD>O* z&2YaWp2`3Y-VV2Qn{kNfkZrz+%Y5OwA+z3?1QLo=B=qpW)(wDgLs${g-M)xG55+8h zPRQ!nenFp8p$)Jua&_S9z`O4NmXVxiK(^fqiFH9%&}C7M+RbX>VW`cjJ8=d~&02d0 z*fyDpXtvlnxE$3`BqKWO&0vX_$D&Yv!>5<_hvKFqqExhlfRg8cbMFK zddb(Rdc^pmR|l>Ryw48kzvB_O>OJr;EsoC1b9os5X%F+qMNW0*8?B7Dt{_`|5nG4l z4u4Vvo;6>wTT=PsGqyJ#>md?I7$Vv=U>Q%8zhQ|^Pi(THoKng52r$w8skJ{e!a$SZ z{6)f#YVX@3)>G;%ps7OQVmR&J1(F86vLutiH1$>?@xO~On7&Q&9}h}brJzRY!I!=T z+(mMJqHu!H%M&Jm`?XMqTY&S80P%_dA(?1z4=;{p^2PVIAcjoUS53iZ0f<2{Q+M zRY0&HyOMMU3!p}&XJ%CBAjc&CP$8NMDvMOA)#gagSIY(0ojJ+*-Q>*j1}vC$NsU5% zrOKsGARz1R!NKM4L|KkD zo7Kd_urnjToT)30_6~4C1?f&iv&GIOqx09SH-jZ!7D%D9FV9W|XGQ*$IgD(!VIr56 z{}i@^m3;z*##?G0w572cv)$9iRH5T~g1}4!&rDhkT_=ypfFW0m#20!vSnD937+ny0 zw%<9xie49Ub>Qm22kgM+NRO-Fs<=9k1QuWv>Bf725*X9e#= zSCFl~2$I8cr{mUqu?UL!n9A`TdofNRIp>`I73rn{=i<@|>GOV^XOT*_M}U>?PputQ zu&Nbk0GbTvFJf#DZBy;>f9ZmXrdc?7akMhonz)C{0Nrt>9^aRgr27~qiED9gX`G?o zMQr;v$-f(v?B7)>sF8Z`rEdXuk(`<%#k}+KMIK*8^=py1LInI&f8hdzbcfX7?P0)? z=Li3&7{(3oI7?=|F$pBNP81NtBm(J@$fonaU@wiU5`CbzhiXRs4$yccJa2}BF;tqfaR3n=)1YRH- z)vO_CC~QWvhLA(i&@MmA7HP(xOQ9XPcWw7V%FOMv>_du9iJ@Ip0l|XoO41oDfEtya znNgvG$aJh}t_HqFB(I$B!OnXdW24LgGA_Gc4*sWb_uQyTpjqUJK&IjeYl55 z6601^yttqBfYJMn&J0#7;;9Va%&xQUC=N&4aa`t0yCpO0jY%M3NZ~>c4`iJPgd4(& zu+iF>Lv6El6M2CA6fs+WRHHZVQuClK+ZY|7uEGPL>mtm|PIMbC8SF~Z8JvO)uo5~8 zQpeKzb^fFdGv`@oY65uWVR!sylH8OkHtw zkO12zQxVM;I|rAe8j55@XT2FL@v@8xWkRAVceRp*e$6X-`U(Lm$pZU|4WydM%{6yo>$pr_hO;>95e3- zWUzzFdU?})7i${?)6wQ%C!`=G0Ba?niF(|WtOM>MDUbEvs$kBAsw!Td0#O0SK~c=` zrGN;bn~)|GL)$oUyDEWxk*fn& z2i~p&r{3!0@NOjj|70I?h#F5N1_~p$nXL2Tq5Rn3lOkTj`~%He z&vw+2N`^S~;!j!qpb^LH2XP*EfAIbLcz}t=<8ebodfaOgz7_lS<_-8$8~fMBeT$N? zM87uCg7!p*0`lk{9C$08%GLp7vYJHgcx6Mr)txv4rmi@8$qKM-G8NG*u7k@_4Mj4d zv)&Arco_kqd>rToJQSBt?1#LZR3cupDw@8DOHUm{_6ZakQ>odsrH)%;YgsNx0%)?; zaXsB(CW2=st%k18JDq_8yi9F+G1fIxBiz%+-Ob1Mji}c%x5p zGe=Zh_1e>;i7UmydU-4&-D#UXT=UI>La-V0ttejmOWRp6C4cnL_FwVwxM_gGpWS@K zL)%n4MzuN1o>fS>`&C#oACHg~AL-EcJ^a#^(@)wuqNTN2Q`QJiD^UT*L80~xB7|;2 znoN{8-})T+W~Xrs;|2*qMg(J8kQ?K10?AqLg`+^cR3ajb`o$%i&f{>|DlBXp75YGL z58b4Srmqc%Wq}ro+)?exv3An~^s2ENu#PehPFE2iMY0tWW)AwIcuh$v1CIb3g2eb3 zlW!mc{3iK}I$G7z8WyPlB$CaMUNu~CIM}Lx-Br%-CTEs6fYEFP4&7JU+`#F>!8`RV zD!ymXgxR5O<1=Rkc~&Klh$DnlBy`e%d9X$!ahv12MmuB0i`l+%gfR%x)~3@j9jRH5 z%PdbN?*L5|CT@3}X~tJ!&u-8l1I?051~U{Tzu`{k4;Rx9F*^3TbxQ*AC>v5l|exXhP!OJ>#^ROuS$ zEV>SDQ%BmiG#whV+ysi3?zxAT9?mF)+3!UkV0Ma_PcxegPC@4Qf7Thwj}0E~v-~+B zGXjiJRJ=o#kYD8Lz}10|(g8jSW5NMRcMlG%3tR?P#W^ZBtBHr9HWMjPhD=>?w0D4Y zQ3Mgmi!=TOHRE1!f{ZETYkFz&OY>^z0oG1_-@KY884o*ytdho~BIh4wFG=MX!sw zI&gL119re1l5w574sAJ@*P-nZ;{Vbmho^j+G$*t9u=Zc+A>p%aqssTI7iR&b=O!+m zUfpj{^*;t!MWSw3lF5L6D<;2bu0z|lMc7Ux(Rjzfk#Bbz@Nz&Zo&k556LL4D1({y6 z1d>0NJ)ih|1yGfU2%(!0*>uX6JLkL(^numWYj;FdD;1Y=giwe7U%Hd&f9043cxN^&U$-rz(yz!bOkgar1 zQ8aA8xwv((O8V!#kZm1m-Jc5La>60MZeP?KmSK!ub%Js+lj&AeZVR0Z>J-q~N)@_` z71Jl@c&YIXS+srGl;iD4{g=hP) z8xpf6?Ytb4O<8BwY&c}A#reO4FUl{pG2Xg@Y-RUQ;Rsm{&zdhWR}4NbRIhOY3BsYG zT?1C(sQWIQq%ZeND%oA(A2^60OBM62pa2^Y z2O+&om5g>A0j5G{4R|OnH(C#QFL6U*dOw4(8*yoG@ah z$G4&ZWk|-*oIC;zv!>7?S{6#JLiv6&ee3c^5dARitj2+@Zy1|h(yIek2maa)U|k5v zf@_L@B(2V?TPMaV8_iAxbF}f`;B6{M%H3kee1Wtk0cv`A2y_BjC>04k9Bg$1AY79` z^{J;Uti_Ajn*LDk34eltmxHNY;Imk29<*f}!2$+&jN`H&VrCv@+i=NX49&?S(CpU< zP!AiSvmjmm3{pM0PpexvpnpUXkHp^l^{@Ay;2Y-mnQKQ|f5r^GBbNRFQxwV%u%KU( zuhiO~YXz*L<~LQ=jQ(>*kfMe5zQc#VQ9BM1@n=sr*ub;q3;CMNdSiYJmq6s_dqQVF z8e9j2mKEJjnQJfBc%R6nji<1ICWD}UO(p)7g|(q162&B?68XbNpqYw)PO4sFpQIrfdW!$aF`C*P;RpYJm*mDOiHxctnu zmr3wbW+>KPhk3_U6i;oDLp>qZE6`5w&kj6<^^PGv@K0QIlVZG01qq4|6c1n>w+5sk z?1sceX^PG?#|b3gkY3^y@@sk-H{f*Kf`jz;UNJ>iTxz!P>g3Oiu&Ji$bg4N73Gu&l zA#NSFA|AeaO2^rnxadbMR*$bE+KRz&8ffM%ATVRd6(m|J9}J`EI0(T^5Pqc0K{~5d zXstWdbnWu+oqyQlWe(`-%ka(uJs0;muT4&GJ;I!Pn>=2qeuI+23)6c6)a=3GAHl{7 z$vv3XB>(BU|;_AgZ>}c{WI5&ar+rF^p04w(<3eetGV=* zN}M^#`Q7ZyQkyxtFPOmfSWX+w;UFqV5O?B?4~v;^py7&{^~NNSAf#}ilLmxUIOGfhq0AQ8y^{A8HDbPHN}vcO3eKNZAf!vOOQ0UEsP`-0oO=#Sck7M0ro7j*~d;ilt;B6U#K4`ph6 zVMU_}qoFq$v~^DKqS!$to!|!t^eq&rg3IQ9QLpzHWr|3N+XIvjY!dyfju1TQ!)B_9F;>B!De<=5aKf%Du!4%cBo#uBhW=C}bJepX* z0Jm{m_Cw6f_`-Qj#?UNDpxLiATGo2l2%SB-yZjlXdUBsuw=qD!$kld6W7k|RBqEa$06Hf5dJ>(3+WQ)}t|l71I$ID)Wy+WlGI zmy9rGjtnQKWpgs?4wthN+Nic!Ux&76(SPWn?VsBj@YfrB=3kqB=Gx25`zbTjY%aKp z)~EJ~w}JHv^wImX^5pHls-yLashcsRCP7RE34;%RpYGy?hrblXe2aGT>Y%6BIDupp zU@DYf26`yC3&H)0I4Ym_mp_A4PfptUneapgAH(F4sqvbM+P=O9@jnaY=a0yLR{zdb zgIO40&8GWv?!~I}>Q=+?%0{yj!5nQoIK9FK>iIB_l5t$-+xX1c02RGF1Ui8%l!}BN z4z@ZG2-hS~T{jvOO&RfGwyzvvhp?!o?R0%O4B9fyRumR6K!GY8ZfzIE%sk9sy(VL5 zmL$;Z;~Fh%J#2(>Gvc6_<+(2CT2<)S3-jF&LBMxUH%c0RUJNZnWz+Y-@+C^{}D$D@NFSrN=#;nm(xA zd@wnYGWU|vR%dJCh63gaiLV}<9$%`L3>t(18kZCS*vBPUQ99U2C+MwbftWG>;neD^ z0G`N8j`Udab!c09?KswQ%y}K!Hj}PnuR~k3L=J6z{6NcRAI{;su6-auUB}*S(rov; z&G7Y!$*_FJ+D$j56-NBhTeG=fNIbROsbJPC(Cf^ONA^^78Ztm~voHFhf)^kD9wNOR zssU+8*8$@on^oC>glziDQE0juH=uFJ9>W($Dbjz)i`l|U&?tXqgiST=-WE02+7TBn ztYye}O2^rnxZKJ(`04Q#DM5z}8eyPWl7PUBA%|EH=9Wgsy5$`QA(#o$dUAVx9Abqi zACX{K=c%JnbAz|iH~}Ujg8zKVlF9t%*F39mJ40uVjXX5`h{d`fW(?^^#xq&xHCs*0 z%0{ypa3go*Jvexq3X*cS*fC!qtx15IULFFSKo&|xLb*`tRTltj5~x1)z=E}SFGEfg z>dAfDf5f3J8gr4W1E079chtT*J=(VCD=n@=+tLa-z?_|0vtcU+V{#qZ&bx>f-O$D- z{-r^{bAIz%-_qD+TqOWm$I4qd&mj_ z|J8}zo;q%$jJK&EA^n?hEi}GK5sLX}~HRb%8r4w2hi66Fnr`-#n~L ze^|S;aSGNdfF{HF-=Z_Mha?}gMa-wv0-7o$E{5};f+J>TUWs~1Hzf%)`?v%vN@=O* zMtFoG|Z^hWD7%mD8Ja05j70gr1j)@`3qxmjtISE-vzU zo=?VOa{hsDGQuhNYy^*%4|tSI1q9_$3f9mLE*^`}8xcbnNmU4oYWLL&x1kh17d@`DVM_%d|I09|>d_sc6%H zUC6BWx&KYu&Us-Z<4)CO2h$(cE^R!83N#tcJfYIijcOmXWfvn@K8J4+2emE$SnWipmbFx&~k+wK>v-jEc=^SoS?U4(|UbP zf_r-Tuk^xyVSdjy#{uwUmKSe`mn0+oPcmt|<6VmDBF(Bux!fTY=8Ic`F{Z%rG6HrpgF&0v3Sl%W~vetX?u(GF*l33yVg z+O;aFmscLATQm_sQ$-tB`jKQXyGJ%%uPmv_;P-;Qf0g)|rkZZ>+2o(i+NqV??&&4Z zAEc7+<>gnGx$@P57inHc>&=?$yj->attitvl&-iEr|a(_leAc#y^4RfHr}d&Y=E^W z^24}38=Zfd^+wW10tpZzSHZ^(sQNkAtZ2Xd-jqN0$eNOETt&p6{rNvp@2fZ3SOp7C z&`LGUJnn0k9vqEoft*!6ps7N2F;qC1nR!+93vO4E$zXw0RcL9Q)j9~KW2g=#h_8Y= zD4kU`lJ)6p5y@J|$75qTXFIPuZU3imHwgZ#Q1c9ga!r5~jg0r-iXSS-HxSJhyPEGh zB($^M+@WVQSs*LrX{pf7-hmqw$%S(}<8@V@$lx-$I&gL1y>05nFWdrL>gEZ81@Y89L=ci&S7pJvUat;Z9r%zPaLC%OkU`6FHzBi!TmAZD zx#-Y+0-wd6$^g!+u(H-it%JpEv17n$NRI(C>y1eudCCGQ^zgvb4RDaI2`j={{g78z zCfAX8Cil zs;B((hva#x9)!5a)q$%6@3RBp2syFYpOHD0wd3L|e|v??gZX1OhtGgwCLjFHMEU<| zq`gfA$trO1GXH-X@T~a~bH&VhWBz|p5`_HQk=7&{Scj5%)4MlLo!AB$L53^;RMAzlhNEO{SyG ze>f=KS_x>PdVArh^5pi6qlqtE-BE}N?_<25V0Q5BUfh@{fg1hy9`!H)Om2y34UmDP?T99X3SsIYEU{WU?eg= zB;)DPsn!R+qs)2g?95V|g(jUj`zD9BwY~Ge@=t%JRW_%ScfbgpHQ~P$!2!ls2FG4#P!h>{rI~KjR-KW9-6cbbV;Jmz(ob8crhBk z%3-b0zwFTVRMW>boR+%NmajGpuLeAc_gviPyml$QWP~NP0obYezDx2k{UD3S0D5cR zi~dT9*<5fvcaJ31d2y)p{_H?M1)OFlf&uA|<1pT)f&|6=PDpq0GI5!2(QaNn^z?EN zAbm!Q;w19%1uFXyL=pkOns}-onTF!UY)yYCcZ5H|z{?D0)9Hv|YH!=Jix6lq&bEyk z!*Dn~{3syKp4pTn(CpV9@o>rJkE76RKMun2^x0_eHF}bFRxrNE)qxjvKu^yXfnG4P z4mc>%N*OP%kRjimeCfQpbwZD-fYa>X~mc-e0rcAbr;$ zNJT;q52bEED? zx8ah(t|XnoDaZgTp|c=e{+y82ll!!YiBy1ok*fn&2R>p4!Vz-Xazw>d59d$3Ulr$Q z1+U$irI?k&gSz&tf|Nts5JPEiQ$d0VT)gCz?C=>Hp3JvMvug1&>&@)Y_J7BPlIx>6 zZY+tMi~CJ-@{f2)wudY3ra!D*+87(UzZ}rEhqkHqGOCCh_TbUtyI9$5bzB)v?qyIc z8uZeVbRV50xTI-*h1k$9VrBX^%inPjFhi5S*Ht>f%v5hLs?IB`^-bqh--x2ZG@flt z*7#WqgvfhXqgGu((gheqGK}l0{tOq2k)y2#rxVD+PUK*#6M=9|IBc??Tbn~0Kq+rDW4c=T9uR~kaG><#Xf_SIt8nv)EG^z%?su zLXfpSvJMur#f|~1Aw34ntT#;p$;-w6WPucV_$W-5Zh*_O-3u$iv*sbMuEvPwV?@eB zyh#_Ml-uzuygan1rtNfByDPTh0?!HQ0Fl)=Zrymn%sh-=Qj*S~hMZK8!~r^??6!wO z&w?n_K`KJBuOUy>gAf>ZtVKbOKq}i5zTIA|ixtLO5*L*q-wWK%=+rPX+PCu=W*> zLjp8cly$`FNb_?*S(0UD`5~MYc7OpEIxdFO(_PH;yn0DV0$nm_>tytf@sRLcc$~}M z5lIlDpt2#}>1%vQ#*8S%@)55(Ca)Y}b9j2@(6+uI(XJ7>Q8>=l#N8a)I-)HYX^??tNneYvnAJDp z0#goagq;M7|3Am-0B*P9F3-W-Q}BnhrW;>E|O-k*(k4Cf*N>5rNk zf|v>t8V4l++w4@BFVt(|p{AFEKqrueN#x@TRI*V#0$ff#FJbFJ>o>F%EEw@(wx&On zy9G$6f|nW2rqj{G)XqWZzHy%PxBOneipsirJJT(CpU=3p$tRA9aTEW5X_g z2FVBsC0<>XMSSKJ@y?h&Z4;jM{9#A7>xYpZ19&{Hivb?@I+4{|k1!|SiCkV}vM*_G zVN>BcY!!dWy+c%F#T7DWIqoK;^Wso>cwoYzTLDs-(H-I;@stK|@OHRu`YIw$bQ6~W zt06#!WY!y#K=PHsg&rP=x&aQ-HDN_a{~@og##t4NvPuSM9yVM*+LWYb-4=0y=Y({C zI$HtJU5r>TGvoV`l5_@$Fi9WcU??{u9*SB194tXd_BG_GdJy6wR|l>Ryw47VBjm(Z zr$^h&9oI@Zjpg!SPOA=|!NjatP_{wd;+MADpxI#7o5AU17VUp&doJ!bG4p7f+%KtQ zd$?lunh^%t_RzNbrR_3TD!&V7v(<4w!l7-5Z-y^Yjysos_XbM-UUn}BhEzZk)!Pe4 zl`q^c6f77=oiAK{yo(Ar!@U-F2!t6iH4_hY>`%IM1xXUpOSy(|ooLC3U`RueIx0Ol zoj?|LA_rTQhzOyZ5DwdQXe$jXUG!{N0H^0wohmdOFletUsyYeHd@5#jMh}oE^58HF z;++nHJ-wK5raJh=_bR!D4OIwkd`QMa+s=L@2yBx%jh&rYc4i|~BYTrWTN7h^`?ZLt zRX%ZOI}T)|h#RFmq%;a!xxa^0t2m&6K5^m1O za2n{@q3s-~(MWuu*P(6GoQr*j9jH5lcbMFNTuOR#aq!{p9;vkR;?wu{0uz8X+%cSs z1f)NX!@&VTOa)2F{Z4?XiOYPUUK0;By&MEOfh&3ZjUhBXz_ltFtQN>-Flu%R2DLoAhNtKP`|$<#;-<`2lh+1GpcO&Z}D|#w#1lu#^s= zDfHw5ICwkU^7*!3?3k~I@0!edV-iRpQn=8=16nsgq)<)>D?)=F@?wn+=(8#w8DYtQ zJ_4R%NX@z}A*r@k2dK040MK2GLYSF{G0|3W(I5j|Cy&m+t)N5~zzF4L#6vO5pMzCB zxlfC(NChAlxjJxl;3IY*93iJIM}1tUeLXa9Jfrw4pyy&hiyTT-W? zcNr|PM49GSh%@wy2uu)}jyC@~A)B|Iw^jn0sNP;Us(j&2J)S$Sy6Y7caPWQtcq}qq ze3Rw7*-OpD!=!kd3X(3sAd+ERCwej>7}8Lrj!F+sCy<4m$iY@6B0}gUgu`|n+DgMp z7d;ym!0CBarwR=R4BG38s!l@vjwtJbOtJw?EAqI(EQohH2&SW$ai%)>9Y<9)Y@nKq zo@dX^6zhezV~R0MTi&R?WO1s?uGpqmJw_6&E)`9W#Y??uBq?TBp@$rhyDB}b>mae! zRWxisg&GDd!ccW3{Zn32eD!|C2n!lgs3TSjW$hk$7gc>bKs+QJ;PAb3xZ+$fWzgYY z6tEfws=@$vR+7%3sk1_KoSB(?Tgr@c#iPr=j%-!QG>O5YH}*YmP{ zarP9#%Ta&@L+>{ZZ5C*~Vz~4e??YFRA^5%-$MuX;K`H7PJm#yHPG1s8jxN2#%jMVf zGH$>lagQSa?GY~zpUH>&s6`bIjj*mJg0R!IW{1d7Aq<2QQj>s}>A8*@hypVays{*d zK~pHBcZ}33^zbm*2zOv)0S1fS?6hyy?#9$1jyFJWk1AB z&ntp0nK3j=5@_~o309P)rN79R3Q;%?(&f(}?Vxm4Co*`aCV{oQ(*$E$@z?~*cpE5(gmgoU*cm6Q$KFew(@4WbPtsBhsZ>sK)(hT=2a-;GNZv5-6 zq(o7X8^>k7Kw6V&Z*&3~L@E+`+<>hUSqFqx;y(BLN!Iwv5jNGdo#t=d%>NtbsZwQ} z2q?9q3KO^cNgM?CbHR$$7B9562NWphdLTJ?W(L)Nm!3&%MlgZ*PI^Fc*b;RPT$2c93iuET6MU5 z3vfB+%d*W&s6}XRQ$d39?7}#1&36;DsAs(yoK8wby9S(!`$eoA+9vl)D%r~0*Yu~> z{?G_-PB>FWQv0AS%Y>8in^@RvbzB)vzK2k(H0YHj**;2!D=P7?LtE3OKg|6*y!BlA z-eGcYoYH5m9j$$<8LFPRm|}R8d5$WcSCCUYWI8WLGc1dGzhQPf)tznwh6}9mK6C}y zlkb~x+!~OEgMbvxdgEZxfQU#aj}uHHjSD~qguM??KH}vG2(MWcj6#P2BWQX!qhXVh zgP%~S>bOBaB6UiRv(<3}A&|TXo|&{7IwB7k^zbm#K?0p;gOUuaRnuzv z<p;sb3l55*erIkp3Z|Qjl2zOv(-syoV>}h(Y)xGD!@*C_D}pTavxp( z3{pM0Pdg4t#sPtd@tSj%(a&>c*7a`H$IQPA{O56JnFk+9&j1J z{g8BCn=?xRhZ)wpAvA?Ia(8g>HWef#M3K{HrT3(a7xQ)bcJmTuz0nC|6e(Qj)=v<%*aDiK-(anWGd|!kH0IFukx6Ty zS&~4b^51p7Zy zQ(YE>n2Gk5U`=ByD_%M-^Cc5e=NI6r@i>75;DJ&*3@-;oNu)wSJR+eAAMlb>pX&XJ z5f(HgUPr7J%Gy2hE-Lg2vKi?B(enTY-NlM2BMtweaI+{%9&k4+NoUa1sZjKdnHcqh z!zO>IBUml1VWmn2^JumlQL%k;{zS_K(;WnU7vpe*%*tuo;qooO<(MzaHZP&pqrFW9 z3C6Pvv2tje+%KtQD{o)ZpIZAvBdiZkzexrHp6;dg zL0iOpN;^PZg`Gxx55Y_t^vaTS2Gh)yLgHVCwyG`H&DDX=+W}uoSDOnwd6O2;tNMtm zE*;5KZ8_H?$hc7Jdwd=a&_S9z)$G_-^80}j%SK;z8Ua#AD$j<(0DXe{|^$0e}k_+ zt-3=>Gu*GpjmkSXcz-RoQbD?dD01Vttg^UnUIm$6cR1(-vQR1#dfZ^E6M=9|ByMwj zw|2-{@nW{7Ka}53fYAhAHwaKo+v(Y%Eg_bS1vFKdxZQE4Ika7d66K~OlYw|G=^a|3 zd}rLCu(O~GQazhd7b}2dqPG`yV^jB}t@W7iyz2UKYR@x9)lye)&9+8Ykj&~%L%j5c zsODQi7aZWK*EoTM-~qF10L+#oR4w;VRW#+0ZS~gu>8h9lwF*Ilcg?33%Gx~~8&wN6 z(BmT<4~Yv>xAK2rCQ_%t|sDSoh(*nHcp$(;qnH?XV$}yiop_%=%MZ3JO8o24*7WHQbN>!+J(s?BnA{tu^qFf%Ykzo#`V(WM zHy70-J+;qHKkXGAUHq?HSQgEG16u+oR%a*|*u!}13NjQEAIJ4);#C`LTdLPMf#l%Q zOT1iuO)ujHP`zRhw{Emn#?*D$>i&2dq6*%x81d58L=Sel*6b2cY<#0ilI2x5f#Ym- z+(0Z8D}q;+)b)`;=ZwS`dU)7w@)xu6CAOKgYTrDMeQB-^e69}EMdJl^KeAdq9S-Y) z0{~+_REhNpOvfx)vqgvYa|TG!z$`|lf`qVH>>hd!)ThX-N=B=X#gMYd*SGPK{xkpD^fT99X5>$qp6$xB|c}Tf3hfcgWlCK=$8-my~)-28k)sBa^hzpMm zv4EzE8{AbFU3|c!Mc1LN^cQ;vxn0t_9fDVVB%a#yEWx34)yQmX5Ukl=R93t&yzs2~ zR?r0pxau`dAR&0b>>2>GB?(o_H*ghAIb>VCb$_}lra-Mi(BNJ3sfDt3564E;LJj#2 z&{ToAt~jIr@kT~kkMA&q6$S`qC7BGY`|#dO4Ef+-H{MXh1_R0Cv zFgqi>4sE3&at!@l1mOsoHK*31UeYh3b%zsnPh})!M!#l+3z}5(P0|qXbT74EzqCEx z;Lx_dho$!)iTV$atXda8K)$a`@iW(6`siQT&Wa`5iXzdQiy9J7?NjgZ&dU|-_=-_9 z`wf7@%+q?s04XMl0InGwc4Fp2+B6w!fYUqeO%s?VA@{q~#V@}8; zw<8Bg@LrSu!MvWRJ^WzE_vZdHW+>JLhuRskE`KMw zV!Z-=%xW@QbZ9?k>Ucm2du1$ zsZ+i~JehB_*k9A$Abp9Jo)c1$(BlStoyb0Dw2-*XZ!S;xi5F`${h|DR0*of`xH1Ic{ZycV;|1GNDk6-FTT7)yIyrNOy z{^;)^`}m_ses%dafyXN}KPJrb)yqGrG~T9yWcClS9mhSGuh=c=us6{|(nkUbLqy>> zK^!+gv`gx^Jww};)}oYbe@P>sF4G^@jy4vf-7C2jo4+4@al+tX`+gFQX6K z0j%lylX+y3je zAB)FPL>`Jn#tmo;W^D5&3^SXNy!(!&?N5u;wsZv4$~zp7bdFlS4AB$doOY?t{57$s6G=&Phz++DbMlb-I; zDrBEDUE;1JL~`otynN0vJmo`jNMkE;2AP^J*DNlR`9#0beBchtdE=Y%s1VvuQaf;-k1aukW`fEyaDT&qRnv= zQUb~YE1DH;vrTq47`O5ylQu%VCirsX4y)YOB)dV7NLzax;8xXGjada~d#0{08fkM$tyH=+FMtU%zU*S#%=Pg zmJ4py8>BA@Bm{`I4Om2@Do!d~(l)tY(vodl7vV4I&8k>}MP;r<(8_SuH3Z<h~mtM-X7!)Tq^5(4f^6th; zd86iUfdq-cfI5X4lFP((Ca>~6{E{59*1Ngx4A;X?J3x-RXf zf+Oy8UN;FL&6rgoc1tQ~dN|uoceP90C9Wv>NK0NWN=>#p?p@r(Oa#wNS`A%GG8r)B zijnw2j~lFYkUKHDAoOfU9ai+Zn5zR<2R>j2u#ft^q#js7v&o}u#&lkume_eX2(Whm zcr~N_oT+;l-<>PEkT=qj+q{o+FD<(i`pjlEk>MJnlq@_ZSNf4XA znBnsX(5w~27r8ocb>KsGVEp7NA1`7-{!~$1R~^jlIuRf@D;vz{4yz%Nb(N{fBgj;c zoOg>I1JZC95<(A3F9!kAZ$YGRq4Eu1fD0PXxx%)`MBN)~rk zFuusufme0F{{WEt0pHK*>W`4>EK%7$r#PO&RVXVAHi1QI`B%aFExncd~j z2`LB(z55$aZAiQuT#+%JZ0=gqDc^YkG&(@#;fwc^+4D?+8-*Z5k@40QBo~)n^5sEw z+?p@cYvPK!dW{oER-u?4y9U5)O*lCZq`x+Y)`8Mn_ou7k6li&Oa5!r|QfR2PM>b!g z!tI=R?j@s*&ep_@mgz$OBj?g>y!7}M+3pn$LPNTe9Q@hG9bVL%i4i3_h%Xpj{=-4( ztcr7b4S=1U9-V6ajd(b7`bxq0v`U*fTCW%&MHB69Do79_+8)}5WWBv+y+M^VT6b_6 zp@$6!+nC9KXLa{t9tzpK+H55~E0;DtG{U-?w$okh68F@sSBJK#K$ESGduIz^CIZZi zmz1P4@C>D6E&>4_c`J2Zo-k*2JTzW1K>B~VPm>_Jf{ela zjsqmd5k&<^PZEq+^#Y8CKcgK-7X1q}tH%w1=bF@+^2jvoveo?wjQPw6n`*c>O`tx# zG_^NvNt)&5s2yi(;<6voB0atYTQLF31RY@-M;gqT+|oKj<7Nc5tNeX6B!De<*h=6sv=m8P2BD(LrjC z)W=&6g2fu#2g=6THgR1vWfy(CNjfvWQL?`_C3zsQUwg#E!A9up$*uBFJ`7SlSya1q zOSac_b>Qm2hwOmE3Nbm-3#W?uE>__v4&OxJ^SYZ>lf0go!!;c5aqSVW5%tCD&m)Ei z*}xnQqJpGyT)f6{nQwi9XT-_Nq&J62AbDre|8pGQ1Zv!Xb8+pV?Kv-d*!YqWHiwU2 zq&xv{Yu9aYV!EUqpsvDpQJ(7u%=Ekp%TS`+m83H`wROld^Uvc5v^GIxI@Au|Fp z)Q7fS@-DQz8|3lMc(S?E#*@3w3!u>)Di2S*pD+Ofq-Th)M#fuLkjxxyJvbe==1apB zlaFO9p80MmwWNEtItf05z&5bW(PJ z4lX*bFVebxiJ2Z>_-=@X-es@>D{3<_qEH9%$}HZvA{Y*eu2OX~09GGSMJzdgDzNL< z8`bdoO2PQFsxzbgoB>ia(B7tk1R$dAq3t|ctC{r%Rn}84|MHqE)6kniawUn!OP9)|EDR|h_M2mYG(M191bXn%UV2HNS(MU_7S*?D=wk6`v`yB@x9XCLFl3+}$*EoTM=F>~Oe11(Y;|5T@V(MH%`YU7V zx@>iS0u7%TVN*@Jw`I*95fGR0R*a)^oUMt=en^Y-_!4Zz1SkzOOX~W#0)tLkD)g8H zvH6P`KT>8qYlR>exjJxl;IHd|dp`8+!2w8r3YqIFybilg1i&;aTM7&_y2ENnWL-TD z2R*z^1xdME>==-SfE*GJDZLy7I)N;NNGjtek^mPp;GwvDVn5`?Y~kgR0p+d;L=N?Y zz^i)#wJDj}p{nCHfllH;-8fql7hSBInr2=_Bu}&zvneToq_8k!$Q7i65;Qhs9E4yV z4lt{8J2`e%`5&Oc<04lFt`59K2TmU6XPZITzibSsUU$kE?(of%y$`)%2{vp>0~ySiZ%@(^pdfMwo79w^SYtseGxIGD zZA}7rH@G5}ce8Bnys;kNTCX^QazW*BkN1<_^YBe3P9rJ^QK!8nn5$lu^$_Z~%$H2{ z9dNG5s_{61WEG03xk8n zX6*q`MTK5%;5$GE2OZZJX~h&XHNLPaw)0mFy~&`dbB<_dX0+5neDUq_w}X<+I;-NG zUISpeBPyIbRlMrcaW_if^_2pB%6Ercn|WHV7$8Lx?QJSZ5F+YM$>4cQM)^YZayzE8 z-k{1Ftvk4kc;f~<61N`TJ>qqfS|q($6%UQDuBPpDSG&ZmZwJX}Kwo=k`;wA$zrrBt zUWEB2GxWv3v^`Z;pVTF}I&gL1uj{~_`x)%M`iJ`?@9e-z;N>a6*1|!6$3K4bWjSNJ-G?y;lRPFo*eaBC5$g}b>Qm2N9=$*Tu%Fk zj`Y4u<>3gK{U!o`_{@$EPvw|TtXI^R73$BlGKXwv4hK;|QaLVO<7{7My)g+S zoGjY^(smm%8+^n=+gSUcE!%p(h=rMt=44fdQ=aSb0iW6TbZGl$oT1n=_%K?ktx<3`9 zRN;rAJ0Z~ET}P~rG;0rVE-Lh@1Jr^J&_S=``Xa5EVy4CyR>gMys-ZU-G7Voi(6ApRHzVU9HvekY4vMt`)uhdM$Gj1 z1~{)tgieODl03YTffNeqn7AlThKZKzWd1N~JvnJH5l$r_VJ~`h;OfA8=zuJWITweO zVRkTiD&g;974rJE{p-MDhT}c)UQ%Bc)IZY_8M3809J~%~OaIUZ92chb+hxTMjj%a< z{8B~+>6syUrEAnbQP9Rx@Vk$YsyI}(= z6zqrO7fMU|=e!)e=&k!xK}r>#L6!{A;9Ww>L&x<6reeAx z(Blg$sHQ|icO^ME7PF?#DWJS**okPVgZSdxR5!NCL5;m?g>YrfA>$q%odON z(qqL4GQGwLWC-MRY#Oi%M_u4T#r-aIb4Ie|=Z}|+u-W$x|H-A)uE%AbX{)h-rV2BS zzKg4vnei3%l5R>8X!dalR+KU^{BL4xg3LarbWx?7d(AdhZFoVSb;v zcC__p%utV5c$C$LJD%EHHdaI3dGRq3;073nTfJitDU@Rps#tq_DEKfw4iU{hCo$gu z-!+-_236K*{2VKvXOBZ7=mv=NR9tSf9`a(19zkYRJTk(P0eu8K#gIWaZNX?Ii}}?7 z>TCl%br+)$W)Au%CT)Q0CIb(%HIZ6{+D}ol{5e<$Jvr(zBC1@+zO*my0B6LDaWA+} z+X1}0%?ioK)TzFBT5VR70K?9V0CT3UIL2F7kO8=4VHFF2g{Q~uNiyq=gFmCy1yWR8 zC`}@#BFoe32&c?p)Mcyt@rQ9=9|>-~ z0vB5R7V8c){ad|ib|M&m)g`|T6K_*Nf`X|2*iFZk9}=F3noMr6n^nnZ@q;W17drb( zuRvTAiTm8|Cz-A359QB{uo=##(|zqtTh?_(?VT3mY)#zmCvj$ciMC?U2m{TMZt!Kl zR#?zUONGvUvDxL%Al0)ObxEbkAb`hXo$oh%3dT;MaTu}IOF*M7RA$Ga_6&Xm*~ywr zl=l%}%8g08(-_BPzGS*^tzgm{`*lNd`MvmsLelH70jJ_Rg80In@;Z<$y+d&pc?BtL zZ2Ahr5pfU}Z%>mzjy|)o1>(mYIAQg1 zxYcIW9qJJYRj9o^6iucg;%3>w2A&L94Ph`OK&IDt+nZhG`6zVKfQRC8qxFy%vlXvd z6;0oA3Bwnl1t|G2@r||A3<_0fEaq$nsIwIiGmW^TbU?=VzN93bfkZ%{2|;|BApF=6 zU_Z;BgH=5_>e2O7J#9)7ua&)==a{`5c?VeAwX=M!{<*l%d2KQe8~u-}-H!r1?jIg^ z*?P#Dv^D%W2ID6eA5*82@U+^jCIN<>83E=@U2%-Jt{?-*qG!Gvk?&;uJjzI;pB~X- zoIrAQ=_Ot+zor+xW(UeoFq|pRczFiU{i$+PLAwp-!A{qj9e^4YBy&<1q;a-7 zZXgg^B!X9#)QviW&KZd>^zg9Vmwa&|h~UG~KR-ampZVbOGuK|G=1-ZS z<3lq3)l7ftU1HCi0vB3yB&HA7#0*Q(Iuwwi(br-q-ll@2h>Qs$S?>(G|}NIkY~yyIvZTUpF>k7mP@s|uObV91`h8jll5 z7?`A?;=xNNQlYA0$2m%T;ZAu;w)76gS>zR@RB>u8I0UVDdqBqbDmm6}dVpRvb_3Q^ z7QkT$9d3~|lC799^Duj5Nh*VY02_kD>Qd$4u*o0lXk1HcSfo;ezvM{oo8bAwXZDK- z+~G2N9oimwWF9(xP!>z@zf+;f|+v^T?j}sBQ`1#m7W|6ILIGTWwa|p&pS?h1%Og(PSzjel6!<15XC5 zhA$A$olS^k`m)$=$UVNcaV z>x;QMaCP8ab^z;xULj+qT>egE?P;@FO#%!%GXl(+y5bmbT|owrMbCUUB1QRml#yoE z8wX=Xs|%#4_&6|2`zTB&lc(1aI@LnZWvlz+>54Y;e#MBFegZ|0MeU7h1)X)>)5cVx z;|AivOa!ki$z;HgD@NiAJv^*8`HPu)+XeX6Z43n$b9LbAz{l&r_>hbzqvr~;2Z4bL z?fA6qYk{q1C&IkRq3wyd*Dq~TlQt)u$wWp|C}vhtZLd2m#`AGJjq1?oLtBC^nN3MI zICE||TK-u<6pn**ht3Ql2nnyVDnasV0FTEy-*3&4QDZ$}t(SmCbEwRYL+=?T zs9Fq!B-GvkcHEe>JB@MNnlF6UWY!z(>?DB%(u>9oSO+XxM!v^aR6tk&|Sm?h^8>}@Tv+37Q{g}E6HTAK&mP|Go#!=x5*#s zXxvm#S)>B2NUlTM+KUMnj*vCqL@#G^gTDhTzc&3MwhjZQPpw6}q=5_7b!e-*_+9!Y zLxTp%z=(QD&3Wo|XuIsz4=R7g?-+kD#ee;v|3`NJ%(Y|Oe#Q*-h}AvZ>r;C_i?A__ zhVbHJBEZ?~H>}w{1Ri+VPwwU* zB6rGMd$C48k;_<}!UkG^F{(M5PItBYQ@}Go-SeQ$9B#Rz6amJU>J_sqNoTM^syc}; z)P7v(WH;Y$E|eybQJ7BFJ+V8Bk)X>~_s7%cnGrtoaBzsww1qKe z4B8Xb<7{=@Ko}G&f>)N*^^rm6jKmjuc-U_87c3p4u-y<@2Eix{Emw6}+%$y7w#LOIyLlL4zC42ERZ8?*mTzOs=QdITWq z26#x4vY`Uu0z{qByZq(4EnVQ0v;#Vp>6Jmv_ojq7Bp~9 z?o^HE<8^4u1{LO)vOW2G$hRI3^Z2m#MSteC^K#rD{pvEn??;vdd}9M}CtoO>3G%;a zWW03++3LT=b{x0nD|Smd>y4z31QLdbb`4m@6XidJk+#YGl1jF6o_Xm0)Y=~!VW43+ z|IG|WwPREp70qW%2WYA=(};Uem`Q_PS(3?MmbsEk{C|kl>%Pf!wD}JQC0Hu~z35Nr z!1c-Gr?mNV1@S01KWAN2JD-@1Y|M6ECcUHwIXrP5`+zgv4J?zfj@8|QNxfC%u45e6ED^Pf43 zICKJ@?xprYTeA7;r2{lom}!&?Yo@I<=%GowDamB8%APujpFhv}C{CZ5QnH);>x2}9 z=;LjbQ6|^uqkfXz#NZ75TQX|B{woRoC;s;}F>!S9=1ih^-SR8{Fc$9CBqQCE%`Lse zD+lTRoqp2fqHd9y#AUw8czfMpL9ZJGI)N;NsN^}4X=AbPFWd7O%>MHa!YGx+P%)FWhYBal&bOw#%oW;!a)j|is+n~$8PDq*C z5uvlHs5h`!DY!m+YDuyq3<+z?iT^f%^E+iY(WxwP>VDmr$DF{)`hU27h+WgDXd z)K!?cwI47uJH>cG{3_t}AfwD6F2 z%(8CsD4H^z*Y7mN-Up9+4>`cA8SUpx-9>5d0GGPWI7Gy4hKCJ29d1vOS#OYjXkerw zq5NLcG@x;rv#iL^ZF-H(Ho(Nn@zJOU7)cz2dN|W(oq9>lgSJ$o3CHbVfPu+Y$Mr;k znFyYlv>LjWWHMmL6(jM59uC$zh$luDgr4csrChL*+lyWuxH|9=JAik0w?bn1lNEGX zTA;RjrkK@axad@O;tZI&;+P=1g6zp9%K=Eo4Uit^9yqh!c)&1PT_8mjzoaQf4z@_7 zae-n$YVV)$3Ix>ssq$w=*i@q$=n+vU;?{A4encFF<7`b_^rL?BsK>W9j<7uwATrP_ z$&5Nf_DEHNme#M5CP4^hf^c`3A+1%7b8%M(t`2;>4w%2=@kJ_dhZA;BJFmz7xX3<0 zwD_HCkEEvmUpf5YiSu2!aD>d7|GNn0D|SmN$n+W~kTK-nj%*sRj3-LZ=M>Tx#ga<4 z_?H%G{m#z-k#|)r(L@O}`P)VER1xrOCbjEv5ricT7ErP^aWS0V1We4#_=uD6oonVlyr>X8wtsTvv-HH*k;vK5# zpmqmsqpJ2}E>yA3)b&|l|?E< zJ#Jv_5mi97*1c^tc0B zAKJQgKxkRf*CKexi(_)rXp~DE9~t30u(~tWB$t|XTRdFWqyyAFzr$O1F$!UZ2EDW- zok8=^m{%h4h5luSwtk-D>oj$#c^&3Cq*DvVIjD!Mo{RgO*CsK)(f_FW)O`QZAll#S z+n3zcC*Mopeh?(Uzk9ep@>X(8LT?44_{@%n-b zdV>iW8kj8l-}U>=SpyoEIm?Rt+@{yqYy(WJT-w+p3?vRRJ)Fl88e3C)t7@#qEEgp4 zGTG|5o**z20mhf=72}}P(6uC!!3v7H6u+6F$KjyTK|G|~5sMk;b~5nkC0|HIZZCRu z;Of9f>;TrM?!m$3??h37Ht_Nkm?dkr=+J)7)D_1B(G_F>h-Qmjm`53DX1(z+X0*CM zimF>q(ST8yPKLNq{)AT`obFGRKQqE+IEN1hkH}41n9GcDRE)DVaoG=Pk)BrsTQLDj z1I?1UQD1>UCoL6vOoG__#f-bdjAyM7X^Mn+BYVODm+$ z`*EH{D%s+=aC>O$R$$bb!$&?%FnzL})UL;croi%?9&~C*DTJa9mv=++R9kh+A z+K;(V#X4IL1+vC)*13sd#lI>l;EeN7%u4F|I0I_rW?~$N4kG`Cpr(l+C@&&aRl~xn z2D*XOM^p!Y3|lQ1Tz3#C=Xb{)Ui!2xU}$Kzz!sGt)ztLipq$?&`&)X+*ElZo6|*&+ z^~NNSK%^p}lLoBgi579&-&~4nL2b4-*jl*^!UC$Q(6KutXlvW)uJ&8?-g6zG&h`!j zJ)BVpv#&+}(voxrNMKDQzRJ`PKtRmy;a;EG`>Y&I;8pjtXLdaF zUNUvZrGo@`HJb|&akK1U15bzBlVsK#v;R(LQn*n25yYPinax#;5U;ng?xZti~)ifdXi<)p0#RU?zfRCas39C7BEua>Yn|p@)OD4&sT?1)*o% zUaNgGJul|!z}0~d)&ab`yA=}4pRAzEssgp}@)VfWWVq;5ce)K2AVrM{qASRrT(TU1 zbld_@ z4f+vr6pphsanX;uxzXcW8%Nll2@n}*mSjeqA$z1MK}%(ZPM_QaGeJ1FGo-buaW3xa zz}10|*MZHU?YV-!h?zTFW;bV+Vus^A@m|vFm$u9HQ0Wh!`Ll<%bX+p#@KK&B@v%bo zkkQnKwo6!12BMhxXyP6rdwdf=Db^gyi+V{7^d^HPlqh9hJ8T)!lRLBW3*}k<-5V$& zc2!E4MDZj>){J-jmW@trH%e;RzIX{}6amm|24Lp0Psp#kmnIYCZ7WDP90K`0OtmMA8WoE;F*)p$2-z^S+%Slnuz@{;1K_bWzN&`Jt{nKdKL+8wkdE?Qna zMqH>uovnvLcd=q(XvDuLnyFH8JI+HgD+$mrLs}h*79cT4sRy^oAL?jaOKaFVp8+Ln`&GU!0ej76xu%fTU z+!wNWwb|ZaZ{^a)M@IM#tnQ38$z{-WTLN6xqyyC1-r;@n(Do%I=?vUD|Du(a3cU_( z&vfmwxjOJUIuKB1_i#V8V8Pje+6`e8pV{%yd&v}}5c5K6ct!_!HJb|&akK1U15bzB zlVsK#lR!etqU)EosTCo;oV~aS4Dc{LA5SChC_TKMnY0?Z=4~=Sgf&U=n;Ci>4)!{T zhm`q?8RvE~@aZLANJVZ>P{cc7`Me3o?0JYMJ>8RjKkD{e+~>S@xxVoT`(6Au(7!=R zSfbw`*{2|}K6MWcyp>L68yFd0o&vLE4Hup2PPYM5R~!>WSCBm+nk{xUAPolrDVp`h z!=eEZk0d54j=h6v4^&)c0DdF%9IZlP_i{~F`VB7NX*Rm zih4;6^d^HPlqg-AnSUIA{V#1#Z8wfzC2yHtaqw_KWi|ttg)SQfn662aiSo8zdLsYFS4*P1$@2Eh-EabQ2P)TxaW{(9@`5qA2k%ir16` zXk^gTiIhgf%*^9}x4c7;S(m>Zl#Jb3)rdE+`iSbdera12V4d*2X86TOv*;xjuQdM}xR6k-G&B*3fgC=L;Ev+Q95Plwx+WY!yOctQh{Mc1Ki z>PXv`rbA|7f4af8t_Qm7zGV_#48{&1Sm`po4=TGcbMI*6|gRHb>Qm2hwQ*h zj`Y4r>F#iu-JDs98IJeFdr9Bq&m%7*iqaoGvt5;g)5+`5Hf;^^W1>CJl~&H^b!dyu z$U7t5ev@v=1eE(k@g&A$y>11{V_h~Otw+yWF9D5~P_6bnp$8mDnoPz!4sJ}^oyIsW z^CdF~SVfcGV2NT2lY@g7x*G3>4LB9o1B+jhobr+r>+1cA5f-$PLSSaiNV9eaZHbG) zsvaXQRH4q+L!rA^F)=ja|H!1((1H--4Ksi+s#lkpnaAN_y~!WyXk1Hc*k)?4qQ73J z(+&vmNSAA6+WT+-YZ_bGVO$T7gNz8qw7^y40JCn8*mVbs$+&r{S4X+BMyjB+%^R8ZB!vGmrY0lT46V{=-4(syvawJ2eTvzSG2- zwBn)dr@cON?PbtE!VEn-J=J~#OAbHv)xF>X&Qa&V;SH>}M_E^QT;sT0+8v;lBtT0q z4}ne~3uRFeis!WKh2&$W1HzI7YSAD^!Ga0UF~yqxu^o#tpBx-EW! zsKrcToUMbk9?rD6DVNzv6AkJi*_0IE1hcl#AzTuAXoPkjnP&MTNJU6Md|QNccU@Np zt`1xsIMIRe%Esm71VX4bddc!o@cGs*S>w2;R?ZqvKRu#+oIrArii92^N#kV_DZn{rMB66XsukTP|mZP@iVaPbXU8?ok1!&+EW2_wgJXn7h&e0KlPM_?XD!90h~5O z;tQSp_RJBc3qsH1=&b1V@t8l}f6BgT{rk`MwHbcq+R@1mFhkFd`PX6?FroFI;yed} zpKC>9<30FomHn}siF-d6QLN05yJiU_^Ba7G&i>LX%+{p)jo{iG+Adq&pF2V1=YC!@)t8s zt>h*}u}Wb5Orkdf0inyD2fLL`IzWh4+M9cc<{4MnVO%ev$cSJ}3tTl0FzdE#gT1hL zsYFBwoC)DZ8(Xb&UI&V&w*&m7irUvn8d(f9Uu^1#xgyA~Xovnh5E_Fy+XLzBF_qX12@ZI}NTw zTef1rxWi>B4;!yT+d-G2$egFjniJo0neF;GMp4r1&{nmh-h^`tX?6GuxX*lW`I&1k zQ|%+n(6es}wco&#m&bfu=T>NrN)HZiV7)!cy1L^U$7R53Nc5fw5Yfv+pcBYKSyY7L z$!EWMekd+CS`T?KTX+Q|O}Q@ukwZNp@N!V2t@Zz%GRdW8-4=0y=Y&|m0K0KqZvVwh z??gokj0qV-vm^n58ADFcve-i@wEM`Ur(@j)Bgk=7PmX%E0{VL)9J8OE5Zm>WBR?1S zIj>D=ZlnKE^{M&(qd~O4)3-0VlQrojU{8V6e=Yfx`!i0Ma1Oq9(K!Jbs*U#cP&9oN z(QL6h_0+2I^wT5C#|b0{nWI9FkfiZ44Jg9RD=TsvL#4LadT6a&s!-0eo6QqDyGhNU zeug!Yb3qa>oo#?m*F~5)=pR}CcO~fz5MVv(y^&dYs+%wTU2kjZ} zkL~lBYsbjF)eLoqkN^9r*Vhs)U_#?i>jvqmRB-MUZMC;K=F3<(`Qu+GHF56@h!vIh zL#8{v8z+!_ZvYTFJG6ZyZv1G2wmsr?M<%mlP`2^Z8ZK!1@G*v9r~BHW;&YS<4H(Ri z3TS$+<4QkxoGAhf%u7l#8Jt>*5npEL?9c2a?}+s%@5AA?X>4VOaXmZ^G9nn$0#}U#%+N-M+eA8%hf*aXLg*$$Hl6Y%$vLkB z#namXeo_Szo8%y3p!srNN6d*qq^MnJQH91}&h~)13J=$kY^Xpm)AQ;zC8-Qt4Y}X~ zbkYfaX!1}@@)vcT+tEJ2ClaJm1wV(Ar~7qi+pIpj);rF=>zB6WI|G?UU!-;JaGBNf zO0;Ww9onw@b7`**Tpf5p2kJBY1z=|&)PCdeaKY2$R5p%bjJMt%Wvja58pmb8YDn~+ z2@uiCLxA*K5Qyp{)xlOL(z?K)CxIetP#^MQw(t@(%6)+sdAXat!plLAYGm_Xq^5Sn z6&H9;hy@I=8^`7LU(EClUZlX7kTEn%5)ha%b>Qm2)q!aT#w**Y6%3f6V(TT#Lm_K@ycN-Gu{-tD0&FBeu3qB=l7mzv^ax2B zFVlb`+`O_Pw=q;|o2`e|${+fcWAnt$A*5zdiHq=S(mic-wgKK<7h&e0=QA7kE3zv| zXRt!5I*BjzrH8gP%*9*US(;1>1{3w?MRg^Su7)fOM~qXL?2b==wyn2F$(C7BGi zB_sohFZ8&>ZIi#4RfOm#Me%4?c5J}>8AR_m0zz_YbRq>HL`&oC;M~mZ$`0dtc$_5# zu6hMHc3ZZ=URbv(tlC`;LQ9QjJ6tgPCZ%OsW7yHZT;TkU)%|Tllt0CJ1 z>MA_EN*6=LfEoN7MKzgmyOMMUGZZBcxRXxsLz9PMlE0|y+>Z7EK9L}mD)>2^KYR|P z57$DQ*)EaqG`N0g%T^2+cepIQerY>sPAhufhqnGWzDTw*q;mi9Xei6oyH5Nw|Jw93 z*Ip*&N0^~!-#&W3;oW*t1w{Bqwx?loy^zslO{Thv5Im=hibq}c% z0l=CBs=3{zWX^~evo-yp+|Mz34ZIvQs77zzWi$tE=>d(z0tV>EaoGRTpgHpV7#(%Ihp!ZMX0P^vOE;B z*2h~B%@(`%@d)n~>7E|r1QLW)B=iUXHVuGuO<0jz+i9)M)qE&5$@9W-+`w#i@2Dnj&=qUxb7zZbGx#`xE>y7Nr9_g z0gm04t=p8>{kl%%RAkw7@=KCaUI&V&w}acPic_dS^Tqgg`Z#i|{TQ^Ru^O^HpsvEh zt8_6`44A>cQB;!|w<}3!Fhf!DfV(=cbr5_}DQ3}nF({oCz<(a`htI*TLt6~onbteJ z)6=)pWVep)aM|WMwB5AoeIMG!Pw+6#$-ur>bZq}D{{X~x5{HohIpkE}RNz!#Sb_e|wzY!+(`9VEWmyPh zulKjY8f|u4Pc6WD0_1Gf44A+7oNE=1W5Zx&DN zXeT*?+96m+fb!(2)6qJZG*yI}ft*bM?q_6`l8#`8lx5;y=!1v0M!ukmi2e>2LXq1; zPX$f|P6b94_?iR`yATewZX@*`ALm|PR9Wjo$@pmGd12r0y@x;MHOF`T0IWy20Y&JK za%gLP-jcIWPJ)-MF3gixgH=`Y#i3`lu2$Zn{0=P*?V0@upgkvYSS$3pLti_QaCsaH zHOsXfI-y1jST7_$`-uEy&~N@FH7I{~k-PQc*hXF2+M@sb$q>h~sp$LtFEzIYK+abE z00Nd|^lt%nXq&4*L_DSc6seR=?xz&d{t{+BTvdIVERxpZ6=;&pzeHWY!@cAVT8cz{ zNE<+%h4_^!A~pZ<#Y9Lc5GH2mrWCAF(h-!FMlaP`hNc%Jr-|@ct3mrGOY#y1bfNoU*X32|AkJm4J1g{SM0Qm z*F)LX7C{5i`cBnFgQ`AF7Ex*S0yN1ccJJ0333#xV+(AoG5KpfLP-h{2F`fU7SjD7Q z>uTysgsYTv1Y$L%vM^kj@wgf*C!_eglhR~4_5B{g8$kb>X!Ui&mdAett*_ywvi@7( zL6nB+7Y9M@28Qt(wk@WoOpH}e^M(a#dNeh>(y7-hr;!E;qp7$?v?DLc4h5%v~YzT z85alsfz$K5{hUpBK+abE0HSir$RQ9<`rk=p`FLcq2xZHR$w=z(li2I}v{_8BvIuA? z8=Lt6j|`bj&{C8Qx+9ypI@(M5mFY~2C)h}`)w;@XlaYe9S+O5MmQO}l7{#hqPKNP! zC#B7D;`u#9vrT8ypX{sGb%VuU6RjS7fhn8bXtN93+WvKiDy?o{=l~)UEZP0}IH(E$ zfH}ES{11-S1F>SXRei|6t+BEOtePhfEA3UQ+)Ggg>W`#6oVq*o`hHmtQ3K-!t1Z%p z9!0PPDgK4_J0128xk2epN|WVQ3`gly;8fs;t^gkQ=p7ttkz3hyaV%9FMzA)x&27dd ztP7pEd{gD1TD05XObL)_B`{S00Yfqp>U+3!=>mYcAk3&}xfUi~Tt{nQQu7`7TLigV zD6@Mrg|+0|DNCW%A2xtGS_`YDicqW8Ro_R&U8STWsEqr!4s4+pKA>F|f*Ai_WI1|f z?Ic^KFSL>!v;cC*slchgt1Dn$?eOjX`a2u;$h|!Bj-$6+hp1$)_qW38Z+6#ZU{WXw zr$?KoM?ZjIDvw2>^>%6#zDs2B%8YDMbPN3?uA>#JnlFtAz0A-JggXz1>dBYqZQ@|n z$Y{ToNC;jSn3$)er0XRf=(#(9e<^KVX^Z#`(FDOWESX#RQ2Pu{1x^Ki;0l<_#O$ko z0i@Vamc{vv8tLyeyseEa{V&`^))&$3`*qygMQ=*wKUqSnegFYOVzS&H(_dQn^iA}^ ze6-v}Fl03m2< zYYSt}JimwXg05c&i(QhC3#)zr0S+12Fpif4tpWjeN^+xZrh1hSb)dC{e3V6H-oMq2 zuc4CVh`F~lD0BuxL%zjGXW_s_6;XfBgqndo3&5C=RZ2R72~Z)@3&RVv6IqTq%-N*W zT7{q23>_k<4%cwZhx*Jz`AYE(BYkFir<~_**YePIYugay=44F=5dBvNm!m`5hy3!8 z?;$HjyEwG9Mcu~3#R+FGclgD+9YY6+tPf7z9r}I0&2gq)R~E)|(uW>JP&_oous4W= z{;3ab9g_VHWNX8Chq&J6_ia{-@VDMp3yhg~YrW3^9+$mGO8Lq6cs!rh0t*iHbjah8 z8MVpg55F^~k@On|w?$or#TKgayYL!n+b9cMB%>4^wDWxtF3st3PZ2b+i^%O%^Wv!@m_bn{{)JwBCzb|{6I$jzt!Uk7cLt{drvj$}-3l0N zJNj_VUN&gQmoS)Kza{Da4o}dyH^chUhmuk2iy-y=I_~Y*X+^zH<@kUH&$lyn{4AaKo&CG{)xcVX9c8^qsCO0;jX6x7$zxOOi@U3ZRK zVE`fMV) zbMw#^0CRGun1__)j0a-HXcvdJW292DIN^+{Rqp4Pw!SL;x^X`5s4*w&21X#2mMKJM zcq(uz@F^hEmWboL^|zT~sfTdqTXve)}t zVU0FB1Cv5gI6c}tJ^BFzQ`ts^4!%5dJvR-H8QCOqjYf}AM=Mq}U&=@?Juu-J48{+K zCU>Vza5o^UMn?O!L_zSvz{ETyC0#G^K+oL){7Y$bGqQ-^5KRy~!;+cvDa4eX!KuKh zz(=mY@2?HcTqZiyhikUjP?quhMveZNDGu49))&$3`*qygMQ=*w_>NZn00M?&WVt`e zF{duT)Sn2?FKsX9|1Vrs6`SKsy{@9k>ZOL}bF6=Cyn>5zEQ}xH(AI2~gl~jF-+8g_ z?4ms`ti(m?Rh&5FKp1_RkPGEe%hNRF7nWTWNCDON7`eI8Hu2uY*X0Z9Kx+$&K^8?_ zC(uB1NySjpa>U%LuX<3cLa#G4;5T z5BcTs-9uK4c5!IyntXeV{^4U$X>U~J4!@=cSMy|j5bzF-zTfINlLfjZD+l8_=|hhq zV5c<$y+J7SsfV`LWdMK3slchgr>VgINFVd6h*iIFIk??=%0kyB`p2N_WaAvvOn8Y` z-|yDWDG)@am4gW3o2;37pz}-HP?54MMTPo9Hi2S=?hG}zu+r1%nNUL;;-I!g`p`LU z9l;i4^#4a*q5RljVLpn#Sz19q_f`l6ARmQr&R!l6%k^Tl^HA*v5KLu_ z3gzQK7r^!0G(2WxlgKq1Jw_d^Sk-*_0*_vLV8SyP)K4HM3Z6>Npd!liR_NA4Zb)KP zMXUWyuMfmr zCOXxJYqr=>mNEU7G@koQ+oji_@aUoKfBZ(tov}J@L;?2v@;UX8ReI{V%fU%?2+8M~ zoG|XhB50Bgp9ugD7;!d3?wHj=v~*!=K&d&h5WiSPANtVtNBO0#S6BJ$&r0e*YYPX1EQ-1g zBVhxK5DYafNBlq{Uv@&oy{FJ@hK3xA5oQxvIB*ec#)O)IJPDqYl8V5>!Gh?8;g$E| zcNsRPcI6>L$y%=&IYiJuwB3r~E46MI=`+(iIPjMKx9@2 zm!m^l0L;mqVjfbGGaiT)qg@=@j*&{q;)FA*R=J;F+WM;W>&E%KqsE-98yJB!T7~Qk zPX$f|P6fIZQ2oZ`ptIM@BxRe(AGxuGwMl}aqqu~{X1VHA_~{O&3xX#$tsL~L00K9% z&Y^86g$Xaa7n?u>3te*yu3ko-3AJi|p*<(nrdmQzgb#A z8Amal&$yMlOprf5wT52brEtZ}(TC_TYQ-M=~Q-MJR47Qzf zX#2p&l+XA}+y8`zgpI4<9NLB_w~Mt{96INpewQcd&Czs(dg)8m45*&LY()ZupsTFe zOZ=2!^04dIi6#fa=+gvODE9*h#%RxM7{|+jsz8JZ*?>sXd124nvywK8))w%CEQ-1g z;s|Wr_!??jj+lE@1JtU}>kJKf79&id_In}Nj0rWdPlD&9q#}^85Z#C%u-v5Y#qTm+ zPED4%mm!p_^`eo3AGLVp{kK(RLGVBZV7f*YTu<`QfvNp+MRNePKCy|Nl@0WC0Fl|S zy7QKyfYc>pWw5fy!)>CXrbHCvgL4VW$1M#5EA+ znO5@)Eh-HL8hQ~yndbn{vkgR81^!MuaY=3x@vkPd-QlVtwYa`f84{O{DZV);U? zs^QRmchsu8i>g(zd5Q=+8OT3AL#uuO0l{G63}!1#TO3ven0U*g-(@J_%l(u}w47^Q zpPW0gn1YGW0!^~vvMm1OlDVS>g-BqAwD~wtWg&jkL%(S$r9jV2sfu72dMOb9zX`Lh z+aUh#q|{k*`3d+ZqJMmXSpA{x4}1N{xu;402t@bn6prz3th!2Zt0?PMdaTnr0sSYu~%;0ChV?6!7J;yH|HWx>z^ zM5bgU^fJ)Z1psqS9K~BtS!jzDqpj*gz9sy|09FR7(}zQ+EK3hHpo2x#`WZJ_#I{3!gcRp{<{3i-PI;ST0XFVPst=13{C+Q!dNmWY%0JA_y%+6XYa1hqfqD zF)8(-?Xrj;SmBQk9GispBOhG;$hoKaf3Fp4WqG}hip!spOWiR@Pc;uGHz}31YL5~I zA1Hml*&!8Yz72$Y!t?_OS`Mm0`DLJm00nr+FB`3gtQak<3?d*OSqLBE0f7}J!BVRT z$$=>pqC9UjY6q6AezcWeRPnkD?DV=4EGB+dV3iYoi5>AO zt)kSk7+xl`FZ0wm!kjex_h!7!@7t^vxoo|y78o-z7vD_jxw3ai$vrp1PlAR8H`+8e zvM|)K7-2nBkG>$3O^@G^RDK`Zw;cS@%7UQ-h)h|dLN5bdT>voW#8LdnG88LDTh)hr zOZbfetPE7Sf8itSWX+O!$F*X zg>>%WC0>2MUq$R>Fr}lDwJLys0T$`t(AG`;iI5rH632;PO6zFv(60GXMsD;oR8&kR zp*dp>wpH$T;N^J(qelSv^Cea~+RE>Z5Kt2ajy#`|l8(UApxQ4xI}V`MCpNLOvVk5}BwHTOZdkB#FiC-A zD6qRE&(b4S7Fe{_4Pl&B^a1u9w7G~P7OI!nCo@v-8fundj z(9nwr$~?!Y1|qBif2W&+ylz zZsDfeF-T7}4}}|)d@6U)$3|rebM9RhOzk&2q+(&*3=KFe8af&WegPsZq5Lw?LKlG) zCJ=OpA@40#j26BGjeKMwd^+n6V1-Gr)F~2iU7YCs2zzF*cu)T)Q^(p^yKLv!&6H0!kiYM~=^HYH2)bF zu!o!qoCcy9`qW5a1*up@T!)JS*sUuK7}oEo@XwCgG7o+b#SCP)A$&y%7^? z!r);k6~=>AN;-luPAL)pLZ5qRi?*qB_|9Vo{83}Fb}tBC(?A<<k`*Mn2$5{{8Bs}Xy{c0Qz#J{45Sk0(DsXz#;@U6VsoV;=|jn=b$)4k$#G%$ zDl;yk+4&$#I~oYu=!7%a$$Ug==ywFE_#gF`wtp|`r~>Za$dT)BBChN9qaND+AqDxs z^hf@+>5rUyT9WUyLeUz$blF>YgYT+u+zKT(W0iHMJz~Gp_nV$RTV8{bfo6PWg>gTC zAaUWvUoO6e7u}#Lxml*4@c>p;HvFD67&=%-YLy6*G4blS`q5T? zSq}p%y{-gnP8TUfXkR1NYmOGBQc|I`Ud2x**^=#bT7YiD{ZaW-Q~-OjDp z6G!nQZ$GhOwAjBJz9sy|0B8oP$fm4xemHc>vh<(<|9&}G^!>6PqE z@=g5Y$R36}hqkF?w?`_6W5erui`7^0bjP4MgyhMhXig~59G(`<8EY_=gX+#%_5?YJ z8bBRw<@ZKBs0rhlDd`C4aXJwHLf?33o2o2HT^B-`x_%d-18UircorLzwNpXxng-gi zZW|;Eh1_0fzrH1U?U(#_QFV`4$>A(l^mjS5^`XPBBr&BQ_0TrFW9&3?B|L|=svPI$qgNn5UOsxH zC%)|pSZM0D#DTjt<+ka50^2$&*FV zoKT=SyiuAn)?j)LZTaJ6mbPEF8!J7VltznIFB|+Nb!vZi(W6C!@{`#Qz;J7=tbe(p z#K|A*d&vJ1w(s{}lYlA3)G@Q8hIHX^3EKx|8o~a5p1j5p)XQGm|JY(BRrr^(m0b zk}gq!7PE1MHoyZ%*g^|Y5Kk^w$W*lb1C#>Tz!GUaGbMp$9g84G!(VKWnDBzDteY&y zCjRcEG+F}rDjFJ&FyFpqu%3jLCj{zShV3%{*XyU%TUq=5$azWVPbANO2i5S-8TgGI ztc^+=FM>>~5J31_afFWmB9dejdp_e?p;K%FiMp#78|Shp+sYuyC0gI9n#ic?qq2w| zc3^=f*~CJJsq5w5Da*=*s{yMl#4nc7zXG1~{}Z)pT?O&-TBIb>< zD<`A)yOYvnxe>v0RjR)%|64-;`iPUi2IYT*7j5lgiTJO)1%<>4YJI=AtQ1D8D>}vB z@<-@?00Blaiu4{hG3+LgAX#3~Z$P>)RSShO+Q6>rb0ZH~g!|=ngGQN6;0bsTtK79H zh^JSar<+$1z$%Nmg$@PG=J--*NZcNa<6(RQ!m!BAQMWFkiK4G7-Jp566pqyGL&LN2WO0R%u~ zWWqRIKif#FKp>ow*p4O*lx?amLewEN8tGE?v7*LF$c)KI&{8&O5~Di6!&qihXd#*) zM^Ot{WudC*GMr4hURPN@8Ld*PBA6g$5f(;X)!GS`qss=#iOmckc!tYN$ue_ZGP=Rb zUlXmKfmTdy}>F+ ztLu~b$YLG?q+*3hxY3A}ZgVe0R38l*z^dkzU)DoPq}SERi{h_Rsv=OfqZ=uy&_(aS z21R0FQx+XGS&rNu{;9w>Rv`B|-w3pCUbJERMn`j90S6WI4hFZ6Oz|(UxqP3IE?A=z zwBQCJ%^};2%I{wymvp;1j2qpj*gzJcNvffXjf(T0`w z9GT5dS*Sl4IP&|^R(>&^IoWD{i8dQ7QnIjRy=GXDnTlRl-$@fcod`kzYP5iU$f>}y zE5HT#Y~V3oxpj=Sj^yzQOgEjavRgWJ7*#v0?Dbx1pfTF)=rAkNqBE$U9u7KH0D&tT zq|nPkR~Nv5J15Kt&zgsY##D83fn^yl{xCuCpn^)hj;oiRV8WiL|SwgFR06|s$c4YOhs|4NU^_yte z%gS&~CECj*U3a-S5PqFS(ptP4py6Mb`CZfnJlr$)G^?dZ)Q7YIlxVeInNGfOp(X{w z#0=e(f>laY1f}V4EdIZUM&)D_e_oJ+-~nu%rGUPW;xUi+lZ9t4p^Zp@;594jszLG! z&i@Zr*RK)j9(760P}^dJ@N+X$H|1W>KvxF>=A3Za@;7XAgD7>-p|!4$fjF0ujM)Ha zu;#X?_Fb9HPFZHqq0?;u9W1n8uNnGI3t^t=YF$x28))cN1T!ScEJjiZerPffq*Wkl zj96W2jFC+~7-o69?K{x!)Q-grD&yThh9ofMYP(V^`le!Ulz z?GdXS?c&h3+;fmnO9ZVtJS~pL<H9}FD%(dy^Rg3JpkQCp9yI=DP9XV;@M=Ygf zG3z$Kp6gWL=@roLfp3I&-)R3)%=zxz42XOErvAID=~;E~_effnF;>(a){h56p>B;;m|3|62Ae| z(N=y_Jwi-SYnp(i!|_Aaz*a}F0m!eHE=TQt-ST|aPO>HYG>-)>qMpI2z^TBgz@P$h zT7`#?KK0Cd&%ipe)1j^N+p@NH*xPW(7Ie1{ZEZwey~yz$p9uW`0!%!({J)-Zf2{rk z9;pC!Q_LVHxP^K){?6PFr!NIkyN>2NhcD`WT3F8OfLpfCg(! zqcSp(=`qy1t!ErdDQYF$x28))cN1T!ScEJjiZeye04NUK297{7?s zq%>NsC9oNfOk2x-3s7q(sJB4s_=2n7_{z5m2`Ay3$;0cU$4aDySYJ> zHqrKvLG}6I3RiNk4o^FWwz&pHSyu4ZjT-%EE5EFVlt`~Dg3Si2l$tuuz#x;uTA_dH zL)(pd9FLfqJAGLgwzJrx+OVIJ`A^t)&gOTn!E#>@*kS)kn`F$*V zL8g^~D;+>&$^%)b^pFlFkE{v{8#Y?JpAE!{(N^sv`DTVv%V32`a1`gxk{?H8R!b4} z2ZILCLb30cRTQ;qeqlT(eP}KofevcBsTg<^Iy%Q_;zumkl`V@|w}3t5RNz#gSAqO+ zD5S0!|4_sJ&W25AYcI2`m&2&qVflP3x2(QjIy3~G4S-B52jwb&z?E%O=w+d+12N#v z2{Xc4ddP~=iq$9!dYJ_SGz%SMQ&zgk9e%|GmIKlN>SzT-SJ7iZt!e_El9G;~`*yCA zabO7LW7yh-K?GidF{4Q#BwA!yMBla>#%Ib9`U{ktEN$T~; zV@^u?MLbtdM)8~8q}V!30evC;OY+t2wb&s{;{k%#vCu=VRfFV(4ho)h{Th*TAdD_` ziEAjd80i2avtb$Nsz8JZ*?@4`@Quixl>-{Bb$v33O^Ug$FzgbbnIz0JR`!m_{Zcis zUAUUr06J)BznD%-b5Yal>M1D+bc&$Nlir(w1xG5u4-N)`6q%@TrHVMOZLi;GdERTU z8{Fx`wL7?5ReqO4TP|%x(j{LL*D=g*KeT+HAI^XRw-4pp5KTQOgXF-`piRHH}QK!rvj$}AG89${8jpx z7X|3x2agMbTRy&UKO<;Te!Z^BTDM0Lf*ZU8V&!*h=Y(nQRcK`(LiqIN*@0#K3q<@f z(7|Nuc?n$$%0`R#vw>JK+NwU}n;A+igB2#hQ9Q}L6j6ULXaFq~`+iwPQLE+`#&gn# z9)0yY$AZ)Z`fFaHPd&6{(s1^@iTi#5a1B2k0^gSpTLy!-`F)$!B0#(o7g}!@e}~of z9w~j>e80VX-_^3evtdTJwq?us9Y)m-Th!H1x9^t@vmz}z10d7NL8l5JaAl1Oy)1Nf zAO_qyVMbVn4_Pr%q;B5ZVcIh%I{3dD^Wt00Um1r-M)T;WJI*Tco2o2DdhqlcxZ3SUY ze;08bt@bO+h`kJwl>*73si4j1Dy6!PGc1t>|IQcqi!drDA%6c1wRQZaHz|#lfWDCG zX28O8ik9u%G#(&$9c^9zp}tpe{(rc-evL>u5Js1}#5ELJj8N>{%z^OpD0&?1R*(lbho?VNE`5yl~a^s}SkmEb<;W~U*Y?0^C76;eix#7Ci z>@t5Bu2@OUFB2uzKQjHZsDHvkTOYcu<2Uuv3i&l!lJpCyZU!tor)b&EP2&NA*U{F} zOSo)Z47+}fsB$2TE_I1(D6|-%*twahn{uybpsNBACS(J`$vua*Qm|A-%Yr$KbPtbO zQ>#Bfc}AU#JHYE%?955-FRMJ-uW1UDjpqtzgQU~YkdnEYLL-ZB*Qd&FgC3V+M0-Nkf$ zGDs?;$zCQS2N|sMjO9d`yM=BN<+lUaUD5!e<__BMYtn7Tl$loZ3oV$Ah=X91l8&Ir za|G!5)ym}CvRVaA{PmD&(D$4F10P$ir6uOl z>IV?8@LAycU4Y%?;;;%t#8di3q~b_~*ZzRMkyZK^=d0QcSHyH=l3t>&Fk-^6mZc zV|{jnKXUG<QfSxA>jes3UFh&$U%a)$_RdZ?M#09ILOzmA4b z6UH-Bsv;;7rT1naxeC23R2K1z8b475GZ$Xsg;3=7&<|UIGgBXSYJQx+EK(h9IvbV9 z>$v{}H3i0Evy2*c0>0ptPK(k&`uq2d{3gzE|tm3DWY+3YH z63RvdA5_J0#y)6(J}m!h(;xQwk#kRz{ux&2?()RXkH$ZCTLRsvamT3t>#iXD3Jw0) zt@4|H{zt{hz+o$-)g8(@fXD>v5_;XBs|x_;oQPljL$0}vf6mv@q8JVTzCtSHtKZB8 zUCFsqmJ+Hvu793ZMSFu$T}4r==C|vjW-d|^XwG_V-?_hoCv^1RMjid6FaMWC15l#{ z^cNBXUszMRXJCgg3rG;Wj<&wq1}S$MVx|4EedA!}Subel0{rq%pH z3#KFDAQ+{jBPjA50eXJ5F!G0`Mf?zFgy5siGH_pc$!XPPqE~(DxfO`ZNoZ?}<$^=D z0A^W*zTbRCw&hxm@3^%30R${Lxcps!-R0u23Pi+H`bDG$Wt00Um1yPdTh%A$E+>pr zGzhE1$KS+8z{9=dehzJ~b7(6I1oYSH{sZ1xzP&$SaPJ(_kDNP7`w3R)?jq3r#)XHW zN#=G7B{wPBTH34pFfKZ-zTfO{>kS6vY}F4SWMRUKzf61$F9^E|aF1TPFs%u`a*^%4*C+#SHbtZ(1; zL2VJgsCB=WFPr7A*YCv4bN1>0a=BjX`E7pRX0^&}>ut3H8Oz;R^lp-ONXfigupb!M zBDT?{vk`jUL8}K>_2>&wvgutGz}m0u=n$@mfdU^a{Q!cNgQ`$&loordd;vPladNu z^bR?GI?0yBtV<{x5qwY;_sF{cPC5L@2bVu`?rFJwh84Q|#?Ys2cbMULFF!{oa5u{C z80o`7#|`U&Lt8`8$v}{Ke0PVk4j?kY;sNG$gRU-s0e4EoFOTmYvSPGflM_KB{|@Ix z-N5M(Slu8(Hf5zphqktZ*0O5AD%u+?bQS#r9>G_Kw$DgOppkj`6l}u>=U&lsXnPry z#FKuB~^i?-7@oDf}%fIrYibx`E6f zDGQUmOh$qR>-@gRi86N!oFqc6CfGsL0HWp&cJOP`ZN`+DR`Uxjn2v~pV3d-MpvZFs z==s&c$R8XQ@k5*uf{!-KzdO=X9< zHJilHG(P8*S==pkWe_jn^tdGB6SfQJy!* zd!zxZqSbyKA)qDcNHm$rKpevMiX|Z~2HQtVTlv0Us>=0D_i-s!)EbU?D&txSJD0@ms7I zZB-xg^8=24#sgUCCy-ZXrQ6&K(HIvJOO1ZCm0#Awz^SM`COz_MX&{VhnCPk_o3}pNle!2cN|4~k%wZX8=^33}7@{&|sb8$%!&|3)4cR!8&&hV3h^@ znq-Rl`x}{QJ-;0XEz5y5N~wyV1?X_9g^@ovEaHdQBj(hKp=8MXPCi`T+!W0~?`ima9OZHYaSC++0sfn`m`?EVXlAM%Hj3R+xm` zv$4``?uBTGD}n~F%0l~fVkT{*FrJxG6#-q&2I61nWud)@U(~wa%d5V5=KaV{1-`KY z+;YAV=a_%T3Rw6aZ8{sF<#kX!xUjRC0%Nh+U5`8m@>7IX{Q!c0haiMHBTT`y3M^1jd3Bd)aXZB`DHx}?DV=K*mST+NuXJ;DOeIp zNrm$J$5s4vk}cV%g5YKSj-zNV@=&a_-$&Xv z?+2t z@Wu*Q*o`)w4cNScRu8V~(HEd((;IAd@_gR#8dMDQ_+aS=5VRarh4Kpq3jqp%yE!ow zzr~8tR`nr2Kj7$RJb;yc0(o^-y3M^1jd3Bd)aXZB`DHx}?7(OjDp6Y={QerX$?k&<&&mU)tpqCA{B$-RHF`se?pZFuN5S#DMGnMxMT)K4a& z{&K~4f-8@xR_^{yh06M88zrVVDE*h{cKn6~_CF%uqJm7TegFYWGIGI7y#DSYsRBu| z#j9cGgt9I4lUSnti?mx+ed;W>Krf(4Hf-_$9zd8oX0;G4eb^eX%0m2N8U0fLMNO|O zkn6tx|Ner{M|`uvLxyme9#KWd+y_fXFgs?C!%+&0M?;{13Zn) zzCS*{yh&w^r&9jTihDQzhQ`5Bw3Hk0)+8dAR{a11kO?oBjj!ni!Bhn(6newId1mp} zbv>OCulo8%e=SlXl_ed43EyH6voXT;lr4eeo@pT}40=OTF!gL&NK_RIU?l6H_RN%; zI>N_{B>%7siWb___#Ko2$r-d+7HY2;hK3`=?OTSh7JbX(JPD0s4$?Db*S~_$g_p|O z_eaKaLw_Q9#_qy;X5X)iPK!5%*PL8H&Q|>Z0)k{@<0OU2^PQsgqzc4y*4KZdNT0FWwO%_|Aq5mzjiG>bT1b6^p?pK=CLbUW@YQQRss*16tG#*tZU9YR9 zyP&X2sfu6=6AR<|chvSd)lRPTHmKw8PfD$|6~a@M!n4C)UlVb0lK2l}CFbJw9_4@a zua)&J3a%@NaNPopYJI=)qkdEhipvYgv>F5uaQ*?XNJF-FFmxbbE=cqnkWjXTI>cqP zfpzQf15dJmcuw%;$Q@cSo4~t)5s1oNiwdp&umRLr++kH#G4h~Rt*gF|in~flM^G8} zZ>6M(hG2V6FrW8;Q98N#dqD`YnAAOtpcRHMzW(l_!>}WV>n9UQ*wHpGSLkW$u%m_R zXB&xs;ou5S=5T4hzeL{tOF}NJ`T+z$WRxO`9{htKTvZ^Ew|EK9*>p+xazCZ0LwLT& zOV_8(VhScgK}*@hNwh&G;9)GY30jJRcy^^#5j4cA%0gAqWGJXffiN*yJ{fgVirRw+ zCP-NX|9MqwCs+k08;q8g*J!k|)r&@xO=mZPzf$pUY4kM_*`H*u_grC(HoIH0+}r$LowK0@;vjTWuW;8fsL;8b8x0RujI2Xv5j zpxtHXE~>IdCs_1;(i~oFGqhjVbueTCIa~Du2=+F-_{+xE@Pe=n7zhM+bCNT9gOww; zu21F{Z9H{H1F@>IxpJj*&K4l>JAzbv!@GX8m0#9FN~GtPV6%aPu!3ev&8*MBAd`{` zy#`L|_(ko)r@aJMYr)AOrvj$}rvk$YI7q6U4cp1qwk-SV=m}~I=c~<*4yjleH$y?D zm4QlUijsQ;2CUJfQGz(aod#D2(%(Zb3i0`g5_2p{4BfmM}F|KXs^lILvz9oUYt zezcWeR53r`^}4b|n++Bz2?*5aat3K26gqlx6U@S(o|MRLw4i**slc-;V7~##e1q*V zea8yuefI18DD^Ew1SIY>MVzT-%VhFjQ3O3^X#}4 z1g~3J{>o6JTg3A0r{fS~1)s$ar#!OG$ufrxZUIc?V?RtA`~*7a$! zn1(BHWINWiRPw@<3 z8l9{m{Oqkcxb)EaOz@tZxkMJP%;=sJ-9kT!>u4psnlEMCdUM_2T4z&My2)MqZms&} z6u633`@JI?{#BMRuri*Kl8(UA(Xw%tSs3{Z6d zktrLb(E2NiN0zmP8-7W{``JLO811MvFf)`|)_(@}9}bEYup7emAG z9(R>lyf$h55k4*`Yjc@sheNh7He5%2zrRNV|B|2J!s$^U(`pbvFpU}guj~3vaO`E{ zPzSQ-w?4Gpv#JjptNPSgIEi#htHZ}HqAcLyUUJumwnkK^v;ovv)Kz3J12uhU>!z+m zxJpS!fF?kU`!p_$Kd$Q>+Oj^DBYCqqaMJr3Z{El=kTm@*7XH>85JQl&6<{1x5J0$V zS+KG}>Mw36>2~_c#rcqx0Vb_=eVQz$Ay5c3Sm!JPIG7H~LW{CMGA0_(>lx^3zcz96 z{v~R#&jOgwh=yK8FhioOS{Ro^>AvuFdT6^B2hP2`^79UD_dM(4 zyI}wU>?;t34i0UhwIDpJyDt=#xQ^Cg;naL7qcR@d+#t}0kA9Z|co0j@prr`bWAfZX z+p(WQa>IC(Qd6(Ob~OB<4sAz8IQ&zAQ-SYT0R!LNj$tpZ+;O3yu(0d2N9=bDbhKXw z?k4#q>1C^a071)!7k}CK8eVjRDlHSmvjO~imEw^$Gl;S#T3sJUfZUgnH5`alm5plo zEv$ud62PAkLt#JK$}j67CDQXtu-U*tSV1$Trj9c($fTq~uYr>~eo^Dcjfhuk!O0<~ z0;d9}0>cV8NUEI;+sW3pEc@zp8GymMdh`Y1YO|w5Dgv@gEV#5XVCVoM6RiArtoCda z;32Lo@*$@Jrvj$}!wTp#OLw`biQ~PYRVlFCdn#*l znW%?DwlFr_y!w8Bj|ST>K&I6ofPg0%{U+e{vT>*b5$T-PhqiNVk?O-nUkqKJCJV8f z($xuPFqYi)q3slw!Y?waqOJT&73H~pAz6KBD_C<{K`$bhV?inl%+&JhWiK1uW5s=@u`W*CUe{v>Kcm2Q8OW{SuZ7Ru=aukPIbiJ<7#-Jz`}5MQg+Y zes-OTVWGYtK!bIjv79J#cYsPFlzai-02&x*zcz6*rl`UGnJEc$ilE3d#n634U@i;y z;;$zq+P7I|*w>7vhqiVrhIcu%MN#JgG{<-SQ{w>g6-YuyhqjOS&A+*P#Oj7fc&<9i zBCi;+=ukl$op1&d$r;ok+Wdy>;0o)xhqg~iN!QCsq*HnhZKvfq!c&1$fp@Qffd_2B z*bVI?e$k}l-!Y1{YL5~kH+TaN+OGq5ll+qOvQ-s6z2SS!|A0m_gl!Ur|0uS9!LK)X zgO#HnU7yU~dL#iwtg3AIJ!w$0;ibsEC`*t`FGFcR+R88MAtloDOR(9%L0CaEB|wYX z42rT?(!4^Ok4y%db^J~v478~9F$U(lh2g%F=ePNNo7E~sEZddZo8?@hZ$^07@EuaJ z4+rrlFmTAB+SxFpTideitJh@!2J7n47leF{IH*>B>5z)h>k|zX7zE2|d5Ug>XRnk995{0f8Dk46wj96&*df31(r?EUmzAw4i**slchg zslc!Ta@v-*O?SDdDaU+6vqE6g-t$NJxZoncIvo5shqmiq+7@|DhM)1!*5_W$%Ot@p z`XWPvUP>Q5+sj4;Sw_;+_@*WfKhmM?AAW_hnW|2PNAdqI>C4&<_aFVAM`nj0!S|@m z%zoc#vO*qOFyR80MOCxWcw~}@R>PLfPZ&_r9usb0Wg$p`WGJw^gp2cf#L57R)`$iC z>^c?0LVZDi2J1XyIZ@{B0F^{2`2xNHG%(P9ZQ^E3QG@+6QxfPDL6K*Qq5F!!To&%d zUr$Q3Z?nv>uNh4bZTCWWmqXhv*ZTO*n|%AB?IV8kq3t79H&J$2IHN2?Z%PI24TrW< zToFF^&{j~V^aklDrKVm}v?M%-wi`t{DyIUc0`FJ>1MF_cu;&*|N^uv6_(;<4j0 z(9wP!xSOPDe9+NY*wb5kaLF$N4RjF*?&c)-NN=!m#Mbr6{M?sObvO_!OoE}}B=lf*yVKt87O%v7~v0HXoS`4D0wE0n16LwWxFkrvj$} zrviftIPj~T4ciI016#0VU%f5^4y>z3Ul4N3a!{@O@;Q(}q1Yo9Oj;Q*bO4bFR{C}` zaQaV;hy3!1{g4%-t?EO*i2+|Ok;N;lR5sSzu+n~9Kxi`Juy=q z&!Me<^2MjzIkX+Vv))x;f!=LQ*dfe95CpH&@0d)s&O-~P_REHcgKXOwnZ(P={Q!cN zORCbe`8!xy2vQ&!3hXYCrc+w2Ju3q&TI&WfgQP5M*LA}L8m#k-v60KUI~XU?-Zs?$ z8h~iOHgPkisHypdR?;26YUo7-MV@2CdS!Y|?ZhVACjNR-qFSSsj9>DKbP<<@&o@*# zXNJE#sB2UdHV^xLQA-weQ3=4&Y7js`L8)Cv?9N+;%8Jd%kYm$m%Sv_(TDxQ{{0x#N zp{Oeqd&Gd5tSwbs8pX6_ndutjw*!sZfhEgfgqj=NB5DMiF`;Im_QaH=UMT_x2MdD0 zq!OdAVVd~sNr`S6t%dXFi>H65w&l(+iMnA*Zxwer;xvB}R<&BcQFCV?$h7JQ5TWo{ z;QAuK<}z`p3n0=db$ml1{HeAGC0hQ`X!S>bO%`G}rPUuRHr;!e9LZgO9-6{ZSOZpB zR8{<4>_n}aUlC8~A|-)l9j9PPC=0{>EXtJ=tb!)~?xZwY0{RK5KN9=s*MB~GfX|Q5 z3gi!%yQD7k6Rc1Pbw#oJ80hJaN4QfEm!;a;LcoXdbqT9J7Ld;wY+)R1=LE>K5*R!T zvp0T@mCv)+B_4DEguCVU!ttF^oLlme91HOnxz0P2jl8(T35L%YxDzyH{G>V^-B}*$n8{#7r-k-s#z&BUGelx-W z_?Q*w?`-CgVDpYsZCTjaWUmjHi_OkH;+Id6Y}F4SfST~)FB4zGi{7&x`5Oaf^cE{i z2f99)zx7B0idgAvyfAfpo)MlX9Mvs z^s>-i#4l>>4uhEsFY!Vsa{CGCAD+1hl5r}hgqgZ|lM#f|y zR*bf)5BbPq0#%4$Rb_Ks0C!$hau&)-C}2jzI|cn{E5EGA4R+Q15^XkEq$JR+*9;3X zDXGxWKeOA!Pbb-uzYNU_a3g{zt5h9_>KW{oucA><*6by?;g_98-!ItvHX}ohO`|QV3(?ZrC1c@dkW|K^u2Ad|17@q((?;&qw=kG2 zT671NT!&GW1)@f<853$^|HPD}UM2?Q;_LDSfk`E<%fMt2Kg3=+r&bJ+<hqfvTgoW+Q(7H9)@Q6&m>ikSb7*V%HmmA( z4sEBa?7Is8^Ig4v7w1;I{(!kl>Oy~%L)+X@Nah{tGEes#76LwuFFeWvAG@A`4lL== zfqkk-+PRn3f9T0RCJrimMa!kxqQqmEK2RIrK_?OZ)f9E=izgb!V-_XfcKGc5IfOGaL zhxC)nMb=9OZ}a;$t3^U?A>R|rdTq5$%X)8)dj|)yC%pso$A!d#lX^Cr&PL>U$EmEb zV#>O55%vAr4R?i#etLL8KY(Ci!i&F5d<`#p&vxW*44BbdtSlYq`egnio26LkY`hDA z8$S&H3zvzn6ya`8@`lupR{M1XLy3g(%#@m0r_=F3{0qG-bQkf98kbfubKxakTnNJW zbo7r;5b+OqaLIN01Lj_>$j`7stB^;xcL?<1n#0bDt!QMN`0sLPyS0to5LkV(CgB&S zlfn`@I<$SrFOTmYvSPITV^IFbEG@E|6QEUxr#pwX`8hiAaHp&vZRNK)^wjIh5^XkE zq;!KV)VMFrAiqK=^c>pq`wm~3e#cQ1HV?7VE$RtNY!|zI9N=g*2q5^tB6aZRNw?|C zP+74V8FFkIZCTYF{N(^M$YN_RxC}s22o`s2%9&dkD{=ZF>7Y^qX0(zK5*vHa&;7i*;O` zr`G4tuCC((E{LuFzexEutDO9>hqkdS=jDS{z<#iJPB>4g0Cpb(Fx~Owj$-1=Wtq0N z5ERXYu=ur{fetL`Fe^f#OMpzPe%l*O<@qQSJ9Zt&Lw?z4J!Hjb#cGsAQMZ^v_XTJU zLOx6^7$IND85AN1jX7xmb+iIfEhBc62I!dIr=+AK5D#!PAn-2>r1{7+il38}EjjDn z)mA=(kPiD)U|0cJuS10+_=FYcZ`S6KO!AIXZCO|`veySpE~36)`-opYMY2^tfB-fSRNIvZ~RaN~#Jf8jFml_K2DN%OSPPwZh8 zq2_@8%#^AK=J8kl8Ha^H*Uf=DURpt+(W2EEoC-Xp0$it0K|3HHqXKt?p%2#_w(6}I z-{sJD%kvFdJO=%m7!v*)4s9Ru%R}3TtQc+o7?g*$TcGmWkxIRRto_88sAIjy48})`+UZV3dXEO{sx2 zWn-!9(kP~l+&eX(`eqYz! zdxIi_JVch+&x=Oq(DsTm^U(1tH>!uME*IzY9NI3Hc6FY54s93p`X=!w_#NYazA3>^ zX>28GdEmemJhBiAZM$70KtbmABEz{ z*93xi=7brUxt^BR(OQUWetP~Nau*Ra=A;4C(K=XH%ZMGN zfgBTqyE$2jVyRS z8;Di&1OmA6#^HbAGV%2s+J-V%)I!(IfjeGWL7~y2)#n@h@d-lyk$-K9xA7;KrS}T) zGpx|f-0#pkhqjvq3u-s&^7xLN@j$G24%j~iefy!UcYUY(;$+r^cdYaOk9Te%qWWlX zr=TD0IkaVgUOK2cH{COAMZ%78)OQv=Umo`TKKMugT(;8TyCVL!7lu_8NMSM@8cHlj z8v{gZMAcz1%0l#})IgfDvD9@O@xZ$N7N*b`4lN}PqbdtsMbzJ`Le0V|3&5BV1KB90 zDuM}87U_lI`3AB@{1AKPB7;0cD8PChIfu4aoSBD?U%62|WOcbXt*8&>z|?`*fhWyoMkevC77y;~XvM1LOBVDpz>Dmv^+z`Od(t46-avmE za5GrS8bBSbfaofEYp59jVP!leB^`lyfTIC{e<>|LHaO^y;%}B#&^It*mc0KH4sr!v zo!r)9d38`P^7kX>{vIWkE$}_C_c8mMwb=(Kcbsa=($C%qDVtvX-3To0BYyc5$yWUU z0;mZu{xb13yy!jKk-stE)V;;Z(t)l|<|7O0%?4tnv+)+Jbk5lTs1SiOCV8*zN2~oh z0-;30cxFnvXQ0RFK>Q26EYuhAiyFJbVCKS0ytojAapqB;UUY?FR8)$yQ9MOKQiq5 zwP;yHYe9jWt@;536v@c2LHx-?^eT|ZTfO{S6r^l&Kcy0_d>MD?`ZQTg!9-|*=Cg60 z_g~>h@UQ8Pxnox0m#VXY2K1U$7F8A5gF;OTgo&AXqO3?M@KzDfZZ;7A{}QFjiL8P; z{_do>T1!9=Jry_=I2D*w09%KFivHqZVn-35U!J3_Ep+${bzlV2^J@zE)-WQMR{a11 zR{HkfmkjGLtOCgj!x4Ae@DzXG(qDgEmxb*pi!Eqm^Aa)RY(3yY{~3I;Q1voDE0PS9PD8^{RxT;T+1@z|xXeyh)19&u6xogoJT*^}b z-eJ-6i+Y4uL=6SH!D@^2pvMtxL5lxKBJw^LM;Ws57VrdSqA2dub)hG7gz|gMssLM_nUUR6hf*D_ z8}RYLVh`Ft4U@p`%@yX7GiWI)wEDvau*yRFwFH5hFfcI`&jtoU4IMtdrK^en+&K~d zLN5b-?ZgtLaYD=R;Yu!O$?c)10;d9}0;38T2)dh&8(ArS-f^l27xpLF>w^)uECUGb z*MVColG7P9Pmg{8!P3H9sQ;2CaSQ|qgaLxxB{`!vSUE!K`eZ(`$X;mC4#cX;MitP) zOep;3d4s%144M6CE5E2mZf^AaJ|(4U*6EUwb_UWj2)!JX7V(Q3yTfQkms|P3(;=q< zrvg881st}W{y)yKRhnP8_n6B>i~hfG6GXp9xqlh>{UY)$YA+l0Xw?rO>d4=YJmo(~ zfh{^bu{m5uEYZrp4THb5@Hq^!SRw`mpryYXxg4J+<-e07x$Ak^f^PsN+R87M(Qg7O zYSp?D@sw83bxH!wI!?ioP!@*yNt7!mqxhSp73`ZV1@v{a>NtK*p3MUR6pcbe;{Y8egFZ?0Fisl1*<9$s7;Bb)N!;iK(v;sx;{-7)SC?iEm^y)niFO2 z2GT;5_4^~2**aPafvzIz?`25VK`jfwm=FuuD5a*36D$!`3*)-96Zyh2hdEkW0kF{$ zFE69|w9R2^aJ+}m=fT`5uB>km6enB4S{~XO*v?6Pd^ZRnfXHF3(CZFpT>t~_oG_!W zN$(*mo&(6?jqwxK5vhcVIq3 z1st}W>TnImd)!rKq2kc?*YI({L`8i#Xt~QjaA=F2cIG!cJ#19?B5M5rqBO*0eLjmr z+daS3LfLpPf%K?E%fm*Ts|vr)!t_8IUUm4$cc~oOhAEWX^}JBE!7LchJ+w6i@_4vN zN$Lf)pTZQ(`G~9Bm8`t);52Pm=}pW&=S>)-J0ia1$8u zrJ%V6K{~x$mg;CN1iFf-zn39d2em8!V?r!sgOmhX)Fwz-R4t6_66;0$5PP5^gFMXZ zIlFqrNT0SjOpP4#?L=^=Qe}OE0EcYhPFTxBTbM40KEAs~|5!#qk&J|1cVO!RfVm*d z=<7mJiR)-@kk))DqcR@dtPX9%3X_~cZzHT8ALYqYr=z{Yrl}&-P@t!#q$B7B-SEV} z&_DN~ZIk|Ce6k9-PZsY9cdG(b-=;f;Ercs~T-w^fJa-hAu-HOb=)lt8c9Q@(TlE77 zXy}AVf4D>2Tmu*Cv3s!zbg-yu-fx`QQCe7GVsJMn24W5ETPg6X2*8~a@h|i;(AQ2Z zQ5q+-%!T`bU5_xj-iT#L`BP6UwS!6G?Xa|BedN^2b68;x18(&%5 zJa6Flh#|8dZRHnL%*~CS->0Nh)r&3}X=flkgV4)CX%WAuacxI4y4=bKo(?$`*scKA z>9)mD{P-1c*mnAdwp;O^U)pY!$v^9CRK#&%*uUd@O88#{##}~*Yg!#X@?BaV+6E+j zXuHPt8m^#cgHCK@m%e+MfaNQQ!bk61EY z8f{tCA0ZgaAd8}|^w$n7SSbXT6;dN-0wcZ@G>K5FpfJ8%7A31X3th#GiKN6n37(Qt z6#>G^adt=5!niIAwMG08d*z&3F)WsL*X?^T^=X?!4RE}-RpmQFtE_Jj;E*lc32S+1 zYlHUks*mpm0R)`t;4=Sf`MLmh=`$!WqpwNbCbD>~qrE}D=1UfN#Y}+TerW3^s9E&f zL))jMr0ZpJtmBcCROmUh9oOnezJCSW_YdJj@catkA#Z`KJBB@X=>hG$skU}7FPaNs zv01jzfu+IiCTSXn)e%Lc9a%Ym>As6iGf%{=eVl~ z=3tNp|HTTuE(3vfV!>tnqQ zwv^!Yx)Lrydjkh%1 zRKQ`|sSek0ytftNyZq92%d^GvZ0$S|h&Y^86g$pmc7eCZESX4FdH_rT)-ogqKgS$B~5Nqfh zcNM`L4AS7gSfSTtAka=MxQt)axVD3W4KMLRC~|w~slan8@W}h+IUWzn`&YogMSs%) zcOFLGan?_6E~36)M^71)tagBJL9$gpfM96Di@$7q4KLN6jZ`1;>p|XN<%08gp%|kq z4AiE?L0Vmi|4>OwDsQ@ z#Alx@qu-=@7LWF7U5R)~s~^E~~SQ47cT-UGu11%rTl@q)Tn)ts6ctpTW zqa{kOqgBW8bMkB=ap`99D(#S0Q`YPtS@*Kj==&|Iy6_ssK&I6ofS_xl0b}xau+o8K zDCqZyCDWzRmQ{7w=q=G}4YDZeN`LLZf|WvWSs{U&z=$seO(INIP#9k>i*&RW0$s(7 ziKN6n37(QtRY!!Cgu74=gaD273selah+SjAJh(@Xt!{4QHX0A`>;w985}3 zZ?ppQrI)>I^w)10wnF)xT2;f;>5qOB-M-)aXNRIUrRFkGzVXM34z+fC$9+r3#nrdp zr~T|>P0^-5FLZ3MgpvD~1oL4hX!1B5AYl%i~gjN#z#c+%yDHGP$nJFX@RlxPSU1+X&EqD`o@{bx!~a@J+BFqsnt z=v5um`+nKVh+4I-hz67{=|l71ZWU;#L7fa3iNk2ZYLXox~!wOEDM3`_5M~^qs?w>=LD=L`sv{r{Q!c2WF+)* zf$OiT0ExMHWkzP9sKj-&7Sft8St#St4Jzg!=eyJv29h&qDJr!3!v;`C>tNMX5o!kV zt*0z>S1IWTV6-6OU+AFIF@$NH&@z0smJ3>P`w8iVbf```xFPse8VXUaWC z{nXJXSfRW5eocxF3;LUW)g`|TyTN(qw^d+WSKsd)mYbydaTkA_c7r{=zU+8s*vUVcjHb3d((h6pc7O-APbTi=KI`uqzJAPhZ+M2yY zv9|ND>(|2l#ep#TG{I$M2eqbU>-556r2-Kqa0W!0PWh5#&+0<*v^IbrWRdGS2qUtA zW|K~yF_ReaRT^DY7FQ^Yhb^Ga!ooBK>oO43U=P7_Qc@9^>~b=KfB8h@HFe$aaZA*^ zd@w0qay43k`O?c?Hu}?tYp#rJ70>TfIES_@MQ30x6S+7p3>!&&8wtOAKG?z0tm5#| zze6nEm~lefW_RI$rXm5Iadq%>M$_4%m#>Ep-zkq$1a&Hi1A zS5C=C%KcrEU4njw6}n6U3aJ(7cMR!autG9auoz*r==Lbea>v#8%V$MaBzik=VA0Bg zp#z9aS;0cFnMyAt1$f9W8?A?|5ba;mSDBr|Tx8*p%$xwtcrEMyhq9*T-6C1Z85Ge5 zll7$ly}E-*;Wu#fbY?ZZIf*ea2BZ%ypGWEl;9-CTwykLMk!ch^VoAjnA9U%2^RX!B z?B!vxTrc+gHotGPTBK$c@(0Du*22a2Aka6cn{TiknaZ9tlK(0BSa1f()tk;n&Mxa{ zYYRb9S7D7dyJl%+?A}N}J-kLgfM6JJ-09j${^Q$?s5$RFANS1IWT;9x<-ztD4Ni-P^SDBK4S zTTa>s2t%Y;t zHLI;J1F)j7dD!)9VR3OFj6O|pS=m9YY1ulxuvn=;gbADhVWW*!YtQOJ^0YR9A7qj1 zItU}Ofo79Vo-q>`sDr#gRasn6SY8#N*VkECAf#X&?mU4S>>+qUN*Ow3ZaiasIjBe_ z_@T){Fo<8o{=EuCPl_S3%(B;v>}8{)b7))aKC99juD<TSd@HJ)TunXa6>h?&! z?{a9n6+m@-H##*AST_I)9Ua<2ZBF3Ve*ogHLV$aCrT4h?-CJd9w87Zk+5(CZE}?L@+5{Gyf-yj`OOtXC4< zaX7eUYqSwcemqpx2FAtO&cm)>3yWQn;Ifs2Vbij8dSS8BfdF7mr0L|BBy)9zr#<2#@|#_}D!;jf0o0T@NNHuk&;dlIY$`&-V=rDh5HRP&QT%Y5 zX4$Os9VKW@7W6V3z{)@e*#O)NL%xzTXr6=_a2GH9Hae0?1wKSY`#T%AlS%j@ax&n@ z^J<5cz256t>h}FU^c>(*BwOh{GkeP$Br|ger3!=r&IZiL%(QA5tQf6@Ld};(q_*$g zN3>rq2O+Y_mHxX=SaPoBrHfZH8$cax<=4<0YQkU>K!x!D1#-|>L@>rFCE{PGe0Hdu z7~1GGJ)4$gdkHOCeZIl3A3tPUl>Wm;`{b1%DSwLG-*-};v_hXeL2t_WYqD~f-E(NW zQ^ikoXlqP+U|pQ&F0;k@@Os@N=5uJftl;}7=w`sd2^*6Qr+N3OtPPB1!}qs&*!62+ zu}czMwsJ5;_y)IuG%O3D4g}0Ok*1ShlFZdbisWf+AQ)vKc2f#8o0QOB`WsU)WHy@` zB%Rr711M9d{o+e6m!Xg>>#3Ff0XbXs0|*9^k%raPiG3MwCpm-K0aTZb z^5m)0(K;A4RfL*>920}PIa#HoBbZ}}RQwA)hqh9gLr(=x1zuBuugQ(WF7%#2QOgMajUq`g%dHTes`Rssa0cI2{3SIge|P&% z9NVZ%TiYv1eli5J=x_WN0yZ)$zyGD?)&R)asvkhWl8pW>zz(fr6^MwZ^q(S?@a29= z5$!J*w#ceJO%_uy5duxJ`IqnoJlsp}pruIEhqM9IS%_b$B70D%Nr5miLpP;hm6DF2 zv>cDc|Nn?e?q82*bG6q$j0?BH- z`5n+q)GDU!|FQQjNpkE+wxE&8m%=K^e!^E$gBqgQDJ^%%C7?v?X*tnD*^Vt#1JTM(HAI7^KD#WU($NiQmQCEfdoeO_wYS_sOOcAF z*AB4G!u+B;|BP5gr#Itj>dJ&iDb*2})s))62-@RuG&W8~@pn6Am*v#=O9(Fj{Y#>E z|FHi>?HlXACd?>G%`LK2?E*&aH^dhfcF>p*AZM$70E%!0Orq-bZ;5kB#6G~m)0{-V zSJgrIb9G3oXq8vjXP3niXtJuaiM*nSS0EWJL~|d~8yD3m0h=s(Ra73-tU%}(1v|XD zDg6&I>(%QJEh(7)NH4B^ zvHln$S7&5gY{-Js^SivxCOjZ#t9}4cIb{?Oh>-qg5?MZOxhz82GGo%RI=nagx<30X zCRkYnw3Lm{`~?1IWLR&4!f)0cw|o}W(QcJr>&`TI)W(u+##M%!v?^$y75fon`J{z` zQH<)!$uRzIr|h$wczy}dY|>fuXY=Z|U10H-L@_^I!BxU3Yv5O>we{-?Ra#xZr~`;h zu+l`S9E9Bj0)RQWQv5fzjvHphXq)uj=8n9}zL8U{|YjS5NWRzjc%EPX^LbdOg z^)NLsF0fi6edtjHOOWQ@=xF8M#oz6eoz_wer_x!0vjV?#1+d&>?+{Rnyp=sJj;BgM z3)T*gd7H5rYr{_5KB)>&EwObL)_WiU+uieVWUl|5X#>H>gyK$sEAcAyS%8?77g z1Nch>xqB#c_vRuaol#oOowC4eOd3FZ+`8choN*PAY%{LLehSGvr8a`XaNGJ5)2Tw|Fh(W6CEzD{xle zSFV7=wA26N97~n?O0D#J8ZsIA$g2OsO=NvG-M-(zx!v@p6u-lft@;5dhQ;JLKjLq) zG=WV0neY>)XkD?{G~tk1v|E5mU7uYRL!eR+fM(geHzC0Fk-1AtuR;``XE)aZHd&Zo z3?n^TjhFp;O+BtmI;BS`H4#j)Oo)N8{b7vO$sqoIr|hyc)aOwQV+W5Ig}1yud=Uow zP8lY=a4m;e=`dSHm4cCroP4;iA! zAU6?8)_P7WAcE#_4aa;-L49GQ7qsd#(<|jXciTq4p~5q=rD?;EX?20CI)KP*4lYNB zwm13ZFDBh&m7)zS#uY)gS$Od01Xkz->rQ~XG?6yBXv{X6wIzmzAd7TwltAIaN3&$#_#@nkve`d?m z$wEeX#;K>Q09!15`edxpWam_A{Q|P1MLz%)TSi9PmD&?yp}~yqv2x}hpfSqA^rqB7 z+O9w$@;}DBEoaaqg543>tu{@xwO>y-s2KwtL-DNPAgrPD;AtY5K~ZM@jc$D>o(4N7 zwA{9x7Ol?4S%C*s;GJ#$9)NX1yq*d;Ogr`AnokpoUyAc<()wpzLF3#EYZ)k=f>BKF?m}i`N$_lWyxn3TPHJa=kObSKg^eB*N)qGSD z3LBdsjka^PPr9W^Vcj&Dkxzoq$or3Nv}V=vEem?-!zHeRuw8*djG{UZ)-XPzhvSXQlr4kDo4tbu{?YaH6TStTgr zi!j=8u;L`ob)DRU18 z2c#YtqFmR_hGQFl$go*t8*7mv%dGXBRzNWQL))b)e_^B-wCXd{E9EyF+M=k1X{Tw( zJO;f$sSY4An}f^Iq3un6`AyrKtQhUVp>04ib5a~W%1de8nJWEpb58rW$sK;(95_j9 zK;d0sRrnQ-sqKz4>v0ueJSTl<4xTHlp=MLk6!QY9(fbc=gCOm)1o}zN3fx|S&dl%f zoO(OnY0;^`(k#)jdn{|Z<5_a$lh(Jvu9F*QRdafaSKsfAHNj4SRsrDHBse@OiL77j zo3?HXo21<4?zA4O7pDRTi@N3>+`2o32{mj(0@RiWy3<4XAc7^xpjzMZ2<49rUIlWE z;@=G|RnB`WWU0(obg^PjkBQ}avgiB!-e+}?nm>@Qh{LzBRvvs~od-+&gYgt@>F2l? z@cTm{G2lFcs3#q_6k48fYU=>&qOQgoO?D0@vP!I6Kz7va2cTjbqei(L)CCBHnl+e_ zPg-H7Oj#SPS+#td`RRoSorVLiUIVeLeA?dYf85e?1`V|do(6;yl36v;)_y%vpk@qo z%=f1x4(bTZ13h;e@NcEf+rESN9nlOy7@o|fe5idk&I+tm;JtkqwWfY*y^RXE&BZ{! z|Iqfa-?Uw--mQnWzsp3)`O(e<>jJF##T2b8Hk*f*7VQ?G+8l#&U9%I$Lqt&sK(lPP zCMbB=K1#~6IQVVT+?C4ps~+0^D&Mqqv6qi-AF=|*aJ}!8VZtjnVdWr7mcbO+Fh-vy zxI(!ffEqV3>3~mH6^Jn*8xU+ZMe3qPi1))AlBczY#UP8Kt`lgWg{0!B>9zIYqyA!} zZdQK}KnEG&y$9yY6e4)|>t@_OLN;%Kn4w!tuD~61Bgu9D;oV3 z{+qVpqjUNn+OwQHWkJD)#QKR{cZF*IWOa9(*^H~9pHk3=9z{@E4%-(;}f8b4Ua2~ zBkN~7w3U3Dtv~l{F?YG0hqgKhg5JL65jv_HHqN3v8d?gp(^BSnofTNDKpsDRgHPZ7 z>t&E5aT3zyfbKu7aiVvVe$fO_xTqMQen5Z*Ym`%L03Opu?sW~^0dNxU06olV zzaeoQgu1e)tLonX<^idp4@b+m)M%{heRtGqcNfi8#pf;}=%j&tOSb92bISdKz6q^D}yk*fJ*0k{Lc}gu> zj_A5RyDX+)CiFnFUy|go1h^AL=8hUbWDrxj`*EPj!u+PiYqzDe0-7(d-8LNw}c<0Fs+<-YCp8S5ajbBtz7x;A5{p-PX%nQ;%|W*g1k5=J6fdo^&^9YZiG!X#Ojm{Myq6!NKpBX{Rg6KHt zVGQjzNFEA#dr|xSWO6o)(WO3dv$BI)9YAF6Sg;B(Nr7Z2u)BmCZS3dPtUR!2UDqdr zxTqMQen9GtZ|*UG$F!0AR@J~A04MPd(8H|u8xq$+m{<9#f1yRCL8FE~hyZyGpp5O% zuuAZ=#CjB%8sl#}CBp2q0RBAEoLM%fo=b6jrdDHJA4*28^U!v)<3jyZAr2xtgyitF z6Gql`(l9hTJms)F4{gh;SxLVdv#r~CXls>uee@SRxa3^$3+CPoz;Dg-8-DbNz224t za5;73xl8gUrQUC}p9iWj2ayL@ms3{XFJ|<@V%9WdT6t*K0Ys*a zQKOrKZXF1ia}p@NWf+XTk1w%ZiN2ZY*SnS?3M4~;-6gi^w5`^fl?N8B>kVWEaZxcq{eaXP z-`ryWk7*s|0^=s7HaR zG5)qwBFs(;;LjuHp)HQxyh*9|8yiN91DFyHA`fQm*EVs5BJ{e% zfy*%a0jO4hs!@Iz=pjHL3=r%tapc}(#b}%QkdG{~7rN^-V1-Wb)Bt!8hW^tl#5-%7 z`wjda@nrU+ZTzAh`KP72e;v_gjf0d71Zs3SgS4%#(VzOzc2HEcuURcbU0YX}NFzNsz(=sx;Iq24bfH^0D z;#)e_tQalcs2$%EexcD{19PP{U&|TvrZ*YoAz(mEeZQ=SsWpo+jOU~eJ&ItC1*vZ+ zcN`9ab`%8V3zMDYm4R!Qr3p@YR$#pX97cN+zh|AChgZPP*B%Z$0<6z0?Y!`oFaqb} z#`+4MJmSpfZs#{`r8Z4{zMx$EzA&F>4YdmLe{{m`j8)%g>rK$Bu$HeKV0~oT_`MJp zYR2GUDHX;I6rzEi)N2eyiTOAB$V1y=Nv6M-ZUi_OZA^~+8-i#$Xk!fRH%J}|yH7`8 zdDHf7af^L%X&E2)#Hj_)5bwc2F*H7!IIEQ zYIJmtv5TKhvL(0I`9Dp%5W%T(R$#pX9Bu#BymspluTnFw6|XY9mkz2wvvJZ{aPO$& z(W+Rk6AHVyiq&8C;URA zc^Q#SuC(TBIfL>|UVyiLB4B_~-!JQ7YRzK2;?edA4$5sx2F*GyfO_Z{<&MKa(2jxt zKAm_lldH9Ze)SyGm^U$+Y@J?oU67OkGv2=LV3 z^Q?qn2%_ttU+*|PxI%I>fLZ(f1nwg7NiSPD7}fzq=8grc02A(p@H`{7>Eu>xrc9Yf zi`Ml9a-Rh)XN`K}o3kjvk-KepxyPH~Le>WqVeL00b(e_TJz91DQao+c&_@wWp-kw| zuu81P-|Z9w%UPP6XVLS}_UAsd)p6wHe!uWL7ZNRGB5l1~sMC1X6Mj^`m26>NoGW*dseo+ry z;L}z2uW=z9kb{&A1Zs3SK#OeK>KYxLV-T!y!jI7-+D>cc`mM`Q=I5v3p6~K?c$7Eo zm(Bf!dLXtSlmVhrOs=|eLm zgJ!+vXi@5+W0bo&2SGau0{C>|!BDcxvXGt4vjX2)0r#Eur}=BGz-+sXAJ?M-%=mpMSfg^2^DP7V}0z zF0A?iC`iy-@d?Xjn*bmA`EwgQPKa5kO5uBAkwgv}+@4hRDUiyN9-@{Xri4Np;L0(! z(L$u+$rTD&6)h`?F7;8d0CuoMT8~W0pjk(_nvvw+ELF3tn+?ZZ{M}C3Y0VtJgiQA` zT6ftpcpq&D5H4rQ*Y@fj)@f5Ka|rU^waVP5ME`Yw887+bI5Sr|hy+(5GI_ zp9A}Aa{lF(82+Nlf74rS9b$?2SKd@1u~e<^_mY*gb#z6i+jddC2;C1r#gk?c?PcHD)(BX;^`Ip=^`oy*kn=q zwR$KIYFBCM^~jW(2$F+?yZMh)bGpFbApWRU4lOmi>Mf2Rgc6^hd((MHFPVw;`WPb7 z$#V5d_EEdBe(xf;_yh!Rvaq{;ebisSCFH`YAAkZPBd6_jeeiL6*92nH8I5*H0cD$M zQ-(U|Mk8HSeLVH76Eb7c613O>AEJHg#Hjw>u?r>lSa|DI_?@6qQ~^eAlST52?hLex zn;Cto$5ob3T2`P=O3|u`V1krI7#J+cRy!HR?{^5o2$_jcGUGX|3*7W3oy7?LM!o(D zYID7+{nd0YXw-gfMmMbk3gm3n4?t0_fHKPE-~s^x!PA`NjP9_?(V`fmEaovlYG~+$ z3yoOmeeQ*b>Z8UEu!*+u%X(Oe>i!*hsrW}JH4#*{qX!HO+v6SW9k@ZUShy*R4w@|E zj5zXq^3MvK6*w!P6$mH;_6`n@x6B`(V6(|SBVDk@PSAs^#5RW`zr}XDuo^Wz1hjHs z)B!}MWn|Poa0@U&0q`^@p5l9~7;RG@@*Uw98n8kq1X{4t!m*q?Wug9{5ysjjS%L4Ufd3BL)AUtWU^?lP zGxjhGPf0+lnPF|N7pa5BXtJZjtVoMaqg_1$beaH^YcrzJ%|o{?fCG0tX#=vH>$3O(V$I&IHg&WHQddzRpw=vA;MOkMr&&s>TSov7 zElB+w@Mx6VJ`ceteh$cN$zB)JrF`JxBxePdDo~H;JBC}<-!Fl2y<6p%F ze^0}2K4zSL(?S-Jy2q#0_#c$k)?o`#l7G{J|M3N#?BYDu_;t7S8IZG8KLCxwGCKO} zDly`t+gDSt@a=g@E!xc`wWdD1ET&*4bU?#jnEAu_2CmP{J@slSGW8+d0XA8{uXQJ1 zT&P)r&@n?drQj%~CW6v**f#&4O`~x#ioe?_zRl7=pGYwWV>964`Igrw&*F`Bvq2K* z0C*u?zb?yHS|KSp>Uy*gemVE-SY}lRLa14T-IhOLo2f$^$)j4J~hQ^BpFk0KaD6%vm&Dj-j_6AVXF z<4AR|t2$+;MWtsoE^t&Iu3Zy1KsYBaa%h{&J8}Lc$pYt%??1G?#jkir*>17Q(H$J|pckUi8qm zDnQf$TN>|UxIR$7pGc4D)J5vv@ZJR z`oGHp;yHnpht_U!(0natPzT*5vIDHM@BrCW5o*n1yyWsIr8z&^=Y zfk#y!JPPQ<8CAe0#gY6a_;y;g`G{VhdakV{>CiUFd|O+GEksNlvS~YTMd|x>Hn;m| zd33YmJF^-DpfK^^@?V8ws@63wHtRtAk;^FmYFa*(ZOzJ}-CQzn>ciYE3ua~Bdei}J zbZDzx$lR+#+t7pC@%}JQ8*S~^s>mUXWKp1prc~F_S%6cjBQr=rKbuxlw^96#onXhl z0^r*$4fKgLj@{9oVJQwEXg<(KuKNvAfP#>&Uzg=8t&o%)bv;^j0Fk+4Iq24bfH^1Z zw&F~4ZlTfu61&rsB3tV*%ZP&thkwe=h*I$xW;Joqu zhqkx)6qitQE)( zO^G&XOj8oOT^%P_CNlp<5B^F=#|bS3a+jsKIq6w}@2`MNXL+gmez>=a@ae4vK8!m+ zQg2JJ;~832f?N~_e!c7Tg*FFK0JHI%w=jj#u<0S8l>?&=ATn)1Hfnpw022g)r#bNy z-($sSo9!d{j_?Z&SfLXFEfie;X}*>-C_915<3^yUA8q58_3*H3`j=?4#w;bV^RQ*T zW>}E9hPKBC0rFk^bYcjqxYL65NzMv9paSwvxd*_!bqN221a6rM9}rG|X2W!{6iY5j zKs?P1YjeFw9W+Lh9UW#xT67xi>JgyR1fX1-AdR+jHdYM>ggIeG_gL+69A!Z-vtWSc zp|e{YG+)aZ)FoY?$iaOFSVwCh^)M1ls5Oi6LsF_EfQNY+0b-;4*}+3Fil3d8E&0oJ zV#<8-@dN-*a#rB}3WWPjPsQo;#>H$NDhQ{Z* zR-6wWBD>8+ox?+0(ZV-w&F>+$D*RzuW@XXVer*`py1qfp*W=2-rt~PKCW0xJ39Y1` zjnOz6#qWBZ;@d0@^og|Iad>!6(Q=0{jfWcrbkS%7EFd8Rb^SV%vtf)b4TOV*+PD*lqZjcFigPjn?%BGK2V}nCl9|E&-ZL!rWsK{M{DQM(*js_ISPv z*D@Qx+=aDY>=rX-01)gUctA>R1Z5w?XNSPQRX{Y>;&;R{1YzW6kf$GUUEs8TXuDM9 z7df=$(4H0LOA-c#iIcS}jEd7qV;S9jkrM^D#jkj|!zxGHKL+KYtrPsiOVOMJ-5j2# zLtA-Uy&znHVibP!3ki9TT*&N4+xXobXV&A&5pB}20yWU1Z`#_FG(luZU*^vvZ*HlS z(*RH5uU7$1TXpJQ9^dMKdP{MCkTra1@~FG#JDvh;yE}$8Tx?Q)lUW}I7)7YOFJRai z0nEnlZOI!ltsGG603uUaUTzTCMsW);K_GaV6HoCyR*bf(5BZMp3k_JI69O%)(wc9R zyNRefX#~pp(Kdcr4-Y#q9AOq32Pt_#uwDz0PIZ3EBXsm*+%A4Pi3o}!*G?<3U&}rG zxIkF0mkgnk-+g}XvpPr(Z^VJtf!K}Z9DHMyM@!aIn#A1%#d)~lKksoptB1ve0oR{2 zm!@UUSOQwj3|rLIQMd1x4znUHIt?JxDnO?RK)E(Xjcy*gbs!GhIblX9+f7!C)~rTZ z(90|spn2#Zo4l-OzLqnnOS(RhgZmD!j@CfxDhejlnsN1zl6JK21!Q@_~z!oE2EDKv-2g_1;ni?6hk0G3xsdZG+5LwRPA+#Ka++wgV@xzF&t) zFWMd7?D&pW{Qwk*-!|p^*!`yMu}{_bYHA*3v*#(bXg8PCn)>A2Z~1t`0qyY6R=;JO zeh1t9PJ=b!AJ#CdCX1$uwytkbvjRObr6vLka7xvGkYV!Kw3@ovaBSo6c8YJc4D^W< z!??TG;!8G-hc5!hu+&GdW`iW0pzL&Y{W_DfVT>*fiR&ozXw?Bk=8ol{TLofF$OeSn zb{^VV!BQ1H3l`9-$5kFGRO~cRUYA695H{l}sV(i1+mR{AwG-@ieR3)HkXkMgxqG&X zX2{H^wl45iAFf?*iQz>KZI=T0lC%N`!}lNB-r`quc}Tfnw~Mxa44O|E7cfWP7)>Xf zE)BM;0O{aXsu%pGhw1(OcA>l2J z2(+-=HQy$86H#~42$c1sZTzwx9(GOt5^dHvNXejCuNf9(PU&yk7OA$kzLQ=2bdoK( zy{`7n5%lG6xAfi1M{|03p$fP+`#VxERFDCRV31U^7!z&gv=5yJPhBrJgECn_!{~WvYn3_a>#Km@cH{K* z1$jnvdj;&YYV*;yKJ{FKdx<}fyyn@C?>L9o;fG?-o`<&Qp{)#)&o;2!=3?{U(Al*^ zOSf&_b}!Oq(}15u>m7%O*Ay+cbJJLWAUd`6d1zagE#Q$oU2h;AwS8*kx>C|<0L>*) z?lFMJj?|kfq+Uh8cwro0JHP;&+V7Tv^#nAvdc*sWlngpWkhkUZ-D!C6Pyu;bi{HU6 zkL{3~+a?b`=5lb0g5FVOLlB_ax*jFbPp+|9)qYV+7Bw1;Z-ArKAOHpMKso5Q3}0Qw+;BF_<^@SBmDU$}$#A_N(y?T%RrX=I0?(ozfkkMVqpSeg(j~^SyyV%?gB$G3k^xzkhiU!4!%@ z^UuGW)HoT%p9iEN2&8MXq?@>=edcjZvhu0PltY6U8TY!E8BXqTl z(;ZJ(Ldj#}L(+FJ!%LDE<6;Zf_v>NF?IWMN4IpQ$egJCg^d^^!cfBF(CXk#A755Eh z6d=3B$`h}yPv#?wrT1E`g8Zwq5r%?)Nq;BBNmDNu@9YG)0dqid5dCOtzkw(ykuh#f zNpWguVe}&aS1rbu8U?);fG4Dz&M!fY(6b4W=%upeA}#?^p+>cK)hx;y=8ctUoHp)oi)sg(IUJZ zKQC}IILP`dQ2HGUsDy?VWr1W&JVpIzM^$vNtH%|=rj33|yYa+2PQjAUN@{epa&r_o zfYM2}EPCCvp!^0&V8*XEc=@*JPj%T)@+qsf2fVy#bh|*eE&!NwVt(r{a?NdI zy>FvMF?Rgx5mG6Sxqpn=c;O?P53$mJZZ4`?&YiME`RoQjc3l(g1-5M!O|9wQnJ3Dc z@9G^yK(krn3Zc>6AEq6}zZ+T#wEN;8(4R;gd|^!0dmb?7;TVEw)z&uC+nOK>xoK9l zUvA&n5To%0xUAd{Kmj~ZxcY3cauB3IG8EW75;F4!D@#6EJHbFKgDh0z_zF-#;JL>H z+%@I!&`o|J1aCwtKvhDt0S0vyGp6-4?32L3Xifsey_8f`N02)dW?j-$BLC2I5I@9% znNus8mSxxH3o`ArYID&^ed@X7H{^V3Yrpvjfb%#i+beZTpP%=D(z4iGuC`T;10 z9bEolfME-<*#u(ZDgA6xhqBr8lv=bl?3()I+>7(UDWD3=!$&E@S2Kv<|CF9A_w&$p zI}dGbfPntiJio$6&)54E1oz}vURCZtru=VUgsv8*-fuMfM!$rTHz`<39n3H=^J2_T z@7jHi`OOZO1~rhgRX+d?$LUQj7w>vQ*i8X$@w;KYF47`;r?HC`zIJ?MQP!;kmslPW z%|`6zrao;JGpsCwRqO=EvJzYsL)7-H0sKbp(alq#A8mi_&6}F0e~C70lquz9ktsRY zvR*SR$ZY*F%Kgz%{B)8ni(a=-79x11D&dxK|ATUP3kR3?j08Wbr}RmH>@DOzO5-v7 z7aXDZRP!-$uAtPXRacnccrUM`6Q~PiSG4NG!N3WNCx4>X_scUf2dF7AWLjOJUI!4F zVC6qDdVy{ohy!;@%rB4cZn8?z%G&iMIWaV3@o~Gtc~LiTIwV@9LtA}AkqyAT7|1G- za(`#J!>fPnAMs?+x3*Tt$`lZt6T+#>0BW(dLG(t4kZ!N-*FU$ z%}ujHN5T>tG46*lbhiaKS`7kFTMvM|CxDfMAO(`4!0wTdnKxM3M=RMHvGlSKp37b) zEki@#D5n_YM47t>P7*E6$=ePP(Kdcvg3g#wGy5cfR?;2b10IjNFhlsn8nKvQz zDA>iH$3qs`C=+*Uh(kZ5}T3PACs;Mf0m^ zTk-YzJhYX`BTYZ&p{)&&lfLE(JbM{<&9(S>VypKXTfJlOOL^u^N^Mi0c?NA3u4d^|D4X;KlO30c1-GK&pvKYJ4?wj7RE=_? z^bnu`c$yPO@jX_Iwy6*Kd4Z#!aRXNM3MA^R^gj1OG{%L*Q==bkLGnKR3;)_Pbjz=I#NPt@;5d zhzAmPaT}~01jXb6&X9yGxxva#__B4qf!t-0y-Zq$25ZD4$nyUW?>48VUT<>wcrW&N zc%G4*paANHnuqwny|_z{sJ}c|Ps2V7U^gKFvN|PU_9K`eWl=LQWL|*`PF#A-VUC8D z>g}|W@e}Xop>2A7T^itPmH%vN>sDR|oeaD8GM+Ia{3cAf>@b%vh@CJ->A|gkXd49D zZ<`D8>$~Tn?Peu?*K4PiG0pm^3` zMq#E^$wV_+$$#yM{JK7wk1VJ+YnWA?jaWqRPyeCmIr*oTi}#`v@H`_ZkEryct^Ec< zp+v@bTuR)bdiq*un17?}g@gFB6Iyb69T>_&0H?}Xf#nL|N83`LQ%=cTZReMG)#71# zc)uQocN5Te740TZYswyKqe*80C8yLZT$rC+fx#)ugIW8v8NINWH64Ul2S!V{Y6Yko z^Q>W3jJBx{`8T~A#Tpp4%`<=q?*5@z!jG3x_yu=PJjK!K{pP?Z z{0hf|%PP8>ac@e3;(^qD_I1-(G54w~xHs_c7@_W7pD$%spSE4$#*X<`yk4kuMXNp>3|vKc?k0MD zzdR!&=B#1Jw7NpO4j?iuBcs~|x^*C6&WZUgj_>9MQEFC<_DeEq__rL|N@am|Q7m~x zHmTD3A+k=UmUE{pYBs$pK+$ZXy}-DwqN$ySw$tj~Ep)KNyM;N;-+*TbV$xV+{Vmpn z+%&7&?=9Om@dvnU)ek^4xz);h0$4SHsP54fvI4@-j7ba8X6w2>yDTP9S!8Ii&hY?T z86Nv&q4CN!0AoUSfK3*474wp4Jq`OTnD~MyfR0jXA~*&Vjb>ov9~=(ihd3jsx15Y+ zsoZB?=b`Nud&X^Uz3iV&^(HGjoVCfu>+2+!@%e(-31gHV-1>*M`lkA5`9<#Mq3vcR zedM97RQBy3+Qvb0-hOBW_~P%Qc)w?zoHtv6X1`JI82nONc|g?GGQ-6y?fRDzZcYnCO_>Q{qSwpl$@_0geU){?o=vbvzUg;x{#Z zh^=NpZ}D2n$COWcRzNG@&oca?6|kNkO*#u@$umwfD)rW%t6P6R{7ijQwu{qS^fhP544MV2Y720(GahA4> zjBXd`)&&4_PR#F%9NKQ%b?&{E#@zAekwucSkvBC~S}OnH&-2hWmo%5QJnUxO_W!lo z-O$qIdiQ-?;XU{A*m=Bn(eI}%zGESO=5id)Kd91JfACS_^3KEl3sU-1Sy}{YzZ?E@ zjzpX{44GE_02IVB3S4_Wh6vsS5_v~A$DI?xKQf4Ni}s!Nyk1Rx+ANaN(H&@(4YzLq zS99i$UM)mN=$mf=n=H&Px|6?0ZK}82Ky`vwP!SS!=Z7@ zmO;m&Y1u{`7M!V9zSH$dJ&iDK!z8*_2{nZ2yQ_l2hws5P!c@ zc3Dn+zl89w3G_=MA$AgfH+{+BHEPLtJopWBRlDddI_dk3Kk7#%RXn`Zsa&*b!oNgm zy8R99NHyCl7)2n(Obp?GM8ArJvJKQ4b`h<klHJa=$$#V4${c8Q_b*W+#Y-N$11N|!y!EE9k7G+w*;McQH?crlEpRy+c`mZ z@KE~=;4Ts%XRCeyistnumydV7A#4Xm-aLUZAvvQvtO9}S`ec5wji>IYVOC8x^0SUw zc)c;_^aN3q9N!#O`q4IiSr02w-M<8zH3EbUG~?d&`V0&*E2+_K;G~V;)HeLIm*5&L zKEl~ae%T6y@5vl*Sc0e?z6bSo+aKt99_(9x(E`$IW;Ud?RCb$JM=Pi=DtI*6(IFKJ z<6YB`Y2~1T@JkTuD5LTLRlEXBv;ZP2O(5A5PZr8{lNF z@l)3?BQ&3QpPD_-icdoj-NqX4v&$&C>A|f1vZ~o+)^bUht@;6|R!FKcgzbWr$1?&k z>6CJCZp&6q<}BN}8g^ZuT^6P`r-%jCIUWVqa)g|_G~<jOZONziP z1@aPywqeQh=wuDyhoWD>Iy$ty$uECF=q9U+rDoxcvRHb#BARcHpyf?P?)sagDff4l zyNQbGSV(*N*hAa(lq8b+JT<3O*URr??r`j|*61S-Z9DFMEGthn&yK@A+adhj=l4FV zqZF53s|Yger~I0{^R2rbqg8l;=k=79oqt-^{D~ADazQ=o9nV^x7#jb~4`Ds*u(>Jg z%KeUmPVF~@7=FGr1jw2fcZ!%9^5FTrMw0AT~o?fR~cGcd?vN%IJmmAmhxjo;Kb zwxe0A1+0^t6?jAiK76#FENzl{1nPqp!8Wj#FXn*Jr)tT9cg)9W)V$Xr85EB7w`Zl~{UaL4EwA9l=}{ol zY7l^$#*F^kwtY1mzxmj#16lLi9@?&1wTF#OecCL7MLMO;;p1mhPT(#+TJH6sZIYS( zh&F&cjcxo|6>VMLkZgTu8%AC#egl0F0X6{@!tNmsjBnfaB8Rp+Z%<%&_;{aav*%d} zzz{^Yu}<$ZUfu}h;$3eZt=jKWAHY(GOU-Q64?wj-QkB=&E?9XyBM_5LDF^3vipIsJEKOl$&);S&p|KxvH>!3HeLcH^{I6Tcs4Jf(}`n6x5xTwE8xWupmWdZmz zQbQj_FhioO85qK^o%p1g!*q$!?UbEX(tYB6dT6^A$4eaAu6eGH@5H7)a}MYk1^WU- zqwSgC74jtlzdW>EF!K9vh+24~EEZ6=!QrF4p)vRO|Ew>s8apjoosFNY0-t_FKK66KkMR9V z`3z6a*1=zQ$FLTQ&gbds?>fr?%l(dnN$od)yGVeXt@;5dn%A3LKHl|)upJo1!VJ!s zy0(+;3gz#0-@6qit3`R535?^|A2~2AYG%K%hpKGe`%a z(b39HFb{*aQzCn(1?7{R6Ewg7<4>Tdcn6!g2qHl4QBTC;M%qIF%L43diB zyRLUkpusx#n1X*wX$Ke?O@2{w$VQ|F6fFnM+OJRCjA?3B|3WM2j_)<}K?Eq`7%fT= zSjcL%6Q2aT_}fm2YCElr`lMEK+E$->`lTRnxF))_bwFWw#3}C%SjT@JnToRzMki}u zl2P`yJGc~u`b_W&KezbJ$9K0_UBpuy3>Mxfi#%cwTaPH3UXo1^Qk}61<9}5K%3;*} z=GQ@VMpp%>N=>x=DpKtVT#SrcQ&Q`L2m(CJ3H;j#eej{}$E8xvBRr*Vx&mv9N0lN> zT*Z_JSrq&^pxUauz_V?^UjVuf>A=Qvf!WaamHS)_n*2RRv&M+YI||!U3XTI-?KgnC zNPwKJn(&Ju>lN~M8OBQE)r|F}^%ABzqdTkuKv;}X7Sx+H46Vt=!2ipOvHmM_FUq2l z>E$SeRTFLFm-Vm`)%{DbStCH$KwC=f&p|UN%HqJtBXsv8lY?d(f2a`#T2y)+4fn&s z2tUa4eSYt=>ZfSqokvT3wURsAc}_mxGcoE3OL1^)bGA3{93z)=g{`}o3<+nZ`*4-wAB^J$Iw4p0&a8K43hE|`$HN{zo`81Y5`^Cj%#*vvTDP~ z)^$^>ziE5uEh;q72N5h`#*z6=%E4_><75>79|j*0@X-8uWK($tb#UTA-zQq{dBB9q zfcVU>t!0?R%VmY!^kCM0i>hX$amytUtp*!k)e1?~Vv;9Vc?eP<84Bz!;o#hEv2wto zbzPtAI+f9PUGJDcgLUpP1^@gt$ep>z2YF6@(OIf6xoSXBbWpDS`oztcrUv_mr6hg~ zIz@mYCjY}b0t;DTE&jGsqWwP04EvlGj>N9;Rv){rh43PWwo9&?1H{p(v0{AzpwZEx z?Ja)uq3yAi43ak5fPvHU^U2~d>~>L|&}Jhn1@~e5S0R=&sQDGi@pW)yIym}fvR8Pp zL(^l2qw`dxBmld5Er6PTqp5CUcyQ=^AvP_`UPmZYIvYP%1>6rx=RfmeiAmxI1#-H5 zWCa|+(5KiE_*-0Hlai0b%(~hhB}5J)2M@L10PZ6Bl=QMy6F$A^kA8Cf4ytWz6gL+i z@@K7hoD%pIom*aoU9@$50$t{P8CkdO1q_(W3KB zjrFh+)%{DbStCH$K#xB9ok39+OPWWhtlWJkZTzOjpQxf)s|Bo+{A?AlQT*JzWZ?f3 zJ>K%N(&%iw$_fNT)y!;|PQaZ$d5^pp^ro4j?jZ zf;2k#?CK`JT(NJmVzgQepVxo#T?}{&i5%Qvg$S}utn|kZ|EV8&Th4V^+yQbF2P&cK zJQ#hy95AL<_iuplob;i&-WfF1IHYEv4nm`&m3tRIoNQaRWUuG01NupRl?p5kx_gTe zw(YljZBM(`Tmd_+N{dgx6n`GtPW$YY9@=_2@3FWYmWTgC80VpF9M|9E2U^aOZ}iaC zy4R!8-I#EPVA?%u2qJ5CYV`(5ZJplYXtpzXln1cKF|BqS+y~!2g-S&7(8~X-O031LH zzryi}n=xHtnEkye2}+%kFbq0Hpm`o&2rOjHwfNgkiT3*}GwhREh|9wrYIIALb7ofI zrbb0!bF=Rkwah<_&8q-7S`7kFkR~SKbo(tsO*}iwd}4{Aux;rQFkyoh#z86&Z!kmWC^V2k?HTLErsEjk4K67`)&o>{YqG~Rr$K)(Uig# zVv|<=0HO|J+HWH30vPm^?si&J?Iiptv4+^>&mYY%{q3??K-IV7gX%f?pBK8@y=&)K z?sdP2VBu;3n=I6?UZ~<9@j-5;*7UE5r?f~(^$sGKLYdG8hL6QkZsTMWf45V1S(=+S zNaaZEwO_x#_5dFopR9o1Apb9G{JQiFjL_B2!R+Ipk1YXqJjR`Zg)FVDJp?-6zl6MP0m3>E;}({kCNpwL7&w$XamgaDrPkYIXZ@DV0XzhC9$X@@Li0S z3IA5w-H%M8_;*7~fgRBi3ZKu$S%L4aK=^Ki6X11Lpg*&@TY}9qPBUd;hO@a|F>TUo zKOcgnzr`(lz$-lC8%bZ%W4L8L=C``+yJ2SC`EC`z zGkc^F=K~fe)U7^?`4$NfjsS?;??oAC)t3t2S^yCG! zP;-YzM2%oGCe%FC9+^@VL4bn;g1|5eMA^aMAbyBNIj2@M5el%LN9r?6zxn9ej`>#N zaLlK%ZVn|C>(@QBmGxf!r`L-e+A4T`!uc;->`&{>^U&7wH9HS&b+~NX8#ogCJw^J< z++C6BuaIXjTQ&|pTlTYZ%G z(XO&Sp9+4=VsR!&Xz!YA#DjtZ$VpQ#7w`Ne4o`EE!ziQGStVVgDxyRIYUmg|&54J& zh8AW&f;kwZ=HKXQ{GRBv+_pd_2Ld^7t?}&*1pJx~E-@%~Rr5Q}9SjVo(#LDc{f>+t zVDjw&7_S84ia6@SwSal8?Dk>6FLG$RG>u&lQ+u*z;TNZq#xgoOw7tnMkMC}>O40h! zA>;=;SrmF6W?qG5dKg6P( zQ!ARt5?Ie8=b^0*c>Sz(ZAhtZpz69+^G(|i()G=u_E&}0%gg_kuj24gt?ENt465_c z)=KL6niX}^TK}@&wAJL#>xWdJSO=2-dIk9*F`Z6dvI3ZW9DLOMop%(I5JHyK)*gal zP#J5tUxXzcW<`K>36N=()=i#LmLRr18r=dA>jIP}Q0Ne5LboQ(=+K=0Z&8$j( zv_diHWe=4($UT6=#l#E4HU*Y5sEXtY@qTox09Cn;Ho(5FVpemIKPn}Kt0OQEa5NzB zZv*7#KC~Uw;AFpG1(sgc#(x@=uHi1en61_Mj0(8dTZ#T;eN(`BoHbJ}W;mPcwFoxp zHJ^>h(i1PA$m+dbJ;bUXfWkSw$>ri*Z}prV$X{qMqiE$9EL3F|ZCxM02tgKVb9i}Z z)Y%A=mCiXk=oTVy#^h)tQ~M1BLbAqqWJqzoBZO?c5(6A zMOz+&%A(e0u@s6~X(!0SaiviNPwSGE!)Q?!s*f5CVEzhi|73M{oLP^nk(Zj^haMer z*S3SFFW?(xwVRXSUHsin*=Y^Dz975VanyT;CBHyW-P$_9oEwvJr_uMj_yz#jc9Yqv zAAqW3vlq;iyT~SxEFZTVMV_sN2I}BUHAutDKk#>1i0JroP)XLF27xW+-l;*M)NgvS z16oZMh#FNy{Y4dO9#&ZZ#)LS?MkzHBOpvmu9vH%RkR8Miu_zZAQ0l!YN466!raj)mguGt4BWo1$00)%89ZG1Zs1_ zjKW;6mhPgh>*J}7EciTYL@SrF5z;IU`iofm+}Q~tJGvS`?pizy>yg85MkF@wA{9x7Omc1#{Ir`v|=-22LfLRCP!JQLkb#L-@%B*;PX$|$Q5{Ya!Z5d*+D(dUw9nUiF8x} zn*xvYURK_p+1xEo^Gnf8S@qf*A#KuYKO2Fizr`azwysFJOl^vn_98vZ(D#Zi^1o!@l#hI55-ZMekADeU5{zJTV7JLIqB=Jz!l-0 zhqgEL(}lV`*gO(2nXbo+-XSlR4(N-bJ`#8TI1m&Fv!gdS*;O%UFn#@_(0&&(aY zT8OAVYU}`;ESf5E4+=Fa5ISb$rQ#PUDgP*f%69Z%{{L+MzmQ-?za7z3+&G_fj2O>OOg$x#}>P}1}33i(nqB9~VE z02C`_lr{hnJH)#Lk|Yj~3xu<+u4Fe{r~_m0upMQw1P!zhm5Xlkg|)FkOHrZKYnr9V z%&N{Jz$(_nRFnrbr){~)QIa_0`%y}D1Y?|1lKjI`1(g#FM_*V(RaY>W!A`4CdQMaJ zGC@4)mO<+-TOKDww+swYo~Kvb_c~Rnt#yB-oi6(muTr@}>|3o@->-{Kqf*pAxB)p^ z^#f28%jnMtsXZb)#ZDkme02M}Dg^mwWz*-w%c7O>to{X{s?RQqLqJu~{cn-YKcbOT z(ZKcDatAF%QGIsX0XA7QRg8%hoo)p}$ILuYc9c>R0qtfD^B;en^P<@}vEkUp-|ZCN zYRx>qh%ChSWc(ZL3r@eN&Q)(0y~*{LM4CUVrOe2>NMqpluT;{;(RGCatuA2H0YoNP zDYm}}D~7!b1ORh#jbcSqpw;UtiaJlkXw|5x&n^qqIlO>YWuv?Zj-;#H>Gu#?6;eMD zFn{FL^NV_DELSy_3kABwhs9eDdK|$LsQHgH=G1f2i9f1oEe%1MDXB6`Wj^_O@1jGU ziRIFnSg#L0l9ijwN{zM7XnN&OKy=vR>iYd)(nXq(v(+E~MMFj@B4y}8pjRD8WF6c> zmZNN$F>9d?GP9?vuFpP;85U(gLpGR&Me4TyppNw>sQIOQ(kKC|-mLwiifQmfI3(MQ ztBI#9s-ce}$aa$!28PcnwUbf&-A>tOnPH#P`fGAiP1c+vmqNHwE6vQbzCiF7Ds0B$ zlGFIb`jZXjEg;is5P*XG4M;|}D;RYFz&s$#2;m>7L)=Dt5x$pstmVfnJdBPAa=)sc zyj93%+b+u3El9?7I#Q2YsOIla7x zsjUMLih*e?jwTNsSUNl|5+G-*egKLlYfik3@^j6m08pC~X5{C3wX}^ks91{E^6`U3 zZ9IB%5NIbzZhYAT_?t8=XHbevWkz>^O|zjoq@vU5U9{o%?kXxZaQ-%bVWrTBpn7elIy!pVdFJFlOu0uBjvC!MgAZJu$O zDHnsO9M&9PeZScu6=xyrR*!xF3gLlcbhpN#0Jr!R$UCe8B8fkVD#9p>vTn3#8-~_h z96tJ}p6lGjy%@9I1ElDTkry`+;9`}q|Jn0ESqoMS1TPaGU>bJ3#z7j9JaN0iHL z;PozQPhDfV*Zr~tA8Npj(KdcDjJ_JECDn{86HjRaeGtJE%7ivB+< zSpdd_c*r^_Maiy?6D$)o10(m^LHrO4Op!ruA{6uTG+Ljw1#}IL_m+aXGS11(uqO9Q!t#k6+z*aSuQ0ExC`=^P^zYJqagdThLrn^JeA)Oi`g0%J=Behm zGLO|*nlK*gGNRq*_dcuWa8zRbixjI@d^bDFembP5!VcO4SpESREks`VTFFoRi~;A7 zA_mb-J(_0FAf~l-0A^8FV{r@Rp#w{Y$3+60 z&_){|Yx!2j!gSPpzd4BNY_=^Vek@4LUA&-IA%fun;e=#XO|-RNPc*0*106&0tl=Q6 zp_$UwL@$o0(T zZ%G96l9(K?+?=u;Jk)*zxQk@Bdh`QOG!ICl{D8qhfI#pxC-5suY8B?nl-Q`mQ|#;|R#> zAbwNh*p6nqECF_sH&g+)66=!E3eZHy?`0U3d%?+h%M}P)h~YPfYdGHHtTIaxhqf}U zJNchp_2HmTvwf8O5$|#v`2B41rQv4CwCV>CF*PPH`5YYDuKA@F%Eo64zeg=v92e^R z9p`@Iw^_Iz$d1<>K5{kTckjhQbH9QLfnTZ$Yj_1}HPJSHw-6z|8jvMbk1J>5DQ%z+ zB6vT=g3#&6{B7GDwHqg+_}fm2c)KiDLU^oBvqSrk(A^DAY&#?-jkUZbda>?hv+tKx zO_oP@AZM$701D%Pg_z_CR!tyKn-WiHVC$fviip-zwXV-D3+l}phL)^DR*m54t#jZS z%{9pCgI37=I$94wT}9MiWJoqZEepVy5D!^DB|@9p1SyM}fw667eGosy0#sy>o5j%1 zzMjykPul{z#*X<`0=QDCvA#gSBhDKRZHYN;bdNj5;{HS1sXGdp(HF878f~-}*tC2r z;{xR9@X;!*Q_=@3hf(vpg#Xw>+a;H`9ojBIT1kzL>X!R+)+sx!r5H}7H&}r@K|e3} z|JeM6$6U{IdwP2D3N-t+ddINlJ@2?`>j3j&z#40}&w-_b$sz%Aw(19U|`y$X>=PnAy|_p$9BYPwPv1A*;}rFL-0$}!s8PC&&NTX zNUx^?0n<)>xF(ATCzQij&u`iumMAKCta>;u)cHHk{l@=nFm7|wTztPHntsnVE)RjL z3BZH)qxB{zMCNWvcYqe{;-P0VuBN_B*g&@_H4&KAl%|qyzs8|$n3lqX#m1-E*5K7= z-OHUuvk8GE$0{4+PfU|_(5G}Mc#!|do?K3Ea=Cc7oqh5G)`)~GsH61|AZi4gG0`<mYuJMLDNdG!Y6>pVgQi+AdZ3%1{F;*qoW-{7cm? z)b0Dld0jcQY0+tnPS%mEK@}So!i#%eI-tHcR zQ=D)*c|^m}Dk&UIOWNRF=-u!;5xgu05tL{cb_jf}&T6s|}~9}gmMs&jOif1@KO z2v^`nouZz0T1W0r`B{Nn0hgQF>dgEfztt+|)6Y?XdcT2f$=XMlR)Dm`2AN1Pmwrl; z0EJ?6VJr?Y4;@%KJT8*m#-|^EqQ#hgx^LQUn?tFv&*7UJgzvZQKlF2lCU+GrUlpKQ zH8rpOdg4OO80Z*^XAK8o4XqpgbTtuxJ16SD7@?!Od7|u`6dCNaX!SZ8?6aqbrl+Z_RXyKo}tPI*pvs9abR$I_8+r z-hnStWRblji|*a5nrsrd_wf%TdsrGpj=A3;?-55PteToPeo>F}(3WL88xO1i-i!w# z-U_w!(%cH#=*u6X`d=E>`S>$bAZ#I~(HySXG2cpxFY-;>700r2`l$EWwB6=nvvWGB zEH7)p!8dIUX-Yj`Ih1XxZ9CpXJ^u%M@FLf%98)#N7DB zF#2kEmTWVwOgyCx^g#quC=)sz7{6`jp{*4pZ-<0~;VdPJmkt@ZSogBo-)p^37TiDD zytrJ8JG6Ro1rCZ#G_F~@c7qg zn7dQHT*)swE3roRkOg(L9s)#-U^6DV#_S)L5(g0?Kv)Q8L=c#x+@p06Kg6P(Q!ARq z&?fRT8ue*gKn?7eZzX~&l^W{{1UUcFCu8v_?n}}!OCD$@_R)QGvR0o?Mik4)=ynBo zU4SExNzRNA{!LcM@jZ)CXYmpL(e^dW`3dK{e+fF+Eay&H4!s;4nO*^~t0IzW`uEVC zD%^Hxy98 z?-6vpV_3^1jk6%8wRM1bvAHl7M~{aNEFB&f$!_D*4?xjA>FrlLwEf^U=ArC7bV z2@J4kYK}>!8AjYudRU=j@H8h5;u>1kJMfzbz?~EIUyRUgbI`AycyJlNsc~$pg4bKT z5Q;sX^sK=5S3usSe{bKHIDLIT^oj68E8yV0Kk0xwk1)?T&6JA~Qw|gkqQ2iiPZ^Y~ zeFMnZsvm$FdcDcz<6S4yX3j>cxA+yPJFJ36;Pr-LjIwa5b94nLXxx&$OOHYn+;8sp zND|j4Vt!F9FbBku-;cIm#r!EH3Itynjj;Ph0IPu>)eCX$aY~NmYIGYoLAZ?H)VMp0 zpsiNv>1@AX1;PtruRwDu^DEkS>wMh?|Cxfj5l_R{P=SDHr#W21@!nE|=b`OVnPlnn zQL%q$yM6zmt&^YL(rOZParn5obWSZ>g48$_b$qcErWM#=`Yl%ex23Zt!OPln35ibcLe6B;L$pWKlf}-%|@9ZAQYlLtx<;^ z;P;j)=gewrju!N{Lg!}JuU8$te7qmt5?odeu-J9dZbr#2sz5Rnkh&yymX5>a|BfY+ zPu8FF+cd}mfpsHDOw|xH4ZeuX;`(>(3(w2o%=O14LG+xAc3 z`WMN4@A4IM-ogl7Enl_Yz?8!e+PN~#&>V#xExf>;L6zsFzF$tP8I$le*uV<&d{#fsc zke{Bw*vklehn#=*+!yNgm=P*P{qfhA6hc7fe%H6U?7LwXq}6`yN!VcVZ&fyaudrMs z&6m6Q<+Kaz=`DX*&_tsz4K8`+Hw!KNTdb~BuIrQe_7yuSP8w#V-`C%FV7{4~vZrWAtf)%gO<2yDeL1FKkv- zAjSmFfMByJ(o~@}D@&f%4)B94a$TXzNMkG0-7(0Fy>L0|c(jmhy*-LD4kDTC z;??-2!>kC*9tmL5%7ak{5Si8kMzQkQUdXmgH~Hm8>n1Bk3#)*j$@ht2e251GRt{p6 z)i&?)d8lwK=ejIrG5{U`2JriS(Ve=$r>pK?<3czfeQ2g+AW);r0a|2x2#xN3WU7ZF z;ty2Ywrt5>&shTfwGa-1rw4>Sd6HjGKezi0VtZ`0UP*h$HpiguZOE?Mk8PL6dt<(y zMq`*BU6=cPOxEiLn0r#c0siGxG2k3Lp<8ZAE94++YY#zDS7ULYJLtf2Y1M*>5Flr( zegJA<85!Mza^;EzkgvDJhs7H+TDS81XoVH8I*Y*dAL2Rbuh?$$(d%kY(#^5}i``3;`2SPpwRb+XUnY0>e;Xu^Q1{?~FPJ4C3_FJVl0*Rm8i!gJaL0Cq z1m|ADsjcmBkVl-N!Slkt-z#C4-i77>aTI`pUVvq6_v8yB4h0SHp1O3Y$}*$dRa`_=t-bfzuhV_| z_U)d#W_qu+zxVg8Z#~XlXP+zF!FebDr;_1;cSsAg04s4dOiP2dgp4XZ=AlGO|B=n_ewk+2U`9!Dg1@iUO0TzSGj}*(htgnHt#QPN=>;O1P3o?RrgNAvEdhjYyDj1p?{@ zBp^ZRSz3h>qHf4WdTpaMo(mS5wd9J)j0zkyQewLHUV?FX(%D>KCIM3Q9omUf7IJn} zO@Wbg^uqJD9>rpOJ+G9ROdVCbXtP^|kj!>Z9numw5UF)n+)P*`1C=;eIIY)ZSVr zYE59>+DPuTD3Z(*zsbbH?rexI$y2w03I;0GueI(t8cMv0SyN)1WuI2IF~)Y5a;Y4pzxbQ9Ig3q_P zuAvg9@51~5NxQXmy(JzDkpk}CrA`a_tT&wM*V=kv!2Z>m1OU`2JG4b?kGs@21Ci=& zYc#@~VsnGrlex0JD9u*AfgEG2EUs`xGOlgeTK2-qRX2nJ`m3^-aX;5ju2?#6+@6Ro zFO;vh7HJ`GAiX`bK@0y&Ns-XrYza%I>b@2SJ&EdG1VVEZBkxd=jQkZuA?a!{Kq2FY zEa;L_gGb(JB|Afm&5MVC(@ppWE1MK25Bcv?Za9HoA^7OR#ee9z^;aHntDS}0l? zo+D}0p=}F)J19w8;8SbL^}w{8yL84H(2w~)VV0H@qEdV45@t$qdT6VWSpN}a!#r?} zn5U}~ZTE?J+ce&rFttqmwp5)M-|vmE@!L*QR!p+1H3f8do5oZa@O6M_O~`vt14ip@9A>8v0JS#M;Eyh|iiArlqezE>9X8 zxLNoFJvp=9tcArW`=ncVZ1){W-mcf;p=1OEa*e9mMR!>+N~G%7dhH`qeHb_wDVDZ4 zS2%5ZU8qQWT0N{0@B@xT;>-Ltz|e<=kYLkPAK{6`mAS>Y+1LtfBfLvktni0Q`@S{X zXEvKON7xk$O?}D=L{t(-L0yyGhRIr6Jw#i(0fJGFv~EtPUWmpP^T?0o5W1$dfy_0y zL_oaQCUU4^#G=r_x3$GV{8gV>2caEX)&$n9?T#YJJoS{}H>|ko5~yjx%muR6Ef|(3 z6slkAyEwG1zLiZ=#@TQpsji$zt7=9C>$Dp9SZ@YRIKoT_@J#ic1mBM}(Cf$uJcx*Kt;tf_Qb|-Eq+@ra~KPk&}H5Bjqt2Kd*gYvE@ zKAeZPdEwWjwFK-B;XT3D=aEPqwlx}|vt(F<+ml%*eB731tKLA4u~imVxFQ*8zUQq} zYoI`6-4Fu%E8TS3Ly~@S#nO4>_C$1fp?tkHr3E3H>edf!F8~-Q!nHToVvtCBFPI8g zJnOm_fzTYq$U9UdBYy=^NV-~8m#QK5WT;!vC8Y+Bywgb72ZumJhy99nE|L&crAbo? z?s!_kg{0^qJhYWlM(d@>SVtQ(ddyi5z^JJE+{d70*v4@=pXlzvp{*ogax9p`>ie4< zJda7S){08NfyCGC+UIAj4=AmPZ!Px^Bou zdTpb%5tms@u1G@+9x_1TM0Zr=@dw+0V5{%ct1KOYI|N3;+x6PIqhthx%%#wL z*L7_dZ7!)0l9|dbaRLuSYHc4IJQ4LQkPS*MR8k}e*i^}>tj)1=p)>{JJ z2i-@Y@_vNu2+Y1mBG{Q4l;)%}LTfBEb?!ift#8#St6lGg^A;r+u66^&4xJ#ic9GUK z3?a0?GLL*eT^-xBHW1x}>$99XcgG!lk3`d(5@`=a_WATpTZDoM(zS9+v~ua|6t6_i z62Ty+jnfE>jDYW=i(QBZ5B?Cjas00Ro-uG3^ z50E5*c22n>Q(doir;#aOW0xSlF1phK8q!~>ey!b#^mQd_uGz0-rBg6a)~Nb*-wW(4 zB&nXu{Uqd|!-9JzID7^3Lj z`U%Bq*z~@)rnL*lDY6ltH7|OFDU#CEo68DU;c~COv#z3)yt7^tSocEpY7}h`N-_-) zJEl`j6*1&e-GVA-cU$$JRg#91F8fAB`kvODar|wMsL>i@>x$sXQWWN z6?i+UQqfVUdn~A^8-%nqm`fg;ls3+_FCs9QG&br%$nwc(v=jo-`(+)Ec-@vT=17AX3z$%W@O(Pj-syh6r}J zq@9)r9m6)vAr!P0J5~A5A?{OmuE5v40BX1-X~mngdkZ?SoNal zWq00A@+zI)$g4qh0Te?n)h!qlDFm7rQF=UOV?#-o{jHs{=A{Td*0Q9wtz54?;u&Gg zd7;^rON0B2z=+Dt{E$J&mIT!G#x!8bM~a>*DMg@`D3)?X#P zNfOQPCl@SC6fR^Cc!E}Tv3MB71V%qhNmh}yqFg+s(OJ* z@emlhCIc)p2Gt3{kV_P;WTRv;13JCp$2v_C76fT;vD*Qf+`%thuQDYK9&nTe%f zMjKl)f1+-1&trnhy2fG+*RD4WKqVfoDYhOQ)>!S=*9Iw>D6&^Qvin6nuG3h1v^hTfD*vc{}!#K+)E6F;Isu7)?2NJEDD+!B@{4cbp8 za7B)Gy%rB8Yvk3Cx`b~R-DSZjkxNo(ZN1Ql+nW8Yow7zX%7#;-(+G@Dnkn7M}*>01$x1wa@ilnCbzQU{?Y3%}$ z-0#RTIJ%fecfw`Xdg|-)Vw5?Q7K9jrZ1?5`z@k34ghfd@>otLOYXceAqDV3ZD0a$k zK~!A=dccAf0qdYhkk;wbxxj*4P`d25&WedFUrMjj%L?wac^ZMuB2cnP`Jy(CxL((E z#0u`QxCh;SK8@;_bo{93l^Lf#Wkqu9T#s7?bxn4jEEPh9wAE{?N4o*SsvVVUnL}Gw zjVQE(#XJg`G!AkILE@S^uf&m!E-y@rGPKp6z`8fpNH=|VvChJ~j%sbSX;@p=8%zqx z6u^!-5|`>0s0P#A+Ms@2RGsz0fc@U2sRRIm0h1}wZciHzX#`HY_#y4s<8{k(+G+d( zNM%A9v}eyK8b3|a@=GK;O53hC+T5;my|wD8ym^utW) zM#45#@IbBBx=6x$e2VY%VnAF*M@my~%oqw6D)XH&sGtUQ_@=;y7pj+O^tcMtuh-P` zO0m85kV_29=cfGkH$hejS)D1{L zg6sgZQu*mY>jyzLV|Ul+I{eO2#TcRHtJ z^}GsX?yuTKn@cL1WSlShMJ|cf+A@vF+ZYDLekv(nNDx6M{LnUvjrXUFnlO&av{(e) znch3&Dq34x!^6t{1{ddE%V6IsumLpc2E1}xR+S2H<7P09VV8__bmM4j9IftT5HjHy z&q$+2^r)F1a_bONZf-epd)`*!svz4!HS~^JwI~)9B^y^Hs$qaY69|8ogQ&8#tp|Vt z1}gJtqcm(<>#3y)j|19kX!;%qwE4pe0Fr08G<;7eL60eQf#9fH8z^HfiX?0F?--4` zqi=|I&Xc=t!6=bYs1BV=wX{2wl>TfgDV(;wh7?kXz|(T<5wP4mcFlLCa9_Eb_J@q{ z)jU<&`%s@I_fZGEeX=f-&Io;_Q|eQ0B(JS+)g)@y>qn@okWg~rYBxYQ)FZ7qQBIq) zZbf=`(>w~@H0zkAwNXfdt^ZzbQ)v!Dg}2q7z^=tXWU0@rBUwgOLmQd8-e5B6tOAbG zrDhyWXHP@*YwbLV2kcie+Z_s9kV`6-2nsl@PkaR8Miw$ZHsZN!;-HUn?^@ESfRhvf z&uOQAxEAt+5=L3Nm#Ofocl(*Cp5F=Cj!JCT8*OeMmE?MSXI$+Dh|c8EK5CmE({bYh z?)zjD129gnQEkMPSH0+BQYiEHRMz}1FU%{Fw^k}m4^JU6mwYnoWq}R&&x!9+qwvsn znr;Rz-l)i>*3t{r%P2OEGsV3WD|XCLxMcCl7Q_JuGCJu;h8`$&Gj1LBmxQDTiGR&Y zm3n+N)7VoZ6LM61$wCQoSLY5Su%55(G+OmWa*VCA!S27HWD?06i^ABeyrokXn<8xTn3j76YU1Y0}vPaMHU^Yfjfp# z`hrnKw#e;yTXqyqLCt+mBd6Yv=)@tqAP~hzRv4*nHnOZe#%Z)ETb+rmcYo8fvYJBy1dm*1ZS= z(uj_frry|^K;hzd_FZdPH;igfi8s=QwGF*YBioW|r`PjpP@NDAxwIC?5mNQY^+0Kx zN;>R+AP;T5I@w##3YK#_6EF~AJzw2vkjs-Mb4K1VC-knf&XSF*W8<6H8#YOHI@&2X5V4y_h>1))3OXrL>sg-q1l>)BJi_@*S6Y4A@!5(c16^ z4Q$oDh=kJEB9mmE_>4FLmmsfZL7;+xiiR-)Ag;$vgWa@07O@3|HBJjn(c9yyBQ0ng zuJL$pRFrqk)+Jl@!@-r|^(Ya54!w3pW~p6aUTdxhF|H*6bpsNRAUnY9c+++xz4@I> z^xO!pmc!Y;H*NjGMLN@8(RX%24y$ldc*?Mb??m~2!5PbbLY7pl6?fb8w!DK{&#O2_ zWrygR1tNzQl!4eId`XyvwZsPgl_Pw^>unB&XE)F^NhaJ04+qVjtmrE+`dN=HN z=BaT-3a9y=w^Ak0QM_p@8JzWwTV=Big{yS1&nS@=(ac`pDmSAGeGg=?!R`}aJNe!4 zJ)_7lR5b*u@9IS$f4w^aWY=)KN0N=I`du>7BpW3%=|8N7wp~e?p1M*?)U8no@B|g> zvtzeulRi00`^|4_!3LYX%sm#&Q=oevmf|QfyAJ z?)By}9yktmW}xBqNz;#Vhw~C>>)estmAEQMmlhXDLr%|I7q!t_Q?fUrb^`>hIjVJY z&JI~d%+B-?SanDg=6bXDhuMYp~cr=-P2u z&sTREjZH}2t3*|14F$Bi=eeuedFs5AEY&%AXUxxMhqA$A?PmNP=T$w7m-jJTV#^V6Q2=B;1cB3 zEC^IEP}LIy#Pzso7BuaTMQlO2(xfSc>Udg_7Ss>d%F*TsD|U@$$yWW$bY*xucf*)z z*K22F6`t;F8wKHhdSoOxi&$O@U1>8hY1`GaGp|s80y`U20k|O5~DMT6ZZ~v!Aw{zG*uu z%nu(?UT4BFJ2rbmQz7S=am!wl`SkvTM4-0caFJGR(y1Zy9CFu*J97JsaAil~6x7(~ zm|pvgO4fmjl8q~pzF~ks6X+-oZAF-Ql-4X$FQ~2p%BHoRv`u*IlFBpX%ryJVtAg`EnM{=<@?_OT(5pv!(!k|dCr zPT|fHftb_k;f%m>_w!*hjGWP$;M4mDDgx~@8>f>n%9WCd^(iZoyOJmh>YD64Sw>D{ zlw7#l4G^I^L27LpQUGQy2oXwgCf~PS&7(l{CR|=cMmD;p27?WmnEe%gthf56$VvB@z5cLp^-2jvaDjN*xY)Asbxw%Xg=P6%j{ z;f)=W^}IcY0vWk{<{)R}9dknOI_oUixVj7w{)SDG@VV3sQ6O<0m2Ns^&`XKwI(T6m z6898p135appkV`I>l5^6GUd;R zyLKtrP_sbIqIF#r4bw>2ho(q|4*L}is^VIuNmD4~_$sxFW_xPhAj&EMoOSN?k>Ub~ za*3?#dTl&dgJkVh$lyZkNmn|_a0Nsf!GJ!Zx{7}=1bu4cfV3B(D4iwdPe*Wxtbl)4 z++-qet*5Q)46plc%ctr%@l<^UMohg669C<)l5CmH7H$b|mST@PBUedKk7N^j`Iq)k zC)0E80y&~2fr*Y8AIQWQFkmr5J(1a2xgmc>M1c&Ky66E5Xx4yKPdp;PQdbf))Dvm; zmwYHF2`fv`#xd9ZTb@zI>=>19)aX}z-<_zMd#LDQf|E0pE;6A#4gDUYakUsgoTp8m zy(RgJ<_sfl;ex!44nqvrqZ2HRKSTk>Q6*V>c5&T>h*X1Ca6R!67q;AdfuBQ_<=0_( z6eBPQ?bKhO-6cQ_#4Waje|~lGbAS5}|IJmAB*91R-E1~<{?p=|#^A2L!>KV(<}-@o zP0DX^EEkfcumZx4QEYE5E=l25o*zgczn)J@mS~4As(()jm0Oi`*dJ1-2$M=cbInT? z`T*94_uFPaY`}&usSgVj3O|laslo&;nIYi6 zV%lqw_LS$^?B8ZY;yc0-z3j_Trsd~tQdqnOOOV|q7>dF41mu{j=Ss#XVj3bD0qhth zBeJ7v6%E#Q3kdCyMKJYOd~Q{Oeqr&fNoJ{)z-v?_KCO-{0@`6UfuVMHhc~T~J7tyr z|G$3p5m0&Oo=(J*>0kRZXFooZR^8QmT}Zfri_R8TCvN}Wex-)ouMRkCrl z8<6y?N4bW(K7nmlxk*+;vT~JGNd|3ecozi>^?$P3;-vqabJrG=$M?Vfu|=#cTOXHk zJ+6rF9`8iF@PYKM0K-}$9YxGzd4gaJHkxkg0_WKah-A#Yh({rrMKLC*Z9@WYM^){j z&80{oBpW3%B&za_n$h-~k}M%BTk|r5AINKZIqc+F9xEp8SK4>qtV$j)E$+ofob$0&Mk#J%4I|mYcYAh^weWZpPobgq>DEK z_ONe#=KTC(-ot(x2R|MnD=`CCXIZ45i^U`9!^i)l^LQTZ9~DxG$4VL~X<>N!B`@v9 zJAwilEcQ5iMbdiAweuU@X|KdB$;FQ0U4O;yY=|x{)h+0krC8Okb&3&?4JAvZcWX+F zlf9lONo8Ee)`--Ee3IhRRrfpu64p`00{3ikAagGf3PEW`0_%DgN@@)SwALX*3$Z6z z-GBsK1IaNbO5~fU*^nYia9xF)O`yRAFUN4r=fNFL&SLq)q3t9ES`KX?LEw-gkAmIB zsf#o3R%k~28!Sz zq?|`nzGB&+Q9DM_;I1FCC90H~(rVWmN*9^Xo`xPE8dtjkB0)X!>@7*(l;beO10NXx zp&cv-N|CrsqCz|C`NGX7U+qG?q9h-|p#3~Kv~}*>><@q8|9c$*gn>45BlmODYmkO5 z@eGHy^ILQGnxA<76EDBjL%alkA%{y4?feS@^7v2E@qs+Fh5hw>3gXJx!o+ZU%Ank* zhqfA#lUuhO+K!v6kIW_Sw(}^Dvm|qNA!X8`rj`4O3!|3qY>-cDr~A>o+~e;1CW45L zIsnOP0BrGHXkS6)@Zs?_(3RZJnlX{klmu*dRweQ4`z6g7U*WVQ3Ix{mVm@UtLIt$d zois%L_X$BsGi+V&nRj1)Ls16|LGAI*F~&DAY(7b^oqM6ED$dREj4O7-MfZE z+u*$VZYZG~ELkAPC@_+PG55SBnMF~_8vRS^{;FMcmj(T@hz*UpYvo?EpSECnr39(g zs4BPztvT`$%Kda}zbKczqr0B(0|!jO-m8|!fSO);cZ_m{*l>_P2DW9^j&6Q`i8gfy$jEax zZMnxMsXKS!?TUOdl9wO*q?gsbacFDnC`s3=VExo}WU8ItNTaSp+hLbr1iP~#y2}FC zIHEAWG(ozQEKO8bY6-y_m2n+gBT^Fs>Uo>HbX1g80yyj3x|ayRumo+m$W~qNLh;s6 zKx-W`v=Doe!TgA(%-re&K(cm}$(&q5CneJrQ5o8PEsM}5T!F&CosLqWau+N9ZgBC- zaZHm`zXm@>F~gxP&VypR?iw_@2@Y+=2yoALWP%OEEn?obQd#h=vo&&U_t57KCzxii9jxOB{2hiu5b;x zMfY&yGeEAT8RYgpl=j0@U$Jb^s2!tdKQragYN9&ELt6w~PWfWCPCSyP&%HH~^u>or zN$u1#Q3*47|Mfu88*%9ovt&ewS;P}F8AS8js4mQ2c-;%HyMg!P@h2^>Use@;wVwug zZ#Vkv&86Tk{68Jq~deSUk(^dQm(lx%hVWmNlaL9Q#m`ind+Et(-rf<0_a#)jSBL# z`G7_s&~A1-J2w)VGl@4{RoSF8xREhZe7fcfL21rUkh)%`E-*$|VP0!`Ld?t-14t7| z%KCENC@$9w*+_5NaEjnzE?DM;5|?c4j@&u-11@|KsxS{hZk>Z=^unk6zDt`poh(t7_YGi7vC?V>HpDuiUF zvO`(|Go%_?z}l6Vu!a)rlq7A9DnU;#4@Lx-$aie49NHqEe(NXx2}JmuS@HGqs^^DYCa!d(QnbhIq*D2*}DtZ%U-6?(uMO3FcjXh%2ZziEFT?z(@+3 z=j9e1-Hc)sI0^$4(#^M4ApU94Vy`4_$le_(6kzW$?+mt^fR(0dm?`lDwio-`f< z=%s)D^!s#Y3UI(b|C!}KJ8pkz(F0v=GAAFiqm9!x9&Yh?ZDmx=i6OKv$vpVF8|@0(zMT(kgY2_&!DH#$@zFPW z`E@w@t|(IUSImzhupV>m{6-pe9oqKmB9`6R5Zz_LD3SP#kc-wGC&NpVCT^n7)>2Cd zmU2mj!O+{|t0Pr$HSoMGLy>^)Di)MyliceYq+qm>t-9WvyGAtB2$`U8d2-YZNWcV= zH(IrTOKu|XX^3LGYw+1d+l}Ueynui6J>e!-8p1&iZ6|&ak{1`)MBma;&&0hAs%3>w_!5I*Ei@H`9z> zKNABybtN%NQ8Kf?bVNb5c$vA6@7g%CY#h6evSY`n8r(b_yibR=u&Q!8=~JwO9@+xg zIIeTi+!$y~%a6Up@m!MjDe>QijJD)?0yn_O&m(`s@4Wo-%Xrgv4(v?#2K}al2zCgV zFFpxxW_V@z!h7OZ#kXe9lM)XJcpLxISrBSKD`Cmto-4ld!BX$dq!*Y*6m3GFvl<|K zB~hjI)J@R?7W7CeDAm8Gpr(>MQO2hIVWtc!0rzWEO7j5Lhxg0oG9PwZz~FB;D177o z-rt5vkSv_faLkj^@uG{k_mlZFE7!c4@jgR4u0i2mf^c2FF4ZhEk6ki=mVRTx)fDn@ z+#fz1Zip9wuCTw^r;*T6l_r|((^83KW2SiCN@d9t2(0VPnM~Aho+kIanaryiq^oEQ0>jOf)wI?z0?%XmjDw9PXz?TF$RL)Kr zvGk_x-k}}Z+R_lAMON;pqGsGD>-|6-3@>J)_;i&OJC&{|Dp{j{$=qMHi?-xZ(Io4a zMXb(MT93BhloU?eUYB5uvf-5It|MT*v9YAEF-L=85iS7Y@h|`S>Dk}HVGl~q3m@=E z89$G_S((J|ScyyX>{lc=#uTLb^ro%+Lb8-iCYsD~*H?en64nKjwPGE2T#!3YqPw<` zs=Fr55%Rs!1h(okY&5*4rU2UYaz?Lk^fe=q#uW&t8<2pSt-1Dj+z6&_NTMCOL?hTF zc@h^s70vJ)jaWHg$aC_c)GeOGAcYm#i}@5y{5*0n9sLdAngx7f7gJ{R24gi(0`f&k z6#02%FAXPh6_xIXE)0)xMKUnvp0^~kcqmyTuSnfrwTteupkEfTp;2qJH7bmo?!e0C zgtnx(nI<~rT{O@G+c7*+Y9c4 zpZ)YxH<1@OwEZ_<1?dyKX={UJKxU@%;J*FIG;Z&hqhPovfgtqK6?I&+ujwLm5jREfBfW` zD0hR!r&C3o1mD>H0{lF(tN%Q506zvTHsdcXXCXa}lQ)1?gJLTL%nz|Fm*j<=W>%vJ z{E|cu$Du8pNu83MVs1-&nE-NOFzo)=8j+efL3`eop-4b?6${Fs@+#53RKr49hPLHhPmWs7KM8z`z#y3&JS6 z8+Fk`7Ie$0U_9H50PgBaV#fPi;Tm#lJ+%P$8Ha1I*6}tT{zKc`>z=Xp>@DfG)T{-d zWJqr>94I!rh-Mie3U94>jv3@NTkrC_dLN0`@Jq-zwB2()DWBeQ(=%>%P)UteVHqfU z?Eq5zX=@DkYu=?Z)*#Nw({(Xy;imYTelG~Ur_joScLDd7(?eT^$DYi)hw9L_xARYt zT@jdU`-I{og4bf75J1GB8(rcw{|ZeS_oKN^2_M`D1e(q@sJ`PFmpWywX>c=(d?h-T zSnYa?LL;m&uQfd(mf>v%WLPAr*0w|jA{c;;^m3!Mz{)wIc+wvooqQ<+q{JujORO7}fMLH(;mt9Yai0pl z(ujKMp07Mk$(S+MFotNDCJvK4I20$u8IGl{NpnOzz0m}=I2myiM8j97taiO!!>b~q z(p1UD6^N`GAUjT*AZrt4fE9H^D4@TBIF=MP9dHV4t-Tn5(G}w?pgEPNMy~~6;o|e} z#hbQgZV4JI<`g3^K2lj0GQ9nYvm`<6yWQEV-Qs|MQ!@ZsrXZO2!ZV4z8J2dLbtuDQ zT^ET?dds5PjG~fBY&_gXHM+Em?y_K%*gz_+yH;-N%18#5)mi zD?zu?czS!1afrWZJH6lz{?+qO;eHXnHfl=9?8;Nd;Ab#8^Q2Zmk_Yh?uM;ce~E7CF5n-Ka`GhHk<&k>%CJ zOYS?|WQo7);e*59w7u%~X8+-f_<3ZG(*4EW&G~=#tLM)A;wVG%p)DRr#mUy&-sdNd zf75o6e5cTO^U*i%ia7ed8YP-UC+yHx_7IGIa%rq9`WZoMJ&lc=&Kkp@MTv1%bHx&2 ztQ|*1H<3VKnvSWG-IbK7Pt~Xkl7*$g%^h1zrx2OswvytYF*O@{FB^VLLnRwmy8%g* zdX)Y?yFh#z#n>a~<4zhfMs4{DQVN^7KftTjo(Uwp=n|{IB^Y0<{7W6f3h1jTZI|Ah zRoWDMO*IcF7GB1H{i2lpbzPuy>cuQ1zDgA3{(1u9qGXN!RdjFN5ItZ)uP8-oVg#AF zQ)wt+Ib=x_Lhu5h&*AXG7t<^?V{X-vp>__6{Uy_FD!3PnYC1=?)p z6C(eMY0*nx4Nl7u-q(vD^*5cHO+-?VJABL?yMoIai(iVD&#(tzrIR8F64N#PVV9_H z1+i8XDLN{NWvt-HWD7ayub~tHF)^Q3N!=OZD@5qD8zq z^rjtbNJJwpD%rSN3=q4ds7GnXyeHGvv) z)r%-ry7O}4!9~d$c_rw<(h%KrNkx-vP@E8GVtClb|3#o1xLS%0xNyWmj>1|()wJy1TLs{i* zTa*l6qv>i1J*~RvK?`~$6%-SrWOZFhm;GT)0syf9)yo1ome!J5Wa>b<sMNvak&npww*GT4rpds4qZdlMK%5Y2!&2PqNT}jh^wZ%q8 zlGvm&HK&cy5tz19F6REy>^&cp8J9!+7D3WS_bJvmeJorVp{F{^|^0A6}HG_DJ^FB>e8H zTzuT!b~ok8(8`D{(xT{*{0ma_y`YS`vk?tLu0Q}|-W5e9YxJ*4>ua=&cHEQK-=*$l=qWBCy)7fbX_x6Tv2e!X*5X`zK$R zvgf(~yYl%MpKV?IZ21M|UZJ2}xh?Of&c|gZ1(it@^2XiH| z)tF%`Y3+@+U9TxDgvQa*Xs#ZSG&JDLDl7z*!{-TlK6^K=0srWYgFKdn3rUdY8wZ98O3_pE$6$rRlZ;le zrvjl#ua|hTkc@y>hbmEf-6mQnJ<0196qQ7`RgplgyH@TZtgb|QsFXFTf;w&8bp&*z z4hr&v6h}|6aJN#b=W*s|A!Hp$7qPo!Mz889SdT|oQsXVaFOk}qng0n^%exFYy*{uJ zC_j;sT&Vv<%Q&y>`3I)@l!Ub(c#$l$@e?hP+V%RJ#N+gu#`j(qWv{LR>s~->az8~ex-e65BnzS!g&mXH z{TC1OeIlXg1EuefceSh7!$!ru`nl%S9#NZp}-jImS9gy=%`f$_`2pe@IVX zxne{@QB|6)dVL`s)1tV-704w9Ae;F|tP-$p6F@$JWh)w`HFlf`t#z(&ja(Ot^NAbQ zomd<5m`-NyV#FrdyH#-E`h4|{fAL-E+yrL% zEF!omy<3aHu#OUzMsG3()PX2U3F#`A$QJnnZ-*<$t&1MAU|1w50;w1Q+|`wI+3(3$ zBmfW$7_D`@jV0C957$;18j0+$c(?|l=9y{c+pVyl(e{#!y57jKEVJ{7Ldk`z#ef9j zD{K(CGO>*_K^n4wUP-6XTp(6!!IRjo|9d}qWrp$eOK-PqjzU zoYeraW1xJvXm>V5o81iyEM@v6Q@>^?W|eXFE1BhXQj)q)S~R6k^L@bi`=B$cj7O$9 z{W8m_!6+*4Oz$w4QA|aJ_f96Jc;(!U#aTCb{=GBzMbo+epSQj&1pIX4{+nMl!`J;s z3@cegr#tSKZo3Q5UYK0cx7%!VAUE;d(S?LhJu{N5y( z0t_u|X-9rY0M|Jr|m}GJ`%)eGhNS+{})DkWT#@q0qAp#sO z=Fy#S(b}221VtECp3>~sBQGZdOh=D72h*58|IL>|1<4F+^2|lRW{Xid`^m0?aBcN>8c z+a5{QD?Kz#lnM4t%$WNSg(_v9q&j||k@CJs;0|Lfy+AO|u&)L=(isv&)(wwKD&z({ zhV<*ngr8OqNd)w?D)qngzVtuVz?4f&r~y~=xo8Aqoja!4Ue-6x@<<}f#&*3vX@|Zr zpfjWO08zO*3=rbv5mu)9p{7V|~PyAyTgJ)6ra&rE=@2aS)#;K1F3+Ewda?|s-EpVHJ3zM7;(+ZD9#eFkTF2oG1gH^)>gx%1g7W#3o>n+oGMH*GeY~00vk%Y?DuBz z>7i{3U0QEs)T9z}<#RRm8Z)6c`oI>0U7dE;K*A+iRyTwKdMcmUWMr86J>&%?^cXsF z%=$$77`kxp2IO*d?oHFhValjo`MDSz+NK*Ihe{A>AU=yj+r?G2N1mP2_o=kX zazPErPI&fD;fiGA0QJ1hQ4GAx!I7JK{~EftQ5QXAL9Zx91~w25mbwyVK~QY!T-5H9bX`;qTHw>7zr74_=m%eL_qq+476 z_M2BRk-+3IbwB+5Ut2T~-daVB)$Q+aZ(2;lUwrCIFZwUZ;foWP#7GBWeBs9TZo$lz zv{8u4Hv`wD;mJkIH0E7VR0rz)Yr^^(9iq+dh6R114EKsUv^B3E@5fCA+;Z0j#Ss_LUez-`+gz~}iIMUqK9m6Dr*@|@qcJ+ko; zN!rjmcHzq0fkKSS6CeiQZ$g?j+|nkibq^WILPL1hQ$c7jv~X3m7^0;S0E_r{<;R~6 z@*>XU7T&a--9EVZ!p}W2zdcn0A9uTN{0zv(ltX-0iy*v+&#pf`3A2UAO)hGcJa>>o zTPgK^NuZ%iGy)0?1Tg08d?m9eDj5NuT%)RX(H3YGZM{B1s3(oqwnZAU-;@+i{fGpS z0sl_RaYrChp+7do0h)dtf9MA#2E1t-@#tx__4^Zh+d(oRKKe!%z0eF4EZyEYNSnGF z?lo9>F&R`!L{56iyI1&|wxJS}homXJiqbym=!~6dI0jTRr5aWu3qLNg^omO`rffC!hmvsaZEUyEEc{hn} zmOy-BQ%@fSy*lko>71yN+{FUuKmR zG-YD_a1e7mXL(Fnwl22o^-S(@idAyqYBxZn(Wb_sEf5VuMrqzts=%=6eQzysKqT<> z;UIJ#;Xu56)KyS?k9fR1!86})7&mUO-oTr-D?guNahOcQV)DVK|Ie@bb3E_DtN^(v z3+%=59?`pVJB?>WCH&CkKnaxVt`2QgSa0nmG$`W^Z4>F>g^A&Il(L~jvjF{*i@GVD zl8Q>eO=wb)tuZs5)C~gRIveN&rorTQe^f?n<*&uUArQD4?~D8R`ug*kZ6N zs}2T8Dh1?8TQfv~#C25GZ5V@6e7g2tKo}9A5EpXHDx~4OylH#xMgUxvT#tWpmOIB| z;CKmb8YbY5f-&i^+nyfA3pfbESF0{3d(KPb#nHgeBJyl5;=UFGAV-vv0*qWF(=6AX zx7pahyX0(Ylb?uTmxQSV?SBTv`3n z$MlY;U${%NnH<_)oz8#$yI*`4hSf^Eh_kEC{rD$7yNmVHXP&-mbhqC61>0K~{ZD^p zdGWxf-;#m`q_Ui`B1eO;%bT|DocT^v84g0zR=jgdg9{f*Bj#;~wy}_DfY>n}n8Bjm z*$~}zXj=wik7VlCuN5HB%$bG~_UD?L_JxF`qe<1H_!PBi1g4jM`bR|c?P3w=AL->i_c6$rW?5KyZJ9)cq&Tf zp1C;L!E*Z-zxndj$H^?!9G`YuejeEaHC#I9u)B%Duv(!Qo>P*Xk!0g^J~&j7rm}-P zZ#U@{%VH~r!7#O-ANw<2EAQ#m-$x&7HEx6*6<0_`pGe(rDM zuTOjT1Jm^G&?=Mr9O-~N@i)C``zrI@IsvGm5{;nIoAf$$e%^o!rA0B2j{wixQB_rR z=^#sv&BooPe>K-pB)yiyD}lzAZ-_8y=3Uk^#<^c z>+yw8d{&yA4he3n0)Q8nk74^OUxTVp&~1z~ z?>!G~E9l%@cYcke3(#O4h;orK?2^)YZS>b58?C%w(u0L%!ZDta#SP0PU?Zg6`d zDsfeiC3-`zDJ+B((ppinaYa%k^QZ1hDomPaTDw4GH2~513QI>5O3fphKZ46m647*# zHXOm>$TmsYckh-uJi(0!UIW_4y%f`uZ(FYT+aXwL58vkTv>u*d?&Gi>6COG|7ren$lK90=4c^QiRprtgiW! z%6vM?pEiR|VI2{O_~XtUs7`R{wN4V}yHS0Z%oeHPz#Y0-S{`4O5`H$jLFUI}l$MPa zg1aioUGLlz^0?^xCLwRFD{e#=Y#Qj2aSDInBA};L=v^uGQ_ln%yyVTD%=2~b=wjmK z`IodKXGodsQZv-`dI;H|be*i_6WZAd2I$T+fsoYYI}MF@L}|z~uCDDWikK11=x@Z1yfWw1un>e5?O9zk?+)LX`ZE z->!lp94LwJqEn!Nk1YpEs9YLzD3j8N;w%AiA(;lKa^$HLowbBW%26NMMkE(PlS@O1 zreo8751w4igW2h!ZF8^UHAvP_Kx-W{)EhFem4c0L)w`vk82_>md7>t{&J&6PiR-AW zbMxH8H0vN%@I1OO4Y(8ToA@z`^z+DgdK~j9Qp%`Zhu?7w`EY`Ufx5fQ@FT0~Xak3~ zn31j|FYM43nGd%EF8P$B7K6|&wSviE5db3>iDV2sZ?mz1ckqHO@)I$}r5qrz`z&I> zg3_Uxy!{#oW(06I&VElmiK3O#j0QX2#**szIHPguIm#BEdx5sWT|eeavIr`Nfpxuc zT(_!O$Z;u!tK9&hS;+-um9ElfUB`8qp!Z6>pb_(9FD;Q!n7Jm&+J*lj=P!NgneEw! z-5ch=_pbPXOc$rGnup*0uRpsh!)>tOr_c{y_uOM!%j^wwpe4oI31>iC^8U`=v_0yd zM;6-#O9~LE8XaUVt@Zk#M9WOg(2_F^B}_-{to77Nx|&oY3^*m(ECOY&uJFZ5d(&pv zlp)b`KElY#<<_k@kNc0@@YkIC#rMeH%0&6x%ikOE$m+S@duAt74PIyNYu{7zjj>O1a-yS8& zHijY(Z0RRsJ| z2~s&x8+TGOON4dX@z8eW{uT~%D`V+5Kk>&7FVPMcJZJJ@Iq_?hoSUExhqnIc-?SZL z+?rA20QXSzkO7r07$Uvj`1YBNv8yCmx1GUIku7q2-ZF>ePC;Fhodqrk^v72eXqrSV94{iMqBwe#t?Jzq% z4?RYiu$bQloxhTa1BVjsEY%}c@uT#0lv$@l_c{W4TE)4oe(X9<`AI#r#RM76gQGjN z4e7;NL%ksbTMTw}nW=-o zg8x&g8KOYq+A0Lax-ESmO~2&SM%jQx+>1qtd$E|xo3;@Uz_)^n9w>Yx0$ALLQ8Y}z z-31?td1#wtmmW*Lr$bv=d-J&%Vt|8e_Dkp%TER2~IBq5OE z(=~-Sx7eLA-;scm%#B9XTPmbf$E-R`7T!~~YfH$U*xP~hIW<~|BTCUP)|h1M+t=)^ME;AY$S z+0?gO(5w|`SHUOPfS*L4zzICkx`H3Lk#NRKF~}ok9!SF9e7Y=kDoK;ZimFkn9OGyb^Io+f`rkSf!5UL!FSJzxRN>Xeodjl?K@IAA}~5K>&LG}X%i?MII8 z-SUjm7K=apRMx)l7Gc4n(5|<9?QoQ8-O;CxjbLdvK+^Rb-Z{nZC@pTdKi~TEH&Oc8 zos^6Rz&i|pS*oSoQ{tX}Jr2h1f-CwSYDLXm_%-O-n~SLnk1t1Eki?D$VIg0G*mIZN zZ2ud-<{RI#hbaJFOuuhTHp<)dFnlqeeauBSz3$>$UU>QM{AUZStylAI7$I2%{Hn#@ z03O+vx++LK#uj*+i*jkq^SF#67e%|%tR|UvKH=FhsXcUQeE)L5f+1-culn_SuCP9h zxFP#XLaGGF^9?VhPao8B<%Ag?Yxd0KZts#N>~(yF7l1jRw@$I(q0Fp1-5&mOWhy~BJ=p4W?I1yuy{XlANu$t(Z;-zfl)lxIWga>&mbpt) z7Xv=8iHM{|8n4`P(lYcedV-65qzGn<&$kLCvZG@90bA!znFDCft;{URluEnaK&)-Z z?7p=@$%U(GfS0vb%S5{DPz`jqahH&?b#+)V-9D-i#^{ae(Q4*?O}K7WW?$U5mc{ju zlpp3``Dt+Ono!$xUXuwIZcp61JoD~} zt63$~`;64EPz`|{RWX9WY{Znqv zKQDLqJUUR`J_}+0ckyMW{rTjzFXGPz$oF;9kDGh<-0x0GCg4q5*z#&k(E+hg{oMOR znmlpxSD5JT_4tj(=?_1GjR3ZS_#-8+dWTCh)u6Off(Ii4fo9fcwz!G$Wv*#Vxt!U2 zMHoSyGiqf-RJgjDD%rS_0qMbPVi9d(-NO09*+qAIHcfj;fu0NTnU@?07Wgfg1F`4D zXZWx+vG!b^a6V%vJ7MQj&q%w3AY+w_W_}7vs6J?r-K8EHl^k{KhQ2C$A7dJp1--X-A5* zPT+lC6%0u(Pe9hEo-3Ko8}KuidR`GYP_>J;_0E%>WCOx7TIXY}yH@Ts`%OvVtnA3t zlusKdV|KI;IeozW&vHJ6W{z1HS zH+NsSUv%_}j`%gkN8d7=qyC27>5regj?cHh{SWYj%7^(MJvmu;Hw}1?;2qEYeR|kV8;8z4|JuK`H4Br;uRM3royAul;_Kb=qt_?#FTeKun=YKmPb_z*m!~g0b|Fs2 zOoAb9`^odmiy!cA`N=c?dk8M3uznD0_^$thZ%#uM6TtqPUzPf|-Y*sNdYbGf>$*nF zmt?JXr_&JW{$lW#MBQ1;=^LK1wx1enmKGEG;;imP?e^7 zNnyuU>1mtuNhOb_c)T~tidg)qa|fnL-&ewXU2i!f8>Lzg5Upd|4G>v!XnPPQcy9ab ztNz&ZkZ+PNmVCBM&_r{j0)y>xSq73wlKvl8NE&$)T-jc>o(%PO#1MnONrozvow$ zoeL8$X3z4XlG<`VsstAkU9bb!9yZJiuNO3kS#GELVB(&TMp}-gabXpuy0tIYff8LB z+~M{4&=%Af#8PhL^7WhiDu2Ko46n`U9m$<&DamEzNNq%}+x zu++J8PSrLS3bI6xS&?!E-d49}23l`mEJz9IDwlQxMA|N}Uh(*G!^{$wspdKt@cpGU z4l=Ui3Z+@^YUVyIG~YAV&*>c;0zP|{$jEb5=dJ@1&+q2%AHJDhM110vz4{cJX>xQ| z-Y1;jc0oGfnscvCfQ9!A^ZqZfo-CFhd<26gF1Mb}V<;i|E>q_-`r1~QqB)|Ez5Dr} zb_ahMhqmvZxi|dFC*x1L1B4BSwmUFJe#aRuWG{BSyZHJ)n1rli;Ofr=9NNm5m)~2C z(UA???pqkc*W~sW7yis^@i-Jd;!cW0WNZmWNG?x6wpOPbC1ZDrQ@Ic@B1U9D)h^oX z_M{|P;p=IseyzKdtl4i$3a5P%DPHzyKH(^2$%!guGRbEB$!|R6e&9NeOn>BEKXR4l zAk*vUjIVq5hb5t(-@;`?2{pmfc?@9^taCdAq$gg$EfzZq_l-Y@Kf)sghqjOJOxXeFmR0fAbl4IqW!33Efr1 zn4m{z-NlHXNwpEz%@ls(Ft{+;o?Jd~|KdM+uX}b2Pm<-(HhTAKXTQU3P0!>{xb8sy zh~>w>_XdPk;?^NKTwF|XXp2W}-+XxRY4;j;J306$Y(%7&?)}Dh;6n2(8-SsLvBQWR z(V^|IOE8JuxukUi7K|F-E6UQkOUc@C>{@DxpfxH=KgP;a7X!+H8ZvZLlvM&)>fCO9 z;w&*%uDV{EudR^{>9|r{A#OLo&5+n~XzLb_C!10xfJ=<<_&M+Z3LM&kyNK#gDI`&G zH-&4lHOO^d;PEilAXZ?-8+F2J9yqw8gbbQ@y0HW2;^fhqf3f2>ap^q8ihiwtgQC{C8Q7 zN@oYtv*-!DX*((dV){I)9puB0VNmE@XT1{5Zh9GyjWB@x>pgPO12*509GIS2&fSIg z{LD9f?&>r+;3l)dFI_p55ajCrsXKr#4kGo8buxJ;ribK@m%koAU+e=}JG2$*p#qvc zr3n&46g?=&z zQc5md6$2vhrY$!Q0m>BqOY-5$wEz&x)>IZF$?ytGg0x<$9?6-D`*$z*m#xFuep0=- z>^wyJ$u%An<4Z_M<>QNGR&{f7h%Yt?RZUAqHm|hyzX{lNr%$d7>-HiD>QO*r5LxNd zxYSY-7gxg!>9`_T6sTNgRUivHztNpW7D>jA8R3$1?V=%w-qw3vHBeDUMg8o45Cswr z*so-oIEgEgmtN8=1D-aHE&?~cAAjCCVqE6JG@I_--d}yG+n>9$Z+tQhzzsC+q3`h; z9@g;KKWJb6N7xrn=5G7xDDV8>P22pvhi}FADlehaUr6u$WzF#>p8XuwvZUK2(8{5$ z{3y-bPjLiPDc|-#;?L5jjDoaM?nRFIBL2u)I?j$l;Hb&sC=?x=j6h9H=e0?5gdrs; z4Q@u>S7cac1On@Nbv~_d^ff(^mWpi#Bn>yiXP$cuSoyueR3^5Tg`aptmJ~U(UD&r( zN!3yL3!XT53NgM# z|6e|T$pw#yr#Ee57Qc_~yYjmqz7g<}%zHkRziYpV;yJi}2^#)lVA!JbF-+b5biDBasH|97phUzG}TcQ4L1q|}@xN(r~$Ozb-Jcn9Q?j~j|&6WoDZbn4p ztQLZB+paesSSa;St&)vvMGl%T+AhlgiEer6{ZHf2mMez5C%+V0+{dqe@(iA{Uj4z( z?oO`@Y`Cai=K{E{RQ&7U4IY~I9S&!g*P{ES|6m%un=Ite)`i5f^^WKsmDVm6{?+@= zeq`e1Zm>+e!=Wv{G4jGkKJbgOXUJha-1cu+e&}6`DV9M1Ki}t*ph{Q9~P#l>n9o zH)eS$=zJ}u=?SXq-OzuED_kuGWCin(-Zs6Gm!y>3;F`_lGv;cs=P$eb^T=vwZ~Xzm zuI9@qTP>`M2cH{QY#(!zvk`Gv;y6~gwgLnQ^Leoja4d=#Vkl=m3VEOk=}sU$CC=y5 z=-gBLctjkMXLfZO$j9JY0K--n0$y zE5tdDE>lOukABThe9a}mqIBF;{xJ0HI{HBlZFd6T!zE024*r+JpFP0e$^zFuzU$-$ zM(xWX1Q}n`%UJJlCb_H6j-tHBj{jzpg?sfkfBHZFcW=hP^>S#dS>J08C|`{uUs!#r(2+8=QvZYx!5R=5K)ZGsf(Ttg;ae9lalk_596p}F|>y5ME;7^Qh z_U8k`7QfWE@3tWtKhPLZ`RVMUtiC9D8;jpJUZ&fCZ#!W{mYw&QGFyTwzzFFC7?WS) zg|ksCn_qKNe+igeJZqpv7v=}($<>HCJHL@ewvCKb#Eu!IHjt_=8o+i7M#)tDT1(7Q zsVj+un*G55#)-HZu$tNiJZ;>41cHdb=f3GD{>^+QNtr{Tz5b9w~>U`$GJgpL5gY3)q(n2VNq?X|b2)kIF?#luUTL z3w%E)!Fn%Oem0?hegCnDM$YW$u}Q_pf*1gD^Z4i+?G*w6NXdk`eR8j5(l~)OhWlre zs_vR}Mp#y6oW_)!QqwtKkwH)yHg&xlCX-6G6s#HmplB28JbobY*?s)xzr5b6B{lKZ z?C;#pFY7(_v|{>eZ|Lig{D^Sf9DE=Zf_#nt3qgzb>sF{HH*vw?Ev60crWmF28Jpz- zzTXt}rmyzXNw_gN6CwIet$)ts(nON#R5vW@Yj)^Fc4sdh8^6GMT;f z{8P!o_>Y|YJaV>n@rKFlD}QHk7I$)JYm-W^3vuSc-+TPK9>>Yb?q{C+&>S1^!9&|y z4y)~jmkt6Ri@k8;ty9T{@G<=T_p3?OL0V-0)0^M@KKJbG-2UEV_WoWI3i64=?|%!N ziHl$TD^vWq>g;nrHGk}q?Aw3%v-o*r91+7c{Es0_o=|vSVXc_^{BFFKZaWbr9fa7+ zgDcu3AFjrhr4g>!BKK~-jTK)B0-{~79lugif2ER*Yeo9>+0ah;GVsM`&O6WCm0w$1 z3ix}b?)IBLU&!UqRv=?aNJMAw{%-vK&+dBfUl{mg`wQ;ewcsv12d`&`|81OJ40uiy z-D};_pTpa+_z|jeb3L@Z=|25t_v4kAbz2nhC#*mIE8l(bn!m98`~Uiri}@sn74euo z_ntq%p)Fnjl*i0Cqr?ct0*o@#<5#&EF6<`@W+UcHN~m|Iv$NfY>(Dl2Z|PL=l0i7e z%2OBfq_JlhV~9!sZG)S$n`8`2X?jBHdUZ)q`hl9_3Rk-UZd;xd$4hR4-+g-FbuawA zYr+VwS-=hwhqhDPOx*VjXft$VD_jQGTfB2ad*nxga{)WqC2AM3{9R3$tk z7@oa|c({b0M+V)v5;NHre!f*U$&JJ8pYz^2?G>9u6l%{%V zVvnhzr&Wx5dTt^n7R!bViG{Sz9hfFOzY{sZqR_5)qz8!BvF!#Rhmdmc$vb@6 z4`u0YISdbJ9^m27uSve+WazR01`Ax+Q6hY}3DN6acYPD6h{WG>dl7%S`U*zX7YKFS zo6hiC8-T;c?8WvX!i%(t7K)*g4OuzbBNGOE?smX$}iCDI*&X2OVO4(k_t}spB~zln50%{+@GY| zi?dZSr;=3Jyf>vUU_{&`RGEM>dgv-l@h0Bh8Q3GgE+TusLZtDacXnY$*|U9_GTdd} zy7T8SzI5ePU{{@31u4ra{*c~;VY9`}29JmdUK2`>q$8R8ip z=1_Gk5R?}LkVTR*w*qg|*3R0U4N5Lt6ywQZ+I&X9SyG@Dvkz5*>>yG2+G}ceUBF@< zy%R*?+K4x8?e`%rMUm^>`<7B;u{UWU-G?upT-ZhncAA!iXuX_qA;Z0Vw0xHf{LnQE zQQ#gTQUh)H?oml$SlDkF)^%lm6fRm7$Uq^DG&18O$>5HZ5iTL1iIfwmWeR|_yKX@w zb$^xggOPT0DJjD0N+8@gOGroh({I`R#xkh)+l*HI(M^B&JKg#D_KiAPetk*4`aWCC zd9&?b-wI*Go3`>c;QkBv^Rn|v_`CQUwyAt;uJ&>86mt_pYsa}Cx`gu} z1&pcl4^AD^B%o!O=0S}Xtx|-dYZ0K5s>=0$f)2(sD$4I5FkG5}9$B)sM ztSV6BG}mjBCeeMB2F2#ZNNUbczQRmU*JP*jX@#S&sgkWb8s?ie=N^}zN5-hh;ymhX z_9YBluwQlW+Il*CIAaH|o)kC+e({+AqlezKeJp+Q+h1WxjLV;Y$CF?|z&|O^b-nv2 z{-&+0B-sm?b@3|?sbHvrzlm#(MLWGO{MCtL|5@k$=r`UJ<@525%D8S*LnSPV?5u-f z$mI#h*6Q-9Wbi5%&zgXZ#zDJiTkljf$*8EmQvF(YtlZKoxp>y5q;T3cKsxWV+`|Yg z+}3w|>Jq{{owU(?cy?s~KmBl%`(^Ylqd{xz{ zkM8Q~TN}RNP~4e~MU&q1yEmj^^QnCSrf0_&>5gdC4Am(4*audDa-E6ormfEOY2Qx= zg1;=`xcwK7;m6utfU-2%ThP@noQNm!@ObI%OK%5uoyIZzD8Xvm$+-k&J#;uko_@J#6vGHAh$$7t=AqSn*TSCbzdM0V&#pl9>H*THJv?E0 zsaEnp>U83t;jBfgP-=DVA8a1xALgW#H*J@wy5TaqDoSy}&VorEc*UE2$vT^(wBuS( zQKgpLiJ$(Nx79i@7p3v>doD0z@&+X@E$$AjD(%u)w#~&1V+C@e(3)ax#nJ^baU;~T zRAs@hgt~LkTC}qOBZC(mTD`M0n_CkaAO83!ZBZq@v*f0T^dlE&azkXStWLQNGJfsT zjUh9EsKA|Qo1^lTNB+39wO+ipdnn)~2d>rz@S?_*2%#-58LozAdZ1Y?H&qB zq#G==zvx<)eHoP(x)L6y8c>HxP7vd~H6&f6WU{S$a>EhsxrZH8qr?Uc79SkHk?5$5 z+u|IRmLG1T#Se|hl_po+t7&i&?~iqsm_6xYm5rT zgFutK@`89Nj4_4bOMx5fBLyt4PkcG;>OuqATCcG+)3wWrnooib3IGWT4B?97DDQNdXs%e_s>rHxRyW`UT5Ag1YrXdQg(YI@QedTkz*R86 zVsnWU!ej9VztXm3T-qA`7@7@nxK3C0RjZdJapwb=k~Q)cOX#e%HEiGMs94^_6ie|x zExyZ(Jn=bK$ZcuZL>2h8LfU#CTZ~90WOWg-0$GXYYP7bw7E!&{jcN+yLRRoAWR!yx zsRl}oKW9OM-OUz&q8z+qxR50_C}DQ1#M{q^MkN)by#&s4rR11Uar6j7YOF#Yi5X&L z10F291k*s*%*`VjL!xbfONiL+_pwq1dJ%O;##U@-}q>6Zq7x1WdgI&cFb{C4|oU63~5T+(B z`_2V2K;gw*l^U~gcDOG+Sv@d!#>7la_rfhl8rrD60SSK!QQ(vd-}BDsobt~jPf~S6 zQ8GJxH#U8K{=PTz(Sw9__Ly<{!#~_SJT~Gankb3Q@8O3$ms}tBidu)`q$~e;_Z=$J z=Bke$*H=qr-Cc3r;KHVj4xbMn^Rq?fIzTFWe8#XlgVxiu?7Cyiflqp-VD6EbNS zNp%h?lHDx2tp%NhNv_xLLu#$07KF8PEhbn-6}VO+hqngQxzoRfQ*DXC*A=NgJb135 zwF76yI;KtfIfFQZ3w2BOib%JB1NFx}c%zC-H*L4`F@Z{U?oj_Q-9c}=G);%_T15IR zQd30n#(nE2pG3Vey`}zF>&|>*l-&KA8){wIfIH-yuYPixp=-YWy=UXFpSEn%v!oY) z{txX)fJKI`UU#y)m$tbpm!rQ1loUaRQW@g)p%g4%!xXq5hIA;Tn7mVx3ktrjv>!Fx!Gyv+8T3Yyc8 zZpIhjQav#=E`$}HPM(DGgiv1-90%78JwzsK3^rsGqZ%)2EMBsTm!ThD{WQMOQkFy+ zW#X5ehWEd?;6z(*we_xTCdLT~y9rbv60Sm>OXGX8P!+z>1tAR+gmsD-$t;Ktb{8z@ zBr4>2{XRtdJ18hA+V9CI+;A{kk;;i$xgP!+NS^-n*x}iFXtIP_uQTieTisKeke>{PRR$hzXTL$CqNhY2> zv2dKaH18$v69&) zXe~OljTa(hL1i0h7Of=HhtlxjDWH-3AWREFlr*-G^A(%#sf2hXIJ`Ar>=HPE-}-hj zzQ)8U4WyQR9{EHpj%}Zbl86_s4Avpc%!p0k@vn=}xck1vQ1BO< z-{#Uk&eqIC_O}i6OQl;RS3?S406By=EgIhUF>ql9 z;Z~$`&B7;Wnr$;lstuAa$KMb> zIF6t@@I4PD&1edON+#Pa{Qi={JR3isC);%CoW!s(r2B|_JTm zUo=i0VSyi^SlTezC|}Yl(J7>~>$`*jBf;0sxm6O*R?;pUFM-4fWGc@kbuQm4f?g}a zH)mv1xCmLHeSL1nuprtNi5Xg3&{34nG^kPr6RNeKq@DfCT#Kd1cY_d<_PHKm%b54Hx3@(@GK+Rc8l&({F?3844XzM;~E}(L71W3)(5aTnY zlTEMO^h%uFOA~wxF1SmHT+Px}Q-2>m7pGx~_3<8>=N@_-*UK3G48Kc&1VZ*SR^2s7 z`+#1!l(0&%rS7%EO8q0D90FyukY@cj~g=!uVg&M>KA zdg#78DOu8*UJ%h$`pNX(e}B#J^~$|1XCi#hm`hqEWi-*~5K0 zlTBOZM{RJ!WM+f~XucHM1r+5V{*gCbbDdiqkWz4?cAK`+^E<1pNVfP@i3Pf|Fv%6i z@D4&$k&I>~HNgh^Jy~!qCaCenLW662)Z-w`hngd8jOtdQ4uts-Xi){HoVdHfK4a{r zZE6;ip|u;&ibs(aDT{?+4S_iEMb!nzQ0+tSG9u z2^Le7iYd`FYb#<+LDHi1^ZD5rhGP$(&h)Ti`QeJJIV5p;EN zy+QCChQ@jo6kN(?1=ke4MzCE5B01+Om>;w)Q6+f}zT#xiYaArHhD}>QhD}?8uwMn6 z7~K(kiF7r>&w!Y?^nuhWs~6ptE2DNUc8m<(gsNbqj}#5{|6)`#l!KHaN3@G62-E%C zBje~VUW_400plPZtdNHIgs%*35E?KeSeV+o2>foLVtZ4HDfEHFr;JM3!oEi{_Hk0H7$p5;y3 z3ay*Nrme>6600EXh)b@@=d*A(*y6k58XA>#Orc`keWUN zy;(L~tH4?4wr{OFD^`l=O%FerpC=c9e<6pc}KA=2u9l5$4Jlh(#Ei7W)~Qjx|8 zK-c!pvh?)i)F41X74b`7lG7X+gN+_>z0FP>Y^S5K6eZ z3R;T}c6-r6)|E&lR6cAsb1$<$D9Je+d_{}cmEb2)11UcT;{N4&2BPyuTSd6}<8Z{- zR9F6t!#V=1$-aFEuCm|jx(aivWrMO=y7Fx zq`rC7lX(-(YHqN1q-~wxCGsHiq=VjU+Kdm<_H^swO_gOS5AzLR3jp#FdE0aX{$!# zF}rCSnNjB9Z%Cr@wSt;xn2VGgr?D>JRzvuI}lbG5dhTplP2 zjsZ-w678hq9-tgznQJk68I_|wf>&NU0&4aewx%W|*;T+dR}R>J0K#pgVj6a~JZjl4 zpKw+zf7ch0oO87{faQI1^Hmp&(U|k18Z8>)leU-Qn*$U(D`nqY(dm4FDGd1nb!foLUi zcxxctyR$OpMp&G*P2t9aeA2c;3Y)fA>EaOi?i=-?>BM}7iC{_3_!*@md!)C00$W8G z$|iQCdIUUt()Pyd$Mwd48ou^b%J4zkXo-Ija5X-Gt~v^n%tb8xsyE{s$xC!Giga#* z-yrz8hkg!0W`6MRC!)LtOJyeR1#Sg?Vl`lXVv<`6R)Us^v3bSQnx%-%9iqSupJvEc z6tYxfq~Z&pS+B9Ut}h}v=W1<$HDS+bP^Lw6hQ4u!-Ly^3swblZF@C*dmITU|2oZ{4 zLKIJy{if{;HHZ`X4mhYrn>d)m-&z~F=TC1S%=(%Wb{#k{esg!HetEiI9JPCqW6T=) z`4q*Qy81L8O~!D3Va8T+*uL#*kg>MlqI|@273y3X-;-HQ%;Fne5YjL~Sf_}Q%!26P zJOv9ni3)jMzYnR6lA`^dEZhrNiAAcQW+if1YXG|~n|GtKm6jTx%M@?g>i+pJ&s~i^ zW76HX+cUG}YGp9uh8(nBfaen>ceZusa^|_1^>8181!c^eMm$bn-rxHvoNX5$b?O%t zI$OCVRvNaWL8(u{U;dy3C7pd0UhpvFJI`i)z6HE+vR&1GsNYBgf!TvKES4amNP?W+i~ej*ex) zAtA}{7-*NfD4i|MzERR`H&8NlS%SK6nHKp^x{85-fk}4@@fKBxU?Xw@j-|u3#IU6 zf>4gjV_mA2mw}h%dI3|%s_dlg(~P>_FzHZ+g)I6R-xOO@mTYe(Lo_WWYIKx@5=KD)b6BnPfG2FSd!7#rL%?%wc%cTbS!>B%J8mUqk^NzIh= z`7Tt;rfm$tnOZ`JDdR~{ZV*MIGnDmXo0Tqf96Hg_0!lGD)=%-Rcf9+K69*TwH^Hbb zA8B*981;mnOX|GKP0!{{ zTQ93~SP)%eL1$T#Yiv8y&&WwzI9oaBoJ5vgMlgvBl_U}5Q7uSOA)MB`I44AetaYFq zIwx*z087)nX$uc#o6Nunx)4s zRE%u%F@;B!Z`ulPXVoIP5~x}jprLhaG_7IN7I(77Hu4f4xz21`wZ0DxU^i{?O2S2M z)3#Kvf-)8z?GW~BJmGv8Ir#2RIv#e4gy)tVim5^G!7A72FN>sC2W1E2wMEA!~)Y=NC7L3 zK|btgKl8S8EzYa)#ez`zK#G_@phb%8oze zP1_zy7B2tRI`AqdxzqKTMB{sD-4xCMopujt%@d`e+%�@wdO25U7M$`J>`e1ctxD{VXno;r7-D2G!;+UcGZ7M4Ok&? zHL%0h@e!;ICA!2(q&4-SSdchk+!q$OWi;oG<3Uj9HG*l@Ydl?dp-9fTS{VQh32rF& ztm&iKNpFi9GW>aDylFu=X^Xkfm`{X(xKz29Li+u8U<;?4E`XcikG|%HD2?Kgoty0# zt=y)q!Gs^7)ukeEBsNRAKq1}P8Z$Jzme2ydC`dng7< zp)M#X+V9Dl8@Wi;N%K!3PyG~hI+f;dX;u)#!mviRmF;Rgi!^39d>+}*RXAy@v`N-( z<18la7SJKmS8t0{7xeR>iTB?7GD7cN*tgT3$fp!NzRGl2Ugvya}>R;KxIv6!UpDLQ7xFjr34}7TOkdSA`?vX zqo=UOMmQU&1+y%ONe3KH(D8JB{}(cvBZ@{AoTk;8eIWu5lLef#8oz4kVA9*@5rS_O zjK(!7fZYF89hJh%k%&!?COj4?hYSzRYl zmXX$?eTxOrLM9qoN(x9NF(0;@xq~n*45Fl=5|OctN{Cm2!&Us|EO-Gw4KaJ4Z&`sPgB8^`)BfAp3=Qm&sFObT<*^m3~$%Z=-(-Nd}oWzdLVt2c{F z=dEly#j2e6WGz*k+fDplD~>SI!b7C0W7+Q!>otU#OXxIz=U zI`9>yorHY+QVxMKT5uU!kR?I0=n@OWtP+t0&jfX|67Bex*`K#;p5?s^EXuJR@vGbt z)kHDhssSck(A^aeFa?^qja1Bl&xYR!s<6u!HuWkwX*V&EoO87{fY2@Zq^;7Kw#|TE zqNaG$_By5b^T^o0dCEn%T@#Ee)9v(XOhuZmj(W?;kv}w?7~Zr+N2=85&dH&g$@IPG zU7P#aahX*)8GBeTCb(NJd{qz_C{rIy@@)wf0?^r6*kb5_8z)RWRxgHY_eTJt=^ zt%_vc2pvS*EEC!(=PJ~>G=9O2!lq|UR7k@}s&i10Y>3u~is-f$2zBSc>-Qm5gucXn zPZm6s*=l^T&|Ncm>Xq;iYak{*X*-@K#(f@H!GE!73%Az1Y0Lff_&w_|b#?)H=Qb3t zJM%_d%eV{{t@ts$z0_~|sj_XyKuTj6ym8XDf5LXF=uG7ErtP{Xy*Z)2<37XRMJ)x5 z#ktzHBc16*pTuKi%TV(XQtOhmdI#Jc_+uMCdx5Ta>k5~;T(ImboO9Fi; z`klA%gUbT9cynXh2M2Gh*Bpx8u*%E1S{p!Y;ck>LbOn60Ke?%I6V2eg#J#-TNoE^1 zgSrJNQH-+ztJc$$ox(cux*NRl-FW?ws{HWFS%TBQcrj|2r|UQc7NGFANULmD<8((b zX@prCBuPAkYt^wci>6p{dnA)&78$`GH`g`-T@rQ^s6ZrKQg$PFX?#x>hBP6gX1@x; zIz^0R7DNZT3l?+|74ocO{RZ@1i#H{*4kEvv?zppD2= zPm$6#06jxh*|`KakMdmEp<7&4GCqfAUKk!uTxUB`G*-)$E&CkJ0IvcQ3O>OJ9jYi~ zEsGdU6<#S+@LUZ+8fP^}quiSt#?G-8Wmtu+7CgolA{TVNnvgAAS`fCrLgO=;!k;uJ zo9{pn%B748O0LUAJBHR42)46KCD}e~H*+tuUurKJ+gTIyy#Zp!B0hko^l;^eTkLd3c(j_)612UX`w8}e zf^lUQxXCq(4R%FUR~e_QikBi*J(_BU*(OvDAGrLSVuW4{ z!1fP(n0h#yQ3lU(`Q=?~`(&viGsjaMpP6k~#EXR1L1fXfHq3?XfZTxA^ypSlz?-vB zO8h}%D}hhirUsQ#qjL?i00VQ8fteLZ)a_*D_yiV2#xR06cPcy@0(w%2=S|z2<0VcT z*}Oo=2aKI2Usu3&0%;$RfRRDjD-XsNr0CkEq#2P=4&e;Km}rw)kR?I0=n@OWtP+u8 zn90eSm1vi-%>KM(^Q?xNQ@Ok&8*8riAE%b{k~MR)w^(SX*gV==uheC53X#w*5OIO4 z*?>U}4@Q6C3dfqW!csI}YH-1tfiK?(m*9?sX-HEw!pYTK6ce@r-Ajt`ID}`#W!1O~ zE+PXh!%DG3n>hrej2lVNk%ke){tpu=ZN~!GjK`iOU{>>U=vwv)4Myt2pJt8<3dIt6 zn93BMFk=`1Y6zP}7!C~6_K@^&gdIVLTqCi>g-ViaH9(pZ^(i1^T9PiK!Bsq6i%<#9 ziPnL_NUX^Mj|^0;BVt(I_mt3;*e}^2&WqL%6;oR4{0U+^E_u4rt3r7+Y0J@i{mWTd zsD;*gr!9ZC7wdo^4qS}}zzEc-;tiMBXcjpgYo%%9_cnfS@fM5G@hxf;8H0<{gvVEz ziGq1d-v;i6kK$M8PmeLB+2!1u+7LFQ7i(k)0|RsO^)ml)}&i?751Wqq2r6)QH z!}7V|NEd2K6l&gAWtdeqzy+TVW{=1IDUbh2VjtWnM9V?vB(9T(b3A!QtC)RAw3;Se zUNT`r9ou=2rtFuX7=@{q#bTx01z>><;O|ay@5FtpOeW)c4ryJ*tpIN5tgFuAtCRqI zMq`Gvoav1D*@4HOhyK`gFQbnV0n(c6%K&AsB^Q(DH*;&rV2={eKH^*{*C3o>31b3b zr-(=nT-M>iz~)O4nB9NKFf}Nx<-v;wigQNry%q%O9J`JNrD1Gm2-?(?6@mqX>CEAB z4QoahcSc8jGZ!MQ(1Uornyw?am77hgIW`IQOVee}iYSUIxGIj}uM~n2T1cJwQeUCuLZ*T|A@c~)6{H2a77?jnBUyn*3!>QqkCn_e zfiJ5MyR|6OT1u7Q;9m|AO_2VZok(Zv%Kt4KMq8udL<>lw#<%je{W zV%q(NXY+%`a!3**MB0T7dm!1WFZ(ol# zM&@8JE>_lVq^ov5FtO%L~)ShJ0t&3`T~D#%vdCLoVnP55#7ohw(zA zp{=*ZWR}pM=BAG2?B_vgiXWA>q~?wIvdr)wbMMLrdYiNSk|;yN7Y+5I^AhceNF!;f z65I{W-FYnfE0PgLqc~RRtxI2AAM;%=H^PJ^EWhMNNYfSSTlwxC=fD7=0jN^OUhYiGX>(gP%AV12>IX(|4YM_Q<`|;#yv~3owXVK~Fba%53`jFU0Vl z`IEPf!2{9aYo2-L(o@mZbQTY?SLoC9h@l?+p)aq;qcOueIs)d=gf?Auqpsj5`^K-k z^`i-frP-*K#x=@T-+DGZmD!Dfp(uMYxBIm3;}9;29BATil zKhQ(dG{Pk_ugj9eJPE&w`L1Z}TXTF?Z<2PO_BPCg(iJ;cktvs{G>)~h`Lm`AF5E&_ z_TBe6ZHR8YdG!FEhh@>u=WQN-4_49*blT3#^ER^#?Ju>ERcKAA za}ngpq&bNy!dGbDAgxoRwdimR(2EwbPLe{NIEMF7;9DzMW`9uPC9ue4R6)-Xi*#D^ z=&r12SSX0oi^CaVPjWGNw6$LLGYcW&5iLUzmlH2DK!Y#SAh4UZy!ipBnF>`6s{bUc z9(mJtYh)O9%){zTZZ=TAwYgcBdP##U%atL=}n~$@sYg(GtdZ%q(w->mo zB@JBG0L?Xwn??3kX9D(im~f1@SuK2$6i0RZRGTqq(WxTkvO8ZR?5foMcfCK>30{xF zyOCXhfk8Fs;x`zvX`4}kKE?a0G=T{cxC-`^hbluA{A$6BCT*e#F|~tmjp9MB-Od4- zMsx}z3EUcQU_F_#3T;CIiw#rAMJ;z;8ldgpkw*(tAu@X%CU`mD|DOWOQoFVA|e$pE7RK6&_U?o2}Fz#aZdU8Yj zXC?Z0^U%jo@8WPuM2IiTTE_cwNBJhtZRXaJfl0uF_7U&sN)W;s6y}71qeVm{2QJ$c z4X=mctuZ=>gH#G>yNu;YdnRqBrZLw1CW_?7t>!p7UE>T}H4LNDCG0A-69?zPB<5P( zP(>A_^@PLY2!q@trZ{7OjFBD1hqh5oc9HiS{v&cnPlY$~(q`a}gOV82LvC7Vx6u#E>0B z%)Ty#Cw^;G97&l{Ml6WY?ltP6@l^AsEersRTo<7;Syvt<#TWoyF&>y8dVx!IyejZk zKUG1wj9Jy!vo!CiA#$3Iu}`At%tTu>+Okp=-?L+s^3+EzG(Q1VZs7U}2!1?^Y(286 zLoqoYLE#w;%3j0x)L5_LHthy$Eu38jB3ZZ~n+-sTl<-?^5t53sXI%$7$0UP0+{mhp zlr7Q6d#;Y=nGfHX$Zxy@-SP? z81d0?L1m+B2jo!|sXpGURn8#PEZQpBefy3X{fmq`7#&4XW*Jz7QH7QD;3nyG)WL&c?E);Epd;_q+UD)Ph0fORND+kSb zv4|AtY8a~svExD)VgnRLLu)=i37d<~bReRlG-uT7b+R3{0mO zWQFyPG=F!%AgR_Q68>LN>bK;f; z*uvON+kR(Ljb>A2@c8B(ieJ{Bz&rd(le$WUbyx?j_(?v{aXUh;CUX-?k{i&P5yeib z&@@crNusDm(Fg_%!@UUaNdS-I^LBw=B?ZH9>b^HDGh0ivST)0)uSUrfm*#c2E7pv! zq@%nuOJ|%DBR|pDp{fAgKVVPVrcQ4JEnR>PG)7`53xl%PP;_a|T&9p|A#)i*CAfBh zk_=a?I*=KOHCf=1fvR;x40C?XBueO<5->dJbwb0 zH>PE1efdpO{p6{?!Oh6Oie)!#nX@CP8eaH-wd-`Ocx9cUrtGGz#tTgN*N;`K&Mv)w zgUS+9A#D^!`P^e#%TD5@IfKf#))VPCNpD^Ejq|>JMS_RMc1M_d$(Yu#)K(F~1QDC1 zTgzOAUD>pCRieeWIko6(iJNW(4r>kMbeDoQ5j(62R-k zUI-W!{s5I9*5CKwo%j9D6+igYeP7zU1rNO-g?~~uho>nU$9sirv`(p)CJ|BZcY}bw z*=FOFh{QeiMIG+H^57NQzrFR8U%mP12QP-eeFf9-VP-sZ24Ei79G)xRZnbf~@V&iJ zJe8xwiQ;z+)SS`?0LEU+F5(|BStw%{N}U_Q7Tm~>Y`%gha&*EhOl^YJqT5-Z+DK_e zi+*nh>dfUEA!}#9kb%leKvW4+C}l{mL=IyOpvKK6Y>%YVzVfpyURd?I*d$cJNm~_Z zMZ9TSrQLXM-ShctzqR3!`geL=wvw$U`dsXC$glTA2j3jx?hS6BGJfty*LbjP1{udS0g{O(D&AngS5$gxOkY7rof zUuaGq94r_ilZKI0=Riw#vuGe&ThLjUP*d>w&;M#-@R#+(jL>Ido-f3{?#MK zY`79q=O|rsH;uBsAD;f!uU~r3+D-MHzxn8oPA4m+d5sLB%GIZh_Q3TvUo^yvWE#BT zwlnk~GO*UtkxtZi?l@hmTjH6GKUg1)6K(wc&(-T!TzvbtH$VNsFE$z>@g6z@kF!p` z>PF0?w0`*d1RuAH%(XZF|0#d?`F*#aZTr$#JW3m9*}pQn?Yjf?*_5hpI-8ZQz)@QR zHL<+Ug%d6?GOkHx=Ro%DKvdu^Z1b@cL6vXXc2+656@(gpb_PUf4N#a^toioK#r!15 zz+s6uZE4YsjwV@vzn`{uBD>IJe9{&-oV0f18r@Z~CvbEIV3l0C8!s{!#tF_`24hRf z!0+9A=j^bmZu>-EawZsY*LYaocBXF8(W{{8adgx_qQrs}F$R8c}ZcF@|M@raIn-eq~4S%&tPTF5H2 zrqsCz@?_#h7@~x)*{_1Ij*-@)gY$UNLe^1~&lJz}9tw18CCls&O1uP?xQxoHIdY+M zWb6H`R9p~#-Zh8>rf=ppA|jCxK^|?bx2t}$OkB>@(g0f+-n7+}E--T~!V@Wj>c18V zY}!sE(0DdA?;a(!nAig9=dvhl+V=4+tC>@{uiUa_*PcJV{m&n%AK3M1-L14YK&Xe< zmK&S1HxMTYSzMR3Nf!IliACQXO96jjCN>3G1wxKgk0zjFIm>h&+yzy5X1^7gKq zIXy)9@p_C%HO&7tgVM}XJjHnxV=~s!liUa~LlJM*TAdtX!;7<+t{c#S$Vel22o!B2N^+cN9q5e2*aCpE*Df!jKlf|TU1GmvLrX&m@~D{7r4fgZ zto7!pd)nEZ78MGiNm~}-etc}&!Xhzn3@weh_m}Fww1~AbDqQ214^fhnwwWHMTIipx zBc~JE@fN#jI|@!5B(;w4X#LWcy#2Lzx|Qq(w?;1X3_S8Ra>tY$mvD3AFswrGM&RSY zDAAw%9XdDy#4Kq;CgEHFo*VI=f zYJ`qw;UjSjwfyXQdQ_($<&bDzKFiEJ<>r51{amLEMOI(}F>v7*)ZFA_=<-;9c#k@{tgL5@*(j& z-iRM>9{L#S#}1irK@lOX!wuXmn4GYgTT4dh5{=%{TCa4qTw>>#NY1$$4RD*bY(&Zz z0GEn4F!|YxyU9^*)0WP)SVp6#bOdJBPA?`qWs_JV+a1*xuRXZuz<%zpETVBDAC z{JNe23(mO60NDfN=t55nutQdDHfR zD7!_(MzLA7zK7;?hF_%SUdydwB(qbH4`>?8$LL*uZwG@;9LQ77=Wr@8Hn_3g3=~2W ze=~~D6(<Q~NlcH6g_3ktbGjU$uZff6_anB+{drmjv%V zg?6ut%xs?wTDyg8B{)iJp!LY64y82th$F7%xt$+2xwW7$K{yRY6bYx6WS4<-p`5GH z0Oh*k6nB~`E%BypBTQdbA-uMmEF8BRk93tUMD^z%`j@wEdAR=ehd=o2Iu@op!(pNe z0F_vP+GLu{SF;Q8vB!)a{pIg{=u7X|^4crvpT74U;MmXeVgq2)2PMbb9MkwQOS%n* zaq!q!&qa73nPFaBh4-|LsDL30$GsZ&yF^z+=bgLspEuDTT>ac%Tf5e+kwXPyAc)XQ z760%(feD{SUdYHj;Y`q9ul<#_WFGo%HOQS1YygR1kSurp_GB^=!;YzZzgMJ z5Vy6#-$p#Rv9V_ze0D~Q3XflJfa{wGo3;xIj=%E^gEsu(-)#TRzaQN4627fOe>K|? za4%~BEt|F}-gWqY|LsKdVYB7-_icUk{(soB>%rqs`4R4F!PE#_V1f0In6j8Qf6Mw` zO!L>CO}A1sT$#Wetf+D^J$eQ`&rH)^tPWt?*&1(Pq?OulRF3)B{dj@nK=TNK&XC2} zv|Trcj{IN>-vcVU~4GY|i!ElUm4Xp;eQ(v}I(S86@@saHy7 zIBEKDr0r^K+ES#*ejXV^>F(38OG4(6SD%Nc!CyVUe%qD<=&yUZ_c2cnDs0+j^hba9 zs{`0H+PnSL=e@B0#qWHxe#&e9!glz^PRp+*!vetFYB<*0cJ!gP@#9*j{p)jw(VHtf zlF#X(q-r(vE<`l3Y0m|`M0xZ)JPTg)yJx*6`TpWY%&9E1FoMi$-n2#cH26F+reAOY z&Okwq{k`AkhFQX2?VORdylHE8owTY)QFiQ~|GN8fGSikoE#wzkQ|eqA-;;?O5mkh* z*{_1Ij*-@)gY$UNq18JIbD828-oJrttz?<~L5Y{Z@|ICKB}ek=8k)4|wB8lgJY5+g z5}3A`+X#EZ@*6*M%nfGO$L2808dN`eT#QXy z_a43-ZFZmj;QmKm!yV+=AK?DVeXwzj3@(2BOz2!^Wh1F3GXl(&>%Y1Gk@^Q-eBk;| zzw$w5E=tr#zC<&bs9wixaGsS+% zZpvCtWqFU}fKN3?~QUX$-z;mMBhj1cTgo z&dFRCLwK6?RyuOnOuP_9Rl-SIv^X|Ak0S;2Am-9_23SMrwpbbiR4T9k=l;X!mVlRx zSsu-d^+TRwpSu|k$#`8nXMecXZ~|3;p9zETNMqBs5A<9unc}=M0I?Owbha{KC|e6y z*|bF^_{y*~a&%tuaqMwrzg;#a)+DvSKV-#V4AnTmp9S2cB2?&wwNoFs^wRo+_0tbr zyyqZhSzaS=aYS-8c6LMpLY3e?R6lUV_SgREaeF|_)AQHyw;g{TcxAhUK0w)^W)@t; zk_Aqp=f%;Ki}~A#TjJXOfBoh|1HU_I9(~@WSN_JqCV?y%*72Dhz@(ch7PNMeMdwaB zf=c|%moJLsTB9V(a-(lahfD8}XN7&~X zl)VPdpim3Gb0CrfR|^BQL0>WA)*!^8H9)#LRvgZ{Opk^-2VQb&&u?A)?f+ng`jz&YUzp4=mvQAz2{W}un)?~! z`ybZd+8Vr=FfFos6a2<3 zZaC=zoV3;aLU8m0>&g2*zjf<@`lss$zqIS}y1WD2&|*6G9&cr8XgA*r-*nBJK6mgX zr?+?>Ro|cqjA#9~wRoCqKaY$KB(t9P(Pa*hP<{XQ_x;Xsue*NR+Asa_k6OIC1r}vb z+LH7w+lOJ6!Cx|5p=osD=O>ZUt4}i&1O3`(y1tA2hB6`bGXeT=l+xGn;gI#?%kW+! z5~Tgrp$NH?&lK*?MHDZ93bFsT-rGmse}lZKI0=RixgEmD{kfoyF-XJL}-_4|;k#zM0aBiLZS z4v4_Xjpjir!zWk5$6f=u!x1ltH`2@$zw`f=W8QN9y0jWawb`rF88w5Gw$r27oteCE zWDrk-x&p(kF0=}=yMY>Qx_?a!FX7K4&yb!0Q>48VmVjeL?;7>pg1cl_u<6Vj>1Ibc z28ja`tM{gu$g}EgQyDM2hwv0G{S*FLMn-RXVG0@sUW%842_!528LHy(5UGg~vJW-k zl19e0t}J|YWIsu=dh$Aa4P0eBt6R!b+ZRDPJ--kZ`v5|wno>Wihf8-yr zGGL+nXe$8U(eme!b!xw7p-oz|c|GgWq4yZ~!?mE$pZw!hCq_x{wlBSG?N#Wue5dQ~ ziG!pz5o|3k#E3-9drdJ-{T~`UPKg@Z1qAjx`wq^zIk# z{0Kh{{!#s|`VaOlKPP8-X6zLgTW#PnqZgcTQT2h57u5HR9{ir$>cs-P8N9WWIJ}Yi z889|ov1QK?=ThK5{nqfOKQ(pJH6M8ON1xyGc8nl+P}V#ape%m6meMSN&4Lx)Q1--d zQK2Hic*9D%gdk8JNBh<+==IGhMMDi6tDxXlT`4VyF0-I3nc^6PLCZlwNjv+sZ4_ql z5)d`TQaX_<*Pl!caF0bF6Ubv0VLh7Yo9{mFJU)_s;D7Dgw_$yYb8<`^+EPT((nl$M z&;NSGCBOTIx88MrJ1*s^mxp>e3hz^W^>@#E_(`Yy!Ud-$`rjUEGZwUBY{Uf*1JX2R zti+G*8jyxnQVKg8HM)0c>4d}5HFIm>4Q_4(!9gp%sv*CtsFmEvMor&x7yd)#$E!4t~O&nQflon1@X_PJ;p`nZNt*>2+`T z(Vbfk-np;-=^nb51px1Xzw5?4qqv-bS#OdvH2&kskwTR5Hp06zy-4uFo<4K$j=kAO z-n#m@Z1|Ly$XL*{MrI;NbB4Im*s;jffo7os77aQnv4)y1!E!oUEiADMomw)2wc4~K zI1n-=C})%;N`fZQr52P3Ytk=9F|J98xT6+g4lJo^K!g(L24sW42JBBdinWY^4h^s3 zddE^rA>buLFcRsGVAs8hNt(HNeZ*Cc)rIC`TXwb#rKpxkLq2b8k%AR$Y znyfblBlI>lC!-o0-B*w_OeaktuOPb2g22});`Q76IStB!5_o|DRu}D8wowvfc?qqk zfIG5atXYr!X1~T}SNHc2W%-gbW@?!5hqO4l+4Gj~ANkD8s`YHj%b(_~yQc4xIY+i@(>xCgvk9yOE0J zyH<`GUSN3+ocZRnr=R(; zfBMT0{qwhy37L4)iD&u&^b}F5^~*Onf=a1n9I8sqRXgqsYfW*=k)N<0caXD9jf$N z3ls(Jie&Tz0`jPE?5UvlQ04(h70H3C(E#jvE?&L9=BgOIWoKnL&eF`jm^6{%i{Gnn zy=D?JF6h}ffNXqY;#C?!p=%VA+!xJ^)jKe+>6s_Lw?bnvZQJ$NAAH%dJ)8f}3%4Be z?d9ilv4ovdJlFM^jH>Usc|v6xzlw>odR0oy4L>-JH*hRevH^4RXJ6EV41k?q-ohIYm*i0?V!I+Tr6FWfpl8b^yzwrxjx2Og6x-gGw1nWXbJowsS4 zPXv7b3nwCJc71TqBmc7a$U`rC+O9`_AT~67Fk=h9V-?N5V&Y~4_Dxsan7j(S)wmi@ z{yxt53{0e>S0Ur|*dLxeb}kv}Pp^N*YP=#gNE0;>uE0@T1JZt4ihyZ{0WQ@&YxYt^ zF@GcG*6y^1)vTh~%A0!?pR4Z%p1G(T+0Gu)%21VuiMfROR*&Pzo(M@n^Rfrl(R?=& zL6hPafAnOp-u7J#A>k!w+*+oWAlDT)e$lIK8)fk^l-+@oxtI0ous|u%6Z*Fi!a|)( z;}@C}cO;Hn3zsuQ5+#9>{AST;Fu@lr5Nzkb>-V8^3-B~6(Lu^GC4m!zZ;>jbS0azS z2IdCt_uo;94gapynDR}pxY^7q{d~NZ+_Mog6k2IdG!1WWm{?myvHo53mc^?{KkeJm zG+Y)(2lkx(;MJEr!js{KmRr4=(x(n&Al`P+2p~LB z_E;gdS_U7*=JED_`O^Mh-%@{+Kaac%LZRP-#>aIgZ2}gttR$A3E;Z#UP{BML0D6_< z&@%|DxV2|m^b2z%m!0Q0F2<**ss-IT`C=5YG^1hii8=l2H&He4=21XlN(R z;YGitzmH!J*pG)+TOgwOe6D}XA#;z!z%_0;CvaF0R?d)e zX1_ow#`DGS8KPa=>pSc9@9a9=eI6OI+d~xLz%E0QXfEg?%0=S}7wdHqyXZNwI>{v& zy8=gN4Hz=k@WhS1%K8iYvTOft3dLVqaZuov&3;YV6L{a{!OmD@LGNgw>?YzR2d+i~ zv>lz7SdK}Nz-ke%4ciF493G6%5G&k3VxyD#Q+)CppJPgTsnu`CHumBTkdw?NxZ?Y& z3U50ki?PnueFu~6&FOQl+*IFw@ZbiwX&W<<2lS#@(x#>&4ZC`Wl!8_GIu3r4fbpJ; z_+Y>@NNJ_b;@yfxKji_A1FDJCI;6r(~m2u!D|!9WWY4Mh7UTy zPKB>iqBXJ1&`StWPUNQifVnFWfmWvF@pbOrw7@WE2SNk08K&(O7f)7bU!UDEEQk)K z7W_%bI*Rg{-Z4~Yl!B6W_Ky}NaC%uOJ<*X1ZLO17?Is;4SBGGLNMMe{u_+f&@gl%>kYN)$vTH3F6U}6AR*k(+QlgP0{SG?xL6C-hqpewbp%^Dgh#D$6d|JmI%P=5 zv)uB4?N909Tzn(0 zp{9`67E%m7Cb}N^IGr;zq^?8k)|zdIi2AsX;(iy)?iyD&htRVPw0%f+1tzCzZcQy2 zQuorFQvb-4rZGa6X9%K0pe4_VHaTT$3-bI9G10FAiI!N2{gMshh7#n_+@FKsBNCDJ zW4{3ysh9zm?8>N`qg~Ejkqp`Y;*>{mcd}5>8=h_|mtArd$$_iUd{nK$rmaGW48&AF z)iXSx&^K7*B_Pap&s{Tz@%w@^o-`1nU(=rdtu)a+TmI#5uRKtH(Z2eDNA~0K6VJ2_ zx0B4R3}5YgG82SPq7u#5!Syfu*8b>~`##Mlbc(QLa$JqlJKo>dcZX%=QcsynR^4}} ze$wdF2mft7|4g=Zkcv+G=ObEs#<14p>irlK90b8(oe;nt_F+} z%LZRMvUg@0MA$IRZheUQ<5&}6({|%1mZCd`UzRD%wfD|mJx!6p4|~9?7wLx2qR;*E z{`#lizIh+|Yw^(%q$xPchG_fic^-@Y^|_d>&EC_$u>KYrn-m1t#k-++H$FB#i^Xf@&1b5r0s3oOUOBx0BUbG^k=7;jp}$h88GZ4w zkNo0qzH|hiN8S$08t<1e^nm#t%!YdPsIY|6LL;0?l3fNO zIp=CH07cMGzT67R_(AdUYjGnO^de$btydB01-of$vImxWj3L_b_J79H+XH*H*Z2L+ zU)Eb~xnSURYLp^P*RR5oHmk3B*FPM5_zSQ7#@GMoA$(PN8K8>#>0_Tfk?v-LuxX0{ zJE{%M_VDio^u{mZF68PwRSBK3=2!82nbL=6vaEKKI%DhJUtYjj{k_Xh+9uj=+LBgg z+qpwLLG;=J<6=0{m-WX=Bx8X*%eVw1)FD6^K0Q~V&RygC6|oMIh0G(QVM2DNh?2}^ z(NZMj6)fl^D&(<#Znj{DlB{MWTCgpY1Wux5RDo+H^4M!2nZFvlq38|#@S)bXiByBk zB;7r?DjUUY^%dK4=I4GJzL$;NclNVSJFx$~yT16XZy(qv+pnQ7SbpO@8S__?-4)I1 zWOx1KORqTZDSuXf|Gssv#bj&2he%+p&AOlAejyV-0Ob1D-g|pe;H&?J-CuDZzD1?k zGuDurQ9E99aypYO#`M-rH~r^#BfDvPDp+&Sh+@-rbxi3+L%r0?=?19E49h6-b((gg zLj%=H^ysSrB_@m46z1Np%Htg(%w$^FWPED$lQ3i{p=s7@1lwgGl5?&`^Lc6oV7Ae! zUnxX2E?CiW%!naT#A!7>&RCkuz1yZ+Ul#2BA@U|EW%G?Tc@?x~!EL2I-izML91JiE zlOy#d2CHOFdfR*4ooFv%Na+l^>UfNH;VoKCSPq5aZ~+znI+*NXL$PKQERnKX(z1&R z1j1FQb1Ate^Q8+5a6w4ng0M~zBbf!!!R~?uokWE^uiuB%MoH0rPZoUJN-RiP^(d_YL&jQO*j$TTV|UfWvS~X`r0|bHxC@(XoU_OmhBkUfU2a#C z9=p7@^nr^FV3ac;!)#`a!*&Y8;0{c7^tJk5J!M+=MlreH-GV7MvM5S;dQPr<=e`5` z&*#siUV0FBw!87V1Kv(*gi$rS@XzK)PwJ2Q4LTt@PVWN`V$=3hAG+^9-*)>x?zOv^ zs{ydp%fDWWS=lZDV*a$c#+y)S_LMB+Oz9 zX)$h>Nokv^A?=>VR3j#e>96pPLO(WbYs51rotV&w`Hjuzqg(9Svc10f-RNz6^7eEP z=TJ2?#i@!iacp>>pkF`AKOleq&cA>71AF$^9*f)BUEuW4L)AgMIh*uO@OvN8BpwX$ zJlJQjh^ESSb#=PMq)Q+E`uaZh z0<*6IG5BgZI+$6Sr&ag`>8r*66)AHI8lh*H^rK&V$zR_)l8vQXzVV6A-Opm1yDp9p zokP57J3Oi4i#D2QTO8Zw98PD_OCG-GPMVwJ*RfNy=I|^H<0QrAVZ7E@fer4aoFgS5 z{((_S2%GD?CfH^-0#e8dekIhM18L5hP?cEFS(fB_|MKAzd(*b7DtY`7#kbzEex2!C z;*++D-(2L$6en%*oETp>fAr4N2hYJYd;CQTo1IzhWmjRzY_MsYrZ<(A#ZZi)R?}*h zYVe!Uzm~jlDIbyB@hiTg{N}A^uqCwn_QW870Gcs&fSj%%O*m+K-n1DfC{WY`L<#ik zA)KwKpGiYe_9W6#Z>nNir<|N<^*oBccl|nSLoq0OUAY{kHPCUz z(_NXOKo+|g`UZos*QUjVM};Mn78>DHlI${oe={h1<%@_}I@$e3`}$3|pH1x79TrZ$ z3Tx3sNVUdm2z%{sZ1722im3m~_^NnHaaMoVs~`D%ee-|R_wCt(9KN08#b^%Mq!GPK z@%ZkWdcmAd{GPsh>4C33_vJr)_E*31Pz$aMuTb7%E)R2DjNM|xkCU(-w$F@2q+Nmj z+zmszA4ePZet7H2UwPr#|NWj5kAK@=w0!LYHI0+DOSl`rsKn2R-6~0A8mE`x_pf{H z;&qk~0+QqRL@^c+99Lbg?gE+R0;3qJ5M_|YFSt=4)0QYSjHEgTO0t_pld~In1q(V0 zlU#8O?;t3@WHc+$f^DJ1O8~_(s=&1p`SEK&Pu{c|>#W%<`8#*g7JbB2KUIN5W4u^2 z*KMotIBAJb+L}>XIPuTXR#Ck1x9j`&ZGW`BWy|~O>sx*37!InP5KN%8o(rRCP07n& zkqr#@J}Z6a{+)mQXW-g}&W?xB4G>cWC-O1d+vdkd8xt3UZI((IN33wu`|)$*DpHl1 zYc8mK>K&I|xLBKB;7_Gv2x-2{#`{h&Hf=Q){`di)S#d#UVC~)>TAj}0$F^P9!sDFU z$2U7Ac^B~MmGG#l0VUS99CS=qMUlY|w1pwpI%s%SVPy%b-C&n141}FbD9q}?0Orx? zQyj*Fq&Wl_bQ(-d4Dx=TvI&@&8jj(cHS=43@K5;i%l7)gU3)IS!+joki%@ZpLJF_6 z8P1I>Ty0~qiSOEc!U@}_E_ls#m)~{jr+Vz+p8{8en^k}}8LM;KZC~e5vu~;>&c+tb z>OP(^QU1ZD*Z$Y%rN4CD>ia)iTmO6+3*?T`((;sG+YJw$Y}ikyxQtjwOsHNop)QPE z`J;ZU>j5(|^VyR@j=KFdBNZ~aMUe6Z5WF-#GAvj#I3{GyuFxxkQ2jo=HS#qJ>5 zlLeJ+#96d>ruWc%*eWOq!V1LAo+##R2z8zD-J8_324 ze~CNO@lP;8Gb02B7?}6_o~m=}y?gt;cONni4ECAnTUDpdId!V))Sp{*tKLn&ano;1 zSgTGDg>Niy(sr3?qPRx(gDGIUL1?rstKr2EuZ-A+wd-8nI5=*QHe;q9S=O)*(`zmr z47of<2A-xhete+u)mcL{NxW$*6$92TU=^8}uw9TEH1Vyo@wehvBi~NA#?J}D&zrR% z;U4D(Wuv-?Y>m>`1x~}PuOZgfVtU;4%-K~ctgD+7ozVb{ISsmsN+ZQENO93v$R#4B zJ(EVKiIh`BDuKhRs8XUM=h_-?+DPP5R@N~tQ1BE9OqJngbFtvd-CB;rrIRQlLE&sE zRf*{8h-A-Y6~NG{Fh3rR6omJKUj@@>zd$X(3=yVUDUP_>UKUPqL=|2{=n@oeiekdH zzzq#h#kWzM!nu&p3s)b^{>(%xaGQDXp>X)bYsGHbLZ0H%f(`)Qv{h*dF`^UbprXi( z55^j@hHwggfhp_w=JEj`wj);%V+h4z`&M?DfK&37W&Q0R5d<`292Yl!25q1Di7Pk+ zgv?0LMYNboO4r8Kf^(&6niOp{5M-08txptFK2nR%C6X5QD*YuI#LcJ{Z;NSr$w$J& zW(}w~$4D6rxnNJFTz9m1=D4d8VJ*@5QkljfJ;F+(aeK%=D*~v-O4X0qLg!vsELG8<(pZqH zRHv{Yb=)=MDk8fIHm0U$Hh&hIw!?~EuLi>%d+s!Za*s`i!_eDrI#VJ4~ zu@CO09AwM9F4(LY0V!m;`n7o!mX3~8XI%&iG*BJov_zzak-BS}wk?J8g7QX7#GAGW zCc%{?lucV`Xg6&yz~1XyHV-G8dF;48E|cbywll4>f%chEk;3>@KkMUfxrPQz@Pm3O zs^REOd*T-CLpc<06Mym%sv&{W3M z(rJNiVQ=dV%rNj*RLW;wgB{=VhWlnH(B?mF-w>dyGB1BHE{AjjU7+-i$_e}m5XLJT zgUH}(4&Ha_0dx;EYb4J{2}u2=6(qf3@@!NIEU^J=mfMIB*kKAL^`wTb1tFZu$M@tB z$xW^n1#}Vx^^!dRkYMq25Z5E?8wX7)H^eoo8x<)Ecf6MPgJcWBpAvO)eU5bf=Ika< zCk`&=J}w`8qp|x-B}~Z-)e>ymDB#EbGhr{tO>men)R`F>FdZS}>ya_(>TnITfb_HJH6THRm<5j6Tll5A|zI_|fAy?+E^7GZ{^@mCpdMsE=s~ihu zMWZ7Ud`<(wc6T`a77HaVcMI7>v|zpd$|G8Gu!_nPy)Zn!&W^Y`>N%$fyNvc7mERfd{33}#zVG%`dBEoRbIA|o}KmHFKi4F(Z5ZCxf9KZB3{!;|nWvRW!BgmG;; zgECv#F$%&%Fduo4Mshe4?zPemXPVEuEF~JW?Q~2}>PhDZT5084*u?N!%T-XFIy)nr ze%$uqwjPn(fotn1&S9Hz|^ z8>F(y67kNkg(9vvoa-~pWzb0BC|Xh@_IpS}0skPLTaJQj(4X+;s+tNbjPC}aiXjO+ zQ?ImS_A&K}LjZ=4P2GWc|O98MoWF2-4o!e6uA5bgxZM_7RZ5 zQXZa+1R<6o%tGA3F@n#D_BN5zz$e*3oJC9esfD7<+9%?LZQ1fvB5Tcg4ke&d z+t8CN1(l!H8Rn7$VhfJOOt^H6{aGGF2gV^fKlvnr5W(#OVPr@U2y}$$U>`vPD!WGaPNE^u3 z7&T@TH@P7m-D#@o@L1pd>i(}TVG>ZmrY)irNVsQ1EOqfeg2A zF23Ab$G!IHwv=i?sy13Ad#<$oD2@%t5N}+f#5LPjokGnhqT0Enb%5)UxpH{Z7GQYC zVoEnfF|sX$;dX@WA59*2hg3oszyBM1!e2Wd1A@b$|-jrlIr5EHZtaw9+iRGQ_4zu>y+JM8vK}QoLD=ZVG>eV44(GKVOAfB0}d% zbv9*6)fgdj5iO=7_;!vKq!VqLByBYiWRt3`PZU!=Qj4!Ze~AWhGixp07Sr~UkA#Qo z4^VNAkus1?TZb%o)_r`AyDAZ|#1yKj$Jz}7xpe*ZtEcPg5y_sbRe=!Oqr7R0(vI*K z@^9KIN-#tcop}pSZtwib-H5;`f+07sRqHg;H93x)nx$c5sfLo_=!w$$szEC#hJcpw zrDH!Dm_F{}s^PxAN@2ZvO{jljKlLxg=tTfk><-yn446Whama7)*tFG90GqZ`XqHx$ zu{T}_;h5TBU1~cF>tFh5OsSau9bI?=jnDjQ`5U_ng{K5!AJ9xNCFi!^S(WMpiIC;$ zS7dZ|+KcX_L3ddaYl{^A)Lq-O?Wx#~JdrVpe#g!0mT+v%V0a~LkKiXKVZ(eq@(mGx z3$^d`Wm>A>H*F_eml{nnX)%C^uSdrEPe3PVTqd_z#G}w(FpZ|`NX?!1;r?1UWqIP; zV-pWmG)Q4)gukU9egDnBJ0M;zGvG~m7B1LtYX(?gp z(TN;glPjY@DM_zKRygT`OUpyF!RAk6#g)LQv8vZyJ#upI+oguQDws@uG zOy~>AHY#-$sZc=PC(G&U0quD_skj zRE&hWJ4&LnqHU4bn4AXPg-NU}QarpKN+Pm}Xu*2@Q?eFLqE%F$Yt8eVOCX7H8;v#o zkOmEJ+A11>-8z_#xShsm?gR>ehg;Yix&_RU zv5hLWhtq;8p5PWIilun|q4z?Vis&D(X^U4^K50vHBlRrHe5iRcuF~#mZi?g0@o&kJ zt%Z)Z5>TSB7)`Fz6m0iQrH1B*2QBo{vo*(nmM%*PO*UO4Sl`+Ca9fW^ZgRD%FY7sR zh_={o2O-6B041#y}Aoc^P0N7>YpZ( zEv;3#?4I~qZ0{wYluqjigOOrJu><&ccmf!_5^@zRNSv<@8{6T5L-sBviZIC~xFGta`XZA>ad%NX024v7A; z8sTVcftQ5}!N~Q<7|oU4v|a9ni(4wE!sU(Yk$FyxZO|n6&ol?T=5+0*En*b@k&25| zF%@v(UX5X1UL!S6RFCy>U;7E%{LI3E!orrJDvG1513eBm3Z@OGYZ-fZfLOo^w7IYd zo_hnlfeCtf3eY(~Zn8|ybhz?JY+$4qq z2DA!)+P0GIHl*3U>SUJPlCQzK%p#H)Ldy%VX$vu!GizL2W4|T>OE)lXI$On0;wr=Y z9K&H#fliDH5!jsNGx{1lQ}~o(66MnmEf`Nw+?H0U4-Nvr7r)wS&?-J@t9ZyBie{1p zaN;;E7jA&LL_AaB=A{Vl^_CW?2X%OPSmsm;!89o#fI-S!+kmeqsm`WMAu~eeB3evE z@a-HeNE8jg*r$E8)j*Im0!@?^4B^r^*nm$Abc`#UR@eTIr|>M@AKXb&qp^ z28N_(SVk3p=s}=7mYL!24hCa3OG8^iZZLe?Lwv~SAYmq4cijtii1^zL23HiW43K6o z;7mY)l>Zo5V}KZ}wgIa!d`3cWgiK6GB8s!b00T~UHMHM}a5J(9ilud*S z9ANCzK3pQ&BaHX0rfNnVA)h8~Q))lu=}CztPnDZ6<>uW?Hj~n}Pq)Xff>I$$DpJ;- zvNN`2JMo<5;Wg3rb#5NJEDtQvOYymyy}ln`HolTY8PWr&H8X>zT@3g+%Vg(MwWkce z(ljvFnWkBFV-E4LlG13F8dNGAyn%_MSWh7jifRbhTtu2bz)M`m0AzQ-EFUmJ^Xw#0 ze>(ci2M?~Fr+JO}#4MYpp`?aK00P7M0;FE7zv!VOO94T-+T_;|KyKz-PUUf?7_xR{ zQH773Xr}?V+G|iKjtRsvc^O|Imx!&FHs3MkP0Mnx%4I6_NALQ=I7~^I@GuEFY+^LG zC;Lc6-k1&wDMBhGk|XX5z2xDe$~g9Ukz#r&%CgL(l_Q2~8|J{jEVAfaY5cnG*1MDv z>D`juJDnDbx#GA_`d~mE3Zs))}d!8>h2T1mouo!p3Rz5M{UhKDY6tWg^RF**d zp3PfP4|y_8nrxS=C8EWuQ&gwUuBV=}nVv{)aW<7?LBX>SR z@wU&F_1b{7j<$pNFYO`S*A(5w*OG}Fzr3-e6gS2K0EOO)L9aG}>z=O01yVJm)XJ@P z801`hDBY3K0aki(a}1DBsw-%__q=62%_4{Bl}M*NxRGl3)=#g~5Mt1hFF5vRkh~ux z;OiZ{5-AsCGDw*l8%Wb7B|$&1rwFMSAKlH^wE#}$D=L$HNaRS`{Wx@`TqJfaoC~?%<5d~LNhF-BDJd?@!F60nDGt`g60+CT> z^J~9x585+TITGM2!3DcM#Xg!`xiXi^&zX_S6qs^$)itR!vM!#iXdp%JoCYadS62)p zH4v1MkY^J~)%E(PWPF=}hgDQQ=E!-nGY%sOJCn%{U!8PnP871-q=ZAd1P(R5ZPV4l zLEe)h+Ph9%lh|lEjWbXvZcZh0B*zg2gHtQWLyZwHf;^ zO;O-!4>K~^L_PARLKRC(x;>@G8Ur0_NU7g|G^Y1rvR>yIE`Jp<5Bzo@As53qKA6TE zvkrCfRq6QVc$u?Wp}7#U%+1k=+lu1fvBr*YodrTerg5gu1p!d@Y3#G;(KG=iq^``N zumvsH(7HxKaD+_wCBjiPiQ4p9u$U4XTdK4oI+MKl+E%W!ZR z6fDOtg$OR6C=MooHz@w$13wSkbun!~E_(UWBGRq}jwox{%TOv=Y%o zs4yPAl(S&h^VYOQ7Ci9Vu_=X~gijkkvZVNS?lQ;#12fVNBGMebA(@9tCbVsU5h1?S z0t~uS2JGzuj!R+hh~XN4;p8CJ+mO4D;(m37&#rn!;%<$ zPwRs1pUR`P_=KA+2Vm^eJp_e7`*eMRO~MxLyw?cAbIl1t6!7$tSQGuV(3$h=ClwP# zSlES1n+!VzfRB9ZDT%V4Mf+)CitFfV#F*m;u~J6(L~7QZ9#j*qe9E|e!g5|R5?lgL zogyPzTXg$}a_D;{V=5B$O`qm@L-H!f#H50w(?3Q#F6Eqpr&l5sE%Z|6sgP`SHY+`A zSEe8_7u{a8*E#i?``g;Zi@BXch0sA zB2SbH$JCc3@xT5ZKIw?no%luSfRr=CppOGLOxkkbmor%r>(v?!(Pbzg9m5 z*CK|?rH#W_Q?i@3EmhMcCs;c+xCs$mgsLC=nkBLm>@M^i1=|}O+hWK><_F){8pVA; zXdVeQ1sA;T8g-fugZiWR<_SLl6wKayKGv5F*opwR&+Vy33d=&+v;}dDvq<}Qj8HI9 z|G9^g2zeK~8_|+C8Df$Aj~%=~Ec9@cd&LPcQmL{vRTXScDfD})EH}SYG4M-P3W6%$ zw1vSHgGjCmWx|8Y7&xmy)MV54X4om4>i+(Fh%V&jgSe?cn`GTtL;7aw|Jjwx=#)fZ z)3&5~={_O5xT;5_&B%Z@44I8+2NmU!paRpPhnd-vV-iJ;6K$T~9pVVp##{h&fK zbe|Q0Pr4}l-M5VCUJ79D@)(y#Z4bg=7`@UE(y-a9qlubZKe2JUo+X;rbh+K5lucWt zi%Kv^%+lIKyFA1`Kmjg>T$xMd=gi2HKrFYDG=~?&9SxrmopIBb*=SO6psVbhkCi0Qj{YWx*Iq--|;3s_8$LKWn?fW;u*7^H*?Y&0%6|5c2E zp@Ke!zhC12D2*u=f_4^`L0%&JqkN3&2>2K|gh*ZvOL)Hsugk{1ccWzm(6YV^R*jTF z;~E>61wh%SvCpE1)DOs%kV0FA*g4ucoB@EbPx}xu;g<+U)g)@~%Ze`0K(&{V!x{-o z2_TeBq?7(y_%c~D9?4bre1PV91-v*mZCiJZVIe3}Gy{OEtlZT{MvRL$B|FDb4PU7$fvGQ}{C{*$&n<@RVKN}JGNbq?yA zGRBz^(tr`)bw(T@A}aA-fILDk->w(-7>=`<`d0fZntL6Hd2=iBiGSUfO6pxozu# z#>r$F0C^D;0cQppKCNQSIUgx+q8fkwaQmsQe4v4Q$%@>5D{j20-`?1^ci&^X4sH9~ z9iRD?2GP?HdNO#L5V)Kt{BxSf#wfnGvc4&8n=^hQ3?FxdajHqSUX&#*dPqI_sx!hM zWv(Qct&TnF)Mp8E2jzGw7s~7*xmgnVl!9BBJpUVFOGj1 zFX923>DH?b9el9yxq}C{ed}b>PPWjqqwpUmZSkpy;gh!JI_Y(k3F!woia4k7h13+$ zeJX9Z%+))n-bvRek7xeSh#HY}V)PImMFb*lm~ zsbkLOS33)Re1Ke&av?PrjMq!+6S`LEmu#``zr1PdyH-cl_G!Xo+C~@*wu@i>?3W!Iz)|5SZ)3EjK({=o2pul}Xm17_x2jHR!~I@u1n zCs7#-O5aD@-}M&<{^v7$etXxU5`7m!GkrlAE#llR(!o&8Cv8U~76-r=UwS>x{g0qL zXJWc;2uJe)xq7j4Xj-GKIR$>qt+@4ECVnC>p!v2+K9|H=5LKC4G4qq0o$m(f{*RyQa+B!pXlqOH92ma~T4Y39SWQ zI3-YVsu<}@WOJ+fY!q~_WXzG{7Q1yj4^E;t<@V{;9aXPSk=*2JRX{0w($;A||4<$<<|ME-vA8)6PY4R(LTRXJ%3GHlw8CTRPB zI!z|@JLhkdiV1#o|GoDxzRC|kPZ~SYmM^V^D_7={My@*jrf1HsL}+)XF40-hK(^PQ zyD*6r!$>WZ%g8}CkyKr;e@fyZtSV#JxFvEAmJC#|6p>NLVu>Sk>tnV=i= z;odfmAL7I@@WzJBKK-_B4UD#b-FW<8FeGlnUn^{zqP}Q1Qo=8XsgO_FjvD;-0j9wa zVStD6@WmErSsHgM8fT#={hLGo>p#BzQrbMB&!5Lg{wPH5Z4p~CH54Lm+8TSv4-@XH zt;Vq>74@_5=_$yD+h)^Nb80<+*aaw+P;<5cxd}Hk0T}zV4$< zY1^kuc3PLx6uL@G$#b`6X1k5kVjeH!c11j(;B78HN$+311J=IO5}JrZ6*M zB$VA8jj#M4xu@~L>yeiQNSq1FwEwP0AACO=)L*2H>OksoF5W(mgRaV8Nn2ybsZ7UU zZ5!ni&uGSLiVW_N0?Z&7p%I>nRjx+kq5pN#+Xufh-v8^{>JW4{{&=1&ux%WC3?tDL zcxX8uiPg6o+YX&Pg$Xz|Z3od6&7yr7GBl5Vfn5f!7iE3L4-LT%a<%F9&CqzQ`KQ%c zPN|V8>&@C#8r$8?i7wEfyDW)a+qCUaOeX9Q@qD2}t&p_F9|l%-C_av~OqPP+l|b+z z8H{r@>DxV%6##A=b`)yL?Yh8jue$V8pZvSVuBRIxJ8)ats#;xiA<;4y&?w%E0V+Uq z*bEOY+OUXdg3$oAglPi6;8V=s`IpAFQy2d-JUINaxAE3b4%U-C4`kpG!w$#MSQ$bx zEH%OWqJ(WQR&zRk(l%hi0$`0_Jn(|E(C1LJQhT<`bVkm?o=trzpSl*Ga9ew{2IwgS zg>d_HeaGrKx_OL5dM+&prvO@pTSn#&pg6s<&zPEpO#=p8zW*jtuxj^S$ms5%w2Plk z&?o?XR6qEx_g}j08E#g8@OZ9qaqt|XTeShH35?;EHKC(n+klrBF@;6BW2WtL5$z0F zv)U|vS?s#+ZrgR$=`+>k`|iQW+u#v=FaA(U#cZiU#In`szoJ26H~>eEsu8Cw53H& zTX1`#uMQz<>x|B)>sHug*|P6+JI!uO*+k-`Eh@VYi#c(m?tJVd?j&Fu%Wr2}j5K~S z)6=49-MjVr06#Kc2r%PV@ny@wqP<7994?5QFrXiN=|r4zFtLUhGbs(WP~;lH(NO{g zolXy#Fio0lm#ZbB#bi=cr_N6L)277kK9MY3a54%6v@*ZWorf8x`QKUxS@xrSmKhnv zo3;w$95!tkL3>L49#{xwA~Zr2P3}1GrP2gKdv`zmFOOgGOyd)c@Bd#O3$c8ZfrMEu zGT2L1>c*`P^SA$mh3IShDVYfD4=8>SGLTJND?w7!RD++ z5IuB4o>i*T2%3*5_xSDkrT8mbug7)`bTPJN zjgGFEUzi)l@&0R;U-6QpM%B;%f1hAUyyVro(uJI1yvOy((QrchuPYA>)7$BZmp$>a z^6eDg`}6zIR|Gmh7csdr4mF1RA9I*|@#MeavSOq!k@cGDv&kSY={U%7XE)g_iJ*#4 z+NL7Ay4ejx?RVCymMhq7&VNb&8Te9aB1+t*?FDW!T7$F9o3^@UqPMJEwrKG4SvYAs zE?ul;@A!xpZB!N8F3Fx(@%6~`^xbc{_^}4wZO_^F)_rMPZE=z9pP{iz{Y<)uzPs=2 zkIyUay?^H+T#p>kop(K6L6fdS4$&#-QN{+h;7DJvGJER97lwbOCI|le_x~EgKGq_T zy(bfWlt%cZE!*R5lSA4qZb8x{#dkck@g?XBlrgk<=h7E(XpyR%0Kiv*3wC{qeKfhU zWe&Y9@_UJ;KX-?m4z;Z%;;4u-Z^K5O7alC1Z zr=ml_q0Ft?%=6BfdNUP23f-%yauVDV^kY;c44{fF*8^i<=} z-p0TCJ_g-Y0GWMLNU2|qL}5&4k~Sf2P*k78aLIT>q;0}66hq+LppTxu=T-4BSb6Si zyz}RFK_vGF?50o(&?SY~wAJ{Q8Mz52kYoMG%7L-60vqyfaO1{sfbDCWcb-yPP|oS; znRu#{3koyD&e6^xSDi*eaD+_wTOyhyoqSo*MH+OHlEE7ZNeLj7O{A0lTKI^J_qBQ@ zm(92%iW4QFqOj?yp*BLaO&NgahOA&<2x2GHY1%d~8dA0^AvQB?uqej9bbW$NLeIO}V+7^7v>-%%4p~8SF1_)IG=qOK z8}kN?q1Z6dU)#=@H*Jg4HKD3A55GqT_I)R$2M+w@!9#l*`+o9|5ANG~4i=I3qJ_1< zIrs{TYL>~pOof9;%a(Z(eHM6}8X%X8>UC}eg>oy6y^r$8j0`8^BP(8<&YURX+;BNM zPO3$Ni!KdKHhV5WhKqwUC&eOpR1)3Yk$UnaV}xANR1(ZqCzq^)tX-v8iR|FC7u`t% zNuh%*L2GtR(?WfjDUJYi(qD9G<&=tJF2j$b8;TA721ut_elmk$yuQ+}lOVuJTa(&#S4DkACQ6wtSG}PAr#{?+69uXUgE>CI9dx+hBKZ0{@ZiKs%6)7Fufp$izUq7S5=j2C*}cpjdIsaQ z-iwed$}p1ydp+_Dm2e~x({-m@9T}OM`FWZG31e_jkc=b$aeltwEcA!33|G%=EEcR0 zwR9(f?&g?gWR_b?g!J(oN>QCUyJuOj+0g^?TNN;x_@pgp6h1m$u$#7?0tfBx4c6-# zg^$#2(~kM1?Go!)00!~Wb^^NP%iBv3Pxugd*RIE&*>>>Z-}%N>PjF+)f}K@|Z{+VP z=*?Aw9T~G6&~>luXZ=RrSfMc8v?X&5-MX&d@FKvWU2d}dOk?jsT=dLxTj$8QN@v7w z+G@0U-n4}^*M5YYpOeKe~sTjoYY>WuT8q~%u#y|lFQ4q!}pFTf)MJGwEc&s1)pkBp~ zf7XM)wNJO6O6tuO$xW^n1q{Au=s!~`pCvO?NS}CgT!&k_A)!iRytUuKFPGHAHe1qHqSo0dA zzBA)6tY2~0H37<^Jip`g{{A3QZ=rRS$WYx<8+^|cY}`7w6XWJTA9(2dhwzqsfKF*$BcE+$l7j&`Xa z+&Zb~@tTacnRxs2sGG&A!2Dr2UY;@6sFUYWvay@bX=f3yEP2V}@ z?;4E<8<@`W3>j0@ER>WDCul$xQuQ*q;3AV;n8vP$9^!d1zG^&YC7^%B>U6d*0If(% zbMp!(nkW^{;WY2!wnnAo9o>mECgl=sbLpnlDOn>Dvb2CCOR2D~ZccQ8238XWEt@O?#IFt?Ew@U_u`>&a^#-g@zaA9?p>^=*Ir3(tIH zo!zKu^u)P}sMN&l;DzHy-;d$;nS;lia3MQo~oXuwfe^uYkjE!E&p;lB{cry5H= zCJvFTIt0)J7O^-5vu)qcJ+=G(bKclk_u0lHZlk7kT;xQVOj4NPttY5z_iPczc)P=D zB}2I8AIhe0Y-=2R2A8e=ePh?3Ub~KN=OLU^7Et2aTRWf+!ZA<2S+Et}LR$ukfujK} zrQ#5spTg0?WrSEVr6g!mYZ081NuITk_2gtk7i!RxNSD58q0J;B=D14#7MpMqSimZ( z7O6+Zi@A)lirDW`c&f#UV#=W5^aR=#D|6+zd49xkn4hHiRJLxpyxONbYg247HyiHw z5XqjajRLF}15bijuEL-F(h+k$4Mlj7stgq7Os1!Fhd^wFPC#ga7tmg~G?9KCv^@jG zikWI1Ma3oH%V!QkT`u4;D6Ld&1UrJ}nB2U#pK*{Dsz^RgLKf576gN$mNejWg4rq|2 zTvFyp*8q!B#6M0C1bCsw9|HIjGMFjKB+bUB=^NJ7T4OGePWrn_ z$>m^GE_>49a1vETSjoA$<%XV88e*ynKXTmGgd~ci0T#t%RSp5N=^B)e|FWCC-N7ab zoA6xi6<{-}TS+0UShu9)f{Oq@!UI4f5k+it*N4F!R7_CEw@&aADH!k5pLqD69&B9y z>y5p)?c(c^`Gu6@JWOG!m;;e$q7Y&enwRnc-sM6Q+4U}j&Uyx)ARqk5(+3~B^uWH8 zae*TsucphptRx1BEfK?Z3E>9vxee8=o0h?|C|~eZnb#&_tIpSECf!_hvO!4Iq{S)~ z!@>%oo#-wa6v|_QG=1wm%Fvzp)RDJt11YqejF|y_jqLyMa%}}aunK|oaopxFk4ps+`!Z~ z1?#V#jmm%i^%GCv$!Q^IGrVGnt_}_T4-=k1SL0RozZ~Q4AID)+lK_dFbwcZhYoX zZ+q%BceLpX2B<<4Z+iFHTz5~>`YO#JA%NLV%i&44?yR`%gr>A9>E}XlWsn&+n7$jN z_2jFrF4R)yQu!&Fm{D_J&)HSCqgy+_@#42}3peNR;`%A$#|Bh+{1wBOx3n~2S?%yKfSFrg ze=E2A>RJ0~083Kl{qKG7!CiZw+V+3m)p^^0FmsujPP0o6lS6IP)Q0-Cr_!Ov0HD(b!b4Z zoQ)wjh~IHVZwVs}?b02C1@|->1hooj`vtGE(nV1vR6RLjA87qT zo-K1N*sK`=DP+0&73%JeRFW2|0u8#$l30^-{cDbvh)()@gGnVYy<`eL$t5G#;P8|{ zV(6~Nam}cgrXrm-Vlznf!B?TFgai2L9D~=|`qxivIfv2Dsqt#Qu7ja`>+!$6w{yyf0XQS}e;i+_r?R4csk6q%K?ciW?NY6oeb4w{zH*99>e z-PSKO_FnxNdh(ke{P}nOrHE|39+|n!txNit5zaDJEht_F420$;#7Z6{rDk zh-2+p8k!BT_+)wTg1ea`5n%026?8be9!7AApnsmM45quBA1Yiv^jf^w?!}Mn9o*_J zqv5Y4TA+mS(2jR=llIs;e!8A$9K0H6`}QO|uh1vD2yqOL{lRx1efqz=_kBx$+c*2m zZH^{<3`*C}1fe?5%-U?=K&|COr5boN3!2jUc#HId1V=G2OCk8yZG=?vt|TZza%RLY z<`%S&NtOgF$PSJYd{(r}5=Uh<&_dnak@RgHSV|@I*+jHp^N9eRN`QA2mFHUXJl7I1 zc$tI@`9#-BE5pK_*ac(V(L_wZIk9%JU7z|qS*%qf&VZ6w)epYKttS$#GjlABzu3Mif)hZAHVk+*gs zA)F!tIe0XRjki{Qv+>=3d}!OQ#~ODu?n=klU8x7|I;tXhTpn{SIM{Oyl$%2jj-8+w zKliSH<3HRiQ|4vL7)?A{`RVeN?>{cy^7o&dpTH_ys)Qj~OJ(LyL!j+b}Emt0tkOnKS*dh7YjEj|f zDOSa1SSrS%iXJ8>x>aW+0p9~JH(pGXJ&SDBXOUX{yK>XCD8sdKqIu!YQa-aCi{ zX2^1Dk>Sg|b*9laT_YU5I!z!^dxb zC8Xzm@y);ZC5rSoigEiwXo^I-c>H3RLe~T8QW6iV+h0qEhH(aWkcBTW$sjlAie|6W zs`YcY2T-0yi_ew0v`Uns1F23af8c~nNqjRx5M3PC;8W451R^awSq-`fYKfBcn|7T| zggWSNnj%_q(DaHbO{yc~GonFmb4|AQdQz(5HLZ#-yE$0*@qXV8ZKi#?evhnKye-^$ zZz|byRfU2T2x7ZC$$~g7pv=hTz^zXWX;|}?mCLZ6q;cN`Hf`xE*t7*%59wBgsH8%A zn<^GOf=S&M^`@Q= zv`_pZbQJbc_?nF>yf_@?O3u07tk-5FdJ^#uyF&%7=6;O;b5*= z`OJU7Pw|BTUGnRV4Q={@lOr`p^tLU(MYGX>8GB!3xU2dp^M0Ld#?7ijw4f>!k7!(- z9N>`!q}Y?aXStqh2&o=+kpBO$%Y8u$6f>3bG@|RXsZs5CY8W$|FSQ3H!IpAOQGN=Q zOSgxyPJ~)VBzrC+k*q%clnrXD7^4P3?^rb3@tx~%T-|NjLJe%%8qgGj3Ti?W(41bt zYh+YE@UCBZ7_IZ*zQ+51g;%C>u#L=kWNHr_Z}c#Q*tFF&hm=ph7x%OV=J&1~f* zF)N`(4t@uJ(YR};DlHa{=mA8lCYLL~bXKB8gpf6xrI6+7w}%A%geNDulLkGBG)z^q zhQL06*o?M;yg34y&1Ng7?PP^bs3f%J9L^FLrBhRJp)(_cUjPbeU!XOrXUlq8QVYAW zX?szW(sgn5f|6Lc$pckvu&5^w{neZ9Z(Q|o3DC%^2$W>}A-ZFAMY)e}( zUR?Whm5=Yq!;($27jCD3iAZzzXm#R5oi?Y2Rro3B)9j4h!eV&SmP17l4@e6za~iY? z|C>e7o;i$aE@BD4ss$hZMnY{-vEoEE-zw?C!7_`#(T@iX-R7xyS-#8>xKf!lm^w8b zL&C6*u=~q_!jC?uZEcFUX2(zL)YS5F| zH2u`2_K9dOESF7hT1>Et%5$xGdMyFzBRskCKI@5tMKhm{H1-}eMlU(rRf!#_3^q>~ zw6{?k?C{W7^R=MdvIY)I?0$IHf$x9p@ppgf(#F1L&R+c%dJd^kH_k6$i5C!}>TMr^ zcj+o4nkn}=Lac7%7IPl4?W^)R7_a#wXE+`((RRP88`UlUs8Mwrsi$zl9=?m%z+9en zVrlJXK+5t?x_`%HWk-wgscpK(TW^pOc5~AW zM9-B`AQA;ao*{FNus%bHdDl(v+W3YUW{Jj3f-#P5os-k$lK=5c1iL^KJb`cZBg2Ij zAWQnmw?6s)#D}9UHsfiyhhwoun4U)IbgW&wv`%ylJba!phFKJoeP} zoJ|ydv>dB3jqM@GCgfe?AA{6OXafZg<*Bl@X^<|%v)i=w6=iulJo2KuYhXG^$)c@c zz(SW&bUqO=$NY9|(;&sPEPtLV6?z2S$fczuNog)Um9Maf1P*1nwGjAnXNyUpZMr6n z?a_7OTDSsdO{~7Q|Lr)&WI!z{a<#L05~>=^A$bVGu*Q00({?I9aD#0XBqpg@x)V%1 zK88(Ot)}TV9MCy*SL3aJedsfL9&YmuA{m1;uw=vqWH)UoSxhw5#!)0eNIP_>H78Y9 z*nkBoR+Hw;Gxr}zcYF5YqURO#1^B+A1$3k_G*{yqnkimx(N94h4yQ+$5^L-!Eh&T+ zaCId&S`>oRss^@KP@YhWj|&qZWo2x@&xtvI4unieuo)qUE>2c-DuGA~Pga92f?A>^ zeJKG%WD|iESZJ#05-|?V&t_DMS5#?I9T}eyWwM)V>GobvI=~_Xs^XTMdxTEf#%$ww zJvD@3#Q_vBs0gdTAWdpuS*H=4Nw?*E>~>}7#7|a}=|I=tQCc_IukPbb+iAz%^%>(Q z>?{F(2`kut)7CMLDi|C`3XLysR^&%-OAWvYBBU9veE`$b%^I)UEeipsI1 zu0gZJrtQpJq`rCW2gcKJV60BT>_zo^U?uVGjlH(n?!~Ust`89L2#%kh_JD>ND~#hq z$mr`h^CouH**_aEo^;m!3dZzBPzR-%(f$P6)m#PusTUV0c&7H@x$44T%N#v~3#MdZ zM(BQoEN54O?e4S}-ARM)vLv>eb6?b(wmp@|3xcSY=?qyVrTNLtHRKBIB85aR1j;Xu>LQ+TJK#u8_BP0!_iw`x}39N)YMloeyoiFbGt8$`&j} z)POGf?uUj)RZu^1N0dw~Q;j!m<3!hA`H3VNK<|I(Y`=DFj#mV zL0VA|>v)o0J~zev%9e-E4ud#GCxh=Wk2{a%L9qremJ*ObzWt1$r%Y;3WyB{2rz9xj zIfqh|pDgFnZBAi?x4R>fg$px7A#YV+f`=K`2-4Pz;Dr>d%&(hFM(b1>q6?#;sMnLW zNJP72B8;lH)cj`VnM@Gg5YdcvR{ic%w z!dKO9JT1?X+W$a_aN0glA@w6QPN20|n5h@wva_JX&6c?qtdKQJSjckqE7aW`sm`3} zrtxGo=q^iQP0n5Qy3k2~(S=a!O<0x7X4IOm=Mpg8D6tCBEM*nVIoc)ciI(h|EPga= zy@J{ENn45RCXVCAU0s?bJzXE$N`3f>sqyzu9(vdIcVGEvo!NRs(vdV#V@(F|M59m3d7{(cM^@J%_G7M4iP z`GGduWf|d4hY?UmP=1lTwB@qxlcXwo0smoX;)*{-bdW^$S1c5iVWHobEVB^ znI=Pxu$c>}4{mY>kJ$jFM+~d<$|Q{b{$u;F^|QC};9qRJ(!fX}K-g_-*3 zc3TOtac`3PRNBpWg-l`V%bm2vGB)FER;_DUtgp+%Y1P8T$^n#p`Zp6H(}MNIoFb%R zgxOQI^(euLegzunwleZaNk6sFp7mE=P$~fk?U6m@$5XF)nk8WP^j$k}Se$0nLSfBQQJs< zs7+fhvzy0B#@-~iAGZEB3K&?i!j`CQY$J)%fAqFL+K7f>@C%h=SO)FK_~x37E~ibW zTbdZMCgLamq48(uBSD4HrVQ$+D+fp7LoNLNr5bjlA=Z1b!-^7$4A#qlx1-jp&wBM) zWjz{UzZP0a#V~V6;Fo!9+M?OxKCIZ#{KQ4SKX~&3=_!N4hgOqS%qwPj(>78l0S!sK z3x%Y61m#JEOKOwTWsvvfRNHixj#6^nP}Z(2OVJ}Qx>aW+2Pa$QQP^NC1l=k+&! zs81!ZfIL+y^a#4BTLxvHxj9dYl(-I#NZ{DOkw{*(3$+@FuL9J!1tm0&(@02cA`NwP zojA)?w?wNHVB;B@!~;4RIA#1%mCem?Lz-gW33?iaPY(p+y`+or(puzLxMa}Y>RR={ z#rrS;PSomg1x>1$Ax!b<*V;VMJmaCp3~N@`?C_?oo!K+03+Q18!ltduTWL zP9=D~Q_+r0caoCDi(*^?4zh`K(%+=ync`ZN%O=&4@fp#;4FYV>7Tj`VnioNKa4H^O z6`ycFmrYwKR4=-%rw**fpX~D4=7^x%p~dBCP@sYn@OF~ybP5)%HN8x+{C#hL(amGe zq!fmH()Q9SECfwLqKIw~1=OeUZBG7b`;%e_DCx zU4MWEHc+qLIX+dHL0bikRsM`NzvsT)x|f|*O+)cde&VblJ*=My(R%yn5}Rg!ZIO1~ zd7xr&{b~TQQXi=+qLrmBc%=5xY0Fe9KP3}0LiZzbvvy?)QghK#ojK8+G-x)&F2bu4 zm%83&a*3?cf0b#mpjA{Nea-pdOF#+hlzp`f7Zl!JxskdS9@M{j)}z-)Be9|SRj)20nOU}__g z-ttGMh1j6!kAFIuW%J-o+czW&G=I{2;>uiM52ATPmOlEQew${GB|2eC^okh2TYJ-! zA3Hysqj+-P*}O+RVf!_w!rJpiQvzae&aN@|IIuR>V;;4mtF4+ZDHq{J5$8`)ehQUK zx2K*{#KPfLhCk0`Budnul$Z#UNQ>&@Pn0caN`A@U>!Q$3nyr9+LCP*tIypiH5p>_= zACa2uMA(84RiHmq+DHoO;-sxYii_$!OB8)HG4rQyYjj9r?0aku8}XUXPvTXa@4qyCbPBF z*qLMx>Bh}rFueUMr&7Nbp+(NW=YE0=pR}E4&lg|z z9;%&6ebpW7_!ZkhfS)bsyD2oa6w$@ih|@Kg4zf9E0(=SfN=F?n(#P+7gfJSLc%hR3 zX;Gb`e-wEABM>TG^p8OD3s_|Po=s|0^`tn=MnGD5u7_jBpw^P6P@L z8yUX`8^!)22-6QH&f{;4i7xvnsUjY{$?_^MSGc83@QYgTqpNUf8VVH$i9p3dYxrZg z8!TcU%7DOxf#TfY&|V!5U|MT-a5o&4rr1|3%u%g9kB$;hq^zRZ%{9&T)ho<6LhLiN z*)v64x_`%HWk*X$RatK~UGwbPt4J2Epq&CU7;P>?N}MCT2_*KU?Qp*`Z03lVAf@rO zVFHqJXjLkB#FGhK``uT3;oQh*h33FakXrGqJ+kJ^^Z>U*P|!bac+(d7phs|?{`#S)ZwjX;q8de);F}JOf7~5d7czPKRrMg7 zNfc+#!qLBJ3kzLJbA#fy-hxf%ra`W4+Dds@N7-j;_(nofrfI07>ukz%u^1b$7O!BZ zW*pWwz=iJ`fl@51sz3(9a}&%(BYNEfSg_*jk%gN{x`N$nA2YGtv?V?4jiED_!44BP zXU_u#Hf>d+u}}o{kfK4uAHoL^Z)E1WW<9ZK8!noN5nW*};U)6wlH%2HK54sHX8OvE z#GN7MhF!m|(TV)EFl6aR`ah8}oD>{|H z<>erwL5h^PPL5<&N&r;ZL|pl-*55ScwG>y=E2=c9j*Jg>V?kb{s*wV4%U6V-*-c8w@;ThL3)R}kb17FAfSMOt+E1YINmH9mj*xmGiS^BWizm|!C$@% zn=zW+vHt4#RKjoC{+#{FNC)4u+=Ex#I}dCOOsI;uVj3M-!bpQjeWEswVbj)x3uY|3eIaFyVE_D^wik{Dq<`T@`QW3%y#j8#h zG_sA8wzCw>@p`QR@*P+7v~r8=1PbJsv1!5udmT-;6FpIoP zv=XYG9Ir&ml`V5ELWE4J6G$P;)vr)@ccePCP!(vQ+o9#dgn{7$JzV+(y`13?)T%>g<%T z_|DpgS9^4R^gveHD6ps%@6d9NCOO_}V+OSWf<`e40aQOPFve=Wmvnt!yR?+dGB@(y zECNQffly(!7x?g1hBZmb(-D1<>5g*?nYAR9!2=^;+N6Dr4YqxR+N}qx*{})%bMHtX zZ<5327DiybEddR`;d4E6%EtbO#}}6McYH9P1tYF4KNOh+CFeq>1?#IOMM%YXX`Zf) zM+q(~x~X?o1Jg#rYLuj(8c5IjD=#XQ0EG5PQN@SXJcT77T}zWrsyRit;A{|)YY3Po zCTz6~$#IG;Xt|6ZcE{vt!WF-PzYw&qa$M2Ge5#NIsj8up)px|rh0DogV3`wHLxLb@ z7s-5d8U!w_%H8TzBKjyKGfXMY?A+yeA+`|WJR&@^A(^YyWd>f2KMOdnv<63g2`I6; z?B=O%R&#L9*7Yt_R#TEcI0LctmQx-R}{E<_x( zeRbJ{*l&&T1KRdOsqS*M!G~9du8qeRF}y9|9lo-&@mS;fxNicYF%m~hb0*Z9w9#|q z$^aR*#nN4}k5ysn6|Qun9O*I?YqiBU|+RP?0Ia zp=vZ)ON`yLB@D)6)42SCPugM&m7}|Y!EBdP!mX`HM`5eCuO}|3h0WPWvvO6f^k@a@ zneiGVAu6)U5;kq&LoWIq4*qU{?hz^i54F;W3XjFWNg4@fPGDwLZ&3%MR4YdAuC#W1}(mf1}V~0wfBf( z))Xv7HW97>hP?j9V(p_DwTh}qbfkPn5)!qQ1fNAIrxL)K<+hCnSdBjcoqF=stz3jH z%P~}o6sjk0=fMXHq;ODHIWCac4<<-YQ($nyT%#^3xT1wGF68v^6_ISP9?Kkjxp+8U z)v)(joVp9?gxI9tEF!uSaGP~@(}zOhJD61uTyw{9IT*}c4F!bXv{llY5%Xs07+VzFp2E-$dLgr?rA}KNDC){G*{2H zX;s?DP7k#2B^RgBvXE$kxmPii#&IJnQsF}b2HMOrOHif@Fc*mVeKWZHo$q{S|AkNo z#W<^avPNENBQwcQ)SbcS2*GKeyy|=!ux+(GfV@+m8bxs+RW24#BPIOn6%tRHtxZkZ zipb5Jz1A|NG@KqlEW`SX9(mCP8Wf4M@oD-qDRn*(*Zr8h{u(vqAeDg7Dyo#`D0FLw zLuX$|Jqc4xrTM`yt=U%j4)4?|xhW=?AbP2NgN7-<#P-afG(W{K)V!x;Yp>xFyOcpDl4vz1ja`UCMwWt<8-z>Bsv+3eq1_nrM3Khat zPC5)|{dN~OI6w+hAAOOkG2(Kwz|Lfe47&hB_tB)XUL9%cy8NOMPjmYp!H*MIbhpRk zI48q^9h(r2Ze6Re5$zu=+9*tA0hnmJUo%CHz7rSV4Ah(!8dw?M+80s}8P>4ZV_!q% zQ8A6$9GL1`NiUflJFmmsEmWiZ8!_<(Xo~jtm)IvIj)cb0o>Aq&&#u^1$4WMyX}W_q zlSNH~COjq;*_{iqD|fB4v*Z>0_LeqF6yE-2+-HH2cJT~$#G+tFcwgnSI>n$AB`e3` zve-c5BWD8!SAdW)a_4Kua74nvYfx0;U2|R(CE)70W2f0e9+juj;*+K!c4&OOH%(yL zr|X+U3r{C+LepQbmNd6KOOog~-Z#IFw^z!aoYdHAxo>VIPzsR?A^%Di#s0G+H4qJb ziPafdST1d3lEu?2Sl1!;7C@Xf0Ud<+G>LlxRltJikfJ?X*DtfGe1S%&#_7IS-9}}! z+K;|{P=;PaR?(yb2n8^0cZl#=L|9ok~WS$z`SDX)d5Qfgn@KO*?MuLMNh9p zt~Q;DKIcLvV^_16$PH#isoD7UqP_7L5h7$giPS=sx}8SuRr>oxnw%{&K_g<1VyCBN znS%UXf>scfov{^=x;>aZ=fb*Qij`D;qYcA*$G-Q{fh7}Pcj|SN^eqG%$7T?tlR)vW zWYH##*0XWt9|HM`Fs`9#eA}FF;=ZNIJAbCEdTA=-sbV!6R}`K!f-N91+BBw(i+x$M zd(SES)_r@h(aw)GedSdVu4FbJxT#D_hUn1;8|U1hEOUZaVQ)fh#5t70!nb+t*nmP; zb?5FFOJ$ftTzuE{h6XWjf8FI1RlFk8vKkFcv`N}*M`17ih{Iu_FOX7Vg9lXY(_hIc zr|ksU-7!s@l}9cr?ZsS~>e9Qas=>mkH^&ci*%<88BbC zb?19^mBN)ze}LObeCh~=ckZq%*YE`c)2`43?CR23ygdDqEo1RGP7%EMo?-iL%miIP zsr0-Teza%vx|8bI6$YvZMo4e?-q}Mz62&L3ukwT#GwfSGu)9p^r*AuJ$PCjlETUdT zX|6*Grk5ThLUY`5^<|R~RzGp5q-n-xuYwKf$!~uC13~msJE}~LVl_;!I`hWq6@t`L zvsR=wZA}sHXIaQqXIeygyDChM3EGS9q(M(2Ni5U59TKT}Y1wQ7ol1ar6_w{YVjd$Y z$z(uD(A9>YAqcjuW13hcUa3nNE_9Qi={17PrVDF!;5{j#of~WH+yta7@mQ3^*j{%K+57_jMjo|P{3d+7lmSV-b7$=b7=2QgsataXPH*L95jL>2) zTytnz(BxeFVbd0=(R6@))hYyO7=JKbb-5tLA8^#?&>|6401CTT*tFH$HSsz5q-wLb zeG;q2F`Y>~B}e(-4|wah6FjaLg;0fQ8nv4Iwu+95b$24$bdJ_{dN z(FGcaS_MLt#G?=dvWXanRT60{i~UV|XhyZkrDr=ro)_Y#ZI4+u8a7w~F+MODrr`lx z;()-lApx)88-$BSHHCn!T5Q^4ox1keCm*{Gdm;u66%%rtl_P}{ICG#K#)UCG05)xJ zee)l_d0cTzz_sZ1yW%3gA!YErBF@igrbME=#7jY0VMhqdRDEc5i;Z=kJ~6~4CX31L#* z(`Xa8-#w8K5}lap&PmebigaQE$o+kKhM+{u??*(u4$LR1?&%~=97%&w@ydlm2$umx z2E-4M#GH)barw9sHA3`a7+!+BW&k0PJo@{uRjc-S^f_nmfjHzbYo_bD)~Z!is~&r= z+I7Sn<_yZHqn7fIWzNlGAS!|^3K&YIFU_s52pu=thW2@6`i&o2Y;$xRWGM1<2rI2X zcroPlD;|b_IQOAh}XnhH##1CY9H4*Sm5yEz4g#uE*Rwn=7@^7*>k*L0c3II zz?u}5M-5Kc1Cmw9Wu!ct&bkT1iBM)7Oal1w%mFsISc+!l)fQ(A0JB(?Tod_PfMx#t z*Ov?=Tp)fHyT&*vU9{??@N zIrXL4TH{$$dwVudRw|vi ze$a2E^)4i5W|W(v<+?4&o3Ir5VdB{zog8^{^%o&Ck-G<Wgp#~F~C?EZRW-iGKzjreEV@jz=40~n$PJo^Mn4s6*@*$Az^ z_ghFPqshy(4om<)(qi5y2iX#S7Jh3sk5{~yQbxyUAziJ1Gcq&dGk2jDI2EDQuvGuz z4KO{2^n@JeuQ6&e@@DyLa0 zt>r_XGiX=*SJ4mF(o$IE^#M3xbeB@A}g=+*AknJ zyv$v|#VvjH(ix=Y-Grom5XDRHe(}9nCIwa&M@v!B>bLIR5o2%WUNFg*N3FW*n|IX4 zk@Dl8nZ~y}3sf1q{Oowm;Lg<(v8yNiFMuirBDjqJ4c4u+%0qMK#*40pJgD#<|E8?r zkh@my$W=jkkMQh=QbT{lP0?j-t9WtL>}tvg=X9b1ZYOn9sn!0)v5=JCvR3C*fKpa{ z%tEV+VTg^k`9o#XxfKVa?dyyzCZ}hM&J2xR6Kw;X6x5{aS`9FWcI-)q&mLp*@b2?|rD_dc?|$L6 zd*>%c?5`bs%Ge?qse6;M$i40FMu%qxvC=%lA2jSfZx`kz93>g6Op`g0v#O5Wo3A~{ z9)A3K%E1Z-;9j+@PADaIt9_XRpwpTeI=@Sea;TtVjJAkpkueT!oF$o&@=nB- z6u9-&EiGB}NCwQ9ei9dz7ME++`8gE&Fa3xwZRbi!J5I*pH*MEI38QU4{UPgSM1!14N}1J&>GOaXJB zEes{7J435v+y($`Fei~*0c3iRB&9bJapD#_ovaHaP_YV_8qL=hK&-P6=ktyC;94JQ z>4WhJ?6!iIqdx+8SQ%}jMLryn@t7)xB*J|y^4lMiwcj}ZH-<-6CmpC>3zan(B6ZJU zhP_jz@i96Kje4VPMyu$!+R8L%>w91`zQVuTUIbZ%R_=VF`>UCVACFDW&KXG zNPIjLW1esrz-;5;FL3AMjBiB3$TWH5dTcox$X0S+3Up6K6D4v>r_uDqk#f$~| zNa{{BX;4Fk;2$^I5?TCXC@?zPe9nM@UkKp1e5NS**;gQZD12z$!waw|9F0u)r5l#t zM7Cq6V(~^6qli}_(fd(EblH!caZEz=9Am2zkOXVWJ<oO!0WgZW5tbaI6#?F%Gt`)ZM`f}u0XNGhrT|EHXavqK z!%m2gJCA@CuqvY{VE2wk`n#|a`P37Z2d5;eDW;7>t~^!~+sjS!ru|Csgfd1sttz|2FYAt;X45SE~gt@tB+(*)5hzBwSIOw;!^1_Rz(hp*4GY5!GC zJX?awfI9=0SB7=oF-tJQ1?L#0&xvo0BnLHOqiuE_9T+Uh##KNQ7H-YAMQtdl3lEz# zWK(Pq!{p%LS^Tljpq- zvX$izJGL8ZO?=DuD1WG~;>-4EaSsi_pi>~qf2Nu1D8-kyOP5$; zqb-=X##Z`P-GgY7)cd&eC~1L$NvA|DO^#zVq?3`(a4yeppR#(DD~H_~TQl1Tdj+vj zveEX!wmcYZ$&JxW18FDG|Dvrr+b0x3ttp*sdSt8-t53Kiu0y4F9wB4!ewmML%*V}w zp>huHwy7D<1Z(uj*y+3hFQkec=6O4Xx4bjNW>!mh#!aRgEME3czq*xctix*oneWG- zEuKN5WspVq($*Q8#H?iSqRh7(xK38T0v0~Xa~K1X8N$lrV+F3~(4umR-&-fsJFr%?!MrrrcKLa08_nn^e_lx7!1$YLsZ1Wjo@MPSqgZ%pLziB% z3#j8_w4IraiNCa+N8`n#YjEq|x~r1x!WJ}vX%t3V$9*8zBVRPjZ+tFYqtqo^pTWb> z)W81R8D!sEFl=G?LAh)AP22x+acUiHIk_ZNJcB`FX&es%FPL1yfLgY6_wJ-ILZjdQ z%#OGL$tbJr6R{PR5bRCTzx&5b-84Ir9 z%)F1oqp1bDtZfxvH#ORps;JB7W9p=CD!J~}I2Mw68*TX|vLNYQQXJ_E4&!d=ylo?K z!s8dL?W&Dov>ndI(z6=wblPvJveS)^VYE=<68_Q_KXS*YbchW&*S&h{UK7!`nhR5i zUHp-|?}&J3S_t^jARhiSg=@hn7%U4Bj4Kv|TeL zsJH}6jp>;chxf$TE5}$<*{&K?&U`7}+unVWIVuuJfVA z)vvtnE05D(q+M*J`25ybbjt$R;Fop)l^70^u-G;4Kj)cylb_>*esK*$97l*JTTT7Q68A<*Vr43oNd3$3ySL5YGU3a3_P>BB1()ERL1}o<2M%mD(w- z6v@iZO^Yc<^qWQTplA*a#L#B)l=vX0n{|N%gIMKxq5N7%=`N&?{Jv9|C~!bbuGc!A!b`x2aC3Qi{4yA%cq~R5QNxKxk(p6`juu_bAdBc9c&P(C!HHL6 z$t>SXTx4?LkB!I(k=u{O5+Sr%F%`~KR)OoZZfm$y*&q(dq{)}ih<@^!SaFH1j*RU>R20W^8S-V7jJk0-Iz031H;#yN#lMb4q|Px6mOmRdSpIKg6oluU;Pn9 zG3#~tCP}nSY}m>wFK7_!<9QGB7GV7W^qVw&?m*Y%xmH6wY5+PvIf;0uHD&cG*J6N` z2EJyAFB-OiLS9SVjElqZOoudBMizH%#m~DhBVeQgCXRm0+}Gz^pVoN7gs%A~xSspC^ZOmbcP?1L*7*pH}2* zKW*wwFD)6R@9fUJiMsWws5Hs%&AOiirC3_U3Vy$pTZchQew76ss2teagw>Y!NDGFU z{)dr!g1DJxO0h7|^E2+Mqc`zR>e7EWXJTH+vefZ>;c#8lO-Jsk%#!0FV+?<3n-~){ zulV#8PaMHb-w~a$h|Wmr?t%$7+7P2{Ozu-3{L2r$_kUh=-UDxV)!vPY7;*UoVGB$i zG^bkHTAd+m%JFD>)y6k=Z*1Ip-^Mw9&kU~(`0ZKqQ#)*8*=WnxBd3eakL;O!NtBFD zK7WTfoyQdZ&)5-1v^BeADxx?3LH3Nsy=K>ubp0hRc%6I)U?5#nT=h2?}-?Ie)7A+c>H0T(FLjF1QHy zdyilhf?8L3Jj?7^&&I61`!f7!NIG-d_T5uS>MR>=*NFb&k01Q(2kw6E>A(JzZ{Pl} z7_a=QNgii&X)v~YjnY}VawutLPETmO>Vd27**JXP299HFqH4lSeah$0PFArcz?Zf( z3wGHRH(z_vGl}f3XN{#J^pjjd6K{g;-g~wW#~9w9z5L|QzVbDf|7ZKl-~DIIAYb9R zfst~^@D2`N+ODl;R<1`jnKWw^)jjk}w_NS5LSn3~^75j++RW)o1hk)8z2fWc-{-YD zzpFb#6H#4@(Ecq^AZ*SaE9g~$1f^I~C_ngp3aRJZI;)A~oRVl0R!()y0!~X3btX*D z9$G_D6Z(6um1Q)j)Vi0jEreFkX<|pYc=NkK8)YtHVd_P^RdUk^WS@8@ZQ#H}5*u2# zls2&b4U^+%THYALtZT@5qpeNe{HiyZLr<+{L(hC8SJA;6uNpd_Q{=VxCzM8 zOdL`ARz{A|KhVj#NP_-++H#DB(X0xcg*cyTG}Cu8B3eC!T3KyDi;N!y1Zx}mpFvGi zrcE+QALPvBnO)SKWdG%L?|UrE}|H-Dk2PKTwV)HxUYjDN;o$Nz%D2iV(-$2o@H1{&wKS%d*1z5PkQ|;qH`WN$M1Hr>1_in;~K*k1qd0`eCfH3wN;nU zt{0sByJz4+M&2WLQn}$OUmCX!Wq=Sjf2bgBkxQ=)h89Et$4xeY1olv10 zIwuSW;KA{QkVNZ}%@5T8Z50VWMxE$UQ*Wy^(f;?-HaSf#RZrCilW!;jwJH%ZatL}w zR+Bo*y-8DzjE9`6cfk1ML>5(qtrtF>#YZs!v*PnD))rrirFn{sq*|=g2+Zk+(X!Da`^BqfBEWv`O9Cs_1hS){0;3X9i=D!B$lMjZMP>lgKav#X*Va2#>?4Rr`>sE zGgV9$&%3w$CS@*5_zbEU_&L_|%4%e;I1u6LRLiRj;A8mG zwu-)5T|jyKrR|cI>u{j30R+1g(f%#l4Fq0=(U#%<^EN(t)qi^3SHJ$Mz0d!ynq1me zJ!gP(CnJ)xIKIF0{a9^d8rvUdvlx4S|6gw0arSm^sA;3Z3_(j({HCoCvZ;A=(x%to zdSnQ6$%S(#WQ*a=>*@p!JkJsR1d;qswNSw6aR^JQ9kbE4Az#|^BH){%f#3Ii@)eZU zutMQCGh?7IboPr+D{?(UU}>K?B|wcBjJToPu=ch(y-TkYd$8A=bw3FP^U_?~<@Z~; zRos^RDhpIaIk2}0t1a)b7`&L8pV%1Vw=5;VP;zN=2bS23?jO5<3_pMgr9C`Nj&;eQ zz2}?5b2Vm^POR~lwv>>W_C{N*Qy4pIl1tV+VLXM=_QpBO*aa|)8ym9^KK_H};^39r z?M{v_L{Wv1@rh?=DhEMykDPz9j;rjRAZ z4Bj{&xM&iu;znTITI5Sy6*9-yBkM@RXl;g!+<=SM*>5a zaZv4FoYQ1Spm({F)y&ouX`qMGdP_q)@gZ$2!=_2=D_E1>{5l&)Z;bfU(lonb|FzRR zGve(vUyrzGsFU zMvJVYQ}NRhI`XmG=(V7F*V40YdFzvszx(muJm+ip#{Pk}tt7$Yy0rBiWu(<({I`J%)1cum%SIS{!_s~V1 zk>t46oK|gQ@!-B|K)R|pIjULw`X4ewNrrK zi^^&{3|poKh(Z-`J<#uBT_C|gRv}Xq0}<={9HFj4`pKVnO5ng8H`S68 zkHbUU0=A8x%flh0L&W%u``>fl#xH*V?C)-D+}r&ENJg(r0*VU?4SnY2I9Gh;U%cty zvu^m%=f2QB%zap>d;ve8YjEs?=K`4skAjC|TtCo`g6cTx!@dQqN~rUYUwp}xms=@> zpo_Y5NC2ZvfvlF$Q7%V9hUO3S3=@cTN2&Bmbf*Q?TGWn!>#+V}urU>$Y(0{_U1G48 zB7fuQ4{qH0vY&lmW9wy`M;{IrMoeRwAdSSELC~G^U!QU6%jVy zuf}2CT4Gz`%khOG4OAt-0>`!CDV5PARDwZSTZyzWHj?10g`jGNCKh<@tX&&!ZwcBE z`UidarVXLJ5VXAHY?7ZlMWI!LO;`ctSosdE&h3sZgN4UR#e!nX&=L~yL9i~FOw~n= z{gFc|?=C_;7X=sX)w5jZ3tiOq6x;!hVX=pSAp73SAvJWww27|*2#Zi7xfgX7Nm(2@ z-c{qX0}CNnZBTPT@9S`5HMtDmY+Su!kaI>hO&qracB*(YhCoOAB)%3F{J0t0twDYG zJET`>!N?nN-uGfjmja{}W9J`8SYDI)p{;Gu-Yk81=gBRG9nwlI46wLdG<)byZdgRP zReYy+=@n-e0vgBwDX``?lPdL=fO89ho0L1vKvrlC{<;d$VX#SlQ7sGnzyU%3B02cjP`N1r@^N~8a(Ajp{=Dhppj-Zs9rNdwYjp6;#0kl0oQ52AhQ^RVI6pZ zO52>17^L&Nx^pkm6|KoQ0M!g1DRAqW-_DxT`bePIgS}9`_*|#D;ZBlN&{6;#5#KLroYJ#KRx*eMF$i+u&5nVwIdYDYl*Ce3Aac`TB8_B-mFPwPdj~PnN`euC<$3B>!)E(!LtC;9Y%mt2ad+p4H zm24QbsZ8Cj&FYqM`eOItvrZiM8lS$)FH}t_p=|qlcO`i&&SuWlwSVl zLn+y{oI?XhzKA@jPr&dU%X7HF#x@sDh-|A_or!P|OB*-BkT%SrvtKx+5L}MY)ti_s z8MO1AM8Z}a5!;zyG+N5*%^LHhr?$#O(Mqv2iWPjGz6FZp&kJc$_Nb-j^_X>i+qAdP zfTnP0`n?gI7gQ%2q52rU8(0L*&0E04F>z}&Afg?QFWj+3v|FA1oUmoTQjZK52GXX}^i^8h4ZC;+`ak9AtRYG-?=&ZFY$vT%m%K?## z^!+vxQoe`|as2PH{B{b0ScN`J5kFeG$j!l{XM|>LjLk7$?8L#yp;Z|Ccfkl4j!6+d zFu=uSc_G(mz%vUIpw(1G)5b=kqG^ItG)>i5A5S~hYIcDHts?ud<7B6K!ROWxu-*&R zY%%MsW{U&kZ^BY0k4?{zIl79oY9@wV26Qj?@S4|4>r-SwLdF83`1)L2IL@c9&C5^X zK*ufT80UI?W79EQU~-8qPyvmDvXWbJjbbW??Kr?{N%+c-rdZnec8pU9GaBE{`D7!n zFR62`qu|YvtEjQ$TP)@AiIK9*F2LbWQaBP`wL1xi;p8L7-A8B(47^;VT%GiU4v_WH zwC7DT!YizhJlV-~XZ?5)N(Uo0E1R1Y+#+X!Ns~pOiPGW)tp&BKB}|Az`g3>z<>)ya z13)Gt!`xR#c^lDvq4wCFlqt#w*!L2jmel3bg`By zF^@hHa8@CN@@E2OS0O5ert}gd{jGcctmpN}(EKx*xQV})Jbnq~ z4q3;a_8ordi>~_GIS<^2;~2b7;vu*V5-hV99p2UW1icVO+jEDOk@w4Ae#(i{>FAl2 zukUgxpRxp8VQ!juyq`Gt$7 z4Ed`t93O8Ozx^rr_?V4f?qfh@=1u%DXeX%N`m}y-Jrd;jJm zKj+yq(1&#{cb5d({XJRbiNRPK{9MxtPSUzy0j^IZ^7~{bMKp)8~HXz~f*3t>^xZ&LA7@qEMz0ft5jAKxLkmCzLSXGflJVKCK!#D@_Mu0q)&=g zilvl4N9f@Iy$catVHB%)c_Bs<*xQ8FmUlc@&;r=~!3^3$!kxonv^72nZCkf^yw$7W z4lNH`^oF+hjG@!8>B}ybHoOyegESZ@49n4Rya1t{$i^P z45k%q!UZy>0>6ap!FPP;o_juY-&Gr*e9JdJgd1fxQQ=lOOE0<{V~ED@-VO3Birf;! zyAjt{?RXtVl=VzSCz1m=Ly=4z{Qj@J;{10mJg_nRN8i2w6sq$KlB*G;Ct92R5bOE> zl_G;Qh750%*&=M9r_K*81dqd`rv+3E`c0Z8Dr$2ary*4)qtUjJ6_WfSf&BJzZ9bnW zVUZ_{bM6NFKp1Tu`6|_-_!+_g%b1B)M5YyTo@Z^rW8FbwZHbITv7T6;Kgb=5)_s}4 z_2O@<4Z;t3j^)ZKcx?=r#WTH;fPv6h^|RDJWK}b|3F#ICP7oQVKLj(kF^n@hR<8)I zBg>m&zKt${&wnwvu@5lfmUMC<0u`iX7`XN#U(wq8SLjMOy;-;9?v$VeL$t4A1;4cX zDocw4Gtx>Sq@r-*aVXgWNvrulVJ*G|0A#ts7>*`3m9Hf^3`36<-yP6{2a#NXKIgo0 zy46+pz@8WU+&ll<7yrNCfAE2q^7Y8P!U;`qY-?Q{@@bCT`(s))r~P)c|MK4%y`~ox zdRVa21q&h!RolS8W$m&2c#3I5$5c8`EDZiu{18M0U^gGa!mfGAXZk@&yXG}2uco1C zVCj&=4Px;rLIV>4 ztNuWbi}Y(3(42|5JXf=9^~}s#I^9G9giD58EuBKr=su`$bnljXFHnJI){_{QBJ<*j z;p3)p47mPV5B$|n|JlF&;@^JyJ9t#ZK}Wn>I;TSl@IQapJ<*Nh-I4_rC96wjhckBW zG&0wozwO`=|3a#h3U9?=oE@8)Kv~8bN3m%@ypb0|KA4`}BvrZY&ZY|(&iD-@a^G$* z7S|&m?z$dXo^lNt7QTU+#R#q)_?si2G_c+pW{xZHxC^=N{4CIEv~|cShP8m=z>qk0_qN*8O#X{&}T_Axe`fYBDk z8^_``=)5HdBN(;_z+lt!yum}TL+hmN*CV@cZMx!y-;?1#WO0rnLrqI`lXTn2CorJ(M63nJ`7dwiK|IObxrIn z*C!6gt)5b}9v)`D(cLHPf=XJ+J%4<`UOD!?)2U|v_V6w5s9YWMm$v(&affBj+%Y=m zqUdRMj&W^eA)$j)G&RqpcmJ-Pj%okFYlfq&;qLqLpT6gPzxSn|I{aHVosB&*n_q8b z8if?Q>R_~;maaZO9$lx=sf+GNVGsJHe|^bse`JgNj%7R5A}@F!+w;|3xV`*b7;P)H zRf98(`_3N2$3w}J5ASmCmqQ{jOg2a9h1J`tv`PoHZKPzQ_iePDQNGpS0hysPHBS$G z9KI=xr_ z<}7;$`moOBR@MQnH_JSFFc*|efLQ8Mkb9h`%A;iw%7X$Det&67)jYlT7L|5GZa^vt@(EB26podn- z-IJM_Wa?c9=4*b&Ehs)VV6t&!>zWZnOKF*5P@$zGw_jEx>>XjWrR4@6L%!_#bj2>? z7pZIOvtVkj+f}pUaWqx0V&WNK&dT%QW7N-=HbeL#j#rw?@nknMatK?+%r=k&SoO;khDLPPWm_qlPuXaT_sxg+X5*jz z#-UF?@TI@{q%Lq+Z*w>WrBYpZgeM%F(>U~7L+R*CFMGlXpSk+3ZKveOc>q*X>C?Xc z-Ys(m=OYfCZHXU4X>5t6ufewdfW%_Yb)2dZF1E;Kd^EVY9+}y77;W(&EZKN)ojUXD z)FA%PFc(ugbVP!Yb>g$r*)MtWpn%IWyLwZl)y@xS+MT?}d(Z@<(NbP-*3y+sZ71(G&}gv1)owRe_lw7GT&aeL{aX?y)rGZ5}kD@N?g7P$CDzyv}Hv(e9IQ@k2(Cs zCLuE#tU?AU4A=Q@=&=(Wt2TKg;*`^N8p@XL|JwI|Yvap*e9i~X`q$TVy#SIy$lIfN zRexp#n9SzyA6fe6H@)IZ$;WQ}+5NZSdgS}swz5oCk+&gxz7E1@uK8phd-%P*`t#1_ z0e1V-|AZ$Og(2^oe31G0nOl22W!pqoQ4D)G)q1OpHgIj zz%vAnQ9PAORl{nkqH&cxD4Hg?&Qy){@p`lFCqb*oKI}NzX1}VGe=YLNU)QUhElD2;&eKaX3d5zbjjh~nFZ@}Fn0OG0l+0N#c%*GkJ(#GEPIqL zAGzueKKt1(pZf6!|LRNs#HSM(t`gTfTWLwPDmPVS!^=mWec+m_Z+QJp|MQzK`siz} z_oKFxO4v&YH^DWlX_PD@;8wg6yyU4(!~oW+ij9bTJ`ry7{~>oPM9{JA)2(JV{9=u1 z#4A*Gks($)3{|Hn6j>iqbqvV^ea~$m%JIw}NecvP6O;c*#D<_dIIzaBEcB+7_ z89%=hpT~=6zwIcO&8<-7Y4HjR=kQc2zqCV*b)L`M)lv&(d$(S+j;_9D~4NdSFR=gMB8_jWu@E;u$@L z*>~*|_y6`O)3ls4zWsW&> z2HoV1wpf-NtVBElPsiyhU>AUkWB=iTY{X%-MXigec=dDMZh(y|ObK}SWTP!4o#J#f zl`yH+@U$un%gi84*zq&BIg4sGDavk_9ve%tEN12y(lZ1=A?(2y@cm+aq`+;dKv!?7 z>Kdhw#J3u2b-L1PhR4d0`UE;z7f7ID^CO5bG=i-NRtTWykrD@g7{8huVU! zm3T};buF#peKk!rHMLYLtKADEUDTr2M`g5izCd)8Hmb_e(~E3+*4Da-td(po4c8-| zez~PDp11Ald5YKS4pvcq_;t`}KpfFQ_H6}wWw{=C5ih2ie{EM`w7v1V#Om81#_0o= zO)5XZnN7BYaGGJViBIi;Byd++Wq{|Z^tc*~y0ZJ}kC&x;4oxpLU zZJFj9h+{%-sh+U3VE?9)%*D7>?V4+^y&xtt!$#XQ%@!^?Z#>;^(&p~Hs}|!b^$ZcD z;U*tOLfqg>+mU3X`Qm-2rP(%0-?e`Q%aa4jK!`2#;yz!*$zg%z*!e(z*Wh49bmX7* zBvEYKJ$LUQgM~e@(bYUZxnI~*vsg3c5Vo+lCcD4*lsKy(Rsbn}CU@l9pV{H?Rl?XA z+n>Y~^)>!66{OsG85|r(!ElAN`sxZP$Kg@X0#56oDq=LsYFQSba13)82@>#1jiAov zR#Vx_CwQlcUFG`WrFlhOG$%$|)=>uApmi8+8`xuxUpi?x37@i}Ogy&6GSKYMOyX;X z+Z>yF4o4RH+^lTP5@_}I-GLEP4uCqwmH?J$6@LJ>X02ITde{D#i+DAzJxys9zmsq? zK8BsKY3+ksm=Q1B_<*NI=Jq=(RwBiYd-3(SL=~4kkGv#8EuE)8Uo2)vAm>`0>o|li zvcK2eFU8D(;c~35-qfDb&JSp)h6k&@CK!#D@_Mt*mB%U*MJvV9Fcw-xd=8_n1d8O( z3o#yF+)cG?%X=6E-LaLywiTB*S6fUINyy-OWCtOc zU?)yRVR`*3MioZ^7Sl=`ou2EcPwnF}k2{wz+?TES)X#_0P=f5T)zjGKWw5i5oj>Z> z1-bHdrT+&;wWl7^63}3eJs3FYZ0hM=?PK#qr=hMHwyj-Fj@w?Yqd=(zrqH%x2z;TO z0(fxck6jum@l#k*mE`qkBEH)2R+Mo5FD#Gs36e3VB`^8Wyo4<#&<27q)slx~?15>0 zAPJG zme7ZnCc7>_v^KYcKtK6a7PO@zvezoIRDIegA5}rqRU0*}cBOVj9nEp`K^2!Y$B2(a z-_}E-_c*HCz%`?imF91pF7eihS=GYUvYB_2^6d6Z_$2~l)I8UP@RfQuZd*J~WBgPC zLv*9Kw4TcK$o#?#kc`Ae0(K&^{F3B-qp_8Q0gj_tJxM>lJDp&jnt#)k7ZP zxclg8fncrDX{XcdTCS>MP?3{+ozzZeC_h4kS6FFyWXS-ro#h(VzOs-ws3y#&*du>( z>^;}9@zLtI#xOHa!%je1EaBQ$PczAC&+WJvlQ~*w)1eC7cG=x$Bk07J1 zLxawU&~Qr1Z}Lu1-DY}=-to|;+9Bx}`PzS?^N>hO_0no$fg~*r=%m)EANrF+Td-%j zMljJTJ|MAv4whug2H9j)mY6Ez!DzdK=Y!m6TSt7)iGc^CK?)V}6(&NWq!@L^K;`G1TZJ*pINahF#Uf>BWv;M&Y@f z@v3;OY%IBDkVKp?5SB3Qz-XI2gD-||^5B#n!$FMj?v1rX~jg!;&Dl#a;e zp|+rFB_7jIT}!KYzsu}eN))ww0k?~qA20z`?}@8P1eNm8UanJ9+OX5i!JbLkXp6Tl zVnd~CfQ{>sUx^RaZa;6^+o$mhwozql?EEOHV>8=iUdaNx=z&Tk%iRh43k z$od^L4KHW({oi?Z)m_62?m)0SX*gE5OHd2^rY$Cr%bCK>Pef+d7tS7oQMZnGGm?FY zZv(`K@mCh=IigZ&Z%Vny)6NfQ+MTUVZ|~on)!;xM*16nW5)5XhxyOyRrJCsnL-H@8 zY)N8E_Hnxt#ulUP#ZhMXdSpz_H5hGYccpaKW!HZ!OVW{xJV$4EX2x&Y?l6vjiH}Bx z$+FSb;Q1HVBR66s7eEa530?ZGOZTS^L531kz>-0jVB7AVeYe5J*4bJ7rfsr5M&BaT z;#4rcYv``?vh`W2Uw3xA?wIvp$ih7N95z93e?7lYH@MIK;FlBX`!tTXCs#ycdi1E#IZ_l$H*?6ZJJJ95%bv7;8gv zjmt~v8<^qkFE^&aP>;|BO^-SkWijd=Me_zV$5kA@?w$S8muq{5%OhRA$>jpH^PNO= zZsM@*OfVWP<@IKrE00wsidKrHVXQf{GW!C(3sH4!$)6Wul#abkSZ#Ta#h^L5O2=ny zvO#l%M2nruS3vu7|A6nL#UkmzuWpLXBP!zY?=)R&(n@9}oO3&$Y>+X(CNSuj20;*F5h*SAYP%MqP+=WZIG z4w#UP4c2qUpgsJXx{&pd__^LbB;1ZOIqDV|IO(Wf4rXfeY^NdZRHIQ=QUwzNK_|5Y zr|CMVh-{A7KVW>;sH(inBJ2b+i+4Xf29oEB7|vi2@6rjf?kT{2RRpjVT4d=~{i20E zrVSYVe2d?FZ}=K5^HVOSg<>k~rf-rxh;{tt3+20v@SnkAJtS%xt6$?K^mb0hR<~%_ zCbXa{(4;dUsp8d`f09Ifgt?h;m?va$;J7qMzT!Bf6hkhAQCwg5FjZPjRWx5EPE#~Z zaGhux>*J{s*lrr537ryzRL$(|IZY0}wi{YsGy2J&D`bl@-(i4MMNuY?RnHt%#SOn^ zfGVnLL@)N#{x_bXSC0E)Vz#lqIH7zmA>%{Y<3)$-Z;)ts8x*NtD|Ro>o zp(Ko8@Q+No3w58t&yuZW`!9Lti*14&u4-iX6b3g(ZnQPXaL6tREU`eK(%zJEk>TGN zpc|xTEf*}HXxu;y`AZ9l4R*R%7fCRfndWl&E^h@LL3Zh~y#T@}i)E4680f2$R^)uAOV!I&nL z9PjE)9iT>0y|7keL{39WuNkGQ#MFkJ(8L_-DS;+({s6F=$4%v-oct!Blg&eILDxz= zW+ADt(c-j0e}GmF9KfiPTGR=tZ4KKB2CBAlF~FoP`OT0vDnk7s8cXp?_h~dEeSxbF zu}I;tLX=hwzo$YfXCRruiYr%KVDx}}g})k)Q;eOa3|1B-E>SMj-Z8Hx9-tQqUootd zp|V3J=F<;kj78b_1Mp}{h|^OVnat~s83ZFY2rig?oE3ciAeLi%0O(CYTnj+#m^pK_ z`Ufwx0kRlc15%=W9A$`HPZfI8DZWUZ3)|uudRpmyhEbxyp3`h)T_AyqHJD|ntj*D! zh6?1@Y#_I)))ox4%-J4;0E;wm%Tr1Q*Q!s~hDp_=ZGU9*R_IZ##Q=X2lmmV_;5Mr{ zd;;KJaP>>i#~CAs1iT^U^enPqWDx@3-K^ilIdWpOr32F5~xsoAS&-DAfs%(4A5-PEj;zRzy`Z z1h>fPVqG9X5jUS7%J@27Ao>;+u%Va`ykY7!ngKVp+g;hJiyd;e`P;-dL5RiQAG3g$24gHU6 zW$kIFC5Te7b_qD|6}YMw!0MzX)u#4!Lz8&26L8*B%6vfZWL*ey^&2i(OpK!D`p$B2 zB9~?jjSr1V6c3I_V6YABbOGxo6y!LHcUmRNP2DIXW60qjctQ9=Dhou0bX`2Ril6Vo z7J%Fh_+|%5CUIV=ELvumarERg2m3=pOUT5w+g2DUeEfsj*1;Sv(Ji}%9e@$nHw%K? zN`;{P1UzAwZxyXlYRwhRX=;uZ611!qw;XYEz-m$_Yb5rTKvOsKX-^4t4L*9!LuVmQ zQ*-%ko{&?b)AGc2)y@+iTLFXWY9p4bxNVv*qtA@$ACz~=J@F)LJ#lF9qdAKXmWjrA z(B6QswU&l=2ZeSy(V#$nwgbb>ZFyWE9z=p!YMhtyvmMP*ynAnCp%*U2uVXKP?1fR4 zj1yxJVyUt2tuk;2b40FVj0#Q!Tae9+f_EEy^)Jdiakmj14?c2Qz^bTFVTMhUrcWN| zwq~3zYMq}<8+ATqSxxLHcg@eIA+L?DS1@t(itQ}1@wr2IDYN^8$l|m`6NeN5Qks*e zNhb-pgJSK|IOejiFK=NcEQrdVWAzKZ9CpalYbUKY93IO$Da2PXz0VH(d3b+-`94fq^##yO%3S|uj->v z&Kxue@m}R7{tK`cQcl++fQLl;u~*T#SW9KXsIDe4?t*j6SYDRC5RKKtcVlwe*gq~} zLu!)e0#(fWZc+lP_Lr>!uUOMqe15@48ObMGzpRDJP9gpR7sxk}|%4pMY? zeTph+6yICfT6g#r>G@q-D;95p8LDeD$?U?umDiVR1frAgs!w5iedUd72QBEeSzl=1 z|C3+c1uHJURu6R#ep%LFmop5Fsdex7tsb|cK3+0WW+>fDWv@9K4oqL|P0oPxozyTPY)Ip!yMnfwYs5;A)6>=EEPy+qS zEwj$dVe7D*El!&sb7JT$3HNuHp$AVD<~FCP+F-^jvjfObjL_$fjT1AOGHl4Xg zPqn?ObN>n?-ZS2_-YalhL!py8jD?^}%qG{JUgfr4gSH{|E!=8OOh!W1(5eskLQnz+ z>@=K!)7pFc@`LC`8z9Wd!l#cj7wPE0`>5LlrwkPkxpizthG}-J>e-vOd7~|@jnp}v zoQi}|+}>`I*UPa;G(crC>{Ikf60wM}eQAb+03&YRwxRNx+S}89LZ&d}iATVCPs&BG zt2=Wvr)a7frK`kbDqn#Fp#&|ckEi8J9|($7#LhyTrsnbow3gxkV-r?R^&cLH@G7Se zS}j(H`cNP^WrAXD8Ga2m+5*!nl!NlP58w(ZbokA0&2==W8yFh=wO}8}oTYCyFY`~8 zl5bo2eL@+IA$zz8d(jU+p@N9jlmTAkO!}ugWmLjw%ZM&L98vw!$kB&KC>>KR<>eUP z>N_CBj8zugTug4kdUTw*#GQBoL0^5W-F5AeV-!BBDwUJTltX)TVOgz?w&$ivvqWuM zGiVpJYK&>)kt>na#Ex>E5q)mM9~i8$(H0-gta&VxjV3VKHW6z+eJo4#hqM+EhepH2 zfW~vLhlpBSXqph3UC{=6y;FxMMvDwMSXyf~DN#AQ+JYURKIB%RbG!>Mh;Zx05l_HvEESR=XUSOOgB z3zjDFW~iQ8>&qE7K;4EwegUv1u+f%>DI0B{gt!-^M7iUs z13JD(Cmbq_T#}SH_v>o-kd}?J6hU5G&y3PwSEez$PNQPXWfKr!II+nPzO+TeaC|VN zxEDie<52Ud(G`EF87hZbvPBqNn5$JT!Iw4&ouzsGJl`yw>#4%>?UX>I&V^M4KwcP4 zO7Am_5)Jm8W-IFg2~@1XEJI~&j^;E}AirhpH6Dai~(xq)_Vo6j1s}=qz;Pb z7eUX2R~i9TD5p`Sv>KH)Fc0?$cpAscEraEKC&0*m{Emiag0+lmg;XL(R(!la*77yV zS%B4Y=GSPHk$IIA0Qbm;2DoSh;L+kX|0WxU7oTQ5Rm@LMc08T))b(laTa4>MaK-}1 zxO7pT{}QXOoj}UWRV;%bgAq4RR`E5lkJlRb%1ouQimyz%x|0`p0jFqOcR-0MwPvAC z)}Zbwfn&afpyf*+2(nd@&O)4~=8^`qd}J_!V@IG=eFE~M)i0$-ZIyTQ@@cX(;`_vD zPNLnbO&W(D^Ur3!3=3Q~+FDv{j_#(TE!dX?#^FkIEqajW%$2`-7OkatalO?mL53eC zuoesPxjXqweGjWK*=n=ow>pqJd0}1Vnv6e#I}VTZ7O+|Y?eI;L zW{LW>W}Gf+9WSPhM?QqCCbpMrv0(aSqqzgU%+ir3Fuh_cD@4~N7>l(B7A10ig0#Rz zkO49ul(&Id_A;4)__(95Hn0Y}*&JJ;SU}_JQB8)DlPT9+e_#?jdli z+TjRKqO%@-JdttjLT%ca^a@Wqk>_Wg0!#A6{KkvHr1Woir3~hjp+HUoIB`4H4Nd9q z**uGx0gSkPRz7J(K?rDCjZ!VEoGJ1F)hip4r8 z%Alej?RorkZ&68Cx}rB;jW2D{o-Y0DiPtB7=L)k5gTaAchA1-7Q%&P8KeDj}OI$|l z{G}}=<|CEs!J@Hxmj68H?D;>F>MJ;W#oxmIIhP$9KZ&#KccV-;nQk(3Z**o!w>sa_G z^Y!MiV+Y{GJ?=chTRwSP4cH24!6 zS+$&QnThO1o1JFh#KtrBj31dO>%>YnjV1Hg6W0W5XL z>dt9pLG>f2@^vq5^la#idpw92 z%M&;Nvuj%;irBIBWaaT-)Ne1>WTIxOU5e1pGx%y1MqB)@)r6FT-)E0;Cg@5GNMqS( z3y_RyDbxxd{$`H&OV=SW+Kz$*Mq3zmc^D0=_=4Hj!BB9V*@Un#+J>>v7vE^HIebrRtpCCmA;jsbOSu6dCIy-f&rXbSzVgR4dkIfe$57M zTMb&lP)lWY%)Fk)Q;67-tVk5sLOsStTb7KQm9Iy>_5x^?h2AEHTR7#PwX>3-IKD>d zzMai;nmcR*WcU$-NP2ILq6NO_IJ}XTyuOYZUwZ2FCy1WoD5)|PhF~$A$eVz;7I`z@ zjZ9#$_9t_ER3gSylf>h@Uvclb96~K-^j&oUW8-k0GG?5#fr@}P)tCUfG_wTeDF!ij zPUy|!Mq3&W4chfNZx{w>LJz?Y0!3qagj!$fOs!Q_^U1vO5 z78;rrmcfJsyziQ5ND^tgr!!^=2^Is7Q}h=sJxV{<$b!aHQG7Kc$w=vk-AWg6(#QLR zc!aW1-c%&kCyWpa0vMf@l_aQQu6vaP5m~OjKS6vO^3^4iXmCRqKbD-i5#>v zI|9XYI?Cdu5x6nfnm@pSsiYW8&5zTJmbep!`9oe0Nj*Yfs73}J|1lVG+d4txgS@~n zr_#z=CDP7UG?%kdw2+|vn`aLSSk3HYjYO^zpi2UuSm1{8gP%8VXCW?Uv#F4rvNc$8 zQF5xsQoyt-+txO%#D1ZMyZm$f=^O720S$D8+p--W)XC^Gl8C;>iN9R;Oz3)K!f5OG zx4rm!WJ}4=ot2;vO4-LlDS6J?jo0aU$~>ueU@4>F>w!*sG_ zKD-S-Lu8c@l{xUOqj=R3uSJszFpfxomh81;NTvP<03x%lu%TOpwI_Gg(VgC#okJv;fQ zWQ!riRWZ%GU`LJlOIx~-m;29u>J|K@ZPhd(hG}>v2`sKpKBO~I0pB{scKM8x+%qyd z@9bxBBU(>^E;)but2pYAz<&%*TzPbsP#MSONQn;_P0&hf=UYw98!(`0Lg-&b8|?LF z?Yk3{fpwW?4+VwtgWqrE-XwosNQ<&fO@b()m`9%P@*4jzvRe?lvJ7rt!I!qcPW<)A z6j_)%dB+J2Gr8FUr;Q?2IUM_o)_1*m*ZFUNw(*y?IE^tR*CQKB#;-M{N>1=ngU>Bz zG*9&AmtAMdRNPW}gFX2-VPeiAd}+(~G)HFtjoU{+9X;dE*HYYUVZMFnLAN-UxN7ss zwOSdj5F+~edoLhMS$$}7#S&LNp&43m^#1Q|k0!?P*bnBh#3xo&1~C@OdAj^aY3O$+<>uxS7u0eDk-fOQi;c zBb!_aX%pfvZD(St<0RC3>Sm#G@Q+^hyh`0#X{PGrq8)edy*3K6_mu+~7Vn`R_wlDs znUO4g)}4RN+h1wcF|6UIzv!#GXaN^_0FUd=pne(Fo&c`)Q{I@NH@STQb#ZevRU@>H zc6ygyDfVEmH|u^94CbY|%`X4A(Uy!h2|OKdR#SAr$XW=kpwUF_UZJ#DK90AjSQ@t3yzCD84kIOh}3yoP2n zsl^~hdES1E4@9hk)eFZ~(1>jBar68eV9Xr#;`X)pW3V0_S>-|d2Lwu`UFejB&RNDs zRRIuDG$|j^R)$9$U zb3rikNm_y9T9xRewyG{_|6(>aZ-w6FN+&l93hckl-I+UM#;tz z()fL_LpMygyrmem53FO_@#ABKsX$v}Os*WhP81fcx`#F(i+_GN!z%(|$Vi@w3qdhl zhBTq$asi<`C65yn4GqLGQq7QXk<-PxK!PG}K0lOy+-Td?UbZX#gG7}_Qi^uScr>e2 zh%upozQPM&tbeU4@fZuMfc0KBD@I#)F^?D`D{i4XLO?_b z1QxcmoGO)|q#=TmEDUC5*(boZjPVTNaZI$-yQ5pxC8;C}R3gL#OnC7_me;btVd3!n z>{>)T{aDr#im-N#y$Xk?qlN8(v9W2ugS;CWX}@#txi{Z?^5$1R%@hgV0@MpTOFxCz}@<}F~d6W ze(2MRid!h_(Sg(F1Q`jHU|8gCwnDn`g{ha)igq|5y*4rK`gmHL#t7ik6ax3&LsnvJ zT$|{{7!$xHtwm(PQ_lrT;abe)0vv0RE%5nrhbZKdz$C%4Il4>m87@x|Rl`OS255T> zl-L++clv5s{0U4XOlsR-S&* zKn}IQDs^?_^rJ!5j!{ZVVcPf{#YRr)@c{K*6ewS`u{P=tVqfVa4W!^ctT}KA`f^qK zSH>j1UAo9LcKeUx2&e>=yB>yy^KSV~TcTBWXe;9gj@%GdJzavA2Ajjd1<+dCBEsQL z8&|J1_lf8k=)}o`0Nfi);!m`A^PT*+`YFbriV7-USWyn z!9!mpEyikx^f_S9r0LO>Vd)P8+&Vv*9_~10u_F8R_9J`vMkL+mk;};smV7J0_)F&6 zhsBnl4N9y^cp^%2ziG?4JG3QJI76ECYi7I<3>4YlTA!;8JD3-C=aP;*Nx@lW`H?Gs zk@5vHVrOP{odA5_f_BosN!$Tbtw_vS&g2}Qxa)vAW6!cc{LuU{XIW3(tuKttqS?xb zV=0UjFfJUi@|81RARF4hDq>Wmy`X-@k!-jHvA8Oso*Dcbq{Ee{xqGS^M}||fhpI~T zE1=Bvlxb??$!eWVb$YUrf%Cx3+Q#5WiLb}e{7HPfU;`3@d=E>0er$P&iq9y|Z{~V#7@f#r@x&zrr=AvoaFyCtemU zAeTgdfy1>4k8KpTBUM*Z%DwEfR_8T?tfG(_uGeuaH*+*g>+aCj{j{ZszLs+S?cc%+ z0gN|br&4@#)rrHfM(k}WjEm=hlFuXKV)lMHv|S=P&!)?v6_jmcHxWM2x|}!q zU>xH>DyOj)2G@!9d1+o0#f3Ng-L+<$?0CV)m-KGZ@+>~Vc=&-^WDnf{^jCn{e64lc z6GHErbqaGre*U+vEs)D>sC$e zppnR~QiXVwl0ApcY72?4I4BVAq0+K57qRncT-h0?6A$-FY@6LWa4fX$BZLFo8M_jL z`9Hv7NDS92_f$>;g5=0G+yIdnYGh>yJIJkz1`P3KHK9?TjLlX}BZ|c? zOfG02nB{9>K%AQ}jFQl~R z%VhIH8o4j~ht~qK>I19`-Lx+$quBFn)I-``5JEey5yf`X@_aqs4=jKs*pYy!<*g}%6%9~Y>GBnUvvAe5QA4gNCruvD z0B~$ET!|VWV9zdDB>XSH$NRy8sRfZHa$6Zh7$H~jd+J{HYEO|cRDkIzQ!Z^M))MVf zU$q{=N@kTzjnZ6o#9Hh`n;zQX7W5E|PI~=4eauQ*X}|3eSk_=~Eqln$L{c^!VmG!7 z((c%oSVWATFO3AE3Kpf%N-)5U{gDAy_9vm9ZV$ph4%h3I#*GT-Dglz^b$IJc6)qSc z{Q~n@7-2w1Vt~|0o?l?8tRn&mBPoV}U*7$@N{Z@$L9pwHoTQ@sQbHZ4Z-+!oTyl-A z?K4e@K`nN1WbDS@ChlGBIN@~?Q?epWs;sqXI~HjV2=^J(85I;%h*hs6tqa65NXMUY zX>Shbl~xp!-ImfI5jwr!uTW4AgQ9CJs22zd^-R5wqQjlj9 zCcL&~A6eH#@p8S9C0$1~hH!wp?F!<(C&@XKBO9WZiCzik;klqa7W|njFiT0hin+Qei9{tOKJfa(A(RcT`5U5OV3tZZpp%z$91$-+Smv(`Y_4jXCT$Sn7_+XWWgNeD;qsdnOtoO?5jX0jmS4#)vKMkK3kW!) z&g8MVZH(COJ^3)+hsQC{=WduBCEjeecDjYduVRkR zPOO{6HESC?hewhd4u_7>{_u;0=x8L{6KOw{T-uv$m7zKYx-%~9T_sb`&|G!Y*5ZEA zBQ2;FrlmoDh-tWzZWK09&3JSs1be6=*DE>EGr`p~gMHuZ6|!Dm^V#=)_Rb8int$NB zP3%Fpse8;%{=$!E4=6e+(|zx~@4aNvD_16*VSdOl>!$A0Z_V{~pL_1e#d0bA$k^fd zskus94UMhdn@((Ea`@VppI#^VhRxP@Zfjx6DeT6p?<7oE|K`~npPlZAm}I+BSa0E0 z-onK~nvBmfZ6=oNq@Bcyi;;ZdNb?HyO59Js_*=lJiR#z7%<<_M?p8?0Fu<)l!CvQ4 z6r5Kz^y?iEP;bSza89WrXa++OKhKdcrC-}|Gj-IKVrUDLW0~k$kOO3^WH7d6bD2g4 zDH#Pb6sBxU2lzPvJBqLmpCmgMw8>mebmG`yyh>nlyL8{{8M+@jiduxtmccmwW^#Zs zpc(+iX={=}c)9$@V1iAAfC2OB$xB@t0c#?}jcTbpMq@ONPib#j#cSsq%|@$3rz=7` zR;j8ZtHlGNM_EuUOiP3Q5Yq@HgZ2k9xK59rL8_jj{bWrGWEg|^>6}g=<8fTM!B-7_ zF7M*6i4P0lH)G+(E*Tt8GA1>17}=-ez+MKz855Ew+seZb4!Gg5#o)mnnHF!N+y0*u zV@4ED-*&-SaEI)|Cy!E+viDM^1%ooiUoBWr?6^;@qMqa6m#Ig=oOkr_a>(q*FS8b~ zTAzWL&AWUvuMYES9347f!u-TNO%|uD5qcwOB#fB73HGRISU4VPt^z zH40)opLe|2DqEMphZ9{KZ1$N^p-M4axN)M_)}yE$p7Dww61Y9{Danh?IIxvDd}9fb zIha{QfV=TtpHH!mszW2Y3heM@!@j#jPef|5Q4|>b`MSqg%@6Gcg3(}Ok#eyjWZnU& z5bH8tqf2r>!uV{!YT<}zxahdv1tChN9XCRjqRl`YC+s@=Rf%uMpd+f}fO%!d>Kfly zBe0xc0?f4QiYz*7k26KVs;J%4U-|L{jW(v7Eorx{c`lApD-yfb$lxiqoTJN~V_Z@b zbvg(D_g=v=@G!3Rx#WDqWorU<(il__&bymx7=9?B1DwI%KD;bjz#oyL_nog>vaXh= z@uWr1^F9OIM*XII(gIu4(1^qJI_>R1Qyt3#L6|g+QW-l-7`e1X2F@$DnxGzqZUvT+ z3oO>QRUt3zxUTWh=5)vDRgIS3MCuxD@R)w42Z6=piY`Aw`6^+)3ta)Bl~xP_#i>@M;B6R2~xwIg_%h9jNa`uYv{TpNDNhuWr7 zA*?J~U`lM($t~_nFVm*`XnF?|!)%Tn_#CQ-%DVrK1xW`@s;Q)*e~?u!qa|8v?JM?J zbpT|HM+E+|K=D;kzi9OkFbub#N>VHv@J!(Qm9VEQ%`_fSx?)*`{t2K|A$!K+fz!4L zuXx!Q^-u zaLHJaQqPn&^3c|}UrAT7@z6Pty`&Cp%c&+-=L{uG6Fr80bKZIPXMXfEKf3EUjvf|g z#5Z2TRVrQ)uu+!5nwE9OJMR9|qr_K>8_8F|-RIYc4F1&uFBJR>ukXGC>zjoa6iL#A z3oGFzr{p(1^7j1?=1a7cWIIovIKrDWdvE8}2j{l8Q<{JFM~m03TAJLri540RD~o&D z=}sr#hSgJ-up#{X_Mg5(YJ`&ae)UK(RxVTn)k4qm0P0L+ljmPa@%)Q?@k=ynqPA!M zj;ERVI)lRV2e{Q|dfPR+QLkPgmD4uU=%}()JmvJ)$?s9hE{~tMI6%pntP_sCJ9%nRoqPtsQNuVw@Nonalxm+ za%em2dtlM`rtGC_!PrRRlBtRL%0#~P?Gwl3!H^yNrkESIX8qzrVr^&Z17fkajI#wk z`q%L>iAs@DD8Cpc;}CbHxtO&j{WVv)PrpS!Elc)OFZmX*S_AJhWHcM66U|peVP2&{ zZuJ=MVUA8@6*-`{9AG_6Ba(qO*-?U3ALCQsVm>50Z5APJ{0XW<;dv^%?P!aO4qBJ+ zgJ#iarZUo7rjX?)46Q;X4+{NTwuU-lcam7Q9U!_{-WA4(u$>N@zrbnCdL+yGe%5;k~_ z7BvGJpVDYW9T``g0B*ENwnlGj_}L*$1gc?lJV)rY2xd)e$$bj&|U1FwXL_ z9t2^-^+v}lSMb2FC(gv=1Y1;N>6wS$VG?2t2oeV?u5LPpqc$cTN2j-=rC>62c84oh~Jp(nk-|-HMN3C0blrsqu?|LqY)rp zYH`sgkqeA*s0loZk?9v5ne2rvSb_gQHGnjmlg_mZxOW7usYYCOM=n0Qs3uclC&0&B zgmcw3JPQImMy~g$sU*ozi?-iU*IJVq45JCVL=!l)73*OV(Q#Op%AqY{D*^rltP6d! zXtFkP0v(lz2N)N^U>|FbvCnBYB4a$l8x;Fjku_1j=sF8(g!y7M%$CIcO1O^<8RHS9 zLzYzw&RSA=+A|pHkyuw%PWX8FbS&_fWWv$UZM9)=zcxTXjXJb-bRa5wDsb+Nu|nc4 zf;W?HDy_T1z2nfKYthn6e|;?&M4Qc+F%0y;Qahn*aSSv!X5s7ZP1|Bc29El?B&vW@ z>xyyfS7N(a_N>DX4{#^@(EQOkn&CU2{@lZqZ>{6UG4V1io@oC2yN=B*CtiwOA*O4O zADSy$YPdXy&1dX&*?C=i4bfq=zERI=V_o5|ya8|8`kxLAy{T~{(Lrm?k*S{@_jG4G z^z5n}^^733GHz?B`c<6;m9j!%&>vzNuB032Nu4&3Mc)>Jt^^KxTsxp%fw3ieHhFeB zt_oF6z{~}HF$7y&OYYFtru6#mhmT|P!??e^*uxtiTd*oQ$B-*%yoD z2cJ$&vPe9@9sD|$_bg{dk^Oo#*TYbmwDM}6?twwLip#;LX?;3bTKau?e~-j~AH)8P z;nPS0*o9ys>dd3QC$_0!I|6IBSTxj4WiPmJ#s{d z#~7?Ha?t|^%G(noI0E|HkK)BzJh1ij3Eln4Ll*!p{wX}6aF0yDBui}!XPHcDLCjy# zVR!f578^rIMuCk5%EgKhy#N(rU8d(&7xyEK&jzd(j);bfjy@5DD4BNL2w93Y1M#Sp zI|^fEP$i{r3w{rk62DTTMxInQj%!mnxp830N^Ip!g{ZA4iXFNlF3ZhB4JwNRxC&g>y0cX^%db3unk}d zG`X&*VRYg#$MNOB+r+p)yC1()T0nie|8Nby-0RKNb>T>A$vV>h!$HjT(Vt8hKp06b z*{hc+bNp>;1jcN_-DlFo*zP;%nIkJq@){0~Jur-W4{b?q9y*&W5sPfqy1Qd(1%|9C z%D6%ys093w<>R+JeqhnnwrG>7q}D>*KSMj<=9wMGF)J5E2YjLsFX{mQx?*L!_+Kyn z&kK$mwP+%fx{R3ySFZ^%u5M{P_qNDLU4rnf1c$aL^!<@)EP5MBcSNl~8o0DK8y7Y~T8v7k zP==fjulTg6;tAPTapTP-_R7(zRaS4wk@p0bXMMdS@ zq`PEbDiShOU5q4}1)!bf(xU?r=)rS|90$?{0IfQ^Opi?C5ojO>UKuO0Ch8YmV}Y7g zBT_4COR|0?>WLcP5Ls(x;(4FgXM z5Kwzg`INKm2pOUBy8MVBx1XOpe~yeVwn@h@b(W?~Lcd32*8%Uep;vdeeT|IzD?QNx z&jsUl!n_KHw)j;{C!@0otqt_Pv*WHwmp9h(?%_GRf`^*wxl-o&fBx|~I$};fjYTrS zLlB)mz5c*hL5sh0^LcZJ&cf4H01F%V`opi8!tgFVMoNZ4i?2I*^TWjWHBg$L;Ji3b z$lAp{WDktxV+Qk>jlCIq)vC4Sa1f>uP44qYiBwR0-y*DgC0+Hfp!}lag7b zu8!2df`^V$(v4F3l>i+iAi0Msa_uMTTVR3ieP{wBC`&%`^C$79txShYw@sz4cNdMH zg)L>gg;64qBSVkBB4hKCQ}dgAMd6R0v6Rz^58LoUQ=Mdt%7-AL$PU|g ztyy`f1Tan?p{)n$2(4ic(Wp*!YWB-tTrFVK9G%E?HssSW(hm>9>BRuI&gQ*-6DRoL zdacvzLzk=z@L^#~##434W|zE8K7`1s#z#wXQOQEH;R!M9Q1T&}Pg7dd0_)zS3j|fM zvA&*b3ke;3+nhDpc2zu5cFpyFn3!~WR}OzR#h?%U#+&3G_h;t*1(_^c@%&#zgrn!4 zeVE4&4R@(yZnU!`b!T*6AxE1Xn!D!zU|lssZ`dBB{DxWLu>=h zxGRj$Bik@pU?C;C;}AYp;jTP6NH|E7JEfzlFW?y>dD9l(C?;c_Lma+D-fu&?7Q*tn z1Iy-!XD-k$>cU)fQKLi?Ccha`Pe**5Ho44WaY2NX)Lmiz$dIL zH%%@li*v%*$P)KSbEvJimfgM>r#=3d$F-TP_LNSyC4!-1Aub7dO|EeZPFS+lVB~!! zB6jz=u%0H?(;G@exWVN@sJj$+4Z+&7-#pXM&_=A*krm+^JM0MpS#04z*5AJYt1?DJ z!$rqd4nmYHsvIHBp^X-Xc+|=rg|RZI611fvB-%sOQ})VD+GbT}KYUD}wz$Sc`csPz zVbn*l_k6ulSdGyK{SHhat8t_ome_7-x3zM-uZP=RjUHygqfxRfV2ndRGC%te8 z?3w*2;@~ICuCy+2qjSkx1|cVf!82F_{@q)Pl)>LVyzE*)&P)IUhiiK5+Nied=bjFc z#XkY%HtI8e#&;zqI3=_W)4SuSngz3>Et$Z=vVHGQC(j(ga}yT8g>>2_XlDUVh!q!(xssQ(j+@WpO%BRq52Ir#<;Jq?cBrOcpDVzi) z;7D-$n$w-a0zb2m728YiN&fgqYB7E-A8#NM6)?HHw`)_JU$M1#uCs;B_2t4V!sWJ> z%w)dqd-|o3idLXl)NYJ46tceIDv8ju=oVb7Oo_5Xe;(Ijup00jN@12>h*$X zRyw!yd4u&$-n2cZ0hhgxrVVv%2AdQ6&dkV@$#SlWmt=u2E)Pe~7#DJq%wkvrU<{+1 z^VH%Ysbx0>36HyGhj1MJbPVzqe*)HpI%lDont=8XNL|Yj8Re2T0BD1;%k;=J9)V_c z;FYl=YodP9H5RB@H6pdLwj}FU!oHwv6XOx3Ka@p7YUzp3TsUyrrbkoDr(=L~635Wb zZM9+C6`U6sP}PUFjg)hi?>>0*1#?}cHW)#)arrq14G?(KHe-Lvx4vs;cN0CZREwS{ z@IhhRkb375(UT}ET3DwxZy6KTTF4UP9BFy3LnqIAV_BtY&cvb}<{pEh1M^SNTE3ok z{`0>&JjPq}KmOT2o7>r-eisfSA2_<{ioszk*y z^-Oo2;*f1E>Q~ZLY_va+?H}64miYk_=*0U!KPf-HoY4IIvlk+wYpxnkGO~Enb}dLx zh}|gjd8=qc^e8d5%z|*&sz*;Qu=<74437$H4Sv)1N3+&hWWZ41l(ilVJDMwU>O7Pj zSjVGGIVJz_#F1hnC3Dk!lFIh|ths+PyTXJwZI2|z(N_mHK~-^MI>mMI$<22mX>1B> zvSfwqgRqYC4Ryhl=ElJ)$+@-#$QFvSkEpW^JAzmgI)J#zVqN=E~P&k4uZNz(4Zj(I}|~ zGns0QdD0v*ggtLHgD*|7CmzELlG};%@jD^bkp1N~cjhy9@!w#iW%qbGY~AJa=j|pk z@!Mop>Nqn&e~4e+ybG7Jj%_DpdjnFt^1?1Q+=AR7A0sI&O~FJ$<(_CYs}77wJD$SGHXMTi1ELnJ z3~vBB{H6ydumXzjb;qVUh}hrg_QRr0n{@OfKBA0*ddS#uS?oI=0(EA*kZbTJ1wQzJ z?eVm3DCB1#z{4|F4Io(x z-L}$zT1j^N$Tl6{|Axj%q!@@0&%lPkc*+U+bs)LgJ{{N+VqOhQ#ja}_i~V*$IW4Cn za-a6a+yddW%1@h?tTQ%T0yeQ+UB5%%?c+A;iF*DevUCrJ)Ns8!Levo4{n2EC*YPC% zGh@#jnHHnv&=x-nTfS)v*WKKPL@6}5>$7sr7q0n&Jl~L#JHoR_W$q1g9KXtVX#m^1 z&pr1uA6a8Ly#ZGfHoGpjLGdwXyjF)})^%`UHZjaau><_wSQu~p=D&XUnI$*6E#qjb zfgxR4f${<$Y+jdJYp9YNrNSzQwuo?1@9U0f!nFYyjP?sk>cI&VvcRRi3B7`4{1XV> z8Cy`v_781c^E~eXtHjjDy4$lpr${9k5pjv{=Z2d&FeO2mWJUJtjlLQaCGVaTo(RG{ z7fbAjr&cf`3c3#Nv~J~C0v-edkbFqW5j%T;!f)EPkde*Q!o`oR^oo(^tBHk3no3;pnN5ffP3lY}%ONS=5tMDo=YR!~SOfepwR6 zm)2I8@EguMI(mU)NPrd50HGTS8$?D5J`SU&m^ur{)pN;nODWCmrug0j^otL)Eq*Y2 z<6wf@((YhVgqS3mvLKv-$ewmZ$xtw|weA+P2r+tbvCcx)mcaT0Rp)Fj08V2R38X%% z4mlQEO=UhdniZ=7YHTS}$=HoWEl(qbCf0|E9Y@$Oc{j0SqntgDgbi%9)*@w-M3nrQr=EHW9~Oq| zV$E_tMSwl0gGIUNivv=C9NI`HJV(#nilbKS6}k8^DWKHIr_%6^7{v8ZP)Fq16gRru zO|hkV9zx5A$4r9{Ux(SrQPEj>D)IvClF8Do42qw7_UE6SUeE0Y_PemP0d&$`d4?0O zGrZYti6=iY{TFBd#n}*!M;c}K?ww8h1J=5((tT?K`5=MC9tL*1dKG2JxMFpq9VJGU ztV<5`Zz!&e2SnFcP$?=DvU(=Rb{$YM%6>GZhaf?6dupjPFU82+m;L?>mr?M2Lq=D7 zUY?o2`7P?P}-$Q$XCV2uq&2z z(Ls)d8X!+34uFxdwY>*DK;^S5Qg>`7EF$}OSWQi8MFzv+qn~a7@d}3@z(ZebEvK`O zQM=Ry)n@{>(r86zUjJYgEzgjJoH+Eb?9wR!l}{j_&EW}m`t~s#*B<7 zWJJe5fiF-r0^I)Up6~9Go&4Z244EQNFHe36tU1kJf56%x1c$lBefK9E@>Q`#q5Po% z>`(vsm_gEm$?*e%?+KL+*!}or(*nb1Hgh`lD`y;?7X!DtO_=LNX7r@tdRb_igGh!> zRj@$(Aing1YuVXfmfvV6d;5d)QXT<=!Rs|i{t&+S&-hi!6c0zbH_OX;HPR1FV2pT$ zx!tBNekiL~!%z-EVqTz29z`OZ``t?qcnQ;w;0cM`j29orYA+920E*p=?wLFvUxjkn z>Hv0ZoK4gP>)03GC@Z&r%D$1pe&B~>nKhT}APppzP zsg05nYocE?ki#tqY?X1)AL0>8Y!ot3&AzSA9;(Ro(o1xHXeKA=^1}~5d<4B*-1}|$ zA)F<;HmUn78#*ta>UXs& z6Fy${kv*OHxOA`qZhaKCttuo^6cz|Y_Uola<3?HGu}EQ>-*Sklb=t|^aJZds5_f+x z8^b2_{kPrl6B|UrFFq9{emM& z?!o7g?>J|?5f`?;`Kh^w?RT0ZkOoPO5(b0L@DniK`2$UyJJcQUEjR99@e^gR(#!8j7Y-GdpN;I$;@P4gZ zNp7S`B?xUFw+@${3BNZvTyLB%VxrQ746CH|cjNtU%i_=$He@)ol`Rz$`9oWL)YKi? zPG?&p?+FR8{(?>(Da0ceoU{8(Ihbl;JTXGEOm}VxmvGc`;WP%VgO_uO40RKh_ZBRi zrvO3@ZH@oJy_E+z694Oq~|Tgu7_IMc;&rsYQbqYm6|HJ~R097nayp7AZ5b zEi8pNwB6-KUbRXa>;LuL|8;6+DZ}QW5esy>t{qNnJ~@ zZxE#S4{cq8!0&%3U??2g!a1c=u#U;_WCSu)uyV0Q49GX`@d;v+m{iiQ_X`laK_x44 z12B=M%Q0D-Fc{(h>j)7VYI~(5hVaZ)t^oLDR}0P6M6!hAGNJ9sth;pgX_f6W5^j{q zS8D2q3*7kd>41uxWur988HY_ts02f! z9?4Rk842+~ui*0(Zx>L`1{+2gBnm91SP#XTi@CVXVa)pC8wDW?T`d%5*V7ontuF`c zqsnmGl^$GhU%|)^>HxNs-YEs!@^G?%+&|XF7^s~q?hn|ea%q;!L(Ulb>+)k@0`DaH z7$W!jJ>sw-=B1XVxOIHqvH6j*KCvogDE?C=>(j#kVD&banf%k7RR&r-=*8} z$%}a4nqURSj}KU)h28JEK0LWOA+FXyFWWE-@N)v=%Q7nJxwbLHpFDcluFkMGH{Yg5 zK8!QvHA~&A&+5|5y2pzVSe8L$6;Tm^q_gz_Y%JVF1uNJSLq?W&dK_(-3^NS*!s6@; zAinI37eM%nRirvxXipud=5)-3k0=aqtK0OpYxJbydO1jH7CXt-_&|x9ix&#II^#QEM+1pRbW5u2MrQq|mx>X1#WH-jf8nIc- z&=xPmGg%(P_3%Ydxo|%Yq%h|1`R(t~g4IndZVhk!CWfr3wL%CMsr`+Ak0W4qS12|- zXlzlm@E?4$Py*E+LL56m@l}!b6G)Uxdy|z(+hU+Q;{tD$Og%$$)e&oPzi1$bTTm@b zON0Ip$4={4VxzEuYRZfsVGmU-dFdrOKRlE5&=w~u_RVwBx1E~~th2bz1Mk{GR$4qB z+9E9{r&u86(>2@7XCGZdAK3@fmMMKysD^{Jsj&x+{^Nl~tZ}!#?}WkAz)iuXttpIG zDyE&L`|f>LYUu8zzkO4Sk~P}-)yLnr0J{o8EmoSyOxb`;cJ`2GvEt@Q`tFC`lUvT| zi}$bgx*GZ2GYP{h6gn@TdUv%d6Fy${krm$u=v3r0qe7k3Q9Quy?!b^7#6(b(>{&hZ z>!qoCv+!s4mcY^X;2j`eFFVnd zf%@5lIM9seuA36>XKY?{5;5yko%w#ubQkwYdLxFYwvF#zt-j$i*>*lu;7w5!~yLxuclqcGG-R( z>=Vc4Ty-;lK!pM;wTEKu1UGXy`ih_%%LaN=drCV$kZE_8o!;NS9HmtyhKr7Nx0P4P zP@#HI&kP<4hT%%~*so;Kx1FjzRP_ct-xNANSmo+K^<5f})jE4dSRXeW&_hqdmdW9I zb-IZAp=!G zqL{_2g|`;QsUKETi-H9 zdfFAap)iTx;ifK%3=F>+>;8(6wXMlNVxwnD-9Z45UbXJO>H`>vGaiMi#ZJ>rp3wSUZ*VwPcATF!clT=ew)|rc5 z@`tvCv2^mY@}_MnZfUd3JxZ}i#sa~DlQ(VgoHA}GXWk`pz7q+<_$mgYsb^MRXXH)W zCIf}Qk*$CFqo2M2Yb_uzt`HFoz>qc5n=-`R>G2l6KwcOa#bhbLvyyA=xu5;ao!ICy zv1QXhA{a&5PL?jn$7hP9;Nre_bl$KCUTn1uZp1m*KeR=Yx|ZO~w}@;yToPX3Fggr& zLa~*$1+2LcL69K%Jyd~cKR%5XxZ2a=E2D1nvgKz~PORWlBRz)y{ooFEsS}p8X@g=T zL%bGpgVj->I5({&js)(REg4K0mI8QVsgod{xFC~-bt^7IsqRIEs21+=6xkv}mbH|6 z;hZH#O4v&1z-rvLXhht8;w9DsnYY)d+2Tn6b)qI-OxAI@pr4zypvSob%HJeHxltPB zj0#IaB^VlsWII^0UgYk2WXTm^X_VWnp+-tAZQpWDk4?C zYg&gKuA~&!Urn$C2}tgt0&X8puLb0use>ZRCclUi9o(3rJ1&%kEy1C!6rGzgd|Emx zF$e&-h~2#VHc;kfcWmBhAGUm9b=c#13AOKkni5mZ;7f~i`NXlq9qigq?))U)jkT0K zn*Jj3!6ffqe}FM~yKtAf#T+KE;c! z1?nc91_qaYJTT>|&*-RflA;?8*UJsm^^iEpMRny%rfp^~B<3WheAu?%N zETYtI`LT;sO5N6dOO!5hE{C=Wbtc=yrbl*FGSriK;@DwIdMh}REj1^<{B;>-W@~56 zI9;#(_=K3bMc)CI*s(G$!+*a!MrL88q_V&)(bCDy1B@O>4__*y*RSL<=9AB3m(g;x zMma(pJ3;YPk@gcvluIki$^_K{1Kk-nH`bNLy_M#wBi7=6(LfHjpjw!gYL8KfiM60# ziB)X0Kalm+U=LN~+D|lYfrR~`?aY=X`)#___8YvFZFM}l8es%8v5``OQa_T2GRGIY*~=(3eu)FN(=UDBGG zB75FP#Vc^f=xA*}sy5mp_x5jWw=>k4N8Iv8G5BHL)g`zZD?iR_)4*k22eiAvR zYi@k#vK>b97ruCzOcJG|BE1hUlNRV|J^U;k4z;Y#YmF-Tf*jg5(%cp*LtBn`YPCqQ z_O)qimmj;Hjsw}9IRCsa8nSTT?vK2m$HsAw*}*#}GyA{ad-p|nTAAd~HqA18Vd8f7 zrPX0vepYhs@=cdc#ZTN+@o|<;zpeWxw7R<4x#e?c?IdkI^Vm<$<=EJsda?@}ai<$F zwMO=PV~5*TSAi;-cr~B{wyB%Bpa;JAon^vXhmL+M&(}WrZ*Q10{;B8Cn;|}(TVCC0 zfO54J;jFEHQ?=i(qOi)uaM7a#j+N)YsIr zt@7zukzAQnE>;@lJe}zxirWzx_Vc(mOE|R6tbEnGy_9A+3gycn5#|^KZG+vc71}Py z4QTOkbDW-Ft|~a^_(+0KRKUt~wjjk96?jAgT$>fNWl@5Cc}C}@9kHbge4ev~^AuL_ z;ymsfv=%q67|qylWLe4}4foM3;l1H)L#q%(ZRrOQjvy0+_D6_O)EGEYT1`2LQVS1> zkF-0r8-Y_Y_Qk<7G*=xNE%u^05?f6TSP;vr5^7jziN^M8^&q;eT2E3PU z20mjOj`^CXG_gKR>==|=9?=6>{0rb*(`AP1T?>SbVlNpUD{tD~IX6p7(1tN=!M)~0 z;fu$x!5f$^W;t^!>7cf}jj?KYHg%s(oJqGy4sDxmOgoQFeRt|DTbK%P^*DIh`bEjn#5kg(w(qzZEfc-z6EPpMj*mblj(;qs_Lpl3S1`1QU0WhtHM^ z#>1{eXn*l}gL4zf`WeinMhDqJ>kGH-W)~@w`fPQWFIj1zyu*t^C{AGgM4q{Z3nPnG zk_o|=lf00R27@A0g&jpE50wDeM@XfZ20X+>K)mweGwq=-U<+qnwow)8EwS4hXtpIy zKR0VZk6Q;++(H?pQO?uwEep;b$;h?w=fFMAU}akjxEo`|$g_d~tYf}rHs_AyGxtl> zG@B%^^Th~jA!mQRli@>;AU3rOLeR}pX=?lgg6xNL9H;V%;8)}$HAJgf;V-g`e`~hc zuwA3J=YlB$;SG8Gn99c_kEKoqa_CKsS&Ev1`Ul!dIb1`=ZMRkIfE&fGF{Io&Kv+W4U6MC#i=6Ro#07D)?$}}1 zFNqr(m(bQqvg|o$Dc!8^ZAsawh zgF{;bWY_x6P9I5ro+g=!e|KGKuS~i03v>HKsMLUvfh@!&bX3fry6M+ay3LecX4Ahx zwb2$T)~*cjo?dp}KTof{USR6sGn+Xbt!0l6Oj+tMVXhaM(KUzb<g&W;3#fs@YbK5IPy@df;JT4=Flqr?*H5>vKjjD-($$4pt$3KpK>?E z&VEh0P9|A?X89QdH!@3|`D86Q5Deo(Gf$xOE+B2SUVgY3eGnUoQ?U zP6yhKIPuXGx5?gcxJ^v%^T-)Q&ma8>_ekz05q_mWgg+!TvlE8ss7)@i7{YRBTcr5V z@oSoWe$n7t5|AP9>ZMyB|NBc{bC2Ze;DRfud-qrVB)KxN$G`r`iB`(gy5zBo=kA@E zD^7MF#4N(D?o<4Je7ELz+tlRliG|kVkDe!O_}8C!8m-T$4`9qp7KbM0<_snnWJ7O; zICg^2)<8FwD_2_)&f5J$+t@s3I5Du}NWFUB{mo1X(>bX7xvlc|Y%j{>aJ@QRsGLgu zLJDzEVmp(6JaxzCv587>XuAq4aA=#`9hC9diVDGxR2w`bW$glXs~e0m9CKPjxKFg4 zoy)ievPhJ_g6EMUwAsSPU?+6^FJh zs7#*0<5LSAY#LI!J<(g@m8RGJ9h07n|DDV1q7tAeyU%cf8=RT(BxaAm1QdkR2a!$*sSrx9* z0V){{Ho-WwEyfAQtawnv5f=t)D#PZ3SGvzEqJgq2v6i#VxKf%Hf(S>zc}w=(227}z zl%PRySGq9T#uR$9r(eL?3~G){q1VY#RXahbb`6@xwJD>PjbY$CwZ?)*VuOB0(|Z_D zGRpq7Kp!MXeorj}(MvEc=dmB$_|uV<+N*=YRCbG4aE0CK(@?V4H16USIMQC@1Sk&) zq7KFhBKfO_HKRNIYg)z#x%+Zz9pCoCuIM(HBM>p!bsWzMQ;MNaG#Q5}7JmUO$@O3| z5lF?RlBP?_JeFHQrHYrx_M~5-$e59Y7%K}Zo zT>}i)8x@v>fniwO>y~&Sz{`}Uj{t=)WJ$IJfm%VlD}$xQvS5lF_jd)EEJ{|!Q$5HY zR^ZL4S(13A3D?2QU0LT#_?iX47{Br{`)82Wu|5i(Y(`(wX7pMdc0_Tb4gb`e^U-^!M{xC4*svq`NG`i++y?i=)<0w;W;ktLro3_Bq z=aE;Dz?-&-m>0){HOK+1`^+la33>$2V_-*V7m z&$x}YE${%Az-*q_*WWWoYeZdS4gLg-3;Wg$#f*;1k)L=X?M+q|ZLxvwj9p`uOg%$$ z)e&oPzi1$bTTm@bON0Ip6Kg@g606u~e;~u{f>=a*sLG=KRMQsF&crXw7V@U;^wL3+ zH*GV)KX41{{aAb+xj@VBx^CKKi}N7-rY*)V4s93Fi57>pOHEW-gT?!TKfU0ZYzNOL zzH@$|36u2n?%ZF!HO+QYzVPqh()Db&)Zv!DdQVACfF)u1wZiZ3EXpT z064F*OJBpg1X#LpEuW$ur=C0Y+`4%9&pxn1&7?F?v`_NlYJskrGvVW9A6aqvrr<8s z9Pt46z%ieYD9SGag6P-luKonw4BA3wtb`D~HB(H=o3?3tL*BGC7%JUkGgr!ONQ=Lt zhYv_fYGx;B%0B#M9CJ=`ibLB4+NK1DwsLEz7K%mtaUtp~Y%=}a*I#>Rt(FA@xYK)b z<%54>=Mwv>Kaw|XS7_|Qx%20k@xJU=9;Sn>Ew@jYTAwq^bL}?J4InW*c6EL;Px{Xz zvv%8M7`D$odj4F;IvK9cNQF3dLIVxmNHfrz&f5J$+t@s3HX&bH0$7=@0U5gp3yO;y z1-K8QFu<*sR=Ex3c-Sx`hwJ6jPzy;ax#Svdfar8JvWQ)Eo7CD-ERXlf0N(K&K9)Ho4X4w7Oe4 z9DhGItIX)7RuK{n(`$Ol8zr4&$EB=z7+C-}fXHGsU6YKgrQw8JT$%j-!0Jl5=3^7B z6p~S3r9e!V1Y<0&B5n#TsDLv6#0e~6cm3@Ta>DxiF(k78a(n@9|4e0d}j~N~IiLSL^w4B}&uV0Olf<7gq z>^D6kVhy+l*(0zA`$8wNm$A^nXmx3KY#a?D*)l{Uk*@@|?=?cw&u!r((&X5mu#^I< z>sx8B;d+fz>WCbDO`wtk7vvghfk(}U0d@)5WhW+agJsvHrLD13+(0y7h%2rR+_xZ6 z7yN7=gL1K&I+W(Su(pksSVZ;YamKWRyS_c`6KWBgF>qGK2C`%lLTyle-Mym~rSZc( zhtQj4vpBt#azo*|OQ^tJYoS+LQS^pZ6jX1e2K>qis|%z`J)-L@s1xVP)ieEk%|Hz( z8D;;_PT|2?HZtM)B(mrbfhixgeMDm#H;I;os4GER0)TR>*K{4u2M*OndW7ByAq(Cn z=}PEosd6RsaY4Yh!~iDa1W7u_bIFLLuFf{8tuwpd5Z4*8-(&MKp>W7tzI@*f*=-LL-VcSLZSgMV_TP+#|57^s0AAE4r2qWCMOxt*k&HxD%Ws&q?bz9^g4#e#18$e4dBd|JH<*?CG zL}ip|JLt(O4r;Z1^yw(q{!T(@#!7L%&=k3ql$B)-Pzni+FWAtV8uu1SaTV+psJ-d+ zqK$p)`|d1fr_kvGepRI^mi3FSvmmlnCA3Mor0G|p?zqSP(zSXzWe-&;^$evZyq;l` zWKh6Zc_v1QYL%%iHGGn*+R4SM~K@((-hP{&^pTD+B`1iUB&jh5s*qY z;8#jr9jOy^m8!;qYFSz;O)3!L#`dc%y`0kE0koDOyB{}h0h8WIKlk3BJGyqWv2<$U z$bvx||M(oPx3dpTeec#CCuq#zX(@~xTJ4_t<5TZxVen?>e~hlmLbd#$pcUC zWSq{jy)4V&3f-Ij=zm%Ca*X8~fvy-w!H7S#! z2QQ%(&|YOVSv(uyJ;0}HL!HP#*UxR06Al`{hD7itR)lhzSl%e1l7j)T`sAg;D9<4m ziwQs4K5R)!8T$Oh=vmz0z*CR3l4p3VaMlnDnZaK@%#xq~3&!sY?2H*(&mt7*h5o5a zv;5UDY6Gz`f9!B!dFR2&V>G*Ld{3BbKxt6g2$(t;|7?lRVelO!-;O)mmUmYV`#Wdy z;TsPcTg^6#;;0W?z5!!XNwWb4+z6AR$Fq;rF3r?LM$7v}V=h+wfCY-Jj?}+OJB-rz zE8!?*kCGq(6nm&5*M6dL3*cFPN4qQ6nMV&>xpM3tgI`T=U-)Dgt8N$Bd*KI`2M*vp zb>`2%iBfqa5Tvt>l-e*1;G8pGX~g1)mcQp*Z!6glg_iBpC&n1Y+N&@PELbmy;V)?% zE49L1)i3b$JeL{IumPbHA82}nRI6m4;KkMgMhzM|>DWfr>bwM6^)^;EKbqoPFIYvD z>sr5FtDHTA5i=y=hEEn``pY^uG90b^;t$gdo>nyeK9zx`JATOhm}lDZes1$c>kPq} z%n&vGCokc%Na(^>%W5c=qz+xP!`x8^2BJDOmz#5EnC*TSRv2Ar`%9xctx2vvv!^^1!ELm5bjGQ+a*Z<Y!R2HnZYhu z#K@|EX5?nO^(Oy{WPGixyT#)(I4vf!_3wLx^4} zwD>2m=0XH4T>}{KD~GEK21M6bP$$imqe*?72J!(VqwH@5`XE8_dukbo&RpzTUE1A4 z<|CuoCXq@I(gE(ov&VM#Ug?p;^~P59L{*`Xddd0bx%2b$WB64aO8r;Vuwrf8C6%&g ziwHA=!7X2ZNN8vInYTRi8~9wCTo50W56R$z=Jx))ZR3fBa8y7C$G=CPd+uA;QaX)K zwbEs4erBj(ks_Fy;aQNRFpNV8liDPMIX7>?s2t}BI;4(1?--7FD)C$2E z+>mys)LRaDQfuiS|H(TZ1c!m}iSYS#qas4A{i4{)$d;x3y~$c2-2hN~(FF?H=~lC4 zK_D0%vle;Lwj>;GL0MjrQvD{9u%>G4*J2R&)SyiExOS9$CKCRZXgG(m+Aw;|*T|@D zG;@Hvtp)z3kjn&A?V+tv-iin$kZdzqWdQABi#DG8@OzF+=B^v&D7R1G(AF2ir1KkLB4dmW8^@oXpTMYg=Ywra#qx=xV`DH>`@$(38ep41|C|mi(<*h7 z@$Hr3-JVAzwJGiTsUjYthaGd<3u7PEgx){UYHcM%n+ps-SzY#p2$f6`R_jt*rO~2C zSjm%y!5R*v)e=;y?4dX>pJw`U%xcI2Fqytt4FZSWvYY1 zCOLjeA>Ax8=0v`QT+p-s)Af^y0jG6VNooW%^7j$E-zS>CPrfR)tg7(kTBZ)iT0b2M zr`4l=2DM=A=e8=dr(FXoIyx(javIGxj70JbN8)sy4*MU{kg48m7#!NlL;g}5S0ikR zy)jmK@CcD>fP{E_S#dQH!*;cnvi4sdnjl-l;fk>*U&f&=u3?LRctXs>Hoc2OTil<@ z9y73FLG_R4#RlW(S$9E|vh$40gV`9kd79lf==>T7`>ZhPb*HO47I=wKT~{Q5o$p(*ccxJ?RF)JQUucCH+cRv2jNn$f9ox z0ZZUOYZ5I?B6#vPDbyIZG`VC;SXv?AP>VoA%Z>60{Od#6_@B;~!cxPc=mRK(a--65e`f+0#$duRZaX>9c z!2ZBFFtPZ!tF=W*A9yW&sQt`Kt_6%*ti9>yR^rpCN9phb+~PL?b#j+h)TqhMI--6S zMGcFbx~{ico?}R8cw4Y-zc$dittV*O2qNCjd76i7+IOq@Y zC?$jT2V2}OC2AO?iUs?L<}IMzXw)t33=8kHcQeN3H1<_=I$BPQ5b=^lh~?ABD3Kex z^&r2>?qG@vY&_vj>d+oLB4qrQ7GR^LcWEMN zW1(G#?jz6r@qO==hlf)T!)j2}0e&e6oBhnLfU7XYBCZb}KK$@u$VX-JB2Tg20;D$? zjnIE+E7h$98>t3*Q!g@3@6guN>Jx$i(KQyJvh`r3HJ7O8Q`Q4Y$T}fwK@=0aWGf(? z1kLQB3PfivhJOfH7e)s(nr#xP1R>2lz3~y;#6fI#8Djy4>uuBrK|~bi^js#wGrTE| z{jQ;IyCapdp9HZ1As%Mv$|`A*$DwHkMJc@&2c~$S>KkP6lk4%sLMST0>Q!=^wu{t) zYeH*X!Q+as_gzL}iSY}420vOa&ofPQ(j19p{u!|cfNy2U?1RHA$<+X_?BI&sqWZhw zo=Rq?c7&r_$Rq*b7^qH+Q8^*jeo<^?WXn?JQo~paoYip`Q#OT?1^%+26gVoyTHr<7 zl5DsIWqCzP^_xh-nyRs1i$UB|gEFbLj8e~3Law&};!gna00BL;^_iNm8_Nf{+gjl7 zZMsZA#oMFK|g62iMq*4?PF^w^#DWv^qgo32H1DDWaczTBxu*V>siR;DfQ@mta0Ny0PF4TQm-0>)~ zCMw-RM^fP#tny_ge?Z0EEo+%_8qGG0RI=*(ebnMF4@p(>xBrzq$>l)jxbk`p$nO391I=Fa+hqJOHqiwONpbRtF@w!( zYEIC&ygqc{qjT<}T(ypG@)zF3E1Ij0Qo`%{xJpm$=65Dha~$9bpc*_scQ%R&F;(jx zVk;y~LH&csDu=eY(X2M;fE$G-f=M1=QDZPl*)Mve1&!ne{UN5|N;nD|sAivQ?4gQW z`-!?1i2hXUdeZEwRnt8RzcpKY_S-4>h&!~!kK#~j?1sA@-3iWTaFu%;k4eCx%`LJy z&G{<)@)p-AMY%0|khAgpXOrj&Rm|Wj?9=nO1TC)Jc`LLczy0GMglDdr+b^784pMQ4 zC*R<+P~HHc#%AEu*<;z39x-|Be)zI!0i!h$2LSX>n%3d!0-cxk zaEmhugt=bQiYgtfU#}G!2azx!_QX)zD>=^ZreIf#HMyi^nwucz6banL%@%0J^Q0-u z6;mpENEnkFc7{xr1`2*C+-0yucEDyuVvO5*Ywyk73C%7!OPKRXFJooL#Wqd8P7sz_Fp)y*sCBoBS0RB+yE7U> z{r#)VQRdKuRqTN1X!n2xQRPr!iVSmnh^4I@3@C}h29(5+;g|-gRMvjfyakxp-)O;h zkcBPt{$&@uj0e%;8$Q`F+DXW!u3xM#$PW6L)ir%?M0g1Iw_FkSvCa!tM-cX*v*g{9 zpSD(X6x62dA|&wbC?nGFRUCwX#fcS(dMuUfC}5V+-!l1!5Eb+p>j`npv*c1*agXf} z%ckhZ@8@0uEnvwyD~BK2HmZQUNaMkfaS3>h!~@5Cg4&TlV1(Y5FKrSUSv}ZMnp1B% z^_F!!WrPb>e9UbJ*ra7$(aa_yu?9Bbjxv*d>erw8(ZxLD860y?rm)!JPL-@y8O}JH z0rWsQj%l`1+?)z`X)Afngggm#e~!l=z?V~tWu4D=ak2`O#q%0Zv^M_W|N8^X19+Li zFtsYhXS* zhE2!{*K3(&)on8j8i4c&&_(^^_Lcz`C)m=~bJ=16#w}B_KujINzJ0X|dnYU! z4cq4oFE}_MV>sGPaA=E~^|b2APmx)zZV@sJzW|hnrG^r9Q)h9Yg0CK1Wid3Faks4-VIcv(bdTi`H_G>YS z%c7p7)-p;xQ;7+$XxT?r+dvnPMy=e9rVenowE*{s0<=SdhU<-IWE=^r5>E12zBk*n zDouQNOs)*Cyj~=K(S&+Iy4+#gSV`5z#hjFol{+X0Q+UZV9; zO{o1Ot>eMfz44*vfM2CG+FY?ZL04&OEHFw|83oS_abx?VLzbNThqjeX-LSBYndTo4 z;Lz6M0sK=ZjwA+mY_Fa_7t4Zt9@!FE46B))BWGh-w1s>g`Ebj~<>|K)n#t0gkKdBd zy5XGJo(Z)=dx1Mrlh{3ukIkO6Z^*cUG!|hoElz&oXR<9y+LxWPMcB_5ANtaNn}i|x z+JCyN__0MxKYP>HFUTnEq^L!!nJM^;N84;Mo*gkK<$k6!loXC)oz{n8&|C9oE$ zeR$cm!2i$Q`v7TjRCj`}s;hfynjWdT8A0n0Lw3{PmTb-~5P!T#=j>KXG?=wpSom1` zV(*jTd|FO>Xno#eKyktA)<`t0uv%Vu1IOBqPcj&pa2$ir8|#gb!r#bP=vc>EwzZss z;Mg(XSi4=l9yU zNOda&t%#M>+nkIZs+u)7idU3Y$)HhZFiKe!jV>v^rh#IcGiiUwLt!zcuQp;88}$!l z(YJ-bO5#9O35U;;2!)YT<+mV^~YVil+GnzLEwqSMrBspWyMz3wul=kILT#n)624nb%aM`j#`Uw0a@{{5oFIjwBV8>_8snTK~ zZ}4Mln(2M*b<0!8Hxf(cgme)ymV*i@6KGf zMNM7Ds+&L+Gm*w> zsYQRS265T7p`!LONBPkMu61@8s78BmUIy7Yur7pkY8{Ly-*N;6{xivV`RRz zErn#JDR0Fd&M@}z?Wt>NCR;!8mc@M{*&aE;lYf~7*)Lyl37!J>PWLl-u<7)lKlJH@ zrY(KyYHV~2MUtKu)Y9l4c4u`xI&ySB&93;C1Z_LP2?T9t@bQB5^6wnoUdfl~*6qO` z$%?Z#b!;ZhGkw$6COfBSYD%wmnku+;#Gi-vM(b zb`GPdd9PV$wN}RotCZqh-#Z6AYvWs$J>lr=g0>TcRMEjRL*7~c=#V96bXqi_#;7)S zaMW&rqPI-MAO7n@o3i5k*t?fg~oXWdF-7a`>^?CHMhkodxf3YP`B;v!Ckl79fB&R?Awol^GDEgt-W&^V8 z1>O5j{ODdh`m<}-%gTZ`Z}0g2EM2sFZ~CgC*S5>V)6EFf-m;bsmT_@$`~241XqmqA z^IKU$C#e6)Kib2r#o~1UFFXtAN#1JDQlA%R(@}qdhUZh2n^nlr$ta-W#j;fz&@N(6f1J(=`Z=T$w3TP>75e`UZ_vqQ*S$~4&psC6C6pb_(qor077gR26vPXke?xEE_q)gZLH+26yLDNjiUvcy8Js(1lyVO%fFghCc|Ht!5g>) z9RWB~Qufad`JbebeL`V9qh-cZC19OJA0i|LotXJDF5uF{ON})Lg%^YcjP_#uqNCX6 zo@TMSwq&WtcqjKn(TR*QRomrARSH$YahXUq<(->Xd79L^e9N7039q!;{Uj094BYr) zugw*7SXy`o<`RJMABrHO_I6peM-<@Xe(UlsTw7PD=zF%oV=bn>`|gv>;|a{0bH zTS=ALE0Af!<(Mc!+X`gDIT2WEYNDgwH4Rj+iQ-&E=xfNk>K}BeUWkqKvbpgWNv%Dr zej40n@~|UlO@_@ij z?+KYzpOf*amlc|+T)!pC&@f-td~ zxcFy0R?P1Ey@4f!ag?s5NJl_oPWQE10@PfsUND12FP9SD3AUR=^ESI3| z_pjWrf$L%SeZH$;fcXTMtdzNVC6sN@JMp3E_f7k`>qNIP5Me)6Q1)f_V}zLUba{gc z1Z|6LIo(^v>$Y3VfARavAIQ@i$dIw!#J*~23&BUwvh)U$Pvl?wKmPXR5~)rRw1t$u zXgM6T#VKBIrnf5%3JyzR;Id>LW5=Lp&96GOSrgr&K_`(gsXW(m5VS3=HFW+^XM>3x zh|2(?-G_^{D;?#G7d)}xMNCLV^15u^4Y-z8WPUCn#(^6(gJLHkmT%g+pzYEkg0_ec z(IpFLb)|u|KiJ9eKADF zm`*cn@#$FvbNw13y*Qe84%%X^F;;GJS%%`+;+#GP#b`imwnaGY;s-v!NCGf~t8?V& zCm?faOTuNn=L(}~wIcPo4reJ-2c4D7R}8s|;>TrHkzO>HBx5yDWJxu)q>7nXX|>d% zzgB~|?AlOq$hD*7b5f|P&D!SKSh?(3m79zT8!~KJ9NVr{4vK|<7@vD_kr;Pl?G&+0 zK8d#B{4>z!w*rcnMUXM*pOv4pn1hLY?^b>R_V&0#yOuKR1`A)tOR*00(3};a&A^#q zdGZ4-=5!TkaeWK*=rxGcxJNF$kX~+55RyFZm^Mq)TKAyFR_=Nee^G+f3~^^#*4$U| z5W(bPIng{FVm-wM$MP>rxC%0HXyJ?WasY2BPsfD>_&ro)XZ zYs2DbWr6G(a^Nr$86G_Zc;hDWS<6T9Ioc0T(G>1F1tI?l zV)tOS_YV2hWIlO27rll`eO$5bGF&djRyKQ1H6!@_;=f+}*u@!R?^ikVT9CJcxfxn4 zuSj3f8#EC6AjW4eAdE-IbzIt|gQ6-B2%|Qa>ux~pamQuB2?VmLU-`PWv?jXJr6JKu z)+Wu>t7nGK-2hi>gsh_*(LXw5kRW6uRF3z&OgQ~+t9{s;-md$v1LWy8G%8+$=MgAl z6e-2$pd%Ppn$}}0EBESd^bkdl%MLTN$7T<)lrkI3v5SV(2?trx{; zSTrC!ex-M&+)+!ycExkytc{sc>Y-T3j}k_1%Eg)&OM$(uUl85Zq1JJ>+9&N`9Q~%Q znpkPIq}=MD9P8sH95CbCjnl>qF-x=rc$Sn3#l;Ll4tb+_d;$P*do~mjlD4;X)@b{4@qH_Rs_#@iBK()_|P#&6QOz% zn9SL6-_Ka-g$hwiqqBn0K8IX;YbQyq;Hv^fQxBp%z_>KF8y$ufuLxTu)1wL5c+t^$ zSlN_Jdow|nqHQh52zZRq3hm~I{z`_CQ$oo`sD|neif3m5hBXI^-%3_-2WoKJoW)kh z{lSk$6CcA<7!}(Si_<0fE%KiHbl*JO@v)?EeimU6F?7Ww2a^E9pPqSy9!;&MFpQt1 zPrOG&WHWe;e@QRA7)tK`=r{c2_M{DIg5S$$a8IqEog-()(V20`1KfFU0l1TZap~xy zspzJR%gXAKWwj!#^*9WuNsC>ll~ctc6Uip7!VrJgDcNBrqX(f0{`c=agoP18LHOX) zf^jU!FkMuwhab6(MX%+rB%7?H-IG240cw$vS-Rl@(I~{1r7-QS zjufk)nj1x<7_Ar6cZKnyCuz`4YG^;?{@0DJyAUx+f7JyPk<+=Hw%TRryD9kHqUz-G z9hG}VKf~r$D1Fb#AIY-9_WmSU#?7aVS^?&#JzuTIn-MshEb+pn!s*x#v?9vqwf9#@1OkzfPOz<`v3ZpbH7Ri4Ml#zUuWg}RSoiBA@Gl4UyahGTc)0Y`h$nYCg^*Lw*8ZxFVL6&2ecxAW%o z=XMghF11Ilp2NzZ!wE*QG-McLJ^TsuTskxedfb#%1%gsXbD&J#zM)-?S}R#Vs9!a; z6zj%|MzuOmO@qkSR0!>dJot=wfk15eO-k1wm^md z;-M-2ngM#?y9SV!WzrjTwHz_yS<&-&1&GER7?-k3+maE1VKki$#EKrgvaCnQoZX{B zTG8Gm5l|J~qJa^PR$!%23*e~Qh#EVPq2B9nQS!i{;KnB$XfMOzxyr5Dy&7C&@tm%( z7YV<+L0e8OG+BXXNS+w+`wZ`)M}Ub<4BEk^3?W_VjSHDv6{&m~+e&p-W^&18o!k)SO^w*sdIy-o0k zfY(samVxk**+h!0qZ#sppe>9d<_EL|oezSxVx{L6Sj1<9-I*lxDW7`RDP>T?3_IF$ zxnRZB0eA&RGR9tTNHrQOn8{!RnZ z$NC{B@=M*wm5Q4~LLa?th5iY8FFuY zAdOZ`(qDBUDmkOmmc3LV&zDR)^IcFUn(M6EmY^;5_w&b(!?tkJW0yMiO$^TyQi^9B zc6jHgZPw>xa-azBS>rXGb-t9_yy@FcWxF=fo5x8jGapVd&{ zGx(eRrwK0K4NA?x=of!`hMu~>)fTjxRSNglr%9>C4uk`n4Z_ z(_Z}b+0+&BA{Vsf-5t8`p{KW+h-00>osTDu-@R(^y1>>(MslafN=(_}{#Ng9GMgz~ z`Ah%&xA*X&OnU8a+Q`^k;DjEzR5Z%J@Re7MB@Nz&c3$l8-S^OEZ3Nc5Bn-a;4Qlli z>$8@0Ce~NEapmVggKVxGPiW)Y9e55K7i)h!DOJe>U!TtMn-R1%WQsF014e9?fAoTx zWp|26`DynPl8n%vT*pZlYR_?+@fBZq8&i)4t5Z{$%Uzbw`Im^0Th_Ky`{mm%oPrkZ zT-mzWJ%ZTaX8Mhd={sQU0;(XU3~hh>n!f_xYX+NT+0VZ0$E9b`rX3c05AGzzM)I$hW0KRG?LEWhTAc_tWfEb~QMCY!c9;XInZP*WKCo2#6Y?WIbv2uA)+IVcc zR-30-2#E2y7grKnvTrqL5E0rG%^N(Rj6*BE!H%Xt@G^?PTe&C1_GxkSmTe&wl3 zqVc7w=oSskco{V;>#_H1IjApb}0D`u#Jca^q z+HQ;OBm#u!>&ZilieUTaZhNoFhbn|Y)Rj=W!VWbT_MxL z;i_5EcV}+QlZ6BiMx_!{hI_1H1;OMq^YpI&_~Ge0<;Qqoy19c3zb4B}=@Im18iR=j zJcP(BoL>4a5b{vvkS&R=3pCo@jzQ0=U$r!*)iu#A8g!Bw-jfYsdYP5Z#4q-sZ71tJ zn?$U_;;8EB36oK#Y~e#A`#2Gi!R!FAE>TiWS<-MFikXN5I}lVW>|(wNFgAfgX7F3O z9Tsv&g?HbD7LnR_q&*ah{%Z!v2+I0<+z1YR6qMFcOHCuVg$lpq$!ip7bM_@!hK9@& zst@w>-U8|#-mjxus~2<{a=3|plTAXcR)#$KjM0io`l~L^&6Lz# zy!kRm)Is5yT7V6I9zk1P%8SAAXj?aj@e{Tp)#7Lg^BN$dE>}+W2s~d0Pw*2VA?xde z^Z4m5EFd&+6nu=}9XQ+W|1JVffSvW(4@%C{U!uP3Mdx4#V&$daZjcs?Pby$W^-jFJ zJms2h%m-BGtp&!fY@Jpx?K78sR~J@ps}(~tCZHxQcDkaM5}QjZIdT~Z+S;NxA+NA5 z;2ZL|?qm=d>=O)0P|v?Ihhnzln73R5Hm6m5>Z`f2vX*1<0eTsgM-e@yU@ghJunFyK zz4ZN*?#QE+r|+G@gHgOeM{uF-HkktBQKqZum_dxW1IPo7r}0=b4Qvm+!#0qP2?Jn< zxWj1H#$||Na#8)G6zI%0>C9)MASDY3^^92ERM6pMrD@TiNm5xC+7EflwL@G1qic!t z1Tdk1F+703rv>C9^HUG}NG8AZ5VR$1ISlW@S8_~Me~D8|IfUi$~hMrvPse(|EKeEvOo60k6;-w z^o{TN#`nzPrdf8~LvJPjOSoAmY8j_yi5%^{{2#x{{U&JTI3RcdSYXZffz@F(G}Sws zp3Ow!8n>RkG|cCy;t6ehyMrjIQ=u9_#P#C4KlY(Z;KN7H%na~jlF-_W@xO0xNoSpK zBZ5yR*pmEZ2-vWD%M^Cz$2 zB-_BFQGI^d%dVTxx+ZL}_YM1Fwd8Z%xNP?XJero3pb6m)c za)oGVtSyQP`B0VCOwL9GR&7o?_(~SsCugciw*vZ@qm7Giww3U4;mVqbpUL-hRWT3qaugv1^bFbTZ6P;mXxU z-~|HgQkQuBZA5S^jZ&3W=cr`GdjZwp8V_sc>Kl^1Sf_U{1GfeTO&oA+!xCu6w@dS( zzC&&y*MKfnE_Rkj&=xzPVS8jFZDotJG`|5K+eeQud(*-NZEr`FhU_+iZE6W;YPD-3P)(UDWs@CX7eOrOE)`1#DfQx4HB@5&pKIXVtH|v^XNVMT1T< z!>xW<;5>BHKRRTPAl%VUf-zL)d6@Z0^L$Vok32z*u$bbL?f4j$gY@Wn(C;uN4#1}f zktXgp?oz03$``_$wwwOPGnpppP{;nK>PE(L8L+ZzE#2tryeF|L%pXf<#kEv@PckXp z@;8Qf#_51{sZKcLYti}ZG%uRt=Z}Z}{Y|bT9h_VRsylZQZz7e|l5&r^JSwku#VlC|LdiyY zIaK!|F7h+#JNB1(1VLMarvwqSwUBXUFh%SB9x{A38e61KOCsQ0+1d?r7lO9x*S@AT zwbRM=`fFRsJONtA_Q(Pc{3^DakqfQvJiT+s$l8czSJ{j5EI80(j|I``$K+!`oglDUI{KY2Plcmq zR%_Q2Y>y21#QQ!Yc4D*o$$dne3Y&cWh<*1~czJ)DHs|fJ@~qh;7Wy82^PfQZgn3(D zo50ys!MfbKS^}oQ)Ta)lAv^5X#Ee9YXsd z58SLGCh1=`5;@B=bnIn!J)U=ztIwiF(O1q!=Fydu(`TIeQEd zf624-`A}m*;l-0bn;!aIw%VF+pW)d88r15!gO15eq^ogj2t$Kxjw(hq#n&MHEMz{-z=-lfY79k0NMWESS@u{jFWJpU~D_YsY373(CDut?e(n*^0pAUdp(i zc1aO$U``S#_$+(;eGlD{tZdNrKXlC;Rvk4fs?^d3#UB0ydM=Gsdeoea2&~xLTM-g! z!x@8~HNR?ZOKS(3t6#Ng&`G9xX7Fz;cw-w0>PGzoS)3WdHbSMc&Sj=PSNJwrn?9S< zUFo$oZll6hc7jqnZUO&oR(+EQlr=)a$RW%M8ZX zsOdWMvY+|wpG4ee8$?s;v&~ZF_L>B3L51GjhfIeNC4)bJL!f&OG&g$KB^wbKh7cMH zSeJ&YMb;x^erSS1Llq^-q*7IMn+B7lRPd}v!4m%R3rMRKuq1$8>JqQNjR=mVQL3`) z9F?r_q|%HU#eHIA|-LXJGaJ&`d9RSzWGRBWlN*TDaX*uc!TPsWA&q+E<%V-(u*#wS_duUvw zI>BBom(OOmlfX;Nt&p|=H4r>444e=}4{Cfl=`#KaggjI^WJ_Y}0)x#v20g2O)zX+& z*F?8y&`D+pgSiFVanu@-(Eu#F6iMi2a4n2dxqOUJ1+McjkJdd$x^ul9IY|L9cU{o- zgwE*%Tfq@K?TmF4Wuo_%4KAz!eV4W+^WjZf+?g&%vW@FAc!mOi08@&rD0ai?=&%+1 z?`;_GAc*Zcp+eOTIk}(cOP&$Wj>hnCf$u3nZn*FvM6`f0p&jHTX} z0=N1!Dk79_KEB=9U`ZHx>jf91bx7r!mU)*O>-)k*&pkgO6xci5(PZVDwsL9$xJ^ni zgQjs(A~SrADYfIkUP0{fTgDk^r4!d1@IVLHE?#zlrz>!gjxCx2sa->AfATOR1El@* zW@Ls!D}tN^g>@PjcMI7OsadNkxg`Jw(4|0aYbHsp;OhceYavd+xHK$5IOi*{=2gE6 zSgo9pjTare6oe>QY;uA$hqjV3>@2y1@r^`bTqPUklq(yBKoyS9!@R>pdscg;b}wbJ zSo2BeX79!;tOjS#@cR(Rul}#o#QP<+mExXXnNUuYQ?OlOo9Ncxe+4eTI{>VcBWT;_ z!d(5ki{^Sb5%<6J6S#SHcy8w_DfQjcm?~)g&k@$?Ak?78`PVLhEZlwLF$~kdIfFQ# z9YgS(aQ!52NCF+$fE5o~2NH*lNOu`TSY93SNk_@y_eyBGYT_{7?I@mBku~{ z9pp{UebBa_CcTrV_NywreT+8u@!mqp-}~qDOE;kMJ$K_SGAG4b zUiaZGg8o1J=5@NaO`Oz2`vFZMwFqyRa?S=`>8AW0zzfU*Yra3MYe_Ba+NrbQLNo@p zddeoh76BUOBk^uUjYRph-GR_|hiU*(``@ zzTQqPOs`>k2KVmg8LTkFlU!_O1NCktK3!>`qV@@R;HGN@$K%1>TbD8F1f}lAi_eA+!@sX z!FuU9V{t&3&QUdY+?Y60zX+TSmvKVz(3TfIY#-|aP=bdwwHKbMB~@vmH!FcW2$$p7 zcXqYIRSwaVj0jYl*V+xksa?Z0vT;&_S)a`=RW)c*zN`!F%cevQI_f{-TEcAVz4Rgv z(r4EKI<@SGR7{a)0_>Rl0@sm$QcEMVegx6bfN7|cDrxj=_hgM_9uT3Ktn59wu6_Zw8qh+l>o!bN)rClA)A;By(0396b4mu_k(XASE66)LMA=*kKlk`{Zh0R9ZF};j+=ca%Q z4uh8Dk^xR2ms+AIE_p1nPGFr`g{#Ib*GE!^>yyw=;~Y)wHNM>~*P{1ES8PsHa^xCP zK-z!;#wmw#=+TNu{6+j(xE+WL6zSnm4S-TRu)EUwG=!c7S7Dc&6;fQWvU3u#&kR~a zFSe2WBiHcIAh_eUM5LjQ(i`cT?3jfE*LR5b5c;lp7#FQ=&PD{P&3!LiyRc#y&V46L z+EuceUp2R-wKdT#8gvpF9D_wy=Z&>S)E!6kA8{?=AE6TDIfb6KHs$l$?S@XO%n8++ zBsFevNr0>JMSuT7$a;#Xw##n9DxXp`WGY#?tSXSw!@^Ushyaf z;IZb2B3+gXX6=!9f^b+cw!@B+;6`>N9y8^s7K#etfw2E97Ij-@rJh_)s9 zcn!+>hLW0e$g3-j1a}{74dF|XQ$hc%p zXm>^>bjt=pX5!hy(5Wk*_@jGpYUM+}JcrNO9Y1;MsvL(8;K_!$H!jNSdnCiaNATj# zt!C#YEGL{S&bM`S(Tf$MrBMzFR>#GWwk2VlqQHT2=t$|{2eP>!FOVss7w}#3@uDYb&_yDJ_Cp?h zrcM9okR@lFEal}(CmjxmCRiZ-$+^G!=qk=Ar+2>4mkIjbVpr}^Wwb-LAHfLhV@nvk zZg(LAXP)T!3)Y!e(fa!4Z+-39Jf1k}2LA;@Fb4_)@_%%F7aqom|0n+aOJ&hGwtdGy zF5wNm{hAbRbK;$UUS#R^8h`U=zj?t&i{y@t>3_4=MW&q5@+Y=A>*Jxxfjn|SwEasr z{O>k0m!*h0D7+9XppIJjzOZ(w+fwg|t@7ZEr6uJydMK`{U_!xNmg1n+Znv{t6e5yY zE^i&6^hobQOPh3R_IrWJ)^NkfwXjTd3~5(;57YvU3q8gumzBFJ&z4H#^062O-5 zYSExsmez7Dk3M6yVv_!<3x-7rC5vMfdO1{gP&|7J>|Kdn)bJ+E1NY5X%9wYsmy~`i01S{{4z!1-9)&9hS4MCEn^q&{@fv(q)d0qD~0j| z*Xm!={V4q~-X%zx1qmo<_S0XH)u022vtb7+p|raQ1n69mV+V{hdc8*-q%Q;uj9=Mw zIWe7jSo%tJ$ztUma_fMawAdMCp^`9Q#^oy6_&WS1l!q9tKiZ-NMhV+D#>QlyHB2)B zYphe-7;k`V+vC}1EvdF!umz#456D{J{+UA75Bz-}GMjL^Z&2XXzRX|RSlLv~R@iBl zEOlBAQi+Yo9_W4$61N}#skFb7fZK zgv=;HMMyMj!i@H!=gPfHablX}^i^%?wp9wRXC4k4`5q&zDj0mfv4Z;zEiRPG&QDNw zTHOR???@&(7*Gx1s5AF%va+KM^aoWh1Pd54t{d)23pp)0&$r_AU7>XL8n?b6S3YSm zX19-OyByc{_Qv7oPBQKhdoCd0!wYypz>wufDSr$KtjGlMePRQl?tX1QVSK)WvORFX z02Ub#Nymw@?>~WeGi+oXR~No5Dl#fo7A`ODA*T7mG?#-p%@zulFNUN=YMhq$Uy&4e zSZW`tb$}GN#F*{@B|f>Zg>GCfx;T4?@pbtNqZx7?mk#m?kD>&!>S!|B6>!h1fDHcx z+|ne4FzD6sm6}$li*C`NRh|&2XO>UF)f<_hzcZz4AxMyekzP8AbDF@}1&m9b<4ei8 zkfPc$l^|q^r&Vt2kKjKM%Hr5|*%8`E-cVqv6LICM;TAs|c}DQEyBZ#2vIy=N@(z~M ziUq@_+ycH9AOCnS6J1MLKgEZ<42TR3${mKN39#W4Wc;1n2o^51(giF-+avp!l5#Ul zEQA|doS0qd#T@p7yMsRQ3xD&4?QB`PBzwWNgT*QYX_WO0`ykKKjjz1%e_E5_vqS7b znC8P(LsVmnCSt9YQlIORz>3x3O!UwX4GxSV%8E!au}~EqB$QpMYA{hur9#^emXLMD z0V~x6{X;dVhI&vIRTUL-&N5aFYQZ(VA<{{ywWw@QOUkWxfCjNX#@#TJ#<%O{oD6ws z-XZRKF-TUff*wWCmRQJ+&ETiv*FXL=_C|!k{g^m1X_t>!gL&=zU<+^EP2uP74`1*D zmtbVt+cl&?+uJ!S{@~bc3!SvZP3u2=@}W;BbjPV%pTw4^fUN%j)ax${e*NTbvNVmI zDFBOPj`p^{_&ZR=%5fVk{n)if=D>NY51D(jGPuI+H<7C25pu0kzin>83ly5#XsXS1 z@B^8;5z#=!R{hEX+AYGwN3ZYoBudl2d1@M21Vk7wrOHcK7B0V z4qTX|`QWxE=T|KD#kmdd!voCfpI)b#z5CI^eksS&N`8Ja{jCtDjjFJqy{mNsS@L zO<;ZH^oDu(wkEovy517?b`BkrFV=qTbEjw>RmJ|(*jA&L+MNN~ouBcI_bKTQrY`I} zr{?bZwlrfU0mL2{cj$k3y79o>>e{$CingRC(5-aBqa$UNU&+dWQ#;qjSE-w`@uIQJ zDVvH`vSwLY%aZp?5ACdfY{W?rDS(k)dh|is-2yg}u58n;58Be&;22)a$-Z{a2jHt_ z86+l>NrCl9{P<&6%o;Mhe&Q{p{-Bi;GB~KGV+`q;V-u+A=vDlJo-?#Poo_F`|IOa% zPd~)84{>|{I zu)4;JB#z?7w`*d3r-DjWF6bdaTlYy=u;=tnq?S+{G?>j}&^GmRFKi{A-2z(j&jw1V z3FH>EgMDL=+g*RuoLaBN33)0DuuZu)R*^5uFS%_|(?c%tvXyvRH7o9| z`(xKg7|q(av`QBO6<7{k)#kc_1u`3DDp^4I&c@otg3;P)mnLe^C@WNk_Cp@cU2Vh$ z`Y^;MA|hv8U{R&Lj6?^8v$lZo9%c>oFcvn$W62JRe);53a6-)seU#BE>1LNkZ4BD_ zN0RotFj2m`4Z6Ze5Sf@Z;P2uHv%B7bUPFn$ZIoE&3kG!^An%J1>t|Q#L+XoCHRNp_ zv)Wz%1zZUpOdv5B#v*F!?g0+1ma1#LlR#nSzOB{OtXIjA@4`X z7BexqpYTla1kwr`+M3*EmKZNJz&5*34=Rug+9H4S?N7h`P0NNY%vfOd4)>}eXy~B$ z1fRgs~ZcdSn1c*M&Jbw>iTmjw5%HKWl42zO03FMgKHtY*GY%9NY&Gl zzuK#Z`J^(05}SjzrEOKv#~mIaiM$Eg+_E5$nxnSE}uO` zNH#(>RQDn->T24_0&$8nu8$>XivTR0zQ%6ah2qvPUL#L!OcSn&Ps>N;LF0qA1G135 zA_s?Lp8X>`ux$ z4saeieoK)o<4XH)U-`GMTsP4Ej(;0_H6&te@$lgI?PT1%%pklDrJS>|X}@$=0B zI-29J7&<9yBNb~2?kr$jTDd$5sCcnlYq#_=;rstbJ%^-OuQkJ|MB8BAdf` zUYO>Nei=V)6aKaI7^U*_T434Ws(bk*(Rdy^K4nf1r{DK)=+*e)DmG93O)f`lT*~fl zwT=hX#>G*zCDA5cU>wb8b1$IkM!>0^wO8z^x~1bqV;q%TMJrh+nXFVHAMzPrGfDs0 zNXZ$09)MF-@iGq5?iR2mDR!wq&~~5cW_Rh6;1}%AV=CgzhC$({F=rz2z<4&8{j2Uw z#b-YMmN5NGiDOIU3q*wPZ>8lkvOH``1jK?euNBVOGK~zP3Xn>XRel( zt*4v@s`z4)sIm?}#jTya24Crf1A%c2#3dz6-7z!=sPoPOx|yt?R^PThg)D^$5z zu|p0MP?HurqbyVs2F$p;diF4KbIH=WNl~KQBzwp>0}<{Km&Y&g9Hh2_aswQ7s$?31 zj%Jmv0kAEbyzCUFZmo~yxHUAO{-FXv=o)l-J1!McbE8ORRkYe!nH4!9Gm5W@o}_`D zAf<}d_QQC0*55=iK>`pqB0KdbQXdq?TR@!0;yD91;6*N{#e&V|63)AxAv&Qy-1ZsH zghp7F{9$uyC;(OU}!HRs3dz0-FfR`pIdfr#bncEs6*?mio%7iSTO|U`X*n+hqEF zn9a?bR>r-2VFhp6ekM;XG2MXGMQrYZwu=bnF5%W>{@37uiWN^PV!c{+mJRd zeL>KciA>Z+jo*U=D~%21TIFzU$%w#UbF?cUEdz`g7ZC61DH-~RF^PU9#a7^&=z5oG z8nnt20v+iWN6^-EGKm{EPw9q8jO4)jjH2EB3C3fU%P5WKWIfV>3r7=kFIl-D5hITK z^(lVpt(kl$w>a-6Oovlqf6bZDbt21(O5mE3R#UubOBR2FZPTG$#);BhY!gX}DO_m_o{HIzK^Fv$sTjc1??gEhL^EK8g0un(Fwv`^ zmWlM%m)ub3c+|$ln>;d%FPMn7TGG*UHlWybRkoC=WP#sTC{>g>zEBk%BoKzpLq&st z)VfKTDi$mee>ku*Owd16gR1P>P*GJ;A?GY(RYv1bJ#EK{QM z4U|hq3RV;dWFz6ss$a1qZcE0Co}@uJ5gX+8v@YZaLE8pnor@}6CD9aa;YiSSWfwCw zxejA*fm}xN8p3JU9kK>(WosBfCa0e>)T4E4Pd*%8KaiRh(Cv}sp^jr0n-*eMog`-P zq5eygWUu(@k1|k&wcG2jUBFf4=Wm-U5`$RnEAf9`cD(qtU+v_JkOFwgU6i?%DI+(< za@zC-)EWFcfES0`OfC!?2p1loMII@ zAv5u^#rwECmMB5nBH4L(<~XMa{vd?^82DKz;i&-@Ft;ASY zY)jHeW+Z59mf9Fx{W6x6V{{^=*~_3svS7G)3j3+%lw!d!#g_3>EX-&RAHj9LKWA^RJka;rxF|()7S%9Hr)JZ2#VS_G%7Ig|+W0DUb2eUd*`=xm z&9bzXCGW$uk~6^AEzl|Di z@qOYx8KMVXH}0iaTrLi9<#;^4}pbnLiHh7MfD5`X*<9bMSo7O}WU zruD=B9Gf&#(R&b=$cYiOn_Bti!jv%}=>o-RX+Fnejd5BIvjIB^hAcOU00z0NPZrRREM*wqMr(3E|^Y=mn%+{o0WUWt^pMt-71Z8nsCTkXwFo!@l?3(&EV_F zaw@-#iY#Hlql1@F>h>|km9hqH|nGzqUF z!!r{8$tpXqfu0}Lty0ODo)Dr5Z3PFDV2>EDMnD|9-Y~vjQ2alziP!n_JXj0 zaZVyDFZ{({Z6UL9{5y1V)6>k3aG#@~t@r<+=t6Rnbb#|BC45dqwk^f`wNlGwJ4yYU zwmYD}sd>)`p7wAfm|*~rc7n_YZ4HRQwTouj0Y5trQ(>S9-q4YtZBC~#r&cUw)4->= z5P0+l|H}_votgw2o#zFIGh~x!gExvG?J$N8Zw|}W>_*<2*pu#h<7Zo2=&Fq7w&t;_ zNpM+b(on9BCZk<}^C@Tx58ZQ0Bk8C=JI@iO5cZYwyd(l$A_$)H*-kSr(5PHDc|}P9 z+BM;~#7mgL7%sx|jVprM zl*F2S89184T^fR;qd0A7fCH4;!MZ6`ycBJNOJc9>JPc*zOSYN5*s1?NZS#NL%&XQw66>!lQk6?9NYv?`dvbO&BbHFex>$!fHuu4sbS5 zt#PQzssjL_WCle6U(uyYbxpG$dV*M=;os+3gcro^g@ z{v_&Yt6k0?K|$vv?x4o4!NEZwM6M`|_V{+?H)&TWKPuV%$bn@HB+)m-rF5^9QdUNkvH_7}vHHG>j`R_M>z+J@(b2D%V+7_v7kG!~w z>Dvkhj{WtI{^}AMKK}l-Ic9L2PR^{c$qIAVo%a>fyG{nSM^114@4oUo)*ZDbNkZ5j zIqRqCt>3(fOf;)nng>1UZx~INV-xpQu_Zwmr#N&2t<#ax!4G8WM!3zVWHrB1Y;!hV z^dt?MWod1%mLCLdJDKgdAgV2NOib=g+a$@bJ@O{bEUTw40#UYtpzQoD55AQ^q2IL4 zleeu6F5Q$b0iD4Kn8{xK?F;Z~eHQ?g3)-4jXXe5G8+WH=X0$5=#R3!GrLR=;}b zT^U+rdz`LbUdJ8eOa5%$5FPIQ)KC4?%-iS$4U$ji+$PY~8@lQfKY4eSq_n>HKdp!fo@fciepIs)v{c*Ubf&6)Mp{Sj{CD~7!~pyDM|t=(?(M&-u&61b+# z;?xvQIJ@Z#PAJ>7_S26djc9fo*@I7CW}wf*4?T^knz7Bk^W`agwdcgiFC6Pz`JjM+!HG)Vw5_d4 zu5L_%JIGJDUi|vWLwHl6WP==lH5pR*6C=3%EN61m!-x=o>Zvxj4p$$}lB_nqO5L1| z7wt^r7^@mI%hFnwykB}~_z_4}Dgf1K07ShJ7Aghp6poZCR2<}IZvg|pd}M$T$O#ic zoRly7X%X{D8I-%8Mv3K6V3}y=lJ~jaH-psFxv2%!yCv-JdqGY1XIz{0j6do0)n?Qml{CpB_aW zV9tLFj9=MwIkBDkCqCx^ek@R1Vci<_sgcN#d(3Y(J2*i(CA+oqfBx#rB6AYn8#(+cqI%z9iURg#WU{hly<7_&W;{|h6 zGU#x$C%-^}R1-P$_{7S6HcZ+X-cth4gOnBVGUPfQArDoqT_u~CMI{24_T4Cl_FT!V zVxx%yLfeYcBHfsRQCwAY*`=xmJVwGOD)cqvZq$UV+K7#u)kc7hoH9lMlqwt^9pD^wbY$3OCmMDjI3*wCz*DC3N;JmVcA>;J*zw&}( zTk(Xhu;~eLZ%3y^;I4-G9My6VI=)>lr&S=FoXd$4zK-aR=VBJxg#@u5oW!6D!nWzA z#WR0`$6PVnAlL1Y-3G~c7T8rFNnwCx>M~a>K6l{Xv_&(RxyuwMi3pnnGlZ>}SJEpD z6rmkZG5*pOFar-H0*ZsLJbKMC?uy~xK9Vkw8pt`k!21XmZGp$Q4hg3>K9m(Lk#1`q zt5E0wrY6waT(oD$eGs(mV8rKuB=a(jidGl&P7{z?Hz89AQd{8`XK@fmUYsew*mgP8 z#zH`h<_0Jcm#70Fgk#`LGY|~dUqj8RMbP%6T+HH)0z%Lhn@OeD15ef>;TW_{_i)?F z;6@PWQPB>CkhsKNkGS^C8`w4KW{JBu)Dju-amb!aYOGzz>WvnN6Zbi$rQmu7H; zj{&Rl*_is*Tl3z#B)yE^SNd zTtO)K#+%)!M6XyUE3>j7Gg{PcReKiw48}oGjRARj@={ zR&>DG*9Wqwf9Vfp6~-rk4TYH3u3Dq=dQ}qXnhLhgWz-^~wJYkQSxoHY)Gm3NWXHPY zSgLVXd*G;?Yf5Q+yQRKSW>Y~fCjs^Zp`UthDbE(f)OO{BJky)#FGh>GU|olw!q-3k z6Iq-jaRHsM@SAjr4f14V==-K)nT$ zCqd+rINv&PG5^gg-{#uQ_9i!9t?9X+18HA=4v0~cP_4$7L-gHYLq1gH@J-2xz+iKj zP@v{U(G*I?Rljm9ZHcXku6L=XL7O;NA12LapsqIp+X1+)zxCsWsvuz;m9U2-mm$Nl^6@|NG%H@rG1Atp4^ouCVhIH5_@YcX(JOEq@u9C8jl%^wzFgr zvqb^V6Fco+lk|Kq*5jh19G-7N>ZNfZk9vvWZKR8qF2{qlQmb^VBgfc+jacO}ityS7 zdj+yIkOwkFXj_3SP>s*Wi;m6{L@U`)N5_j3Z0KvqW0zv@qp3NpBFXgPX}P6Uygl*zTa*-& zOL5rf3F^+pAIIY!vM?l~Fs9haM4kxA>FPJ)9yfFmFf@B&FnG_9YdG|zgtH4zCc=9B zG#>QowAM`$b%1|1ETHQGt1LgLIIxQ7l#Osjhcn8rtI4EAr$Z}2QmL9YQtN?;YFq50 zz8%^X&j+9bo=aYO|JF5d-HgqDPQ*@6OqFwLS!jjW0~7t#6LP+#lZP;OOh#9q!Q+O$ zvTK^ti6du*gf{SP<+SvKe63_F$1@e|6e%t}oea3x9=vCYioGIU#G2k+hy0~p)1koh5(bSPLDn-fSy1|OC`ITauv+<&%^90dK z)+|eFZ7mNzLq;nm=^q;j5`=!Fmn!6Z%xWjIbJzv^tiz;SPH;Y5ys*GSL&e}H_Ew-k zv2DHCoy)QNy?7e;l3r`HZ#SaYj1Pf5kQeTg5NkuZ|lTXu~Oe@)g zcR-RI>`dcctpn^QA#q$>E6d?6TTD}rZ(sXX+&Fw{u)TRdr6c(f|WQI9n$ z&3k(nH>Mx~oK^17m_?0(4TZ>6Z8z#03z1=5!FsbtV!U)dz)%cW-=u^IRlZ)y9_~A< z%7#sts#~Z{Ezz|mIh@Gm<|bH$8o*)~3aLgSA%TuTTNdl^wGZSLj7QKKR7B7g8($eq zw1heh+Cs3AUPKF_I1y3{N#fVIrtS$<>~1i=ASrQa%)MtBMK)(60c&D)hHP`^k70EP{m_0v1=lPsG{;i z(W4>i@kLwb@(w4&wP+i$lc2)Qu#&E#Az6-fHSTH;996vbdsc$Bv*N9=u=di808UzB zH@krZ3NSK(*drgb-LiWyL4KIzK9%{6RoCD7ZXQt3jt|i~savJ$k-G0`a%mXR2%NC|xpxsHoe zwZe$N;E(9LK+TP!1rLI@&OFciq<_vet`thkzv{#dT_NXG4wKY+%+-K^3Uu)J~zDjh36t4AH z2c(7}^=hgqrlE|c-$+$vOVlzVQ2RD(| z0+kJgVU<{sAy;k7af?i&1shSyWfbAH4OilUOox-A@`}*$4a_QILN;D>9Gf6S$zqce zq&al(uaL+2q(-pH9EBN0Xd`jjIrIpX5_iZt8NGv?CKB6J`P|k;b4_k0<$4`Pa08_-7wHSKmL$w6dq~}#(EOTt)CX-lw43N!vq|^~iqF#bqYp&+;|fey zzlRv%pZBl1>U@cBzzvO}xas66cO%?0<+JN+Pe5v1SUq||n&-Y3WFCG6baBtLS+4Yy^#P#i24PMu&RRqSK+VAZgMWl!s)rEp}1gA)blF z^aQpmB#!4gn=QDYE&B5QC9-jUWC-vxt&|RuL_QsVQ^8luBsxkvmmz4|$*b&;LfE}+ z=%}%HcysXj83xIhW)j{Mh4SzH7Jk|$cIMJKytvPp!T@_C6}S8SFWhlUl27An2;j<> zzv4Clh%>jebiATLlMaTfTEq`6NXo^^p|&)7SalY!)ZA zR!KrW>C7D+fR!OOQgRNhr-4d|&&TXsgv4rgflW>HQ|Fxs+Vb*h{^$o;HVYPDN!0k; zDEgo+3Oh&MwMR>adJk-@WZ4RWw!6WvQ9BuA17a7n-Nutu+jksUHeG%+&eF=>J7-?C z{`qX-!9$lNcmpA|XXyA!u}gf>BWA-G;zwU`2KSH+Jv?>V-}13F z2lg7trSC6tI2Rr|P#gO-I0Tu1#8sd`Tn7B%_;f9zl`F*WCPk~NWG1pV6xdG>p{Q~X zlu3IaM*$T>aXrBTlr!qf4%?Q@^bq=(54N%QNzir%{<-^$ht@C!2Z5h`;IhE6TTX8= zL|ad6UpIB*N9oirU$K}P+C$LR?E6U`*v95y^|Sj@h?;)a69b6kv6REe?Ig3S|Kr+` z*+u&651#%fd&@bV^SF>dk}Pl9^&?l$WqIyG&yUglL|0>*Skq~QO?uVw&-Bp#+TN{) zrob~2;S?pppx1)7<+usa1Q-!m^~W&yO4f@~lq?{0e9y*dYobf%scK+jlT8I}Klqt$ zAx)E}L46-qhz=4^?8TN;m3WMTp0BOPiOYE~E@OYtlGeF`P_SuLkfR1QD$oyUCo2aD z;H+|o#w= zV-uI8pht6fo5lU8_i~D>)x`x9tOCl(keE~|kqmG%O5PBR3QT6gEX4VA9gkgtaSn|G zA?hW(X5l=$cE<_9n@a`WwH=_E@z(}f0=?0R)V*~NYBeWH(ou^)fiOWe_nu{3Ra;UO z2x_Yw&IYmT?6F2GOETs66&$M@3suoA8t61>6gc9UpsqH;p5OQksr99DWQ|8iS{AJw zRzO2*AxIXLkH6$9)Z-6qoy(}QqO~iI51yJK&BjX}!Y;?MsusAbJ#bXdZqT-78^dTr zaPUsq6Grs?`gcQzfR`8|Mvg;?SGvhN{WCkW^PxooUzcR8M-|ZW0e}?dROK; zE>hJBBLaiX$vWPe8^t-KWGr?DoR!noM59|Cs{Uk^EYvpUq5aK36}VgUx6vbl1PI`I zFN4q*d5-DO4yI1BU@TCDJCUKF1{YZx>GI z1E4M)@Xc-4xj2&Rf?*Y*uBgHTS!9oFV+wKU373k2yVe6?RTNHyas;Th>nE4^VI=fq z<5J8uMSC^b&j{eO7r21+WmY=0cE2xLoyS^{xQo(m?V3{|Xp8S}s)5?I9G~&~Ce%R1ZPVyRF7qG;; zM?Qtwl}peTD~z%Bt~VXSLz(*<7oEZK6&B1Z7I;9nxn6XUOZ^9-4a9xqvfzoG*ba!E z8w-SCROxZ?v}e=Y2$y#_h%hRqWzp%-Sdc`~)wGdX4@8urP#WKE)K`dGftA8@Z9}{d z+CC~lTU5#(i4IV9U^VxjZ2sz$Re~*OgEwv0In+1ggIHHsJbCpr@pQyA6iiA_Y|mOy zeA~Ypo73R<*OS?~dA<<~1{76`SX!Ao={{P}AT3teK7R-&*3F~xwG@B~8Mbu1q6yY0 z2O)}?T&N3VCDoBKdZ=Xa1Rlt0Cu5~<&c=(5T?(R=tXY=U+FCy8%srxiY$Qk!K_gTu z{UGaX0aH?DlpttJ$=n)(wi&y#?PgicuIPidhl%V(@A3~WW3{oaD)pHwHznas+dhbr ztCpKc%er)yC1}e;58QYCe70pMAKdwt73e`{j+rDcj6M3zzxzS@A^b9b=NIoO85>I2 z5}@FxW)IUerFXqKs{MpzX}~d@VLR6g`T#Nre%v5WkbFGzYb4n+lI)lLQap zgCwA;+yf=j9>`HZ#pq&BumI&O_4VkMR3u|LR4!|GC1?vAOVD;-T2tjx5%e>XxP|hT z{u&iG-f&&I;0`Y_u6{6dt`gGmz?f)`{8C!T=Dzc#-=SBJC#+(b7(v^)+{~W1BxqT{Pa&DnU-WtXZNG|LLLq5Y5tpJ~&-bjZm0_X^qu zeVX$kRvTZ6r}uEV%1Ys!hDgasC$&~KW?a@9Eh@J*W=n#y$cn7CtNOZWQF2WzS=1QD zr7B<%Qy*{e?a!OM&*C;vqU^2C$fWO3d5)V`1>J10)j4RVdXy%3XVy>$Kx2M;90$E8yfBLc0m=@>cN6S2n{t%PZ`r2J(?q?lZ&if+?jvYeqBqh+-Kj;f8YuQxtJ zYJEw&hXdmgl9oj)hZU%WsG{;i(W46exC2|~GODa-?TRmqpsjRf-WuuBB0H@EfmkbbJ2G$f-wA4&i2Bp+9rFOEQ5A{-mHLkB*rTIzVBr|WR^DZqXG|twlAol zZNJq6x)ThaC|bG7Sz|1S;lw+bAS8cvDBrX-?qtO5SS*O8$&~91V~#DA4UVavi1PYm ze)Y}_rK_%&ZuVkEu`({C?wx<`)JWzdykU-KwZ?-?hwdb>Cg6p2*gqHD(J?UERDeWVPM1oDs$gk-NYSeEVLc1tzv8 zli9=lE@Pdi*&;qbAYiSe$&#dP5Vl9gmdB@rw(NfcXF*nKrD15xQbrLa_P>lXGJ?W~ zZv6*5w~ae$PAsJxBF$KOiKn!YAwx+uV?~Bss=9)Wgvwk0G!`Vm50zRQsr5iA%Oz`kyHQ`2)RZx?R^#^~0Po-w-@0fzPmCd% ziTa~mMLM0>5h6LdN5++BwjO*M+assDPM>Ig0iF(hM9I4{!MFPvrUnzBSHePgeo*-Junq_INt>u%>+#~wOMuG$pG(x4) z&&RCO<3$}i7Ja27y}U30pA>Tz`AxLy-n1R%-3H19ZQBCx&fNQ&^mSy=*x@WOw1X$1viZe?U-uuDT=@7erv73I zTRmHQ$)D+x(<;_dcGcox>Hbw;3hx#VF%8*qcp48;yqJp5riV_l+dwNuLR3T1qe;9G zzZOf%6|a<7N3<4gtCL0k$%P;Z6jknl@@Nm_D4=36uqRl6a;m;vUCc>lAAlPek{LlW z__V7F+Ols=S4Q7)f8&X6*7|6Y&GtV&Mcjo6 zPgrL^a{1f?v(Pr_k=(z=lTaT?4zJVq{QIlta3|Xd9rS63f8|rh9`1ONOs})MH$j8J z%YWh^XxlIj>R-XnVxT`bZ*3aHp!3KCk~Vs=p&{1}IQ2K{k4sNBfuKV^!WB>N;c}H# z3Qjlz#-;K1x*j!VT-F*b>XK0Hfz(+gpy=z>c1wLDVN*fHDHr_S&;XAX_gT!2*2~^% zkBY$_J|pnqd>XIvA!sY}6tq+L!!%hOCI@B$+(>I*lMfnfpuGfK{&|fF#1V~)WJCO_ z{Qqa~eSkE(syng!Ucc%2rfH!!|M4PzShJ}P;w_Kml zCYDp$0^6x%%v8+jo|b5|*ffcpP$`$HCBv?ku!)@Vu6L{Cs!u`&lDLwo*jt&}q?Ezn z^~Ob+!CoUa>#XxT=bn4tpYQ$a@yvkWJ2U<6edqr@_uTv5_wM^cWcb-wxQyGP%zAb@ zTXynll7$VFUGpGNJIi2y zGjP?7`00o0{=4XQ&;SKfTtVq8v5e9E9yveS7sF&vJ7f}(EBpvkCcjidAmm;QLLe&nk-Mb z0_2M@M6B*|p^Y-eDY9zUM1zr0`5FtWSTA)Z_xo8Qeqh5V_9Sd;Lit?YqeWL8iG z(J@9vxY_{}p0q{7)%|{NFJx{LI$e?w3d#&0<^ecLEi*zFbw#6`Ea*(aJgopV*0){e z|54(bA^gE52jzlDw2YlFXdFXaK^0ov)t+ijqhc!40BL3fVb#%6G^>t&2PMj;7Fu*E zTI@qm{Q$PvNK^)10c9&o#$GR4sm!m$BIL%wc)B^ z416`p+j!X`cSd&Zn@P4|&Gy53yF#CBv{O6Rfi*3iF?CBO$-SS)Tj}r_>NU>5(XRQ_ zuSv|tJHKs4;fe{!WWIbGp1|$a=BXAF0TK|r+YV3LMvmCTC45pa__+-{POyrX`PW8vR9vrwMO(AXwewe*Pvb+K$ZYzlayzFiS6>&D*Di zm2g!$LU9=>qGpxr5`l?Y(RHEqXtX$+im2AglobDJ5+F^B+G>?5k8FXxqYRqBQk9;l zP-$f=pn4WW zbFA8~AZcr=+dQbc+qM_%hZ0NY0yQJ!C|_+R&`}as5$jxWpU()S=SYvptAXSU`g|x% zNntYgVD+rgU%kO0K+r*XYCYGGt&JI0ldiRZb@6EN&}=vQ8`wI_*4U`~>VW77Es`TD zkC5g7blM9@#OT#iY>e&2qpY0U0Fv#XjY~=s+%!N&-#QAi*@1vRnt0?fQU57A9NX05q!QEb)YnZCN#y_?kT^ zF|=2`eOqEE8)@}ly=Sqa1*Pzn6*3dfE(nD~u$W6uZXGJzy(L}1bikBUyg7hRl;Ag^ zx4FM@%HU80;p~&Y~L)(q^YMI3BUBI4I6o#1B>}ndVGB@Ebu+{R4$-Pih-Qz*8 zI%Wu&X%pUKjWr`}{>Ow28d!d+m5lU2Vjx~(7&BII^PWCvJ7%u3)H)+3yqV)oyjU@j zop>EV*c8=Uh^9qmQ`c0w)&gemC}yi&98t+}!Nj#b5Th7H%ty#cVl`x_<^WJeP(_KE zirseJ5iI;(z}_&h+9%wP&kqv;7o-@HL?%fL*$@nU=bO&uvrF;6l4W#9oRZF6(r5fkPe(9k_x6W45$$37?mYVdums&3gE2?d>EBr0Vv{zNLN)giY zH9vbdax{PB^rQT$wVQv^PlwhRd;W&UID`&=W;|z8E|)Oqvp<`B2|pzN-ZKeaZW@Ek z)OL_Wx(NFC*{2rfx7r!Y6nppCOAk7?V;+CsvGZF{;g(-`?cxcuzrKAx+&Jlk`LVTa z^SAE%vtb|pfyBY{56$6Cl_vS}ZA*K^%TbyuG1B4SP?RMSvvh344P2J@zmpg@FnK9sMJOktt<@9YDbKK%N^zKdQIx^%<66T zpS**tnZJcpiJgqk`!UI1$eS}(@W7s@`)Gx}AJfIou!qXU%7(SeOv-VB8)shA9Mz~D0l z56Bw^D_hQ_;h>rzU{y$^Yb{`+qFU`ne^pa=;glStk_;n5T5=hm)WMy->Ii`kUkE9| zQ(VU@YhE`ZPyTM9Ch`vImV=V)NCoV)Z7Qp7v?h4VMK>_m!-$~)gNYilFt zZaQZ2Q_kDNxVCS4vER1mu;!t6-h|_}NzZ-JEM(>|3dTqSqhSbTnH2e3Dirax-qe^k zrxAPPL3*RejHs=v(yTfrk5gG?>(UfyR%@Y*UESw@G*U>0-(OJa@Hc}ii9n32Bqe`{ zhqXL+9M7xbt>s+zaA^nk_y({nH93b4z~|>Db7p17QF6P{91C16Wqk0D9KH;OH&6|O z^w`-i2q(`I5VdamRc|ndshQ`O$r!S#CNaCO{m%>^j)%aBi`#q`b&@=GYcVGd5uEW{ zlL%PVsxxJrA*qVjy_RB1Dki2=3C;TENhgZ8s26n5)OrLBb3M4NNbsiFZZudhMu}R* zVZRa^XZ?Qe(>EWvHLwu=0`TMWa^i5$ecMQzq)Z~Jrq2iLK1CjcIN^rghmKnkgc2CvEvjyAPs9oh@{sX4-!_8#`&UW zJEc&)l7N}0MAu2wxLOm?({lorZ1BZac65s7isKgAU(vr1nC zG;azv47!+Oz>fTCva)S?K2r8WE%)>~>83+BIYo9ClSoc6_y7Y_anlc;%U`-&;NKQ5_ubB(9t3@Ltn!PkRj3T@3fGcYrM51+-Wf_ z<&Q0_sQJ|%s{9CdT9oeh!KjgOqtdk&uu+O*t@cV0m9*t?#{%6@kIjS+n@$qnT9>f{ za%+WQ$SogBCBGlm5xN32@;y&ZucAiIVLJpIGu;Z^s|M%RLnL63;O#yF056;+Oc#7( z)+h6v@t9Pstku#pr{@U4*fci}QJbJeXy}G{3Jt++0lA!7Tew8{7a;UztzQDUv)m8V zpfJQ7mKkbklnD|WWpf&7?cYG{EYT#PtLi=vI&}qNu+Kd%P%{$JvF?A7kU;~aU7bsH zN}=;Dd7SkHwl3ECD>kw?Un?f@KtdNY=y-Cn6Hj4vue(qUU~7CWnP=do8E^l(lVT#-cUmj2rzI|M7+Q$(!Yho-TT`+Ar;TOBBruU~0Xofwju( zyVL2Oi9KD*t4QyvR8{wR(4{HToYph~*sB`RbPR0Kf2(puZUZsJ6`9(XsC3<_+$$xi zYSrg3<5X%A>CLNERW^#;T@}>?mZ~(av`$jPas0H@SG*+xCpvJ3c?brz(vs+7=1UY%O4Y0$+6L zn)%!lr`Slpx9O@~Kl_C-Mwk1Yb9fi5vu2!p{f0$I-~IYa4`NXGRy<}l%;x@kxn*cT z59H<;eIU8DTsXS~FUBHau?=lU(oY0gluFXPRbopqj(C+~&j2Cj&1qCDXIA^S zze(+?W0Ptg`1wMdYTsyng$y0+e`sdRZ84#ZDq7iYxK0@q^t#Xy_w5n+uO2&Hkt)lt zCU=lMd+AM;tPjD$k6&4|9j#_={X6sT&CQA5-}%Zudhs+b+M*m{cf&8*;;xANj?Zsm zu=GngoPmFv?%YhW(cGUtxeO~fNKek5pWxj1@XO~id~$2Sym21Ow+_!0yz4$bl@Ct0 zyR?$0iyxT0F2!pxo=I;n^0y?};ab7pZs96ZN{(GE&F*R`x;lDlCl_%(w?|PwB^A3$ z=RHzw8qc6SvJEh%n%0b|N!MDysuWcudd+V1cYs|zS8?H3H?nxH28%J{4SVp;SF1)Buk}lb zqrJ*;5wKcnW3{K8VwJ6kpt9BSO1Zm>X4OUVR6Xd{rBtewZAb1Y|6@W14XkL2OSR96 zD~W)=I{}yJIjsC`jcK5O(&tA;(gpTuytWvW)Q{=F(^FcT?J|oWem%@)J=X=*O>kQ7 z`U4TM{*?93;BK-l_h8^U^8g^Z^O(rUlrTVG#&V4#Kn9%w2#aJf33c@-?h9AT#zroc zI@+RbF{`xb7qq`=onR^$@zYVQ1xLWQtOW}F~YGWzSW%G+90W3$G5>842tgTh)^ zlMrT%hDT@&-aKsnHCApuLMwt?!RigjdE!P`@nq+m;JY_?0r|g$68xscx85C%(sY2- zfgyOiZ&%@m#i2Ga`8wP?fv+L}k7t3>wcY>o24HX&jbLQBgDUNIgQ<_^7TU5j*}w`X zw`M=c5L5+_wqw$$F4`9Kz}HkxDGV{^sRwYhMcV;Q;yJCNy2k_0%dT_*=NG~HN?@uP z3F(Mz@DQ3AJ=P3ms;hIUj1)R%$m6UpuywK4U$K$J`C2g$11a$Yq%4DzEf2uqpc)|H zR7j<(Enpfc1BynwwxAEGk!P~LI8AVXl4a}y3GUm%$ zslkuVb-iiHYwOsKrQ0$y8sR{@E>=3YJ!#i3+8TT)h?iLno~MQ27pEFDO&dncMg3fUiDqSd>C^D2KQewwK>yP3Kfbanll_Y)KcTXjSsrEE-~GS;^}8}>cE*q1H0(Y9|+*SprteLB*6*>{_40hExsGm%++5p1|r}ccGfV zWR+2k)LOtqMa5GP9ySbCw#CVu?sgVd#sag%R^o|0W9~m?5AgsSY(;Ch()!$2wCI$Akk|IH+oFX*l z&1qBwrPjYuTUVu7bxfX`2VI&X&1x-_F=zVxS6@ubP*$XkDq0B~F<}P%5r`4>tS-sZ zuic0EWhQ^-sd?+Mq^0@Ruj59CFvH~g{EX~bW=Zi(J%-Rxo|$!ex@a8Eky*z8z*^K~ z?nY)@d;HD?B*6wc`clH#z{cZO_SnTVyI>B1>;(soix1sMxY$BBf2hc&Ucni|wTggM z#fdND3`teI?zI$CQd9GU=6>^}6UAH93))2@X-$n--PIQGUO=@?cF|zL$YO24nq8QM zFgP7iDrs{?6ZwV{Gi0~1Omxe`ZvbxNUnrSS?% zlr2n)@pP@0SA&|=tlAi>URFIQOtv=yVfPTq*!NBeZT`m;DI|-@Kekep%!=U=h=JXf zAF2>cEH zUHU~^=BY~8TEGl)%;O4jRfe0Z+O^SNVd~q|Vv|8S-8{2!Y5|M3s0Rn2#^J;n7RjWt zXlq7}fPLB;7A$k%v+XT%9ZMa9Jc1?^)gmIA3s2^@5EY z&ew`$2qe`bgUD!*c>ppfQtIuS!V{-V+SY0dm`2KgqS3Am^jHaq#*#eN`T{riIV^Yb z?^Is2MQn@KGAc1!`ZRwIK`h!%a*P^O=efDOXqy{V`X85U|+rqHVczu+s`; z%z3t#;n{lDfQNy{SZ;+g4$D#LG7H)>nK|JMy$SUqu1skHtX@IWQvQ@VZOw$RSM*r5 z?OqzqWbh;>^}fxNLQ)BdLD6*Ytc&Ubo60Mpze%j1s=CL6aywbL8Jwau0@$k>(O?HQ zW5^3wUtsHEtyHA~sWrXo!C3*I*kE0EvV!i}Oi4|mK=W#qDi3VYXcTLxs3uTq($yA- zWVn>$*J^;8^9of`{iPUGPi@;uY;XwmZYFE#?hW^>V+by-{l=q-%P<_v0Jh9Wd_4E} z(0!A0OV;k>{G5EACit%AA}%g#XO`ur>yjxK?Iu6)Zsx5XSf=?(m@Kn*-}Z$uIeOv8 z&bqlhOd_NI{7d&OF5SBDwugW1XAEBpX29E0^MCTppA4Hpz@L8bK`h#4=9mBLk1ZMg zLSKMV+b4<(rIL!_5M&z4am1-qEgzfHs94Ud_OFfFIx5shOt8ONb-MPsF{$E{q z9kw+bwKGYasJF4KI&+IE`W9pR_fThvssJWz+eA&&+0| zI_S{Iosj#w-&t5Z?{n$b6GOTC*dLrUCozARcjHN0!cAL;&*8(ir;U&Koz|>>?n0c- zJC*WjIzD{QJWKC=56ctR1g*Im{T?lxYgZ3MYHOd zJWiD;+aQ&exz>!4lIy0~NXU=qe>74^md?l=YdR8WypAMuRAxG=z}4fA;p$UaTw-%r zM8QBn-lv~`qH;lpmEjfU-0>lsNuIRb-?R&tFLEEcXP=)ZaP->8?#A48ZC5=TjHn{tqK~=&DEBm}rkG4l~(UyrLT;nT=`6@|l}xQ4PFGMjM!S$=Ytix^hFgM9&Q zeTahfSm%qLE$bJsTB=vtQ%Oo<$MIEC_X`$r47jVA7 zY${MFs~RaZFxwQD7oKgeC;~q8X}aPdPWX#JQp4)Uj-oP8$HEnNpEZeNLQGNKX#)xb z8*2g6Rq_Qgcr`jT@m$-oQbT5Amy^J1mSC)&G0a$GhG%cwl22ueQO*}@SZ)U2+X#>$ zaUd*`#grO)t%9X(U8*>vtgW^gC)QNCF7FAdcjFgr38t#jwHB}*f284BSS734E&OGk zUZ}@r0vCMl<~$C>f#T5|Yo0KPf6~_Y`y*CNvVq%z^JSB*;Vd&j1NwoACvDfZAf?lG zkKlen@OI1Max#`#(}NWEBEmr)tys*(?NFIX|NITVxR()MTTfSe)J5_sXgdQ<=*|@& z_X9!Nt~=73r+F%n$)HRM?5*XL!Vq)JbquvM$^?mxvbk#i25M(%tE&4v=+qU6oSB5) zNGwS?ryTP{}E!RqYqop|l`PDI}$F>j74_!C9w!2F>%J z^3LxKZIWe0=GF6|EfP!;GmE0i85uKsr2W`j(^edx#b7PZ#v}$%>~(LkH2Ya zaXtC+>5})Q>LBN4Ojj!c)su^2Mz=>X5c@tz#s18_8d7bNM#fCBDY>gqO>0xqwHC0B zc)mlbv1T{=tK{y&DcMV<7Dt$u=1j7~Pm6O?wr;u{70}DKTmOPLM&TBVg@?u%>Z47( z7XnY(Z19t|g?r4?2HIXvUO=;lfWy5O_&(=^@|~qm;Vp|qTPFF{%jUhQ8C&>~hbL{< zaARZg;@l>X10db|FurNa9&P^-fBA=^OpG)z-02P*E&*kd$Fy%Ll2pnmLVHSs5!kdl zVNTg<{j1pSqFHtHJE&H+Ze2>XT%xO_!OvSakja#2y7y4@yPk1 zS$g=XW5yZU{sT=^=(~|`ws=NU_HY+3W#tcftQx!*g45pe*J%sxZU?k;(~-qFvY~Ef zPsLXdetYf`e+F+f|Ii%V$deuW`Mb>uM#IOD2pd+l+<&WiK6%;f$9z$IQ$gE#&fm1f z#ggsG>j%5vq-ut{IuWp{MpG%ykfit_-CE46L8@&wX`VC{s}@@d7xAPuHDYzQG#CP^ zZL*84bSm3jux4;ZDfZWe-A%X7(#!+AI6=jewv6K^fVP>Ct|0SyHclLhJ~(zD$}mUB zsqRF4=o2zY%2La|*zZDiBEmZDj8(WI&ewna+?O}ZD#!T!h8DkLSH zRG+${d$Z!oBVc6&8i${qP(mmfIAf7Q#B~A7Tg_wVMesbGkh(W|M@M9GA%i2Pv675% zpvCifhmH%A;togjIcW|Mp85fvCjgtLDEV&y_^iS`%$z^792yX@Ys^BLVquXi_G4-F zsMiHsm-+!*w8a};d@C(RgGm?DlgN2IY5O}EwuDqhGCK(rKK_i@$&&K7MYP2#4Qp8}#^wn3B#)y?S+sS=FWT}~2l!dNC6mFC zc?bI=^S6OgRbFA^76;0)jFUaICiSmJ?w2wPe$f_pcBH(_x@dNI*?5fQAJ-yuzk=Rnpg>+wL7EE;aEI7Np@)QxDc16%apsvJTbYo#g`$WT)Y>Xt?cMBfY> z*gDI)ROmPeHHJNOyYpHHMcH~@-d6i47%K&~s0JxDp_0+xSSge@)L0!Pg?awO!cO>} zv^DfPruq9TM9}dT#w4n97&?$z%F;Z;=v@Pe{GwpLU576|gWpW7v4@a)Y$3*y(Jf#x z7Dt#w0A$>8pCx=p$PN#%Eu1in#q=JwxM6C2&}5kuDE)!7>N)cnGB@X~>n< zR%ri#tO~UYNd?rd^}B`6(9%n6(vhuvs|7 ziWoL!iw%^ADzXe5fN=L-i4=L-DpLwWKJwALup7EF4SJN#R`V)QJImVrmpvYIs)|I- zOn`@H7m%geGEW`wu%@mkiY~ zYyY|!^UT)<_3MxtPP1L7lJSHr?l)FK z?t9{j@t$Oc&sveDn?cALgZ~1d%r?8cK;76RSoj@aySGWUC~~6jzj*RgMq=ANmoBgFltb-Tn2q ziujFp>$%UgvSrDj17njf^R;9T+J|Acu`Dvr;k$i5hmR2qgY3|J9pBb7=EZY(Rv*{J zATB_7g^pIa*umd?xP7*SZ>-`me|$<|2H!ss(0ReCM{!Om(q@3Kbt#H611HVM-(FEo zU{Kdcd220TY|msD=2KPBS6DERnOC;^4{84GH)2V|q+cH2hzqMG`Kfm*4Qvd0u~q6L z^3(S>@%;iUp$Kls22Jqo9Hk4n{lmoBAyVK;zQaR2U;U>qbBPDxWfj+vx#uElAl?8h zT|gMpAu|ZL-M!yItKzQ%hpGp-8Gy7B$`UECw3aSXRLUwsGpjj`IMN=p8CR0DHPtbB zf@<|Z4Rsg6ekj|H+%f7?MheMzgf3dyZT$P0O0mV)+e@EMgkDVD|2nt1#&3&x>2-$0 zj}x}kyF5-tCNU1B#ow;U(!D!B{h84|b|6sh8pbpO2He^Cv-5d^ulRiR7pR$O3Ojn# zJol9?ppSj)x87wQMTM;;>>a(lWKmqkvk83U+y`zI2jeEPJ8&~46^=}PAp%W`Vng6qz&9$$BT0zxOeJnA-X_2~b5>D;Z(z&iwE%O-ey@a$io$5m#TeeMDC z1OqvNYs297HE9hqBMutYa-{vT7Spv?i%wu<57ZS(%ps#aHCAzD(=_4+c!DA($~LHI zRvnuZR39Z*g8fhq_CFdaBukI)1y{<=(xaF5pLD8_{hVsctgZFBlu@M+P*TvNVb%%T zd5wznJ8fHA5USF_SSbUGYLKehjsC_;p}e8S>WFv=#874|-omx^*wDCo6q(y9 zQ&RhZlMG2UtX3H-ySg+LmiYwNv!S9rRq0v_SdC9jt~J{&{AHeAkl5fyVDjCce)4%l z&_V(O5Vg_zYKl9Mig(4JMH1pl0FV%bUf&{~eC-wwts&sdm)`NEcYKl@GrM7FN7*@Jy8_#lwsm_9yzS0fT*Qe%{OusG}s$oWlGC0}tMmtLJ5#3mE z5vx)*A~b(Ac}Ve9HW#_ODj^f2YgW0dEf8ePoo2gECCle}5j9=@&k)ejLC@E)h3Cah97-P`mB~2W_xEF2iz~&! z7JFdff!DR|-@a^}9wF62OCgK47DVj?4J!~Omzd6AWgAHrL+;gQ4KDvM1{xgmbwe7MC_j^7 z(Ut~DvCe;2E_wOnvsQ;?0(s0Ku{#M)c}F9PWn1C4(n|nZnVJaHguKSMVNE)c6ZS~l z*PPjRozFKI^PP>#k%m%TilW<^>`oCHPgP#9MgI0m7&g(hAYE$#Yfw~?=vBK#E8ESL zD3BlC;4cbeU6dpR_mVqwy3FfXGLB$ z2Ma@0i(wbdt3y^1npriwF%*GK5m%D5HPx|6LA83I{&W|?ekem)gfkka;#2-dBZXu< zvq9Q)TYUvk!?^e!xSE*DH(vhq8s!d)w%Ng&N$Y>q|Sf#Yk7b#Cp6W*0}!34VwG z$6dZ!78Y%pWmEWuZQLNX*!Dr(KZs1%B}3PJTdhq-We2+!; z_HT@X4)`R>)i(*i1as~N{btTMcf(umhCUnkTg#l}XRx99+}K?#+T!ThFXd-+xU7U@n?gs)klZwaz%HV@Z$8VmVV+Muph7nUdNM5@blK&5NgDnJ;j6 zl~lAxU8^k)Y71D0Pfe~h+b#TMo?h^pvy@Y7Vsg3X0^igi#Mt5;s<&cQG=x30NCR*h z=cZ&5YZ$lzBV*mL1mL5fEZSO@#X^!4eH&c*!Yr~W!OAUqo7a||92C)tO|&2^+VX)4 z%T&Sf9>u%_3>ISbfKAzA<5;;uXnU<+0=cuCQmDN-aM9BmE9#Gww1^C#wMkVEM1Aij z*bkF9OjL}7bc`twjBsiR1P$1+buML@6;}`e^5c(;wUDMoe*Y+b!Sc>D911Gk!SN4M z;%PtgWPA4gy94}|eUuQO z#@Ec?u|pwS;tS1KOx9)zx^?4}qMe{&1+vr-t307pl8Pv?rI=EvUODBj+NG#P*#biQ z_o_6h>Ors&EjL!we#p=eZKQ{1*Jc*Vsz$&RG@v@g1>6j-FakI&w)~_m!iu;4%kbqz zTY%+F1<(hh|KNk1zFYjH?G7qG_f@?sqr%v@LlMi1w!8 z$lys^v|!(U0z<_rS9d{59=Q<~ZCy8WiF*2tH3aXW@ zN0}#wK@-Y&GScUNG*U>$Mh(rEK_33FFj1+Yyl8tkakPO&TSi}=ypv;kc;V&~l^nGy zv+d9wH{Oezf=?u8KYbF94~(`S{=2J6?JNk2=lr5Ar6&eIX^VVLp7@h3i;HIbr0ubE zEjQ1-eEVm-El!?MdC|7wb*Dd-iK~ZmM!x0|Soao4hr2FO@%7Rpz?9T{5FTq~&X={t zwa6COJIZmSO|+)cwH7c@QK&WBjsB{pt^&6db8Iv|W%W=El0X-(RPUX*iTVm zEgx%kHI29dUVSaE2HDgksHtxAV35j*a)t7HwrD%ZTT@KhdNL4CVgkvkA`NrxoMDKS zpaHx!X*E{Lz@i$Ys&)&1hgc4mwM6PM^9D1IMceF{GY$vDgUn&5EHaI)I#sAXISf>D z7v4LC@o})6nHR8n`k1ox6nS=rIVSkSeHS#Z8X4CG1UJU)2I2L{KC9s#99UpH9F$h@ z1}FFHaDEUty5dFKLHdpM516%`+J&$yAYL0|{hlTOc0x~A``2^zY)R>=y3d0iZJu1q zOzs5_J^m{hyhYPW)zC^+hF;_z26U|+2}9SWSOnEIr~SZysbV!V&1})O8W*!x+rNIhIx@Au>&&;=_Gk_>9zLDtczk+rJiN$4kM`kMrAB&mJJ9*B7hEsL4?M$l$xux( znbFH#quDtq$VFeNl#ODV6`FIT_$ju?-(D&5t0rA-fhbT^JcS}vtCCK42Nw0%?6REo zr!%=8>+j7vx>GjhVn=!hXQ}`N1*?a|5q6Y z;7Ndk5j+%R`^Gt?rM@i0Vx%P^Lbb|UA}OZ5m{M4adDSjOMamWs+P{(9RdGtJss>X1 zu6fXL~=zA$GFjoEt{-=04rlzOsH(xqlae!$}O$YPfTc+nOMPv+HJ)ZhrZYmzOy^DX!p z`l?1i`^~D-I71fG-vD!UDT*?+*`#gKiTv#q)dU80jg+_60>;K9~^vBL^?7c>5(tu&gZF>fDW=yub+9gK&{OU^+^At+WDq1zco}kuDAnq{I>_vbR-S zB&d{CgvPvPH-;pzDdI|!wx&8JPf#6uT|Me5g8fjo9l59ck46ef-+5v!xYA|%`(IN7j_MNfGOJ_23%HciX?%<4B$-nk$EXV>h<;pktI-v1gS^k0n?kGQ*PtKkn zn$9leMcX{FP+_lEQrNVXUQ|7}gfoBAaq`6+x3<5MfT0 zuC;(EibAc~ZuFO#d%?#h_m5`c1*>*+>5Y3EXN<#>wy#MK%;@AFk0t#n`lP;%7FhX2 z-}W|-VV!;It?L-ZLx4OJp0s87XgJ64*w*dHO#a5PxjdzNFOGj)F8;dr-v1NK{?eRF zw>IGe;2xYvPfT3%WK=gGV%&FQ<wCKl?bk=b}2N6d~*0s6}+B1lv!Kr#T2VjMPe$+s;tfq zQzs^^sv{w20HP*cZ2=2tV^Fia3#i&H{PonHEvwtd&r)17Hjh1x{FK)tr+7U-f76z~ zzU9OI1Rs(RWAJ;Q@bfp7Z#eH|mS2yIRQ6BW_80_tn{|En_;>#gNWp#jWv`KUIv_h? zVf_*~QZfd2Nn7-&cMq?$7z00k5eM6MWCZ-ktXg0O0rAuI0F9i66Nr*qju`+>wiS|M z+KVZL+J&Sd)ilxs08QCy{o8J*L?NxWHL2!7NwU3K%S>ZxMywZ|@?U)bwIG$Mp_N`5 zTc<&uE!xJAOjRT{%f>I-+S7Z?kU9?KC{G+RC%hgxb6B)J;N0G49!{zh9Vbu6;noH+ z>F_6QWspDxYs!r!6a&D)oY~zJ&fHoqxrbRCt-$4FKY=~WDZz`j%rFdQPudQMQ@AiW zTePhO%hmR;*KT|_Dn@GtqpLar;wZtnzvQsdyBY+6T`+Ek`nHe-DdN7?wT*`#-0I90 z27SO9_hIpD%|E0WQnTtG6mZe#vg-AZ##><QefiYP5xZVCOGm- z-)Y-ACA2lE>H)Q>so=#v1l11-hcHx)6w0bbz#1i`6IJ=3_9*Z7X;I3PMh{&h_G%(+ zjwfxMlM_z!#G$!q^Pk8GZ47R##7=ODdFhc{d)Eg^PEI%}ez6>1_2;0M?eG%BA$zuBJQNZN7 z6h#^BMW=|iNhk8RSBiX4*GPG5EnsX+FsD3KyM@0>?k=n+V?_nv@OOfrw0&_G@ADUM zdw^3nhzplt>{(J+TvPd z3+x?b(8P&)9@Rmn7u_p@!>^ntsFvE%lM3upfQIm{1$ zA15BB2*$rOi8;VmZRcbpgK`h>6U;$F=K_e#7Hv5Q-7rydD6ie3ZRW(3H9qgcwGUje zI6{}!r3gvxVMJ2$yw8wYDO5R*T(Uc8!$%MgHR)Olm}gZvLzdR;`cFa!p5C%8Ho<*$ zfb|5F4}b-xIRMPt2?VN*J)mLhlnBJ&ElvUe*syy9ZQR4?1yRbl;XTY!qAj+@Ckym9 zwOxC)L;_E23R)03cpd4{X)E>b4cAJxvO#l`TkhmLa4Ek*j8;&HwrU68WiC zMy<2T)ro++I%*0nwy0j+nyaXb6GH_%+j#{l~{Ei^|Q4J ztg76W7<;N^cWTn*7KoNOcgK|qQtcucb`;lNaBQ4NaWkM}(_cllD_&OartoJDRxpmY z9)ZVk#Ebk*jKdAhQViJeXL^jD1kwHx2H3tg>@-RyJg+U5iIr++Y;t`d1Z@&pTM{Zc z7SN$AkxBwh)gZyNYHvD50kliK=Ox7&WD+Ln8?E&hPFdQTq^bj3zd~^Mn5!g9INks{ z{U>4Zo7ih15R5J<6fT@ySXB7vj#!Y$aAr^vO3IzV z4Z6S%f>q`s-l%Iqy4nI}@aIqtm1etzzs%eVmDuo!3moua%-lS7;lR2o2|mRDI0Rr5 zL^xtuR0E*w-NgZup^3PA;!QW*GQKCV7RxTm1t@mULg*xHC&o-N)aggCIZ_XcwxT#LGxKrr`CStB) zN5}`DK5;U~G~jjQY}YLA8Z-E66q4MOy=4Vs-oOXZrmb*DlMqHv?%6h7No3r(Bo}&9 z%QC6N)m)W+Dl05|+nh!d)}(B;ylS>l!}c|)>OoDoc{haAm)xc%BRUKwtfOpXjQya2 zY0{_(*OZH^0g3|$WAcEOd9>K+u1!gmG82avh7n1@GcrSJrQjKDAW(^~DqU>>v$=w| z(Qe7#g0rKRvBJ!I&e}5`w1zk0esF+s+M<-}0;!K_ZpdPvphwUHHsDo2Z7DJVfoV$L!4t*E4tEz~JnEw2iC zN3E)Qx=A$;Iy4m|%}hxP!B&mvFtCMyH&RMS)c}quu0o2`z|;&mU-0zS#*ss%)+1uh z*E%Mh$l6m;P2j2;skMN$1XSB(H)f{cP>oHBXZ1dP-y#zKYfIn!f6TAs_N%|3(;+_- ziq;iE`f`-R2FmIq0hHGX$9zUybk_(C5<67#|d z>*g?defw{1pci~nJbTib?B<_b*OrN)_6=sD-#h-&?=nNRJIj&Qg9CWhy{4iQ{C?+F z^P^B$jd{)PBM3PZ?i4$yP)*>i8L75Fbj3krRkfy^N|Is+ z7WLRze!~o|`Iv{EJ#H-~#g8mwSOBbyP_8-NFyMK0e1V5d_MOM!lqLRVkQ2(#jaa{Y z`{6MD+>LP8C4gX#La9Rmvi4<5` zOB*RFRf~Deu6AeflTH!ZzfoCNg_KxREkR;Z%>(7`E`t3~a+n2bM(X|twwT)@ROj-l zX4@-?fWwEbaC{8Z-->MVY=!s!+3bDdt6iY^qrxzjIMf^O_iDxa%DOofn+ijh$^hBH)$W zQq-mVv4@#!Q&#h&6UAH93tBayZk0`wuGRu3_Dy!tU}RL4jfG<@%zLTKU*EBoXHttr zm7E*3ia+efhKp~sADVAL0&M!i6%Kkt)7H_lpsnhFl|kN$5Y~Cv+dOyvtC(;s#Lu^a z{4Y@4X$g)#Aajb(E$~*k(4Ht!c1haIe4eVLU^j|1RVX4=$|*v7s%96l@Zhvmgsozg z*itmBj!||hrfktHIo}TXpj^xTI-YsK&^&4 z&|AupBZ<{2=omD%g{_Xx95AO2PvMqpUhW~YX^nLm+{97v6x5*ftH6h-o;0BJ0!}AV zXalRmKZX_AVgu!&3c6ROWtkLt+A32DHAsBF2q4%E-I)YE%2vy(KR27JX zkTQ@s&9$15Hvf@E9)bqmD<m5CHDBkB*XL-5S~$ zxqWc!vH~-90QxUWK6Lp*|AUWNs|kP|>k;Szfr6m; zuA-{C&x0;akygu0;HyTQ=PcZ`9#Kv$kHL0|D^lY6=F}3E@A7i56higdI3iSPJtFin zM(3ifjoe)o)dZHR5z@evMngdLF4|I;!AMih4>N)in@!9^_b!f3r2i6&wuhT$Sr%>4 z>u@AA+?QiMEM0zbaoyPLx#!o(nPpzI4ePP2uM4DMa(C1hpWPiKMH_ev>`P;eQu9Yo zKmNZvXh_#zI`?WkuIHZqpMkfjWsA>l7{_7cmh}%VhsSe|-+qAwtKG@rV62B~+asyO z5jdyItGj61-z0c2RxjF`R2>mcxw{L^%#fjNMkY~9)d|aS^qEdHIwq9 zEq-q@p$FEC`P0S8JD_+Wd;J$#mF{x#f^MxpWE5{XqyCSK-oKSz0j;vq0^2k!xOhD63y`pI6D4jGV<)Rv$ z_pBl`o~pcHi~Q{s)r9wi*QBd05Cw`V61{4d+O0HEG&Xxev*srZFWN3YfVVZ_%RdX& z*gu4NxQG7^JcK_kwf5?_8_Pq3zxZR%V9}O@*1HJ{IM6ya>r2-4N-#r$rsGRLDb9uO zTo9+W&wlehzAbX=uKx*Wy_8LuITqgdXG6xUn5Fq!<+uQ67_4l01C0S3SGJ9j64erk zDV<;=Ri$eAShI_8dQdiwFT<52ZB2FbyXJv6(6bf$MTYteV40ecy8jgQmRnHgicGW0 zl|*3U>?K^G;sAdu$;htZ99i~MS4bt^b?$9n%N!~Ry=+q4RrL)zUZyioGoYij+XxJc zrE{ldevjQV#5YxBS+e^yZtlQMn2CMq+>M09Ie6c@WBSO@8a=#jmb;XdX_I+9mn#baXqlA7@B=6o;my>hlDtwzf%UfUzRkt#Yf8S__yMrz}#|n%(HHlDiA%$(c$e zc>j#S=k?r}&vkDot{ZFt%|0D!$#d;Up1V@>7(=Wh1_$*n2<|4)_5jMIKe?6rnM%*$weDflU!s zr3Mwvs$=p5)yg(VrB$v_hG^I0HsyabQb-n4Y;2`!pA~~6Pz;@IFY|ORe z@#;jtN=|S>Nr&$Tt;FdfITJ7)WnD^tKS9E2Qis(lpM9#_=a{0fw<)7Wjns7yEm=r-jAO$zRNR;zeOE7+|!$B6c&oMU^ZFhN~EDjp9<^Z=wLD}I3kAv_)HbyaGa3D&9+=Yjw``^65`hw-*z_?zzDaL+2Om{YuH zTSP~snm3e^5bib)nze5n{MxYO;UChIbGN#6`UVzlkp#{hKyuEf#jWdiq^qp;+2o1b z*sr`+dtD55Z5%y6|0QOqc4s-#^#$uvCv<66S~2Z4=VR6GBx=+K1cYWrBzINDO023b znlv>cx|As`*bk*?HZqB-ri?^M^kbbX?$0W{5y(A97)7{k0<+-RPbY56@sqX=hlk5g ztoUS;tsX5{j0ejbe*-KyuARSOetXX(gP*ju=r=rQYjC8s^ds+4H=wW!9PY@#7vq!B zyUo*Bv<0gluNZFZTf!Szv~}AfyKg@c$Xz;_=05!F^L;!s`gM#z_2h!0W$o^`-&L8C za*=z;8Bb*HtQ4a`T?iE#fW+fRiU}m5CAU5Zi!Hm*C4kww<#|d2#8RxLQrJXlop3 zdYZ8Jx*N^zi-G~t;_nUr2%BNx=5LeZLajT?C(A)|EYo4Ch08`>l?s!k;%jze0K;Ua zh$~6jn(El3ng`Lru1c^UN<+i^4{R|*MQo~-s%%yaj{wzJ6XSS*aQ7QAV$d#SgP*j`M!Qj2a%pGi4NAFNpU0E%I4S2vTTUD4eB_bkCvc6!pTNe% zE!@Z64+5Mc>$&70_8HSPj)2Y!PR;0C=VxQ!0$#~2MP16L3NzQHtlG?`(@7L>Q7`B) zuSVB`ky;Cwxo@(I1|wsaWmhF`#9dyrHTg+yMMl^FxXwzsWEjbzjvvDTkZduM3kMn9 z2v#q1f|o=aeD3#_a1|ST7Ak!kotGM?5{CzE`>I0sooa- z)?tGpO{JV7ytj3`nns25)w~MAQE6kPS#@kuP@-(nWTP%c+FBW+-Rr*^F(znWMbV_= zy&3$aB7g_jG%tNvQ(|=$R2W`l9MjNw!iv7(9Cpepl-5ngKTbjugI8b#td4KFJX$Xqy|f9M^*fft7jTX&l$_q%9-~_ONJc{J}PJ zso9Z5TQd2?@KHQQwNE{kfYDC;V_1on>80`;TRm z?k}f z|IyV8TsqGd4vV%Ks93ZGZGc@glDqBjoyi=*!fQkoHhq8xXfGIU zZbGjnVb090IMH6>CvZ0{iD_KqvKYx@`0IqHbK|v1lhkp>c<>FCIw>lYo}`_nw6w#8FrbCJ8NqME=`HBxHoU(-vds`E@h4xxOB`-!6X8 zN+PYo<|H}xxjE!bztrO+^Y;03Kfb=1eG|{dCT44Nl5Tm}%w^E^QxD^{$tir|MO$d& zFj5>4jBW*sXCNj_)lQgNV`W;k?XeSz;lNBSFr~1Tk5#*qs72WVLNnt?Nn2H2Bu~`? ziYB`%YCmMCF=OSf8ks~LRU<$L4X93WMX6b3U<8Pe=K}k<40UllhqKF+pR_%2nZc8` z&AI7iTuLis#_Oljl;la#{ZJY70a`97I<2Rqc{u2Nt#1jLexE-eT4;dinLpI3)6-t*CSuUx01n zORnQaUWJ!%xLmRHo47S8pt?&NTOmi;wQg=t#V@G|)}&U*Q6|f*4(ACLZe;mr`#eVh z2!*5cu)XNdKWp6y8T|)|O)DYGy=CM~S`Ii->;R<35liY5<6Hn^lwa6GC zZj_wHIkFQ)ZCNwoSIN9=wi26PdLu`aguQzcZtVbXj-RUsvar)FBGfm@qOH+o);wKE zaRQ1vp$}ggH%brd;d>fohah9%hA>|po?%Tok}Y>6?rYAhnHIc?Go17W!0i5hM~zZ4uI@L{{d-r~{{~^z z(NZ+4j!_Oulr5TU(I#lC#89>!xuY_t0%|07ilC>slzCPRh=3*|1y;Q35LK*t3L>DH zD<-HF5||>!Bk%@vrSuo?4=ib7xjImipA!;bei!B|cq{TdBVDxhJV)DNGMK^lNd&A; zx_X@04{i|>b1+OvZ3a=tsRIbBRX+QIa$VjNj=qia!{iWyL0wbnS_@c@)zodX8~yDw z>gmL;@We(fQg<8jMRqh|87>86(i1&g-0S=qvsMKU8?CbY~s0Lb7; z+kbJ(CfKniX-5M@baHo3!<$7MVa3uq4!F?ZAis-0ebSbHj1zW;gP#YS2&@D#%Pms~ zZLjr9Aa|Bi3N_{f7d^k97Htm^5jpWoLk1V*|=zn4r5kqd;nIk!_V<0Dejf98~hp@|Dxl5yU+n%=$gy(O<3S{f_^Cr z+gP+cacZ=|i?*0tAjYppPBWY&Ps~X>5hZfQ?8E55(GR2x6Y4_IW4@uH06dk_leDvx z)>cd@w8|+nPi(sL*g|JuQ~9GbNx}<#ZA}WQy$7XsdLJ6M>KGNoVg46ATQp5aAgi*4 zK3^kM+qHUBmzmlhM+^=o4C}tYwt2N`iY@ZDS5y-is?xOVWRjQ0xW<)QR`YCf+8jJ!5*(3v zw->DW0LDB(+c~wy%Ct(`%bmc)9+*;C%g3tSNz|rn0il@@$z7GP6052UziS?Jsfx5< zKa{4~$Rr9(8Htj{OmRi2S*14u`Y;||>oCXDUw#Wd&b2fq^X|Qb7i}S*T;6*f9+NKv z28rxC-a7m<+wQ)UacA%UjMA9Y0T`_G!hiF^kK!i9WaCwDJa8Snk%U_rN4#i@NBjBYM{2K*dm&|Y|lqdKit-GR5<7D^Q=P?QEQK3_YFB&~G zHYsL?+s|T_apsg}sXwK?yyIe^xS+g7cEtHm|>s6-+FLgS_ z*u&_xe$kdMP+>PCYyj*NTdxcclUbmQvAzI(fZfmrm!@(-(G8N4fjZ)|a`qreCf*%Y z=HRMt1sqrf1NMlEZg7#Tep5sQFBuWqtfi7{Zz%MllFS}MZ&T~cg! z(X2Y2W;&HtwsJ#T^;)HbGDJJ{Hz|F}e>H*>Q4TJqxJtBH^=J_wj2;Pc%t|K;u-h~i zJ(1)xu=V{wv5!QsZR79ZKo+ff{@96a0*YsDT-s*$T=0o3_5hiE`mq5Ytg425ccIVH6jWE`gs;0I#S_B3HOv^+S;oF_S`eiB=xvs>Xt z0(imF;)W&(KyG$%;Bow2JsdC7RnKC5(YMVU9ekWVZZIXizmq{sfr#6?9$42qlqAek$<`BV0oIT7IZ9^o& z5rjh|fRtjevXxCyb&5=VsmH@oRF&RYSWgwHMMJnH9~V{a35*6eH@<^EnOVJO;Ur)*8`*`hMl_r$E@LR+FD4# zms<(LlNW7W?lWq1(wRj(X$!hzmR_L7MO(B|gU<@UBM?eYYB~i`#!{jE1B@!PO5_*- zG+<74WCrmy>kD*&fH&q8*;7s&C6bZgz zVht-T=HbQD2ga4I@$&3SCjAs^A^wN|zsydI%-!s^HHUmetD2o zzLX_=YXvM@9;L8rvEkROdVJY5`x6I*)Y~^!N#1c687bD{Y#P!{N#06{t*PoFlC+lj z((0}TOuMttsccT!u4a=e9*`R7Db%rI>{%7)@n6YcE}B-Vsw;)@+AU$5f#Qq{)&6oy zY9+{6W2LI6;LWEDfw{A^u|2`H=JRe=B3E!kTeIEhZ>PmTi1LiU!S zX1DE^TrICev~N>W-Qz)@Hlc@*x-78QjI{aR*eUx#NeBk-bJxBCVc2i6tKYD2d;X#2 zo|?zDhk0AOCh#?vDn&|-GOolPI$g^^(%vdDHdLn+ zYAc%U+NeR<0zz#?ZIQ2`(yW@NI1g110#=DFMQCd%!^j}zSI2A=uNnb5N*Xi86{TjC z!4b%}JnJrDO!5sAmX`QM5vLb+--f$~Lb$(mpDB`N86);(eyKU`Y1}^T{(tt~HO8*% zIuqRY)Me?Cq0B2b-JtD+*`z9&ijyDZSW%n-jcn58q~Zw>I*^k_egs#sCsAh%B$zQU zbn8bJDcUZ36qtE5;2+&aS+UV-V}N#m#$X1Jfh)(Yc!JEdCJr#dAW$=%#{@k=i|$5S zJs5X;zP0za*LgoEmL$`zP1b&__g?#P&OPfq{PB6ZNn@JQ?L-z&_{GU2CfwQh34A$z z>F4?~_4vE>%PW+)oLo?zf{)TY?g37>#tvzRsY$&HMm4gV2nkzcCZNBg3ly4s&MjzZi;uil&SBJBCRZ@732)``v%=5BG4) zy}kbbb~TXmxnKOgyzMA?e-cD{@pk0*%@IGsk7-|A=%+0)*PLvB9`Cnua{cj_^!igw zA;8MTwuYjZBv%f*oO-qGu=RfH$UAr~Ou*a8k)0P0v3==k3=@xBWT9KJ#gQ7Ar>(6EOc7A>KnuIO;O-adV zkEWKr%xX{y>pZO6dead`vhA5<-9?j2N;0A-ClHZ@bFOD#$<$S=SW@F|_CR^r8PvM< zn!Q%((r7Rh=Ux25kIu=r_N(3ICnv5K7@B=_<-l+Q6J}Wv(FTB_l|84d$&f8QgBCz!$FWvDTPdZ>OM+| zva$(*E%ec9M?qV-qCPVL@bnM8&gn=p;5r6{944%!G7J{ZQX4}5?`BMJAy>!C7T1N$ z<7szy@HB_{GWAgDt*hCzdT=oJKxModLED83`~PU!C8+9laNeO_Ny;m?<* z&yNLM`AtFF2;G}6L%@Wedt4Gm&^Eo#sbuJ`;dr^H_d=rEOZ^nzX*DoGF$Cy z5Y~k#IR$OcNIo@JJ%EY0Yf;8YJ=B4I%7GKSxkqOnf}CkwMR0mDU3mWdKwYnZ>sqEX zwJD`&G9DAk?V*xf0veA$h|`3h>ak2&9(0yONrj@nN`Y`BY3kMrp(OKcTBkA~cFCYd z)mf=@N%12V_)Zy3AoasBOx;R+MrY?Y1|^|eRK_)0kx`06ATW;|f~-3eQMzlKFI#ze zzF1wvbzO&`Eh0OMQtjqIx&K{`>eMb#-^Fkk+cpGa~G;$7y~GbGQJ1xZi?E+G{+nJ}+QCN{)Go%VC z0S5Axz{Y&6>lKqkvJBwNF!WF*5Lp)uAnk5gFeJ)wS${5j{3gcGQevE#S4}Ew-+PsV z*Ue;q%sukH|McJm@4S4?J@C{IxPvqQ;p5KVoUbm1`3cO>4Hf0*;xEB;O zlr(yv7FfJ+tu3Uw-uUY;!Y9nygsK6fb;H$L#U_kT~wzkHRbFL@`wuDFBq%bEO~bN8>N zaQ(D*fBEd@SJl`JCwhhq-=4er4hRB&Olhnnx^WMX5TV0akv-NJ&WfkeXL=}?90b@f zp4LXv7){QshTc}tvp&ATqzzTNMO&9v376`;Xwl@!};M}_?sL;SDa?|xZauU zdlm8_9B=WYt(-@FoJ%$7m#2|DzDTX zQwlER>Uh}*KIY4BdHO^FIRsx1rjN^3il)G9Z9{Kg(DOUzN!w}eJfboWaAx_m;U5z{ zu<7MwUB&t05s5=wpXK34bcx%MfkeZ_yl`BoIG%&l50ew?UHsiFCGqm0tXFH5O}z>} zs^1eH2(*%;s53Do9DxpfdcSntUKmb@X`Zz89z>u`%I?iBkaJ>@d_$)2yK}dGaYL|*tXFx&%BY!0$%t4@AA;dgg9vnP1R8WNU7cGH}`B>L0CWvGiaF|_cSYRrLDp`Ln z&D$gP2NPUTPuiAq6d~HB zq$h3n-JU=D`0p%=U3cro-@%B$|1Ul`ZM{HodeRma%F8c4SSlDY**mYN0Oey84i~$h zv7qhV5bso6m`Zp=_o{iIJ4jZK9*rt*#+=0FSa-B-CrK>HMm5-XE&Nv$;FS_!+W~ zF0E*i`O8e~uVnqXG;cTj*0SG}l$_S7vX>Rb!a5Jmw%*ELK^5Y@YLhDq1wB!iFPcKk z?I+ff%_#*XC~1-C$t|hn*aK~q)o#6|z2qG(AWlG`TykCtK@G1a$5*V}-{4~JrC_7O zE5}Q>4^r>|BhI}6{Gfg4#x;kRiOVe859mOeyYq_u&>p%2u8qK653o2FLcqy2g0}cc z>()5v7IQB&FTOUJy@(E&A~0+7tVBlb7n9@)$~>Blaj8)BR)b-LHT4;ik9l(%m6nq% zkgP-yFi?2n`nuGxU_erdqWYvM$`S%h2P`>9`9 z&Te8I@#3)tZI2i5uE$c2DF!UV<&d7VoyR+h_vZ8YXAy1$A(j-LnN6f4`Eqe>Z~jYj zkGnUZ99%NO5YbqzAk_C>#c=0ta6zB6b-^8=7pi$z>2z8FrPXPv5j;(iu%Lp<8OmU- zV_8LwDoFxC)|ihCy+=XYQBQtr61*1AF?RL*w8Q($HDT)O?8m9AChtyO(X!Bt>B=l@ zr7EE~SnB#c6Qe%}@Rl<@v$RWmd?a;selsGaP0|6uZ)(+vKaT<{78{IKucBtqii0Wv@^q za+dZc@JOzb@it_$_C}3fp88Q!^upe^Qcc;^2+=jO8_T>B@^XY^2sdAyVGb1>j_%;}Sy zLoAB(3+3`!jcMVEe}N}$&-htvo_1UgL@HJ$EnfNW!28=;qcAY1`i*cR~iE zA(uD6#7)!a`zz&qYbdGrAPTU#!<8fyOU}UN#6o?8)wvzXv3lf72- zw)$xTSm-H|?nH}E+CGo9BWQ*nXg)ztj#lCE+?^)D-#K?Gmf9XmU%`{M`x3Vm5eKs_ zB4~TuE&skm&OmA^Kjda7)-QeWpTJAu{FlDxe#K2m zA5fx$OP8F(i^`9iO9xqt;?`_)?XJzxN7=-Rck_c!y!CXz6SxXTieq)sd2@yWM-xZ5 zF`N}ok&GZHMyi@AgXaPP(NoVsRwG5pcHj(ArpI`t+Lv!x3rhM z!$lHzc6Q2r^OLis1bFG>d*=ZM&%eP#0eB8Jt%W6|=pWK2{v%$r`mvylGq@l67VZOj z(i8lwB-ET_S}5hy{~u3aQukyBR7z%x8M<1p>AX zAN`pcw1u=ZN3rluxW&zKCa9+VgxjRudqr)D{6TP^rH5UDf0}kU zJ{rIYj*~uej%0WNMoK7Wtd188FEM5arj*jk57Q-N##dO%E9Cn&Vzc@1D)uQ*HfLq2 zk^|kGt(~T{xYA?+t&o16O3x;RldNPXx~mWZVNjhrlnB;zeK2+FHH9T%X6P!_2Qu4B zF?4b6vyo^SgSLA&osUh`q_;Z8B9&Sf%{DdDM9V7%CU{3~0a1MK@*&_QF8dC`8ffNY zQ{QDlc=1+LJnYh5AZ552LwLgW<>V6LwX-n=mRdCWPLwEWG_?fQtrZF&nKyYP%K-ZK zP`XsNAZswqot3B`jCq{1w}sSw_O}K_={=cj=&XJ3Rl@6LGKUdILA;_7YiPENL0g1_ zuD(mpf6LT4Yw)D)mUGt@|9wd}T+2g0-@1AIH}w^BQxbj;<4M~P*AQ}iuB-SG0#6#8 z(!_nzx$CKY_<3jF4`0o_muv)P4yEnS#6*Ntbk^ms+1Eb$Ig1Z`o<2ju5*EixJ9$#2UeUSGy~ow=80*Tdq{ z{;yA6fVg=%3KMbi0)n>FQW4g8(iSNw_Y8+vydD`(+S-Z@T6db$joKVdffV)O1kgO~ zoF`2#D=1?6i`LPG4h&?e>lG73vJ5!PE;TGLl|z-RKbO(Z$}nPoFrmg7Pp=3rXOqz# zRVI4CyZt}=_@A9GuDcb2w$~PWUZ1oTe0mbEN7is?nJ@|CH*M2}FELz5jcc1e@>YE>8P8?F{Qp(*a&Q z{#!ryk^4_xPVM2`@64ZkcJp^Yw8EJD1ePzvoV$8D005w#DmTXp;0cLbjo~ak4Z+rT z4!#Y-1o3O5>7I`by>_W!MZU)PnzW(HNSCr`^Vg6p;yAA>@$haXE&EMLmY}<8i>hJ) zr^iAfEMTBhnulB)FI!yRmTlo9`_e^-@V6C(YgA%#;3<+RqVx3o7> zk7a$n$>!%3200nzRi1hVZi?aVMaCWAFvJ|mxH}I7vd1y@66S8pY$fOj02h+Q1PMteYh0RhSK#MNDzJi}rt@xa}KFQqROy^3RecR ztfDGZUDeD9T;?hgT}>~CGm|I<$-LH)sy?D2k-O0YB@opyptrPF=|)q{H=9cC-38L&KpYK77*2&-M}jAO;?jjSp2&rrGFt1P7S7Ox zwI(xrQMz$lC@7M&`fw_Y&W|!U9*uFCBtDH(Mc|rjU3xi~a);3aU zo2Qh$FxuWqi|b@2U9%E*lfGkbCLS!aB+NsaMkOn&ejK_U0dC7w3-0VR#sCak}~B7e6ygm%#6rsN}I5A(o?=M7{TW zb=&N*e3R2C8=lpB!}-|99eg6eJGl?v+r#q>7jKJN)f%f&fl5HGHHkT#@bvBHzeHF% zIH1uOmy8}POMxWgXm;z}F}VSZ%_PofFSOgmpJ+%3Gu>N)_ouKi>NA6j|&FJ}L| z(f31>eI%&g140yMk~d1s$H~bXCAneK7V zGO+wk`!D`?`WX_h@R(l72y+lPoX&lD{h-~bnfuOC zsAf`O0y7uAAGTh?kZNriRJC}hP&kPqxHoNn|4uP_PzeLd-993g}EH|MC2f)68!yMEtS?#Qmg(0U{TM~viz)(*+Jm3PoVSBYWC z6%5eWvN|`NlHJ%kD&?|iD5>`#auVd6r=YrCA=G+r?aoT{L8<BBTRM*LuEHCTT#fly*PHyIEZO+__-3dH?WzcY4be6y8WvDP zm!uNLnVDT1&w3)Zp~QqWlvKy7at(4)e@ZKkY84Og2kEXo?^ftocqvIZ;{e#_FzI)A zkWR;@@LJ;3L6FF+Q&VR{2y6}(^I0M@9mxPJ{q%&s!3U-EAlu9{A4$uO_i!G857`5a z_rqMs;=S{^I$pN8?ADvc%Wk?~E;6nF6n4K44D*qr`%N>7+K+f-f`6JCdd=R59Ls_W zx(iP5K=pH!9ncF+4ZR%B-H1b$$r|IE(Sv0}G`rMi!Jw#&%r5ox`(*n& z2c^}^tVYXOYS3!ahnYS-wYVr05{Tm13T0BbXLCwnv%@Y!WbS$oRF(}vnq|(3LXoJq zv^RlA^6VRVlf3C&=cAZ+AYXWdg7#)A+@cpAaOd5bui-lKsd(g@x%&fP3%6Q`&NKHe zv?it9Z+vsZtzh#~a1+O|NjxCZkNzM9JU8TV5!wr0-6(F3U(`DaFZ)hsC~!0dP0UXjo))lIvSsIdcJEOZ+pt2$mL}>$MfnNn85l5(>OQRe}F@1OiHEQi5`D=A#$KW z+mkq8-goij&pN;PW49i~)bo*eIO9zO`kVQ=jh7x>;3D)e1F$P-{=%~#RTI$1hj8OZ zk%G3s)kk(;KxU!O)LSz~_I+`X(jlQ6zvAnF-Y9tnLl`H6?u58^_yd-|yph2Y+t zXI|cmZ%53!mm59>Z3DiohoJ4H;`HJxvrq1w#-*t@T-^oPxLz!L1cguC{-k#^fBU(& zY)#@ix#P}!@C$j?UU#yGV6A?~vz5$(&_W$9phNfJDrid!ZO~mq$|K)hi#h}WLK(Em zo5(v^N-eH(s5pZ-Ndm=Fcu8hz`zuM3fVIvoWU2TygKT*O(vZ`$IkBinc6f^#7V@c! z!3nru!hILJPTv)y*L#q(M;?EP1uJeBL0g62`0m>%7W2Q9`xHMRm0G<9iG!`PVcyuq zz@Tj;MbP#NDwO9V%ms5}YLDce`1)|V=!Do|;Nxh*53wX_M698$b3#zvT36Q_jE`g) z!0|QoP{k8j7hT%juwY1(;Z%QRhNiio*t(LSpqN@pDm@6Kv7xi}QRS6*V1b}5X1(CX zM(57ElMk=!L0g|M1g+g-fuOC|8w~Hm>*Db0iyyni5!BXD$`e`KW%uj`-XWC%Lri)K zfFzd90^+J&yj)vKc$Drv4{&w2cF0MSgxwYEHo1ZU8oNo~repN|6-oj@LrJ{{QGjh( zp7QE?h0uvb^o^;<@m0m=E0@=}lO_iS6}fG{=e&MPR`S_F4xBQ6s-y#nmpR>mFG3`{ zgArL=;QGzQ`PMN|Et{T%q>bUM9kByxa%qD=_)y^uSszUyyrGxFX`N~u%uLu&rAM@N zskI`8gb|lrnoEp*N+b4XGMn3xtJO;iJ1Qo7AY{sUs>uZ|SIW>gn2afT%rT^xX=N}qx%7SC zDdi|1CtW^7Q7*%KQ)Y1v+HR{&J_@e~2ZIYqCG!1TlWx6c?>rL@l~u|3ajN%E_%;5n zVc~vs?$9hh3!*k1K-f)0f4;dHP)kAEhfv}LPN8rJ+2TFr5iy*3cjLn!{qSbErW$a; z%TMBh%pe|aPY3IHbdrBJp!ARR-9sW$%(OC?c<9f=X-5-IpUA7K0&I;c^|%qKjC4r8 z7*%6FHuQ2hceAYAsrtO~89i7wM2}d2fg4X=y}9k2H|mCxKKq-45>>T&Sv3HD)r%sl0ZAo_`n^E{Ya{j(4dO}<$|_AUscyyUMk+0wi6Nh!T3k7P=hhUmnaZ71WZ_0e zs-a?S$OiX{2=+i*8D!DLhF-ImtRsa=zP=SA)ykn|MhXfn zhpukzn(Xyy1R%*8<2#}(p}V`(XTcLB-Ga80to;rkl9gM#U%q-(L$1EKy?)n~ zP;7nSYxprBZuXJ?iMJij_f9^H*|01aw4LL?tU=q;dy8{_ZyyKVOSjjTx7?HkILGPe zmCyac=RN`FuGY`};1&+m)6(akzUGAJp+?NT&odweE~Q{O$+vEq1W z`6ch3_Tj?ORbrrK1lOiViEPg=5PQJV`O*KRrG8YGd!|5xYF0biwR7LrwCJHQv zj-B-sP}dtwEXgw9?z_}$fvFs-Wc|79@mn@`cu-nYLz<6pJs#i}r15Sh|H2Bddx^0^iEhfAGg zEuhECHcFt!G_)t!Vd_!(_V57rh1L$q?T_%`zKWsA6$~(C(=6GIt)oIoz%-Q9dk{GZ z>N`k?i8n%nbX1}b<}M`EPtzsWV|j4;rz3o}WsC=?MVJd-jTLt~uhfMAr^o#1da>|N zY%9}j%9FMMpAkc%iKwu4WszZ`_?V&__4dgLNkF5290ZSQO4gWh9;kNC^2CTB{sLC^d?oO$|K;A z2X45K#&h3EsgE$dGXL8jI#U zYJOG#8WdRe-76XXPfCs8qpe__KDoj1aP@JSBwn(NEG}Ey(97Z6%|bI-V|+7uuxyAP zv0zYCMn;#S;W5l9HI($(e<9On3EFP;G81VzOAT6W`gFvRCY^4$CRY{;0Yo)U29j`2 z8c{`~sbWcuyV(O3WJ8ec7m6pR*=rTzy9M*Da1+QsIw5x1L(7-bvPCdC$F{<4qO^xQZ=!mLE^r zsw8zvs0vBWsQ6W>dQu=fnII)qbV_P^LUXAoKK4sYZy_ay0y%_%2zH&uau|UlnUL%- zyHvNJ(ogE@DrlHDTwra)exgBKcCAvSDJIpeSdFvMf=tey!z|^MJgr(Q5O^|^tXbhD z(Vf&3`haAUCQg=AnnvywRj>!z%AnDpZBXjb6eZ7b>_S?(%RW5v=)0b{i6&l;jAQP6 z^Mya~iWANB5m&&p_VA~i`vjh}-B|n&0YO`}cl+uSe=a9nQ1o!R8K2m3?s(zddiB8- zsKYP^v8NvX6uj;K7b!k;Qie$# z^6m{BukdB)FYydK$~T^3LN=$^wy#4T~Ar%35Z+aH?E=Nhzyv>3Dn$&0skS1sXP zfMo&-)UDoj_AR?zG##+up1A)f0GI6p7hk46L(mqlf>Y9f!i(0nG&@T7tOtaa&r|8y zte#34sJGJM;*BF>Fg>6ZSls7;wq%#Y13p3kfK4`aAKxG+t`C=?sH*^X6Q{xUHADj z#|~(F2KSV6_t)zU=beLrMNo}?a|2ewAbr5_nxZtpv}pnpxlcvx0{HBlO$gT_ItYD_ zWpxlLG=0^UK#ry-Lv)?#4JL+U8SqNG1bJf?n98Aw>K9~YhbQ%j{h6%7i4i1ko=w)A zP@%pFl&_q`Jod^(yh2Vt&PU^d=x`wEiyQSxTUm$(ZFQ3Fycpf>L2$b!5G;iTZSk>r zebP4QB*QcHSV}dr;YM)BpMCtL*(3TK!DzbX{YBWY<-9+TL@m#vypF#Z%)OC-m0az4 z6;pT>W%r4G6}rT|s88c-4Nr5iy+d-gPO?_a=sd>_pc56z$Gqp*D?|<#lmw!Nl6nuK z5Q6&jifJ-JgLG8X2f>9vl&($yPQ+%oJa;-tmfw$TftSIl&LzlWI*rBcM7yol>jy=U z1P7!jBDO{|?_{M!==C_)mGol@Z{9dio{$X*^x2+T!=xZ|?T$v6gW!{hx=A4cv&w8O zS%~Z@yusN=S|xu%MA;tp-WN;qy9WYG1lEmOjtvS z&F#q6q$>3s)h2r&7^P@!J2^GrP71Wb1@kdlh}9^GC7(v8DB|k1iDCGTid3eaL_Ftn z2WV+D*Mhd&dNlLV+x6g}9awgmBAgd7HT_kZn>e(o^bv>L_&iHy{ zlr#6y$OyWnK4|0lH2+Lr?}#UD@vc;aQda>)m}eVU_Tzdl@CM|^+)Y`Da!s*TAb8;( zax2`?rSTorBMfaU($!-HIh6)8G*yo3vE7{of+M$z%!$s|rY9_y36-=E)mKP~pg;~` zAR_6_#+EWkmiZ5}OLYq>{VZ*5)o7SEL||>iexgBKcCAvSDJGQ%2#bDoMvqGBo?45G z@l;&9B*$hdcT$1*6qAvq=3u@yY=e76M4XAKo+g+udi-A z;TEDn+hSHMc3xa38F;0|A3d%Q-zJYge8xL@&ljKCz^Ur&*LLs-9nvXCh?UXIN4@aT ziOt3DJz5@N1{se#1Z~qM;&#O0A{Z`6t(ArTiPK^a?c~OCz9>y^g2#58Zw{w(E8{3~ zur`+^%4qs4oFAn?TFaTWCMU@_oB)!nF~0qJDwuB3eHK(0`>T0o=JF_L+wZH_2;-gm z<@a5E-h$v&+H(CqKhQ>2Er`9vRZU^xy1uQ#GN%F=&g5E3iq=+%N68eY-0ZCj5r{ zhMQzTMYb+(o>Nw!N7dKM146|dM{jma+=U~3i)(3Ocv!8UZ(s(*RFWBee&b)rtM!Jv;XLtzSQXBLQACq6Sh3L=t+Ox1 zG*jWefHUs^Fzq)kF;YHVbQH7|_%*s#UE}GWy59n!c1E1ZDx5C*I}ui~~IuQAtGN8#>;vpxoGb*wbq)*BiuiFf)<+t|MK&UEwgtywVqP~{-_h!(8Z=iZWH zO+)k$fn9A_~*I7Z$80~IkGxq<;WO*{eJ zn+~DI)LAJfTti8{2a%VczRgZdK`GQg?FxMpGR7;{BC+oHbOh3i%5E;2>lPYf=}zq7 zASHUtk2dq2OY z@J$L#opzqh&VvJ##8jk$Y6$EpyuryuGllSmUYjr^!wwqLoph;3v~{Ur0qvqaJw@(o zF5{>v?TGzi@{ALZRxgd}s4~?9mqMb%XnNHA23|LjAn8CBhgA|}#-Qywuaa4u1J^?w zlzBcfC*r<*E)gRrlr2xt2<**{B~6?qAWPq_%#$IPz5GXrd&2{bAlZd%wU3iCw?@hq z*Q@uW?Y6EOAML3J2ZIY{<$kUSx4TAA&+N@~gJqJ8IF3GP3(*1-LfSxQH{zAd#Z3gSG&0`b5H`plx*NwmS;imJ_FP zv`MqlW*wG;rpjt4tK^bMVdp9Zo6ag3&{?WD#9yPHcVYP<7<+c%mpCuRH*K%$dW>NS zC0n|+5~u67cwd_$?|)3W-D7)#do-MT5UmM%7b)KJH;{H3TpQ3c&Ls#aYtR-cxC6wf zki?~!vYLk!g=pYd|07lW8rz*2mcPXACljP3qVpBt3C(3fB`rkt6;dK7kk$qw*mW9P z$|PClzk@EpK`Hfhscu1~pXBQ*XqY!#U~R;HqCs4Ctx}~aCbjf+GAnCwP7+Niufo%; z1_MZ{c>@I2>Sha}cjD#Jk~+8Z6jpI;S?$yt$l@B*Re%*$I9?Itn9|vm@t_beJ+5_zbF1>GSCUYNf z^A^IaNc&)Z9+Ciwn~PWAwq~LkmvO2NU$ld6HlI>>NZoPVo;TRe`0n+55*y|o zPSDp7zl*>4q^+vD=>)kC$PhJlSEG4!V}y-njo%|?44tq15|xx?1vM%@GzHS<=uMol zW549;^J-LGBxr~pv0#$S>{5%7Pqp7BWR{@nE@YkA8M%G$l@e$E>tJ`lxo1pE=XECG z5E}=2Lli0twJTQfq^)gQHWid6C&OkyX9+bmc)e9aRT}ZCHP$QMJf+YJPQO2o)M-dU z9d3@G?RR*3O=f8Qplh=Jc2+(s)WwmnYlw6H%d4UK7|9C?x3C zYkkOM1O#%KG`2g7ZqYV*giIu>cC=HR0s}F*wC&OpLBm@1Q%Na7>04A3a#T$AfVnVn zyfnLU*%kV7b39Dzp4+eid*Nz%w^UrG^0pmU`~bM{J`1GPU%WF(n4E`sh_rqR#~jwU z7jd~MEN^b;%gqrWzCDHUh~}R1K%lkt9TLDv8y1<%ooHk?@nmR{5j<2#iL7%6BG?0M zWl-N{SK3S7fdaBrGJY`Hj))a_PMmiix&L9Pnl1kpE0H3v|K`gejn|J==5n@kb_0tD zD{uX{fN1&fiyL#=uLOfB(cw7$&+oGzse=qoJa}%sGayv8z^CeAxZt^kE*{WLHAC6i zJxGhmToDM+BJXT0tEdW9ceN!@eU8+v*GHUYB+G!q>{8tV(>Pek`g1we{&GSZr*pYe z*2_WF-`dFS*Uh~BnfvA+zkP3ad%k@C7k*~0KN?S6L|CVAS3mMw*{Uml_0A%cuHP*d z&%L;HB4GG-&gz-2+;6ixv-Ffpnccz#sqb}tqLUJKF4p~{$@E%6n==Q()UA@dQXXZO=jpua!KO>rt+!Y4{)P-X21%zL9?TjZr1NT8h zjbvjHa4C75$9=pAg*>}+)6d*r%EywoPj1Q^aQO`BAE10Z5mu^kui2a$YHYmAM*2{__ zI})cM4u+Ccn=)503v!ZF@wsg%%89dwa|bkO0uyLF-IdZ3ApxhqXOmlkw#sU!-arns zF1LG14RGL`wddoDZ+1c?L(n!lq!P4^k|hZ#QZbT84l|(~ zF<;^1cyLtd1E~=7SK9(Pgmt~}q9%!X%t%(BSBKN3ngza8IZzYgvM20^Lm;BZ{*115 zO~`|Srj&q2$g?wgR8sfUnq1}iTqD|653Who|2?7&yl*uIwla642THb^X@d)~TGxB$ zL0d>E@Zg&UZ9|+PzPOIJjtii1AogOe7K!S^S1`5EI1wCv`ulzktM!h9w(}IU^^4Q0 zWfz;nc)F?jdbFSeR$pN@SLO z&pvP!RHp7NTLNKiByQ++Awn<299br7jBiE{mJQL(E@jaq8x)n1*`-H8+w2jRQZxXs zQS%0_Dn(U(hIy$e#N20laHnxjU4cs_g8(gf{K(Y3rB4`4A6>8^wMOy~H&6+j^mwC9 zdaR(OQ$_^6Qgm0}U#YBnlTUPvU+u&#T&TykoR9z+PIOPv7($YYIz3%IqoxKmjH7iN1>s9Wf!1M~Og@hm2+6cR?sV zH4(HWe2U(%R*^`{AZXJ`sx7x;xd<}?I0U%=F(ir%Pp!V3o%O`ityNE( ze;R$vEPav_yeUvf-mTX*p-fhvR~bqfJw>-@>rxg%GE>8MpDb1h*D3 zuV=pAJoJ`LzC)MXE7131UO9sM?JE~>sGNb)T1SD|9jGa11G#Ldgi<)+Jey52f`f+0;f^J7c!R{H3{9nWT))Sc91w7K;@QVH z!m;fGeFeq=kXS<#gSN$t)@snU@=f@ps5=+jYjNdW@f~wF-f@d}M`_R&zsvKREfObW zQ+&6i29zEXf^Gi@6}mj=EUTyrRd=-|us$D!T#adD2Y65XVRor*0TqlCS${6`J}Knu zv%j2>#_60lWtFLIuzRbr{koVdyY3`jkNkG`%{{#d>HS~$Nen>10>N@ngJR}sS}@la zH=X<3FMeNvs4HF*rvV(ilg7T~PV&A&j;Ek4qOjN>7Sc!8fG^$EPhLu}t!UVKEB3_dj+8rdb=uw=HWA0lU0i#tb19V5L>SSWnLlsH_ zNu9e9=8GaMUbvGa3KtSN*9nSz$~HFp$5QMp0`64O^n?rUhc_R82cC&r{K%g^PZ7~L z2wO#(9JF0S{v-e9jo*vkoA9*gtktrUI| zT#UlQNgA|;eymjWhTsofzyhW-?r4PT!wE^|>D>3SBntc6c;Yyf0vjRIy52mT7S7Co z!|YPS0^5p*Iz#>0wa%?cJz{?*vq4d|+$rlNWyQj?k<1Egad@ZAYs`Y2BvpKF8;UcI zbA)6r4e6wbQ<>>?ZkLr+99vd9^#;del?>=EAToi?~X0Dy%_U z6@^|PdCgXuiDnZ=I0^u9P>xD>b4R0abSx&8J~kxgV_7)`JV}$a4ZY}=CW(2>NJf4l z5>-jmU5oA==@K{-neUd-fC}5$6PY{vtzP&{RRi_D~j@0<*OZy_`lDvaC#2pH~?>TsB0HSTHP$*zD4y zpzS1gy#_=!vC@td_Vk@JcBsN4D{Tm6^@LCLh%Gm>lAyO%*ea8qZBT8yjb7RcLSj9n zU0(EtN<9uGXhfwfb)o{e+iIozcPr|Mf7}E0lZ$flg~Tf35

N7D!%XHqXi|m7Fbs zP?8xt!JUOSXkd-pjUFhHAk@0`n!=KhGP??iK)alLU7PwrpO}Q&P-==c`MjD@3F;k` zngmC`lqTq%hjpforI$*#YM6RsN1OO1rF~qu{p2M0T@+qTAvL55>#fsco&@ZC)zi7p zRH@|f)K5456o1&Sl ztF(o^aL3kHU&2#?Hr8F_87A(=+n&pfRNmHt%szpR@_XC^f%d0Oxw4;6npl0AjS65nDk!rWbqwh*B*;tffH zO6nPIE+pZ4e zD;Qw`nl){vN2&XMM z*O6#)M&Bg*C$L_T&OVRq${+oKdjMC5QRNY4m9E)3lt=-88ni`m;uju!6o=f!3#)e( zH_)Dv;+;+(bh~bL?rJE?4S9eUPZQ$4j1S-dy>@d!;0Gt^Wze={RFmn95;#y>6IUNj z0L{~meJ;xiYCv*A?HC2Q8uPKPHxH+UGc({YyVS723>>Ot{kg;_q%>lGCaVof?v(YC zvSQ)cNE17-g_&-(@k%ffNi}bPz#0!hoO?nj&l%VnF3N*ggWHp@azrVsoq7W~rWO!a z;GsJuU!l4bOxNE&=H1-A*#oA3Ik89QwY{TJ032uE_3?$^7>vX646lJ(Wzvxnud+}I z=+&UYDxZOlZ~={=ty*CW8no4vp0s_pR#$>d|0X9&3yGoJLVQI6`wq9nR7F*&I;(Ag zaGj>QUY^NFM8%9`jd@k#2WoZEV-^euDpA5}_QX{CgNeuz0H{>iOQV8|qY97drKuTy zjlj{Y$t5;ra+EL4d3Zf8qej?uRK61I8&!k5(E}yh&9tFYZ`sRCH(07~0t|lu&(_8# z_YjuF8)o22!MmFD<6HQbMqQGxi{yX{SnEiqFP%po92g*_AgN-8lLc+p$~8=zu}iFR zA8-#Aw5h&y$k?9?Z1ln5@xKS$FS%bUbK7aH;_I-AazjxNJ}a>t16t8+tjM z7qU?Ae5}^zRmKjN4bdYO49g-myYwh%+i;f@4Zv&OOgmBtIPZn-(;fDdPn#y%Y$7K{ z9hi~r(i4=PN!V@^bU-{7jV2#+Y!Y$pVzWtYC}xYG-}G>si{qPDH$;*gn|3v^p}46* zTk&qDF&PkTD?YF78tqUc25pB3D!3c*OZ5f_VTXnr=+&s?F0C5EZ9X>ON6owPKp=N( zhwPq*-MY$sm0W$hi6?)PtXpgiDrKwA9f-&i2h9xX+w4kv$va%AWW16hbKzR;4j}k7 zwexjVh5x+cKW~uvNn3|cTx!tPy;~5pRqPj3*3`s)I`{Oy|KA~GQu2VHz6%0##tRRQW@91SJ{5uOcpFcoMVP7h~hl+hweNc<+=6F`Gs_|;;Ld+fa^uu z7^Fpk*CWTPNqExsEG`Optld1nD?IJ0x1jCJ{p&Bjj4RO-k`g`g-j9@Hk8}6+240UG zc@>Ln)IlMB%H_8yNDHvKD{0xE$!derqN-~4Y@~@D3?)_@uLL8JRPzQ1tkq8jgixL{ zur*wiCkhR2Pd+Y9ZI#tdy&-W(D#mjaxA0--U%GF+A0M(?iM}5B7(%cJ+G4$WpaW=> zj6L!mt87ODJqX%v=s7c1q2i|pZE;}7w+Mb?vACkKrBwj)gcR_kt;}aot54cOKh6J@cHXa&WP&&&;o&(X0OT_HTtUgc=dy~bP<2+@0@Ybab-l1(lf*n` zBqM(XQIho4>Y~Ri=#x@|3tQO}Q|%8XB})LHQe`iV3NDT+JjPj5GyEEXqgj(n=n=I# zR)Y&sNIkeFRm;Yd>>B}pWM=M050q>-({}64z4V!ExXiwZ1G~GYQ)e0cl>-O!H7pwq zNV2j`$pJ;Yufd(h^7bx>YSAax=UN#};!f%u)o0tU!EL+K*i^P(Lr*|V@-%q70CE#1 zq89-IC61MnmA}=|7)v7&PGuMTtCk#>2ph|S8Wa<`U~OzR^l}zYV!2{wcEuAUA!%+?v?178qCFLi*ZQWr7D4u=*VsDB?o|&oPA+Wbh14OL z)UPI2oY0Zelb>^m^Dhvp^B&3AQ?onw1`e!|yU_zh5`y^VFgWrLh^3CwvA=7`n<|e%IGP& zMO&A$5R#e79%&IAh|Hx;ZBGQdX~KkXDoKMvSej^f8J$JJXi@zeM~h1bg&F{IoE z=%?mR@Um7x^;Jpos!06~7FwB0U0w(TlFX)NK1_A-v|uf+zTL!=wYllEB(?!kg6iCX zh)PE@sBg0??Jb4&)qFmB%-AU{@T9F<$PIkc7Aa^(eBm?`O-w)m~}_$~FDPkqN~ro|mHIzaT8 z5T)!f1(sUmL1$S-Rj9hFErIk>w_a~TNR|Pd8HOIJbc@cznMXZuz(bNsT-Kk<%q=8g zH@$Jxy9uyyVyK!_);_9C_kiF@Tf80_lXCIFr!Vj7OP&z4{d}6FLET-t{CS*~#_M9D z-?S~>I9tlko{3K!(z^~k5rr%8v)$r$|g%K76? z+~!-JzueY9|4NQ?Es4^!*k4NtUCHE7I0` z5P<|C0F!7Mde`KfQb>*r`b52PTHKdD`qnpx1GHcK>g)#?<-?K$#R@=8E6t$wM9`q^ z%_Z(={HsUzyq>>?4HT17^wI~h8_2QQN$b)mtGv9kCvFY>mq1$tK52XP;8}QM@i&oQ zrEw5qdn{X%pgx=cR?J$FCYKcyG5rO{2?XS7giPyt^Kj;&`OXX42A7W8g^xbHX`Y>7 zs!dHTuD#4DJad|d2=UzRDSRQBZoCvbjdFGFMh{d{;Hd}BkwcW+&|BIYv13`EZ)kot zK*i)9jX7XUWyHr`=)pXjKaI;rGJQ54Y38DNkfOZ^&V5RuG2O`sQ(7L*tt_Lf?;UQ* zma{*Tw@JI*HnJZ)Xa*GG4a0$|EC=6e)4*AZZ}f4vTE}7nwsT za-H0@9w^>x#?+;^Vs9oJEG1$y7bJ$=M1LU_%gXdmAa#Hwq^Fe+B>w%7z!P#c-IHqq zc_tAWx|@wyzAd6698dEhC8vZ4o|vgHBp-8jN$aWW36Q}oD_)6Q16k%Yf!TXJ8KhoX zUJ)!5%034+Cl$k8YFaQ!WYRAc+M1F+`)R$h1>^1LWya~*g}MyKW~JJTa15%R4OL`i z^6s+5wWV}|KRt(1yK%zdQRpc{ML14*0-%#pP%EQJ*)(!DdZ1JuI^2L>vscN+Q`I*T z$ro}GeS-nJXsQ7ll#+Xt91x$vod-1Z^3@N6h7KV0K!L%Kc&7DV#E#6$n{Eb}6oq$g zxHqBHGt~kuq{6pG81`m2D#d7mGyzc_&iLp=06_a52L|=r_r|yYGoD%k>GOtOPNSPq zV5L)yc{Q#N6b;cM7EBVET`F@W*Y(s;(r3R-$SgtmTfI~u(`G7nQXz4e6~-$9q#7<- zTlG4Wlbof!5jvJNeFIs#5RfJFX+Q@FQrb|hCOVXq-4>Miff`*}nbkEVz4n(AvN9;`UYcgE?ll3n zL#~WsLZ!vEk(qW9NLeRy++cwZ7L;V@mQk z8P}Q|-Fo50l-4W>Sg|>&=oZ~)!6cDce=hArtl_to{Wc*>PCLUWPhTe4a70w|fM3X) z&Ye4V9EYrfGymb^IL;Qo`t&6{0Y7(tp&ztsC;gtL;Hg|(16sQGJ#uLo63up-vVrmDAHOuj z_COKz>0iC;(zz$`7rQOcuPON_#JXl;wFwn^ERd9Lbw;EAidy5mjcSt@y3PHEW#MEUfqj=c3tK%!OCYWC zbs;1RCWT}faF|`HTaY!F=FSTBms_kSS>12JnCnUa&Js{R>a*=X{NKcvz>hy*w;r;?5F1iFcvk?Mo4V z!7VOfMV!8L%x?pPPl#Lrd@KH*!#C{`)gn3IxLmuApTMeSfw+suQo_F?${Ed0>s#fV zd(1Cpf<;*VdLH78u34_!i6BngadC^8nzx4wX8BDiaah%cI~rj~)0BtP`cU3!;n;U8 zE2zjjl=-GWTC2U#l=X5r?dn|aRDFCS%UISFJz~L_xQNd#-OtobB|Y}%30WVMRxh(u zl!5hRwXlUk=gh<;C0*hQ2FR#+f_Ne*eEQCyBWJ139SAqSSI;y$^$IyAbTN`ba==Al z`T39h%5&a1!C-7Y=n72yt^G?H9F=RCPJ1LvcUkqWjQmYJh`&4c?xrYgJS_xv9e>X?hg13$48&^n?jWkHjPN=FCK?iza)*;-flmeU zU^Sg`DY2}gDpZ|SZ_vORN3*Wisaugs%Sq-VxQZZPps0(^63Q;sEf^3~LD8`637-34 zN|2_<{)`4y*|kcQrcelqM#$6l^i?7WsTj$dTo%7`JBd?hOe46)Fkj24E_IXy)QV_w zH+rB*i*WYnHG50`UnM{we7GQ2V>m0G20OgwQ!A~qqk!CrH7zb1sz5QEru1hP zZe$abQPKfsBdN*l*{t|AgKVNV^qRe79VwDzN%|nlKesw{C7`)^)?GeuXArc_6NNT8 zmcgCC$KO@_1NU9jwfe%wiD^gLEHIk(<;VY7rFR3?E225X6#=o&P|ChnQ5CB0YD-{!J_d5trxAc8Ym9HVjs|qBOLYqx%-u~<@IlqJ z-Ac;AZ7PWpR0>jyDuIvkJMqBWC+Y)?%G+Mpa9bff^R-R4b*#{!?NdN@Z3YF-k>lH^ zzI%q-GXjpi+tV&d6^{CFGxE*bFFu|pXfmQd$5=meAMR_6YsZI$xIgFAsPU9jq6R){ z+#4Pcn%UYRZTp+h4{tPmyW!ZTV*>gs<>ad?5wfrc+R7kXNkO4V-KU)T_1pwM-hM_R$%N9ZjAT6mJ`pR5;n^Y;6@)q3W)-1g5^zT05vVrjZ@k1En5j zml_sy+ueX>{kfcKzc)F?i9OzcG{xFSl~E7Sk6!ZOj;m;U7Ql-?uTG6qw&HStkR(Hb zk8LiMz{a#J1F?rUxG$wu4p>S`ygl?xV zgLyqoKZp*4bx0EPn9+?TV4y}@B$0Td3|6zgH+)bb=&yQ11=fM!SYU5V?lUrG^`9+Xv@Qc^WSo}JO7lDenX;>z*6X+hf_sdey< zHCL=rNuvjfBnWeqJ+BA#7_Y-Ux|7m6Qq7)^#o3eFOAXpyy6pV+!Kcyl2;Cb zLeN$)d*1!Vf}v6>{6TpWb#){3VgCHJ{LE|bK!1g^=}t+y4e+Do!z3XOAQMq ziCmE?m*(w;-&*!}4oZt^k`3SXMCE2Sp{pL$F=#uR&opRz0t?~9(?98UgH)ch#bz4p zGKn62gFb1yT!!MmT|X$!o!Ni+++?-3s{}drcPDbi-5jQA66i-&gSJatLwoPLC(20N zNBOs~2Rv=#h}ywj?!@L6SDZX5Ay5owpv|WQHZoET6~U0g8o522l{uL~@vK$R4ZXD2 z%%+6CB1#U#E>S_y*3I$A9-g!Xbn$a|wDlN>Dwl_8+p;*W&&V#q1Bk!;mR~E+ zCBZu(g?;xYv-=!=4^K|A15$Yz*`CAQ9VpS&i?>l$luK+*%;>5>aN6&mAOWa=#4%&cgAGtP7Y6zknxg@hkJzIkcxGZ)A(v zIUF%3B~y)a<9CANn3G$We}XD+`j{lw%cSbTIESu*Bc16Un3cCm|dz{kTsa*&IEtgRbv`K8k%wm_dqvG4a12&W5ToRii`JurneQa?B+a7Y14|7&iJ-8My z=_jXh+8tuhc9QlKzQaODLEHFy>NKLL8l%O!Jb;ib6BI<;!h*KCOy_%`f_DRG@COe3 zpOlnt;U3ki;ZvW_^(xr!=wOPQ?ee}ZwIEh~J7}v6qe&o5QyxxqDl!-5KDe>E?f{Y=tS(qn&X0Y&~+FSAsXf%W7! zVGBi?Tk{goUy~A*xPk#PigG*=i41d6laKjWRaW!fo(B~1foq?@z_q%yjhyv|2GuHdFWJ~7u zMi{K7eNTxcQAtaMtgGq`7+8xw&pya{VSh}eOp4!$hYO8bLj?my@x= z+EHD*Ipkcv5m9H|XWf_M>yh1Ozwn2j{t3+0@Wp4%xMb6;h~-HfBR7BWe_Y8y;WTKQ zWb2c*6Z8fb5E3Zc; zB*A-gdW`+dZmoD4oa|pNIkSAP%nG6l-c~rXKE6_s++Xb$ZCzTElVs&W?3d_P z#O3lRXglDnR~r@dCHq&fXf$Z6Cob{z$S6%IShlUYxg$bbR6F)dVGY=;< zXq#?moOn6P1d3Ze{qyIhefnqaX70ysJ+N=g#ViGF4d8J>`FpK(RJk`jfKiO8d2koP zCl$66WiC5>2J-VD&%;HFj8sEKNXP>mK~pWCFL^dACl?uHCl?L9W-nPs3Y8p8)=f9l zpsk(}p1Ueo&hG2+eZ)~n?D#SM08|SL1YK}T@eP09#Q@9aS3fy(bjAd&Bw25~G&?cL zXz%wgegS92vv|T9uSN`v4s;CN8ceN$3J|6?Q zNXFp=kYtVV?bgwNj&-SSL4&!wDGENQy0%+M%YGZ%C_$wlwWtz!N*<;V-7Src+1(1d zV}5hjAg2!CZua6+DQJr;I~U}>b8hPaxAEkCSdg_8VoPvMrofZ7_?fxHIkG!33%A!- z^#;gkdMR>o-Qh`Fq)A-!Q$G~f59qO0U5HQGdS$Psa!Q0M_*JNvnqCFr-6BIb_^zPY zr*|df(3pjiXq7j?TuPIyZE=-DRo}7##Zx%RN_L_<3rYg6&Ml;_SeijL(F1A7>DhFW zEBz(Zs$^V7I+KVl=|$q;Jl9Z2*N~(39IW+uiJPs7b&=p@P^Mq4V%Ve2@K!WJbq`l; zXS(8raIaTLKU8Zafon!_#`$!RCGak( ztTuvSZW8_2AI4_L2#z5T*pUfwC4@2aoKvUje!Taqhdr~?v-iw&RozqPt4>wjs`sAz zv0ZkJIzzQ6TSsOUU+>PkNkOvauFj%I9a%gf1unJ9Dt%oqDK<2Uog;9RO{!ZEG^nDE zO!bEmYK&FF0s8}4ZM=~3##YATsW9XLYs^QOCUu-L$V;Grzz<$Nye9MEIu|V`3}Gfn zJeTo~fVD5j;l)G)5JrGRmp~h2_Op2|d4LdvHZ!M$Ud-#~oNAAg2Q;+C(E@;rXT1=A z8q<~qE{bC;MEP_`*MnYUB_4QV5oPv6G*0v1|HR($l!^X+h!e58#=0 zP|_YY?#utnm;XawHA*6r25BaAXFR9q@L?L?cFl2Isp9HhuuXwsJo;8dz0x$ikt+xb zjjE5UP}`fUgQDmG3wmXRN|`kG!jraHu&6J0WhIX^?zsR?3o6Izp(oQp6_8rjkyR|I zaYtp*@70|~t6mpW#6m!{eY-r~9k_n;*=pTx+|YGot`OTju1y{OZ}F610U8h~xrZ<^-o4 z2KA7XyAy8dSJTF#z&jT%(W5H*G(R+ZUdD_H)Z;b8`((+LF-Vw&jyXoFTUP z*1q;Z@a}TZ))wY({i~(7*|JlWt38`BdbWi5_wKca&$ZJuu-jzpnH85{DlX%jwy0e- zpTsw9QJ4#)rJPk3S)9d{*O8$btxw5tE)nODG6+izv8>OsQ zbZpYRPBu#NOsPUX1#L&U?M@Jd^EYlTl5g7XUogLkZ`!Vt$-n&E)gpPHoE|%X^V@{D=*@6B4fCUE&IaK=g&IGPjgNkZoa_V z=?F!J!fcwG-}~MV`X9U=H>JnV16ECLF7ECyO^K^V;EMY$QZYK@+II}2RH>u`j6|hZ zB~}kBn~Q*on~R3tXs@ykWFpz>w85L8h=aC_qAC++ZSPeDT$ z5VR#@PCfkE*gK0uJ0W@gbyE?&K@N$QJ5_Y&mw4j!e{Jq~zM2 z#@GtK7+AKwT2-NHFD?jVYXR+gwL4L-WR3n6)}f?bblIf31w+!L-f?! zHkz%czjzvm6)lAYu7$IqiXmlI;Yt>;TG^46XPi2>Q+jOy9|cqxyM`DGP);icoRmT% zYO%nQVX9hNWGM%2H}s40*Cc35!sXvYejO9p(^@NN=WD~t!MHJcQ~$G0ZgXNDzG-m? z5-Su?FNGx2pP9I}$*sV>)7lCgs51`L!)ig~agY-rNY>mbUeyGu_IyF0_NG<_MWR5oUg!s_RHQ3t#i&zC1-;bX9yNA?DpACCpc6%*@YDlmzqww;oN| zvGu?dv>og^jto+U8;_rV{#^G-mWCiE1`K?-hCHfey97G7(BK(67bIwG?S^W4Ghe133 z?=W&MHQtSxl!p?rC7NI(ImMFSSn#2oz4U|;#!-c=t!N{Xv;U!Y|0UZD+E1C89 z!wlMn=pZ559YlKzNEHlZ^^pnUarV1XY}qtz3|DC@OR9#CRSW8^&^Sqlk|tLW3chx; ztxEJZjv6>lS&&&RY76V5gzHEN;xG%{ZGAB`Qw^Ker3uk9K51jT^YBJPF^riq1)E-N5*iu47XOe zgk6N$%YvQB%%ctk@*(W9$rebi9|byal$+b=L7guL+8^9%247{RJd`X5B;}~&!t z7Z#-a*YCJXp^%e-KdE=WiPVmZE+AG+hBy1+#pZ~^NWk{k^ z@KKI*!&ut(>+G{e9LFEjBXmJ#{w=n*{}&qw2V})ESKD(}am%9%gL+6S*ME2EyFa3? zJi9lB0qQ}29oil-5;VpoDDbT#!B;tXaF7^^0!)fUKI{b&F=cnc10K}*d|>gfnpdg> z-e_L4YJwt zUR7W<)~~u@m8TrrDlQntaFSJg#`?kAcvUw2FDp3=~Ip54+3eQk!E3 z02W;E=CcR@KX~s7+$}wKr7^dqk;U&HyD5UT_SD0l;n&x zFA0nJaeVTJOZ);UV{DP->Zy|26E3C>#(OH*KAMYPQw1o@X^V`mnRTBUv6FMdIwRr+?l+MRHzlGXc{6x*M*i;jcGDz}nV8rm&3 zv^C_-o+D*luwRwLP7%5Vs&2(oO}huut$;5Q`uNIeyr3q12G7Uuo9ov7{#rPdm|HwQ zLnq)uGh#Q^(P>J4^rm26eRu_vcnpLU+n7t3dS?ucVZ!7|S8kchu;I+svKT_oyl|dO zW`j}V#7tE8v)+1h0vI?xfv=Xh%=vZSWI+an z!kApStkT9)K}{IdT4z^Pl83aK84fv$*z@FF*W@#T2D~xwH|6??->> z^N8-st@_{NH>^4Q?c{ii)XaV0G9D4V@~wC4s76H}pl8#Y|M>s;#~;Y}I?~d`a_#No z!rJam{>plqUnp=}@~Pa~C3EnH|JAnVz6%TPZl85;j=H-sLg(sAe-m8{W0VhIjdAr> zB+?T+ZxjWbo|YvLVa!a?O)^FIWkC{X>fCeX(iZShKrKAWrJSX`%G;k+Bunu0{n&Lr zcz{Lr#tV-Y?@QnIM;BeP0TGxp^bcO&%CM|S*L@26%RVNA5HSr@65jzPtbjA)@-{g2U{!V3nu?7H$RRO_HSqILtnYNgey~jVa7Xx z@2`hLCunz8JsqEQ3lB`r`wVT?EeNcS$A;cnWLL6)(Eg3peFYr^4bf$j>K61#D(iy& zkOyx!l*}T>f|AHtPL}xKU*tlezP%`7m6ei<$9;t+R}cywtqO87FUI=J_(`ou#dTz^ z#9J-uDWTp1t|KKVw-vw zTE{POnu4}eX@(HpY`DQ>16#^rOyg_`_I1p{3-9@eRIm{W?M3WpI4~e`COcs7Ow6pF60Rr;uoU zJ14Y)L!%3QHAbi*{9_2+2|*qzky*<+0U@tc3BE6xg0||N%CzI|^PmGT93I2`;0?1m z^_q7u?HKUcNzQOXlAP%XWvA!Xhu(? z*;)$ah-+{+TEMJvw2}&{>(z-@B~-fB%nCM}X{F_}U~1myl_Z;rMpii1|Z@v&*)tHI@kn zLA!`ef(#ORi?m{r6C^A3pjFxmMRsHq@ycZtQPB$wDHbMpu$n94cAEq#q>^HjtRmEc zs4~*E6ha4wJbJtAO5uvatO`*j7(x}P3sjZ5f#N8q56Bp*rXhkmS0CLqLPZ#%bTEJA zVYBVv;a8XT&CbmIPtn1w7U8J2yOe_B?+{o`Y8HFxzhuhRh+ ztO`TZ54W-AEO5oHvMQq9^Q72FrpJAmjg_P&j(gD~4L<_7M|U~sP+8rN(RdSm&g?E|;` z!H9GlL0g#U((?~9wZ$J^tl{uGmy2;NfsJxFGEt9NCHKw4LFsAzeE^&`uUe&S-C0wh zQ_^<5aasnlM*nu}snoQKj!g=pm8`lsTz=n>|n49N$JlNVRaW}0!(cF7S~ zp8pbjmoD4(plvoRG=_RZCoIHRSw`q|&F3n&>^DWUWeWnu*=aAQm@B6ltB7v?HxQjN7+ZP_p)nfX-9C4u!D^Nw{a}<-%OW zPfdrpAVJ$GA1LgM4um$(5qIUFEouotTYl>zhhMAjO=Ov^fJ;azSG<>ZZTx)hN^L{h z$^%=7AJ@OcPwF9PdkPv;JpS-#ergMt19n*1WGgb9q=Sjr61lax;HvHc!UV1Liyair z1PcO5+3I?o$6Bovw@NwspO2iN29vtz0Sl__?3Qe`DtMy#gTeXwKo;$9c8ZWKP1FFMUQ)E`pus-UF=H@$F_FL0#y(?<)b}-$*3piYxpgT(Z7nR1h9Ug@RN%X z3{1d)I~f^v%r0@hoXIX#qmpC`h^8Q)&kBFDrUn8sM@j;J~;I!L5>bB-rmdcA9 zz3k3>WAFEkxsYXN@{>YY;A03Tf0uK~vT?n<-%n*2u-}i2iFdRI)ZI=Q;t8HcO90^l z*TQ*X;G{D`nT<50B~{XB0aun|s9kTgS0(jlPOH5>emW09TZbrUYH>EjgFgJEt*^{< zkqfuiVw3uvSC+Q1D6jryWAX2sd+#=9)u?{0auYI0Y`Tft|GzUptktmX!g;=qo9BNr zzaYpB{>}-&zVeAP?3mbg67S5#WR1mmP#qJr zi;jaQh>rdmA(WIRKrA-dnK5dKx555>?@EV+3b6k?XQ$Tl0@Fcg*19L^zLsUR6wNZEA zwjy4+Li`TPgs;+#;YC`nZUR)4ZACC>avnWK#0zyYdtnMoeHK}evpQN%b=nr}D_K^LpoidAZ z)s%RQg02tbaYd}Mu{2y*;8LOB)GDV!bTeS}Fm8?XxF>UEozQBa5KzK5W$|Z421FVGW;m4%lI;9kPKO4`NH?j?LxaqgAZY zgXY>Vqjb~+G6yMJU9a<4tCc00@|P8nqPtKRJ!C<*oJx(=a_~fSj(Xks`al-#FNZ`~ zRp}q{Y?X8h+E$#=UgXFc7Oge&vk!got!ER<-Tm|iUxc!>nplU!bB2-p#aIh8Fg|Ge zV;tnftae;&K|%P7XJVAQ!SWqZ-~HN8TFg3*G@b1xt<;dro$J7C8soODKPxBKFz-<; zFp-E$0wKZ}j{9;F%XtuTJMk!QAlBi-hgQc~$SYNWx-(x87^0aCy>KxA=THSDb8ryD zQ8uYzfyf_9g8uD5*z{Y6{jHs{(8?h680H6Wkj-Reyh3}CShfKJP3Ira1An%Z3Ot0{ zm|}K?2sA_%m#@adjX){^SVwWH1bl1m7#od6*-z8vHp?5#v_}i$j67PM_m;GSyJ3#+ zR6S3Y+Z-K-BQ1!1rGvpmJ{_i{2p#$hWRbqRP!9M8ccTR?K~b0~DzC2BM0>TmKeN7i z=CgdAoyAYuvQWN{P=JlH#v$dum+%L`9gu7`D8=T&G4ilLzE`x>{oKwt-*&kh%IpQ| zY)48gBes2%z#u@mv=b#R-7bpsvH6nCtmP+d5z1vq z=V1xvBa#~#xpZ~DgrF^k*&lpj+!om+w9kwHN{acDXKd_QkL^gW72ibAHoxFP(3T4R zVD@GlK%TEUIyxlX9y(l=^4#|JgiKsR9?<@CN*B+NG{jh~U*K9ePw1HII_Xq}b(C$y zla}gdSQqQVj+GJZdZWD+p6;UaRZjKcke{@@x@|tbbdfLeVMd@5~8@pzX$G*h6BI%gfgzyVL=f|5YXS*J1Nf4pe-S4o#T1eRl~1G zHV#B)?lUg-g7vj)SjX{fz__3-pB^}9o041RCv8*F<%71n?|X=QVWF>jjR=*>6*@t? zlN(b)=yc7iRV7hJX+dCpJT~;sq7)?yh}#&n4bf$j>J~(ey@jAZ9H@;3-T zJHyM)xsLl1mxMt*~AcElU#JRDo}4S(Q0o{2qWM@mKRxQaLdm;7{=a$iEmX4oE^WPcM(*FbuJzXZ?a zvvP|vq25D?Foxs4oYamfXxrx{6I{9-sG5GmNgUwfxh_P8+d5@|DhNG>`R*HKvrF|1 zN_D2|@C5sY^(@Hj;+{)|9~T+VTPcS9 zYZupqKQa&8l@Y4b+^W@K;Du2V@coTya=A$EhmVX{#>oJTLokp<_Q=*!P)Vqf6BZ_k z5;a=DSVj4n!ic(F6BR~6Ch7v~D@ZbjND2^Gyy!Y3igm}?L!1=$fHS~LK0_*I`!9fy z!L=%e3#EZ_+?KeA#PZJe;%|ht$${|Y@=aU3#WcG1zxL5Pw?l^xOqtu75C6u5RJQCLGs z9NQvofl9DbawrevVT9(yPuc>O&b~h_u4W&({_QBp(}dnLafku=lI~|=f-du^AzEwthl!$|08!2Q#C0p2W=Vfiq{G56A$PJbK0D8tQ@9&3tS85 ziGh>O2xT_Xkd{t^YP@WMva{gpF*O(p9e z`T(o5Do1QW>FKzmY3^)BDQOCH%GItnF5rP|VG}SyX}jn+c!KEYuMr|iX+j=5 z&1!`@rKY*a^xy+qI z&{l4XcKoER6&|1Vu}^i!!vk|Qb0I`E?rNv!-imEiu6X^!>FGs-ax*1tl12XRf=W67 zMV))DJlX<>!+<)%plyyjp;*z}Wk2i?wEdMLr?>v@fBPtwu{8v3FQKZyiiU<)pR~;q zHv7G~d5(j&PENjakRAfwb_3HDPuf~Lh6zM71Z}sie$!TXp8wLG-*Mwx^cqIww%kS! zH@dU*G%vcL(>0$1H5%@tpzQ$~9bKz4qv5w%^h?*YBTy_*MJ_+qaOnIl&uoM$8oMWB zh6OHt^`cVFcy6>iz!MFmE(-+gw%GiD?8t+)88HD8@ekj0;df@f6|gU~g2@KKON*_E zu_$%E@Q2>iyjnFVzbP1Mf~j);*c!G-;S7x=lk=3p3{9N#6F3?%*O~{ z;HnH0e~!m##DkLh#TQG!XiyHJZ*bRIzyzw3i^K__rdJPq&4|6@*&P<+23}R6;5Vb{7r>UYnUpHn)TV@9iqGfa!q+F4=Hc zaPUS6cJp3_{f;dIAq&E>WhjjVz7MWTC7aaXZnS{O{7~=K8|@XDL&<_~Fh;ESrjWNy zr~%xR0xjBwJSPtL5s{qmI~(@Pp9kAG90#Iou>HMc6OuQ z*d=tmiAoFI$qJLvLyxs(R&WrE3ZdK5yvNVYI<)4u65HF|N3J5E`NfEEp8W z1Yu-a>0*}HP|{_8ty84i!Mo5(R^h>kg8G#k!7T@h5&4X1s$5%)m~*nkNxWDwmxGp@ zrxo9qiKG>#P}4+->IGJ+ya3-QCTmu6X`&W8naw>=&|Tr_6psVAKOt zIG-%XLO2I4a@SfQ;&h~<+^Uy^XnfN2jl3ob9n6y!kU@)r)0`I{zmeciX919K1Hv0F z7&Qo$7OUF^S)j=3#VdU2$CImhiYJfc^bkFawt8v4JAEgLBy~QQLvMz>QYEB4$)Z5- z^M+pSPFG4&vc|Y7>w8K=O=?)sBdM%Xm&&jZY+Xs0{j?wf2v;IQDeyf&9u-A1?^b{n67)61Dy0w;p)Mrb)i~qRZ_@fCn&xzo5jj{Zw6}{dUY6;3w(WCMPYq~4$-km3p1imnAQcChP=yfP5Xl_ zacqmcCe;W7CX%KH$Um>1rZRm}GW--laROxXAN|~>ER4L$$a~*TnD645y(PjEd+v3< z<-y^$LdC^no4sO)gZX;;H<+tXuZ9JxDZhdb30<6ln z)}H+Pc&?CdZ`^P#3=`@YdO-J4q^8U0lDXq=+%*9*$t~UgCGW@qXL5yXJ)f44#b=+;QJ_*9J znR%7BJlWRPc@sO0>3hJ_xzov-OZOdjtxjNV(fKJQ)A_a85xpXULVD^#uGU!Chu1blXmdG&qQ+e*S)H+0+tvasbJ<3+h9Dui|JMhlq2 z#TBJpZ`sN*ijDe)uj)W_o)Wy1C+FxKo`}~+;rV+%ewF~mz*F-HV=i%Voe{V)l#?}v zoY|J+fyC+;>(3?0B{aw7agiTjM0JiI-8i8Wf9lJ?YI|1f$@ucJ${8g zgA7+$9>RSynoCs{2nX^7fnhw>^@i?@VwH@zp@5@oQo{m~Ka>Rh>w(aYv%j@dsM*RO zl=J%b!p16!rQw2&B;-rwCLmNLz5)Y~fh3h7rKRCaC4i8WIQ4nG1&njPg40&LwyYmh zazd0`_}Jh4*x%gZ&kK+__$|B6=0AX+xOl_cOjL5zC*{C6(OFzZ{vHgo_~ARpJi2TW zca6p5xD_FGhsfu3~*(p)PvJf<8&H zj*@n8UCUCunc|iIvp9`8v%AX14eN!Lbryo4ZDv+}+AQyk;j*w}?dNB? zUBZWV&n#ifoSVP?tp^^!>_RJMkhjoRYB}rbhQQV6&KTij&bhLOTsuK0hgNoEvxrwN zSj*6%cOjgqh}#*oT}^6O5GRH=tUXozVT6vhKQuFrZ4tlF%66q~*ilYzV>|@T9)k90 zN!@sHc(i@?#l62vncL$F$JwP7li-CBg*jd9KJoW58T@3nlM^WA8nne4SGbd>&te`Y zTi@B=;MuzRKDcy@UTkzPe*5CL5wy+Mo_hR!xLJP$S9Y0RFi&O|3X|>r!8;SnUoqjJ ztr5ta&ub~nxuY;@ydSLvcc4jhv=)B9(zHW^RdE%thY`HM6}w7Cb2&`apFwye8=*`k zZ5q?yZnS_!DXLR%w0DGFV@RojwKjk3l`w@I<&=Hqe+<7?DLJvqb8}x=@J$hva{Q!x zWrjE}KAQQ;$e=A~*G0&6G?;_7K#TzV9=rLKllfkL9a{h~lAii!?_o!f@y>^J9&9L# z$(5_oofS_*2>XYSa1Mx_;17FK7i$~6*{;{O1U#gCim-Y(Dr*-V?IsnXWTQk{rrJb@ zaW2rVWWoNZ#3~o}(}q=~Oh zr1pS+m^s`jr9aU2QUW5ppy1qr_(f2R?uCsIv?YK3=UcIc;S}Etgd zY$s&IwmTsinJ5=2xpxH)tRgrIovwMcszTLXToCBJ8muMdQnJz&N~Q?cF1#H()TFuv z?J^ozr^g|W-X^W+vcI)c7Fwx7rtAP6KClgrlLQN?I$6d4;h+x_FrvM?5mZ#6od`z4`|JZBJuz{yCyQKQA{R<7tCA6XRh3267GwmxkfW zzy76v{gxz6LFvFw!yFq-lI=Kt(}AU{>RArjE}@5aES5)>CUB@8meT<5JEUj#gA9i@ z2asSb?)Q|Oogr0aeV}X07X*g!Sl1i6GYc}5jMO(r*`&G!HfZe4S-*pW*8`OuXa7Q{ zFh4b08H94KJ?lKq`V1+>(s02>67r>TB8DpI?XEpTWbZ4e1dx!D!9NW37BI$f;-OWq z4YlKP$7FbABWGJYZpm0jg)HdjVI2w>;@^ z>Zj|2X=0ZVv>m1w3d`?>e2R+<(_(PGptV2X z1A%f7_~X8GL7-FWx?X?Mfd2zHEhs+){FuBhddPw?5~E?k6Wj{|R@wb!cR?kAput^lfe28PiPNdB zx3srgU8P2SvnRe0(GFk5EZjF=`^snc9D3+OkFQv!m!5ZfDDCp$Y-u;K516Gjd^2Qq zYyL7&*Pi+J-o8v+IRse6Ez`WbhoSl$p0uUdHGQo3upb9)=jeX~Z82yP^U*(k=mE<- zul;XG%C@T;xn>XoSED<}1Z@XpGr=rU)qAr;uXZP&L_O5|Hwx=3bcl{kQqh5|PgJZ6 zE)99~cEfK?`%5K}6Ed4rQO#61j0Y@;N&X>diy1M0^0l+YuFc&?K3|@yW%)Ug%9FMh zPugCbn^T*olbiqLdva`{^UuFydz?z1{I_nM`QFpGJ25-JE73=>x$87HPj28z+mwU0 zj?ebL{>%RW=K#kqHy3tVwwC_KAUDLVG79!4@f?#omX zNUV}6ccTSd8HcA+(uUq>uU7YG!g-NT#e6wkVcN~P(@VjHln=Af;4X9r;&ZSBepwjnpabCJ!sZ1y;4TiPB= zw$9jpq+E^etauvi+8-g04d|CFwJy>$db3@xb|;*#e2TD9%!op}=-4Du5lS{fpbP+^ zvyr-8$%6e+Ny!mZ#O)&tsM*1@_1|ePNa5psnQ}wiDbp z9DM*$TVnZ_a!6_$j| z)&(pX%4E_p4NG&F5^TV>yxhVoO4K5p9{mqA%U}8_!RhlnCb1>5t7Nl-%TkwE%bM}5 zg6*O$@n^-TaDLv&T*?ppWH46%Es1Scl;PG5f^v}(hEqz-q|kcJt)~qv%Gr@E2vn=u z^=fxQmXbC4_eh#lx1dzn(E>(0tqXbdHfcqD8UR^WQc7U@Qst=jsER48d4Tk2&q@LB zwD{{NTsNuX<8_QL;sSdcKO`gY7{=cPMqusZ4#1{&1dw(qS@P7Q`YtuAo?4k^{s84;g~CR^)a>gz*bf!XI4OqlSl1i66YcPzWW=om9A%Rl7Kr?zBoMdv;m6Vo{l6dY$3%JfH0kT%T zHq^&LK(yvgu+DO}m3{mY#>hdETY~uyAQ%e+X1Ei=LxLx5ab;PiF{U~uwwV{J;7H7` z;^Gx96m1o2CQvI=TXxkFx6dulG1Gj|*5Y^w5^nrcyU^@|womZd{shlgXNcnoHcB90 zQV&IRdjSF%tfZA5D|?zJjR(zr6)CbmD~CXRJfal>R@uF=q(|H+5A|_%BuxsUy#>{F zs?L^-6c;=p8!g6Jt>~~nR2xG|h^#ES5~-#3AX$uz+69Idgo|#{t1a_L)E=#BkVW>$ z)>2SOsA+K5TOgc@DuaO<|5DDME!$E>lWKIiv?3_xct(Vt#t_UxUc?wvoDXX$B3(ASuBU4=(M(Ak!gDr7vi;jg>_Gq4}+C6}utMa7n zIl_dMplxyjTNRFr@`4+#R^i#Yf?xRLgSM+!h;N-w?Q)7Q$8(>`X~Lo~2z+%*g0`Ss z`(62t^&k%uBHFr=aa9{~Zsa`sRXr*Mkj(G5G>lTs|>`8JwhX zxv+W|$@I7{Q%Rc!v&MsRH(J1T@dWQYrJpS&XS7$V`!n*@^FRgZ612q(k>@I(;oM?* zL*@_}7dr^BE4> zW}D_S9JDPVw%wMv;gWJSy0hLEb^{^d95Ak#p4R!S&*grAX9`5_%V6A=xBEk z9sM;zre&H<84OC@u4KXfs6-?v?*f(LM`YShBPeg5#N9sY_sbdGH7rP-NETaNyeAxR z+9k_IAK9~z#N+g4VhCGe9kRHu@YahD17po!{zKHt9mY5`pdJhJb7tq_tuCdV)8f`hiZ2p)C7o$lc{_&W680rZ_{lAeq1fVH3#V?+vxf~UD943g*NnT&a{0~a%#J_Hhy9>m61&FlpaVFEtI05| zaB|2}yeV9VKL!{+49Z1HsnY5uX@9UA7_6j*d^V6S2vn=u^_J68$r}B8Bu%PYP^#={ ziPO4}hwhI~&}Npx>PpH^VL=O2Dt*ch;QZJ2Y6YiBxRl_G<1u{6qn$F0 z8dTR!=7+yEJC6BBalthF-o`W~W+@@v)X6kXO365t?nw_|V2NEJL>13^A^tSRYTM+x zb3t1NRccxzIH)aPdtF>nLX^*tv_m;ddj&g`c*(e^!%y1gyG)+0;0iGZZE@S-94x-lH~=GIuL9}L>!r+cGcdgX@7{ZMdlCPNsHb-kfG zqcfBYZWXRW4cfZsAqzzQP{R5h9K0R~8-DAuzqM1S*~%c4b6o+P$622tC11jb8wMLm z$d^bCpi#9dy!1ziLw8c%wUMib=>%;3g^JHmP#xcPufBhu60jA+nURDR#=ZL2Vs3iz>f^&i1y^|DJhzJ+CyCl zMgap!%8BzO>ocSjOO>K4ky>gGlGUR}3rr1!^Tq(HQLA|*XpgonkVX3Lf=U8GgS*}W z5um8ypl!FhO3fCRorXJcjTQ&5e;O-m_NnK;v}eqoSz39(uW}N!b-1^1msw^@KbJZV z+GZ)4tykxck+^x{bCM4vo9nz#BWR0R>)do@ zhhICJ*uuPe<*DqdGD*-DuSt}ktxUXI=Px^xJe7PWCo&nIPUA_gU6Eq#f%zL}|Hj#; zd53-Tf%nS>x0gXGK|FtQCC^Uh>;LKkzth|%cs=r_Un?>i7BEp92M_4hAoOP%Y__2= zCSTx+15>vaPNiVfGFVCD23C*yGnKTtz};v8OHmY-7M0o18|~HV{*0u$`l|`g-?>SjRo~sqdO~}h9K^ALc%#9c7i|bO=s;3FMc622M4?@Dw3}3fl8q3kF5T2zINFsg*dLYHik=0kO5Ic(=K))62_fNk z=FPp6#@gfrp0q7?5{q(_fme$2da4k51DAET=EhyccK77C*CRXQjBXdxQ}Xrqb3tft zPDS?cP23CViEt4uvujUb9`Ss`Q@}c-dPPi?_r3?LnyCF5&yY^>Vc_Xud$z!}aGp>x zjgz&KDYjj9z)~n+JbO@XtA~{l8BlR)Y3PmilJfRvEE(Hd<=Xee>0IUpBy)9v%gPL% zCMBJ5g5x>kxP^$If#DyT4o(}jN9E*dEvXNA|?!%yMVzyFT zzI28xrYpia{8!iut0@8bg$xl{4`f#H+tt4wnfQ#!>o9^vd6Dt=1jt;XK-!l(FmcfK z?4D3L+ecifgNke)h9PLXgZnCd%_+9gf8J!FuPVIVMQf~7>MnafP=?{d#}cfag0>Fb zy&nA2@Y@u$g=63!1`JdNC#fWrqK;c#y2#U5pBWvC;ixNjzQS_01xdKe_W&#E0StJ6 zE)YKUGmDZiu5pZOQh>tWQU0=6h@h>Lss8CzJiE@-1K`(e_aH&z=%6is*N@-OxyScI zuAR$R2cEPo@QYXQ)g}|_0O}!s(3y&)$gS=KwK`w;v_Ic`n{qog1Kh_dK#)PVZfS1q9Nj<5~t_QNLEkl89c z7&gkw6-(-U6qHpQTNVSCs!+~oZ!EO8OR*|05cAuk9<>GEJt*%&4hHa;B4NQRFgQ;y z<;jx&B6Lxhm%(On%LD)F4Wfj)D{*B7BtzmTF8l(Yff2?LHV0iG_H|WG_V=jtEF28K@BBNXWRmJqXjI7;`naYTiQFMRqE@$$;bk` z?)b!(7YVB;AOM#Ig+gxjIB5GGU5ZXQt_2o5Wn)PW#w6>3$g11IaZgUHW1DZEG-f01 zA)Klv58OQuY~DRpotpRrVx3?6T4o0EEe--%c1}vpAC6lsmA09w$R@gRtmgbRk1pcr zt3ehFY@)yKW3>Iv4x4ww0qSNQ6cklzhnKs}ShHAI;IffMhmneLidW%E7O+~`k(KkK z&TZ-~5bij3+VxUYQ3{Qy#X{XTBGMrm%D-CyxYJizKxd^G0=)5Oe1CG_upz z&E>}*Ge2Z-gQLH#u&f&{*+`=1$K#$tW`1#w^F%^h-@yY9hhXfHIaN&_`2IZL-spko zVE@+g|GUl2aK?r+fJ|LI8?EB$q(8$2sgvd!o+DVgxXu@KAAa9iOn719bQoeo^;xH3 z4j7bNb2s-svx7Hh6wiF+gQITh7$bK)4T83Ba=0rabjv&0>3SI-jGG_E`3qd}zP_1? z(LhA|({`g&1xd!tm0p!JTELZxLaAMEv{xndXLaAKZeKt6#Es7`VIQ%a<6X#AZK)BP zoWyF3d3fu<jSY0G%t%ss|>4(zxoVHkUzA<=PKy&NwNy2TzY@(6+E>(mBjM z4%(s^T*wXO77=nEw8ae;TR1?_)*;(Zt@&XDZPnGl48XdtPmRUDagfMEbK73wMtEoQ zINphB^1z+)z~-G2JXUUZAT&szgzr`sAStE%j5~ufnC#(#nqayU3RQ<$FkRxM|DHn$ z5bOxD?s!gzvG$Hz^M)w6DjHj3e43ea7qlY_WLwEmD3+n=c< z5UFWa>FX^JWE?x~dPzBXOECiKzWFugaNHuRycHpW!qnk47R#_4g8Bmab#L#w;N#u> za@3Jjb|OwmDvCOoeu@xGhQb^c-u*e-Vbp}a>mDd4%bioLbL-A2=#)&IHJugKni&Ue z-%2L24&UbTl+?xm=jG?uPUB_fcy-Mc0~&okzLmO7LJc>D%Mu4|DZ`sE&Wt=O)pSe; z$HD`AZU$IMEB$<^sT5ZM<#H-5p72Q#dJ%FdEkgV;Kq;OBhuIqFH;bKp{f zw$|8n1Z~gZgVkp3<`;NEFF*WDbzV1wfB%R7$b2*T#tu$bIR|ayJgcO)-K5A`P;5uB;wp>S5X88Kanlb zzWD$v$kCCg6P3L5I6VDfdumH`ojWMg z7BE>^3|w`+(cV}ng}0QdzHtZ8o|#YcE2T(j;X)B~!X$*NPv&y5C0@OZdVHd5jkmi9 z+6sN*m}!(=p=9c?JP&gbUUkDk+qA%&*Xg}j-6yyoJ%G-YW=%oc?%u8W2DdwblGc&x zmEPb&7Qk`bw_>t5dD0f2$>JIR1&a?BAZUwPg9$tu);%SGXDrtxd75|I3FpSB*QX2V zluRDDzdf)d%?q(xT>xc0jz8-{(3a$7Q%rA#Nndy24+JwJNk-5_lEgnqNQ%JQtR}c0 zJ)nc4vF(hzIK}t3oMN?(5*rb`G68g#>Es{^xBie6+n=c<5H*z4TOdN>NN?9mQBx$0 zn3h7_H?V_4qPQ!}f|l@C5wanuRD-sr@DrJ47piqam!b#B9827^IGH9#kl0Y>sw`0i2+CV7m>*2B3pf-;vaYnjWy6C2U3-^$lYiGi&2zc3mH+@TU{Qx zb^xr_Yb$gAq%Ec*<84J7P@<@umPx@uTZ5+w{&RfTgO}bj7eniD&<{3NtNHP`yMUk8 z@}#YiCv9zMNjJ+>GkM^?^*}fixZLc>leS$`$%+dkXgj-#pOy&PTCnOVyxHO(>%uM;7UcI)UG$$tCIRN@eLUX&@yF$CvCr!0Ko>hsy0E1aGBE&uM}pL zgSPl7%t2ef^gRmBQ4snhehzd5mo*#nPb@7_V&qBN3nN%2lH=$BT{QfVGGR>#mqW(2 zXo0I-iL}b9AU!)Yw$5X;1PP#RaMxSFva~TMSv~~R^_KSf+JUt08^^DG+saPK>ybrn z*;+$i`9-xb1_}bk5yd-LIr}h`8vOOop8=_U6d34 zIC}t{E9Tb%lZ?@4W~Fi{c~d=UE6$*G%kv|@jwA0vKe0GyYaIUj*CTt!UBc|a3`QM} zEtTgKU)`Bn^F8xD;W4(8sI4ON=Pi4c+G;1<6`g^c3s zkrkPya?8c8(_^doxa?4YS6Sc9&UL@aLaj%P({uz>X#1NT?#c*NH|yY|=yN|f<6&=M zfy+j69W}bZIK`{*k}T497s~P1;I6ko1jMn^u9v#CwAIvojDxJRUoDtRC zFrKtMBm~K~G4(8~!k4Gb`XO~rzy8`oqN*pZ2E;2+Pm=0NuRmv~u)0gQ{<@XXJ@?|`zpJU(m-R3m_6GI!%krd$BRD3KW9b21y<~uu`@MMiWK^4EkO-yj163$c zT4hy^o*k5o6gwufB~gRB-U24m#-L>R5Kz}!+UslkQpjR)IfrVYc-i7B(>Y#`42i@M zT4)cg6_m)@`X;_b@Pp}P9N>%4Cd=`8>N&o!&g)-1rS)m$I;R8>tL7`BFXPX+zhs^< z))^{4CDz9=)g3<%5XK(En zSAHKgxpSC&{5AO$b$D~~CW5xROfd%5JrO~$9YYTqn1~Yz&Mx>-jdR2VlLzhz54=%7 zootw!@B*eSUJHd8qGc)665S3cuE3lH>{_c#ito#4p>h$kK*9)7Z8L}BVK&!7J|#!s zfx9w7{owPRZ5l%pZK#jGjz&?$^MD3eNjdQYHf&m*;_GCj*#1l}KA;_(#DTB5*+3ZW^63d{>IL?3yEI8}{FvJ!)p&9dh zZbo%+rPJ#8>1gu6J>>zq!`5IfB^oqc| zzXM5OZa(hjd6FV%JAH}z4mkLp5Gm_VTqVj?puDCt!pyjKD3^;oI;u$#dh%Z&i}c-v za(*!0Aw z#Yz5mZbn}TXl&S08`Q5r2^yA_2}Z_t)WM?lRtUi9-nVremG3t4It);hq$_?xl4S-!(h z+7g-nZ|~%%3$7ahLGNL%D>-96_sEBqQY`!PC*OuM%?Ldc$&q>hBlONgMxw*|fo4tx zjq%}@fauGcTrO@Kb0>VH+g4t804m&7e;7(dPqGv18r+Q*Fd45k0_}RsRtCD>yvsMi zd^Lb&1e6njJa^k2Ak{;OjoWE;+Yp1)2WyjQ#*XsWMD!;2K%8a9*f+T=rsm&q59nyi zS&^$~iz{XY*Ir!Uq6(dC7uy3dhZ^2hbF^$#O|=DrQk`7ZHOC2FuT_Nu#SLc*zS;H` zSY=(9u*4O)Hv^v|;6uH^!;OD(R!sLY90ZI43#xsX3yWxb6vsq#3_XDDmxbB9??g{K z8I3$#u(xx_M!^CX$ynpDj{PGc0Bt-%m(*ND&n;#J`$9W zwd;-cD(gU2_YH2CP~WKeqD@5z%IXsb$h`v!V@{%cwR))x$Gw0lCwf`p=qYRQk~!ug zW8U5?{irM5Q45^p^?ShSRiTWS4g)MeYC~x-U*M{o=Hsbfr0{CQpu+XqlAs0>SE;Xa z*IU43RMO^7%5}XJdrQimQqwmXR&j>LrLhW%mq=}@cL3fi#V91+0emn3uB;E{mzeGn z?t11*Bw_@YC%Df%(7ABvGBv8Xvq+^}hX6R#5J(gCa4(;mh-|Z?u4wE%Q%VQNk4gB$e4pmV^12Y*P1zt z90d+x+F$?WpTL=6_r+IVzF_q9GKzO1nmlmddcYcMU!46$j;CuFoTSxcTXq_FWbb?C zIayeVFAwGXBU{$L0^glI6pUV-A$5+w-#L$`jf%a0_MWE?!+9u^CgL~P1G>nbd8QKZy?V-=wTR)v>jk-oc74#5U@y#*p5ZVs)=tLt@&9ho(JlbfGg`Hsn~ zA?1(S@Tm|evNf?8sCE>27@uM*T`tOMeob)uL7JpjZYHAW${8jZ&)P0p z)Z;GvZmdoVEA3k?=bO$`+|GZ2tLPAu$ce1OCRv*9e&}7sn!>%_`%SUK3ZCfiDG%tt zA~h;59M&TOUaLE@CRaH+8w*wY+8fzB#0$DydaRP^glV*ZD-~7lU>ka)!bqqhTQgFu z=fY$1K;ShMejx*rg#_!wrouUI8wj}q1TP_TE~<+KpgVzLjha7(3tt(+=>dE46EHK; zjXb9D1d|8e%pSlz)bj;&iP#_os4B-#6yF8hoJRWE~sZffhRFshmyo{XS z{_%j-6S2OVdq1?y#Q_;GJ^2FHb|5Ahvpi~L;P^W&AleDRA?~!`r^^)@+>I76k&UCY zU2n8Ei0sd6zS%Y0IQs?SIF8s93}7KZVM!$4>bC)bqWdZ1aI;jpEw801EYpnwev1u& zorZITm4l(g9pJ2T&bR-Ze*@eQ%T#|1J)pC}debrH6vD1A9QWl5Tyctp6^4}Ek0;qV z0^<}rCZm!_O>>H=w}6pWYk1apsOv55jf8y#>nkG{X66%wBd1JdYZ=91s@>niW#pg4 zHKnt7q0^SZ+D96bN)K@pge>av8=B3pXi>dw8OM`fHrEWoK<>ddf(dsYc)-cf2rm&e zv)Ck!jE)*B3tU@K%$T69jnsXGI}x;XeF}XY{8J0s@{3e|?0t_vQ1EmF=nYfiCu<%} zPRtl9cUHb)@%E_V8xJmDz=>eV9ceL$s6}zKa+JxISWDU1KaUInk`tWZAo7F#?<-2!G^05(&5jw#==Yc(QfS_$KOQ+(29;bvt{PK^(f%}LL zp1Rj@a2H_Lym&=k!2aT^{)AH1sVAT+YAPQ`545jb>HseJESCdD z+(}3w+*Zz9cT(3R`wjAdQwas_ANE~xv)M^HJS+Ax6GebCkz`ggb@g;&4f zi2-uBbs3PZpz%3gtIP=_20??i-fcGSTzdGNtmer&8-k13|7j2D9jZEUhvXg~u?Kg> zRGl-{EAyK;E{_{o9b76DwJMN2A*PXl3U`VflTk_3;I6lT$!w%0E!Fjwt&D_y1?wx7 zD@m}`eS&~<9xqdbi%ElbQ#VYdFJBR{@f>l>yV0 zuOY_tvbSUk+IBhV*yEiJjap!mTcttUQ4O3$D&@jJRnTjh$M#8ELOa+ucoEbLnK6W; zci>4|%*Y=%3FCqbx%dl729)k8Ucrq~^cHsIKB`{df{d5Xy!{}tW*qoF!E~L2-j3mM zX3xw||LEJYBIPG-4|4%}jQEM>jrYJISDZKA;5WpA#=?&2S8V3|q%B)R<&Obx9M9lw z6rB&+ashYqXD%gt*aKT-LjA9y{xF~xjOs3I!0EMoellhWWgf8t1WRbqRpprn);I6ko1SqOpqUw5Gx0bdV@lCv~>Al7W zZLea|dRwA4V|Rp~D+JDNvjd#Lm*XFM1sJjqZXr`^JWY4%`-Ibx44`!Qdo9VKr7dWS z$_b9M2kdb+{*APq$n0~__Fa@;YECD|hVc}$To5RD-WC_~s}DTJ$EiyW^W%eAEGOfE z`1>Yy&zwfk*3bL#yc6Yd@j&~^6$cBAYDZjdtdhsoK?jagJcclXl{79QkzLWPSvdq7 z+>I76v!eXk!-$67s4x;TQ5TR_DA#4)1tY+-PH3gO=Cy_IOZ$djbw0=Au531W+aX6@ zjch9hqP7#r*C12#M_DUOmU)P;Sx+!|VDbPwP@g<{HqpB%yo1(_pS6Z4l%ztjItd4y z8L1BS&M7kSl+-W3-im(OsrFv;fHhW3ss|>qis0X9*bkI}Ydatar+kL?;HgGEg<>e7 zIE;f5jd^;wQdO&A`^~Ph&Da3tUK=kBI zE{xs)T19%S^GTN|=dp2;DN$=iCAQ8Tl-ZJ?ERrJYdZWFuQ1Z5vEaUKk7pWqox%oF- zcKYJ+vb7$Sn-H`W+AZcKV-pUA`Jn9xy&%ENV}R}6{1IHluZFyCay&{afYK(TX;S41%D~%6_=zNHX)aG8E-WTVAfHvd#ty zpfJbfNn887rudZmK>9u)UVHppe%Yi~=4S^dUy$T;B_A~dVUyiFIRA8>=U4ej+X?Pd z4`4ts=$6UJ0VktIiBdbwBNs)44r{B3`VcJ1B7Jv3CE+G;3y%f4ZX7LGSFBp7m-WhZ2)g_ZT$DI20JtpV@8~Ow^ z<0txcFA*1!IcRIK_}*REy}Rn}MQs?NZ#dkIZntk(E8XEW7b)h@&G@7(^-9<@c599& zZL@2bx1db(n|miQ30*IjuM8)HkjvyB=G!smicm?=mWCN7ieu=3_LVCxQ{%cljx4Jl zh^s^45l-=X60mxxWRYFbt(i(foz;5fZnS_a6;%%OhTf_m>HWb(k9-2+9D z@Z5}N5t*odzW$I-N51|f;4pQtamKDmC!S#ANkfi~II(iME?o3JV&Rjxd&C3QSg}Me zZSDuNoN=KzoG)-~2Og4f%L|o^)%GWC195Loe&8P%80LhM7ZgCF1%iqbqg`*bSL6&P z;+sT+wnc&KO8k0cR-f%yHNb1+MQ-1mur54li+M~Af0*RyHWcCWBH$Paw-dBA2RMVQ z`xj`u5kcGONn3QlT>u&SJoW_2ZJ1w8$fF0+CKm>D0IecD*7>AMmGjs*$&{!yqY_)^ z4$5pvP!>s%b-mHvSSWd0O4j2%abocU)jWZ%@un+-wnBnqL1B9;4#=|fEavSN>_yPl zT`~awdgO6>6J`)dSujKm!zJ|O9E&@-{-Eu!q>19*^?=i%(G|2EW%(>p)#Ir^j|tjF z?%u*33EK8*43+E~%$OM;yFE+^4%%Y!{zjo&}NeAOiU zdSt14{!7WIvlLi-pJ2|K?yP%TZprEadzQG2W zUylq|U52sT5_KV)PMqwPzAMc9{FBb4j)S&nfi{Av2EaDIX}dqbAk|RBz`eP)w1m83 zo7CLtWcN-hxcBAX3qjj^-%EGfLQ0&x9(f0MQt*1)2V{2n(OQIqe9*R!wo!Mx^9>)v zUV~ZL%8PSIB>YWq|9POX?#01keN)}27B{)d(cD^AygS*iJHaMK-}lVa~6`LHXO<{&YknqnY>hI=3kO#EEs>6g7zENYuc&QEC66seJLrazGUk zTHLM=2inNSkzBm(ExaCi0~O?Uq&k(^e#e8hDf)6f**D0GOEhL#kH#NGVG7zF9EBSP zW$6CPdcv@zgl!xR@-sn`i^r~lR*@cJFfr&F<>Y`z*f3B@Qs)lJY)McSNs)EE(cV}n zd0R?WaQ*?fmE3Mi&=#!DnD_E(TDF!^a7Qr{RCW!EErPbz6sL%zM0iQ^=qGI<2ci|c z`NP)Y+E-@H99-7SRJ1@Ryp3kzK9fz!&k<^d-|PH(vn!u7VpK-`;KKgdAS;BK^lg%ojox9g4e z_G%23&NwN0E-Pi1Bd^~ziLei$m1!nTzWD8n-+tOW!ZVw))f0O#{59SgmZ&T#44DRJlnj!Z62SKt=Pd(kN%N*D1a~ z6Uq2pDpXG9AZAj0zJ>y~bG}5UlEPb4BwR_)ZXWPV_gAEt#&OaQo1xnIZ_?wo36zEa z?`~ESwidr~OJ}HmV%u-ChgJNPO&&OA9>`w9^w$$n&2;+h*=HUyNmyJtOuO=n@+E5f z{OkOjJSObuFH&!)=EXz%zN(W2+ZF!x%moJ4#y0Wa zPk#)Tg!nBr0+;j5p1cS%(pUaArn&?2${AlZBK55xXRdzkk+DAw@^jzZ`zk+=Pf>vv z6E^iFp3NN#G?s9pn>^6sfrA#@-A2(fFP!IVJ`1pF68HKVJ(QcJo8S1sfA^N;EM0gh z`8>bO;?}EA>SVSHY`uu=+_Kqw_H*myS*wTK8t2T?#dF~`RpImz_QO4_Q`K?uK;v1x zrC|G3D2&OQTux8$T`xLS;U(D!CHksXP&T+5EnrcKG7`RI1plxEghoYsJ$fLWX}xkK zG++DHH>`=z>ajLnkPC<8%72uec2=f|dl0i{@9np?oOA!j*T3>vylk8y8Yf3RiI5*$ z+B28`gD-Esqld6kWzC82%)e%?#fK%mKC4e0f-<%}IHSVdU5s4aBvZ{@^ng=cen?f$ z%Kq%G`@;c);w&|uD+mQ!`wmT)jzZ*;q(e!?k{Y*h%Bd~jqq11v->P}RsA!!^=*qmf zgqz}$0!HH(E8|eI2f(2y00IPUov~(zk6%t^sdaqLfWa|n>k>OgFAN8rF`tC8b@Jte z5&hsCe$}oy5Lx^Y{-SvqA5>L)H&*=W30hOzik*;ekOz(=q_-W6CqGcihqh}e%I4+%v4`W>qRk)Is>{{KHxe{6DCatJg8c=bwY?Veiqr#F<30kw7Z=B({sO6Z9L#I zaRLyFJl-SJ8H)F~w$uR`J=R7r;qEmLxVvFcWxcu^>MA-8F&g7@c;NZOjgwJGbvEck zFey(~z&U45|KdDc%=!P>d;1u>lIu>a?(NIwBTbr@T*_!^WV+bXmfNxdw7g^aV>#<0 z)w0@(1NUfU!|MRSQ*0y?Lx5#NLFi1@I?bV^wqWeE4KLsg0;e^xkb$tkj)4v0KP2Fd zWGl)dh-cRhFn=rtjP3Or3t=@*U?~e2QhulE)VUw;zI*F&x|`kHTV&s=I(5G4+&WeD z?zta?(f?<3p8aQ7?ls2@IBmc@9O|7UP~CCamJiwnQf!n56AfaF2&c~iGSXz7aH?R! z30K@XDyvQPLCwofNW$DoH7TnWg%)+Q2cB1SpE%G-BnYLGYGUSX<4mL~%)3|dSrEVC z`UTBPW7a$QIfi44EarsHK4|Ow1M=`zx^Y+eFlt{CW&J%*>7icxfP=Qx8mrr;BRa!< z8jo$G1-dP8*bP2@s73I|$^8{uUthftB?8VV{^CZ^wm1i`z55rx@)v(A+cU+D@*j%B z6z00Q_sZ&%aq$g=3y#j@yO`#_^>Jf?@lzklT5p+KK$hLHcOSg_MZVU}$@=4XcVU&V}QSd)g+u>@_!q57pyrP=rLlCisAS^MgT0rTp+!bf2b z8OLIAzx$K-uuA%;k7(6xnLpioFPn0fnZwLHX>NREE5>-4qBnWhJIpMeDtg~rE>qgY zWp9crsw2n&#)QOX|MoBgHN&}Q-9+hU`R>h+O(<2)B1xnwRULYs9{ZT6?RXl zrb&a^kPyW^C8|}iTdwM>g&x7mPLRo=zup&u`l^5fLTSFj?(CS~%)zG#LEA&Hn3#_- z%o&?G-M2DiK`Os{a+8}r#zLGq zS2(*N3ta=b&ZSnSwXmR@`{beF=!-oECsT%O1LFMALoqg;MGN3O`y}f_Jl(n<6S!b4 z$mXbYT#``8K(79dmBgSHJ#C)4LI*S{;`=+{5^nlbmhyL!h#_>~$Y3oG$G7Op(VZ@rO7 zRhC;f?&9vrBwt)8dTcoD7U*8NbeT$0-zgR^CP>yF`Ouu=N#Jv60`JSJf!LyM_Q10c z5HD;#QOJVxRO^pGhcekZxQItvwV*A4Q5v4fE8p{4t@Dn%|H5VeZOll_;aA;@L||ub zV?@btsJF(p6I+1~_Mnf$znDb5b}ynaB3f_mdRxcF(E_L60>%83w$^LyAKJtFl6i*t zX7}CK16|&)q%Ty5@vE zMKR*Ku{!2w+yVn3y|mtGfN(3|la3Mzwa$c3^NH6AEkTTM0%l7{s|UpS_}OY5?{U9y%Nhf=xu zETbIaT~+qu53^o`A>e43B9(w!m@hSm?<(&u@}*d0XlS4sv*R&{X{H4B1JZy z>TiA^rfSfpicCQ-O|2c8EFER40N@D+rf5L&0@FQN?%VobZFXU!=Y1`85Z7! zYzRgF@H^O+c*vGa&LHz@=`x4XCoLfSq%A5g1Z}x_AQcnK7*CnZZ6aukH@FTEaI>30 zR28&!3?n`u6(Otop29HD7-M5$%uj;_jwGbF9ed(1EIFZ^93DhIX8L@y9J>~pXLnB+F19Mb5#!0xyNVQTG=87iZzKp8I zCbg4>+6avx^$;sKLRsl6@cztm=0(+~O+H%kWgPAs7mJclbY_{!h3tExND$w~Z;?xN zH&dS@7HMn!>!x7nBs^(*V7<1)AjbzJp|AQb#t5wg$BJqIacmwfa2hSZ3nqfLcDw#t zJ1XipXnU!c0f$p*ZX5rkEne&-DLgY9YrVM*t?-x+zx+z|v!j;=jyp3~XaGkqI1J*A z2&dBmGUdv;=TynGja)#Vqq54TImMH}TWhak_Z4*D$33PM>}C%+c8jll4JQj{ygS`o zuco+Rni1m+T0my;si>~OxvgdT(xxI^e;&V}ZD9@{grKc|7c$JG3t?$Ce&)mPTRC*W zc2s1=h5L9tvdzs`_(|LF^}owlKU30$pJ%MYm12*6H8p5kSa)##;+L3E&&koAVP-w1 zM{WTU4P^VM{+2kl0(F}zGDWL2$*SZ6eq=6NSONBDwRKH~y-<_TNe{SI6}#nD`U-7- z*02q8*bT> z58x#?A!yr!s!e!80l%Wx*g)3IAQy@FfYj&(1H_D6987i)V?;PX3yeYAL1U92_!F}& znAs*=ft|PZq^;$;bqvHk5_m&0N@gE^0nc{ZW`;Ukh`lH^XltyGy*l=-(o7DJB_-b8 z{03YU|H5zMBRRw4leS65ACXS01-ygCXlzr-@aok~c&7~w@I3Z9EOYGD%O)oEZ)&xi zCvkAo#uA!D!_3EYwk+U8-7rMrt`9(77?1=WDvOS?S46W=>2M(-k^PyKY7?y@m*%dF zDqxe^NkdK32-1C_6&#^dffb@4bY`BjtXV+dTb(SSAiZ=b`sAF?Hrxd#f`U#i4-LN6 zAKLY*rB*7#X1Xw$WhmZn!P!76_C132XVP)mACL!K-t-w}mSY+%aMmnPn&PuBopZdIV1Z@prLti?x+mAc8 zo>>cYuUxuJCH2cGR%=mhPw^y(b7;z7aX}UfAhf8PJ@5RVyKLN0CLSnwV$nc~sag{$`Ew>~KU4OO{7xRfZMWSAMuxm(w=!ope0+g+ST*kfRUqYde81&feO@Q>n~ zw!En5esU&fXf@=bUKP-k=KgFd%^J4BH*G%*7mU4(((nxej^n-q59^dnLaW&|dk;Zd zcGu6n^kU}x5*Qy2V3ftlSszE@XY~qmV`?tD#kjQ=Yl^>~eaTLYTiG@KtDMmoQ^C?+ zL}S#b7Z;UkG0NC-f)>d92*b?oWjfu7hD}zQB6Czc)rXW@pCg#aImy0Hm|GstsYyOt z1@snmvj?7?E`{B4D}9rMH*EuZu>xdFR9_TO5H~dp0CcYiJUwoF%}}xk)&`slL$_4R#&GR(=d;ik4+@*) zus|UKOQAXqnek{+ z9?CqY8DmZPfF#td9&n2XO;K1NSM_D&!88*LrTVAGFPtvJrj>=E-o|+d5PPz4&zc3S4 z0InC#LsJg6LW-&hb+ZSIR#v#3aw~l+#J*BkF)J#(MUl~QwboNb1t2(ph&S|Q$G0AEm!r8X#IK9He{iIJC9e+R9lBxWH7t&+}rrN zuiwyr?Bc!2gW@{fhO^%Ih`me&*4}Iyanthe++)12{WwUI(hmLL+G=(WX8OiQJ;7AS zn!TvZn8bBSizV?Kkwy!gqy^xy_C*mGe)0LW*Ba}#W`?g--86r6>yQ4sb$iKRku0+u zTh=Fj-7kW1^O2(O;m>~dXZe%#_s#6N0&_)LdT{y2)}f$z@N~61NTVFF&WZ&{6qPe< zRd0;6ySWrrssW4QP|RFkgH6yyr4ZXbCP3NmTyQ z9|Vh$5Vd-NUoFGj6vJw1EQ}U7n-<7TrauDM8FH+?NM!QhGe$hbn2UG(Z_;9Nc=v(7 zWPaPgm$ccFEjU!OR5|&>=l)GLsQ?Qo7|cj`UIDX)d;2f-;EhdZ+X6D>%ECd~8CgN9 zWm8+`3v*OXab$#A0m#r3=7L7j*q>Eny-6Jxjk>0~j#%N@luIf}5f#!=Xxhf^HI{HR zMkZDiLnxO#jRU4v`!>A`e92@}C_*Skk`8GR#ArTI&ddmZ2~?f}FJ(RF72pkar1F5k zCm=oC84k4LakRjhvVfBd!qJ89neUDI=a~%`z^?j54?A>{rgv~orS(26{v%C`Gbc?u zxxPVtF>8?G@)bdv9Un7)519Xhx<}KS4H=n|lC#Defp+M;)E87L!GQ%HntD$Wi zU;vBv!muLzwhI_w$2SfiGUmoYO2U%_`}r`1$HsvmCeQHPo}VCE_R+rEWzO(;r$v(a zPYx*yqGZQZ4GuqM64jWa5~d)Rrq&KknA=4Dj8)#e4}ybOzBwv0H2d3s^tb=154hxr5*2ibzwMPFa%9|-OqG(} z$4Jkj-vy{VF9!4`i&n&#@N_&Lk3ST{H0@LMU5wGoFgCha81vI$fvG4Vqe6po)I8<= zs?JgA^_rOwhP`79JVxe%RykRZn8*p8yKP|g1*A+0XMdsiKhREEA5YZ@o# zk8&XR!ucEA>ddXb`O?SNEib$wXp1K7Ja+zSwzm!J6uGvT-TKn4=gqy`Y`r$sxd7BX z$+_ae7v8_#gVAnsZNOMR{T3imF$}`me2&4FoUCFB6;>BXGL_3PbpoA3i|9Rh;6xy8 zQj^d~54aXV>K=}vNJ43SCHc^_4do8EG4PgMdP$KHE*clleKjlf`Vk{!;rHbxV`Y|} zzbyL>RQr;{@AJ@ONS|K0)rVVeE6o=Tg0>d_keCB;0jb#w0K^!+ap+)&5XSb=0;k&o zn|OJ}m8fEHtypt2Y(?Wj43BZn7!JW8w;pFUeLhQBX|Ws!0`MU7#TAw3x%3^@>95iz zhCU`^+bOqzOu6laBWV{GyGF4Pshk2@Q@jlF*4nGseFfnJlooZf2cCt1c+m-|DVG9J zu>@&R=4~@ELNyC$&%zhEghu6)n~l(D4m^#+k)8I=IrA>xKz{iXWdwCWR{3^rrl6n& zcug=KV(@ly9zW2CdS0VCpGrcLM^`Oy>S`HbqXkaX0`8%t!7Z4Ox{29E_MAN9YRU~i z#kjTHdh~3<+h<(iO-MDTayl<0&=KP#O$-UlMwC-(fq{^oO;US3Vp$UimJ8Y@4KjI2 z!={0VAf$?!vUrDoG400!iF>tz#j3AgnIiI{+;ess(B_}2mK>C31ppTl;BFpWXmK@*)U0!A7qncV$}_JHA$<z<4d{ zW)B!aI)hTT+)7`@9!w3}u(ZN_KNDF#AjRI|-Kf^QTJG&wV(?)$!;yow8?4B)CU=H7 z{2KAmx-eN|95?>utM8w zXh@G_gh)Kqn3>SaHIl7RokL5I5;>Wp4B8IMWw(cI2wCW*p9k*# zVy&d@J^x(6$9U5C9DRy!R>Gxce!=QTvvbcfui=!NU-swZ@>MVK*(6_QUtK9_^_7YF zA2JD%PesAQX{QBTa&Hb74u=d7TfCHIu0#;K937zzSYZ0WIWyeq?p|rk|e3-KhQ$C};q>9mG zvi6H6cX{|MCEx|$d|_NUxqtaRsM?+E9Bvh^2zpAn__vz^|MPfGHz|?%G2rDZxsCQB zp_}VPni_%H3X?G#EpSFHKwj_a*K?yAUw%U83ifMPT%q%3+nDL|yhYBP%c46q$mT27 zelP$XFW&fUP%2%ZqT19s&wPZOaSO7v`v(;nI2(v^1&X+Ev$7*AXj>nsP~?y83FpvoL2H!E&7ARTf?vBjsk3LFTvPleTvPDSp^; zBHThHil~CVq3hrbg*&YdtJYyE__i0hd7D7yyj-E0>&3&J;YypaG+N-SSwI&vCz``K zW?@0(I8Shu-O}#XI(A@;-t$-kcNeixYeO|-DQIDVxFvC6UdUu@IOP@?2->D;zaG)7 zvA(!m&^A){=K5xRhzLTCAZXhwF*Z7JAnm2$#{`gA0n3YjybBQ(lU*|euZ=-lEXVdL zuWN)qW3k@;8W$4M_RjBq;D7nRTb{`oH{9ScOf@k-&Ouv*m{xG{+Fy}6k~2I8ZHH}t zq8M3_COalSMm!|U@UpWS(5Ov?;T)4RwRUK-d{~b~5w|z5Y0{w9rA2zcOsZnHT-8?# zy`r18*(5m8+j0vh6e{%AGrD6g*s$ahw;Uo6vz>9!7Ktw7#{AHkm z%p@uVjuEs4k<&2QQJi51j$=AC7MO}Ai$Z!y*e)||A{mCQm}xB_GgaK~ zV6p1!6tS<+u+1TR;N73(JDt1&xLerdv+#q`+{bIz5VSR=586KEvchct{`1iH@K?X~ z!+b@G-uXFx@44#}=i7jB=;eOrZ<jkXz)7k11g&U^etu$1j_lGNBHpwAV*p4`-%mO6(@Tfzw{>X=APWc>F zwS3CLD7#F@oRNfig%-fQNAVJnHmOOdqz7D!Al)oGh9U{2^_AoUbDlV{4c&pic0Xy0 z4~R^@@1NkRQ;fHQjt*b_4yOFKU-(9l2fwCJ>OW@I&jiM7-!>(`9$9qnr~2gmNrnKF z<1Y@0%}FT4K31w~46XMSDylxLvF)^2K-}(F)sgXatTMWp+iq|N6uVtX+sN-;aj{yP zBc?}fwAnmdzi{xdu|VBOuXJsn^Ozt(5R0PH;CZVsO&t6zLBl?p$fw`MnF z$KJ_x4tNr0cuwdDcyku$Ub%FcN?H#|RcI}$e$&Q{Rxo6UG|@;J`!jW$xQaNzZ}z|g zbz!oCQo4kt~#18n`s|qqf zXPV@hT#PUCmly*!8>Vs+sIAQ0r;Z(Fl-<}Tilpj+IJiK`&g^Pp11G@ z8a_{^dS5w|z5Y0{vM8_~FRW+u`Zl)B}rzFO!N-LMTlTWdII z3kvJ0_zKl0g&r4>XDpt$e)uFy*P!jQ&YC+EUUZxwm&_ez@+>YRgPnW7OIkon3+XXv zdy|+$JQ*F-NNxdq1V0iBOhu~vJkxL{RgO2T*Bq4(XENPPh*v|t6|%@& z(FCh6n`vWmj^;%)p8bMpA*XRYfMKdNb zUeaPoJV&I_0w-qy3sKdRwuCjylJ`=FjWaIdW|K1C2~XN?VqV((*S}%NPWYR)?6h%> z&}wA~{VY{HVBz;Hx4eHOs!^(pL^YU{uPS;TIS1w(qY)T(Uky?xD+!P;1b9?O-sB-Bn$YO!EmXKx- zJZ)TPj1^W*xg=0kPwSn9)~e3WtNRtxF*Xh=EvRO*H3{01ybi_{*KI(>(c@R0@sO^A zuGrTmQQ$C@vyOkveQ*0FK4z-hOD69vVseml-0x;p-@ z_MlwxL0gCG%IrJ4+K^I+lK~k@zZ_JCYkb%vbBZiNZ9G0c7C4fS-g>l$mF4a63)-TG z+DpR^4q(OgL0gN*;qgt|XaRib$9)EioDbSg2tHlfyre^;L0f&nl#+B7uoi+1gxtSs z@OtF%oI)pN1Bgr3jyCUIbR4uTnZuEs;W232u=1m?$bgd_Q#C*PF%vJk45-sYp+9Yl9|R zEqqsl858~`Ctj*TYEid(z&P823Ac2<*pwS?5{@{7xi!|~%=MDhM@K{f###sBRde7B z{r&&-@BiS7o(w3|RwOhG9Bm#EmfN9P2Rg#vI{s9>MZNGig9o{ZbP#Vu7%k9Y0n(w| z(Rd;tw^)jW2g8v+q!@?yd@(H63O&X`Nd)c$Jy;Vn<-?dBKMTnIl%!|=WOLaGAZf(S zQK@g)CL39VBXdF1rCE?WGpkT1C82KhfExvblBnO3tNL2T9!ew#LRGzmjTJy+B`sXU z&3B7`8EEpK@TAx}w-m7+K5!sy7xk?I78dvc2PEhC7`{f(vXA!Nc?>m?)D~n)wV-_j zj}|!97U)^-o%!CcWLIqN-{Xi*IEM?#B=568{o%>%)EGt6-M8fBrQ?_eyiHawCOe z#5s!=aH4c`Q&q;}FEJ>XgdsiRniA_--s zZvYP*7ulx1gr5VCl>e*+s+5rfOwAPpazX9JKiHe@&^B$2z}sS@xR#ZIypE}QcD zWc7z1;OZEX;{%d#tNI?b49)$=imD%PY#lAoWr58u;EBTeo>V`y=WqR{JBJH${{{Wy zw{8?kL(o%h$KX`EWg}sTndHdV%A_6p~$I}8F3`CNfaAv;3hwv*+ ztG$JpwhGl$0o~8c&7mp&;(~AjLW{cD1J6J}`~oze*nKz&<;+)-4~uLw6%H(oU#xl& z5!_#%eTgpz`E{69c#Zm}`~*-#5nh;6Qjlx0O1J!eF)_P1ePg4vX7cCwDyLr~oA#M0 zu^2<^eT9mu4{K~YF$-9c6h?+qxfDuqs#kbd!6}eJ$tu7}skuWVfrhPf+6JuBq)Bb8 zFsqI2s@N&l35C%@1a#+h+gNxc0gYj}<$@oVwz#+oAf`YC`H zCK$#0J`f7rs4+$E@Hde7`Z4bOus}o5mcMmhsmB`EnUJqX#X@D_G3v4qVQe@_3$#L> z?Z9N3Ds3uk)FeH|L0k9|!A1C`s+fIv0t&sx2Sf5*`spwH^waB;odUjcP*`}J^A=eq z{A$J14GQ^&7_>hlR>C?Q?g5c+>+8~BP4Q|Q2X)&4n*+HBv2i+xfWDl}Ctx4~3hUCPV;}X{c2+DP z`%@Bq^+dY>h;V6MkhQ6d`j!<6tT~)yTsvRUeWQ{KxHGc~by5-`tsZcrfKcj|s{$)T z;n|gu0F}x$u{;y$nQw8pF60Xv&S!jRDzc1Rh!y4uR8b9wrwJr66~H9bb}u4aniphB zwV-_jpDGL3lh8(n^htP$E@aYQRBzlh4z-p60^-0?d!(NO86ZG&VWum$ zu-nKl{_GgE9X8j9aWWRzJQ*>mQq;3Nfp^>dHfO){U;fU&*}msY@yoL()roaB^Vmxq z_~mjkCk#k zSc0}quUnwOqM$9%XS|Af6M|D50#<~DQ|weUg;LV^nxnFT7{}Nod}J0NX%EXm z($pYM!Guj}V;P1dQ$n-YDc3O$C+ClYhXuAVvYOc%1Ay{!LcU8+?f&=vN!yziS~L`K zHHyW>ur{-hV4)-`?AGbh{X8F^v|Vi2v)?iXZ3oYxm5HGp?!?;ZX~l$GW)OhzGXAFR zdI{e_&=&6J{0vdRdBuGhdmvdwU4qIPV`tW~79#3M&hQwt9XMHI^I5Wht0_xTrs!^m zrr7i_b@&=~YB6mqBHYR{TonsMJZFsQakPL83X;C*iFN@H;nKVyYg1J#iWLgkzlL3( zUwF7dhPRRna%W~0>ZByptsZb=HPXA~s=x|Scy?tZK&5g5UepcWgw zB67c21r!_^At=)?VpXXJFC{-OemPZSmeG5ddg2RM0 z7B>>_AD(;T&GpPJMb5JWzHjnro8Pi;M_HYBDJ~=ODYt+V{p9qHZBUxW6qmXq%!5ekqUXR9V1^HepV8svBu(xZo6pLdhz?NvXL*BY`e+ zouk?!wy3QztF1~^u~V)SiqwqR)gO-~<2>JL zoR}&M5zbr9K3wlhR#BIsf*u5} z1^!mOT1Rq*$DnQBnHt*$EI>Mx2M~|3+0}S=ErWPHGCK{Y!tqfiG0SD7uNOCQ&2XM`(dDXgg^9 zuAuE2exOc4X|cMA3C-jK9z1du$gPK88D$`WSHm_W3f$)%_?ofox*_pu8g!bJ5B~4(`sRPVjy4PLA#zaU z60=F(YywdhWt1>QOehE$I^s99S>=z^^B1XovO>b*!zvsA6tcAAF>Vmj6d1AU7C4fS zp6>o0n5;7a8LAnMndFz9W&W^&)7P`Evt zP^l^6>I!a%yqOzZ{y$xRk7A^Ls7nb#!QD0!+k!2qTCBGCrtM_k8T#N2ce1uvpwkFGdJ8yV zIk#}g>X0Ncj@QPT;wee!W&BvF)|MWD3}#eeG^w35)SX3fyX98;Dq>$@k!?N=B7CpQ zMOu6ch?m8kYI8a>X7+RbI_~?h+}djM5lMP;?GXr*(}BS^ZTVO9=D*JFF_jZi;a2ti z;m)vd8?(^@XVU^1)hbvSV3EFO%jN53L z6;6Y;_p{AP2)Oj60yju);aS0(+rR&O5O%a@xKH-jc2X8_CTt^f>m?qj++~)AIVx-u zL&D_m3*jLc>=MKLFU(T|k<0=f5L1)7)dNOyy2^CRt@Mp7d-FxM5%r@2%p>-w%K(J- zXaL3?OxGgDQdFXCiA}jrQN2aIh(daE<<^TeHjWlJ(-zQqNen?QBSV30Q8I>&(1cXu`%u#JHKH-lyXnel0L9@tst5su;9jpU1 zDLFsFSf!|%P`7%(%&Z^pi{+}mNs<@ZrlkNg1853G-MhHLTX8nP2J)r>xOF&PU=)i# zF&kHh)6LS~w>8<5^VhPE_C1<$m?JQ-_opPp5$QxMuo|Rng^c`oXP90MNzh`BYUYVn zaJ&@Ary+}%Rp#!?m*&3AbMk7osGB|TEIf$Oroxd`K@!SJ-vAysHf`gCO>SmPSL*BS zxHjX1$s}KF0FO3w@N#F2CF&0m@FYQ=Dz9Do^2U%ahGEVNXBbB@#xPT01ga#|5$QxM zfO(V?uL?;1q;kRVB%PYtR8$elr3{|hITg-lk-1!3^00wJpzoq?_JA>bS3GLB+)7`M zG<0a&#$oYf8o9MN+)XGkythDP=4&_2I__=!sCd}1bUH`}}Ug2}|*;~s_PsgCp$nsb$K*Ci< zl2swHIwXy-IjU-PXio7?*f*D+id>pIvugA=sY$SFnnsW=t4?r)(n{4(EcE7!Y*Y18 z)^X?A@b#Y{$f8~|fWuk{2om|@&_R3T0wxU+c)3BKSHLm>@d0U3FH}lE>pt3U@CY3( za5gMZlGigF+s@#)Ex0U~ihQEi#!%&V#2kBKfjpnUdr9w%Ja(z0fRnXAxYGhB+AkgW zaVBYrJ1xR3Ii42t)w^O~L@G>{;pH(%@L$x59TZ!N^vVm37EcRBG*LfR7w0=nQrhy4`H&&@TqJLw z;!U1ma2wMpvVap^!V*E1W;$jn(4x{Dl~c^vjFG`63V1qMQTE=dm!=}iSa zhBLz$#;CzK=hOdccjkFKX3Wyo?u42$0I8_} zP;$EU(FvI6*0;a)9=;{=Lw`Codu;=x%jHRd&Bk3Cro!5epzZ(sJl{+C*;|*r7A^Z| z->1Hn*(W5WO28da9=QchVv?mt*UO{{qotnEbXdl2m@AX_`#TKoDebLLF7wGL&US_%-hrFVSL z)=Wg19Fpif|MIOVk}N$kG0%v=!OY<~ke6SYn-sSfM3t6EOZYrGwo|Gw7684BR zTHv%SH(y{}_)R9IFdr37tVMDESEL+eFeLA_SaFG9S6%F0p=?DfdW8taRTg0|{l zk)SId3fhVStO>5!(vG=fCdGsAdhlJjGyAzI_Mt>eku{vfY|*n_1c;ReVV*Q(ghV)Stx4?! zA@smks$!>H5{lHU%Qg%X^_}ur#U^>Hux8zZc5sUn8(;;0XzTxPvl1WCy>Z?5a3NvX`s;K~4L0jX9ZoOQtnr&&nKqy@OcT;$GO%YX2uoh-B zZDIA3X1K|9V1E8nw-4Z}E0=t)v(KBHZ8yUor@3AP@W4^22Jpt_(E_Ky0wg-fT3Kln zmaeLf(xjXeSKhU~jR0$bCvCAQ$j#yH`+sMnd0Vi|Bn{Hxic2FauoJJNLkkrEm)jDw1(Hv=RqF7!&htegQDj#dk}~a)s6R|JwZM7fhIx{p z`WYV-niVqj`o(qgG>N4(Jj$6|q|-$R7BP{%m7Xyl-6#`jkEG(nCJ@Hq9q z0Dh=r5|4?wUYO6HcMyx0ZD3zL;m_{TLkS#-POk;x8I^HnRZ|(R0#|TnVUDU=9hy_T z6Y{1nROHg!nN`EKNlk)X(=>wg_n;FTp|ny>9M7G$0nqnSg0{>N-?n1`GyDao#;cqx zDii_NjYAQM{Bh_Yay8VOLKOt(F7RfXQ79VWW_^`a7h?!quoh%?0el3H7C2KDh_gt@ z9qZ1w3?tzcjXR;_4t#zXYUUpQ?mXs{$&5K;r(8c~VI%uTWr1eMlXUARk;c(p0u_6t2Ei&CkWb3Cjb*Ao{z~xXSmcUm$-!!`QzY$ z*)`vR97tr2bCD5E;2>LgWS{`Zm}h6k+#zG0WPPCsfBqKXSC|&Sge2=GFs;WXf9yXv z?!5nqL214c^m7t>3P!0h31+O>wTE@3OApf6bW#>*g*;cI+-WFKtoP<^s`w0QV$e2e z;B2V|Qz<-V}STzU1AIw{G+-mWOms5KB(mHA}f<5ChQo9%Ap+g6y8bTb~M+=+@3skR1cICzYh~8h^ z!$yUlw0%CC>^bx0C${AkjkHX6h8??$8~imh@4LE(`EqUgLT%I0g*?K}tOcxSj`Ph) zc71Wv7l4DuIVxQ~ozRB;S^P~$0#!7r_hl|L9#*OewG9mzu9_l9H_PG!Bp9l%QuG!U z*`}qw0~5zj+P?3C_{;Xhy!CTXDSf zaL20V6XEE@19k$);HJh{^0_RQwgEiSiVJQ@vYKz~9x3;c*{QKWGvrA!vUqjS;-Ic` zRB`sae(d)MTX;+xqwvpbow zSnu|6@wjDxG`YIJNDkUM!gXSQV;0}Jg$wOCiAQpV!EH>Z$O2Au2|FgLGz(*<__=qF4p)ELFO6HjluQwZK5oHcc4~=}iUS4^%F11ptK+5@VLr0Ig!XQt!)z z6HumtCPG?0;6?$#XS(I8zQUW5MFieTtV z&{h!ovzatc2vloH7n5;E^aQU*-plg`c=g)_%N$zvnd^l}>Ccp^A8l+MEpXN>Q2f@! zzaBZe4&U+Lw4IopnR#xTq$gpyd$?}Nz0Uo_RAOe}Cv7oXy*7OwPx_AOv9y4dUdgHy zHm!h>z>~5$D&2QEp_lQ)g9?fKQTL5f>(5+hKAfYrp@BzgOg0u|UlJumvsDd2nr|&Qma$3}jCC_kR zHXcU{oGlBGs4H$zQ+_w>#jVa8&c=zNhV_s|a7{?Lf6|sOOZj9INJf-1Xn`XM>FIw|PYii<>nWe$&zp{}2tYN4{+=iaSRUwAJ;qe~fYX7(v_c4w`VC`$*2P zp?&aTciMTKdY|2%AwIFESnPYJE2o8VcdFCmhfJKv-5TzOMqpUW^ zm!Od@-Lc&GV6tMYGv>Vv%gvAAm?k&)8B+!Ihp9OFlk^i7bEvgt{G9nU(I(7Zwlo(0 z>%Q0c_rwrMYj4IgKuA$?toP)RwY^GwPZQZ5+_C8lTR=ufJioj;_$0&8Nwq&~Q<0*} zkaGeE!#HjcBbq>!sIyQFUQsPlw|cKkR*UK$VmpsALe8=Ux>v5SY$W$fmm4P}vO4I3fd$7WSuW<#gsd;K+UTSt zLRvlGMs=G7a#dg9)RVcedNM|!!q3$UU&U+wA;T+BU8rJVyDwaZ^zf4wTT~13*H^Aj z%=G2+H^AathIhmOmXs)9Axm0ig=eJttC;{=_R+pOX-~?ODhYc;8ZFSYK=U4?X4}cs z@KD^^6`dGl?(mM~OgS?z6uYRnzux=z*&Y;vpHA$|Os?Gev2|3ZU;R(kZHk^MAkI7~ zL^89OO;A&I!@qAeiEczXTNap!y0V|zQtd;WUaP%@IjVRYJ;qKTMD&u=)E^~`sZWy$ zus@5OfF-IedKS%?nX>AZTj{HaiwcB>hHdbrf!}=j8y?0AxWY?gG?VYx`%k|C=2=*q zrW1C#yFdBfwW7q@ho77D6JLJ))yR)Y7AH&xA~#pFEyk7>Le5l^J@akPJ@~MP&iqli zRegWBGc4T3?9p1Fxos^~8S6`=^}a%zsNp}SAcPf{3dz#C^B!=OK>6VrJubH7exD$ zxB{K$=545@$pxaM!apyYMg>XufW65Ov<-{zQJmrMdmySa=8xI}M-tLgzl-ry9dM6h z(3Vfx4lXBKnLoSmkirw6w`B95D zVII+xT**2L!fBqm)dMCK5FCYTNbD_0aTKdSMGWoTM=Rh!O{WT#XUvqqyFjTU6MdBM49IV1ceHEk)9fgWY&ZbaBxc2?w&Txms5p?P-P&v!- zspgK4^$=$r!$XL*c6Z0T{&PAZSl<$k&Jp)A% z#qZ?cx5HGBAgTB#bl%2FUw#s2xKIAr_7E0mt$RA3yJdLIQH45JsL-$+u(Z0LLJ|$PG6yyXhDZa1nX;-~QBkt4D)XdkB;zscv6K z&^Gybg+UcYgwth#nW)3pFOarEhNFb^l4jXCs^x;VR)zKysM;WkYDW;Xr5=G*Q`0td zaas%70&5mAvvT`S_rAC_ahqY0f7ayAy*7PszLrm3xp8-GW}N%%fA%lX5sD#8xmeJV-ju8QYC#FQ3c@ZR6XLW8+Ikq&XY=tNHx`8@ z4%!xXtheeV_L|cCWw}Cl)r46=#0ZY`BkT1|JTN+w1C+@_3hJk8yFa;&nL}W*@Z04G-+72&3W? z0mcH3WPihig0C$+fM7p160=qtN9clFg0@hS!iB6OIm5;+5I2HP)&gl$_sQyX7NlJd zL0kE0>vn_A#2NWxaTtGKV66LZbcVe z2gIo(ykFHe6)CzOwMM7vJTwUNh^FL9)=>~nXlYTmdcdRtS|qnx?G&*?pn|NFL`{Bh z773rL_3(3*v>=ag-=peIZOpPz~f}`NBo3Rq+$Rk z>4londg#zWsfG~8_R#{T(gKrRgC}jHH#Ahli{EA|a1{zrH-QKHFGAle@T4ua)uj*G z%H-7`J<^Ju6l?V-ZI6`s$n4QupnK)2mZ>BSbro=euH(`QKql+%wO4TZv&gAZt$XEW zF48HKy5*|Aj69e~FanjuQi>;S*)y987-!5Er~V57_(>}?aPHSv_-mE^N!!WQFI$ZJ$@%!I?yp5X<8NAPHYQ*MESbG4wYPEb&K!(PCXwzv%BCiE+--^{LN z7mN?u-p-3Fx89dK@=x0CqerTH zHRGw6?q${Ke&SVQyGp;f5IF&(DP$%z(gUtVkbaDE%1|Vstn>}wfn&oqa6Q98TNfS_ zMm95&vK8Z>v~}WgQ{!&#B53}wU z=ccAWd4@kuf!lmoKC})Tm$cXbx3T$6TcEjZl>rB?b_vdNRMm1KO(fiS93feM)Ge&k zdNZn8trTTSX!d~HoFHJ@kWy1_rLQ9P6$RX z#3}eHjW1d~$&X*qmf#QU7Z$m7eCEW2ctsTV-l6Yh2-@EFm#q-A&G6nvM1Z_i>{YcE z6E8~e`~BEPhEPFZ7Hna4=N$2t7_L92$I=2}Bw^_Y ziAR@DOKl_DR3uDv;5Y%uf+5T+G{s+BsD@yRy43^bARw%K!mlY8%i}W13bIgz=VbSV zNl}ZyUdnfYN)RR_+rhQ{jZ(p>IcR&c>WXmg$~63nMpj>5Ox1j8CKEba?Zg;7(ZWZdZG+c<@ zH8UIhq;0GY6OI^X$^tXd_J~4y5*5{GEXlBbe1f*tm`!=o*3dV8J|`1Rh~M$q?aO#Q zvb`RDKThG<{G{y)ex-h9_3qjoXB-D@{SQtvkT4I(Il-3<25=kAOjSH|B-oIs}f{I4nS>DH+#UW z93Oll$(wR3eWkfSbKD$16*93UKWXb1GErX@uy@FqPnyEI$^Uo$FW!3TcEPV!-GR6Q zJXUrMfsIaS%(XX#6`WC0S4{_8{+m#EJu-^zi-J|(t#3^{RJtS*jA+Mcfg=g&>8Sb- zAZVN6YXrPM#^ZbZg!OL9wnL< z4h5Z|^EXzAbeY@3=eizbe$o5B2i|obB4``j4ouV2#JcN;FJm`9rpMC)-78nMOeOVN z=JSe*R|lW0qi}f$hnB<(uleS&c#2gE(|4aq%{mRP9)bMs-hCfciZ7bAp zlyjx^zCuOShc&jHlm&b&gZE=$AGQ(YI^#!PtoG+~RN;ath^!wuxD0}UgoI!sr^r0F zzM6EfI&53itsXG51LfE)SM^oAzQRJ=i29;{XAyfeV1Pbx+D3W?#BAEqSBTmcPOw_` z(Y{AB_A%2o<))CaFk0Z$TY#6Xu4LzdJVB9yV@X`lYQqT>T$G`O2pID-Z-K^ustwPu zJ|=ZqZqtTJ7nOhMm_-Y3&~UzaQ)b!Q2;So>za{JPAeoX4W*`SaE}GEA!D9G zhN&(p01){eIdRw-T8Y)ZDT-ufhFVgx!18jL;|zbvsje*(MfK`%;;BW9G0Yf!oDO4+ z7$<6h+ zE>))BwQVDJN0Ikh;D`b!DG245914U#=|C_5>Vv7a(-*T1k}yK+3Y4nX?nOKaNlbaW zG^SHy0hx0BDpAeMx=bbM8Rv7Qnkm_(P?`#0CFHF&P#XI);RK`>b+ZSaiLN74;n|d1 z=_}3sS<5yPR$vQ*cm^_u=kLB9>mo6WT~mJU(kHY0gA`PJe$%+=PyDApvd!-O`j@Vf zq3{3tC;#Ct;|``WY_TCiw=9D+j1aWFTE2GItXKv#?Njw#%*ZH%siGQ09T7$goJtGu zQl8%qsvSCu%6_O^Cwk}eSJ9H0tskBJsQt8=?5_RscRa(_tLPi0*}PZ$`WJq@NP5y1 zjxMQ;g(Y$Xkl%B|W(6%lGoqdy3&_sLiN?ASwaav2jw*}PGUQ0=G8C;;6;0}WSv7cD z)U6&c4*|hfxQ5h{tNMo4-s8kLX%{MMHdn8E)=;0&_D*h(EZ@NWi~AR*4Dzj$pZhcJ z<@TTKt~luN%4<(VWf-A1xzKt)Tq?BEhh7piG8N%3d~pbQ%RW(2V;LzmDOD=Lh&Ni` z5n6y2$fh_ouv6C3=g$-WxRjJlX4tDT?oaBSNg8*EEeF zT?1QkRbYiEOggisZE$TESo~L0K>ZY8V=J>U$^;*$_AJOZisC}4+A_wb zEHuboOVErCq0riU6b`^?Q8#pq=?y4h_v(kk~vS;w2xIL zPD=>|(Io+ML^%NqtOgldAtUt-3F%e-*Q3iE)l897g0`gCeT8EQ+QK7-Q`0uMF>sAI zG-}P)G6Y!UQ+r@DaoOa-7d~|x&S^c@=TUm;PrmO*xXrA7$$TO=2->b%yvNbE_Z?t( zk&9CzG3Q|_aP(A^m$ScjE|4AV8Sc}0Y&$I$IEhKtKC;fz@{-+)@ImYS?u*Z1t%ZAW zBK&1se()P;&+=O@{oUDL6ey)O2n2tE7!vc#ot#%ppbaX^2U9)S0nii(9n_$zZ^FYg_doyLts;3e%r&HmqskX zPW+O%f!p%~iQ6~(y!3Au4$WrGzXdgS#Fd03ax+=f6DSyksff4~HXYU%13bbQM0`k1 zOIj?I?T9y8U|9$)K>Eo_2dywGP{Yp1E*!0p4 zz5jh3N|htVCh=qOCqXlLKuG$Cxj%8@}_eKfP+jkA%EC0}ji85KwXS zRpzK}Y=z=sK`uM&%RhR4#s9WF+B2+@#=>ZUQ)>Y$n(4#@*DMfOc~M-Cq}^AGJX`xk zJa|*s3_;tiCvjWGRRnE+!{i6>zh5&q^Wp93o0nMTBQt;Z{h zE4NS}^|K=5pe^c`wq7^8duA6wTk@#M2b+vpLo7^&J#q~&79T4MSm{lB;h-j5Y74SO zi<>SOMked-wO7d(u=il6jU*-UBr8?v0oNi(e-F0gs=x}7$rh!yZ7dKSR&-VXoI@4m zxO+fID3DC^Y@e6@jZpnSfjc7E6dAIC1Qn+$SJWS-f?9^DEFMmZ$x1=FNu8Q-sV&IV zVhh?w@MwY4ZUJ@x@uaA#3~T4>{LUz!b|hc(?_|ZIyG)AMF<*u@%$JADk&M`9#sVZ` zX;DZosUud_QeH`X@iBbTwunL7O$VFg+kDX&|8^Y=NWn@zD;-xZ`k?I{E+S})a1hqq zgX{j5NW^Z{T)utbVVf@?U&S2Z@Gmj($FA|>4URwAKor$`b7$DtL9= zE2t&Cq)q>NWWZ+lW0&}z!*I)m*~Aljd*8ESron5?%7ts$|Nhz&{G=_uNd3q7!Rzp( zE#9UK=N(FRF9vOa$w6DBVJaYbZOJ%XxDI4TdxpIt<6*SGnXo`uw<=Y0t7U{|$U77j zrMdgy-Ns%j%q_eh`N=ys;YDA62N2x7cYk@u%nHL#+A3vVfwAxt`7muKGRG;;w_dkx zrRT6lz!|lGj0z{}>xs6@^kUgpW8vEeu`n%vZt)>*=s zUwDb%1!v?DS6Gj4t{?*ke|?3I@}zB&+#s_iD2Xccm#J`b$HEkNbMr}@;e~394G(7l zD`bA*=vbx%-p^czEeW0u3MT*=a56+%Xi6@~otaZ8NlAoQsn#@&AYE2la#di3C`>xD zrfnwXE5IVKWCf5}CgLmS(+T;ajaPX#Ck7BiclX$1%{x49jwcE%Y6A%bOyd))Po6l` zdyh=D5imBG(1vp4rhTU-Txtt4rCQKFf=3G+vjvt|vpO^(>)rKQi_11puRF%aofe1e zE=ceoMss0Fb1Ph`c_UXAC1>QLUlGB^LPAax^D3jU2aoA7v;grej`Ze2dOC!UJ!nf1 z6@~ChXP`fE7JI-&j9N(pPufPb{@mNf#h|V83Lu6H@g@5qD-is{I=nO4Ze8ES4axri zPugy80*jxtT_>!$7K-Cy_`yE%l$38X)&W>J7L%I7nS=$byF(yi^*Ft`Gt3%y`A&$Z zU<5!CQo%T@EG4LK6KJ9x4k4-eu3QS#6%!W#Vxdr3c=Wm~Y#kd;*aE9T-d4yk8YRgo zkJa9Mj%udp5^9|aK%$Rxv0cSqTsW4X?P77YmWFKz4KUIc+;9dLL6P3UL0b&#i8J;W zUc!^MPG%B(v*6&LzxKr2Rxpd*{#XA37?bb+`s%6$i{wvb2JM98|% zumh`yJHx{|j2NQ@PMrnd5uC6B6247aW)|;NHB=A|W|H4~+b@*cc=KBBgSLCvGb3pG z43^>dmjBI;-85x#(AK<}#M+tMz8MxH?P<0^ee(!CalS*cv5=C_QR$j3gPeqm?6j;@ z6;0}WnQ+=PrbXTA0rLW34cOmQAQ|df`@awPK8S2W%!L7)}7UPPE7jV{9YH#7 zTXI!jC$#-p(>B2(@YQSBBlE*Q7MbIqZEgugEOCwki48$py3Vc+NB1tDJCixohLgyZ zMH51XNr1sr*7y(qd8sJ-B;2&`B=EsA?0~3LLNsQh1L5VCympQ6x*BhIJkNA@lu3-oXP+*I)N|PpaT)U_utQ9-u z+K8%!2x>r>O9X$}c>ByV;-Y`!21m?{ed-Hwkx4;PuFO z>J}JJfx>$H-orZM#uO}MV|8IpXyHFYc$C4cZE>+>AM0U!aG_M$HPpM0l`h@wBlKh~ z5IiTI+v@D3juh6mO@+Z5lQdbWcY0CMz=<5dNZi~B&t?x8I5cahzFH7g-I=fp$b=t{ z1%kFkj(eUCGe`WnpUa*Qc+MB>rti}8{6s-+-nK!sR+^b_LIc!Kl1rW-QlXbgRI&3F zb<;i-lV#3u#jR3mEIl#{I2mYh->DuXo7*JC=3YLtAIS*gmQ&oI8SAUfowElG9pD`? zHK|)YU?itQvs-SZZ)DkB?uYO0$q!!&%@293W~~GUvc4u@jwol+0y6WAU%()0|2U5IOwi{OB!E2^ptl*4Q{&pwj}h%n0t}@aBPg?*CjVZsunH-LHMmJviaZudL>l$8~U!@;aWl zy*vBW*^lK#wm1FAt@Uiv+sqT3s$eEaiHe<$|8 zlP5m1Q-~ne37?a_?OCqfvlH{>FMsK3zV5F7fLX=z#)>%KIDCk5AMWWo?PJS63ZD&Y zP+=%l1sY3_(gL!2VMuYRCgHFrwH`WjXjA#EU?7sF$VX;}=GHlB6^b0dwn-g@Ne@_T zRg6?kxvH-gm}+5Sc92;iBWPP>)*xv6UYgv40{HTCNY2o0gEt%d`txhJY=xlhJt)LM zTL+wgSg{hiu8acEAzOkfc3!AKd=zK6;s%CedejzhGWW+&UmSiIC|VrUaV`+JA4$lN zFLnn{+xR0gC9NkQJdlE0%I)W z0Go|s@h>^8N6e+D;+c%@do*V_a*HaB`DlS9EU>u*?op!J$ZTTH@lpxb4IsR`f}7x; zlw)m0avbyVi2?xYF((R`zP!u<9zUkh0u2kun2@E+X&Vnsq-u!^_0FSHs8Cr2_#v&E zRuXs<%_(+YK{x@WNo|@v@GNwo^U8-r{-~5rs&VhB)$T&mHsH;w;A*l1L$W9%;TcqE}d+!@#S#sTn)qDM>_swdS^JcsZ zhNLvAX||FP69FwjW+Y=5su?zwcI-eS#j^DwA0ACb-UtH1$ObgXeo)Qqi0V}csHw<^ zKNw7tuwzCr;8hU7A4~ynX@^n*BOs7`;HSkVRuIP^z##;YGOR>7r|MUyZq@x)ulIHL zo7t+FzEySp*SS^q)Vt^1`$Q<5k&c3}aHD7uhK`2mfK|};dLS;A^Rp3a>--e-N;bWi zegtJ;IcZDjpXIghP|}vJZ1hmPUjy_GC&f!QECpJ}w_e|&1g|+wlD4K_`~c=`Tmu3f z>LSkYm<<)brU!7z)nLPwS;AwPw4BQdTXu=Z6v<+sP!Bc2N)Xe6l57Ml10dS2a*s-? zw=C9qPC9C|!YC&*O4?GO-uv2;>iJc*dL6HJrJvd3q1nZOXVD8~fA`-fn%T{NNZ-dG z+&XJSdm(f@3sC7cZ?bKIKQRDIzyhvvn} zV@}#?lK1rXW4=((7nR96J^7$oe9yzr{HngcPYZVW&Hrd`emq_6{O0Ek(bQ5sumKMs zELdDkB{{c(?4qk|i%YVxONi-Co`NjKQBZePL6V|0iZ9^KM!-0LsMW1k?A1&?R-A9h z51wmb)XjIl@A2gBM1LPAZEw+1{nlT!hSsa5FH0FF!=>fc?2$V9+B;vL+*GHp9H?C~ z3)y3$953OVoQ+GynE6NGD_F4J86G#gQe1=wFvS*Lm+UU_=}Z@ykaLB3OUyt8IhZ5q z*12fn1PLTFZnED%Z4>+)?g4fm7_22FSXr#5bD0r^rcLBITs*YQeuPKtG4+ zi&4s`&p+@<+nojJo2tL?&&cHW{G=_(4@#h`t0GhBza0jfb;&^%wdjaFPLT9+<7i+j>%HQsAWiw|uNE_B(vDE|H;ejl&D|N*!MjfofDxt0g zsXEfuV<(*Sq4Hb4^6SZc{{n#Xs^|hy%k%63iUM3(lM^RC%tTMsb2I`6mllA#@JoEL zfTv_esD~PmL?kIU$1yHVO9ATBYa9a~gis)P!$Pu4zB1DA!4*TMSiIAm1zh|)Tc6;wU2 z^&ZgkrAykXW0$m@TSZA*Ssc!M$^!XvUoALkdwkzKHJ<`Z7GdaLMvWzV8LF$!4R`?O zPeYVMAABw<(~xsnVaqP@-LY4whZ->`z_g$w8v)CZNolx8CDmIN>pUkNHT@a-!zgK; zQqp!ow~aYz%Vw=!w^maf!lH33+&j`wIB9!g^!01>b;r1$cGM#WEqItO{h>zSg0R&a}`-@Xf z+8)u8zxD3t!@6H*5r!*4kX-BP0rJ3s_kzWYYo+vxoYdl4FKJt(V<}WCv^J2m6`8#a z3Z~9CP1M}_Nr?la8AeqqaBNcKK56Ty#tt?T!2Ag4YthKaT1{vxB&mPm*x^Q@8)`&pLsS)aK^`zzIw933 z^P})yr!(_?^`x!dJ*7eOdy(n?&3nH<*EdSqYQHu(X-nw@2Vfx05N!5{C=$cxE zWiQZar9*SP<}>LQFD^ElIm3-B;kXHvqIw|pz}>Wa3B3s~L0Xx9O;XGEsS(!6)v(H9 zIAfGWoYT}kuL2X!OMI2PB_6<>%eI|z_p!)IBUG)4iMfs0WI@;>69N4VStT4wxM+8j zRTGzpfMg+Akb={oTUe#OIZ>AR9=jkmQ@`N9PH~0bT`_YunMYy$@`C21tyV5+d!jrm ztY9gFMMh)?$ueYWEg{JWE-iSe8O&_>P)qf|v+IHB!v14-8T#w=q^(;Gl(ePXj*%f* zEERkIz$I-@%<;EZpH>fqV6DbF%PSRZLRT&T0dST&UN_IeU3oU?0n7;vnYc1bm?~41 zb6H`_F7Y_?S?m?+p+=l}8Fw}UmLU_}Kw?9$CXm<*^l-%-Ts#*&A3uBeJrliHEGTJf zc(2S)+B%9*8ST4jsvdLFmdbU17kZtkuN@;F&cY>Q%={y8xKWf0HiT=Csv@fgIz3?5 znZcbB)&$y|{=PAkwB5h2b}T<>dw-!QX-oH<;^KPwNX=Z*cBWo5?n&F}{B3^Hb{*SW zSE<~Np}q#PF18^rJ;S&IZ@a|_Zlzy~hSuWR;-sym5sAG8qnrDrt#Cb0XX)zZgcS#-r*q``5~MMTE9*)xoB z*6NZyfCzvc6E;+2Q@q-b8`$ECVFf4+A()8}ZpK9mg_c$@%>a^)fPokcwKR9BqBKWR&k z);mK=J!^>^1?GqDU=3@n5T*W!V=uLX1x0Bhwl*%$0|pbVCT;uALGBw%q*|4L%LB=i zwjX`bEz!eeV+?Z>IzFD6IXxlIh1M+<R1Cod&<#wxvpiN6LDA_Dq2nMG?SGLa5?`*Vu!&GFBVN>vx3-=QQ%7s#E z>5GhB&?8TF*C%ZWW<5OEj9yPABRUJ05uuws!y>jess}db0kb(#J(8yPC~3=T+>^F= zxg2$6l_`4yR$9HcK62em4Lx7*keB&6muSK{E2`oz*8|;=OTtu{aecu}rm}$?M9kJb zlL9qyMrPdE2v`(AaXXsoEsJ$xlSWHMIi;lS^s(Y6Z4EZQP+*DFP)H@PD@W?re)rq# z%v+g&YibrcZ~Y4j9xIkXkmTa9cnO z*1_6IxRPZ4$nkSj4Z)k%8IBSSi=LDQ0|V8ZSYCNY{0sk zEiTib!>2x6`vWP2>jvRSvuRGo-5i0F()gs=rPq$AYN1=cIrJ9jJx}U$vaYS&(eTk7 z_-h%iEIg6*y^>=Hmqc60K7hDvnK9#}&Dj<4PK)fr|dK$KK1u4~M7Kz}Q4P@&n) zg+Ww;a7X4rqsNt_U^6rBr9;S1b8*js99g$su@|f(RqC6WTCs05?)gmAYt##iDvSsY zn5cIN$;&4-gn{G5>19c9+c*bPG_B?Sk`Gjx@Fn$w8yPoR)_IO$R9Gc=?;h}hL#dfz zSz-E7bE+9oR9amAGVgdPyl|OYS8;&i0^zu~g;QzEsFBsd_@57iuJeOZSKXOgS~f9jvc*w;A2QCcvm)|cpk zaLIMiAzqm!Iux0<6slHC+3_e`tXCjxk%@r*1|$(d%AJjX1q6`fO;!x00?wuD6dy9* zOegC4D<3*i>JM*y^FMn)Z<|?t`V%`?3|;jyxhU-*W`w~~X+M*Ysy z-+4+an-aT^e%;07>#y9@0bNp?5~51;KJ@_hQ3w`RywKd_39zTp;xa<$cf`D#bj58c zX~XP$##d!WNFw5lI~{=&CYwtQ*{NO&XknH4=2$)c-d|=bKJ@9gUeLTte)m-aQNFh5 z(FYIv)!mQy?eRMx3~@iwNb`3(^sSf;cI-;LYY~RnQ><$ zU@9%KpPufYqSAMmGyxbDhx8;(|~T1eEdO71k4kTR=-H z6NxhJbOcPMh1Q^z>W%ga;ZQ?+q~|iU4i{?49cuo%)lX=x-U{Qio>Wa&Ke76W-8+;x zo%?4Rw6bpX!Vr)RR}(?6!==F`+^K)!*w;D3N~DQRwQ+eKus9ukDZRM<25ejkF3qPB zxFl(-g?*@T9!Xm}q)>3FZ#22&-B&+!_!p=D^42&1AAP8fzVYCbJGdSl5EHKk=eCu* z$^7&SyR@dwFdfyo&KZKe{@8PXr{hGN!#h3`oBJSGb%fiUUfFE zsI|Lw5ofqtbA_JS1K53Gzhp(uI!md=WkigNI&ssADFWex`kKt+S3|Y9^Av^!p-I7T@{C4(~JBkW$y; zoDc`hXFF2rVHRY7FrFA)>*lT$W zSd8M6mcGL1%4~LnUR9&$1FpJuK$R~d3jJDD53K2d?#QKNiWQ0L3vR7TKTUEj+8x&j zB19iUPsW{%fJI9jvD~AQ=@olDcI0S)2iMezx3q9MX?smOEEFItihN$LY>s=uqorn` zb4()#BlvQzg$i6^L*^fWYY|`25Uv8+N>V+reI7WqunCLFaJLyiU%t0U*BQlUrn!iz zpDJdpwLFI&(1?6JDLq>>ZD*LVc5dQSW7?ZQz7W=Ki~XZ0t$LZEJBsC~*R1AO!0P6VL)$ zQkh7Uai=3-GA*?rGSY48ZQvqhW|$6j_7$fcoQtIPC&#mUW6eP?_Q^Gr$Gvhkls z(zZ-9`-axd(oySsiepW^=bTR)n%|eepLwVCIv< z@BJ?hsLP<@k|%A;81pl^;WJ!jM5U@8*eVa)y*uNi?IU$)f0&ZC6ijF8olm4DKB5;# z{mS959MP(s{nD53&(y>${)6wmxmI*bCDvZ`K+^-*eP!ED+1oZrd)rnp*nk-Ur28|4 z(B2{w`u+wa5kbbCj=%{3NcM%9UfZvwjhVVn3#3!H7CV%*J(^DEl(e-s)dPyX>YjI? z0l!8~)$NCBe&ddMx^lY(I3S`2T5**Za}i7HOs4*^q7ZJB{!k-w4N+BG^}v>RK<9Q$ zwc@1h-I@Mp{G{#YX;oxT+R_sbSZ6b%UU{nYRk}&UbuMc2eYsw3UUZeXMIPvmToR^C zk*P9SG{_}7WS9Q#*emQq%3|orlw>1d84^b<_o!rgMWGOSvhJe+IN@3>_!hNRf8gyp zvYvZB!3z%mW&MAxTVWS+rwu#p)lD4PnE=9RV z3v1{{yspvBD^A*45j@h!leQz|jJEu(4`+&`S@kB)ut+Pgp^{vH2e2BnR~5HmK46$4 z3vw=+yP*ITN#qL%R7*1F>%s% zkGGwiwB=2)JlA8nKR4c{-5;=;_Uk{&>&PhmQL4xgCMna)^uBoW3%H0xgGabGafW#a zwQP+CEKWzB>I+HRf|(N1nLMU5C2dWSH{5MlN0}^qe-5w)D6F#Wva!AODl% zf5JcfL$5P;0r|mCy}I7(kwsx`R1dT~;CEm7wzG5>=fzo(ir8!fknYcD#=FuY6Z-xJ zBwhNGwp031SW4PnRg=5?r0taKy8ep$5iV*Ow*NsK1nuVeNn5Sd(|2~1O`kT1WZf-% z6d+_#l!cJ&14RDuz>2P-eH5r8m$28y7JC4T47ZnA@;iX zz>-XnxST6ShwRdiDWV}2K}6Vxl*Q1Kac3i784^b<_o!rgMWGOSvhJf{u$HLBJu37l z4<&7_T4V` z4{WCgv}U`kGFzxO)>N!y7e zZ5I#7fJb`5M!cy$MgdftmpK|uA5nXDtmuswNZL}GmX`OOyKM1vU;Csj^A#1JwAGw# zid&6Q&YH9xb2ee7Hlg9+}V~q}Dy1wEr z3=X*tmxegu-ozPJBCXHZ3co-PSe%Z&lwOf3OQA~hsRTx<_4)ZtTdS>FzVXtB_SGZ) zO~^#*4v-mrH{XlC*L_Bk`?_G7o3x`aV>+I4WHp4 zw${}H&yok0Q~izQ&Sa+C>ygRw$1l+9kzFx{s(rfcw4`6FzW!%NYOy=}rMDiruU!0# zm*i_yo_OTQqH3ug==Ol$eT9!sR*1@Wah|-zWkd`IAu8G(CHt6doPiv!AnCG_wu&OB zD^q%chn~M%&=)Bs2+HRJYXhj`MDofkLLH^<|l3W-^1&EDbibK+!DKnOAMumUgqDl z{dvABK2@g}WzizE&yY*1sTb{mEbigTtd#bK*dlv!E}F?G*`*)TSpy5QFv$Z`XB|UN z#+{9TnI)WA?or9~ioH>&r|Uc#K*4oSy+nY8PuePV;|dFZ;)vuHF7yRGJ1%L7L3eOQ3$BTXigm}agGd`AtoZ7IZS=sxUlV2~7^k^0=Y?pv<%)l(K%+-E zELQ+(RXy;YJfIO)5hsp=Fk5&PcJwW-!yv|BDsSvb+fxn?)``E^q^$}`+Xcljt8Qqw zQ+U&UNiQhvqn$;(I%jkB1B{7-bawz!xpt={|9+m3}?LleVNnB0jbp z8#%-ENn4!YZK-D75bZ0RYU=oHoblk1W6njhHx!@@`aF-Rc;Q%nvb0Ep$s+ZV_9b@Y2o!Kgmmbu6~~8Jbg*Z zQYUO(%k(-1r`wxf#-$yH`-tsZn>fRCF{ovWJYZo9&TTw9>&%p#D+ndoKw-uiXiHX6 z00P%jHRf!>9oBwWz08imP^(+7*ei`5r5@b!&4hkAcJ_$w7Qe;>R;iDALe{tB=5O%9 zT0V9`;TX_ypn1V;uo5V-IfZH=uzLX$@FyRu7bV zfReVCUEFHAy9j~2VGe)Wk(0I$T+Qtb6ayJ@+1h~2D&pDpfPwj#6EO}TUQsX^FD)(! z6Bf)6qtS(MkOe4^-Ia~tl-mH&nAHI!n`I3eaEiSa@ZqZE8zQ$ey3ItpR?WemikB?o zmXTRTQfWHCDC=Nj2N{v}ly;24;d5&ZxN>;dysvqNi)^Sw)dO4Sfw}t13;c@4*te`PWt?fnO>mW$|${*;gjqCntEf1B79y zA)(t2QRTSQTEeFOF+zW~Gc4@2Q9V%Xfzx8jb0X9v*Z#GaZ#+?Y?+1S6n3gRqW3y{m z9W9VouFTbyg_-_;bVI7KoEh8kQP_d&p?Y9l4`k2k;SoE$it#&^7 z30l6E1+Q3Zw*weGT9!fq^QAx32wXD8%s&D@+Zi5GU2zxY0SisoG0A$v=1%r$g9hbX zK`1c+mF?V;oue6)9gq!65^iNd(b)6FX189kR~kV}XWjG-X}eE@y7q)v=jvbbs~QOu zhDo5;s5kRTTWSd=HKa(dcKm!WzE#AfV6FB%-aKwMN8xbZjSasBj*eP)z$)m{JdmY4 z4}&2lOqBo_s#{!pfm$o=n%&9MXESNb)8EeZ{D@W&j~p)KaaulbLDH5QoeuCsBS$L> zswQnmTvgFq?tx2B+R}sZ>>|y}l?y#SOU11){$>T04JU0`}DJ!Z_Y^ zUQUtqTdsbt_FsPYRk}qqRkz-FRcX&@oFuIt`mU_nL~b1C8T68(GjJvPJ3F=$T7lc` zf$qp9VXDY@BUG4}S^()K-U8kt6Z-xJBoRTzosPf>07xdfg;;PJbPFr2!N5gA-f^6t z|KV@!a4d7$yy)3eFEcK%ZU=a(k)y1AJ3^SCGiznr)Plnq33Fe^^dTy|dZ54qrv)_U zN}?CjoA%r4#&1v6>C1ooriHR_q4@2$>BH_~g`{m62KJdUuO3xIz zAWsC^Fo}C|mIq#HAd7KyK-;+_Z6%%!C{{}#G0Hn?_WJdu{SVcRzx2~TML*aTQ^a&z z*?j0PGnr);O4`nP9I%#N`OVR_xa6E{_6+mDYPoa|SXh7^ldLzIj$Ddnir*zVde3ED z+Z`Yfatsj3&M^Ri>!})+B;0<95L08%7n|LBWt7tBQR=~oZ{~ALUq!z5h)|TY<+spS zY6d|I%Hz@tras4v3>QplNFa9OI;r0uBt zE!N*5C^gmg=pOg%;f%Mwar3*wKSN+=HEGMh+etu7O~8e|vk`+0xUeClXastSNnEr$ig1uccA&c|8-b}314P5p0Fr&P z1`RkxVI%}WXO;P8ZkcN49@Cp>r4034neum(spx6^Xki^DH^cxsT*-*Er!&Lkz-HEp zc{%)yXSm3QN>n|tWgeK%=bW^CqMlIF*675#a6Le6666JRWT9VxuBze^J8>Vd8G!1TWTky|$wTK)BF-w8=u z{8h=I<|mibu{aL@1+y8wOeWqoggx+-?UjdbBKsqCROWuBZ*?0SiB1$0X}5Z0?HO zlye24#0*rnLrZs#MLHmXX;W?s_QswsHoNskd%-(grM{VJ8q_uV?OOWTf!CPPHn{0W zs<}7zq-}$vzo`XfsAZ)$(tx!(kXba+Q4kPr40MCF9>iAU1$&?-ZATq$v0@HArB#~N z5G`3M_Rytl@j;dVoV2||^z}(wc26zU1KtCd{-mv*JYY-WN^PB)u_tW@SX;6hfOTSH zgRM57Lk}2?DcyDwaGh;roQLU-IBx8)Khw~blL0(b*@#TJ4G@i49YAt7T!RLj(O$rZ ztJF7l{cqD6w{j;GSgD0#+$Y>4>S1f%?EqL2xO!_Dk?tkwK%~|xF)x9$eWhlwjx{~j zVO9lI4_u-LrfT-#fB1@0pWHM2r0rF|8vJExZq&7dOSCPhu8S;q;(4vRBbS7!qG21M z%7Uug^uRo_AZ(F|fc^%81rcQ2=?I(vi6h;5O}~~d3?e7ENcQR1b`2SPDT++KMY`!+F5M57;rues8UmUd|PSlI-psTDo(D z3B#4_7)LhVEG2ILvK=GzMtg^K0?XpG423$Bw6$vHlD34i1PLnnN2;kD{|WsT!LJ{4 zv)ciT87o={jI;_G7`zUo77f7T*x`&oH(2XIY(-wM2WrxG)Zx~x%enmC?-5-J==I3V zXAh@0T-w$zUB003T38r|eTkZy{&7j)5A8r>2TOW47cyuxMPovc3MZ z;Wup!NHUwVZm*n*s2=F?fC0RYJwy(H03s6 zYV7y|NOrCoG~g74kq`u(Rqh+>s5r{1$^2NE$TW4|1R=P005u#fsckxdzOx)z23j&A z?TO3)ZA9hP2Cf_)+$dV2h;~an)<#uG^}whH%qYdV6WmhES9r;~q^(XSw70HkA)LFJ zRl#%Yf$qp9(V=MMMyQ%G#R1bxyai#4Oa$~d;#$bK(-AlU0LeFdEX0D-pj%jB>mXeA z?RR$6iB%`9CvB&v5E<8Uw*!hax3(2ah0UU&mMU0lC~V8FerN175+ii^8j6+enn@rTBckJ zJEf$pnND<;w7o|kWZjdtR#|3Q?dtlZEjyx?jeB6?w{vsrBpca@&P=(g7MGSNGu2Ma z!r%U|xKjh++T}_L_1qM?j5{5Hqq-VsyY)tU1KnWV=bK?QFc_1Iv$`=riI@#o zceBM6Z^-zNLu|PJ5lA6iZn|^}ZbF;pq}&E%vQw}PzAnAGfiG%y`G##cHjdpib`8f4 z;vDeUHLW|g902H01=E>C579-O_rTPl4dJ|l#R4ScNOAjK%|tK_+}Q}2z`FU~ zuQ%Gu)T5=}H4kw|(jYUE=N#oO5%XWC6>(yioTdrdsPfz!fv%s~(fNS)3zzv$&Sey)^vUEp& zcT0J3l2%N=WqyK-ap40lW<6^jwewQODJMIczvU zQx^`P)_7St5|+eVtf8c=K;*3DcIKaC6dJ^Xl_4y1)nz;Ari(@Lb(9N51uAiJ@I|_` zw7B9K=0L$^s$JE6hsdEu4xZl;1=D86b<+_r$PLBey7fkTJ<-^)+c)&f1IBR%1E`bu z%w4Ox9WbVm@ir2{Z4ofk^44;E_a&IuJ&GYo4V*}8z-sfdJg|gf7aiovOj8EovB)l5 z&m)(_loj}K>2HJ{MhF?GhN_hygK6Mi0)Y{5FM#A{B{RKZFIY#a#5cw|-!Sa-H$L_w z_a_Z)T7SU&v=i>G3m+$%6=bIl0C1#&UPSED6Ovd<8kW$K!-E?~jPU3+Jys;M5>*de zpa&MTmC(G1zWk*Z=|}a_^5A8{OpjLd$lgz+nA)oz*pvq>1Y!1RksEip0_ttFxZ)la zAp%=R0}&7&$$CXcL<}}5w*^UK{REI~Sq*5wsnIR0Qr}Fb>SriWG4SEL6I#NyA?B9) zB-y!WY?Zqm&|v9r%7_fpl%9~(TG{|HGnE`(ERdNsA8M%{c!oW&N48t~d%B{1r=~`u zmT}!vmOMhea;at|?vW}y{)ia9b%{yUfHEat~ z0o4P~k_YB;{cx+udfPQskNpiWT4OH?jmOqw^}t3wfES$@Wt`Z(AY4m)2#|rg#dRYP zXD_?)-?Sjn+7YbrO$)`}YValF&PKpA$DmY}{&C6lioFgwcIfhrQFFbdlo>Bic~^`f zfTB;nN@)&lc300RmboaG8A90cVr1>Z{Bahd2-eDXBQpQU*n=C3q>8j6>PmF(9>8kA z#*^oqFEVEWV4!Ys$r4jQWjizo*8?(h6eKV><4#Aw1Q-mpy7fkTnR>J&z9ETp^Z1sf zO7ru!q&*C+Q$bhiUWbrOLQA}g(e2COwgn))Y>eVsELrHRot@dls@o6$0x>V?&(NPzT3uThc7}B;;^S)4leE=LJz8W$2cA@qaxg(=tuwC+ z9^AOz87?xR5?!(f%th#r*Z+&q*3?mS!DupYdp6(w#z&{LQtb=3?*}AH(u7;^UOpsk z3D7Jtx}8aHV-L}k`X1ZnJ@QxfOYne&PRuARCaklRT3m5Ii%U7CseyP1k7S~@zu_fW zVokX%SmK&c0VJDc0~&B@bPKD@H~eS~y+mp@oqgn&*ci)VFivbcY+RPz4k*$rBQizg zAj+)u<`FK32R9bU)Vap-19$yp zgO+1sxi;;eT&YRhrax+X^Bx#U>FFYkdx1(Ls;rl^Es7;b+TP^|>a9Y`HyZ()avbcj zylZi8O)K#-(}yYX&=}sn}99M?l@;f>1&OmF?Uh zT#L5xM%*#d+;>HTDIEa=F&Juf>y7q8#Bi1ShQ48OiyvgAq^;8}qn*(20j)^ZjGq9a zMQ!NN?EprP6(a;zS_KVQYlIZ$<)a906uO~Clr}_FaTnx)CG_N}J}XnPz>xQtv@OsO zA6ZqKOWMZ8J#0bdn;H9N$4u1p_D4Rf?z^n$oIu)3`7y5Cg(Z8^))M@Hk);KC&&DO^ zWC?ZID8!9L)`+ws>Pl2Su$3Or%4q${YWIe1nMVtF`kH^z_I?Xl0o4N=@PLJkY}+YY zyCM}@sL~A~foTqN$@Xn6GEX&lge0O#xh=Rb0`3J+pI*&GN*Q+?Kcv1Pu07&8nOdd3 zHBnEzHqfkI_u^t4?{)qWYjG*#G)bCuBWGBoIob7a=^mJP3$VN8XyJ>WGj7fWP;Z@cDF`J7pdiOWM6z=X zK;U|+h9wDie$$KDF&Juf>lJ&Y(WBIZ6W^Gbrj73{HPO^KQAb1)M@#y?t}MN;)`8r` z3y&G3hK%YpB$oetvA!DRa%8a9cpf@#;tWS=BDOXz&jU-S?n~(v%@j%LSz&~-n=8J0U@JYK4Vk6s zZ=s&vmX$?)Lx1)KUbf*$TZYt9J+N^PSV+vaowBzrQmBOrSMC@-5q-0LTZ>Et^f$aD z%ZtJjL5T$mM!>xQlFhPVC>3yO*C{@vzA+?*zQ1^Lp{D$#?Nz7EFwKO-KcxC)(aS*k zqmntm14oX~tCSfbOwg&d(HS{BI3r>1>*zj2g>R(?Fze3MHcaVr)zK|ncY_C^hOm_X zF?RAcJ!y*{$mStv`cp1xE9*@fjA|6!XqPw7#x*AYBF^xb4Hdtp2f8DdM28qQ2jp78 zwPH$kiSGrBYI&OQ zJ6jimJUf+ZTW`TUZ$cX`2Rr*8vK+6KD^YomOY*=Hdizp(MP^BY z&|-$Hm$WU?u@b6G$r6Z0A|`iqmLJgUysbIWA*xn)zrL8jlj=I zTOPby5g%7tFlo{@kPp`~qJv?&6q{H}s3p)jJh(CC?&+=Ru^uTETs?3}9+)iEHTQaC zT9Z$2Pc50Dtwi@UXZXTkhLR zSv_zO9-s$pd5>(anfo12+NyW>3Hinqb0UE3KdYhfvp3$j33m@vuZ**ZQAjHMiCJTG-&Et z`hy|s=sg=3EAu7wj}72(60`vN8f2{P!&P|oz%${2nYs%*c?r@x-{J=XvA_E_ZE?8~ zs&i}hVSQ0M zgj@EVjaU|&;0h|hDfUWZP&oCdtPf1(iYjD}x@quq$o+PDh2cn@f(^sCp10oJ$TNfu1IVFYA-OAElD z1v#CosBGdyODtq|uUQv4F+>xaHCiR3QTH^ZW;pt9Ik9cr`!ez ziEnYIAOTW?2At7ez=tcAJT)e8P0W|S?R41h{bgp0NH>Y@{?1)`8x61K6Q${h zi-JMDaTBV*>H&BleUfV>evzl{1k&GVaV>>5eN@e2LPK~Y6Z-y!0I2nX zRdBBQwRBG*uy($Vsv+W~?eYRGeP z!EHmtf&9L^BBp+@8yqN=zH^MHmXzo3lhwZ4U&m4G`NMxfTWv;YiR=?={T z>bK5e^9f*26)j1*l?Fp2#>Hl*UIPv#jR5Gbow)fuMlR=jZhyQpA>d5?$cl!b)rx++ z%a`oKfTMMo#E?J@rk*NnxWf*-j7vFd<)${9=Zl9&A=ZOonD6u+qb)JM*hoq* zPXvzTEVHz0(P)o_D&x*Zz+{Jk)?i_7AZbg#8Df9c{_4y)+1jlEt9I_#Q(C^qSglrB zhaPi)BN{%?>*8cV)uipPuPS!SJz!-jU$~)uWgb29ig$fif{+ho4kt<53pcSUe4ls# z`%{bIB526gF2IMqk#i|oTN;d*)R^Q3P>=~bz@3#As6h+d*$5aJH{IQOMPVd_%&y8N zK<#@*(buD>NiQ{zpSg>Zwgr0mb#bA&(Wx;0y89E^a>r=;69a+jaCtbI-;V`8!*>6Iy{=?EwSp(#S=?b(T_$ z0%>q-UHUb&41ZUck_c-bis0ux<>2At7ez=ta@c@lOCP-K*Pn-jyJ;d}?3LG9|OZKGcXGAX9FY zj=+g1PTER58`A7os&*s>w{&k=*Z;aYrQfXm?(JRpY3Yb!^0v zgkf%TFE%^%8gPhpq2E)JIFjSImP}&#K!u)@w^VV`mb+Y9dtt*+;->#xJfU&zv4h)a zTb8&ER~Wo((>3&Xrx^5P6fjJ{-3^h}jjqs(^+1;L%+s%B#^hXMIm;~VTBPJys50(s z1Wa}qXpLWMv}WAo1m_u^v^6C0221ga2&>epdq2RC*|GK-t+K8$<^WGUa@4Y*YSMPZ zRTW)5(CGnsT~u1Iri_b(J{6P_G*l8I+G4q8T;Lb`5)Sw0KYy^yqGre1{D2#-V*;QEv5~X~$HVn{wQ0ilI z>!jWD-4Gu`9mukcYq?%07H(UMD<7lv2D;sXYZ?!*z8X1-v=O?Bt{&Jf4``T!8H@|U z|3LYluYE)rT2f}a?5);3za9uvEsb0>Ud+m(k;f9|sRSg~h~fk%@r*hJ3KRlqYQ!rFfieJ2z&|fV-NzUpExm4_3E> zaZ3i$2YX+08<@-ij2SIRvnom2j&d+TD>=K_GhAdtB|2{pXejUt%7{8Et?`Bt66;%9 z00ymehh_oA&Jn%g3KEFOf-u{6hFC|~*zDA6AfU8r_-4sGmJhTzUD9?o4J(>~nN4xO zo*KfWqeV8_>xFL&UbrcKUa=;^dQnkDJwzsK+6NReEzn0Hv-VOn}v{e^NN#do3iVZwoPx; z_BnU}lh8sm#}Zcz>Y}Q}C2LEAACnwAEd!{Kp+8hty=zCQBMp^PV}$LfLe_JDzcG;$FT(V<9xUvQ(3 zc;LsyTBG}(LQgQQKXMzWY26=!-e|874mH>}+Jq2JLt!xs`d~Zxj=DmhV);p17!$%` zsQVl+q)u=+C!}0J1&#bn8t~-s;Kl-x*h~~rR-)>Gwg>LEK^F#@8vIrWX*62BdF$Pm zZqj0yKK#}VcRg?iLZQAeyQ-r1od-6X(raa7yK|N;vI4hKp%*dQ@)j`kHSvyAtY}w1q=zwOJ2ni1QJ`h;S>d@rDr+>swj? z2Ca05W&y?48NJ~O5{Srx5ZoHwMvRNiPQ3;kMHR`S|C)Enf4cLhe@T%vKEn*IF+@hl0u^y@i&dmcODLq@HILu_4 zy}n48&;anHrh*t`Tt`xz!VYj}r9IU4?K%k|CEh3Q(u@5CQ%6GKZ8xj~&8~P^ht`jh za<@E6yRgoDC~^ZQz=#9Z(96oF0C>niK3k)v>p&{cHxK$izbr|vmT zFl$q5%w(<^vUt&|+aKXwx8*Ju>yGtMJ#cOwFp!Ms5EliaN0H(dmwd3Z;Ky3h=%z6c zz~Rb9bjodjkoXqEv4j>48gNE?0Uxd!lD$M0Lw{E-clF}k--TQWiy=J5C7d~6SRt^Y zR~M0|Trx(}19!XnQo$mvl%dj94{U=6W=5%>{j;B)KYrk?`K+s^ix)X*`}yN-FtOV3 zzVSes@?6Qdkr|c#P@~1Q6zb&#aSz$zD4k*%lGf)M$h5ld-YZqY;9L(z*#h|c&6lnoa>*|5$ z$^-Vf8ciL{mU;kD)z3EG;Gvk%7_VDgF)~ts^#wO=KxzP$u!w$t6*!n8w85Q>fbp6S zC|!CR_6D-S+7fo^_YGd0F`jW`WH5h}g9(x|$pDy_z!|pw8D?pEaOFNgDaa9nGdrJ;Ba`60J-029Ig5#_&-Fl9 zw%Y*_-`~;^1-C`OKnrJ5O#^@GpE&k#5(Z>Nlt_!9+PX9kbVsfjriu*1^*nM(bVx4o zeX+Ml2P6^g67*1#jewC7M|@aq=@ok+X}DTBv{7!p-}-y>y93|(jjz({<&M7m#ogU2 z>iE}w?}Y=8jA3!a0mBM`^?JE;4Um#*1tJ+^<{yDCOQZ!F;R=9SR}VZB9+=yI{pep$ z9?hR9^|>z{(@zqpU;Oet!>0d>i6m;CiIG$zpLGvt3;;VP*@)V82G-(|J*t5iY`6WE z5_d|PTiJ1KK@#2P0Wp+lbmQJn1&|8c{7kRd3)YdUA(g zFYbh0c^G)8>7$1)sRIBUsYEZ#A0Y=CTrx)81Gj(|RU)m3x)N0nY>5ZvcVNgu%@1z7 z59(i`AN;vXSCOxLaZ7BhX1q^4U@^`ta!Htys4?UZEyz|(NiY2dgeh5M7dagbNFq$i zZ9&_xG=L~;;gJS3;MC~SiYqBjvZ!Co!pB%h+h-Yb-w9zc)Rb298d5{72aX(NM8*@^ z5qggXmkz`hjT|1_C|UwTSFO8%6;?g4^&YUWaB_o}AobjWw5T+&wW=Pt01x2TDf~Ar z+CP0!WPz0rKH=pvas|&`c7tD{2xQ6>$#+DDLYi@>BXCrEfmSQ+nyKDsZ=f5joo{Ap z?nb#w0i51waY7@cSJGJJhY*Z27?B~gFWn9Z*ui=s0UqWLQU_!>lga{;`X`QkjqlQs ztRO9@sr99Lz(D)d)fPRfWX?oTU&}^>=Q08aC`@Aw1cb|S7yAANBrrkBZNTG4;5xC{ zsn>#|v~uDmkJX>N@F)Mxsao+A{_Ip~TEP2c%YknE4jx8ioM=`~w60`^06JL3jkX@7 z%a9nna2wz~+(v4+F#-l!B5i=CqAtt>BPl&oWQe5nmLMO=S!QH$kqu}&5M0KcjeyCD zleR^djTMWu*bLuVX?68Gw^wSW?8zrSuzNB$_y6t-2Np{p3_R5C3rnOW;E{eU*UP#? z(snH_IVYKa1io~lmGRZcQMg9vDtaqCa1j?-dwC-*x?ni-=f}Qn|$tt zBSXJ!`-dl=P>*MN@qbVD28Ym&YUO&Hg3rd)l+e+>h%?-wwu0V^2Q-*5v*dbi*Ad#{ z!iEr^`$!Zf9HvMRE@TDDjHfy6-E}tBhW4~{?A9yx3f*9XB~Qcbo<3H_C2f^etJf`k zQ|j7N3Pt|?jTC~Z&_PCK7(gX8#KXppGNPb+jKSgaGpWIq!!6)N)tVkFl39tW2hQ08 zMoq#ZI#gFEX=^ntMEbIYn%q%e`Ta!uT8k{?->1MRS?bx@LGS z)dT0~fsvG6(MOtAB9HJAAzHe%}%`*B1VMWv}(TH+@SUCP3A7`$*BFnhQ~ zkE%7!ux$P#cWqsw2S!qQWtK@wZwdM&XGyRyt&y{Ak%4WfIuK;WosEFW0P58%_KM7* z#)^d((Us4AEI8w=oWV<`U;LzZbF={a7a0_@*CDMwhD^c~pR(Qb3t>QaM zy@)4mDQRmbv>xe6TfG%lRwLdg9k6t$c)8>p9Gv%g7bHBxzeV#zP_7VA57(_BS{QO0kn3tDUcYV)YYKqcn}~MBmw? zC}{6_#-E>h7Z?P_F$eUkYhdb=whd?0X5s;Zp5H#&i1V8}S$`4HZne0K&;%6ZXdsfE zV*mozQ#C9}xWf)I?D?484~AQvdM#tPSa%#fIB`#&Fx}VnY+)=VZ5LBDp``8K({uNv zErDFY19#X&?TUskpKLA2C43qH(tTTt3{*pv z@yOF?TC(d*zNV)=Egie{ioHTN*l@nN8y==rhY$Rdwnp84$O^9g@ot*5rKfI395AR( zkT@rjcoM{5BR`WG)H&P^O39FGdMx9v-3#`Bxd?q&TNj}!({YB`c%OEvl(gl`#4As! zdNNhN{kF21;F0bb^peE0agCT_M(`EAg&wf5DT`bZrX*?%*{%hd1~&qymv{rhluQFU zTuJEZiJ%Qjtw_Q|HvmAd4tN_HgSD4z@aBrCGTsyip3ms@Z&X}oCiiXPhtN(3*g<^( z>Ge|2c!>4Y$PrvRkXbZxcyOa=2@GAe?gCa=^}zOfz_0m7Sekm~R(sr{?+7_Ki|Lp2yI{(w1Ki#26^_c0zZ6l1;+@U9J-BD9mG)g_7@F*dyJ8SL8 z#||}VJLaMHFWzA2K9tz#h{i@R0=ru+E+cdSmF>`youd}&p@uAkk&QRY@Ppx2r(Vk# zF4i4K4=iq>j+t&n!S$Y{r0wb4(nrmGbu{Co?H$H($u{LtMPi6`v}1?3(bkUCjxl&V z1~1$OZ13d^V~0^@K&3i&4~(Sr%JfT0ZwdO5oMnrwK+S>BWZc;Zn5;NyD>8=~D?;i( zaO*{*7k~ct%3TkheqlzhraAn*w+}4VN*H*kdy=+6+F-pBY<<#JTu~d<18aD|F7CS5 zBj3}rQ~S4HICA^oul)W(y{*)Lda$>Kq)J*n@LoNjAt2eb63hZ#RAFNnxv(LmsSSR_ zBJA5NphAZJP-Q&ww53FQg!`z8W&p`%Inyilf_|i8-@rdg-KYPYwAISq|GVTL6v&=R!dfcJRz6WTUxk6KsigibK@UcavUqrN9HiA5t5kNpejt0V$A;lSh z!1YuOOA>BgD6aSsWX(>!)-xo-4WO=?C0q4`Q74O=?gywptKL+*b9L~OKd&a5UZZLW z$GgsKFC0}QhB#{G7%Xw4tsR{mq!uLnAlwER54S>x&o3}6f;(FxtrJ^;7wv&`p2f4H zoguc!oSZ96USb9+$Vnz|_^ehmae@Srsp*eP_v$5tVXP|_b*fkFl?KSVE91eQ*iIKO zFBBzht)hP)pl9}`Go)sjF13jOoen6|i}goBy!mBZYy}tL-ozP>(!B6`yj%~YKdxb9 z1z~SjWL%3&%aqBs;55^@WE)2Z8$0X?LB^eqz){gt>%L%nYg4_^-at24hqvEg?YPBr zI1T5@JX#)dT0@0UtCFBV>ywTRT&v6B|R}vci?_ z&%(UU_KleB!qnM-B*JCf*$9{!ASEFJ8p0-1?2SS@b$Xx%&U4L;>n_xUZb~ief2S<> z?|VtEP2EuAqwXv>WG%gNIarHJ#+dm>;BbZ^bH|HtjgwZ2>VYlvfU%RW?eH(kAOG+- zcGUl-f9~Xua4C_i#THs!O?sX@&>gvAm?|2pOjiSP37;AOTξT4bOastT4@Be zf|qbikZ!$VZ-b}5X@T-weEjCCl;fGrZ@uxVGUUJ?zb^4T3_R3IgE=(>z~RaYx+uzm zI&jGtH+zP~rrM|;DE9z8X?w|qmcgx0-k@c8@U`WCd!*Et?)|Sj`_3lqEqidu23GaY zy$4npA)dNBkO9j>X9DSOw7ABenS*d4>lZB;i*QANlzRmdd2Wy%hXqL9P`U&FoY7t( z9BL%KS*S-xZ~e8GcTe@?GuOWJw>S>|;VWWX7*VL*uVQMV!BcljY8Dq6(XyC@2or0m zzXEd(4{ii{xLVU=!@?@|y?Y?twk|}Vb}cLYp+?U2TqkYSVn#{Z6Y>W+XLq)zIBCmU zWmj5zVIYWBGlAc_25N@%7ujg9#bqE+xHoZz!>z=AV=Lw&J+P6Ko_vf7`Ba%Q&tcNm zeOx~F=g92O9$9Mc;go5=HkBT60LX_c=-|tP9j0tzYtpvqjoRJ{51ej+75B*o`!Wn! zxa_TFSSXUTH33rV>Vb`V0C7@7sC<6JE-t`_b>>`F$kY8<*lERmqaze{Ve4o>5@9m# zYy`{-P`n$C*cY~@qEHAs6beYAC0s1cI@X1yx6yEc0_!@2^)=zT9k7;Okv`5vCTf@< z)`F`AXJ-&Dz`@p2iL@Sk1#guH;$k^Jv&{L49+P~Q*=P(WZK>GrzC%AkaI&!fI9v{T z)L~6GuxHULxvYkq4Ky#}3~#{9Dx&Fu?#LCxRFk&1Em6RLMCPdm0MoQP^nhl#3X-B} zP?C*+rNmX#tyk1u%kMeKt{CmwXF1q8aY?E4MRLY1v!`_8q)ltE}A$&0&%9?L75>8iU|#6(Mt7-z0wed zu7>eIPi*Ps%lxFRQm3@>{eY$0Md3+XCc|Ya?rJ+7P^MQl+RB?>#%0(HD#E>qGaRLP z;q`dA9;iv%QU8ZDs9!sKE`T2K&&TsyR`tx1fIa%-qH#&lvSzxo)}DIgcpUIn+0Y!X zgSEUR;DXIsy&jSm3V-(#Lv)(fLl|2^&5oEW|+-lMD=z*CZl*ZU(_F+F3 z;6V3OIhPf>bbl6hS`Z${gk9J=8jwVoj5`|vvjRkmi+fZM`@pG0p%8kq?xP0SbIl*Q zP5JyqC&d7V+M*lki%!~-dJPluF}C1mJHwD(tLlMg!2?+MWU8U3e(27Yo=l#ucAo4V zsgoW4W$NM*t{ue;m9Tms^FVjxieV}v@9s*>GQi6m*8t$s-yM5FGh78p(X=#z+6H@E z7~Ois-Ud&9(@7>}o@=qNx88kK&1Vy%uD`-uyY!^3qoH;fc&PK(7q<+|Ib5uu&%z~R z-0T?^n`)zaVEa7~uLQIbfBgDFPu1k-KJ{y}-6+dqVA;dA4G6-LsR(kmM1 zfl#ISRMnHS4EaJyZ3=&X!y;}HMXF>49*lr{0W_Ml1?xz~k|}oiQ5rj6((7k-|Gk-d zqzg}ToHBN{zgMzky<2NAgBoUD4_!Hq?-MOqPcB|3Kxq}$eo z=+n{~Z?w4LrVc0zA=tTTbmLM4pue&arO^a;Is(QS5YS}#9hyNGqbQMCa^* zjimHsR=p3NwAE@#OLI;`zN566S$BSJVzp|eU7vQ)C^cytJW=cSuLn-IVCb4`SbWjH z7kST|@HOj+r9&w4q-_Ayx_V%<9zdMbkcyxoTe~u4IhPf-bbl6Zvu687p&n|KZo63q z1{F8Uh<#yyDE1C16r4s2T-G>KUQ}NvxS3Dfpzw8M3(`>cC2c`ATxmf|=oUzSBXG$W zH+zQr6<194z&3l}F}l=HI<#+yz0d7Qy;(nF#%})axwSv&gSJ&!7h| zu`EoNiD%XsON&dUnuZu$`nzLqk*Xl6FM`^Jl(<^D^@_a>p8lqjOoBX@rY}hS;VWvs z@SjDKkdjF!@LZuLyfH6?97&lY2WJP_-Rv}&VzV1pi5K~|pXJ7Y>O&8N~f5o+qcy<*_-}2{IUJ7?9X-iAQQuF5b(1D7^B}L0DuSr|)nRT)sR#)f)Efq~aZfpOY z@AVf7*ml__p5y4N=+aA~q$)@XF+@U8HUbs~5VgAX zioHxcS}Z6$*W&PK{>=|wvGeJJn}nFqTcjTTdWfkZm`dH_fKi=HV1;U(O?TjuF=qY| zxDoLM4dE)Ftt8b0+vfpmuh8p}kLG-FuygwEF+XYhfbG=VXKc0Tx%9vaquTZLfebQ! z>qkJnjTYBf&N5BA_R4J{EaE1?QtlO~Fak^60NP;EmZXMJP87c$`R-i(oShsTtCPF* zr0t!B5Ai&3-f4_EfJnv*Mx@kooHkPAXL1Ep4i9dOoCB>e_5qTLx)?jsCcX->wSjDU$7 zcW{hj&Td~d>;-zb(hdzS7QVQlcsF8?z3Le(AdGdSehcH9;sDP-Z5ZbX`i{mSz|}|8 z0oTwjCjr*!hCJ77y0k-13KD54xb`l?1GN3Jq?b2Ld~)61&QOClx0t5X8!0WWtIVM3 zk2h#^zIo%uvz4}5hN>W(cCf`W=Y;tD;>)yMOqPcB|2vh zSXxtDuK8-om4o5_g$IuumyB<69WY?UhaEo14Vsnf$S+YjGJr-aC&`%!)4-jLfaQ1) zli|kDilJ1%x#V`>bVj|H0A)14_8hvOIi)nrP!vm?pAl> z4AZq>$<%J_a7N1A(_8kyEBLZJK-W<&{=S8AZFiX4*dA$_i1%DN0%jh`mv%1QcZeKn z``MYFlz5&l%f(; z4-9$$J0AlgnSFYYD?_%pWRHp&YQf;Ql(cd6Maa+}s^VPNAOm+c0!GSq&Vsb5*U+XB z;F4;th=KRMfotZ?|DrOVd;7Lkv&j+T*_cPZ3SF+l4L9pLVNZ?DNM!^M^QAx32wXD8 z%s&FxLsD{_aOH^FuO7G%53I8W+{agEm2es5maYCB_2Q@BdchicOEQX zq16MW9?&4Vr2)GwO5+F0Z zqA(INTVF|hW2S0Fgogg+%5ntO)C^mJFz`@2I>LuY4LW8SFVH&)()BnCQ6$zSowfd?$+Sl@4d6b(@$mU2vS z&4paSvzOf<_yn>LMoP5Mcal(2?ra21VvKuk7F{+D*e?1Q>qj~9&*~|qPbg`-L+kayl~?OKLzn1HDd}rW_=VY^I7~`nbR(s$gF0%U4JYd(?OvW1Gx=CrD)va&-*UGB- zUzz;onr^ZrVf|v)XDQ%V)ARy~mE_z#(6?#T>u8qP5x6A!ru#GAS8~zr*xdF4Fi=6# z-4=H?0u~`#N(+IRUa=SG;mQ!&YPl7BYBdkqrYHD;b0`3J+pI)&S ztRq$C8)HGwNn2(7n3#qPf=yB@!?Zd#gn{D)dL?3yb1+3_Eh~2=hg-mlsx>`UB(oA# z4_vedbX-ibx?n>iFkiG)Rp0x=1C|2@m5}O_k1$B-N#9ZR9JEk{e5%aklB8|fH1|nc zOR9nr|FJO}0h?Hyv^6~gO2MgbDDIE}GvngV{`6QKk_&Hel%;XFq%GHp11#@i9KBJ7 zWxE462Fqc{?Ylll77(ERqG(F3t3?o?*XhC>osdJz({Mnp@qcwR$Pby zg=vhv7RXf5l<^|N-j8}2cRB*5wtVoVQ?Cx#vf6qw?JIgAvQhTY=jkF|#XVOZI8{nN_~Zv?vlrF9AN*H;?%tPpbe5N_ zl8YCEYN;MLKM(Y6TJ<_Au`#3x4KA6$>Hf@3ZX#)sfo-UQq&9ap0+u0LO3OVe*x_l{ zk&P^RW0gs{7L$p3XGiT@>yoyVyCwV#L}B2e_Mg5Lt!rOk2ztYn5%gKO_1hz_kVB~fEYaEnW# zg8>^Z*4?pJ*oSlkNv*)8!PT%dfF!JDdPQL*gpkfE_05Z(+h~gEmNgs@)8dim3BoF#=G#}S@OEmCs1Puh}+7^PdE z^n(I!1p7B1kOL`ciy?#&jX9ub#D{^(C=;6FbvTnD%5LTi2WjK_E5${4Al*J{QE7au zXb08ef>06>P>_R|WC+8>FZZ%Q6)iE2H*n|od=_sP>h$+Njfy zQitwLecyy`MN!gr=5e`A1l7PKh6EsRJ(UPWXfNZkkS5%lIKxV$_1Id$7wUnLl%6gz z#>$Gy@~M3}%ZyCehm@VmleR^Z@xYrEM|uB)AOF$CqscKRZRt0E+>^F`3@eNv)O`+E zM=yy)(smuLXzgatFa}tw>Vap=1NY5?Uwdh)l`@pHeKfJ|Nn7gHQax}{9_ZY(l5)L{ z0e-97;F9o}?$5$bD+m{|0%eeNH<||SYy>PyHr*D25vDY{VlVo`m0>g;JeRw9{Lao3 zea9zle^5=sleR?0HW@m2+sNi_2N2bGF+x%lWkDUdWQ>`A1g=GVK|{C-Xe-I3djPZU zT zzLNVUOmvRB)D~&P51XV`20~K@Xh4T684(n&#U)k+u6z_0%0&zMos~%I#8zPSz_xq9 zz(6;Xt(xz(=DpqaAyoUGaSvF8)sX6wZP=D3Z7ms?rhKyz@cFP38@iLlT1HuP_EO(0 z7KTiiPu-hV_wOjRPcC%7JWaw}(w2UVb6Iszr?PtyUxvf<{A2+xS-4 zMaJza>qm|EmdY$37xFq_f`?Ij?3&Mr0Kp7<6_4`$30CzS5#>k|#+@pdW zo^~C%yNupgWfHChN&n6_DEv*_>yhs)7V0bCRrlB!B6JlUU>onBU9r9jhM+fG89}eJ zK@D7TPBQ-pT#NXEhHw?oR+8$0ZS=s-HQK&v%dbbaZbiM~t(2?9HX2=RdX7AxF&0Dz znRpiPqN{9+OQM5G#dL=rKtbA51xZR-P(X=BSK=G3D1aoaW_rb5BZNbZ%r}!g5OdP@ z*vHc_gfQ?>tDpgX1YLj*X>CXBwYX%A8cMQJknO&#cZR`KtLlMg%LCfo{hrSJ#er@a z^Lm&XI@D44&A}p z0xR5`IKxV$4eGAQi}FA^&*IrxXQt#_SdKgdpfrY)OkQO?6hM&lR64>t*M3;NOg47a z5PPK&g?F?d&J&*!!Hg2Q)YFt2{may)JIX<$p)QyBc@ZkK1BcaHq}PIlD(|5pt}yt> zy@@j%rA4D^>(V@6uyn$g1!V>O|Lnaxj4nx*9u`$yGkbf~i>VonfYwSRVlEqCLy&PP zhcb46n9(KBE2}9GkSF|0$yh^xWRA2>aCSsp2oyMyC$B-spi7@d(a_2hXvkPYSS%o! z0+xh;rAH_p-}xdVG9ogvwx0K%?7kV1=Y76>#QF2oUxmN@u@u{HW0P%PhkGH+V98r}#1B%&_f&Cn#)tpn z)&!DhN4vKoU;&#PPe+MXZr=uaGuQpH)f0l&g+GS* zr)Gh_kYHeP)fF*YDbf`;bmUA;_Vj;-X+T!fCXqTyI)qWW-Cq=h2gSjO9eINh$ zba*gaU*FpBJ$Y}h!!I}IRqdc&YJ#8@om((+AWMEdRKjpVtNjSU3VWMHvV7(YZ(=D? z>Fl`>aK9txPBpq*jnl?SlSJ|}vGG^(*zf1V{Hs1uX1sbk?c9ff@ zZQ%3)2o{dFw<2PVmFe*)XHst8hdIMy?byFcC;~eKzTQ!uiXaQ*b^6;})+WE+d@s@8 z$D?>#hs|NkN4i%89v%T)V!2+z${W4lA_aZ!*O3h^OTu-Yp+57V*J2LT`2b5nsMeO7 zWg98)o4()Tkb*PcJ8YuXS1F1cb89c*D6O{EnDBqvWNZsmpV<;Kjs^oWx{sEl(GYDs z*ku72>4gfNNi?9_>p`I0ERPp6?ybjjFtqH3oH66qw?Fy^|1z-O`@j3eUzl%i%uoL8 zXMF!OR;xI!I$AxrpVpD}r#Qn$F)05e0{xYX?bkJHT(g?RZTE=BC9)G+a8nkAM!U%% zngS`WGLcaGU0ds-UfOKhd(jHNVD*`M)_ySNPqSRud(31U0RXZ2V97pnXNeZi zNrMmRryiEnVoW+w1eOu-XRhF7s|$kGgl6qcEQYWD9#B0_J#Y6F~9teeqS7=m@I#} zX@2J%9n^sYiQ`Sq37fX3w3uUq59xP^;M^HL4qGLj0)e`GWOa!b7b`~^YE(_b>FEnl6Um0t|U!=A_|Hg!- zt$1`$PpH~>&;?+@uQ5KV=Pif7q$SaM(QWW4Mlu+daNl}WxiN22)7D&t@ND`&F~byF z3fszBW$8XyH^{d<4TmLUj_{B83DFRQ1z`N|p<7v8U z=`97a(?UOW)U&*URf;WmxlrZ~GiWy%L?%dKR`*KpA~S4^Hy_CJQw_~s9Pcrn0FGLq3;V7w0Gz+-01IbqZGlooSr@FD$f$sB~Jbw){L z9}j`LeB_!UozW%7JFQaG^((ac9nX>vTcjH8I)f;7OIeE@z|5WSyi8c07s6zQXp44@PszP}>X=vqt5`dh zRf$JO;9**NxGCc0m8KsgZf|^=Ha*K%`Au8=V&OOD+mKSc6~ezCU!_;XUhaTF(>C6` z>2|Tk2F1ngt;n6y(x$DzrsIo2;Opm)(n8E-|bYj&YY#ilpIWr)4Qx*JmDd7%yU!A5UN@2sGMt2FU>Lo2FibrWxtA9sBK$evAP1vh>s)$+R02B94tV6^((W7nlB zQ4x4G2;AhR?TxvFrtR0>+{C7B+W541@wwEcn?Hhyh5WW14gxLHVKtvAM{rfpbk)2~OqGXLyP@sc-Lmo6;=e+5O|lxJf6X9&fTr4XQ`dmLC;c*Q*6Q6g))tHlR*>%Da`6#Y1H)L zAL9-4NE6sAv;iPZ}g z6V{6W1z(3Oz_QaSOCnenR`7IaO6LU^Ml1x`M!U`++Cnm6X5(SlYQH7k%stq{+^?fp zxF79RYTCNkwEg*&i^jhY2jM7fM*u)yG`vn1dO zZtAvLtf*71GvRV(YHg`bw~?}B==&`WDcEsHQnq{zt!sN5LkR_PAcRo9PISD4vVjxn zX^eA&u$w?m_zgCEG!(WoS}tj9v>xaT)2vPufpr9qE?u{7>YU`8;yHZN*1H=MziIp7 zADhp=`y#!6dLy^h_5srIfu~M~qa;OO4T1j3wSA|vV22lUv!)!pJMs&rDN^o*#z~Vw zRN#%_pk6O|a(jV!G}t7NKgx!c@Ag-JKYY{H{154ywl47g(Vt$DMA&&uWE=qivH4)h zM)*9QO+<_5q``-Dz&Nv2c+@H+ohbsZ0RbCc7yIz^h)vt~A>i=qk^lNn|2OmF_)Xh% z50od%Ye+|9e7y*~%b|NbP1(-8JCo8*>!4>T#woVo>_VAFyU8GmffQzSuT(S{ZxlY< zfQ?UD@60b!(>DBi##W?U_Qd)$+KALy7286-!4ZnUFB%&~GH-ZP#Z8(kgHiKkk z^9BcNj)(Q6DF>h(4-p%ev|#Ri*0FE%7%JvaSfsg4dl&aU?m`17>oAZMLT1hP(1=2Q zE?IMPAjXlp#m6UVj$tj5Y$xxNvhJQ8flz+g5JW7P!pY6GUA$aEaqGjdwC%K9x^3ds z6ACmJhFG{oS}3(P#$yG$cI5=sufo3^5<(O0I)f->ejIl${OkKI@kY7Bt->al4u7@F zdkU zljH)ONDqNC_lS=N?{G+3hf*r=WC+MRl&~sOVTF8z4%mwb^?Aq)VBdPiGY zv6GO%cBGN`Ioc2+^d-E%%o#4$mO@aW$3-AMa^sd(hw^0R@|d{?`wRKs&oeBl;UGTZ z!-j|TT{@ugA_n?wfTbW(J83eACWJKddx=8p+YTG^XFvP=S2h^<^WVGu?$+G>^0Uuu zyhY-7g7PNg2mpx92ly=|%Um4XHd+Crr3;KpMlVZJDx?U!R0QImv;E~i{P}HI((nH8 z&9Cg$7w`VmUfGu#uEzB-B7i#THs|J<;-<(WZ8X_wIZC3gv>;$JahY;UDUKF5zTomO(_eb1K66%<9t*L01$7%`t|K1A#xEUGaHG7NI#9Bf&qv`a zdujXm?REUj4F_Bnb8I1IgzdAm$er>_>!-BZ933Jc-DZN&!5$3M8t|2@2)t+ntV!Rr z4cBqJRW06*z37lNxQ`71YivphzaQp<G8PJdM`T8xHOetc9Rz$F@EAFEsT@( zEClA0O=ve6L{@sKn`HWa8E=v~+_l)45Wwf|_SfOYy)`y0r`CN1Ba+ekbnHz?-=%3C zNFp8X@~?pmV)+MD4&}1|qLrVt2;8CGi2;}CXQ zFd8($axfCssJJziVJI)f-?DeEw+{g!wsIGfna%v$083qPrNi6n1a_+3(Q z)#Z;O_(%`i5dc~0V1GqE!sqd9V!@<#jZew_%o#ScHgm1KCqlsEbc|YhZbRn!bAHma%b{D40$E-@pCE`*_j+`R|!uncrM} zEonAQ+bGfnzz4?hhI3-fU6%F7DnX(>lLAId7Z^{T;iVW<=$R3Ciid1@{y%lH_MAia z0~hYZAANoI%RdTV`}47B>&;CF-=2i&q+djNKdqw_PlkSEPWexPKwUg~x;%3$?X(=t z)b*LcB?99`jPm0NEdAi1>`n$)Qd-!n{d!Or2h@_#x(;Q(|7YgPze!EoU%WT;7C*>_ z?H3rsea&LohH2c++#~RNKP?}%*}V^@-BoNo+E#L z_03IqBXwQf0q)GL`8rb9C|?)?&AP{h!=8zAr^O4mdBpeE-X&LM>5*4j5l)+_Ac|kh1Q#F?dsY_`cH3@H}NQm%hzx=asAHB1&X&VdUJNYE=8nVzBKL!N)D_2@lVtQ^V$I;@(7gQc*`fD%M zXU@vfVgoUpAoI_qfv3ohd;f&ij!|_B$Z{6%VV=r zBan5!$?AQyQg|+?!&jWfU?dA;!$IJ=FdT2xIu=z4Mc~CCu)A*Grtke&32?_3hK`EB zgCk(mLpQDxX?^%04!rR)Jsx*j??uPqVP5wv#khPgRitO5!-^9>LHZ>408QJO!@?76 zoV|`;;ticzZ$1kzrmoD*m!WAJe(S3H3ahJR^j@_400?(JwoTi)v~W*0ZAEQ9YSVU( z&y#a+vPYW-6jb3L7k4g`5B9BAxRPZ9%i$PnQe8PNEmUG57^=0!nT3lml&J%;_RDxV zfmnaAk!(Y=Hf&$`u)8(im>)RnW8EB%&oynMfi=H)6a@Jk{+gBz@^Pc~L!9AaEgRSU zvm)Seaz`z_r7Pva6zYCzAg?rS9o1)(M`_yf(w=#)u(`Xrj!oO&{>7EM`SQQ|1M~N; zjr(uDC&9gg9T`Ueobg+lwr8|1lFj_+He1} zpDx`{uP93m^<^Va7muF7F0HbV-f20Ssp~VTv|zl5QGPsurDy-9?ak-@%Kt0#cjDiM z4NY6~{_67C?@HJ%PQEoJjp=8(`T#_+!wnw=g4~&h0<=8MKkON%S)IIK1aQ?oYJ~Pt ztW*bvAmzxUH>b9BkSyxR%~HWOSP4)(NmAg63a;H4rE z?@2Fr;;oNi@-~eJx+wyWi-5&LR~nPzjaQ`*X5$B8iq?A}IOEdv!J4+;l^f;FTXVXY>B>dP2BE{&=& z8AC(+bt%dVrS8?VrS^0peNl$?E{iuAM52%$@SC=%NsRxg`8UnCf9v1+{N~&6wc4vc z2>0jJhyVJwBsj#xZ`_WWw$n^A^Gbfvu`zcG;uLAmq=3=V?|FvlM<-^RKV| z^^an6=kNUO|1Lc3oVj&3f%WlpjxE>A9M=9+CNLXMXjwzcAL{{uenUd-V^08_Zmihx^(IL5gJy0stU;Jh_pN z0zqV5Yxe=7{dnN%@qTBR>N-&bUI79w#~22C$#tjPOn3kJXY#T47385Iegp_K>mJtL zaB1e;{8EaoR#_dIMZCZEf;x8vOF_s&5O++I8J(iP2yitl8b`5W;-eL{i^_9(v_bAvbbh^!+kkPNu%Q*f!-g5{HvZMF_KT zr}b8(t+8oZ|B4hbj>1udr=!gmS&(V8n+&3nTV9%dzl?Y4QJ6Dqq9p{7#3iE|fN(F@ zfr#np=y^k(`CTv)ZK~Fz{RSWAE-+4G5GJh&LC5DofLHeOxWBL0(6oK&+qW-0K#lLU zBjAt#mNJxhfrz{MW+lO$7MBSRb(pa@gmH)o70mwN3%S;IU~n;x%du>Izl_(5+;kja z6O>{oZlf%T%V>OLI)2o(@z7*yo=*1gYmCi8ej-~~ZL|)omVVDOTpa045qNC~gggJc z%NJi5i)YAdi(lh?)d=)gF0Kwsxj9NTi<`XGI)3v@3&RPQ9@99fGf4Wpm9VUOScRs; z;o^XmvuH&#@h2_*_%6jlZ(J6Q4H9{)*Elcam9bv2S2Uu`F4`I&M>_z6$FoV%nn@{7 z5$GfEU7!5)RB!F&i@$i|JDx++RyRf9F%f9K$tB-C+kEM4!F#Lax&C~aweMi0{z_jF zTkru(LGoRe7VRd3$ONf;*{${~zx_4aIow|$QD=E;>>po#7-{qtKC&Wl8Ao3lJoFg_ zE|fy}Jf2NNi_tdtkPaAUwhE70g`~4*M8Ly0Dkk1okbvL^Ds-Wt}m2$frwIS>AKr#@f!9pkD}G$5XK=^)WPlzz7T6|2gW8+A+fr( zkbx#07C{Jfhb}fg8Homy5uY_Bag4StP;C}-c{tcJBbx=?fqZ7S(TY|}zvmfVia~{* z7Xkki?r~2)g{#H~@85>LaCqy?mw)s#V;4mCBKPxqKdrs@isGvyJ$M}m^j9t}Q%gxW zN;Qk>N8GdxDgT4N@h9o^Dj_b!Wju0KmnTYiL_IeV0* zE!VS|=L?ukmj3$wP1{p``I}`=X))S|J;O7gl=ox^cz8l}%li$*-O`n^S#k0mC`Na?hlUZ^Cet+mR}P1`?+_Wec+pFTIFE&xk@ zE$zBIThfx`sqM3}(2J1_#s*gi_6FM{D($%tXj-1{B@SntOpnK%)?3lB#-{1V*R*vh zulK2CTiz6D(>B4PJ4N7SBJlUpPguB@8JtG-aU&p?9g4@YY@n0^eGbA-i*=WWBC1S_ zLl}oxQ3ty>_(H6;9T=NPg~VdnLI#?2SOg)^9lF@KTN~)%Z)2LR5lLLez|LC@z*YqU zoq-wI%yb=@J*kaWv|74+dZCxSsX`%Qg`_h@;B_Jp{vx$*ioi1<&|kT@Of5y^C{?d1 zfm}c0Jp^}RG%%i&MWNBIGe`zNia#oxHlGK1C*yFqIAG;0S}}k?^#AHko3@J>s+c11 zA`tKy z_5GH3mt6O;xlZ4-4F>$iNK=#tP9K1c%5ZAQahxqo5Umwak4ZlZkvbUd0bkiqihwq4 z58?K>FW-x#Gft*og-L=C6m8lHGCC>(1%c=KrtM~}Pr=x0W5dLygL?OEeW*u@z(XV8 zU~pHoo+%?y7zR^yL0HO1)MpmnS}~AkgD=cl+kt@$;*pS8EZay88#GJ2nS8KMmapZV zG|aqDUgBQ^a#7vK9ZPa4%}F;609pEApZrD{dmvb`p~W0s;KqZNE?`v3qXSwS2`F6= zcm)W!a7W(%o3@XYAaC@?a-eo!1_J$+i_6qfkd9KjHKl&UdkF5tXka`kS7f7IXOIkl z^e9c+5C;PA@td}eOL+8b<1TDA?c=Tw0NJw%%W^-HYI)5oIEJ^QBa2qQd+fSYB`N}I z2z<9D_V`j)KQR8E{LK$iY4Sl4JnJ`YA0Pft+=Di44=;cVBy!U>tWobG;m*HL-?Y6> zO;9(CHQ&}`hO?vFH)e@sY6Rf5}t1HK22SI`rq(0d3kI0`84ZGVevw#m}>O z`zj28FcGwA3t)6m1U3k~pgzRgO<3Eh-yY~(5qNk698B(tR+N#T&mEUrsji4ahXjf@ zd9*mJ#fm!Ey}^SR0;;uLVPIy2#5cYc9B9&E5rjZ@7-18Hqd~V(N+o$P&w}2ASp%?D z*=RRY_%+66hHLo!!!}ycYUu(az4XmxDiNCrDNhj?Am9e{CnNK-@*8*ge}CKKc8u? z)AlyptMtZY(OBlu2Y~F^gpUC~lWKWECnJ?h`IHCO3x+J>7-yoFWGhkrH%5XZdrziKSp>3GT9 zuw3ikw4DO=2{Nzp!~Bg;xjR;(H*Ot_otEWQdu@}MTazdrAOB$7N(sH<>cx#>8pI%nAWDgm8l54 zCIq&HEFW2~DFKc3l_B5|Z+Z&bP4MfN-%e|D6?<4bevPzo-J5R1!Mu6-!gWM^Ml(IX zHZsm^BW&==)+Jjxn!KL@uuWtd1VWE8b}C3_MgTZ41_%Bq3#!j1v^En`-qRou%ddE$ zg}T#)A=h^CatXz)4a3s5)A~(Pi&se~(BkD29IAkceZ5^0w+;e9^}Z?)17+@3I+>n=_Kac1e3< zk{ISkL$Y)ir7m$7HfT2)L{1`I!ero=@kZgp?G6&uxF*3|(dDaj~}V*rxu(e92G z0o##6;%BYRORNT;I*TQfK`3dh3ai}XBM_gXaSN+L*y2+-Z}B0$y6v>egE=k~al5u@ z=)WOKtb<+FPeKyfjZ24h29cCfNxZ(_5^okd+V`;u4O^EqC4hKb^5dJAG=6I>Ck$%53 zycUB>DFQDQfm`!0{;Gee!D(C{GXiqip=z|uwG??I4JSLTQlsJ{Ey`^N6EI%HhNcSx zmI9&H_7K_By+TT#KO@`4UD%*$)4}qt!o~-+XyzsdZ*NSb$R-)d7z)$OY5)-V>Bx-S zRIFiE(FUFezoiQpje7sk_Q^_B1YQRMxFNl{PS1eyFp==ROmtKP9t#1iKfD;l4_1e= zY6znCEEL^ok91O_F zH+&Wh1i}D8?hXa}duVx@tnn%I`<-E$)rlhTdJ%B1H*}5s)gq98(!#j#U)$i_(=;Bf2tvG5*oCd45G{jNQRGfK200Hj928Q;|LoYKDS;6 z%@lykCM2T+0J8AG-m$(w_y_WtEzzcp2u6*NhM* z<4%jWn7sCA>P#576PqooRE(z4t}}>wNG8nseoMTqm+o;Nn;T=zKTq;80LWMvI067- z)4`GJIa`<@5=YS*pOX8TGhD3EtWKT}feT!Z8k6Pno5Z+l1RnG(J*+~k++-6UcjPtN z7cki3+_q8cUa4p@UQ461Nf(=|n>SzFy5BKZ=CaY1#AO_Gt?fo-JY`1jvdk$h=6HdF zZWe)e?hM124lf!3_Y~2U=l@f9+xl2~U~CmQcRoyivUbf=iIe;Jy`L7H_9w1SR_aSe zz$3V(>|A`q3T2CtTBV+?>oW&I+^0p12F8SuAe{JxdWoi*xBRN7MG}xPs=W9-wK<508>SZ**8g>ny)=S0R8%1B6L6#T4>6 z0AS58rO>qHaW6`tNwjRUKFArSHF2Zk^CEzI1{KpagIT&pAidLq(ZB|)soY@P(%bQ* zRE#g8Y3oDzyKUMc0gLen0EkToN3Q2=VS+R1DEbg*xLBiEoje}`7q}j^^p+xHgV5s& zIp|sL#1_2VQKr$pfWa2$iKZ=WPA3y=ekVMCB!Kudk;G-JnzrG=^KR;>VKSrpXz`p# zc#|v|znw!`>+qDM2)r@`%A&du_?h};!JLYGvIux&zAIWw*?WwQrAS>72XbAXISB5= zXka`kH%P7Rp|ZIrgv7Vu4l>ZRI9wdY*!=lbC`i4Sv87pC3i>_(qB0$sk(-J&%r;sN zeoL26FO7Qt(DunnRRmrc0=LfG{oyN%S;PHE5a_R5T&BvZG0E4Hw|g1VJmR}cPf@3x z&V)7p^9`r0l3~g7@o{lf=o3_@5RIhH# z_x4TOkjDW4(@cfwSYPNjZ3Pn@fk0ihmIWkVGfOq{=G_LaG#Cvo`W0GLIr^n@v5BP8 zW(A4*JQ^$0rZR*kv*ctN0?ZZRWac(JqW*c(E7=B8-U_J;KrsdR-rz{|dA6h_$ro+J z($8Y^g$KIpOp3J*Q%O&azy%IRExn~Hg)KdgE2P`A44&R)Z;jaIhD0=-;f}OM`vL}A zoSQbP{0{xbFXMGII-7K{$(jC6(7SAOCGkAE(eH;2jD?LEA^cNX%<%$G-7Es{+!=;3 z9Tb6AjKGzB#ldUnuN480z?-sj@fi$di;-Go`K;?R2SGgGix>@zC)tt@siN2Rf7*j?+;mg_JuMfaRWjtj@ZY;Csw9$Hqv~&SuZ=pl6 z9h#C}E&{mf9yP%7LG)4Gbd1{$ZJFevWZK2asm-2}7UBD8iS}rGiZeX&t@L{$&|kT@ zOf9X4p1yGdIue>ke0S+7>Qw7Yxb(DdTCu7^?kxP`Uc@xH|y`MQihzi9~uU zH?a%ky!8RtsEFWxEZ8IbGg_YZpf$>(c%jCAQmpNHN>Kz}8v^#V1+4LY3<$iortQ~p z1nP$X|~f58@VMa$#-MrftSU_m6}C>MzuNr3}l(-BJa$ zsS;5V!e|J&U!hf%qhHEw6G^4rzVnI3N)g*shR|e|oJ>O)VDo0vv=u`Zh7thDc^3c? zpSpGA`aE0GlH`l_L!9AaEr+7}XGP!w@1vI9QgCb#dR!sWyR5!w8ce;*=5}HWUhXK< zXkWl!i*wsX{eEUPei<)qPA5HVeAEbk(>Clcaf(e6mvI1qh|fo6gz)Fm!fm6yfYH(g zM$wy&ClQ<4Ql=vCj0nWPY5R=s)%B-~fJf?0*~!{=2^mYNx*!bXx;}Fd+=gn=O`8sucU^3*Z$st$=kXV<`i-Gf6_=)M;Pe65sEnt~$c<(8 zoHkkyk(MrC>@9RCwnI~rBJlbU2#uWlR(%_F|Q z^ngmG?u1KE`^KftAnAf+jD@M%uLqUigXM8|l2*{p5-zX3=uKHR+jJc$FsIJb$wn8HyPfF-{UwpgAoX-V=$`ytM7vBscu z@{9;r_|E6nF%q9=OIONH%Vy=U7Z&Vv@1o5ONxl7~MB>5h-@TDp?xU_>2Lp^wjtAoa z8$8*J-KaG&4FGT(jq$X7_^fG3^3=BQFvz0dI*w%fAe>1l?}-q=FFLWf_SzrFTZ^LA z^1Ni45*&Yt;x>P`%^SaFKT3U|XrtX^5XIh$tiz32`z=3qD00(rgpGv1`CTzWIs#zo zPnecB)R{lvA<^er__qZ>E7MixYDFTm)K(}ZO4jr84 z!s;Lb6oy5M_m-{AU=enpLX1l@$lbw`>M(UF zaT!s=uxdvj78a(1C-**DjJCmtbO-b2&M;%ri6Wo~C<2PWIsy)&yM<%v84Tso;%1D8 z1Rn7ghxHl=;(YLhU28iqxW1J&UtWeA3mIsZctM{JBW#)_JQ@Ls;|PGcLvWdqT@tUg zn4=re<;B&KZCYEBRv|^8M&RrE@FgBOJRDwPY#P(Yfk6FDt~(~hFP)Jxp6s+PlL)Y`_v z*yh?U)2?3!4a12L`r`l_(^URZc}H?ESp_0Q@CJhv-13HPO-pKDYFn5eWKnP(gptU! zHWO0bQz7smExoo8c+|6O+OA8vexOvN-DD8O-ixfmjj2srW5a)OYtL089`3YhdkB#V zj1ll_Ys1*U6L7R?`vf3=+AdI^dZ2(3kFR2dJ_o7QGQ77e6mxwhuU8$Y5TiQC-NBOT zFoSlJL1dPqyYH6{iy&ux6`Mz7%j9sf+pQ%g3!Sp z4AdI%mHeU*uul;U?yaYA)%bX>tMPt*@2AzI+#cGNpvNyC0f!KG3&)vTsjLF^;-*bo zkIE%xjVYgzR(c(FA(0ZUVycB~9DFPJ&Usp#j@<5xmFY>f}R6!lI^!Uu4C4EO` z)6N|AENd}O_1WZ6nzmfeW}bI#&^mkr2&0J$?8rC*;Edl;vY>`JqjiT!jD$DJ;^Y~o zS)Dv50v68mmEjnQ&$Fc~Wv6Aca@Y$Cc5sb&@N?z3bm5ejT%)>kQ`MJg*RKS{=n&3m z7+|yS&}!3m1fkL&6oIDYdB2uktEEj_{%At~tHw*G(BhF3e>DcDhnmuyWt;Uu&M>VV z`d5KRMZi6(bv3RCC<2d$K(}ZO-dy(R^Kh`oOHyi;wZTFYMJv`I2P&2js)O7eEU6AN zXg3)|W+}S+e(A6X!e(#qAX3YLPzR8RARPg4%C9zUfwvBdfFhs>yjlbtBHt|><(0*Zhlu#CV#({{s;MB z2I4t8o;Zs5JhLP?%<2lwgUWY2IGzox7)N#Irm8Q~u3tCv)8UP<=@h;@lK83v={VVw z*h1R8VcSdXC`g{#780W@b_RL`TI(^D_S6VGNJ~$fwm5AbkCdaX_0n0kd{AlAb_p;Q zdZ`F_Udk^uLSyuswlDYGd?bk#8L?j+D!)0 z6yKqmzF)?>;CJ^fd=x;kB^k+REL_xqobt=2?I|th*x*CDTQUbBYMoJ1Sw%n*ct8Z) z1KLtkPmh3{zk1~gabR^=ifFXB?G`EvbAPF&M?&lWxK;Gv;AZzj{qS4jrQmEb!lnrz znvnN4G8zxVSgkA$mxkSneMXBpI%tiuSTag$OVTQ&2-FCCT_3*0BX{PB_YxD(m|i>r z58Kk)bz}R#9e5|U0FyRt7eERk+O%E6>2*t4gr8Rk$7DQb#}h{ppJ$c?hgn^rc~H;1 z=U~M+syjDpT$y(LN>GU6a2R3JDSUS%@l^+M=rRhh(B8aZTTn#u)V9zWWwBs#8_SZo z3Oz0Y+O$2y*BYB-cCBeVKLBBr(WY%eN_UDtjR01&n)tGg?8^#Aqxtv{zzaf;%y?6{ zOb|NQgQ3+jtYblK=3NfmK+#PJD`tp{zt~vvQTY2l*_e+OGkh=Sc2Z>q^ggSsk zOr#(PmccsB*YYS_Px)nmdP<*{r3UwrA)rm$!xOq|gEl>9{if|9gevf`2so3gw`-g1{)X1CPLxGEt#8DP zN9XazC5pwH8W?}$Meca?Hza`#dzd>Sz4Z@cIqAkhj2!JKOKNcy0 zO^&A{qP>-$|CI1XSxk)ylh%ZwqavUPC<2PWIRvn(`lQ95s|icix|y9;Ss4fY4>8VV z@z9xQL_wKDyUHN)ZQNn2-;udQ-NY+m)6utD4&rqHiI_=;0KmX>K;j1T`}ffmnqD9~&e zVyU$;9x7NDs7sqmw?hm`LW6dbK{RI5^*;8?c$Yj6v1tN`#v&;?|0*8%@UIU*9er^BCB8WF#Ow5V9$nRDTUd*AgVJ+CK4%%U0^YW5;ka-cr*E6Kf>k?dI%sM2`P_b z0HW;Smi*pDF@%4p5e2GfBcaBp-#P7irjP@VuSDzK(diZzS!#nQ267SEiAxR z2$LD2jRj8LYJ5uWauO!C3X9eXNoUW7K!4>b%hXa}c%Bz6t`5zk|BGzy0;?2T@B&Lg zve9lbh^DxXM97?=-tWZy@N(Kh&yexdn= z3AGkvRYVa`1QY>9phduffXa!5sBZ;l$2%?7s19lI2bE$to(+ynj~TQr4omH4 zgk+@5Z~QV|s2&U>Y?=U~70F1(@X;f0H2@$U49p1OABcn9Mr#Lj5Bkz@60s$lDx?U! z90csk2}L9MND=VJYqxMONo%iof@TT|*szk^^cR@7;yGvU%RSV1?Dda7fQa3H|1 z6~33rbR1#REaB0HEQ>O>-_>*3k`e ziog*9`0Et;CoPQUN0<{oX|dOGe1bQ>>?ZxBMd;k;UXU~HD7?ad&uODwXON`cimWv@ zO>4g;OOcz7BWxsm1Q2Zq=?H+SKVjaozCifGn2r*y@er%=DY>6I!?ZT_t<0xFz`;>2 zAANDlYo?G!vz?Zsq_A)wTQFdp4++YTC$JC&YHbIdoIyG$)2?3+jn!dit7n>$8>mv{1@=TlmYw!w$=OUx+o^>#T3l5ja zP7G4B!DZ%mCA6mM+|=|o%Z7d5FXN@$bTY!G2_V`?r0H4aS#7iy zURt_8@LsV`B39|@fg+#?C<2Or2L!u?1FORlLY7jyHKl&UI|%N?Xka|y(lb~=kwG-z zX$6af0|9<5`Ad@#HcjaeZOO7Iyi-)T9T z5f(0E3kHlYT{2MNjWDV^a|TJeOuK$POs)6@%F`oo(9&BAh%LPf12dW6F{^fiOXmlEZ2d6crY-dQw3@pt%aAC?hm|I?30L9 zx_Y1pC<2OrBH#hRZsEY{z*S=gl_hhxrqqvk2f;|QB3fT$|VqKt!=XTIlVM`K1Vv;0n?M`)uJt(Gn@(o4^n(5y^!R0I?O zML-d_4*~}*y(N>oM&MD;vgvv*IeAa1M!U`+Nxc=>qo%FMO-E^i^5b1UfM~;o|I)}M ztlzaxLPtCOrtJ|zpDy1a^;|ys0z|G!dHEH_ezwzclo1x}STL&6S%}~bhD{`uHf|Jt zV<4*MWa6yr*GEp=eA*xG2H5PsR=X?8i;F6dHNU0MwkgClElHl*E-4Er8zU#qFpGcK z(&2d#Xj-0aV{&tnCvmn~>|G9emKWGUYjbl$j-9+CtI=*Uh+=G`9yM)wY14RTatGQd zOL_}((yWzn0Kh4~{HE$0yTcz{{hnph^;~lD zK1)69H*J?ZpKaQHYYx9@yXKemh5mZvCBQx*A%|RZ`RGgL`I_PVR~Y-*PRmh7Sg>Qk zs7hxcf;Sj8kyP5oK>-DDJSx+!Uk?q#i4gkZ02^)E_Tf_Mqa$$8(p&S-mfi*O2R+N3 z*n*pPlxeh^45Ap@s7Fm(+MG@9z#L^sZ$VBHmvPXvow+0Ljx+tHEuqkfBA^H;0T|evvfw6l44uJL!9-j0|7-VUa#)NAT=9YW`0*f>z2Ps%4XTH@B3xEl$%aQ*faq| z8;PV%+bNvNR0I?OMc~szz$4||!hvOKX=YkBCRU!9gJ1s{kVKo&Rs=ZvFSxV0)n@B2c z+K11YmV+&7 zKg1c{JP5m?D)DI%z|YLdj~en0!cQbF1>;&R%S)yy!HrJ_n;&;va`Ki^jdq!gJblz6Od-IDKC%Tuea&!p07>P9ZjRO?J&DR3I?CWEL7lHn2o z4^m_@-eR=lQAidOYV`w%QXZl*j`~lh{PL6fDJ@3Z;6pmHa0q!mP-`xxTtz?;Py`f# zE&`*4!*!(x#L?m=ueC-$aj>+?!l$KghgrRXdh)p(2MQJmEK?3LjCZ3mp88hHflvpK zh?0?v#zM9Z1jPB^$zEDzAuU?W@nO#}W73Htu#Q0ZrtM4LzJ2KdYJ9I9fjcCC@1wnA zKK#-dDdWjbi{E1NSY+^}vkPp%IK{@M$q`F|P;1{ogx{z$Mo9b(r5DIRv&0Mfd>CPa z@b5O-l97x?!fpWAsEnt~=rWesbJ}R{AkxwW#=V6Oba!m(K48k@CjN^mx>!?J-6w@x%yx_r(70<4&8l_d!i{P9T7F(n1BFMENRK=yQv$ zmZx}KpGl?F)Qwc9T4!=lbsD?T;o|Q=#NsbSCLL06qr971P^i^}zcJz=D&weWyHSBg zXRxFp{8L(t7FuGBbYvlPI_plT)#WPjg&|OGmd6XsJ)Y?!%g=Q+-p}v-v<@(MiZgr= zg0jydFj_d=8ADtJM2nwnEzID8>#w~_uEf&l$DaJgiY%(yv<;v<>>1vmtW!l`6#;G9 zt|Fy!A1?xTNNv>8<2pKn;2oKDKQ;V(E>_v5XIYC`s!t|jDTvhCcTi%B^F-6uLw7!m zu(^NJ_LN^^E;+taT0AFrS=o%TIC+L)O^4@2pe|cWb!k&rekr(COPjXk^CGYjAoER9 z0Gr{1e1V$~rBmKmGN2$7>y4bX( z_H6PfP1~8n!W&_8|E6uRJ)6NVo3=CA!fT_w1FNM=@4IMDX5|b|gp~Dk2-Ib3sV?n_ z5O!Lnr~}Kx8fq;uj>>Vxl~@R}jdq`|8V z7Cy;CRL0RaZ6P)vEZGR3$FqrOG1`Yc!!y^)Qv?(NML-c4AkeIPTsYi7zDwR|adohe z$D_Z$_I7QyM6py}H`Obs-zbzyq3@URZgj>|u}m!o*%ZK=O^cX6%Oq9B=;hhi*@oje zFNFq4!-;4y+J`;EL%+&U1jY#HH*Lq*DCbi_;0}pCP)qOAYuZ{P5Jn{B*CNX}`l>Nd zpAR@E+O(a+^ht8-vb9u~_5>O`ty0wWD>O0AwkOipi@UUWjHnoGJ}mKq zJs(`FWg%Zz;EA{+^#Oo^`M^&ap%8fa}vT7@1N0d3kI0<2Bj z@Eml9FsXndFhtn>cc?BNg$)%RG)tBg%wqk$1({*?1Bg;SiC$rh2X%oeft>Qo@K0$mT4>o6 z8h?i+VH7&pgMrotd?hOaGX$0{-I;;M=h?@1p&mYM1V#&oI|B=ECDG#R3kx%NSofEn zC0Ampyl$#jP`|Mviz=6v#xLXD=!~agnOY9AbpVMdiOXm#WNQFGoDZICgwNyIM6?*~ z!=B-pYvm~dihv@Z2n-Oo1O20E+WL@?B=xj^(>AVZ(yWzHo3;TI-5wl)+x&LMyst6ZtQ@rfbEudT=(kCyL58to>7Xz4dJ*Z0eKDL0!8u|fC< zAeoSi4gi?BBhRzU1#INZCKBz9gH(eLa~BwA#>k^JQgosSC<2OrB5(=;JkxDb;+qt< z2UcwDw74>k`X9|}k_9KwNRo|ql|dBPyuoovfgO~rxrrC-`Ct=!qty=}O8F#O8cYnv zWrj3>a5Ni4Bg$-i&r}l6LV_ou!e?V?3+bU%T04|ffk#ImlwUqLi3L+Uxv92uVG@hm z%?S>a$+pw_JPOaK zqumf2gpUA{8Oi7XfFqZQ?-KqS*w(agCPTGulR|?Ja~BwwtkT+&ve~D6Ct#^@d7k8h<9beSkr2}JNJc)sHI3!Cc%v!t2Alk{KD25k9caa)4 zXkOx6^x}NJjj%!ZTSJo35dd?C;3mJ((%q8yR%`Rk0|{@G#ggsIl9UQP9RlGw8n^u3 z!lilIz42v!Fmr{UwQM2WWM+J{$F2W{D6tN9o24J2$t#sAgJcEIqA>6JbqB6m_6VCM zfT#wNEhhQ^6#jU&sq_KcSa!o{-ar{s;p2+ri8GwarJ|{`XGQ?)&u-yh|6(CNd7keU zw|Wr|mePvZ5nFKb1!ejxsH}5Q3`vzGr}kUorOnx7gv}k4=&dY^!WscEb4Omu2;q}6 zo9v=}*fTtHtvp3Q5l{pafdK-j!yMQwMD0MnOWtX*M!n7Q9%}KOSJ-UY^T!TxG#_9o z2w4ciNs~cjvbgjRZTvD`u;+sVn_3oxI)Fq3$;c=#+&oke2#)51Bl|vDjJCmtbW8IK z6KXBUs)!<>2q*%IK#PC{p8QuYH~_%T9fHe@5dJBxU5=wH=w%iYt<8j#rwAwlihv?8 zK)@THIQb_njK%5{mnlvMs)fAMy5$qR`DHg)d|>><1xnLF~{%giBsIi8LZt+825!V@}A>!~v=)~2qN`D6&x<)fuv z$Jz13QpDvMjD`c73G#*p_mcyamk^F;1D^!EhM`?&5KZ`E2U@jXTlgz8pM@-C9cFa^ ziMS(K$ku^?I3HMOmp5#4g~aucp>~ar1=|ot5@r)xn+YlJsSr45>6QC$5|HN|)$~(G zJI&`}Xk1QY>9 z-~<8|vREB<%hZyoofhjZ2Yo!OA7ttAu-UAjT;IxaeAu*wrGsIFO%p)0B8kgr9BkJB zfOs%4Bfxeb4t5)@9nd}KO9RjFlC%mb0*Zhlpa|3mc;gdc)Y4n}NMk7_{Zy_KD^1(A zwInxfeQ+gC^3VD<8N_Uso3<|HezY55GiuuYBs6d50Id0aFM&Ce6xOsPT4S?%gU{|< z@!Vzc{@#kUK3l0zjX+(tTDo_f9ZxJpT%MI1QCPT)M{h@HU_9ZCkgwq&hzqXHAR6#- zm$$B8E8MlwXE94@hgls!BJM~QvUMOJ&IcCS;v|aN2E=vuwyhqdajNc%u-?UuI zL>5csbyKr~a(yey@#viu9om^k@-wUJk)KP>`v*=p(B<=IjNwbNRCdz5eYwF0a}g3unIXA+IYjZrsZLc+7EGtS^N(|Rr1p!aL}~1E75q~QTJ=wQhny^ zQJS{Av}c~*W#%x;do*p&_zm9Cv^}F$qJ7viJOfI3ihv@Z2q*#r1W=zku=yF)4&=M! zofenRx;~RiON>*jYqciA($|Bk)3}W|i*64hmMM!v#*5?m;94yU0>Y=aK#n9AcFe2~ z01V6rNA}Vx3u)0}jt_f=8Iw+4Fao&h9yLP$sMe>(d2LUn9-etWzxUHRi2fp!;DYNfJyaiEOfDXm?Oqb%rU77VS;gp{WUC<2OrA}~O}8=pAR>SG!9 zLYuZe1X#Cxn+#$$%ipw3sUPk}*xdh{wudg0zxB=s~R)CdAYVGz1^@Bkl{$cC-wZi2@2;I?V zswLB5hC85S+ZN?P&O){dM2O%G1{T`dv>hPy$&wFRdP}%?-ck2!+AcYHl&0;H=XY6Z znB_g1wrBhXS^cK%5@0H%2q*%Iz>7toTeOB~?U{)AX-TxW`qmY=LDjbtTW|(TUzgCT zs?)fQ4Hn%V#Kte<-RO*`4lHU}5b6LDF_K)^fffH0P}+PR1OOb(2S;`(mPr~;M2pcr z>=_>VRfZy<2q*%Iz!(7wR=aR`(D}^9ad#LkZeii6&GeTZP`jo{6ielGQ?r6{eJjgx z`+ms78sjZS!RZboY?=U~t}Kf(4ghdnKP{0N0iaV_%+bQ^D2sDvxQ$Vd6#+#+5l{pc z5b(w)DQWfb(W^~cqBp`uo3?~VCr^w(UA9_!cX`G-jf~F3lIHTPRK3EgD>R5{(>B93 z*t5{qrtJWsPnV446*t=bu9Q{_w_^kqEDM0UckjtZgZylUgUvdFNIZIKFkVhzsy_^{ zF%IIaP<9{XgFqL6CBGi#!;leL(vswhc8yOll0W>~;$<=`)+R#AdMX4Qu08o-LEb_5 z+aF7D?0)&o2T^NFaAOmv{=*_7JRLpXu!L(kMfoP*zD)+vh~uRx$C z08tzya|D2xo{n#YYZ1O2Pe+MXZr=uB8}x^ zLjac;mNLimuwIpFlbrozr)4Qq*JmDd7>Afp!5j>*6u7l^UU};uYUX`|@Wlf(9bFWo zB<&|7Y%E0S%@`rcIO;#0@oS8Sqcd6#I#OS^A1nyt$umr|I#C1^0YyL&SVy40a&6z~ zEZE|5(=2XW0v(KCx!8#<_`s4EBpdA}gJ=q*@EJEAg{}50>vQHE?kyxnS<+is7CntN zEA`TP31v$o_t9ds4L+nVt+EmVwS=IfBCw8tKXV1In|)Bp@HcIBQv@Cpfp^)s$J3Nw zjJrGIbf?8{v0Y%M|5q_7w%|-G8FL3|Xg3)|CP-n{_se);X+8|GsRKwxBqJHk1-9!z z<_^IXzsBI3kf*emV}lRrcT46VM6EMQD*Jc{)a7HT_i}M(mmIfRQj-SdeuY+7j!OmD zCX!lPoZXgC%T%=B0-B7MlcL+1!CVpU2M{$K)Jsj!1)!LMd~fiDn8RPvYCl4>9}tR> zoP{l3CNn?bDeK7*aJbN<)yF&NR7nOO-VaGqjCbacJc}8%`b&6}@(`7A)U}4#e6VDnxwAxz(Kh&y zE@05hY(lM>kn$9PJ_7#C72G%R=u~amK03sox`THa0BI1iId=zOmY%XZt%IJW7>8I{ zN8z+LTu8jb4BAZwkqJ_m)xFZY$P63fwdwF+H^in6AX$;bWgIkZPx)oj_LLTLZ15rd zE(N^!>7H6p(&3pAsLNJXmw3Trm!fO6Oj#296U=n; zI<;vF_?r5iA6<9!`<>zWNm8yNpa>`eia-~Edfn5eZ3iR^8b9^-ONS`sAu6LbZ2^c5 zihv@Z2z=TIyvyki8%Da;Ov^}N8bJE~L`rVQ_2vO^dlFB|F0`)5+l+3~1(yJ(hwbNRBd*n`}Ws7X{Zl%s3 zirrGyVphL*EAdirHi5aK)ej(=aIkX(0K}$)FI<-Ag*2QY+M-?Kv&&*=Xv-+pwp5)z z69U?_JqBKzw&6Kgo`lDMse~d>Bk*;7_!5uYnWgb1CZI9Bcm(R=(J|gqN|7|2?6fRJ z>-x-t4&z0P^5e--)w!+ddEYekBK*3smma67i22vBG5;`pSgnj zCLW!t-?V*nh(C1)?=k?=AY^my?hG(HEp6Hgd>2gW?y+#Eqns0M+D>8mG?{hT%IZ>^ zw&ij_HMzsaL1a?^>`9{%wU{5xd|{j^QJV_BeJ8fdqIj9iHnB{kl=VaiXw&u>Xl>eR z)Asl(QHcoxZo+#htj*&4QbN)=J}v}MeKqfU`6{-&y`7}($ZHD1wm$O^ti_5t?Q|x% z7eYX_wy85nnk*@sdJ&q%Aq6`QNg82eA+a%%NUk(*M*wV8V5Bn;dk^LrEk}dU8f8H* zROn2KwGLBBiog*9N0+WUGVo}8UjLjtnkzN@i6hWoxwb!uzW@+#rDky(^(=Q{3qH!d z&}cUqL{lJX({=-fjq|Xz=PFZ=_S8BORK6mh2q*%IKnH<$nI;XwUHi48vM24dv}r3K zT`0Yoc8Is)LpV`f_xrhsit3up2QA0XJuy3=wSIkat#Un6aFdedz3IBY!hnKgV))!IrUHEqwCt>@39wI4hVmygu z(&7FtNyIQ4?Mq_tx4gxpL`q_Pzl;~E2g3*(grB^@gk*F8z=1=sliz3wu$|D_eDmP4 zwFY{m35;ORhlJQ%M7d9ifV@Kqt3udri|cD!<_EK#7OJ$UhF2MHe6kT&qqxENiI*Zi z>E&ImU1ty_To#M_uHQ|(MRGD5VT14`fM@}vLjWe;$Vw}AIuh8(noV-FsnAGb65c3_ znJw~S*`nJ^K|mh4X?4Idm16t;i3l&0g;rS|(t^Q9{~ZK(Vl*(Gz)}#XwVMp00U?e2 zUZT+YHo^v37H?%)JOW_JIsBHA<&4%vgeAOD79uwtX>BT{OhrHuPy`f#0RpIeP&Il= zZHhe7Mw6YEqa@xpSrG7f8ODnk<;N3P3IdIGok23da?ZkD?bn04IE=7y(5JUjoD0j~ zBS9!w^M*ihG#}tM2;D==({_zdq2KQe)2vPu0YyL&Pz2Ty=&xKxRtL9aiOY?JI9G>e zq3W-_RG&F3OHbpZ$spR`I^yF|*c!idNWm=D-#d`0WkEoeTO*RVjPi!hLj{3sRlwN~ zj->l&FG8PJdM`T8 zxHOet=#m#7F@EAFEsVp8V?tm)*@SkJL1bC34Sm0iH`zJdjj(9~h;}5S0{{+PCV?M` z*r`9@foSC?EyDS=$<8PXaWWlgZ7QYACqn>tgUt?6P=$k1lOBh%(}K~U36_Hq+)qvE zeC(mT>j|=rcAY`AW#cYw4rA@N#0&O(u$f)7`T;~KpGCv%D_b7`;ZDaZa`_k{WjwK9 zQM<-xm&Mr9mP2b>qRyWQ0gux$YU!2BZxY~zytvKLiid1@{y#Mm_Ng7h-~IgFPwObf zr#Qn$F)05e0(J4|seR^F+G#nOsp~U?OQfkADLtFO(hm;G?qq@`rG>@XuLpH;Xe#1S z0MVL@yKlDzeII}*cDTWBkUMi{?V^3yGkh4e3Mc}KfFhs>>=9_zz1=dk*XU4oT3j8P zNB@H?Jr)tvE2!JV#Y(}0*!X3<8=djgfkiC~LLERNO5!pOUY^0gd~jqVd>+pxqQz(* z_6*NlD^C$n1QY>9V1R%%HgN_mJwH&Z$sgoU`l;`Q;EYSte)AM9&ZV`)WvTCChs7tG zP0th=M3&`B)A!4G%ZJBgaj+X;W10Y>b|QVxnD=6;55St=wrRVjg=pDkeULLuYm%3a z&x=658*uYVk2Qp}c8%oNS(Azuj0SGMLW6Oi)tC0JNHyAZ22spX)?tSG7@8$s3eF}r zGmBO~fGFj&Xt;f4>jNO%>BvIc@G&%%&rAy$YS;MevRE(~L}+bIT%{fr0gux$YUwRG zzfkI4Ovx%QEm8S?O0*ZhlaD+g!?zPL5 zJJL`5R!bIDzSirL|GPP zls9x9DhTA1U#{4vv=}Y493mjyW`fYc9t_kP@Rh6xC<2OrA}~Y18k^Xo#^g+wybm(- z#;56fA@qBeB8IM~2v0|cb;<-6K1nt`)B7}Sryj{1VbcT<w?&Ez874l&6y&=D3vIkqTGO(yMeT<;!{t*?H&P`&Edm}V zchu5bx>7ET`Cd(1NA=m{QJS{Av}c}2*u2Y10%1G?iQ}kgd&Y11^~h(mE;+dHAbHp` zEM|371QY>9KoK~BKwUg~YA&s^kltxInyKqEskC6ch*5q#fhGN>?HHoOY3g@v+8*Hb zQL=HfJZf(CQLWF6`x)~QdH3^sKdqxQp5hE2#i0C?2sG;+-woMp$1Ry_wPaD%rmZ$@ zmo6X`QUnwMMc^Yxz#5w}95p7F(*Gb*-uN_qFN6ng+I|;1EZIrZGkrNt+v9KA3Ow^s zo3?X&K4tDrPTuCByobs!He4nj>{~4Zqd~1-gV%3OSYprIxWcTp#hEPvW$Hkz-@7qh zPKs`4W;3k__XCJhK8s3B;iwBhF$MYVP`W)i{535LThxAtGh9CPbR$*b(<0yxT6#;- zTqt#~rY*InlSgUVPCW|q5t_DQdOE^yY1&Suh1o{?z-L(8=%@%N0*ZhlZ~}q4c=Xg< ztH-kVPRr3uU7ty%)zpoYo=sp$o3=BM0fK1QY>9KoRI7V6k>-)3yswB95?Wy2ep9k+f+$#!@*C zgFszAvbw~J4Y%Z^)jH}~Hg8Rq3b0Kis1-e8t22m13yyx%HUd%O)1E6wtfmtw{-;99 zd@2My9O2xSvy<>TZe*wg_e zGm_B(07otp-}6Cr=6AtJwDNm#!ud^)5}`A9fpIAoT3eD-qZr^RK$Lmg%;4q+T(LItxw_(HC=9T>C<03e z^j9t}Q%g1+rRp^$kn2ahhu}_(2F4REJ*LsFGe`zN8vUq;8+++-c8h91fT(JrFXIRR zh|P!Hiai$xcNcAqkE0P}!Qa!BUV!XrkR@5KZmA>{k0VjCaAWF&9Wts~=r!)fJ3c(tirv2urv^Yh2 zHd@?q#)y-;XDUs}XhWN}@zn$#HV<-!X>E3jl&1&`5YVRW02n2ILI^nIilyw9siS)2 z5=Ta7veRNc>miK?zr`VpL#(KS-5Y!%*4hq?O{7BN+i(jRXwqR3gg|!~Vbj##QCAX| z(Rf&_0dSzs2WDimoSTb-+eRx|EnPmn(96s^5t|7q@1-E%pCS-k(of;4@$p<&k6!@-{gsQ$)KUhHQuUe=$n_)MLvSZX1LH|q6dLV1gJb|CZQ4dOYJ6M* zDDKWYEQ=P^b)pC?Bk}OJG;L35G1`Yc!!w|i_hbloctXX*`wi9Y(v>1*STL3E zKrtE!{R*urom~(+-Zqg`+Qvh7Q}dN6v>arh$t*bmzdsDH(WY%5E~P#?0uR#CdoN*1 zKlQB;tg&gTP22qZI`y4dKB!J<8J`emoAp7?Fs&uqx>E!c0YyL&IER3PcwKe|BC1Ew z=SE9g0$N-qJQPu7S{&A5MIG$k;0v+Vc3^BG6%yZ-TF5|?4vQcJy2A*Yrv8q)lDLdm z`Px8S*H24iMmBR?E6_b|qZO@|e$O-9^{GTfKoL*`6oEMc{gsQW!(16$N2z8}l^0a) ztDBt|4U8vTdZgQEAzNpVh#+axHlk7E;}Sq|hm*kL*~HD5%2Nas0YyL&I6~l{rFW#B z`D_q2-Pq9=O?P4oZXTs+yWm&9X&XV}8D2t6g&rFL4+p52SY67GBrf@HwZv#p?pJ8L zwSkG@Q#*B`PaNOg5MJFvEO2@Xw~8SjS;--+K~DHY*dC*OOE4gVbXp8@zD88 zongD+SVf);fd^^ny_aycX^W@bTS3Gco2GTwTDa3ue?9UP9%a5F1oWG>ujpiHsE>qz zgWbC73&c_o9(!gJRJ2&ndMGz_TU|FEI|veDDNJi^7btN<265`*E^U3kC0>!6jw5WE z`a9Z?#ARgIO(0W$!emBPC@W(dt%Fia7Z_J;N*`cJR)rJ+ML-cy1a=7YSFY_lot?^# z;7Hl6DfJ`XLvSZX1LFyo9(mnlAzNpVh#+axHlk7E;}Sq|hm*kL*~HD5%2Nam5cuwZ z{}R~xP1~1n7C!12v}t>IdM}V*>EJSWP+9_9=PmF*zZ4UwW#wVHgBI%4v)B5)_Z%O8@$Xa95RGYSfh>o8i z0$9yna_0Ue2dA-p39V1U3! z*R+j`4cn-9$ofhCrfpc&JXSUtM_)A_oQ#@$;h{Ed358A)0$2H6!yBKD94pZqmk3L{ zotDMb8%ji*EZmwz@pw}M<5o)O6)!)gP@`REkfc5r*}mTrugFcu5jGM&0*E$*bOgZE zpD@3XiNGeu(@~<8mvN@Xr{sR>4Aa`ww=xw0ML-cy1V#urFw#0}H&R?NH?;nAr?u%8 zc&PN>;_#(Q-|&{Y4F~h)7er;r&*+$qj0YsCTbPT|P`^_sOyC6;x;J_Fh zIHN46IGfPgOh|c8gFr05;)NCpCKrZW+r`Tz6t^}EOWRKCH%TpCC80oz=Q|W`J`670 zL>uF=g5BPXL1Mh6y4OZNLW6dbK@{-mdLR2O@kZ&xZG=q|K(r$n9RYCYGYWhacRu_R z*y8cwCea%F09S)g$^FzB7Hfy@Rp2QQ=>0*hNV}YI{{1Mt)%q+Fz6k%`#YwpKaC1gd z*e+>*?iY$BOLtN65_e%sPIj++A}1wv36p_e#v6qXw>wBs>jFX@Kq7*aV;chi1M}gI z76IE_9NetMzwx!hXP3p2)ugo~sX|YJfV@M=?=8|YmHfts^y;?LitB9N;zAL(Ynz6+ z8ih@a-?&6w+1Vo0XxAA;vAE7+>-sJ6ir9P{VT14`fM^7yBLL?9GS?R&z*Y#eS&lXq zIC+!sMp?{kkws&Y# z5|^CDFXM&k!7#!GYhdwK`c7OP?_j$I;J_i+%n0G1(qfL6+8XKiJHu-+sFWh02q*%I zK!t$E5voQ@W-0PW8cudvrAEa^+U9*Lj2E$?>B1;)u4-)$kxktzBqL?MgA6n+4i|?J zHVEHu%t%Huj=pKUQ5jE}ksHhGIc>BaA}u|{=&xK{rpl_Z zS0%-B)-0;w{Y++ANOad;59WN}(lb~=w~=xkv9MYD_4GtRQaTe@E?P~N8zTCe?yij95Dc1Hpr6>Z5fFhs>93qf^(!#j#U)$i_(=v7GLozx5 zVCqkpj`an?7shmyXz`O4v204kfzWqZOsxr%)`Xzr^CEz|0d?OsgW)wp%6PKV;w@&t zYAQ4sw_}q#&Zd@YwCfC_B9aNSzTXn>&P|Un!p1_lWNY@MJ^(#8EzObOIa`<@T1U|u zpOX8TGhD3EtWKT}feT!Z8k3tVavbEY5qQwE^soxCa+8f+u>Jd>Oeg$J77&+q-T4nlSZd}Y5t z1UzDD%FghEh$n)zl&uTGK(6aE2f>{f4U8w*k`Jo2wuj25;u8{!Wd|8(S{yD8BW#-b zJ6cPmpRhC!ls*7Uo|%zb5{FP5tsl?@#wFW!NlJwj0YyL&Py_}D^j9t}QvI3Yw#;d!~*n z-HE0xKRikTy-_UhvaAD0s*&VEJ_i7-`K1(^wmj}dDKv?eZPo`l!?Y%DbbMX}aL=G( zLO~TmTDnFM`c4Z*0~@TS&V+Fb{gt6qj1rn?*BL}xrTpvrE%B~+7IQ_b3BP1(nwWz5 zJ^(9z9fdq+3lk*oC|cvQ%Yt&VNwGGQQr;6GaDksuOK&L*HV8egkaJDjB_DT`YMfla zKnC$hNcv6N4Hyq|h9kVXDFTXsBA^JIM8HG7srp#j{r~KJJCY;Gv2Bu^OB-IJ(4<}A ziD7LNMyw@-&;ms+0ZR#SL@r^Lf~CFq96yoqkHnx*HQkP}K}7oBPa@%tbf9|6oS{_N z5PEXipIHbtVl*(`z>*gzwH;JWJ-v|FEL+Gx)8KG(8DUfP-@%$R^0JNq*z(Mb?3Or$ z>S*17E--G{Hd|6EqzEViihv?8K%if_Sf+B-80ZJGBd@s`QoZ$eYj0Mkoz8}(NA3?< z2$dN`B1p$!AXEBvpt5fBxVveJYLz9u9fyShS$SX2fPp|xDqwV$jQs;zjt1dtltuPJ zjdqi*wLGOL0*Zhlpa?7xSd8?R`cdGkh#8c(#mrK~F!dDe>8ii9ox($=MaAcs^(kkV z*62q!ABsTPKIY~v^`u)J)al*^I$0R?iS;|QqIGs#`JW;wwCj65!PxfDHm5s_0p_xB zKY(Duz|I1IYzp$d#ggdKZc9s&&)Uy8!`WI2MV~(ufg8M!MtWPXl;1hDJzbDvEbe4E zybP-!x;`?rwKO{0jIgN!2qt7&Eh~Q@T>g1vJ99@KGkQy;OIkc9H`p6xaqSGlm@bNd zBA^H;0#^`l5U#pD_O@HL45jeSoy%w0pIHbtVl*(`Bumb#mf8*~$RHdEiOsSNRR4gc zi3i(HBW#eRI~j^3{iW>*5#4?S0=Vqn)ph3tPP<}h*lenZ<| zLIq7u${)H~R=Nwnw3WE0t5|NbECYx(Hh*b5^(Rcr{zCsevS6Ys5J3NhzAv|7={2*} zK}nnHE#j31qn-eRRfh&K6Jv1kdG&OPq|jyui420ByzTpCmfTFe53s?z2LlK;3=Ay* z*z#*(i+9+zv?TegjaUX*oN%STc9X5OJf*xGfg3!IMtWNTaX{$s3R%o78?g;9cgj@S zH!wKj)L+^LM0idrd`K4<0pEO~)?7@vihv@Z2q*$w1RSVU+sWRxt5g#W3FzW--&OW! z7J`i!4U9L*lJlyiwu1^X2uDIS#o2vf~_997#w%gFEpdz3MC;~qS z0{zOxGG%sPa1_E#4@*K-sQR@RR4R2hxtLZ?$_%0|NXKDds`TqX<^3}rcQ;K@?FSHa zEeyy?4+abbl9K_ww=^xw6)i`LB|e#sEDQxFo2)evQkEj12q*%Izz6{y+K!MR-J*tm z6^cO-*P*Q-qU);>DBDLgR6dB*kmWvY7FVrxz^K;&tLih+?U`uQ#pl)2DUw2)GgI_@ z!A{=x{W4x|rru#L3-<#EHVh0c0LZ2w-&-t+F739oB>AlUj5D0ArBL+wV-YZLpU$mi zFfQ%3UMY>1Ny`3NSg_N*icS|K_1aC2#DO`!cor9p73aK!gfr ze{m!ud_%%ydiab9XiT3Tf%3O{cgD+K-H|fhG+H;xmVaN=;ROxj zS&Z`I4J>(qO1sP;8sN|O-jcn_?>$j>pYeOOtkn-7n7f51|G35H@YDx@?AeCDlaugg z!sIp4miXK$_}Ceyx^6xa0R!jhg0c+7r5*b;GCCVenoB!Fg2k@vGaaa@b>3^hawMhp zVPNc3KS}Uk}@IeSXWu#XR0#`H3YV5j|`mdC#w5tq)*f){2xG;5S>)%^UM5R7g0@Zxg zq3s+W$ zXnQ!|i!09HaBFEQ_7yFj6AP^;o#Cw*R7eph5cs7y`jiLu$~)et%s_+s>BhEO;NdqIE|khlDrE z;^G;mS>1dj0tU|0E5kArmv&pPlt#-WW&bQJ*uiVWfuB0Ztrt$d$u;UbPc<%YyM84o zMu%`l%K)2pLaRgD5rj&ADgxEW^Rba$t))X-el?;0Q{$~uXz-R3{x%4=OHCQha?JXa zGfZns|0i)Y*Avboc$zVHSkV-r_){mIa{`eioiAki=pk7ojawfapq`d z*@)4=c=Ikp+p)V7XEg4-LFR#>?aBIh3%_}2I~F~0nrNSUhEJY!`*8>uxK7=zWgw2b z^~O@frJW(cVpn!(4piRb!SQTi$2jUcPhEZ9cKzC!pAK(?O{ei~NaCvuq~oL|afEcb z!`4bQ6eLe=1Bp={!Z=GesH!2<4ZULr3pA`Ye zm-1(g@Hq6Bwx9Rhd?%6NcB4Z&Xz`B2UdgY~;*};wwJV+V}%dtcFP=usC7k2WfcKMKoL*`fPlqX zRxVFObpU(5jEY-Rs0{4McP z;BaecD)tpE=4hcc%3{kXt!+uGkRnhb@Jo648ISChcf8M-fX4Lc5qR!MubIa7|2l9Z zwgHn4Z8t#jB099)!|9JLWe|R<5SGa}?$#Si5tnv`1dCnSp*c{m+~;7&IO;o3H7;+v zekCYGv0O&jbQ<4=B)-Z(mM((;8|~8_whcujPi+I8Q5G8}&#`QYtI+!*phMdwzUDAd zrWsA+{R0pN86Db2r1VJe3gZ-?5 zM%lMnP$5Qjkh_aXRG04(mtCi4@R9F&_Wjaf7Nl;waUfC4f=~t!iIL<5!8%Zm|QzP%mjQT4*^0O}b44p@ThGs5Rg#SrM2auzcx$*bB@_*xU#~S4H5t2w0eF3J1#6 zmbZKIo`EjFEPRf;Y$F)mSnU7V9W16MM_|k#TAxUV^ zt}+P5OnkkM{W9Jy&qHjg0D>{e=wIQ$`TzR>1n&Crw;*Et|9~wVt{*s)zFT)uxWb3I z3yf=vUV_%Pq*ds>5%_Cz@Rk-AU+;m&zdN=OK%;e!N`LXse^2VSv<(04D6nTsv=qav zZV;6jL=%w|#BQ({Lh%o1=6Dl%@jSxj4m|`Aj)aufF#th!`G|h+K@8z9HG)79Z6K8R z3JmY(S&P-7dh7ptGIxVjifwp-B`;ZNR~ZCTtRtzkG&P^`2I1x7 z4hd@AKtTBP=E;(gtaa@J05C9L?qolr#b_&hNWani#)euOvMQnoC<2OrB2Xh>KtSij zM%2}Uv*SjKJ*tHo+U+mt(1A)Z9M2X@ro#@}28X%#JA`ydn_u~5yii>%BW$Vwf)&X~ zR{zl>JxTyTTrA88;V;C&uA?;rx&wV{xro@7O%+lE6ahux$3eg$)uwQuI9V1)qwb&B*&i^K6F%!O}Sv|5($;ME_y ziQlyFllwFavWH!Tm-*kgt+dMwqSRNBHHV4Y(r?aE6EL_J13>fE|1m(vY zSO@~8wuMg0ARgpx*RO-d?lQur>cE4!hUDO+3Ix>Yk{fL^m8+OYp4t}tQ5KbY|B%-D zY^A;yfyGGAZbie9-VNf5nPnxGFS3cZH}Wd&DuW=#G3sh)yY;ql4<`L%lqJ1+8A)8$ z!O-@SU(TE_X))RgAJT6jr_dklJgBuJtTG>sz$@Nl-Nz-l^@i~d;XUT}F|9@TuQ5#Sp82XtAHQFoPEyULuVcq-Kjv%-?coRo8jy=}nUL&wam)mvYn1 z2%9Q^U?Y*!M=!Cp{oaqfFhs>C;|=;G=&4z zVGAKcsivlsZ}Ap_jTjA#H!MAa3W^MZ0Y@t+5*7sbHRNw?M%YxXL$D=fQP$DTvnzgg zKYhYx9jzPC1;(vV%$Af2DFTXsBA^Hi5Lk@#wm#A{gFws5w==Z0gV0Lyw{-Zw&B(XR zAWD4|)z#28S8&njtTF~A7X7Jl(6s))<3D~~0I=tmQW)CuxDzBv67AtYD)DK~6|CMYY;<65gwljC+-MQ0W+7b%gC<2OrBJhVq zz#!_nX?0h!VXG@z>}M^^lzm$x2C3O%$#mFNUFWH%Hgo|}fojBH}L zMxsZkqZO^1E-=zd&zR7RY;;uw6ahs*5qJcF#Yk_=-bL)>(+)4VF_Rg*Gk}{$e1gr)0ve>(>QNc)0kyd>UZW{;alX%Cn0ikUhV- z(Ka!}JuOL|+BPZ+C?_Kq&M=#Q*wW==5vWF<^g`}X}Pp4o~gBv zQ???Y2q*%IKo0=}V%c`))~=`1(D<3pfyMG^K|s@ra?yxEYPQ(K{4Ix8be+6m8^la_ zijTfu#w%j;b%ae7Krj+X`b*n6p2~f11nhe|2=?;_(N}mo`?z@ho>hO>{xQFgX)OY^ z3%;^HAp#CDHH8D066o{D4cTRJ^W?HnSqPS52GsciOJ1ndc2GM-Dx~KA5Ht-`jw~pY z-a5jjY8`^AeE5`g0D$YcX=u#ICYEa?dW1S!(W>bJBfa#D3C+kxS4BV(Py`f#M-V7S zp3V4m%VeWv`3~NnSyofeEhpcS)N_AnyXE=n(Dpya@|U)Ie%W8>pGV#T><1FE$ThW( zE@z%zGrayXqun)HmNLSE9Ro(uItvlJ!E%bE&^{~_&;W;{yzTmR&^WjeLVq1#qeI(1 zTuOa+1QsK`J^vi(-5|f1SvF!DZr&(UX;&EpF^*AJLtEOMZSG)>vZOaJCyC2C7~0O< zk$2}#e`!l7bfX9;0*b&N5&?s#%eFI5Mz@mUSi(V^{j3E6O)GA%He!&PEjBTK%b|7K z-za60tbgwNWxSM|ZbsNt0R$V7q(j>&oXS)L6ahux$3ws&<)(0;Ol{RAL)^;Z=E-HD zvJfoAgbLL)$)FN_~F>@X5v|Px8_1 zI7}qCL|#1CTJn1KYSqWT?p1WUAjgheW*KbzSFdMU2;>jBrC-L&4HbGDn9ITjQe^;< z*pRvaWK*!zUFtWVJuM4c)PBYpKD`lkLsjBy5x{rmJ5T*VhveMp`esjDcH(f{A7`(NezIG_26#!Fz!u(Y>mpW95_OMVd z@yWSgI>WRkG3lxZ>?82ozUYTZ`k}2p6oL0d0Cm#92Uvgy_Gi**Red8% zGu1j9Sn`}oyUHM_f^@J%z=JfIj5izYcodSshFbjqf|P@(tfTqUCBOWneo2ebR``&P zEG$BvFVvcgDOV9t1QY>9po_q$aM-T&fH*2{a$9Tkjf1T!3!jF*Ep}xEb>y=gdkTsK z%9Mo+<2~t&x31Q*Ad~?_qGTlNVIW%u0^)peWN%ejNQ)M8eC`=$OuA77_7U*EwEgUl z|9tiUHNHPO0(T^U-=n=TAO7f!l<}s~;;+~oiVS{qc7qKVr`XsuIbz8ZO6@yD_=~#Z z5EB1F=?yZ_%<+OgUq;v<{QF5;GLrR>uqyygD&s9Px{YO8P95zXA~juLY%O#s7ZK}N zP|{NoDBH&`v~A+f@p!hWwRC8kyINo)K&I9;12%(|jW+JE?P*zR zA@G!u9zRCOJe4mQ9onWBd^J7ZI={b)lslYk*Q*X~*BGh9ixK$k#r_^~r$gIEP*a@? z2%t_HsNj<*Z^a6IZn4&K6fgTT>9nf8k?K_IY!+STVNNtHe)+K)zVsFEIOlrdO6f z>ecv|-^a8T7`);PFG5iERRl(b!(K7ODj-_?WNTmsFSvf~-Et+CMqhh!Co57^b!h8B zdF~lLp{!d)U>5-$+U_Eya^EikcceBN>9LN^Ab2CQoTvKl=c3A1Gs{xUP<^ryOJ1bZ zzC(#4&I?0Z2i^HH!shXz?Ipj*aZB-C(&9O}C*@<5#lS*s^)pVJCXU)kjpW%s+ zvR;Qk*|z5H(p(6k(aKF7SPs_EYl(4mjytZzf|sqd%M5}o8=m6BVJ-dUc)^}8HnFpo zfqbX&ZAg6pU|_zm(Z(Vpmk{L-v{jyCKXTw zMhN^iVtgXH{?hgnos91@l(Km|*tF(WY9sGj%TcH7&kl52Ro_VI*=D!x4mNn#)52ou zH)jd_EOtZnRh(4CL|F->A4^<=ahV1$8Hd+$r?^GTxKUcq^8vWg%Mz5Q&nwtcQVY z83>5;#gUyG4U&c%(PFgEJ;Ou4%1{Kx2)!|M5+)T;1QY>9 zKoJ-sP&SWwoQYP-3>D7|wz^eAIGR~jVpKodtoOTZchKWKR0}KU@T5PaLkdE!yBJWZ zRfT^t;vg#P2!N9cG&+kR4dGwXVzkf_YosF!q0?D+L#-}XiHd+Cpa>`ea|A|(!_L)8 zE~|iOp*pO-@K3SQT=&S3YOyOTs3Tv0X&a#6IeG3GKB25zML-cy1QdZ?1nv<0Zicqb zCnQO|_TRJ(RZWJqvX1^fv=?1Ja8C4>wri+I?i9+bmhH2#<5Z*!9+r19El{ZnKO zemL-_)T#aKB14S-*@)bFHM}QMX;&EpOaG<0zF)>mx!Goj4Z=qN(S&5Q0AS{hJjXT{ zu#q#{NVGp$NLBbScY$$cj67N+MK_9oBA^H;0+$fLd%B5Ar+Y-Wld)r~(PCvB%|Bq= z?O0DT=Wr_RB7-2EM@5HC+9>+?t8k}y!JaQBvQJw50D_c@qIrzQU~FPYAUK*Wq7h_H zzGo_tXCT3oP~da2bcS?kmDZM$D)8{dpg0MGI=ywe+$CK z{~sDOf4)QG7A_^mSUI)Ejoc;uZRqSiIh|jtNuD0G;dib>{gEv zHdO$@3`l9c2TC7+z*#<`-(c~+6g>%?qYdQeo#B%c-F`Fz{(Uq&(tQgX_wngxm-maE z&HSWgGU2Dh3~%k>;j2-2!1$G$BB#<{X%`tp^LQ`v`>tObh4!CD*hu&YAQ%M6WaE7R zGJm`~b^3s9EPLWqcc6}=z{h6E3uidCOIcHQAB+I%Pg6KJzu1UR-p`xj#u9jgmA|C5 zs(~9WXvxb~+GPgO7D#z+Qu@vDZh0PIbB8v)<+3O&hJAx90>ROIfnP85fL6}2#3$1q zJHzvkm8%FS0*Zhl&_w`!m<5xKsOd@%h>aF|)YK8jdtN~|-1G7e6QAQPBka}-EO|i# zVK}KW2uwDY4x*J`#tZg*v0zinfKUbyi69-a$_+OM6$FB#`C`d_M2pc@_>gXBeq%$e z4OtaY1QY>9KoO`BFd)>0!&-+Dr9;`AD{8I_#77(DsU7?;YV^(aO<2_Y8LtQsO5= z;1zGO=EHJ!ALRKlzmI9HQhdc3Ud5pNiwKm>1}1FndIWJuQj$ zFiE|_r#V+VcS*eeY{Xiht<+Z|P`0gx?k#ugjiHE5yL=%E3oql*-4PlXZ+Ic3*RU7F z3$Dx{7;xb!J-U94aQ9Z1#0;e^c4YvO*pLil%RoS!FKo2)9k#hbMw1#08=4FKoL*`J}m;Hrqx`D7>!}Rfy?S!_Gbq=Eiq294QH_AB`fVJgJ6nx zJzY5RkIFCOP29z^1)o|51cXm-o-7&3s=u@aR=Owxihv^ULnC02eO)+QNypJ(VYv}4 z-oCKVK%wf_UaAkwN3vMTx0|X8%KDbe@#vlv9h#X(@pnx>F0kkG+9V4o^jlPN~+}yvr|b`O@w`e`v{;vwb0;aRI_h_jp0!@gyD}W#fO76lnaBytttyySo)=LQe_at zK{^fx<;pL!1be<%u&HH0K=}0L$$@136Eo`r00Z;IlD$=BAuU>rw!(*WL-QLOYHi4> z$cH0Mm?Fo>ou9Im9}Xt1!{h!(4Zg$7=5 z{nA7Af%!-lOT!Av`j*Qv+knb19h#X(@be13lS*WM?=px?Y26oMhiy031Ptwt|#j`;gMcK zyvP!9@SG#DkiZMD%pmX_1pLzVYlP2@5W1^NR70l4t_&a&8;Mxgimjt z97xtbF|$4ZFfd;%*|}LJX}A$B=2+oFx*3}2FsRkxDM=Af1QY>9V1R?MV{n7&}L>a{Ozy~ZD(jI?->Y`?W3Vdn|8eZ$mnbgX*TV0*DI{DLxY$OZ4+FBXExe8 zv>hPyHnD}xGJ`-|y=yRDZeXgvz+4s{-J13H zkYRy^xeq`#)%O^wF7pyXTUwHQ)-LhMMp70gdztLAwTY0jUWI_g3vJZgZpG33@tI#m zt!}{&6FFt)EW*>(@eYe0t;APx|4WO(h~-OD+S}4^j(6%(m?Lbe0D?G3#|i*3Jzc*F z*C2d3o~{zDT)xja!(wgfTAA;T0AJbf?&+xxetD|3cQIz;o65VGR-=kQL;x=_lrl?H za8>7Slbm+bXc@|s{h0$D#vvwDFb4}Pd2XqlD(~t06<&hZ4Z?S@2~CSb`93rc`Gw6b&DYQRpBl-lC#)br)7Xu$pQPR{bJ@8e=n z&)+u!W%Fp6ELtgagCuu1jh3MpdPQ`Z4s;lYm<4sdEV@qlwqrEH>!$BFJEY*uH!#Rr zW%%d2(gt>9ts7Ja{uRIZ?(`Kc3s0P2kFvOUhG|wepBRCBvAkc9`Ge^D`RH4=ee%0g zAM^W|)+(7-oZ(dr%D;%fsBm1mlvo9-;>J;{MO6LTyA^US3YC*8gJ2A#=Khc*#dxtJYWU}3t5Uk+_AX))U8p5bZ4%6u6DW!uW`5;u6ZUMaaJmD@tO zB=$SB^6tpiTf-@mQu`<~2*Bm`Pqg3yn#_`$pf!BJTo&#J5cDmKEC9%+Am3YDCZ_PW zv?TegUE-6Cq%2JKGTCKo6Cq{23IU53nvD8*1?kY1r(lGQ{?e8Z=|&My1QY>9V2VK5 zJX*@4l|na2a(B~c8H$ztnFAfhA!b3HFN>~Iy7Op+Ed#n+2h;FtamaxtkGq?yBj#;t z18I6Y4k5{^Lt9{^iz1*1C;~q=0%hGhSUB=Moeg|yEk~WIQ1xpsrDvO5_WKpooRpDN zbAL#ZV!S7v@m4HTs~6csXF3k3~hUE8X7Zl4QoPZqJ8ce zo_JQ4BA^H;0*b&0fvWD+Woo2W(rYb8cJZCHBbLzXzHG6*(6YVHro$1}z| zb4Z@Sj#~W^9;6&ZW!0fA0MX@#M!@A(`P1T{zqI|dr{;SJ>@6iC140hx?pG3Qv=%c< zF;1}!XE(}J+EoTY3?#qPp{;=Nq%$1g)yKypP`0h?E_G;|PYrtF1{({JQv=YFpk*M- zMjOYI#bw?Ft@Q(i|l2xJH;}QQr3$Q(4p-bXdT+>(02VQQ3*vr5l{qX2%!6_ z?)UOmY`%LtF=EN98p66ia}X@WvO4W_Hn|ZkwU07`sL7TR-K~Q?Xj&ZVFKs;#7tb)E z(~TnVJOu3XOkK3J_4>bPQ^gg59s>Q!b^aoLPphJhiW}d`EfmVTU#>DUJhzZNTKYXZVD&ZWRGVKoL*`b`ijQ^GPGUJKS;_djp|AJf#?Sq&XxNj1b(v7kvUTP`Zsa=MQ-#6VYb#u(z^dy?zlgo1H%5?pN0;Z)k^45F1h zDyqLQ6gAz#Rl^=(V<5@0cpQmj!3awqfRn&zE9KJj-AJZK$GtmC-WeZ9D(_XDDC4ai zvy}641bq8tywlJy`IDP^yYO=H&8_px)}zs~@s%20J-$J+ehH0Rp!rtoWIS}RxBxwG z@%UHZyYPh2M7zu&2psWQ#h^m(jKB@{|B}}K7nYm<-}!5J`_X9qJ*d9<|L%BWw_U^ac}>(E@;lL$IUYU#_Y`lIoa{!}AbbfRSO94Wz{DF_v0}#~fsL%$CPf(qO1sP;8eltTV6XJ+K;2wM*jVV( zTW-#Ub>Jg`Z&=d`e`v~+a*CExxZdqcv zF%V~Us0vlT_ELT3ESH|jNtHpc!8+o?k$+Tv>5zg+tp995rj`K#S)PqZ;BT{%$Fg6tHC6PXsG-_?n&37G+Hp~HNmnl zg6pYjo!1`ny&f-HX_pxUTP8fkhs9d@&GCXgUrb_Wt$qMO$|X^M`O2dYfN-blpUCCg z5Gmu00gKutK1~*5OJ@$Por${tAOsvv$7rONUw)GSZ{(HpR8QU++8V0QHt#XCbu)+L zjj(x35&~g30*UJY0GBiu&-KvulGaU(OL(I!E}mgAtLtY*;1zGO`ThUZNSIeUgulo9 zKBl!w@fBxy6@&6GB2YGuj@nl)rAEurOxd3uc!^YfBc*2>So+^Z+Z|1?r8KZu`gNdg zE>%Z73Lsds;pso;hQ1F#5L-Ur*UMeGvYKe0dxn=$tAHY)2q*%IK#M?C_nI=*YIG=# z7OO+`*8h~!V-P`ELG39nb_x!}$}i(R>5R7)ENU4L$^ar!5|?#w^9%;&izOT3^LVxq zEk^s?Gdy#xJVihePy`f#0RrYQkuwR1LzF)?hKRiZ@gQo#DM-@QOj->xNj&EYB55S(^dT6_+g=jfueaac8 zHOWiYk3}F|4Y+t^#_B`bdyS;n*^`PEjCyXrLxXXb)VH2(ma4SN41$=Uti=x3F*I|$ z6r62LVrH#=071$nQGfZ$qYr>^rz;!ngKtAq`NTAkp>~N+lf{NfFG6d3;wts72soUM z(MWI0`HfN!4Q;7C-Mq)pcIuGK5jJm0LLdxBAaNZGZE1SCsfV^xVKVDzCA^w0KUk*X zY;&72m8S?O0*ZhlutK109v#JVD@D?9(`Z?Wmi?J@T2Dgx0b)s*LCfHIMSVT(! zzYf&RrRs=BeSffKVN%xSXGd3B&79E#S`Lx;Km3z+qbw*l+qfB1d5VA{pa>`eD+H># zSC=Wf(vSRFONuIQYdM(d*Iug6oaNGEAXZjTds1en;6SYW(jf&;%FWh-LM;PA89*dT zS(H`o&^f3ekV}49u`g*cT4-5BK)Oi;p@ThGs5Rg#SrJeK6ahtGhJZOtWRC`uGhOn2 zm7P0W+FK5(+D?VZ zyg0O_-gKiw+bKM+XX0uw$#ZVQQcr5P0;;wAt5+WV4z0X9vekf{A}O`SnGu%<-igAo z1raWw$#}VeSbs5zoQ3-V1Syw9B_@B=1t6P(e0O1^jhjk)S_ZbL{fsl5KlOAYRpM(A za5%Z6k>1uT<;IvF8roW_&o=KewB<{C=6Qt8TT&7T!x2baM?>2ye)FG4zM^$Y!TC3m z=bm9PtE(cQ2q*%Izy$=#=Fw4etI9&U(XupC_Gi**!FU#<{CERP`b*m}M3GbV?>e+y z;PqXyak0E>ZsuLB&y2en^BsAQ`F%`lmBuU1@G1u7Uqqm)d%QPfk{!EcuGW&GszX~H z+HSpoR7ep}1Qdbq907BfnBizJxt0E}BIOPjx8H>D^r7uBfdl-XU0T@$w0GdDIfOKovxvOwNi5X<{+ zjF+3N+u4~!%fkHtf|N_55|cmb0+3BXzPsdUPYQoe%fJ@3pK*reQxA=H16JaT5O6pT zqrv1>7&l5iG_(;0*UKrXe*|tEBxl6?NnNrb+i&*P1j%A z3Szn{0*Zhl@csyt&7-5ky?!i-H(Hiv%Kl6`t*URN^lSr5I<%dEXKoL*`6oD=R2DM9vwq1B4 zafD4ZH4d_oq(j>=mdbe!0%iNi?h-dP?3R;SYc;d1?wV{hV5dmXD>}qhW)O%59Q~zj z0HVaFK3A4lO*hi~Plc5EDg+!H;oRo4ldh$Fl4k+cT4L1efCW1iR&b%F>raT_4VF_R zh4$f~fDFP>-uC@6UT$EczYMUc-h85N^^W3cT>!TH8b)K&Zc9s&r?yMVLeEC7oMBpn zFo~{PhYAB#KO7{PGkih!F zmnPcV$}i)Mc2-YAY{~$l8Odk?z{+LhJHAm}`CBj&t^8dae}3aziO`w5z_=9)t!+uG zkRnhb;D@%K{qdjA9-zkeM@PUS0hBVdc%F!Q_0vv*jTXy9KoQtNpkKLIrnYQYN|iOmlgqbw2f;>+2F4qfo})z*)anNiq$DO;kE0I&EY6o3*$AJ4l zz`Y_6yrf^@s`Bwsug1sxKBiTrTpzlcpvQjz1p1YWWojz}OR2J^cyjp`?;zNS(ZG0< zi$bMcW)Ka4q(j?)Mv0G&0EMS3Zbg+`wh{PkTk_)sb!hu>*#97&7b88p1w%au zbgXv$ndMuuDq^{gPQ1O#(3YP-CytLBn4>H?B0jc3x$hWuE#~2<9+xt3%uL{&nd$vwWkvq;`eioi7lEX2#U(-YA>f<8Bz#}d$DnQ%}M&OZ*HWq~s&a#>zID@x(ZG1a(j(JG1KBczNCZiTwgHV29~%J*PdEuYo^9-m zsXRqM5l{paffWLak={x@@i`!@rm>?Rnl@q^Zr){RyWv-VX&XS|8Qwxnh29$h2M6ew z*j>t361V)J1Dz}l^_>u~uv>P0o|qfLwPy}NMT`BcgL2ikm3`ydftL_Vep_l=PYDlX z5Vkfv#Yf+7j#uQS>j;~w{|+`JaakF570A?|Fqx4N%FbFxYoS!r1;!nlG6&d_RUt({ z5l{pafd+woYt@+AdG;4H6t&Rx{@Zerdb(83b;W(m#(( zD0CAMaKHf_6T8dv4W1=bwU!w5iv13)Y@L_(g8=XG@ZM83AU*Ybd0X8yg5MnPmg^BV zRRFr#(Vz}?}Z%r}v=hmG6v?=zoC z$5)XxhlyJq+6p4NDgugtBJcwuV3Bjvw4${GeU1zoLoZY|gn86j^=+kCR-d?WnOACC zFiw#QiT6qkWS~ihSr7u9V1U4PH?$4K zhGWz_vVO_GY3r++LuHe7^i$)($tcM;9_rARQ0OKi@TYXI;b#|*EIZMkY$R+wHChI* zUf&{`XyMBdDGqmRVBB1p4F8j%RN7?*QR;6Z+xMH}6}jm;!bZYJ0KtZkRsc->3G?5w z5!mE-x=OVC;$n$U&i&FErnRYWWhw%SfFhs>j1aJ3#5!wEQmmLKT7TPUou&m2D*d}S zyy?<6e5Rhm!M?ir!cIYa2KAm_6Bt(>BW$Vwg2_Z$1F+%#bj!$Wh*JbOFa`_GC<`ji zHncVqQr>G22<=yRq4|c%`X%*t;pO6+TjQ6lN2B%Ms1{x&zCjD;+c$2`FVE+y5jIr-!H#6K0$}Mg2>dHNIsd=F7LJz> ziT1!3xGH>d?w8K6SX;VRfma~V`vo0-ucmMxe*!b5TF3v#mk6V1c z_6NnHrF&4kg(v@rPMTXjffJLu`OUyD;|;>g#~l*Xx`9vz5Q!kA*v0_Bz^c&u!cOQ*bsI%!23PpJQ*~BGOBmWTN zKiNp#c`{k3(k?RyVxi9B(e<0-6|wm`!Uo|>0Ko`ID*)#H64zxRz?KQKU5Yj|IO!qb zjk1{8B9GQc(apypaD(f*a7dZjiVPLIDQ?GchyGvF+ONG^KEzVvb^5dI}C=6EZuk^a~j-itw{6ahs*5l{pQ1RRdg zH5xK=lSk5U(`e-$6(4D<`>imZ#fGLcBj33ywH-uGeXo!XY4a^)plNWpxs0$u`0ivz zGLp6aU4=c#F1O6+5iKL;9X6vZL~gp8DOZ__fFhs>C;|%v`jv}iDp!q(9Y&# z#4?cR)?NqZd|~MsRM2yzNa{EYY?giCk;9KA{& zoKr7XX_pxUMI_^QeZM*0#!Zhf!p1;2XM41yJ^(#8HO-RXxZBtuT1(LqpPc)ZGn}o_ ztZqIIfg4GX4VLs$A`9;{PKHdm$Z0J zZb)R5#kDgGW4e551neuK%kTfM@OJjG^@ed)c+&nczmI7xLbeOOvOggL4lz}2r~e}2 zgDPg}xim$!%97rW!@{JjqoM7VXZZE92>*(fqi~5&reEo}vlh+j zMiEd16ahtGAA!Y4&um%xDpCgJZ85VHF^o93Y6*t6zk~{!qAF*mmX+?p(3T$_C4t^5 zmYXcg0HSIjS)b1WfIYvI!qAq-y(ony(Q?fClrv0g;zrkxMF7_fIwmw!KBTSJ2tseP zVAQk0s`^YAH_+c%a>pp4iFTPmu$9}tzTX`0j%P8KwW{!Qwnr6{H{SO&Dw1QY>9;35JJ@>SQz)^5w3p;XxrdUDyHSqL^_G%()4k{2ko9aK&|y^z=} zTgX7u;Ba#pVN>WK^%U*ts=u_I!b7G-#pjsyDQB40=tnmnia^;u=H@N+q+1=->D~r9Ss3++ z^*gkpb#`0%pCT!=>w7-I*!Ivir#p)Q=CW``eR}gRzuDU+=fp8HyzRrR@n3-F^fDxa{85 zb^ajwu5LQUO^5ah(qn!f(^}>8iZi^5LHQRE=vOY5sa!TEb{%=uICC_!EXA@q?Q}M| zn3md7LC=vQspkF=G_ykrb{vw_6xDtJLEb`1))4?#{CbnPvaV=3M8XbZl*Ji0>eQQT zt>);lBA^H;0*b%}0#6y~eHBOMFmd~SL)%|M1x-%MAG%srx(mOwmAI#?SZ=Z`1Bf;@ ze`!1QCrr!!LjOFnV4^D!K>vllFSlXoHM7-0Nt@~|;*|!Yo&bYYhXyedV{q|#^>m7) z&}IjT41%4!?fYex+)TX>u)(_r0|+(@3@rfI@@rv>ci6VHB>Ak3SO!^~aHYR?ldZKp zrMw)08$6CidRqZ;KC<0vs9H>>>$={mR8MWp-e26v9mpOF~ts`n4BSDs?xx zm{v~845BVb$6;Wq^y@(7{WBhSH%(FP2M}~E49H3k1`Gs}lL5WAG%d>&Ek}zbKADaz z3uV5jbW^sEXsA3lHDtL@ zqe5p>YaKA^MZv22OmurD+H&!E^>m7)(B{k(Jzubsw|&2imz$|~n9IWb0D=tzLkj@1 zDaiL0OQK7=EiFktYd_-*XKN`Geg0Sk4BV%4YZ;77yRBDBqh*q^e-;+(bg!b*1xdYj zlOu6pjxV0YMPtP}H$v#I18n4rCFZ16#WVoGo;1eW`psugOWrc6ZQx;$MaFd;$@z_N zCZ)U=A%O49N!wR{BXKW^TFdbzQ?=muqb6U{n8Y1!&wh~lm7?kX8Up{Rz|Xg1YjzU?f^J@S$spZzV#n&y{$aue3H7Q?4S=L%{K+ z+~a-@njhNgLlJmS1iDSDcWB`>cbk(a&=_VdUR$O#gCcA}g&0dS$lb+|YO#ZMl|f+U zrW@f`ei^TUsp;atrIrPu3?LFEaaj)o*)kBJg4tgj$q3(&Fxfcp7;S|Q=@x?5&M=g8 zQ3MnLML-d_f`El^Q#iKXgP}YsZpYyufwy>r!?N^%IA2_5m)aH#*0)^qh4Hj5m$ejk4w67j<|+!*~{>{CERPUZB!0Gl&NG^S!rZukw3O z)ZJ(NUM*|&0|@4B;mJR4@i{#80U&#};qT-m{FyL$O|&IGcM3jshN-Tbk3_)0dAgu1 zLvd-xK8=jd#**gJ&X8cSEBj0bYHFSL8n7HmseKq2JJqATV>&-Sizi|52b>q%#L zD+U!(1PTOxDULqnfxYsM_bD^bpgubSi;*7RvuAnS$*jhiqnTwX=BPf~yvxv*^=#(3 z8H1MLAAm5JxWSIBBLJ@W^(_nD2d-${5y>Ipjk36ShG|weABlj0^YqHF48^70)+?pa zGD+D#3k!De8gbyK&T;F7lW%g3`p#30%iFGB35wAnoY6ACrk&90&~^l&(w~YzHS&CH zq*rU{(3W3K=>ODs>l7Ni<%GWt!tGL1hO->AKIIJ4+S0!YC<2OrBA^Jg2y~lPFJ_ad zOUvRJH%Y0LYlDF%npV^x3o1$o)j{qqhE$6kw5tpPGdJCRzjT-dVY9b55UFKBC`ee^>-8B5w*uzNfR!E!U2+xarXLa6k{0+N{CM5>mO3N3?iO zEDS#B4CnB4rwAwlihv@pjlg1PyJhE2scM`#nprktG%()0%g}c0?!+05J8zJAU}$@? zKHkD_9@>sYPn;&&=bqt{C*6J=0tT*AcWW7l<8HmN6me;1NU+$I9hw7`_jqtTTi7v< z`p#2VpSNAVcIKzU8)4IFd>fMZDg)^_X-OO*o$j!;QVj*kQ`iHZe}I4QFC0hX(B`gJ6pHP>;S}#=GISxfebPAlj0QWIYUAl!09G z%c1QhE#_F^L%Q8E2O(-*QBqk&KoL*`6agS$v6hv~6Hy(&o-d=~))XoOJHM;+NND}9 zTLljmZkjLk!*7n4g0syCn<{`{LhjqhdN>$HwK6!|TAGS|MTS((ki3~ zlnDG%9)89nd*vPPGbW%heR>3*JJM^WvHiae+=y+!q(j>cki3WvZTE2cV@nx?pDKi9 zGLF0T#!|$kogu+uS9WL))GPNn*fEa!&Qp!c+pb>;3Q;VV5jLI1w;_qIGLWUqAizfZ zbcbz25y?~AKxdT2hRJg*TjDD8z6j{hc8RY!Oq6Lx(|G>?gh57!wh<|PQUnwMML-cK z5x@;X2P#@T-ij4^sZ<};S_k`C1JSZ?v!FtZ>L7O)L#oBD>^dF!7lyW5w@1Y?!?bW! z1`vsoxU8ttye*H$^^#vUsF$=D?Q_pCQrAThcq#&XxjxnEhB3DxqaupHGZ3&a(i9Gq z$1NYZ3Y0}vhqi|UfOs=8TX;gKsn}b}^_jG#wdP!H8O>T-;wq#FC<2OrB2XfrL)#LM z&QUW4t!B>pOWO`;N_tNO?2)>+Kbz>~zx4H|3vE%O^=~obFnRpRMvB3$Dj5ISiQIa1 z`6FwoU1bm~S$3Cwzd7EuUoSDj2H{Hp!IosS0$|JUKSfGlljG@%Xurt!KP9|T7E@!w zq%|Svst70oihv?;4FObD7q$4k8eg*Z%`{rMG7jb+Vw`1h=}a_&pzNVtWDxi!JmFE^ zBeRiuidV#@tE;sv#LEC8F_D%4z`%4t=t1U6#12LoLxIo9l7-;bLTg*nD)g=hg!U`E z(0tz+PVT>>Gyif4&F$#~&tqt`{uSh%|35Tn;e7iB&G;p>S|{VagSDQz^|0}B2q8&m z(5^BF#!P&@kNq;?9&wo$qx3moZ?I^HkOSBZj ztZopM8AKD26vS?@7(($6Xy$kmdGS2L<_-JYv@|uJ@dn}L z;|>XG-9SM2^ybNuk*sy?0{}2EU+!c-qQz({d`Q31{Kke_8?q{*2q*%IfFe*MU_e0U z#75NBg0tgBi#@7^8rtnI>Ck~nF&xhpOQypP+6ITY_dA4iNSj~zWxP;bEF)~H0D=|C zNLK&RBRxt0KwK=$2;ncp!LFk<1G)o!Yq^NnmQ58>1QY>9;KxD0A=RdEpgOQ>%pfsj zHZ`Su>$ear#j-l>bT%wKg9>_z)KMKp!h!(5M)*!P({+SRRl0R$UDS^+TiC(JMG zFA%;krmIAIIEa<_5?05GnK2DNS@jj{81K_djF8t z`fR1X7JR=C?J9#H#xd$@XuI{caStZ_W0WPmc^OGu z*1^#Bl3&i8FKIE_3LnyMA*awE>^!KoBdjtXjle73WZlOlx%Gze4&goK_c5(S_^&v_ zix8B36#)Zgi3A_0N63jF)oL z%?O(+fM6q%{wEJ_4-3m>ARsOlW_0Pws-rdVQq$eSd%?blSfQ&2ihv@Z2q*#$5Hy7Y z)nN-EL#d{wlyC7Cf{hprj5jPjg9?faf&oV>C=wO~_%-BjZAREstwXRSWl`4A&9f_h zcRzi?W*w~?&;`b=P|TK;3Mm4LfFhs>3=mk1^tL|IG=o6P%C|GLwS&+~^0##Ozs<zvDlCT>!A>mr@wo^0*TuNfPbhKq~QR&K0ww zh0ey&T8F8m*CSxzGPRE`2e9=TN#c!`r5R!2Wo*EJ@vWB(RCpnb`p%R=l+N3(Uk8)B z%Lp5UZ%=j_k^{2}Wf-+EoTYjAPW*(3Uo5n>(1JEa}b5N#e2&hPE?zn%#?jwBL=D2V###aRbA()r#F=C`(?b8n{GzfQ~?AVlDMpg zh2=635ElzGy40Z7(HeNE>2Be@U|&S6(A5J)KoL*`6afban!a^3@u=L2Z5hch$_7tg*nlJUkuYt;u1%=XEN7z&W1XU@EvJP&Zxt^Pb#*A!Y zxkjQ#sG}9Fnl3QXOV60ljBIpO1QY>9KoNKZfyGE~%VaYMT+J-2sppoHZiq=_(;0=~jB!xCE6#il$sHbGYuItwYPI$QZynGs9)BdcsY09&UB9J}5 zxzRQ;#62xZp4v7l3n(We7tS!7f7sIHV-cuEp7mhzbdo1=)>@oh4rZ1&*urS@bU}`t zypdIDR~ZB`j!{=bTfVeuytBE3Hp-ITyqpYcWgP%;$uECtdr6DYR``&9OKG{ZES{;g zkW;oIpa>`eia-wm17g{B=GLyK)6n>t&w<7AX+c2KigMA2L29d^K-$MTo9dw$tp=$}X40_+D8vdA^H zk1l7PUNgM@GNau!T9z`xf*k`!(K-teyuoscq|iPr6wm;NqrC0XN>D?f|m{~Sr8*bhxQ)yQj1Tl_LS3_IcoNex4jv+ZPJd}jD0HI;C<2PW9})qBsLQr9Pe!+r;#k5#oc*i?0Zl7zuQp9;KxJ2A?2oUpiFJmB}3fG;^xU^ zp|TJx#e@pxV1XsiEwvrwkwG{T(sF1k;ladU8DUek4nZ3vt|I_)G6SE1%#19Au4ozP z5R6e47tgSm)m0Ht1QY>9-~s|Vv|WOwLt9_5-4Z4hcp(B7zEb1qvgg#0p|i^5-mcNI zloD3ep`qJL{h6WkY;%gF&^|1*&^m{syzTmR&^WjeLVq1#qeI(1TuS|35O7GOdlj87 z$Z@`6!AlrO^{-yfv=GQ2a!bGR0rd0bN7Re)HMW zve2hCKD&aRjhHCt;`8!})|Qeg@ZBIFZRX)(O4ZjLx6=GdsY)B)`ootcqtrh{w(r+& zy-$b@UsK}?KWp^^2=WG3wBf6~`V0a9XnVH#RhXALREhSmP%rUmvJfZJ)zaEjOqq&6 z7lGfp)XzoqLtA|)0)Ko2EK)!Xs`^G&rdgus^t?!=jml|G$}FZ9#L{mb`edUg?RslK zK>IriAV@ig$~u}qUGmFM>X)<_ZG{i%fYBo4`9iI^m~s^XML-cy1U?c0yji1MScI}w zWg%;@=G#qW1$E@J8hT3KFN^U>XS{V_QOkl*1`vsok*tS-Y#9iM^Tm<9Rb?S9T8y^e zn`9X2WwxQUnUL}nfdK;km$sk%@t@BgpvI>NY$1Rjo!uaeU$mWn?6xxFP_DdOseOkg ze^GZFLgHU2y+H<=Z#djsU^#2`0|?e6BUuj#y8>X#Gc&qvi9@K4_CBBsj9a#I?pxw2 z^nD=UkOq1!gTr(wZZ%+H!E2V5__IHFpe|T#6`rk_j}MG1!uku znAEDmKN)clm31_T;F%10rBQF6WPWH9qF| zF|7r<`R#BasO%pO0leVKdn3n{yBvm?S?v0iJ23N2m%iVvss%6kYfsd&V3h$xqGTlN zVIW%u0^)peWM8?mM2pdmS_4b-8yi~NkW~>yphiH4wlyMptO&dl0@cj2oO+rar!xKY zvZeMN+8l9S7}`4M&X;-&ItU;bkzuW@gQ2aPI|P>*-4elpK40o+?+~x)lEqdXeVhAK z?)Qm+Lt1!^7#ya~aqER67QAMutwURYiN#`Nn_hk}$)6ug6m$?@EVQV3h+fjtp{>BCt0JHXC;~qk0u~9Q)2eQ5;vVZ9lzcC>(yrR>V1-S$h0W5h z4s8Q0fYAV=`LcD2<|dS@2q*%IfFkhT2;j}Syf>ml+bQgh+}vo8G~9?58;*W&qQA5q zBB%^SKoL*`{;&v4hqhZ;z01&c%kwcBcVaSoKUtAst*nEg?MY*@t%tS~(G#nV_6}Z6 zm!a)Rb-aBWvy}7wBH)l(b@%APeGakU4H+2gH{PCUA<%p&(If`iMoKLw>C$f=+JZe_4A^LYIqr0z(_3!I zg*E!6Ei~tgA^S>$Dq4)T!iV(SEYr_;L#?rhaufkYKoL*`J{keMS(o=lbZ9$0EsosW zXpl7Ah!$Ibes6NVYd5r&8MKy3x>E$U5zt@SZbPMlioowfK!>&ozuOfUb!dA9EtP#f z0uClecSqJ9#e$bKknT6$o@pVF?+}%KFWrlwxvXVizYHJ}8`7vnWr*WVz7KV!MYS+U z?ec?3o5eVQ6NlDLG~IsZ29;Nuan2mzf|)iQy z`x}k0rR@97Lt6^Yd>b$sWd=dm+ zH?(y=<2$qN`+XySYcu+dYV}LoP}SrYwzBFkZMP6sq0foHpHipxvy0(be9!;SWsnri4nv#tEDTWO`2$X>cce*+@rhsiKEli2_ zCksl2Pm_fxPFGr+N-0wjPy`eKMc{)Gu<+j>0Br=9%5@UN-a!pj$>5MPmvC%BEd1gC zto34|$VsaoK#+1#G!K{Rdsr23a2^Y`#nYCC^XghynhZ6XD+zTaCA6TPsXKVbP5q@q?ofWUqWPyP|td)URW zn?M3*`G|glrTbF!Byf&4kR{JE{hY-~b-cZeS<3m25eNk;JbX0@kDpy!LS@)}B>gB| zY5PhL9=P)owz!i0uItwZnG26(*=CJ?0D+H;OqTu0#(fn?=8t!$SuJ22%bqyZ9jN0d z@UdAES!BXw7uptm{9p*&knis;J<&|Rf=ZnWBB+MPaf=Fd$&>m6=4yfEtkn-7n7PB2 ztn2}9U;qFd&6k|f16ny+fHBHq9s{`9+LpKqDFTXsBA^I-1Og6D(GeRQ=2jMj$?}Cf zgB`TdyIJym2QGVuP38C0Zj0n(wct_9fKUbyiIS15a>LC*W&a~VXt(9@h!&%*@FCrZ z^_`VkJHjfX2q*%IfFkfQ2;j{c71JRI6cN_OS!|X}hh0@cS>KMsP`2-v4znONIvZG~ zmV-JVihePy`f#k3}GT)54b? z8{$YL-j3~h0dom4wpSk8mXegHx94s}^aL)$BUy-C1! zMJq?U7~0~ZM&N@bTN?-{`G-Tmd|1ZrgFHXx_c5(iidsfj2>q~pdBNc&VgN*Ld)LUI zDEx99m3Gy32TLI3X1VgaRkawB#g1AAgihNVNY+1rHT$={U}U^lvaVcNqQz({d`LGm zzpmzpsa7X9FOiWeZK~!kEL)9ii|-;YY;#%5{I_`=T{cW?$FlG9fJE!q-+XwPfMabOj57# zVeXOzvl4H;)rhqoQ)%BV0%eD0k>}P+2C}>m(regLpVNjbi6{QjZs6~A6qe`&h~m%PNX6`X%POsHNvqKJf7+z6q& zxa=B>)E0`NE6<+a)bVD_Wy0=w%iRt<8j#rwAwl zihv^Uu?ReEXzP5{dfqQ>_dpqqJ27*1hoha%U)oZBy7?wt%bG2e$tuwvCJ9M+LPyyr zj1yCtWyD%0>Fx(WpzP2rGEOg{y#_4za;3HoZOfOB!=be66+VX2HtjO52@Gie);L{q%+=Hu&8A~C?%T+ESlBB85Gt61g&6^$ zOInQ9!1^c)_7H<8BAM1^LdsJF6ahs*5%^dHbZDD?c6Vv~`c2N+B`q1w9ww>l&{km7 z^)dowhi0Ll`m?yAtk>r0tV)b7q47@`GTATAr`y{E^`a%=1P%o7kIvbOzD@`12+)sFZg7ch5G>n zWeW?4$sa+>fRO^praS(xl)vdh*cLdyEi5U3ir^550i%GKqP zTxv@LdHUljmM_h|-~11JY`K;%QsUANvz@rD8vkGmq~ljHTz9C45zc!3DkA2JmP9L; zZ-r0J9a)Hz>3Zq!22Cv~^G8JBm(QQH<>mePW7P;1fiVL8v5!d#Zmf6WEV@o zo4#L5v)L#~?FMB&YjxY+sAr%p>uCOT#qV)ASiPcUp~J6zjIsbk6z^`bwJuwUihv@Z z2q*%d0Rf93P%f$(xD_Fag_o_gtI`*Y@sq6$NB&XzO&?4XXXDvGW>La}l!K_Oqnl?C zn=gj!ttty?(PFd}KBR9|SqXt!LeNza*hj!!c?IvAeX6AYH*NKy2z&_&e;^f=xq+xMG){zt*d#-Y+s>ki>EfJl^#WIb+>Edv2@zKGxBz;6WS;^2xF zqXifZ{k~-mLbP^8NoD`&2pA-QE1d9_3506?`Jw@PE2%tZ6@K^SYb}NcS*C~y2w8iVD?>9T7 z;4FlyBj#;t1ErG@A<0_b!FH_*D4hj<^WEu_qmDR8O|;Nz=r{@VGB%l8|Cx;Pek=rV zZGAw}_5*wdmyh{i2bC`V~zl!K3EgjklY`Q7}ihv^UqalDU(;@G&Z?s!zEV@ojc7623Lnyu#n4c}pjJWE14Td)Py`f#PldpAXuB2Z zjZ$~)%9*J<)q^+6_WfQPL5gK+^#h1LWmqfgU}($uW*hO#q3ukVJkesb0HdMbsj{)5 zwGCMn`EC#}$OP9`bB|}8s95llm3Gwtdx6~kiB{>CJ+znIc)(oN>IV=kS(wXR?WjeC z;AC-`cX~_8#K8{HX6+K6CX0cYlANuTbUpf>5zwKn4sE~Z*SF?2N8pz^`!jIumD2bb z0@fH5fi417-&XaFU6q=+>N?T4Mm1hHeZRK0JwL8G;%5wP=MKSTMs7>I)UwnmKOSUy zZk8!J++?kxh%yubML-cy1U?!8ivY@dBkoFAEIo3&Nwhnan{~v(L+STmG2RNmK#E%Z z5+0-+L}eY_JcHPLF=XdPgQVd`v>0uL59!EaXsBRNtDx$EBCv&k{?c{}CKXZyo`67q zc*@b{hKCzv?%3(jmXMq_&2aWDF&p~*q_o`X&~^#Y_b6bH6nd@Z9?v>wvEU^u?WzIx z0=fMYtK8aN{fnUvv!G3lSTG2*=1`JA!U7M z29;PW9+^=)O}Xt&~Bb)ES>GyfS^Hp>nk;5R$m>OHHD_!&dn zD}M9c=_^`Ij-xEjxB;ei$<|t)QWSyTjez~#79KUQ_44KoL*`6oGd}K!>&o;79&-TK%Q%JHI&9 z`~U%)h9AeDO%(W&x>P6Q*MU|+{x^>*?VoJqm?Ph^`j^P|{T_c4{?;m%snri4*piGK zyY!!3^ic&8X{#s0#uTuv6e3@u{gd>-6+U$qTSgCB+Y?tQML-cy1QdafL129wX%QFe zmzTrdKm}DP-?PefSMIwwh(=900ByZQ%V({A0Kt$6Plt`q>8ZRM=1!c&R?4LpyP(y4 zgN)O#Q5K6Z65DP`snGX?Kxo{;tJk+$;kD=+N9UK&IO6s1j~0)A1-=VUm9}pnji-jj zRhr6w1~KdZ@B4Mp>FJ^f;^PM_XRUq!!GL6BL$dJ`fbUSP-&TPH?(*^9C=o0Hwxvc8 zkZ8U4^fp%F(`2z_)Y00OxC(tA2=u@4|Mv^Y-J|SZ{IkQw3GG{C@So-iN0Ai8`hMeW zp(qrjmyh7oKd3bbAjn8YaeecId!YJ98Azh7o}=GjDHz&*oTCj&H)x*efhJjiJzuWe zNSj+y?jH$(pIwZ$x-o-WJ3EOa{UrHk6IW=5N)R4D*|_*8ZenE))Y9*Eoeir0pS^2I zlHE48w5;c_Uw9xp-U1K`4>as0V4#7AUP3JeLk+zIEv1(B@Hu&s009teb>FI6om8lR z%730FE3=r*zVRrQcUt`bk|<&-5ha4$%V_|}tdo~iXUies%lqjH9OTYa>`?aj9J81j z6DF+*!PeJD03X(OWcu#Xll5zDDH^%H75hTs+@$e)D`Km!u&i4B0FpT=i?Xr@XaHDp z&5Z6#;t*=16);-5)c+;hw2{?5UVSw-zl?>1P~j)bV$LS@?q;ip_T)o4j>byEXtaP zU6B)@fE4Z)8Kj5HJJ`fhRzq{H8@LJ-KEE6rT&f zX|Z|KsZ_W^&Zz$vZW7C}HuU}emi3ok@H-sT8U&E+Nk+elaliSztpgG6eEo;80h_#? zuZUKD(_(Y+zjTbU$jq}BT00Xo{wpEikqoY}ggNg+TBF~xV#@?h`-1@C7I8}03imV-%Z*Z3T=m_?vGT2qqkULApEW?4@?-BR}W z4WB4mYd1s5WJ^e=L)(y~Pmj^K^Q~yAx8(>HM$ZuXvV1w=aEdg2;}R?=3jaImI?=agTWl%& ze#4SO3N;<^D1apI)60LbrhWXbn-5o(?aDQx8NEX*z~LtS^(YI<%{FRnCS^QBzz{G5 z41tFt5a9hoN{@rFaph*yJ@Ct73`_IHgH0_5LLERRN?DY3aPtfX=8GqL>DwoyMT^lk zoek-Z<`*{9T97pnL%OdpS5AKL1d z$82KoG8%U_Q{$waN&mBLzltfp`Mj+GSo7NsZP&Ce4sC-(I$dpOJB8;}nI4Iu*E-xC zInP@xM9D_GT+g_8vmuvX(~HNh_RAg`+>^x>zH0RYNK&DQ#>-cZQHv`4$;w7sZYoV= zmF2Ldc8$*=3)P(MXl*8Byw^ftI<#F&^)rUHYo15r&bOj2Q_=JeB(CpP70MW)T9a0c--Nl1SEeAp!Kqi8uMYXBa2;`Dq z{+iV#Ek+A1kDy6+g&=gW2Me_Zd?OnIhJYbp2s{A-^~|yvyDr7&QK!;`C1j0eX8N9? z?ULtMIdcvDO{50_BsO9?8`_Gc`PvR`=hDKxIJ6bD`D#PkIX*AS^~ejoR^2%+HDF>P z8mhJ9rIHUa?vyT(V2lq`JL^?^uh2aXY57J=!|)-R>~DMQ<(lkpRVwpaXa+Z_O1(Ygt!0a~Lh z^fDHW&Prnufl9G;08|LY+TkaB%*q}-lmIhezOA`*oh1jm(|-_`;| z8^62*MnTAR7Y{1690+v)nFx|(HoAFs$*&D?CfcW zw&zdU&cPC{4Q&MpTOWgfhueC18VZ%oCxp6-S88+5rD=epoTIGAuJ+3ol^ZJbHm(p= zxF0~03Pse0w!p!b?-_yV&~`1cPZ`=SxgL!>-->pSue0$jNL=kn+a-ie$Ph3D3;{#n zBM@*fQr~&?S4^W5wxR6_XifjlyYvUTw)`g+BRiann1mr<2p9r}z@rfe2%x!lgxU-0 zJV+FaDC8hGuH3960iumx-T_mi5bP};L~1z@>Hsnkq_d&zCBGcnUeaQ;0K+3_(p@10 z(B})a=3>S*1PlQ~zz}#O0yeZQPYquB*J*8N`^Zz)eCyvrL$8HyFBE8&8ZfUg*4i>4 zbt<4+4`S_?Jv29}+u6B7Q{jF9Nh%aki7CG8wy0_f^4&!mZn>$nrsZIZ+VvL%HBz$h zUDpR9tsOWDD~$9-zMaf~?!VU!H^9OhbS<6|O%7B!Fb2xu7Ej zT6G|5Dk%*PN4hV&B`x{Hpmr$ALRTXtiyf{I>@BWGG}?QQ?E>8R) z$sZ*`KV&hDL722A1X~S(3kbxa?Xw^MdG-J;K0{y$fgg*MgD{FAs)@PvdwYCR? z#W+-TReHyZ=#aDNDze$Asup>nELKY%3e(n~yC zeoZfRjSHkNYz`HBLFaJadT>W9nnD&!M*WhM2^j)?1b*+6pNblvw6((!`2G>NBZa?| z^{p&{MG@@Tf~WqXNTYptqHfzj(!Wqz``z^MznMqj-LRonKY%198OgeB{f8A{alYKh zM)-U`+lUsUZSWx-SN`tBT&yQo2lng z?hcpAwl&(#P%;^_p>6u&iVvFxpI-%Sfl=O1S6Z7&8PgExBVa?@J}yQz1U?)AeDFIM zuKPyxm2;;-*|oL@gT*+NV>$YM=}-klp|`>^wYGi$NmUw7S+@X#bs!$p`NE7`k@ItL zaNB4_tEEd8^fI%qxzD7G_mvR9DgA(yA9Xgq&+q%RPGAiud}DuI1aQL1DN>i7HCVJL zG}?9P%f>*mp>0B=#>Z!X(#w?(OVy&fZ47~B1b$zZe4L;SZ6AlddHz5I?yyx4Pi3^J zb#&tLQ--$u20C%P-N5AF@~sdge2$2><)Q5*zuN}bE@?5^lcB9gcJqbS=3>TuEd+4J zd1O`H9TDO@S2~yPi+CeZTCXxtaQgITh{)kZd$x1|p@~qN=HhV@IAZyCp5@ zeW@Lave4B?$zq2q1bd6?5smiZ2-wiJT)vl{ndJp_Nedri9JAWc_QkI)OV1E61PlQp zfG*R4Q1^{XQ;k4d{jPIE-%y&Np<2t;g0v#lXu2p9r}z>^`++^1=3;8L(!6dLWi^krMT z>C*S>mmE?El~c9)0VH{sUgF{MYkH|`Tp)d6bEw!0I{YOqPvIILr6UW<%{HnvlQNzm zUa1eCFN3~ev@<~`2m$bH!PazxHzUGzmeP(4(+J2uuH;ei^ zM4;*0>b`L)pP*8;wg*G+GjBp-ck3VnO*FC~o-TDq9L4(qBs)?cWkuyX1aj{0qK zBo3iAT0fvm7E87-BDQ4HgbV>gzz{G5J{W=KK21}5mz=Tm$o(M)wYv0WB1nf{>W5zs z&Bdj;sdcEF^tNpdCS_&CYyepDe5lx0v^<4te3T9_C^y@v)=bKHhCm;I-}~gJqS}+T zPxa%lVBU+s9f~%zy@242vVe{6XB*M7q3sMM<1Hc3^qK8llLZ^>7)O2QuIJNj-|w!g zUGOYTxoXwnhnd+>FTCjW4&?Q5Rd zmX#r32p9rSgh11`)qUgAL@;PJwYCRC?=x>g8r|`wLluOP?oxNeQKTP0(v?PD)-5Dz zJZb=Zrk%YoBUdE-nL_5b(TY|}mn`UIW}S%5gp6kh7y^cXA@EoPn)@_$=~)X+i$bGa zm%eNaBpcc$G-`Z&1}MD%M!uhI{ETTlL%sOS+9zzxnP1eu=LRxx$-HyMs&6f9C{Q#1!64P#6 z5)w5YO(2ChecjzMa#O*E2^<)M2Y-}Bquzf@Ykjs+Ul4)VxP_QjYPHh27#l|ym()1! zFUCk3AGz;!iC=4{1~OeLv2pc@8;_9B_jI21{krUQcTr@m;R`IQRzHBGFB$ze8%vi- z>`*&_WcJz1zmh8T;?dx9$l}ys5=gy&wzec~La%{9z{UCZlFkiT z{rN(6Z%Ou^UT*0n9?-_$gu7>2dC8<(+z8JzAq?4DRe88rJ*$z0wMxz`x zKF2I(w#cJ3Qf%|`2;jr|50{<<)S!Z^9olfG$}qS!M1^(k5gG7y^cXA@C3c`Zs)ct?YSJdgluLC$s}pwfEbE z6mLisriTnP9o{Z3u&i4B0FpJyNY>FE?95-t1$TNx|UQ>tL_cc5#-M0Oft;d&v-=BrQw2EbF^#jPZB%^rZ6Ly(t{#OtRcvmj8i^^< z@^>Q|d=6QhT1*18wj^yrFM>eRXW}e$7qZ*+a*Z~wXY_o@q;C6uf4JaR&8b#DfMnFA zmv|tixPw*`NESMI@#F{Y7B)!UQ?$nCkOk#t8?`o*GTv(;&>x;+w5b=_B&j86#aeSY7kbrQZm;T!wwB7hT4PLaBAT!W<)g%DM1 z?Ev-Nmp>t~S@w{Dro-FCrRj)A0VHd=6aGIP-m+P409f+OjQo-~gxYAsfG#jD*>+1( zCS(X00)~Jg@K6LCyw~?e{FRtkdgOMKXxFtjn*?dw96Z#11E`D3;a*ZxIq7ZNJWR?u z8rm*-hTkZQ@ULhE3fK53{YuBJS~P1LL%8Ujt9i4)LWNK-pT`Nad###O)T`E=X&`@;plQ55D>s|g8$JAeeVmj z*!SzmU)nSs@#)Yu8r6orZczP_LkKaW_h>os6tEd(A#&5zO}WN21PlQ~zz}!}1RSF1 zmY%Q_B1@0lAM#M^RBqmMageF~22fcx`M$e3+)L`0@TBWuK-SUFmH|S(yBsR^6|F#% z&>Cf-UZ`>0sI?={D29L`Ub=i`9J8JbZP%>Q+M2jY zy#@kJhgRJk2}>#NdbvuQ15$LZ$(U~Ye%WktGYtXeRJb2Nvf*F|O?i9=tvV1j1^M3M zNepGTq$SC#cKroGjg%~QxYFNoqt=c*qr55t)1mFsiE}43GHv{Tp{=LU*=98EYywCo z~I1nS0dGpGCSK0Aup8w4Xd_E0(6K zXMbUT9(f9sF+U4|rq8VI@q{I(u#jXcZ5!G)@HJl{T73BZ0Wj`xZ4B+-`u!W*e-Q+x zL)#?`?vx7np4!YzIpVY@Z4*=+v)%yQXlM)ee4(|um~jmOL%2dTWik{ zcPX(pv_1PVHeVpN0ELz=v+px|neUdQOvn&01PlQ~;GqaOc*mF0ruKq5j}XNo3N_lD z%FUZDeZPU8)F?^EO>;AC6hKn+(3W*{^X!V>Xc7Qj(F%x!gXvKgj)Id-nDC5c2p9r} zfFbZC2-whe3;9QJY5dCKdPxfvpU=kHleSNC5qyVXG#wgFNS8ASOZn{XURB!cAkjJ} zW4i78We?5GGz6Ga;eG(ghJzt(`=M0_qNX6mZCwrnQ-n@m>o7`Q1P?Zabi~`T{rbA`tI`vqXju+G=E#Sbv^wZ$eX0Z@R6rr^>ag#Cx_6P)?%6sZ_ z?cxknSOf$nb8kP;0<9vLRpy7y^dC6Ci*OYll$k z(z6s_P^ntmgTeZ?Z9+QSAA+V9V>LS2!Ln-g14tI6Z;*8hu-gCt>U?2FZZ21I+h{%5 zEj@l)T|YGUbsdv51O$O!Wb?eMzj8f1ZyFZamq*~OAP{guH&5Fw!Gov%qHLqxK8qG5 z`1oGm?|sQ3h48$ZYV`w1^0)L7k6V6CFa3uV$)0WaoSeWm6DIEvZH>>Jg2;mJXB*X; zNg40e5U4w}fb>e|xYmHNV;uFJyBeq4u3shPEA) zjPy+ru%YcYh1;BcX#~);qSNxg0__?4$~i!eY>!>lb+U0zOl`XRe(6vJVY9ac5UJ%s zr~}AEX*gv?F2NF1s@C>ku)f*QHX*{w+~7mH+_(aK^F_7ha>g|TdI+dqqY9f_KM$a z6WFe3-5J5j&~~Ygsx_Lm%@;rbXB^IvfQ(D)ymaDhdd}9`n}e}kjni${uZPCQjS%{4 zF{i=-Vom3ts0WgVY!!$Q!5b_(C@l!BX-V%(Z3pv%EELy47@16KGa=)>76LZ3#V5q2 zXJ&apUDDcIK6h+r`&yTfWn%~!0*1f>0%%&%X?bX%nxL`t$H&TZMP<<# z0#^}uD+&Q8v<+=n0JJ}kyn>R+d?Et%&6@yESMGCY58P-w7~9o2-FE$YXsj;9oN5Iq zHl2T>9!MUtbs!+l7rhU4sYONd)OPSP%3>Y_xU{w;Z9*@BfDLUopMQ{-#;^RKx}>$a z?8%0<83ubX1PlQ~;42|e_iY}jqna#r%8qa~+UOqx`MZ0la<3E}o@mnHQtv62sU>DQ zZLicvSyB1;tCk4ll3)At$h#k{ZC?`sUR>Wgz3{CanmQy-TixO4ZsP z4AwUr+9pI;&l`M5mqrBe%@@_0%Nf@YFa!(%L*Ri3ycORzv_+$^^rNt$?Gj8T^l1qE z=(B0Jl}`3grRVxYx;XHRS#eO#7~()T8M@YSJwN`IL|ptIu%)->2cnJLddR{JK8GyM zEk+4iTaq@R*FfNgH2z%H!yi*y$nx(=<}JN6+J8wju*!DJq$G9&q4pc{1q(e$OqT34 zUWC-@2aqh>VWzCfYYzJm2*l<~_M0ss{JA)|RkVp#<8#Pj$!O795;dV0LLe2Wbo}V^ zk}5ztVr5u8ihh=Ev|}YmN2+T$xQPX)=Xbfz7JIO)TKxdBaLFhjkhtJpP7{do$2+Gi zz@~)BPH^}^^lN;MSxjsxi`JB6yB9}5KCJ&}>B%tN02WG6Q~DAUBq@-Gl85>OJ7>!s z0@S*JPzR8SAZ@ai_TUf*49u51*?^7jXB*LCv<*I_-)2@?9<^GAy*C650YktLcpd~w zM=W=Y0s_-k_B>Kgk$@ev9o}m1w+U%OC*JzqwcAjhF0f3k0O=-xM3szWjg5ObY5+hy zS(wrK7l~-Gjn=_SOAnwgEzEsM+Jp=NL%L$iANpbqwT)J^TDoLGFO8k*t*hSI z8$-YlFa!*Nr$oSQF2{vGky3usB7W`j>(Ty7(MB78szra(V%vTe*}mU!?TZ>Lt5!dN zeqw)dNvl-+umxDJ@i}BMj{#h@wj^#sFMPU-oQhacdEcZeJa#cv>cZBxwcwCeEv&PvmiYdhQkuu~aswb6D%nGOTV zQ`HsoP zhPAQ|hPIdda^`$Vi_xA8Z9S5iFSIrnGw##8?DEmX(HNTX?(3bCe zQ3_3>-2x~zKAJmVT>8=)XiePM`V|nsY3z_IPQay81}eM|Mtvtb*CejnuHOKYt4lGr z)2hSwJ3CENKD~RjQ|oTE(RN+_fQaO&?IAbHVqm5w(^^focdv{c=W}brtn`Lx(0rV@ac~q%8;%VC}8OgeNxU2yH@nnHteWd6_zOdV9 z9kg0{0DWn>h}e=%6EXx00YktL_+SK@`!sdwaZAovdgOLfQ$bnZv>K*c&iU~00KX1z zw;-G83d@c{b@+jFEsJ{prmk_m$nI5k+Rc_3`N9YdzyG$4R zhJYbp2s{S@{o$$K{Car5QuG6dwzN6h$QYDg@A?5G6Oxf<3F{ASXYRJGZkew-2J?ym6 zc9|Cr5?un4r?!XGAd4NYU2}y1^?+P1UcVm};rsl)PwOOTf5JER*F^v) zoSY(c4RlMmpyWl_T01~{SGk2`L)(arfB}45B$Wd&?r;;%adk(MQ49e?zz{G5o(+MI z8`^&CleSAZT^-u~Ck}5}!fa@}gs}-dB?3){R^8)qOA+%z;Jv4Q9}?aIHNn z!oDoO54uh^&PmLrmwfd7UL2#;9q}-Ldz z2dp$geti<@#GXal}G20uJ59xr>)5~l_ zt(lPV3;{#H5HJKDivT{XQDi)VS*o&-by)Q`59$gU$Y(W-l)hgUAHwW1|5D@1}AbY7cLt3;LZNE2B80lrUp|zQi@eF|h0`W=PXFvY)>;YPQhQJa6 z{eKk`e*$#LLO{8S!u6wacc}A;x@{8@|3c{vGSGa(+r#XWFo9@2fjSeX|^XYs4>zfPY-hk2)LQ=l6YDC+O2qtu4r!h#}A-U_;v$ z5qob4d=di9%(9+(x)rA~{fx4;_8rc2ZcI-OgxZAEhM9@7fJ*DTCIOWIID(83B9Jb{Q%YGz9(_ z0yeZQ_}#9+XhYj8XqoKCBM@M6ba&+3qgaTN4$}R`J2E{4^bS$&_tL!>no}(Y`*i@B zcp!~hRE9X-=zXXwEvkn>YS&*(j#-QY*l}oWN3-pVBVa>Y8`{43DQ@W*0)~Jg@OT6~ zLO`e0^o{5%=V9u-)JD5*f3p#`lzqQCw58z8w*!-5_5(;#0iv>whPIddZgRiYtU7>9l>0WaZVs|_ARx|{K(;m-Bn>yB#b`&ZfghUaFlepAGm;@-2p9r}z>^^G z?S{4?W_)MXeZOzyFKtH8s5Vd9rm7}S*ve{8+Abk%LeGi7pGv3p*O0^WTj{xeaO=@J zbeU;}T511O8sQ*+COMk?FU|J-{)_yTjaa5uKY(mXGWw?&cK9Mt2O`|*8cLc`2Cz+~ zg(=bg=s{`lIbG9{%gQIAJ}iQm%_U_M(lds#Z)S(^&N!-)J=L>8H+o?tpkZ5DK?y^FI&moH}boN4PXM)Cm zAq1LxH-}q13#tA&$^1RN)Y>6l6zRyUvMr<}*7ti$VxpJ!^8=P|Nh)jg14!(*^b(J} z-qS9JeF!9RPLJ$2S-PK!?gaMHCbHzYr|+}asgAd|G0QkFj6f<->4?=R9e)jZNtI#s zDEe8t(T{X*5K;k1Kr?Nl#yl(m6=Gg+vs?`r5 znYqK3tn2}9U;qHTn=hKtJG3-ffHBHq9s{^)ZAsjO3;{#H5HJKDfk1#$bi@vCwUq^7 zviwAz!w%Z$-8}iR1DAckrt!OLw?%TYdhn>_K&S)AM9D~2x#1R|vi_AIwcB#MM~l%m z_>k_z`pQbJ6=9Px1PlQ~zz}#00{E~-#S91nMTE6+7MmwCVAoVo*0*hQlJ@`M7lbI_0nILJ@M5_1M(`Wa5G3AX^6l;(TGFt#{bw3Yi-qL+u(L2lhr7 zNtkVDZ6;*A*FxZibh<;^u$1fHDb=5uzL9@nXp4(%r`p-VvJNi$0VK^k)MXtFZLj!^ zCIQHg07Bc| zb7W8ye%ZE0yJ@?VC6KgPZu~A)Er#T=qm~1q)AlBkk1t^H590)=T)9R(boA~t36qUz zG1>+n(%r1nhbjIq9HIUe1!Vljs5$pXvN z3XpF~c%n*1vTh!-H2@%+ou?7qjg}k^dJf=D|25FHW@>}5HJJ`fyW@w%q;7v z=UOc(L)#FmR;}F(B~yNZwW06Vq4cp7&OwnesAvrWNJjF|_W$C_LfIYK`nf}Je-$ZT z0$tORXg62X8+@3%WWlV&TW@t@t;aOl%OX&BXdZbkoidQ+g;37nNQHLOct=KnN?f{r zo$^<9p$Iw3dhF@|GVwrikgWp&alWw8);nx-h0G0*p>~ar1A8NkB+NFnHWM=5Yawt$ zI^Ch|TB@Hiv|V!jR-^(yH~#q0_KM#qYfsuP0cJvmfFWQAd~pN<@<*rT@RsEZ?`MmC z|82DKHP-Kx`OP+f*!V>wyVIC$J($#TAavSZ$w*fDh3f#7E3Kx7j^3RnVX_e|M%&;+ zx|y=xoy#)d1lp zfJBvID(mJUTLa)goiEG?uwBw3sG>E>f?j69(ArGMc!q!>Ukfz2_562bhmb z*RK;kH$v#Hp->%}9=p2n&BO!ALADA+h~NztHrg24u4x5WqjvqpM2+|&sJKG0yU<#f zYs8mC;D)UFL))bj=TnBZODE%72|h5)KR&d*;x~E+Y*(~2+LI@39ey;^MXgQ6jA;lM z0)~Jg@JIv#oTFSgyk+^q``Lm{@0V?Bw9#Svoidy50Ak~p-|lugqaeOf1};p6Z`%Gh5K0i1C4y^(UmbN5#$X2^Il z19nXXWqs3fJbKW8<G3J`7rNK}xxZXU8V01njo!i)ghB`roPTB9uJWflyr z&4i3+2p9r}fFbZ$1U_tN8)DV^xF>DbKpBlYF>?-Epq<4hZ7Dz9{3=|}nk|&cD$#DP z2uXNCN7*Ng6I04^Vogc5`vM5m9hyhRcZ z({gyr@`d-a1@}^a(YwUZMu+Wp%51s=h>c%(_}WH$v#Hp->%}9=p2n&BO!ALADA+ zh~NztHrn>2?EoPoe=Y(J=Btxeu0OpXCqamXD1yt}L;7%~$Zr=!zJpBdm)8R~5bH1a zW~svc0FttY1;iBJLCb+r0#Q>S_m-f<3tE!AYS;Lv>ym|2FO!{Gn+O@}#Smy3xBB1J zSjshMNv^e}f!zIZ70*+%?^pkUk0saginvX16YSNv{UfYmEn9y_&e;blcu2+xM%F|50$V38*yGxp(!9FXDIG@QmPG z99+?2v;gBkzb~1C5UpKNGTHAP0fz)|1=M#(mKrdz5DnGZZ37$ywEYvU+An)(Zlcoo zfH@WJ2apVSSka!K+oGx|$oH0@#1j6JmL#v*h-Hw4Q!kU9TAK(N>%|c04^L&pxst36 zZC6l=GB&hb1j@v|9Rk06J6G@ZR<_gXhSL*QE>fc`ANU)?wQr6^9iPHCL8EnYW$ zzv_^Jvk;n&n764Nly*jhBx`#II~-L&=`8T8cc*ubI^rN5qJ`FhjvoTOj7@6mKa(-u z*Fpf-)&r9E5Ac~>zR&Obw35Hsp&y4cDdT-X1Uz!C?~Q~jNN7>$S5UVz#ydA2#MNA{H~OSBkm-PvgFmp&|MjWOBA5LiYaTsec6t$wVa z4Q)RbPqX$Y1nQaP9bsU!sdaP`-i^FFcJ<6uhLVZ-1_}O!(&jItas=rpIN6A0YTY4R z2at&}td(^zv~{pBUBoYkwwJUREx-_Kq~GCusg6=>8nH273;~CHaE{b>N0v?;u@DW_ z+Hu~Ik6q8FThXfhvWMoTm>9gmoC@~?NZKAIv?u7csA>xGy(K8IgukR^LtBN-c7F^3 z8`_rNk#?I~2l8hTy`*JBTY=41L%Ve&+a(E^ME{Z5sI z4XrK6n#ju_;E)Nft;0Q@^F+l$lx(z{1~>|6`zKnpU-r;ZcHw|I)#?Y3EP0sIu6ER- zLU6JK7$w>5oZSEVJMb)D#2vl_3PzF*(kp1*H8;*S{G&K-iwjKY$5t>vjxe?3sT zHp>(pZd7Y1VhlsT5HJJ`fkz|Y5kP%!BwPuLrAKZziFT)QvyOOpsQqp%#!CS>NKva_ z!jn{hsH~%#XAqk&j%;l-NE&WLi_tdtkd7>dhAIZNDyqFP1eOr6CvBHtG9g3Y0}$vB zPdVCL@NlEd9XlJ^5|Z8KFr0lW%me+tQ##$+(DoFfR}^qa3cc3h9?yBsVj)U4+D!u- z1+@JWt=cbp=qS5zz?^FJ14x!U%xPCUYEdCLS%UJew5W(ywQGD1S*VxEPOVLZjP+s& z*wEI7wl8){TRMh-Az%nR9|BF^R`-p5Dc-ZLQ|~kLpK)cg9N+uDoF|@tn zSMN?=(K_Tf%3_ZjU^*^p?Z`8VA@GM0@PF9Cdkrj||L-+!dWOI^N5I2leQzXOi9;`n zY30r)dDF$iL+#gwwh0!%2!u|Sr8<9N!`Oy^Az%m?0-ub44Q&g+@A=nh?Md5DJ~_?& z00CcyAKMQu3;a~N)F9*6fmTKSH{UhdKl;pZo8Geem&o@0ZhsU0(khmz)ej)ql8geo z^uLDeqX{I_&R!fFQ^0nnkogkrpQHzF@M*JHGP=>)nz%_B0)~JgUJx$hDnnlviba4Uh2DHVaGYyO1X?;7qkw) zLB?s=D2tOY3fnJ9nb0dCkQ%pi_QqB#or|$?3~@<~BhLT$?&SDa;)nFoXvYT9MQUnX zrK$X967%u@zTc3Y?kwhWu|xH7+XRxhr^kP@M6v|fPBoH% zL>s-AkFgq`Ll#R$1FbEIo6u_@(EpA9zh6l1o@M_WUjr^qXx}n}|1?*6mq}Ty?>FBT z%0fx{^hi$QL9IamNk%ft>sut;6Ez-nAcc1Jn*AnA$RAE zu{QMm{+9KZU+_B|)EWek>`6wyigCaBysZNf?tJ}+umPLAov(;ie$!%e@xOG8vdGM{ z7g{?LH2y0g;E@cjr^7v-^IXM3lx(zdJv+6bTMuIGcd6Mtm{YBO07)T03o*ra(DGpL z0|oDA3mfh2ik5>(YS;K2vY17nJX%wd?Oq*$W@cGWJ>63F_zj;ZTWdE%$z)4Nr$gJ2 zq)(60xbv-Os<-8#Z8-Ir1lpnPC9PYskPZoNl!bo46#4G!txGlHS4KcT|GzZ~?pr&A zzxVllpVnE5Rz}Yd`m%gE;c$vHed7`=C<^~O>N?T4W?O72`+mccLkcw=@hE^K@6*eF zu%>v2o>Q z(>?IZVhl_3#e+>P2SOb{CQ4b9b#U_x2Ih+=d+FOJq(zI-Hk}RWj^-CO)LM`=5ktTb zFa!*N2O&_;EW;LZ92jvf)e>K%evdasYi+l=Y)l`IUmx1)m&a^k@G=^AHdEuIok{<* zZNG{szxlka0a)|f4sF-8E)H#jL^@qc(Wmw zU(<`nuJ+3w8r+k`6~1cq14vS#h{nrTj!}y${K?8jTW%^%WR>NxrFMqF;4kWJjr0p8SCS?d10)~Jg@Bs)o*g&V%^o>gn z&bm(Yt=Sej;%)2u4NDFw)O5tBL))n6sa!XxHnb%$wlM?@0YktL_-F(I4E9S8YvatV z7E=eYapmSsmjKbmFC9`4a^1y)N-YOM9Y7|6q(!x<)ClB~U;diaB`rn^Esvl{cZDEy zum=mZ27DtM0)~JgU zqxQ>Ylba$ncy)!Y!uo#M8UO1c5Rh_xZ=~FwWjUC`f+7-y90bReo8Q&~L>s@n14co}br%mRwHyd_ z0GSAqWH!2acFC^|ZGpEfhJYbp2p9r$1U_tN`+J(OgzW5ThqmWW+Rniet_^Jk30oh7 zfQQ?9cp3_o%_oGqi&tuM&!uUAqnx9x$FBCv7L^++^fs;#Rk$BOk_tuChPJ@LmhTyX z>Ckp9u}>M=F1a3!JKu_Skgv1xEl6DLN!ulaO~?>11PlQ~;3E)lFjC)n^;b-z6Skr4 z3206K&b#yny0-i$79%^HiyzbzlDZg3*BBQ&@44zUSX`YWkBjwK(`*m+An)( zZdA9kbA_hD{Q#0wD54TmeAjJJ)fD8ri!|JFQ)x}h!4|daF9>R+WZ}E64@6o!aE$P} z2y{?hdD=ZdefI@fw|&1n2f3Ms0COr_e+Wnb$wqTQM+&s+K-5%H8XS&v zUv^7c@`*w1P?UwPMoJbtTp`$7T#sn97e}D}6DfZ4IbU?nOSwB-DyeW++Gsn&7HH=u zo|=8Xzfy8#BbKSv4W8Uhy(h(p_FKmPOV0a|>9z!CyK7AXf|6hl-Kp@P|8f|6@(4+e{ID#vp4{i2cG zwjgrT6_%;hZ+o)|sgJVKLmkK^zZ>c`ZB2vS+Gst*Te@U{$mT{h_qm*L4FN;I5HJKD zhyXsU145`v&stn47E!p-u4`{L2GZgF5H$UoN0CD1RIPphN!+EEc)0wUUg{bbNMG0- zD)xfT;lB0Yj#xB>ES8M=B`Fg!1o{a4-X}j5H9l!;havF&BXCCwe<|x*Spth9*s}#s z{Y8;R`|w2Fwt=L7p|tk9>EnMhkHWiQL#=)QNlG%3b=&$6E5hP@xsi?V`F^$$Ek@hm zLprjU*-{?0lw`ZtN1*95tIp9crO%FW)OYTBKHc{H^5cS=X$UZOj=gPPg4U5`5V$X-V%(?NF43u0~20J6s{yTU?K5v=>L9o>?|i&!yZQE|qO-w40%1 zGG;^D^u-k)HVr<%3fcmryq~VLHkC4_A<##_hPHiNjA{scI0E?KcQ9P{jp!@qPJ^;* zZ4U;EaVp1h^!?JI3W`E+g=K1O{Q#1xG@P<-0S4J_i3HL8cz7e{<;X@gp*UGE(ZBvfn-D5 zghq{z&j6*DD<77sMRnU40?P>ezAX7TK^xjW4tw+bfe74Ts~(=pXjALx#O0?9ZTSs! z;&{7($-(7YAxQWf5pT;w+e?184X|C(VzehiTaWDK3$4w?jQd&$;EeOgs=7NO#CgWM zbGFjn0`zu0pKkkp*+X+P^$l|>+z%kxXub?YO1DK-QxnIIJYRN8TGIPcI}~N1tC5n$ z4p#{F7S|&h?ZpwWp>4T*FFiBM3+j>^-)$-KHju-#r$5SPd2_0x{ zw4&A0B@22vSlSVY*p6mfL%JVU?`Fa!*Nhazx? z_x{j!DYQ=++Aev%L5hRRw?YUgWA7N+Uh>PK?IkTndor|LGJ5gZFTCjW4>Is)3?=q<5E6B zrD|;thTdo1gv9RFK?a&=WI;S#>W(;y_X9|Fq&~`u%6ACl)MpZ4Ms7(QLT$8uK$k3* zY+pod$)*Vz0)~JgUB~fr4!_h7zaE;4OLJ4}P&w&s z+Z;^F%8J*|7lAtz zZD@M|!5d`(8{f}1qGdzd8A`@mLZIn0+q)(UHrO$a`p#X?r`x{YU01u{S(2UE z8^>OF)S~W`23tqE=Wbzx6t7$!A~telI>ZdPDFWgT56)Kp7Kn z@vV?#wSUtV*xB+uBJfk`)B^6<{OEHMPJdDUJgI+Dq|yFUX~6#)D6suawtc@|`)v`N zt+1?G{Q!~)$;jb~jss?wO*esL+S$v$ML=Ma_tRCPWe;5AbI4+9Oqib5gkq~9U-MAzqYCM`i3UT_n zyJh62f(;WmFa{6)D2qnD|CZMJY@@y)0RE0>Jv8}A)oK*JnQ>)+3D`0$Xde}SXQlm07+jm`foOtE|b`yb^^)lvzLD* zfe`-}*wXvcL!#Y&i2uc-!RL_0slg^;5Q z(n~y`jlT(Z&$RNANw>Hk`29-~)4wH`-c61>c+|RqPzR8Sl2Kk$wmIxWATTgr?wOq| z0k*j~xOc2M+O%)*Ib;F(`9f=RG2^}%0zbH%P;+DEN57nA(a++kexw81sS>0EcV6Ny zl{Xw+zsq$NMv7(C8U&D}5tCM?R4LO@2a-uAFG2Z$O$oCdaEOgYIcj{4S3KF9W|n3x8=9%hc)zkZnmu{}9XNH!a#gggae53U#X3+)gzTQ=;YXMl|>wvN*Mv z1ZZtZ+Js&Nfu_&IS?Dfgx9jB^ZCuaj`I1T9_Wk~F!LOQAt$qN>s7o*LKumE5ttOBx zbn@cK58N$mki4g8jn5$q%FQ-vZ6;;B*FvB_JjG~JFS1F}ck%*GLulW?;D}Ryhl>BK z_SZ!KC!Cxjb>FxKODPH=s@B>8>boz0LSnP* zAp=c^w~I^D5sv~$)^aEOe>%Knv)ll%?IzK#Yi~9Q(zZExsQm^|7nj4mq^5Gx+qQX_lyx+;UGfaSQ5NA} z(Fzo<@lpDfj$5^8);5NKAz%m?0?&rPV0elV=Ta@f(Ds*9L0!%d+Rachv3|?^_%iVO zv+%Wo3#GGq)KF^m1IU^wCLi-T8QQM-r4)v?eBTL@B#D+|)&`$83rEe_hSp|6#(Omc znm!XJpu3Q!c8v0i2cnIue%JHqw(s|c3x1<0%&ArrJ_1NaU3!U!lAzTDQl#dup6tNg z!UoZLiq`lXvY^~-qt<3p#(OOUrbFAMRPU4uI1QVbDMy?ahPJdh-F*DecIu8yX7onV z!lsS(2A!5JFfN$n-^N&yH6cU55HJJ`fd?Vb^lf$DxE9k{*SY)N7ih8X*O9-pX*%N5 zp=~s(4Sn69`Xz@DVn*-La^fjqGs;5brmLHBjcEuN0)~Jg@DvC*MA0ohVJSqG9=Si{ zq1LI~yy@Z~Q~M2|vTX8wcXPOx)Gy&l*TaCUqoFMWgnV~7RO~BSfhM6f%0j(RY=v_yI#(PouNVXx!NZkW9!Ewz3YMwDmK0 zSEc7y_1gi;s-w5az(QloH`_>NO?|pvXr*)R1ehEL5 zH2xPuz#-rI-iR;M0Oou_$%{hgm7Cwz9BkHp1E?&UeBa$PRecmd()BPPs|{@dh%JVI zAz%m?0-uk-#|>?NNfQ>ABmRIVZI?3lsG&cLbUy&bCkowgFB@H zzNa=bQ;s<8N!tV!$E-I1HyYZ4Jzr>TE@oUqzz{G541q@?(DZHS)7IKE#9d0P4Q z-9r9RTpGW!xL(pi#pkoJ_N48TTm;`?7)^(U6Vl~O!csoFyH}MqJ4m$7$(U~Ye%V8F zGYtXeRJb2Nvf*Gz+kR-(fv73S_ZClLD7z&sNnW)P%OHy#uJm`@sI?={C@+gZ_vF1a z?bmZQ0HyK8b8^vmfted2^w(leg#*Nz021{;@{p|n5F&VkrTy?((~|GO)OIjG$U<=) zgptX#HWM=5Yat-N8;Hj3r}Au@bk0k;{zj=r8x5q}93_60UEi<%+M&ozSFybC%Zidw z;91^usO(&)9t+d)g1V#y9Qc=h8hqL;76OSPw6-R0Qii}DfxuIFPkpX^eA3nqL*NAv zDE(RctqYeRE7L4dN2bRP+VywF%+qgceZOdAw_Sav_2VXhL@f_O9Y7|^hl;H9PzT~* zVY&oz0gxkMvI*cZ+6EueJp>UM-VGLN4fsYj1PlQ~zz}!>1n^<)5K3Komf{O4Rcm`N zSl_lyNQe7F(9~kAMkhO1R;_*j$%6C^vTgx(8vsC^FU-izp0#4}WX}cwO@YG+FZM55G(V_$&-|PFmFFB+T zo>xjhnIgwS7$ITa2N>omRxl4wv-a z?e9!q^2@u^m$Voyv;u-A-4}w;!5%Es8t{$$^$@_d^?<}5bvC}w@B6e)V09;aV}D%) zaKgzcQrEyGSb|E`+8zwnHyhd}L|B;{d`OoYSAcK6sMcK0xQ0LvfnR#W=c4(?H4o1P zghlh6Bk)$@4>+Ogsb^S9?o)=gy9zxH;xGoS!`Bh94r_0;)*sql@w;sT+ZC-lBRCn_ zF4a-BMzgm00tn!Y!#NU=acP~GPMl58*;;#ZFt)34y6yV)(Ac;ULVqphR5(Da>HHJ* zK=P2S0uds3gGC3W1)()9>3yl~V1AH=;yMT;lWA=xWW3ixz=pQ?gt+v~EH9`_TARz~ zjty;J>k_hT3;{#H5LiF}O)EMr4-Hfk^p$fnj%<$|w41g&F}3OL`=vt_gw5U(K%|xj zp$;Gur9R4v%4b7cKxT^}UY_xEjlnxCy-i0yebWeEvCJ8o%;`>XH^NQybd8!iDo9IRu`{ z&zq3_dF1E)*;r&(5UBe$57jG|prgA+8~tM-e|Ha6n&oC#e5EyyUo2snS{?+1zi(hA zBUzgUm4DF@7N$!e_ez5*T8y^AhjdT#3ma-J$eM^DUQLVY0aSeeU0>AW#&qee2Sb46fEE+@LDgtjsA>f3z zq3sHQ_UDmTP%@cMM4-NT6X5B}eGct`8*K+;yBeq4u3rz0)uotItpLTQ^H0v^JML+0Zt_U@wM% zAz%o6B?Rie%_DVGlci4C5w1oX{bL}1cMnzWm7>EFO*&laJ;gG$#7w8{mHH?vDj$E< z5`kRuYkwYj_oKD#Ya+ml>szN6zO_U1X9#>Q0=SkOywtUK$#qbvTHAxc`esAhgb3?- zgAeJ_hycF%qFQq~;~D~nfFWQAJP?7m;@gI{XcU%y6gIS7g2{wF4S^qhHtn|3$^NPI zTz?Jg4ugJWt+hP{r9U_t^X!-Ve*a6!r41~rRzHAbOEUVm7!G)Fpb13S)AgUi71-qc zbVam3Ne|rMbI4+9OqjGL1X~ROL%zYj=Og5;xp&! z@B4&StC-o)JLuh?C|6?A)?jm4xeWxw>9T96uS6VRlrdEJ>@4}I_l8Mp4c*?pE&{P} zb1}QrYQ=LgHIC`*iH)O=%hFN$-lWxNrv@@zDzS0J>AAUlzNho7@Au!?Xo{yoXOrI$wgFNp?L*>0JX#BLzeenY-sp$Cb{lAXqjkXro!l7&0W zlr?$HVIKm4*nG);vn7N-7YDbBHqmN)4p}T2Em}*WCiFrGqym+WAAMd@1xQD%468@c z&(e){tOV&ubqxnMvEcOlF4x&&50+J{A3zo^83hCq7u?Hf0#W{W=adE5lrY%|4nK%~ zjn6TQi7jQ(nv!hy;t0rx^&c%g8KxV+LJ4Y0Ut)qJ1@chxP=8?OY`H^#S~n2t05TDz zP1e#L90GxX`En;4u<`wDBU+5M!H4wQ%u36nR?D#WhJYbp2p9s-gFxws<&IH6VA{%_ zN9rjOu!FY4TkZWeA#LcyTfe(@8_LrKmZ=pW-2{-Rl98;jaW6*=0Ej0GGg|*55iPdS zI(TX60raJXxi3kZkRf0Q7y^dCLlD4+wTJV%^th#vSb7E(l=UrskEFrAUpiDlYIHWR zOszoxNmI(AtZnV{NoXHndEb9!M!xVvU#y|F(TY|}mn`U|u~WTu)jNA*2p9r}fFbad z2)NDVxbP=Z%5Pf4uYGIaZ~N=BX~to)`$ zOyA|0_%~wmyZOsc>@O~9m5Lv>0P8hAhb-nXfUDM)#7*c$5Ws2dkPc4BE0+&1ghAga zJzw(h1KjWqkprRl4P>uvin*Ou9lqaLX_|6vhZ_KPD#NWd+HNS*VIX;Gd&rEk=$JT? zXzj={%Bvy}aGv*vwtA6G@_!@mhFv`~y_0`oXuI^WA(lC~yuno+KqkttR@TAL_L5)D zoG)oH+LNKJM>6w;*5+cy{W=JQ$ECXTf$<69z0dFav`)geGI|2g7iQyx!zmJg#IEf< z#l{zj--lf%>Uk1#=_Mb1ze`n1OtdZeFo2|xGx{I4=IOg`IqE<_JXx60r7H_s%+bM1 zOAjaBD>kiFRC{9x7y^cXA@EcP;KSM@s6SMCi{xQhPAQ|hPE&;U+!evleUDyHim#9UHO?2=y~<9z*)k(v7@^_!-?q_;R!bKc>7{S3P~D7aJVU?`Fa!*N=Rlx8 zJoTGj5ARose&EoSHfI|dgYxTLKY(OHGV&~8{h{s59eMVoEupZ@V-RRMw5oG-OCj+> zXzvhtsH1aD?{wSs8=$dqBZU51%~z2+0k*dS-ej|H9CA>0}hkA2_tV0=TvwkjusE_roH5pWpXsodoSq_{RRa2;hX1Q>3neZV4BZ zyeM012Wamqw~%aT8?g~EfRBr$asb91Zo)aP?np9xC(#s zJFOXzwbw zkWPoTn;M0c-U7>xynXbG{fXyh2rOt!a#Hy`^fFWQA z7y{3SfDLUomwzgk{&iXw*GpRVZ`wZJ`TxB})O2V#AxnQ&PUy4DU?GWB+Uy|Fxh4VK zcKwDVla7#IPhX0;op3*ZWT)wc)kPJ^&Qwww9NK8RED;8B4H?N(+k-#IVux#EX#bYh z_C(viI06CrRVS}pe@iEhScrxkj14ay4}rl&!!Mw^p+av1b9&}FNYw#k;(-LM0F{!f zngY4Iv>!feS{}BjU4N3O5tju6#7`DlJCQT?3n3uC8@Pp>RP)<@ONstWsYV+OB>qH9 zmimXt_Wk;$&k3;+3ur#^RjVIBl9%rSj%RuE4|o6o+MaEG6K1%gCDCpk>NP%xEX2ul z^|Uq>Go~TXMd0@?^|^>~XlsWd@ckp;kpgN^(>Jm*%@ReY7eyLvR8F^3W-;|3)_&!y zF~5lJR6AP-8rt7c07)u9R91TMU?31p2K3(INPLeLqiygZ9WZ)&nQf>w6EdD5Uz05YWHWMIjlk1p32M$Mb(7 z)t@QTpPAawwg6;9Tb?Mkc@_kIf0jTdaoEsy0*6~<(Ro!OO z-S@lEAq8i?9hlT=!rvJQ5S4W_wB4ydqq8{D0NW)kMhh*mMmn+(I-PYl)ar7L_yrO0 zkIVT{XXE?)zEA4}UHv#b5j6IfLjWgSeQ#vDa+kvqGml-rawn$Vbm{wDs#@@(zxG5e z4^|yOCQ3%KZVs|_ARx|{K=zd@OSBm6s5S63zp$aT1z8g@1X=`aXxk!U?+t-ZLZF#h z)>BWn;#8)eQMT5;Lz^Sc3q#ug-TBgvK?eaOBQmU&buhFIbBEwEqgx>a(C14V?H%GR zU9woJqi=Jc#(hl$0@A`c;_$X~j!P$wScsanwhe6oCKivCZF>F1M87|{EEphuve4Rz zoUvaB0UO$uuiIe@>p#`sMD&uD4Q&NBTMYq2z!3Oq2zVrnPOG`KiF>SbQ1o7EqusRK z$qJip51X}L8`>sV0HXs$^JVErG&f;fL%5)(9fFWQAe76Wphqg;ueag^w$@4ZEcVaSo-&v7it*nEg?M`E|ZHKlK z(H*Oe_6}Z4m!a)Wb-aBWvyAh)2n3|o+&#K*pF=D}Lk`CJjdx^v2poPX(G>>TMoOJ* ze5>W4PzR8S2hylTg^AgsgHkrUGjZ@dR%+K@Of+`~!KH=PmZVMSB@nQotqpBo;zYJ2 z-i5&L@6!6VO7^7fx5eAMeG&p5cF}1yedCf-y_ec(H*I$^#+K5Z`q*05?5XT$6 z4|SzQ^)N{7`isdii*W!u4z2BIwtaB~Y-npk+ZR8@Ej>fP5HJKDkAO!A=(L)?5q;%6 zOud)dXxHs;Ho}&&?^lPm6rA~XU^2{p07)u9RMyeZ_LARC?zdmkVzkh52#s`PA#|_@ z3$+G(BO3ySfFWQAJOKjuu&(coND*0z&r!-_*RR}(i8>N@eZNap3tqH>QpD2xja(I3#J=YIzJz9q@GtE#d?Vm~` z9OTa=N0a}h*}mU@k-xGL%hc)zkWEQO{}jUxUj*tvggaeBNi)g-wyCr*CE6c7C=EV` zEJSg-(%MwYn1+BMUcn~YUykA6(`Nn1T zPOBe4k_uT=?u4Z`@4gG?i>ds&^Sz_?w+>{sClx+BOM6KBrgl_X+tFu+EuFow z)$(ykjbl1{V&k}c=KMFxm+@tz9UI6HIjM2Q>AC$oiKZ)O;5T=$J_{|ph-GT^1IU&n zqrathF8-f7)MFrtdwTeMf$d;B)kp#oZS2-vR%q}!WRZo=UTE!1(D*NeKy&ZraEoUl z)jubhzo(a4JH(439hp_Og_Okles4)k^wNHQ!166gWvzYyiT##d;*r;T+U2khfh5l9 zk^Lr1_fyfGz&_eUmOS_LeHJ^_@%A=m8Rvx&NChe#u^Of0uOTm~GOQj&KT9{-u@a;M zcV5yKS908S{rV(x;V729YV-q0d}QQQ_D7%hO(4o2@6cQ)0l+qv-Eo>bP}^4F<5dz_ zC}FZoZHpaW41pW+{iCHPo9S0jsdGsL)o|NxS)na?Qh&faTVPqW`T-;}ci57ZJ-`hN z0DyP%MKgMbmPQLOMp?{b09UOoiJOoiU|@bpV+t8ObU)+yYeAzY?T&TaNc=G1>+n(w$geS*f)m zY%+#`Az%m?0*^reAJ(Xt0YRXMur|(O^JE6>nhMJLwr!5GeZO?5g4F12V3}G0GED%9 zDrHgD%|o^h#DO|rm=R#Rq{V1OYm^1O%z~k{nUL`e0YktLFa#cpK>1CJSbBVpqx_~t z{Mx7AS5M>n2PJClu!YRg-?Z2QYeV0!L+PW%`39C%s~p(!9FKo2+4%=KIa|2|kUE|}x-UuTJvkk4ygpBuE z2;7iPcW4`ya{W7{`ZLov@-GZ+agps*J6l-R!DT;yq^42r@p+tz3| zZFjN+k~YhY-=(U>kUVzOav*ft-bC{81uXtyoB)+8*NBIX-km04vJovt+u%dGn;1E; zsCD2N!4NP63;{#nX%N7NH7aI6T<m$~hdV&~6&<$Our0OV_Vc{>m;CAxBw{ zT^&Fs9!L(dbs!+l7dF~@hi$HqxdAfNuJLhTZ-kMA*@o6;LdJV71a3&DJG5O(^;3qn zORnFFRN&{vA0OIY@f&6BN!umBOvn&01Pp;MjzB>E=(HT(vV7tFY|-z(jW)i<`kgYr z*#;0Bzi4E48ndkjlUfdhPTMOP$tu5a9iVch)%4KOyVE30HloF78+=H26C(!}wGJF3 z7y^cXAz%nR4FdSEuJ4U(C_Su=vv56`0lTJxvc6py+BzDYZQ7z5Alw9ys8UR2-8^J# z034|Eg&6_1OIid~v_@Ib%PbgLn+X}u5HJJ`0Yl)i2=s@i@?7dtZ1$w>5=^n)=St5p zYuG|o6gt18V)ngcmDZM|P3Tn+s5>-|w8|;8)_`d*S8KQTe4^<9^Kt3=b;9RH2;DUl zsw2~5S2wu_RkX3(Z zyL94w%FuS{WPB^Z2Zs5_hqhPzM(=>_ik3!u@}#Z9k7l~4wW*jf4FN;I5HJKDi9mpJ zlnaNqEMIs(ThQtKvTcnvI&8mFX44%&Z2a=u-A-q`^m)UN9G*xS`zs=V6Ry5DQf_$e{tCqm8Bb=wuBo7`Z(5E= z4;rvMIvSmAV3}G0!c72)3KG}NL$(IMfjVE95n#Kd#b`xqlm)%af}ypUkns!wL%kU4R(!T5zS8_TVTI=wP^r8sd zkXL_byOi{&3~iS@zZI##^ZSnvZLj!^vi79y5@04|2p9r}z!yg#Ab)gP4sTh$@P4-7 zUg|G;ml)dUu>DS%O?LpX@yl;_JDu^?gGDU|LLERRCX$aYVA;?XP}yP#7y^cXA@B_l zK%wdnZ9$!f;mHozH5HWgP0R7=&{mDodS?U6XC*vo%6%JIHxGL?073@ z-JyBtm;P+60b|EF=sSbPwA*(5IuYeY2;DUlsw2~5S2wOb(YVaL(7CMZ{gvl4#}fZSc|D zk%c&!u9yC9(A1JKzaj#^Jb%)jm-q9>Y7rU&V+8tRA6FE@SZ~KU={lux&KkUK`hGpl zs!@`T8bAXE&p}(((fsL(-)#%9dPU1ahrjkQ$^sBkyt`3rUA7So0YktLFa(|f z0goV1E}9y+6d{U5lx?(|(wB_!o2^gp;!*o8UrY;U;nhLrq=YA_08v>-H_sq8UmV#> zRTk2s#b_IRNMEY55(2e^V5=dpjzG9_2Ctj_P|5gj+S*|VyZ{3IXZ7$WK$r5nQReU>xZ8 zC36s>wJS;{`@JLJkN~cL`tHb5111)tp<26bfTMu6f1*|UWe?3wR2m;Jr^5XJk^v7Z z+7onJR5b07y|v_sf;*RlC`1j3QAGNhPI19 znb@~O;FoXb>b;))QuFX$>!xQ2d@BUdp9T1<`$oSM#YxvGjdQle>!$Bl9a3->LemlR zHnoG&&WMm?ZSP=*qY5aU1%CDJ^v+R79Hc|E&^plZL!g(jNp1aSGRFH_2;ka!K+^sJ zK9kG$`F)>O@;5v5<8UTryf27=N6z)Vk#GeGEeib#>UPF>=f;Cr``wnR7VSCgsMQZ3 zNd<_?I=XoVvH9Z2zH()W7Ne~@8_oUFhb65sCfgVS%Ls%kXYjJsj}^3`?Z@J2)*gjG zJ+r(c42(9lj!we6k$1{k`|){7-Eg|JDe}oQEE*iHs*^V;E)f_k^1h)(upG$qM=$l&O7q4>-lsm zTD4#H(A*RggIAbS;eG%~+rxzR1l<-@O+mi51SOX6m$YnXtFYPbk0D?~+wwcoZgcBE z{w$)GwEmyHYe|ybHny~^=dfRRAUoay5DE`8>?L5Jfrnl~Ed@gjy#y_#miF*Dd6EDD z5Nvhds#~2@r~u|aPm`5d%&xvRv=!KFH3SR+L*T0+fG#s2@49dFOK6;QozggGTWq@f ze$^obXCX8lu?=l!U>VO4Fa!(%L*QWucz8y|Y--?ASSWc>w$ZLDceceRHy);IzuQuc zh3du+qtxmLkmLiDWF0*`gV=m=WNV{A(r_bMjJCmtbYw9!R57SkQSHPKFa!(%L*S_p zm=0~1BE3=Sj$J)74ZC{qM%ljKYa>XpOs#$Z*{2L^WgQG{8Q*LpemS(A36m#Uj22)V z=y$3tY-nvk)}TNm zE2Z%n0=5_ofi40~-`4bvU6q!2)^(z9&1$@F`hI7w;v+0OG zVrYBCuRfi=qIJk|l*Jx5z;s;H+L31zL*Nf1;Qz3N_ZnEb{@-id^bCP-j(~^9`q@ah z5{KRt)5@Jq@}Y}|huW_VZ4)ej5eS_uOLhLlhOrF+L%6t-}A52+Ba=K z`QkM50|a~-er!LuEbvq5QiF_N2U->R-#lxyfApE-HhpCEFOlv0-To&0rBy6bs~F>3YV;L~QYWOSpoHF1+N1PlQ~zz}#00_TsB zPU2$yigMUHsGut8Gb^pT^4ujrG;7KUXy;3|yw~ankPNx>viba4Uh1b|VaGYyO1X?; z7qkw)LB?s=D2tOY3fnJ9nb0dCkQ%pi^~P2!U5l}C3~@<~Bd-5=c5?hH@k4rPv||J5 zA~iLx(p3I4iTU_{-*3oHcQ-{6A0M!+TKxc$0m;axWb-G0*rEEkZ30Q$)8oHcB3S}# zry5B>qK)3m+gOdyA&VuWf!3D9P3Scc=>Nw5-!CM0&$54xuK_nFv~QWgf0`?uWl|RF z`^}GqvQUyfJ(AOSP-_rCl97z^`W6ZIM2$xsNTHp*X1~c&GPHc`qfJUTXzuBWCRuhzn_DvO_k_S-Lyoq2FoQ=sD~S~SBKd>ME3{K3NXL&pFY$$&T$vNK_PbnXlWIJQ z<(*bPfFz2TN<@hu&vF_7GVA0e)!A}L_;Nm7frC7miXF-xpJNtNW5T30A=vu*2;j~7 zj!fTOda{14Ekz^Ow_;yNoSQU$Z$)hN6_!=2A3!oEWl>i401W_3u9?w&NgP6Lv;sy; zm-@eC`?e%yLWY1LUUs81PlQ~zz}#S0s-Fp zrH8d~7NeFP2eG<>`kgZCNC2_%ONSKPDIc~T6lysT>HsoP%A%}!*cCYeDhT9~Usmi( zT8tK29ubi43PI>#4;E?-_(nDa3;{#H5O@Lv%5Pf4(vxduK=HZon--f#ol1o(BOU>rNoNDz0ND2X3h$)^y z%Y(r;6r9f%Hrm@2EeDg-uJJi!F^fQXw5BB6y*dKT%(9+(x~1$MCC)^3K9$(E2# zhqfU}pB|%e=UdTKZ_7j5aOyJ&v_soVTDN2&9TMIs3w?tr^4-^4mukeXjDWuXe`^%n zw{{4B@ALaUt+N!ZjGiI%W%+W!;Sy>3#wA!#6#jSAb)s+0w%Ahk{e~rn6lyx+Q2robzn{CwEOv-qMfFWQA7y=JPAi(>FlpY6T zIix#78Ivdg*%`a@IwIFLE zhJYbp2p9qnLZF^mhArecFydUQCB8`g9v_U>+HP~%n0`HeeQ2v69IJ6BC>2$TB?G&C@WqKrrUhD95po>Ckp9)z28(u6Z7fJKu`BOhwZfNL=lkwrdcZlp$aU7y^dC2O!{J1D#gW zH!e9i>pIc5W?Sfpx2^9tEIFi5(-EHzZKI;6a^0ZX(3Zg1#t<+B3;{#nqY(%&*e^Y- zjWf4eOdZ6=m75P;0z@0XbVxzSbr%mRwHyd_0GSAq7S*OwBalme`D<2}v=}Y4Jc1_O z6@t*g9xT)v@QrK;7y^cXA@BqU)HBOw?79@6N1aL&mXI}?ndy6mwo9I4<;*qoH<2C$ zkl2XnY-lT%=4(5&ol6V%;?P#q=Bo{D=lHxR*CQ|VT6O2R)PRYFXsFhXw@N--S<Iz+j`vD}WP(&rBcm^#GMhQesf!tlB;g;~%v>a?vyT(V2lq`JL z^?^uh2aXY57J=!|)-R>~DMQ<(i}4eNwpaXa+Z_O1(Ygt!0a~Lh^fnfa&PrbaCY(>pJ3JFJ{?|hwAm#emNO?TVaxjMlMI;J22#zZ^Kdl9bHh%d8jDnEsE*?~B zIS}dqG7%)nZ1nK#l3yFz0&iOk0YktLFa+iZeAv+T_cUP%+1b+$ZO^}HI|oa+HnbHa zY<&y@9&YR5X(&`SpAhOUUa8G9m!<)Za*nbdyV@^XRBouy+qgnh;eG%~Dil#0+5!h# zzGnocL)*2)K4oaTAw$3rFa!*Nk3hh|Nd4s1UonkN z*oL+zpf&wFpVA-b+VY=RjO=hOViJacAz%m?0*^)@Ab{rC5o#}}^B_?yqL72&xN@_O z1c)|%`2Qdr6DY0t}C!Nq2=1K%Xzvnu{6N5HJJ` z0Yl)C2-wiJd~5L1zfNmI+ecoq=3D<38hR~sd!azH)PQ+~vDTIWsZ#;ndJt>B?4h|) z-OkPxnhN&=NK&DQN=)&r+oGx|$afcMxaFbJnwEntYS$kS)JVy~cU>Qdw07Va;dK${ zUcC51ieE}wFSq8~?g8q%56HUh`{gyr%`^mEOa$eve@AY!QSF}M5Dbp0`;Fr@te>2qH|u#-QiYAg}c&5+Znb%J3sN# z?EC$dk}DgrOs#$Z*_34Tvlw=p%iB5-;ZE1U8|up6f{|$D@8ZNalKfU8^g|ZY7=%e{ zLa@~kxPU+$+CKa7pJxxy;xh!65csi3IS8W|qM8U5%>ELTTx)wUSd3FSmZR?%jqJ7s zk(;itOs#&~n@vc4l$9RpKrZ>+P_Jog8tm3a>mlCKB@0A0H>$bM<&0|x7y^cXA@D#1 z@MawlLS1^+;zF^A!i{!ad$Tc+4$p_6>DN4p6e_1`^#e%aF1^IV<=6C5*SJ9X!sbx1 z7jzEKtp`uUqA6stWYjN7nUEpSN8tB9`KhS!o3?fs0^dIZcck!_vc8oiuqc8(Tkx&F zDAH&jzEQVrAn9Kyt^IEL^}m@%;oY#IRzH9wB^k-OZT&AR!s2|nk&WEqiygZ z9a+q5DUVu8vfb+=(Da#A=jfNxXU90|J9j;wZu@@ucEQaw1ejCdD*P?%lz%Gw9SK@> zAZlu-+io2RzU-E?r1zzED9S=tBPEL+t`O`ku17T5iz86aESst4Qtl47%CZrHp9^^bxS3Z66n-8Ui1V0N(f=4A*@l`pUV}pzK=P zgTZ2)%CQ`MzjUaAqR?AmnOa*vfTSu7r>t9m!8#BR>U?2FuE_bhIJj-JqSewR3woJZ z*W71P#`{VL;F5ko%8$Al-{<#zS|_lE6TY#(E&{mV^y)H*tG`6)wNegd61 z-fm!WaQRjU5s}y;o-B3fK394zxB} z(Q4_E1-%?B?Fd9{N3*RVUz5o-2$fT{ z`T-<)mtNxG@@smjYg{0GVRNY13p)HIEl=SZAEhG;%FQ;aHIp))Az%m?0*1gt5xB#9 ze`vcD+NTU{mptDf#lhuUAq14McMNSW`Q^~|k`|*q8QLxxz4+baHJc{&^awP4X5Be1 zMbD0L)OYTBKHc{H;(lB58--v_wd(N0&Q8;mN6x54-6;*Wj&#r6!UoYg5e?XkvJkoH z>ZV*{z9s@Tv@N&qrSU7@s4i)3Azwl^w0+Gx>HEyezG?e?{@g6;?+}5eZ>#&prF?=) z)!H5mea^fIiQTP(3^dWmf_S>r9dQ)z2axPYeUufI?-0nT&m_Q%+>$ti+GzcNE?F$u zzKGb8O%pN%3;{#H5cpsOn&&i4?Ok%l(j(7@9MtO4mx&-9eyJaRJv0}W=AqW1a?;zj zIhd4{6|(_g$@8INU(xauuJKViz@Xf0qgpd5;~4^d1b*+6pNeYVw0)`{hXwOq1ny9@ zq3s0(ZM#z-0;x$kv}Uu&lZGTkb%arKECkC3nTbe;A6y6kj!Q)I2-3oNTvKY*k! z8T~gKOSehvP&pL*NIO6KWpJ{OFg{ zEc#hI)sJ*QJ5_>o;K@terSgWO>vy@%!bq{KT7v+RG-A@qlqzL9>OeB--$}`F5|*+k z>vk_Dnm|B2S(p)EI}r!FjrKO6OBPF3nfsEo2^j*0fFWQAJOqLM1K(XMdmfcOxkCR5 z?EqEn{Wc-R2U3OUAp=c^)5QgrRjVIBvL+eHI(p*0=Y=&-5%24SlpDVQ!tS@=tB&lA6j% zZ`D%hQaV@5^ zu5gh;WN^#fARoWboqH|5gbldmKW|Ny~2r#F@{Q!~;2SaGe;~BK- zK-3iEdy6MAl--h+B(K`_2Lv@zve@BDf5(klJMxV3st8Pnwo4bzozTd%@dJjooRK)h0^JTSQ}6t>aJ6M+cAj;(P{fdXgczjHcdx73Lx3aG1)h5mtZxa?;8RAAo{KI zaNpV?{Jqcb`?Std)DPijlE(jH2sq?hKO6Cd8o-<{D0xxnymIr?nuE>SZvd5Lljq${ zQ`JWSBwY^!vf9uVfY@RP7y^cXA@KPKeB99Xmo#B_pM^lvXI9U6!je;1NV1i-4Q(6vnvW1IKK%Ru7rXb&2Jc*&~mb4^!)kZ9XEOxlk z-*KbXjy$8hECSt&_tLaquh{^U#y8K&P2&Y-ZiLWZi#Zhz5NiTR)C0*wwgNzi;0>1c z&1X$ZJ_l3V!TcZ##dQ!yCezwX$at@Xfc$PC8n>UyciW_MUdr`1N;TSOAl>FD@vH3m ze)ZQ5MQ*x^<%M5Xl#Bwe@}@&&=Q{ORn2tBpB`x5e90mUr?!9+k?USwrxT>JRgFl7GpI!*}<}E^#e#2q;HUQ3$WV&0P1{UMs6-w zbK7V=*eyMNT3tUh_jMhUGz0{JUu5&VtG{wTJZ~Bn*_TJ)tsoF^K{wyFTY?AQ`iruS zcKcnlD8aAq_5I$L98w71S5vKi07?FqUgB}fuj!@#Wks@Q8-7ntV4De(cZjye=T1Rn z!SmThwPsSrdo={=4lN+P(mAd*VC)!2edn&m>9*_F3%cA0p}!V$DjXozX?zbP(W(Lw zBJ2znHrn`C`_{Ci_ocRj`9T(n>mZCwrnQ-n@m>po{_s>roJ+a>MkyQG5{k~oZ7x$e zX0@Sh2PGqYQv_^i`%U3CXI~ltG_B~gJg`7}hQ4wRkR#h;S9P6ioD)-Q4B^{<;X@f|E<6u7OLi1eL0_Js7NSHndHMurfFJkS-6d0N;F3t+||W z4S^m4zx0UDMe~nq9-a#bi{?8=;H|_Ta6#8o&#;u-rwna(6?z=RVGLS_uOng|*4}8X zKeWB#ciRNED_VC(a5A)As-tR+W^MBY5Wp3OYa}4!(mF3)IGbLxwf5#G%{2&X(br41-)7nhPc&~+k z4Q=rbap^m=yrC{>Z7yFsHne@MTgb981PlQ~U;zO%t?0BoG*C^@SI*5ivORXtZrbj| z)TX=dmkw1BHhW6|ky;*vI)F@+`Y0P15E)T8%-+WQ6xtwtg0YktLFa#cmz+3Sx)5m7&xfIx^3~iS@f5OoA zieDYtUeUT!_+)5Hx!Fdo&7_R?Y6#R1ZvxWeGoFQXwFhpr9hA{Jr!(Dl{d#DuF2$T` z1t>P1f1(~p9yHrI=HO+N#XJabHI^lD6M6*%Y-qdr{ByiCe&rk0 zB`w^hHne?(8|OuG2)vY^HzE7;$j|$;vB<62?is2y%gwO( zN^2fJSi&;3JO~JX-@r;nvNjDW|Dq!-OqW3Jl?GL`7;S?O>7M2nHq=^>H4#I=5HJJ` zfd?UgH){v?b?se>DX3Jf?ZIGuv!QK5ge^dW59!i~0KWO6T5~z$8Uj58e(4dPi{|mR z@?23_G={)c1m225zy)nX+Z6!q&m*s(WHO(KK>hG0z|)oI9NGgn+78BcHBPr(zaAQ^ zOEITf0g6rMpQs0thin}Pi1S6CLtSc7kvz2>yo|D#2LUdvElHcuOCVrF+s)@65EWZ7zGVp>2l2UY-JhEA{z70lNqJHMfSq$0AVoZ63x^O_uINS9F3tC9b>9$l#$Z zW#2Cysvvcbn*b8EJP36FnV3mY5UdTAkH2b(R`Zfy`}4@a+m`PZfzu0~H`ljLF^EHM zgkY;7@LeK+d&wdAx&|&~6jZ9#_F%BSX*oVTAA;uTt*^e)?od?w0VGj*ZX@d!5;YzT z0EKw+%8cBJV8w2u_29O28`@T|*@+=w2p9q{fWTYH!G^Y|(@Q^68`>_xWI~^Yz>hwg zcIY?%RJzo^hINNQKeE=^9{uMJj>bH@%f8?LQgUen%c|86AlZ_P{w;xV3X5{|oe z?&33t&x>|)vu$X#Jf!OYGO>`fHP{?vYXCr;F1v>MO2h$18AEApwnE=o@(^5FXl+T_ zgkAxG*tofvM{2d=wU`>mboIo>(Z^-!D1C3zYP3@WnQoQXxZ?8MT)y7Zb=LR$@9c4R zQ{?mE3oKJ>5J1wGjQ*8QLi|5^ECN_;Yb^t7sFg#^;d5lF_2IBx*u0gg`1#>G;v-MIN!l z%CLGA{hoHL1nEe14F@-|;Pm`1*V$qZmQ||>9|2_Hl2Je)alx~kCJ^P1cTQP=O$n2o z;P8X!*Z3T>nAlPlttrWNFOGn`S^v?}lVQ36ER>+8^d%-pQXmf{5A_Fj&Xzj_sC5IO z4j>aj+GH*5!66VBm@jv-0UOU}8_{C44L+pbW>#7rwOWRq8v=%aAz%nR4+80lQ9RHQ zhkOznW~?iVr%=ES+774M`)xvs52OmS@w;ocp*&q+nOXtTO#q218Oa(O_j1&MfOxVn zqxBCG(PA5|gO`>bKwnyz`;xQ?83KlYAz%nR1OdERdpNI4k6Q|frDsqNL4NE+<> zr9%~@MrQ-d)EWekG^H%c+SWdwg!TcJ^ZqL{@`WGzVhy#8RDo$Az8XLe!; z7y^cXA@Gz4xXtCb@F!BrZ(78UeSSUKUn$yX<4?8dZ(3~I&m!CR8?Jp&gJsp~2atS9 zMxG_C{H8@r-{qM2H)8VH{N*S17nih3#SdG6^%|c;7V{XuRclM)CiEf*;4*ed2N&d( z+lM#8pzoBPFM0R@Zuo@Afl&Mgve!1n+)k?w-|wt6O}Vzi4FEfp;Z_@MHtJYm$uDQlm$Vq|$$wcJc+sVl8?UMrK%+++LnA6KvKvV{SRC7^jWtYbs!*~EX?TA zodqrC=-{QLhZFA=o7O6-ofra!fFWQAJQV_Xv-Sw;50xHy+%&G-fw}knI`Wq`hi6H3 z_+e*6%A%}orS?17(=B_E_h>mWAFvr^A#&5zO}WN21PlQ~zz}!}1e%#;J@xcUA^uvV z{x^PEJN_3BAOA~7J(SF(pYv;c>HF2eB|kihLT|k~wEa(vjfJv5v|aN{DGY6S-iuOb z673d1sqxX=0prq#)tDRbRtBtnn@&`mDPi+smQ5FL;HJR3GvYov$0s+@~e`vdu`5UEf*wr)B zJNXxewmY5iRxERHd4p^nKqkttR@TAL76#_aooxH2EupZDAz%m?0*1gCfx2%C5ZtxB zV^wfGB?5Nc_BZn!B-kvY!waBaY0aZb-4RdQUdc$-&BJ940Ej0G{OVVVPUH)_jn+Y{ zr3cWLmWzlj*)$j9Y^vxBjn=y@N2p9r} zfFbZ42=s@ie)H?${Yudf9NN<6Y$Ib(e!S}kkW5HMo+Ye5w4J#l&%S9(C~Wf>1ey-5 z>KxrtNW2l+Cqy3V=v>p8Zo7U1G&XL8&|izWop2R?yjS&TnsV*et3Y<9RQ0gaM%!gx zI7oB}NS@jrQiCjZxOUAIBCSnijP+s&%!js17tR|YxnWn&Oz-4h7}_pfjAHo%hqjme z@|(7ov>5HlH*LcXxAB(N#v;Zs1PlQ~zz}#e0(IXO5YAGSg{&{@?}M(BjdK!n=_Mb1 zzx<3UV)M1`h=&0rBRM1crtKV0XzwbwkZfohu@NwUkBg*o0LC3|!a1()NHU5cU8i#w*QI4Tb3{z+Ad*iLQjc6)1g(*c-&INyb<{9so!`fWBOUS>oJJimDVOQ#(FUX=0n@1 zWZx)t!|nrywzN6h+`;7F@&-a3KqksJY-P1?+5#(E3;{#H5HJKjAA!1W3vjsBo)uwV zmfr_mCmZJ^=F&?(`hG8tQRY7|y_3oJYG`T-=iJhzdRJwOA%6~FPRG(2C?a?sfVHlr+-IuBYC ztF{^fhJYbp2s|GGHniPb{;6F0*J)W?FKOAoY5RQF|MwbE)1l#lEd5!zpwBXcg(OyK zvx7wEngn#)^&65*IzoOueJSR4!uS05WF${*5B?yF z9j=X`{VA>OiMD@n1OoD_E?&9+mM$Ez5DhsP8{Rw~0)v}|A3$|Oh293{^vZRRssqTx z0|{CIDkWDn1#)+3-+b1zJZw?BekV~QE(->TpDeU?B4_LuLO^~ua0@x9=C}Qp68)J{ zjW!xc{E3(>^$(Hl`}Irj6JjG4(0t*mRzH9wFP{Y*ukz*}@Bjd`J=^>y%y30ZqTM{y zYkUq_h?D8+X>BTI%ojlb#plDa`TfHzeV(B>w6((!`2G>_NC7pd=^I&@W{INHiz1CS zDyQ2ivzU4iYrpc*m>)!Us-3L^jqgDH0FqRIsI2th!9XCI4CuYZk@y}hM%&;+Io`;wN2Eo#>vOw_f@f&t9h-|t3;6rA~XU{b3Ie`h2>RMyeZcBcZ3&f-V|Y?rhcEwscM>BvIp zbk^NatIIXw7ev56F6T#GjqmgOKCKgU_3iLP(AZxN0bFqPvyt6*bj|^B6!F;gD|ce* zLzlkarK$xl`fE?r@?g~gWFknKnS*Q{2#E6~kbULO5-mnMY7IQiFKlRSLDobJfffN9 z+O~+;xgqdL2sAUxdg|#`oXYew%GTO=#17hPLJ7cG$xDPxUtuy`*JBTY=41L%bbx5SEd7Y)CX8zc7y^cXA@JD<;LX~Gwikd7 zl+{Lqq~S)i*l_fF6aB*S(9)hkYkQ*Y4FN;I5HJLu3xVm-b}7_P8QLy+-bUk2OlI#p zD>AH=buhHuX-u~5&~_raW3|!V!E5OaEvkn}YS;K2vzUcI9<7mL zo0mtxhPF1eeff*r5*#A%`;hZI4Ev_-^ZYCKBQ~2Oh4ldwZm8OabhL%_aidxntl4S^3rz=pO3$lDb>ZD@N1EtCCt1OiN= z*K#;T=ZLfE5|rz(t@}=|0=f+#)_%2zR-MVt7oKW42-g8*;(;`3QDI`Xu+iSGw5T2? zsa=0CIc6~nfjn9x#WpXGfDLVJX#4UPxg|J8;6i;K8~I$$mFGvF8;Myr1pWX59=hnX zn!a)APQ<<7_!ZFrn|1q}iEJr7WNN=Uw51^Ax{CvqVK(9KjD#%ur>(5%q;62<$@xwt zYjj^6sR;j)7NdohSR)--2%XNl8)|jAMl=NG2rON?a}%G>C2#1OdER_e;-G z1ddW3ySjn~@>z}}rSJFJtuL0T<>9IhAQM57qB{D<0}RZUK=zfUTeKMMs5S63zp$aT z1z8g@1PlQ~zz}#40^e?E8)AlcX4&`qM*h-f^c~gao3^Q{$v13ewQt%kA#6g=iNK#q zr}o#7!}FLz{@~W5b$lk$X#Z3i;ULd`qRIc#Y~Sy{$Y0rrWoq>U$fhKte~Mv;cDW8j zxYISTF$HW>X<Qv+YYGkQ%pi^~P4q$0aq6>FSA%VRknqc#QJ`3Nlf(8ety96ElFjq zegKL6mR{nK*L&LKun&PG&gqf;CQJ8I(Vf6P+C-K-_w;=hJJs>_Hf9;;g%L;vDjl&J zrQ@$5FR3!D9z{P(H`=ihqytZ0(iV4e+;#o>By-^?mc45914w*iQNd(n!+iqE*EqPLZ zz&u-ES+)8BBr|u|l9fHc4GaK)v-zSKy+cc*1sJ0&<}rY))|SLg$Ph3D3;{#n5eNi0 zMMvy#s;w*tljSG!9Cpw~@8-#m9k}cRHjUq1yDgHF)q_VZ2SOb{CQ3%K$^*9mmGzGV zsoj?2Jz9*m!H0Aw)>l?)tq7ZpAz%m?0*1h25Wt%?DrP_sC?c$lv)DYD0lTJxvc7Gb zqio+V9jYKTIvZG~R)9F3qc`2InOT03kZbM!YYw!qrZ_v=vlXmP%QW!35j zkc>!1Ke2@6-?T^{wsTAZz}z9Yzlzi)Es1t>MZLl2kcBvzu1>5?rHuJ%2;eft{p69} zmD`6m0&e{{j4W1~#yb)N%*Unc*C~Hx7mARhtjDenAQKNH2iZCh5a$aUZGFNvSIFD| z8EV(~IIuUuNWyGGYcnC^y%qvDq|+VRhNWEpPO1LP^o{%rLtETrJJrq>mUVF14z@XNL}+D+S?EP8KhV2t%m%kk)$ z6^k)cPZn6FR)Bm{!V^_8l6CWttpNb>WMM{2pFYJ{8?6JQr3X=1S(*Eau*nz#hJYbp z2s{RXW@cGWJ=bbU8QO+ewQB8VD4FsLtPOp?4yBK!a1M%$K}Bm2Kr)htw*MDb7Rv6> z*3TV+`>RO#66l(iM7z17-r&RBB@1RH-g>JOYdxmXUKWA6L-WXU>5_pgZ-jCUM=G?N z#yc_sRN~V0>y*E;3q{CL)?-%(kckJ9gKQlLi1USwwmxB-D`akf47F=~9M~ISBw@Cp zwV9CdUJHR6(&-Lu*HZnIq3x3Ew;~nzzVXM0wpaW{S^K8#5@04|2p9r}z!yg#Ab)gP z4yP<%IG-*0`M1%=$5_8p<|o?#V&fN$>`r60^26}=z@pZHV+2FM5HJJ`fu}(LZ`Sp*kqxDXwQ&}%Co^EzR8ZEp3qxB+ zqq9w0R0D*Y01{P-sjQoaYz=?|b-pkoz;;QCpo-Qg3woIaLu)f3;~4^mfFWQAJQjie z@KnB+x)hsz({>4_SnqSC=a@BYAu9@9MOD-%LD^9Av9Ngb3bXVWW+q?V47AHEP!%Ow@=k zf{H5?y9=##xkh|R1a8QxKeS!Ca6V;dyL2(WmEZ%z{NqF0D}JMQz;;DTqdobit;3II zx~R3Om@y3jL%oX-|?dcSO2qm2&R@08he2M`;-{B*a|8E-vU z)N&voe0q!IMDpP{pt9xV5D1UUhTL)5x@mkKN~3z zJa>PEVup+-Gho+LP}Vms$D=PAusk{%oo!&5S^>gM0Er3`*Udw=2Ec(jUzibKyQIZv zMQfA=z0884wV9Cd3;{#H5HJKDi@=8sZ9}YDANNh$HBd(5PRyLc7HDVjo3@mnZhjT6 zXU!JMWR++)SA--yp`+{*#)&CqIkBcB+kF89>JH5#<8leDHDKDy)!H_+tuLQ|Q)$;5 zd>o~H*(t8%bT+is;Th>g5x60*{?K+Q=}#HjE_r?{Qi0d^A0OIY@f&6Bo3=}UnUEo1 z2p9ri9D#uR(P=rHvV7ruw%}RnFZz@i+UT(TPMJ-20I~7QPj@?=@z#SyEeAp!Kqe-V zk1t@^&=yeHVh9)lhJYdP4G=(~>JM!}ormGc4%jsnl=V%^@#)Z3jnaB&1IuS6JZZ{v z8(B9Gdo=(;1#_@4BLH+si_tn*A7#NFVh}|p)7nhPc!q!>Uf@q(5lui7;}>bhj%)XQY2)+R#6 zdNBl=#;yK$HI{M>T9RvRX&`rhT*dR!?EBS!;A6?P{30c8{WROj+othPwm{l`6T@wX zx;f#TuRn{3yP_r0%I(|Wqq!psaWY*m{oSCcC1ZX?1b%t`q&;u%=a1DQGz7*7^v6D~ zD1@=zj&ss=O5>b0c;EE>dYV^QzTtd$XQ{wydN1(-ptl7GU*?mWK|1?PHV$ zAfkA8qt?1?BN_sRfFWQAJOctAL7-eTHE=0H6pJX^Xg8%V8RI8gpU&b@`z;?#3uocg zLFS}{C#e8YSw|1gAU0nd*-KRx(xSy^8+=G#sxN-%roBdG9_;1?U zVF+N0u5eu@DW_+HC_I1+@JW zt=cbpXl|m?_<%VT?gx+zcv#V%pxdIVDaiMhpu`gXl9nW|+K6S4g;Ot+om!g+8SBLm z=nqe2#JQ5J4Q*FYiZV8|T?ER+z8wO;d^=a~_2ieDhxb}HJwxDIA%OlYz+c@r`lTpN zx=v}Fvn}2?eZT6Eg0m2sj+l?B9h7!Pgd}VG1Unp6Kpzn*-q%6^_tpcF_7CuxT)xlm`?Qk3*`aTTGb!VJK?FQm)3wp6uf&tXTcegH`-KvdSz!!wA@7f1G$J4>_}ZQa>u?w8&yX^k=2#t>LW zAY8eEm#u!Rpbc$57EiPGC* zWkXwq&31nb0UO$u-;s8kTLqqihJYdPPz2Cr1_V*}jeaS# zlde-5=WL5jci*o%q~I)srX#kY?F=mA83KlYAz%nR3;_?%sF+O+TnY;%FUmIBb>+^s z_~gdJbnSOrshh)hK4EzwJNHe z7y^cXAz%nR6#~eL?(l&;M(MTZ;J8j2Xh5HJJ`0Yl)?2zUfgKN|^G!eZ%>$4#Q$sobn1 z9v*7H8;kK$01i^r>X+~&6(B0>=;0Z}=8Gd+8x4|%8_{C44L+nJi=m;4L9L2vCx*Zh z0`^VYC74Xe5cmKD`omL>HWxhHD09cohPH%cw>b=F-wN|UzweYzw>Gprh3FLp9Fjt> zb$G^ep0ikpl8tuL07n6B|3s_y%N{z)E*vnYTKxc$B@c7j)s9+J2u_xuyelm#qE+o0 zpF07y>r5wV~~cUDB4$1qA#B*++?LrF~Qc=GPGT00f%8t?nEBk^|fe zu|2J|<)JY8)@+L{W#6wlq~I)srXwB&kW9Gr;<2XvRyU|2)A;Yq;%u-mqxWce8bywy zEa-&_osC-SFpXpgoFQ;_qxmxfpT_6)&&{W~GQ)+uxn2bZDvsdTA9#;+^*{F_3J_K!YuoILx9 zXa5q}zTfR{!e3g&GPU{vBwLbEKw}zvhR=X!SJ-=byYmv;B_geh`lCVoJ zo6oQ1rG6R~cAS%~l*=e~LF@1kjKii;7AIj8wqKGmp;tm6HE!wZjjdL?7GvWW;*uIi zT>tUx#yq%79=n;#2hp(K5JB&YG9)*yf+BN^rOEfVgD8jm`VLOXlSev_qS zX!+Pjo0M+Q+|v_HvH*L&TzQZ-w`AP!34y> z$1JACgh^{cu=Vv3z?=0QnZCR9Wc^xOibk$)#lDa@H);IdirDHaEUQ*OfMia}qO9xz z8UU7DGo$;GIE3101&o$1^?%9sZAr?63;{#H5HJKDihzT6d?-Z+>953;A0lOiMjM^v zuJ_y6TsnBD{RU7M7g$!UegMguPcQNC`8B;DYzG1Y!P$J#jNYLYXuHNo>Bxd|vyE!a zq>N_>7y^cXA@EQH0=)N24{PHrMlC%KVs!=eJ7w090Ak~p4k@@(K5RWG)N&xy0c4_- zMOpK(D{=x<5XdFJtk{>d7%j9sA|Txrg3!SpEYuqCjcf=Q0)~Jg@B|2y-?WIOC)dn? z;&b6QEjEujl?qqL8TJ3dO=3CLhQ8n5vi|Z5euslvg8-5}$>>)x?l+&ebs)l>um2D> zV3X7NifH9GEjAbbOUEdS%shLcwKGBEzY+o-$>4rEJmWdfRV+lwMjQ9DQyaSVAl81D zn$3eb)#?Y36ausmQ#^x~2ZL`YIG-(Sw6`l-4koEx<8#Pj7J>3;O-Z(Ubp)E3Wj*zD zOWET$e4=cv-3%p@Eg_u_Z9|eiJx1fsx1y=umWQ_C)MpZChqjlrZplJAB)m};`UX?v zyRWw{)remi0e%1f)+o4d?GXOn=l6YDXDM14Jwxcr^5ufVCDQbbOR%6Q{O_piMBkci zv8C+$4NDFw)O5t70Ft~#JN;Ue3AM+J{YaF-R80}{d)ZR z&{jV@W)p*#(YUjj8Yk^c`k!t4RZRKK=WPwZn%{P4yQXz1spUDLk*r^hgZ7 z*5T>MdER0nN;cZ%e#Xt44Y~Z9UOaZSU-r=8o-D5LRjVIBk_tsM-oA2-T2$drRyNx5 zP-!BoEQc+%YkUq_sOD@(YcnC^y%qw~q3v3#pE0yu^E?`Nz7=(uil#G=xY{>u*B~}2 zL%K)}HUI<2N}Tyk*Mb)s+0w$Kr8TiS@p)0MM_%Z)>dtYg z0TT<+P^}$rm3+9eq*vYgbQ+J^FPlwniqzoM6}k%d14vS#h)PWH3|bzH5{Q}txw}Zi zE#a?eIoP6hjgJ~BS@^E&1CiDa93#9e0@I<(brVnn zv_@IzZ7dp{mDV~uBN+mQfFWQAJP860ao~*~Z}9#~bm;W#o3P^fG^A=F*GQk!QkO#>X|9A!OrwO_WV+)$yn zafPVD{Q#0wD55sB1rD}+&j?J1wrh!f%FuSn^=RDrRmty-c=3f4zm&FKZq2vd1JrjPkagSl%WIIEX$UZC8fdPNcUy8q$Ted)DA^i=xU^7vBMRDy~Xv2MtgAt>OYay7EccqQCGi-r&e&VIs_xmd)S2kjqTKxdBDaq((G3+*%w{;-Govwj5)Rn&lBhkv= z#ffhu`K?6ghb*Qs2$R-?V5=c;0f9KQefHx&&mN$~X9z4I@MDp35JoXXH4!S9{Us>5 z*7jhq7^iY9N8c|R*=-9VH(g+n~?e_D?QYKT=Ki2Uenez*sYD$L%gL+7Km(a zRCAxp8P^an1PlQ~;DHF>%{m~2y7a8Yg<=tf8|}LGW@8{7o)1COuXz+HR8H0E2av>F zdWnb2uj!?(ae?%O&7op1=p3F~51xocQ^;b;s9%yYAw!^#!0&zXQ&HnLZS61wzJCPn zNZ~JKeJe{~Q3QLo;9GxDq|rWnqi)+k(!Wqz``z^Ge>0E5yJ17EegH{IGLm)M`d?Or z#rbk08{zYOwh=8x+u%bwvY6RY9<`KYyVpmc=`*X&(J!UXj&am??s`7m_Wknhf}3dw zFsH&*_*>X1|5Wxn613_-)YMM5-8vF{*)3^F?@R4al!dNFN)|g@A=q17k7%?PN1&cr zHdD`~+#PO}ZELifp=2^l~TKEDdu0;8NyS6Z7&8PgExBVa?@J}yQz1U?)A zyzx62uKPyxm2;;-*|oL@gT*+NV>$YM=}-klp|`>^wYGi$NmUw7S+@X#bs!$p`NE7` zk@ItLaNB4_tEEd8^fI%qxzD7G_ZkTJr8IC!FUfwa(4(%#_xXLF)(K+agm3JxivTV- zxkT#Hvj&S6g+{wBec2dDHndG>)cE)ePA#jJQdUz_MO|7Goh(2X#%TJ&a$J-4|4ldscLBi*Vcv~LYUh=zbfbEhNqdghg zdSo|WXl*WL+}AURJcpKxG z)rPh&es5WNhJYbp2oM2unGS@yZ(N#c1lsC%og4brB<3mG_e+N=NR7^>?ues69sb^k z)JIuS`S{S*74v(QLg~FSBUiY-Cv>2-(TY|}mn`VzU};AnVmq2`4FN;I5HJLu41wl3 zO;ZDxg4LqXXxF7L+u}o)zF)uOkV2@Os?`r5$-DFt50_ulOI_mv=?j}f#a__iFKKxS z*Z3$MSx|1aQLUMj@eBb&zz{G59*V#n-upw_rO-ZQXuIV31}P3M-wGk1jJ;!Md&w_{ zwwJUR?a9z~$>_!JCa>8vsi#Mv=`-ujaVdIsjHAAD*YoMN?-%#mlHVu+E$U8buyv$+?iMzP)`@7qW|W1F`Va@av(uxHJ#74waMMw#~t$tgM&~085?^75j>or*Msr(g6nLW*gO- zNg2-&=p*oZpZru*`=;$v{WvU`_abnIq77{?Ab6uJVB`60BU(1JouOpBB?Ov2vwdo^ zV1pgwsPEkMe7f!X-F3AKo~0>QtvdX$vvKT&M=k13X|Q#qd+ruCNZyHPzy|a~79uxY z-IQz0*F?aEwl=hV%`4loT0!7Dm_vk>JWR$AczOhyzOC*Xm+r)X9AkT0YkOs2w+U(V z#Fq|LP*i(s-4RELegH`|x8%`08~Tu_@u>nRfO9zkE7$bW z0|fkl{!HYh8{wG(wpa{-9s+o?4&c?Lr>AhF>Alcs*QGBjf@DM6ghq{z&j6(tz{vC2 z#?P3>GXx9)L%@j5V&}0n_Af%<|*X{UA+iZES)ej)qDlzTGB_UDc(F9V6)7RZ2BR3Unn81NC zc<@JAH0u3RTI;io`hp0=#x2COQmd7&#n?EyxTMB$e=|nX_{e>)OZ-|pHIV66iH)mI z+<1h1y{GG}@7HCgyPG0w4PRhcwfX@heaYy**;u+wVu#uZB(u+6{*?qm{9j;8=ck86 zyZsRVi${acA&XOkNg(z9+1iq{3B3ja0XOI0OFB1X_2&!Oy(QUudby>Sct9I}6YidA z&FjyrhNx`9v!kcpB}UQ@O?>_Z?hFkkMOoh$*ixj49YtU21W zZ}2%}0r~ktYjZK`K6q}b-=5x|@EA1*x! zs6hoyRSCyUHe28Ca-A)9V3}Hj0FtnjMOn9dG0_A9;>p5{0NaT;*lo180bR0KvdY|- zq)o^WFa!(%L*O9@^dI={TG{ic^vMF4?95-t1 z$TNx|U5=Zrgs#*5k{-@6WiJa`{b*HW1-XSC2xSDmJ%Mjl`5_`MVJfK8Gw$EhYh4Taq@R7eS!u zGjSEV3)$^@xkelJGkU&cQn!7-KV0yu=2WX6Kr-smOFR%$+(D}eBnzFqc=7{x3mYWw zDO%%m$bxdSjar*Y8Sk|a=nqdZ+SHqDlJuRtfXfitH!wKj)Zd}vKP&lGWJHrANC(~d z(vCsJOcOvdBEwo)2SZyocL**sLim@onB%RsM!IC7Z!i$-E!65UjrJuG(D(muo&M4r z#wP^zKELnNItkyO@QwX-5x@l}mq^_=uEA1@LWruhc7Xcs!=I4YEPKd6)8TY+X*%Lj z0LfbJg#S;6w``Uh0G2#6BflgLp*GqupbLykw%wAH2^j*0fFWQAJQM*3@Ab10e~HQ^(GWYndXcqj>4O&~>T{_4pN+%0Snt*2;>&mjxS z%{FRnCS|p?| zN&an&C0P?P1PlQ~zz}#40!`mm_l;{YopqhN&wYUw`+gnyOPi)6J{{UdquS8d4XR&q z2q9+l9xW%H0yd*8L~gpeDc6{WfFWQA7y?g$fI}4B(i4_KWa*LTLmq0K%FTx^4l=dh z04mES&%2w$v!s3rPr4okWE~A{86f1l%b{Xl(F!yPtx*>0g&N0=T08QLVh9)lhJYdP zBnS+Kr}Dkjl_>3-wks&5dhfF!$E+tq+cm4SwkB>;uYo|*p;b>u!cvO6Uar#SfE1l; zGN#+UUpAZEOhbS<748R+Y&aM~Qy$NtRR^M`Am3X&iJ|P4v?O`eu0J5Ck&?v@SNc0{ z)Y_3}lvhPyI<#H7aPEXgri~vkwDmMP+lsxD=CytFT~n_@=$l3^4pF{Jcv%)FGACi zzqDyO;!yy}R*uQOX}big34PxP=m*hnorn9@4&m>8e&45cmZE+LKa({67el}y-}>2z zFVq0$d_l>JLg$s6pVk~~)_w!1ESo&8PjdwFMDWirXj$b3iks@HXICT z+YhZe5H$t)-r`9NWw)dy$*VSE8Dz1;mHv(!wRYqg{#wkbaDZ47K%yQ<92A?*Ig+QVRt*wchlp(N3An;P&Q=e-eziDfSA@BkSl>V&!)P-A+m1&l! zBhzCC?fNrg=IN)kzF#!5+pa#-`f(FLqLv4t4j>cdO+{9Er~`4ZFkJ$<0LYOr*#z(y zZG#W#9)gGrXM=@W1HO?B0YktLFa(|e0lZl|gi@EDrTBtM)!H5m*0*gF(&70KG_@G3 z(a8>$RjVIBvLJnftXqKH1^`g!3o~+axtiNX>%ng6@zd)1p}DW?n4}>f2>c?O=Ux4k z`{8-hu*kkV0&fL@fD5|$w%rmu_|{*PZM56(qD2XQeXsBLzT}WX_`aHI^#e%qxAYQ^ zTYgP1{Vyw$J=^emast~-n7l)@H9mI=A`70+HmWs~GTy5pP6OlLtpQ`lIO;oh zHBPr(zh2PgMhN}2m{Z{Zu}6;>8L)&i(w>kUL2%u?2r{#eK z+B5W(bATM#9=odRWaFHe+I08*(xD2%W^V}~Qp(tRNa9qhqEtpVT2Uk?G?TMtP5QCH*p{Ju}?1Xg##H}=;>02iEGB6SU1f+eU_ zt?j{JeY2r$LWGsM!H0Bta0U40i)zi~jB5z=5cs7>d@h=QT=Vc;Kv*>2IRbAb{(uX* zo_dC*#+7lYyF|^6~EgiuwBu*GlG+$?NS|8Ycy+{FMt59 zI9wwE8JE_1>B8Ccnys}r2V=V$r`xVy4~>l*A@tW`PK5)+n$AB_4(lHQlv4(110D6WGrGMUz9LdJV71Z-%FcZf^hndJ?2No#ZY+OeVSYu!SYjUiwN z7y=6jplL;?<)MLUg1&NY#*yu@gLcz)C#E*teZO?5g0R_J0*KV|Ak+b5qSQxOQTc3W z3&?CS1PlQ~z!3OE1e)hGbq!qd8&s;+_F%BS+0Zs2!akzGhje*x1^DKRYR%=0YX}$u zhJYdPKm^{3Z<#(eQ_rQqK4oaT(DsVfox&$WTguHgYHcQEyjMe@es~j* z9-r|nq^mt}qwS!K);XQ&w(HkJV|6L!R4YKS>HHJ*K=P2S0|9Zq=%Dmci&}q#*fs|* zqb%k@fUB`AiJQzfU26C!K@ z8hl8XMg;K97uA}}8P^c#A@EC&_*^uPx0UCL%Azp@t|IVO6ap@28``b_Xn!7g1tpXD zLCc`gkAyx8`^F@{~#}oU-?FLNo#Z2lMQV%4EFLA2wbVp4+_{l$gjCI z1U?plx^MF^j%u=WC%U2&^eJ)Obw&mcZ7KVH=}-l!d)x$&sO3SZ1IWZoih^KmsC@iY zOSGDo{Mw&K2Hv)Ow+NhG@VvRcb&5e8aw7y=4T0|x0o+Rt!Phl#DWjlLwYCR?^-at1 z;rS3WPj7wom3D`s+7BR!%5xi8w~(muXaFe0lUHWsP6R7<8?6VorQ6W9g3V400YktL zcmV|7N)9%(MV(&yk=oF92__TzGz5P1*|bBy`KQvQ{xz&S4Em9^*7oQ>e{eMB*TbQ0qKsY5*mlDOx` z-;#)n{{yykdVV0<*sX^w+~9M_;@o1CptU7w6M78XjjgT!RXPUB5Tt$qN>!X0MHn!M()4}m~zzGT1I62hO0gIh(L zXf-~EES8KGttC+tdLaZ-fl9}ZJ}>f!C02&jqv-dvV;#7&M8C%8n8n1FvS>|7wtH~|EqiygZ z{Wi1G@~G7^?A#DA1PlQ~;CT>8PmJP$jyU9#*f3*VSv-XTcF=Y>)!uItQhXp)n2q0E zyA9>(0?X72kZuA11PlQ~ z;2{X$&Dz6xU3%P7NGv^r3d;HxKS$DF-!C1iAT>H0SffTSs9QP#Hh`6RRtu$=c_ znUOF2&=+f{ZM34*(j^OeY3x*|t~#?5L%$Av$UQhw7Se(dw>(f&%& zMjL;sMSs&`+kO_=zTa@|gBmQWRzHB`Q!?@_VdXb1V)`z}#J>@f&*m>bvA?*aRVsei z0<72g9I}|l0IphF5;vh2K>(MrLpr!1uiQSo5e9vy^nA&~4{*aLL=J@FH;}!yDdu)s zb@+Z~rD@8w9c}>FsSLN;XuF|Ihk@j&?IAPDqGRGnqO~K-D6fh@z;)gq+UiX<$^VVK z8+P@~^iKYTq3zP!hFIp{@&;FR0GTMmT3H7}+e>~qbH1d-XitW=9?8rXTAPa*_v;`K z9+&FU8^$Mu_ddVx(>e*?%IFC|Uzm*x4wpy(61%qd6dPY8ejj$7sOL${rI&p4{Vr84 zG10c2UEBT^P+Z7a3k$)0Z6i@Zn6iTQxdC<~FB zu5QXTrXgSm7y^dCQy|dHEbFPKUkdTpBK5!V%i8h3c=-5VI_jZhCjFdW<4fPK4leoO zQ51UX)uHWwVr(pw{h{reUrJ$U%ky58LX&8>07{LI<_;K_KC}i}6F0Vg1q5&zJLHNB zaOskP3U7o_--*sOiR-rOH^AiTQq1kN>hS%}PScc6pI+_Mx?63uU6(%~B6(_i$c?fX zn5oIMR+H`Ql@SQI&ig~#rOe+bb;GWnncm62Ftpw2jJIN$gUcIa>i{xQhPAQ|hPE&; zU+!evH*E=pZ43cJzz{G5#t77XTY%uM?H#Lv<0%oa>$bm{=ODpm8692#{Yq;dRqBp- z+V)CDvThzOYXCqzS>RW{Qgk9;*ln~9S}i?*zO-CKY{{kx83KlYAz%o6FaphUn!5D3 zC1)%>^0=v~psa6N4bvm%e0X?(Ux(8z$Y#32vZGKPejr`TqCUT=Yn(5#dzGDbvt>rU zFhaxcpSID8R!bKc>7{S3P~D7aJVU?`Fa!*N=Rlx8JoTGj5ARose&EoSHfI|dgYx5D zKY(OHGV&~8{h{s59eMUmTS8%*#~{#jXjSLvmO|o<&^{sZP)FyQ&UD-L8=$dqBZU51 z%0%ViA2_tVm+D@!Z-HUMF1C^Tq1Q1bW6CP;#Da1+jPbw`p>3;{#H5HJLu4S|mv+J5XeZI^JmI<);y9Nw~o+0b?gV-tEx1ey-5 zddB0HBIb?2XHWgcI~mi@%3Z%f9C9Os{#wlKgsbp3ztd`B8nmc8Q#;*utJ5BrS)mo^ zpCfr{dx#CP*x}l@m#MTikulbbAuu1>E+zX$sT+15Ftnx3+2#%=2bVVx>HsoPzF{k? zebW|L*-~ zZ43DJY6utthJYdPZ4qdm)6_N4FU5kA7iDYh0PS7n7Sid^c2lFU(pzBJk=G9(vE{jq ztn2|A0Iv9rPo?4cik5@U7O)v*vDA6cnpm~f5HJJ`0Yl*V5U`=`=JHSF(!Wm2;(AHT z{!QEGyZ*n|h?))!7i8(r$_0Iv87w5RN}C-dI@cti+pgb`WYQ7x>*-4|w-fFMknA+Q zu)3%M*_ld8gF_o_mnFhLt|23NYJ2bpS?q9a4DC;8ZBMlQiz5(_Uv=@y{kL@Ch=pj# z!PxNT@eml?H2eUn8!GfRFsE0pgH#TE(wG%mGzYqfQyMbHCNj1Oix0LA5lxnomK;lotWT}6MY~Qb6dY=#*v4G|aU$y!H zBzgHP;CPic|9}SopzYb_H(`b=S`zK%pYPw9G1>+n(gCBVm)V9|Ga=&{0)~JgUTpDeU?B4_LuLZCl9b-ex;QvI1S{h6r^Z3{p)wB?0jn`c4b z_h$)Y5{C_KC*T- zL))DSG&+kT4X|C(Vzkf_YosF!q0?D+L#-~?h+hx^|G1nVbv3@v@B6e)(ABrY6G3Bt zIRtRQ)z3z@D^EEbG4t5*gR^2Lj@J31nZn zvqX#0j#>jx^9vhVTaYyoL!d>#hPEvtc5VoK5(3T4vYvXn6{j-&jIy=%9oigmUKrX2 z=+2jR3_1uP8IfVFtb?I#m^%cQ8QlsYfIeT^Xzvhj>5|1#9etboH12C65RewG5r@;# zIWAo|Vj*hQ+BUQWm{>ekw(0c;6aD<)vS5Jt$wF%jlk1Z-$qK5mCCtp8Mh6VXdr zHnbJkY&8T70Yl)cA>ffPI<4l>CZ4g*LD6Tajds&^Co62aJ#5x~ZD^Zd0gMh1&6lMg z(cFY_4FN;I5HJKj8v(po*Uv_5Xgh^HkgJUbNyCk3vEk_VCiYF+A%ey*1PlQ~;JZa& zI<#HN>QjccOP;sUxD%7v`_76CYh@h_ZFd@zZ9BA`i0)Wzw0H1Yx(sc1s^jh3m}Q*T zMIa!x=IPOe=Nw`o8gek!Z@eSZL*VdBiLNlvHd5+j<6A8Ug*t#tJdj2$Doo549h9=+ zor#0zu~NJKV4}G@2rezOwj^yrFM)s!ZEa}#5*M;1@h${@f0x#`RkCl|ep|fF+b1F5 zVHcfN(>E?T)n}=VcGGqzV{9osOxJ#OXbbjyabTnU<+w9|PH)?~Q9TS&yZ&Hu%winCjzeoZ znr&Yk0UO%d(DubIaZ7K80IJzcGDc?u#Q8;a}2Xw9pc3q$3NV z(^+>ztuEJyhQJ(wrAv2i;&huQc7F#b`&Zfv5R}4XrK6nusA_2p9r}z=II@c0=0` zGrTj)zTY?Umo}sCs5alUO;t_4VJoYB({>4A6M9Yr{!}`(zlI#1$M5<7;MSvcd?wOp z|5O^`AkTiH$^X)9-|xT3U)hLdYV`xirX-_(ieZO#xei3Q(>1U$1#DAkVM??=dQcjC z4q1rebfvYalraqfL%(2L%+TS{m*`8GR>@4je?VH+BX>CWd?Mow&8n<-y z##YP6B{h!e>WPix@|E-7D8FT`Mmsi;A#zgVipz8RcM?r^&cJW(V0{)^coECg>IaZ5 zNk)H5XDA|07kwuO|$`hIUoO!U%ze!%iANoB2m0EzvUUgDA0d)no&4}m1k z>5=^=OZQXJoxncYM3y}F^nDgP)$#T=W*O&&5l96p9kCjvH{wfX@hGk4gMl|8@> z3;=+$`Jx%ULrbFt7^5uaF@USqmc&iS5HJJ`0Yl&s2n0AqN9=H_tt<$W(svtEw8(5}RfJ_rW zqDonmb@Py|1970v7iI+5E@?4Z(HdnzFSB51Z6;(qL%rnb=alV0N)#?Y3j7Ua5v4rK{v`8Peb4&uj z+#$HXiqs`7iFR{Ey}{>@g*ch6POMF(jQMH^;4;Sj z76Lb<(;eD|rCk3`ss7CLjr}90KlP8HWdXexKj>X`Q8LW%LZ8FUyw;4wr}n5Zd;hBZH#w%eFPz zP1~I;fuzlH<9DfQF(i*2wHyeYwl|S{d;yDp7$-pG%01$tqfe(vm~2Fg(Kh&y?j}YK zENUG%Mlb{n0YktLcp3!oW{rv&5ZC)kPowQ%jP*^+@#vWqi!oGB7FecMfP7QJ6IC*j zb@Py|0RZu2VMa@zKE+rYtplT_2T@pAnfr>c$ru8LfFWQAJO+VgW?4@?*J?=_+J;!Q zYVBqyneq#)4Sl~3rH`d>4vLIHMQad1GLnb3{})#l%I?tC&mDsMt4R40=$e*9ySbv? z;KSS{3uYzWdaDy_J*LrK7J<4$^T>1Ql7TF5gmMi>Dzux%J2C=P;?ni&l)thIMaWUs zV^;@|i3gH{Y#j)Q^M#GJK4F_HWNv^AwQGDF*c)LaVYZ>QnUL{b3xONb=?-nzQvH;n z?UL)aA{F?)@yCa@SNuj<`=;#@U?yY;7y^dC7e^o<++teb~y z4S)l6zAz)ec1eq%iqfoRKAzG6q|k1b_u3f?{lT+ zm^Ex6D+-+-QZf5pvPx@9(kApO2-F>#M_T0)T5G_xm#ekgXFkz%fcdy|{W{@uBZTf6 z3e}P6v8x;3OgxYrWUD}g2;N{}qm7~MnpS`{YS$l3)QB&FiYpYm3$1mzMtn&GZpf-X zv|YMzK4oaTbTPh_-~+?_<3rmkexrB5c1260J^7}s!;faVsI{q>F%1Djzz{G59*IDJ zbCe7B|LlD`k|W8nZIYZv<9$Y<@3kjfF|3Wkh`odmTA;`!U@0Mv$R*5DYH2S%$4_MZ zBS8R#>2{0_BGUhU5}EFmUZ}<)%NLGk3p%}DkE7B?hiy;FY`PtYm0$jJchVVeEm+ht zARv5t^W;FX{tYbsrY)e-<%dJSeO^Yq5?>s`eSYuLTBL^C;X+E;KO+M8z?IKN(gV-a zU!j;GW65;bRTY%=Etlib7Y$e*4UNt=uuLrn;VOVY1&QlnAzK1qK%Fnl2(Vq!Vzi<) z%7R{I!O+@FNO_8YBA^H;0-uY(!-lrbSFOi=({>M((YO;cXLmT-+5Dz0<)@qP!nLf~ zLYb@*?O~FTgeP>AeZn{~m03otWs>fG0tCtq%_8IU5!!3OaxYhE>(I9R_&6L&yI$dA zC~ea&<4R6vLu(zLl73JGZpf=YwB1VjDMQ;W&)<@it*$uwp)OykRqT6 zC;~q@0uK43(=s?@`NHvR!L!s~^HXAIqr*EAKHRC55tn}u&XL4>sv0z%b{&HO6#2sEU!v<(3Iyk zvK|)pN&tik=3rq)0O*nyqcyNT%7Q(_Ac{z)wV9Ce6ahs*5l{p^7XcmGrmx*y8oz#* zb9PBfhO>uB>N>O)7Zknb%n6I1wGT9SO$F7e4mQWhqA zne4K)iIB2hg@CkQ^2>s}g78mYY{k+1gBibxTHT->CUVMuS3`uStHY(@g-Y!zgJ8t+ zqggeK(9H2pT?%uAP1X1ZagdG`0AhN&eig0(Y;rtZC0eL7M+~LRGBwnz+-;K6ZW=8^nX*4~pu;%CgbLmT*880l&mmxM~ z0MUqKBh=pD?3NF zZ8K-5NJ?#ScIx@^RALWRyI zTk9~D^mYj3i{*Ktc?LUb^#ce}4x+O1FSc7Su3RGqI;_|{ zo^3>n(N_47E?~@zkw-03bfXAtBjB!l?zgQzR#1nwkHu51H3)o56d4e5)b|0&t-EZa zwU}9oafszQ3a7p0M&bu{(5^BFOpyF;F|;*7di5G&Qw9*tNaC^%hPGzqGw{VPhqjlr zcup#ONdE{v{Oj5oPCEMj*$9+vE4xcP;4xd_)mld`iTw_(Y@N40IHyQTZE^M`hnlyd z1sBj{yxe5n&JO0Xa6f>cX`#LVAe(}GZ*iHJ!r#)8IZf7n#2L=ka!|VaGz2U@Xfo>K z6{JI3o|6$a`b}Fxq#H#*5l{pafhhuI^JpoHehl3p$=yw(WhhqmXAX22hnNL*zAU;< z9ohoEs(@%2fmu0YyL&=ps`5M2}jML-ewxe@r5(w6~YGt%2a zr_ox>EI(kCVjEs=l=;98+EoUD36kF}hPJRYUxwI}0YoE`k*tHE?c5=_;+I3)OIkc9 z6+WbYY?*@)wXP_s?DG&P+g5g$#RHy|_eN{;>5*L-KJiW7PaE$b_Jy(ryYjhPj+cV7 z4a{Y&egMIQg`E`u5SuP8bJ?C}(r|}pv-Ts-aJDw|tBltnphMd=);hHH_rZK8Tmz;O zia?3LujS!89@#6U@f{P;nBE?NvU#+OH#dYN4L6OJp=jBkInZG|i&1{OS#_QHIWy;! zY?d9&!mk~B>2a!#n2)IqgilwgkYwfecACZ&y0e8DxtUbWYodMZ8Lr*wu_B-dC<2PW z1_D*xW8t{;lT5AU=(xJ|_iHbuXB(Ct`5{Z3R2c*tAT`g2Bq_!_b4Z@Sj#^daq&FSf z5;NT>0w)AqZk12e_uA?=ZQtvB{D9GXOF7Aaki)r;E4emWi+=yP+t%Fg<(_mMW22QzB3K4S&}UYy^V-94hy^cOX_pxUTWDha z&V)n%D*fho6L;|rb6Kk&K(JzAY6Sqqri;s5gr5nM9iq+JB|c3S6H}R$t!0|-J`DjK z+ODD3p{)*W*PjxVm>^&$ymw*cO8YJmX&gTo0%h}PnH^fGtxmboGBi{6XAX22hnNL* zzQB?XsMN07-)Mv_Wz{c2GdrZ<%y-ohj{*oLOn9@oH6IOaulUVRr>|)FAn=0LD2t0{ zSgh)*2wXs5_0hE#Y&}+#pMP#1YhSG?0)jxla-E;)h~#ADrBoHS#j_(fG1;*4wNN>! zG6;$wHP45jDfPMW(I*&?M_JNaE{l$q5Vi&3O8abRboR+1YnPGfHn><>>VR+{S`i6#9vZM*Q0*qq77o?-gY&1WL; zi;dpRk@~Rzl32c6X(Vec$F}irE*i9GTmNk0A&fg2zeeKX?VsdV+EoTY>>ncA_j@p2 zk(;g~Y$SXH5Nrr(1;EswFbx}1z$T38D$)K)df*Bl=6>l6)7sRxG8F+uKoL*`h6v!E z9v_{!lN2lFiPqmXTJ|J|rzyDiiztknli*@|4yV#SXArHNp5XNSx`nHTJ;KI7l4bEY z63K!QmOcO{fzejVrRTemOpjhY1S@|(>}=@_Y0uD^X3qz@|6~Mw`(=Cxp<(i$z0})< zkBe_^onN+Ijh2m{)bQ!?4Vv{!XxswLw^}FTp@ZH2|BtZoufL`xko-%GN3ld&zJElC5N4%)iwu5Y zARI+f6zltCyii>%BWw_U^ac}>(E@;lL$IUYUhT^M&e|^cW|7`Mpv1_!@r3E!S%J`d$HbONDFBre@P{c*O^j2z@83YNN#KL>m z?41xh6jr`t%(Ee+L4YJJMa#>sf zu;mn6ey-Y5%^o36Arl~Sf6pa>`eiogH?bUx@B9i>i99%-XZqh%?H=S>C# z{Jad~S&Z`I4J>(qO1sP;8eltTV6XJ+K;2wM*jVV(TW-#Ub>K$=->{|^0>ROIfnP6l zhnA!55}!=J?+nwdZWIAUKoL*`_7Uh;u0yJW-Lk}TV<67zP!+0v?WOw6SuQ=5lPZH? zgLTA(Bmb)W(jf(tSpVIEOf3TfvOF7+#ATHyd=4rIc{{HDcW zQE?6*n2R={U1bnhhP9#Zm+?kB%eN6WRRF<`WV8Ta=`srZw}@T(2Rsn1{HBFJzb4ul zWg$+cE3HkXl=(6Qa5b3Z5Dk?-$UW&gltv3iy(U-|MsPh#Y zFKOMxxP&*#;^G+=v%0=B0DPg}xl|qTD1czihPQv68~Q!~L2UVg zUoUs%%4(v0>=|B0tpbXGBA^H;0xben-D}EJtI?q}TC5J$t^XmV#~^~Tg4$DD>=Yb` zm0!kt(iv|pSky8glmSGdBrfaV;Ta6f7fUw6=kaVKT8#FwXL#mXd5VA{pa>`e0|d-r zB4;qta|5-K{F@xgJoUQ}>|x`!KRm^VbE}rvB=viku()WmnwcVlz%r~feZP!1|L_qE{ktw~-Wi58Nj-i?3rQmF15;JS{0|-(siTcY|UVQ+B zJ6+jmAG{4s9V1+>0JUWW! zR*IzIrqQw#E&DU+w5q<5(zDH~>qOrgO|Ydju!xodejTWrOVtsN`uYPwfA}ZuMp;m9wsAA2@)Q9@KoL*`RtQveuP#$|r62jVmK0S!)^ae@uf0^C zIm@NTK&-5w_N2^C!GT!$r9%pyl$)&ug<1xLGJr^wvM8%Op>t3{Aea2IVqel?w9vAM zfOL}xLI-=WP;0)OuF!dDS>1t7@ z4)4N6$!cbL&(L=2k<1Y`RRBR=GFkvY)6-2ow4Dl*d2whuGb1h!+=;@m1raWw$#}VeSbs5zoQ3-V1Syw9 zB_@B=1t6P(e0O1^jfYBmS_ZbL{fIN1f9mN*s>IhK;BazBBfYIp%8fDKHMF%e+y;PpeYaj`r#H}h2MGvjW?d?N2Y zzxQda(s;!gUd5pNiwIP8kI#lovSYW*)ml@2aI~Peh*$gHDQZAb7M2J)D~wZ3*@Z@v3%~vc)7{Cot;UvEZh$uNVy~`G5Mn| z0NE7eyGx$-r11B&3~W*R5ob96)YFYriLXV#Ek=4<(cCC?*U*;Q)6G+cwo{M7e8SLH zOix$%%|qL%v@q*vAAE+zjjoD-BA^H;0v8Y{n@2~@y?!i-H(Hiv%Kl6`t*URN^lSr5 zI<%dEV83^Ks z@+yPCWT)UDTKQ$X*(d~iiv^Kd281$zNCasGz$L%@rtKvyMqA-SIX zKoL*`6oD=R2DM9vwq1B4afD4ZH4d_oq(j>=mdbey0%iNi?h+3+?3R;SYc;d1o|}qhW)O%59Q~$k0HVaFK3A4lO*hi~Plc5EDg+!H;oRo4ldh$Fl4k+cT4L1e zfCW1iR&b%F>raT_4VF_Rh4$f~fDFP>-uC@6UT$EczYMUcZaz`Bx}$hn7l19lhSAux z+tQNcsqK=o(6f;%XPDMtOqWkZ;7j`KIehrPOEB^qiE=z$8?CP*UbW!(qb6b;|G8M-%OB<(KhBJFB-LHe~?OjAXO`VC6FM9dA@u{uYcxD}NWq zpWk>Z5jt}h7`I}fwJm8CQUpo_{LuE@U;ldd05!fpIsz66pp>D-^F-9EUv?5~v{)t_ z)M3Wp5XK=UR51IC%j8nqf`JUek&xIdn?Ut1Xfj?GsjIgUHdX%}%t+$09uCG!0E7zW zU|~ik3Alk=Nv@-{VApg3`eiog~E{mR8MwPnLns;nuVT;Adx1RF6L z7;jj5j!L`CAQ}K^^s63r?4`$PifTWAplYBm>j(gd&6lQP&&9!QqAl^UG=eO6JlkZg znUwMrfj$Di_sMTX^+Q{IDFV+#p!$XvzZm!Jiql%lvD*D_GV=jzFb!4roFYA24X(K35GUo#RECnlh7N7RqY2z> z9&(0hZFY*3rw9xX(4p-B7$yHi2w3EbQuc+ZqkCkDBcrovwAjx&NaMzDa0ufN%j#hF z7MF>owgux9sgU?I+&~7JbeIJp&|OB@RQ-3*mBeK|94wXqSWxE+Gcrle&c(s4qZO^1 zEl0g!ZP8_+26u@Ru~cI9T7wWzKeMPM6&-?t?{Pf&-p zpNIWV;(0OBvs*CKgFwe>*PmH_OIAfJ*U^c$rwncR6X?Y8aRYOdB}c@^_R#i{-{Zj0 z_L3H(ee4;Y0j0c`A>iN%9TTrNbhlfd6lue}sdNR3QBUZ1XhrL6z1aG7ilop!9CS}T zU*1B?LI#@5k{j^*%K#f4+VeCT;$Vl(IgemjXuR<_~iCZ1oru)~W@67T>bxG@R z5pj-LA999iE!x&MML-cy1Qda52v~@hZKo%qdjx%MG>;{q#WLZbh%VFMuoTPcVD}c6 ziKVs$;}ofo_^i}G2AXu31tHK~M%YySchHr@Wkuzy1F>B{HIW&a#IdzN_qdK$v}*dD zXSnNAiHd+Cpa>`ea|HU8i`8MS46dbARaE5xRsHCu5u<_ehNVZQjRvx129XGo4s8P( zB|bI+6y9(Wcs$$K8B=+RfFhs>C;}@479+itdg60HSWRO`Uo>sRHrzaAXuIK8ziAsl z;u+pTOog6}fP({cOzbY@R}#1U*IHuKEB8CJ=IO}V4WIEW8t-5!w|~_`BlyknuKi|n zS*r}+os8gF*NM~z;G{C#8geXm8=LwE5C@(A=nR_;$13tN1RgTd`!3w`5z5Y5M{A)} z(*?#In=%L3l2su^KoL*`6oCeTe&sqp(`i&1f+eM?DdjERL9h{{f$@f=M;V2G&$L<}h)qLt8;a*PjppRI_)^+`V&f8rzS6fJG8b(~8y(^m(fJ zQYst5JZi1_wo)vsPu#d1XsK;813T2haMbrphgLME>j;~w{|+`H$(v_G?_jwM#DY3s zh`mX2b}kNX9j$29bouFpUS`&b*i1-yiogH?JD|T4dFw)Wr+_t`eiogJYA8u$HiVer8AISP8|E8_4Y7Ui6*3nmu2PdN> z-*~7)TSB3mh`^uHvxdL9cx2g${$e9x>#fl;`1JY~(L@Vhj!1EMQUl{gTId}w|3jfl zyUZX;{g=r0{pNT@Zn}=Jk?;{fupy)s08@X${HJULHaVWI60JOpJ4$?V?w8ImtxbI^ zQxQ-E6ahtGgn$Jj)>(6sV#Pes`rAh9G%avY=|9EcLzlkcGxZz}_SM4|b_(J%sQ3Ju zz_{`nVN(SVOeWGAfDQMjM@D8toFc%1F<5X$Sx|Adp|zQi@?L{LXurY-%{NTeFR8Z+ z9~a-;8ozA48m)gvweTtN4O%$gzHxJYvHl`D84n%o`C{}E<5%o^P2eLmXjd5o0T(~- zW4}4xAiaEzu&DwFb|j+}085`i;2+`5`TqsBaJ+m;vlAyqPRiX_pxUu~296>iW&` zir9P|VT14`fM5iq6##R8iR-cuV9SKrE=3y}ob;0LMp?{kkwGnRY^ra5l{paffj*&xhBP(yyZ@3X;;;S9k&|ut*O*WiUFIQ=o83aWn<9B_(Io`%i zk1)c7G#x6Miedy5EOdMv`2%GzdwwL_!_slM7@toX{$S8|zXBftGd20mhE27Ky z|5tcB``Ef+oE09lzt8V|T8ohFg0Jj1M8F}Ys_pc@h&aGO4q3y4sf~Kg-nW<%^yD+rn508>SZxzc;mSq4@HIS^&X92*TUrJ$U z%i~^@LX&7YW_`#RrZsV+>*peXYX%(?8Y&;s)@KBvH(D_2*UqiG6+XP(r?dw%bcN9*${ei*`HYmHexg|-oTO;;gz9MBfG#j@**05JDx?S~0*ZhlFhHPRxmc!h)fngpvLml~7*gH(yR|o~ z(@tl@(j(7@EQHDoA`ztHFpw$zI#5}+dEDJJMYYP3-j2hvO)>@uY6ahs*5l{q{2rNc=OZ_PDRm2R++hS%ZVwif0_H@;6+D_pi z)1u;Y%=(ZsOl$O`n@>fcY#(#;mU_~y4(jx51D!04`o#JjTG2YYt^7}s6x#JOpI~fz zXq(fW#Q<|zxF0|;VPIzgKsE*W-eO5~X}6^%$!G0HoZ)OOg`)4DiogxtMs#TO%o5c-$vLVOLsC9N%~FO6C%3(3t?h_6pK{e(%#- z<@1U&yoy2j7ZK=JE|#fWHYau+dDS>`G_x$lvO4W_Ho2IV+EPK!ks_()`4BX-Lke~r zlGGH{egHwT82q*%Izy<;j8R>l$ zN9Hhb`@Es;uc3k_C*>DiEi2uHZ`w-S(^V`tS(X7r8=K#>o%$1|Wq+Z69$7Ha6$qgJ zLf@C$u=JVP>Y$`e^%n6-gHca_!Ky=pn29mC_`Z5OMN(+9gG2_wPTuzYGD~iz-Ury= z?!f?p4Ff|90Ji*E*y0nmEiFktYa^CH7AIWkuia#8El(*gN8kpJqmkZLKpYS{d_op8 z%SLR&%LipD?Hd>zaq2g110p;p6+Wa3jDT;xP-`xxTtz?;Py`f#E&>kJs_kTN+f}NG zh6HqRx$i3bGYi2+j0VP=WXXBeQrkfV8H6Jtv01i(>R-?_@nHLHgiY0d2YZpEL)&d= zRZtO71Qdav1c83#Vwo~KFgOa~p@$`*DpdX23o4bmn_NsQCuIgv7o_7bFje|>pz`?{ zkGq?usP+R0x)ugxr3V8B0?EmM-dmcM<%*W0#S))PM;3;HlTFr|2q{YuPy`eKMPP)0 z4sA!skZw^!zY4{mi0jZ+5YhG32$bz38Y&+|YRGb*HjAs)I$+f6fK~OG==MxB>f-zA z?G#C&&6z2BzF;SB`+gZOH&gF0mxcQQ1RDm1764>Zknb&)M3;73T9SO$e#9Bh)>0_? z{<#PkxKHQSG8mV3Tc4Ch%Oqw0E-cvTUPY%1l6vhXN8-R7Up$M8#)@@rgwS6H*vK!I zn3Gl&(*OW_(im^+o6nw>+%ldN1Ok!aDthps8!N`zjYEAcj8X>Bg1Tt%RVfa6EG$9)f)AKL0m5qKs7-KNz$v~Zfc z%}Eq!46_!mEmN975w@U0jHMam?qW!_*g?C>ATV>&jqoeKjMu=_baCKP%Ysk_5Q&nw ztcQVY8HiB9>@SXFgl|ZgY#exuw!(*W3&Cq=7)rV*0*Zhlpa@(+z(Tkw99#EbD36NU zaX3ie7H@D^mL3r2i_7d%+k(ORmTSH|3_lEHpqb+ZeZGvasY-Y-B7K9bBLL;Mel-9gpml>){;}(3svHf%3b0AB>mZx+7)0X|!&X zE&sl#!v`A1vl!*a8(8uJm3EmyG{CR#eM|N#zaNRZ`;PCcWvzYy!Q3sp`PVJJhqpce zWY0GIo}7d~6DF^Tw#4Uyg7=+as_W)65ioF`E-1@TT-vcuBcrpiq`9;+Bv|aqKGT7k zTIan6EJspm9|p!wH7;+vel0W(ZiLWZ2iT;s%E17Fa`nSN?$?VzY~N2sWuuKJY?>M4Cl*={I>TErsE{I1AnsNwebO>j(46tb@v^umML8$bHB2bMy?;GjWS~|4luO{@rYP@v{4Q@H%Z-a2V z)Rf^Y$E*)I!?d>auL6pIBA^H;0xbgFrqzqtB>q6jDgiohQh0gK3+ z!jYfptaHn?qbzPZv^^ZqL!~xrFtdbI?&BUUo)Zg$4?4p+Jl!b*ihv@Z2y7#;7}{>x z`Jhxa&K%7w8!;LfZ=N!=9lJYmM&r&KWbPQ+o~)0z@SBIWW6=|*iT1H)_~c2qpND{f z>(t#^2I9C|Z!ASz+8Gioc4dd=K;<(Y9M2YZjHABu)Ya#0*RP%V>F`F_bQ<4=B)-Z( zI!;;=M@Xk9Y^_v7LGsi#kQimr80Zmbt;bZ_s}Xp}NKc2hIBgEMl-1OF>nt1IsB~z% z1(*uGD*}!m<#&znIP{yg?|W{3kjU`3(IFkQc*kL{cmnWh+fIVME#jPn+26q0V(j%euf88p0uyE7-Qa}9WcqusBjIgN!2qxsY zjjV@*VN@%F!>y&M*jKceqlMNei!GzHwk54Xia?3LujS!89@#5*ymw4MV|sf89y`)& zrm_9M4%~=sz@$Ul4UoKu4sG{v`eREOgr6#eWipPt^~O@frJW(cVpn!(4%92pIoL6d z`p#30%iFGB2?|jxmk~Cd#0G;-xPro0aUY+_+Cfmy~5FGemn&5fY2c`UKBPFgbwy# zskILFvj!Sv-)2FD7}Y`UE+$c3eo9<+ou0v0e(KrxONUvIy6wh+L@f(K89*dPk{1N) zK%M4ec{Hw<{IWs4q{V2V&^9-X6R3|h^c^_#XG(3JE{1niNzw?CWc<=^!6rweUSqxDZQ<1l&r#YT$3lNuQR zn-jV9>hh1QrFNA;uw>a?_WkB~*M7ak2pfbi0R&r;(F%YqzyBjr0-GF9S48_oe*aU# z8)Y#yCQMorg06~yBA^H;0@n~gRdrE|zgOc+*1nlWD_6$B{6mbhEH0giMi7)ew2KS^ z--I{3%4cLYQcv-U*mQNZmW6m3KqMy85&#&OE(kryT#4AhC}Sw_Ia#t0+*)XDOIn4V zia=<;!UxUwo#EvEGdlAhm(bjvPVhX2M(ZCz-ueGSgBH%WZ_tciLaTK$?mJlPsar1_ zFNYA4ga+*@gJ8_W&->Ufn;jc_%L^Yac$8{(At)?3OyTvza|IY(&FOhJ<#}f$2J0Jv_7KJU;O*ullm8_jQQsI?)hB8q?_pa>`e zH39|%bWUtUT`f2}ZnW5=TBxDj{*n$Is1(ETY_ViI?4WIMn0voNNQbofm0!jS)x|Qx zrV1cfk&I;ZKYFBB2>^(Tg&86Ig*e!Cv}Qnepl>Y~5!l(&8h!BQ-%(@tl@(le-_r$`;uQ6ww~@N0zcWHVhy*i zEz3K2^~Y}FZ(8`teVPT?!>+>1{O{aW+GPe&>Z{0_!^CarH)knw({+T6gpUA%4I!-n znEDgu7xotjUl`L>qCFhMN_=wem(DP)O?@l#RR~x(O6{Y|ZuyzXq|vU?vXm4Su44lR zjPoWz`SAu8f!7i_jIgOX@L;YXIXI~T0d>0MM%zr~DkhSrwgrEb zMWx<9q_sX9>$m=nr;Y)Y=hNna@Vx6*pP;c}Z^FFrE_KGrR~v*;f%TP$=8Z<8W6Du?mP5`&kP!_`u;K(uhH7w%Ek{J%?6xou{7OBw7F7 z_se)GH{Fb|sR9T#BI*C+;q75zxeNrv#lnm(U0HRs23~5qTX-+n7ZEFT^*|9&1QY>9 zzyX4$aG*MDA!I1k)RgiTZz0%-(ZG1a(le-_$RHSSw1OgGL4aRF{?=xMP1QOCTT&Kf z9X&j|;&=C_PuQ%ZbpyJKoL*`6oCN(i;>>ek2K97(6aLF3~lWow37Ti z9sb{DZtjTfBu}DVEh~r?X+{k!d4Jkb~?gQXw_J)DOP~Dn}L+N^c!uQw0!Ir7X%iczEV| zZW9;2s1PBfTw?%^+|!v#h3`TTZ@H zs?shqh*Dogb~UsWx#=onQ2uz=4N zo?R4y?D@@&wuvF`X-V?bwozF?IT^WdhS~hXmM))*KsEBL2a~6hJc+Z`;_PxTv%J9; zMw_P#a_rY&kdh9oCw>)1R+WzZUe$#f(FZ&Dq^T=C( z{X{|*xu*8f<;>G(hSy(aw7W*jQbt&?W56g{XCZ<&SWb}?+J}V#8sKo0w_U#u8V5H* z=&u88bZFa$OQ}ysU@_9$^Usmq4f2bbWh1uX<{M=y?J9#H#xd$@XiJ;3%?FsHEa}b5 zN#e2&hPE?z?>d+79x_ARGy4Ikc7VU}CV0u&G*ypbZk&5db-vfzLo@ zMixR>v*JxQv39IVR(CwxE%usr^IYm-v9~N3@ox@SycKteN9NY+@zYeg`p=}>7r9K}4 z{A6R3C;8FrI7}qCL|(ktTJm}JYSoW_-K*$yL5>}{%re;auU^lz5Xe8|mVOy8H&p0t zU@i+ANR$or22tw2MONC|(r=DeDLa0v;tu2Pnf^S z=2C|$(H<7+B|bU#OJ|tYBqm)Ifqevi-xvKfNk6pJmm=^?1W+dpe4xc+Z)>-F*IJHR zWq&4}R@FDMG*hj!fhEtWw5tq)Do6)Q1UyKS$#}ETjz=LGY^c=_AV@ig$~u}qUGmGH z)Gui<+6o`ik%dLb^MzV-G36=(ihv@Z2y_t`6%N~#9uP;xO&)8Fe&b-P%EG6iZ;M@7 zK^^%l$DV>Bfih(w!+1|RJHha!V7o!wvq#wj*7O^#Ud zgi`whBK$_(aR`Zjq4WkBXy$l9pD!b95dOzWTQZXMkgzKNPAcOqGrEmsT23A92SjSR zz}Q;oP%a|Yv7n@fB2c!EUufIJo#XLrQ)}taHg~naMu1GMYX)ovD;sS*VcXNPFiGu4 zoMCyCI15*KuS4J=BR&2YCG%8%WOQhoKJeA_cWgQJ|Pb$#pEQU0Me@TncLQAZXjx2;uXWb38x?Cl`83OrY zd0t@ld8SvEKkL(YpWpkm78tzZ3@<`Z_EiK%g~MJk#3~?K{K?k93_fuE+PmdSERBBc z$(^i7QPrWX2j#J6_=K`<6@gs@bZEPal*;|M2z(&5(MXSVbOymUGRt|Y|NUH4*=lB4 ziW#a;He$((l-eIq;)wIY(AGhBzKpQBe`tHj?{VBxe3!I%PCkC;~q@0;nJcFmS+tE>7rklxi(U@v;Ngq3u26SANr$)t>NnHU>1FlgFOn zjz=Xa0*Zhlpa`rG=sqv;N_M4q=CcZj79XV;h~d`Xuf1ne!@XF_p}|R&K`@Y?_w@ZT z-l4ZM!{LBh7KAc@NR-57Jq%>aKtP-?j_mw+i=^R3v>0uL59xMjqQjt8ho>Y(KoL*` z6oC~29}pOg^j7+j|BX`RJauzuOYPa_DMQ6U+9gaXpa_f*_1be<1ut!D3+Yl=HJ7@PR}hG}6pNu$&$~pqzqyml3Vn{>ym$Voyw8R?e$U^9J*4`e ziohI!QQ@$2wUWy!AX=ynt6%u1SZS_%WJtBxl@-*Huivx{Q1F~Q_6(m;)~zC-2q*%I zz%BwG5d2|=w$3LcNxk;pv<+2FhPASe{ywx9UB7Tn^qaP8sD3tyFX&W$ z#E?L6G+RU?$eeu7R3gtnf+wNC=Va*&>C!5#EhSap=?M7t%XufEVG1WV_IB29LUVgM z!JaaCHCq1_gpL0{G-&>OhsG^jO1{;yei7rogWdk*{M+lLPj97NWe}wP8Qvy-8E=$Z zy$!KJ_y{1Hk&G4qtXxLEjrgBn+tb3C^xe9N3Kc%gU0~d@N^4uvD)eLooWG{R>+fl~ zg(cGXG$b*m@3+7`YkdoZkMQ=F@Wuxd4$aewCOFEMPV`Q8)Oj(j^+#e zdZ9bCa*icFnSS3Ho`NDw_ae$3mOQ+NtHohvbl5+t^6`xu;+^fn_32hGJr?~>5x?(xH+gG5FE`HOZGil zjJCpubVKtS8)|LHs)!<>2q*%IK#hO_p)MS*q~mC?jEY-$K9gR!S@&x%)d%Jy*^=q7 zt12k#TQ0}`Sxl0x{L-O;srfR(rV1b!k+LZ3001+02re^1_?NVr97kEu%Pb~Zn+YjT z5l{pa0YzYdfID2|q~EkS460KoQ``wS{%oJ(_g7wWe}ts zYlHkDnbL2Lmo{gc5jF^40thA~qZI%%cjSGSokjR^JY6N)!z3{YPv|_Ym(H+Qo4Qu! z%Md8rM?=4syYJ3Vxp)D>ln(l7CCF(FsdfOk`Uh(U_Bm65` zIoijb;Vwc-d@}@Iag#Nlmb3dL&-eMgPivLpE6(sL2IXHwplluw-p|byJB=2rZ`q$6 z_=t#cifuT9rC*Pu(ylTHra;Qga^;utZurf;B(?ehL|Y*v>))7JAAn1K^V8`aH47m| zTj4{x*|8=v)DnWOihv@Z2q*#<5HOHMb!f`emZ?UIeV2tkZq^SeJq|Xj3d;JH%kgq( z3rmY-giRGdup)`edRW*l0RVBaFeAXW5C^-C)(q$l^sR+wcuQJ^6ahs*5l{q51l-{w zVKma)`jN&^O6IAo6FWoOy;_onw$8f}C+T;6s|-Rm+e2F$b6>rUuo(?)|DPY;&H>o- z`&|OFM^xC;l4uW;)GK_NbH#I)#QX0?to7MSeKi7Q+iK|Ea<|?XirBQv7oxE6F&;e~ zp@H#+7ee|BdqI5Q$_#=57v9pV>(>Z(Z*@t`P}*Ww1`vr2$w0OY1jPBmMms-Yn=3@F zgABDxd<@tJVI*O;p|zQi@?M3&Vx+efhT|1g%~SV=wp%_Qf3g1ag2I{?a|P7 z%k{S;HO!LU_J_7t{CZjartKDBDx?S~0*b)fA~0%N&6SAJ80H7KtiEM`cA(P|;}qL) z21{PD(ylTHrufv;g(Lr}{4(CeUA$ZHsbxSw`1Iz3Uysj8r?Z@C|eMnRz5{giRGdke9?| zJuIx002ol`3o`<2m$aH3M_JIzEErmw2`NtzPy`eKMPPt{J6z<*sEFer=po83b{Vj>AE@^2;p2o-Y<`Y8em^KD~KzAX)#$%=!Spz{;pf7Yk*KEL;AO#$GIbs?qfw?e=mn!0efl8&Rn z!g3>8tPU0$_`vl`57h_eBUvmBD=6z*F2`&GD!+7SW**5KVN;dxATNo_dRSN~0WhG> z7iNU;FKIP7j`eiogH?ceu!rQ6Jl|HyzqKA7DB1tuhGNIM#+w z`SZx@Z`wx4mv7%i!m?%yWwOedJWLX*@G)^oxueS~!>NjoW3&J-5dB=BVz2+TS`J6oV3~zlPR7ep} z1l|XMFS(6+pP+uiNV-j{$H82|0*ztTV)d>1S9E=1oMIc!VCmP!NtHn`#irZAaOIcr zf<0d>*wiv0AbfiB|r(#_CBhe53lPf3b^BJj=# zSZm)oyq_jEgG}qf;XvQI%d*^v7OR6T&GbtTs1O}2Vktjvswyb!TQ0})#H;>AEykOT z4!lP42%9Q^AS;Q>de~^84n(M64i;tvfG%kIZop2~B(^XHNGKz_!bN8a-+W6&nc^6xVTWAVGgI<(!xRi*Anpln+W4cWBg z^+!f$V@R`Um%CnJl^q(ybZDF48oaa7ey5>r4r&m!l3#%UN(e5rd{WYnMrJF7S__wB z&;?8Ebg$lvw+4AkY=eFODl-U_)m?+}auc+MuK_lPg$Apze}>$Ux&UnXb+F}^gwU3j zB%ifQe6o=%XE3K{FTQEzbs0 zqb%tymqkazRi)mlmryn|a*r0Ht?(gTz@V4ehFUWrHmRMifuR(OZi`*9DNtM$5 zAlj0QWIZJ8GLTDtj|1O?yrjh(AA5$kVo;%{BT%-jx!+68o!RnVYaO{H_B*t)bKGjc zPLY(_;_TG(<*jJJ1vD8iH`6p>E(`Yq2sSJXEda=-Am3YDCZ_PWwCW!r>StovNXo)w zFO!{{@Rap(1S~#iGV0?MgvsbuKzRrXt=~k=9WHMB!&4b?iu7#Nq3sNv6Hm^hT)vMv z!(#2^NVkf>E&{*q3VxoP<*o1YVo=XNHUeeyXqhZpDRhG*cQ=iep%{8abeRrx7>Aez zb-paRPWf%eXoS~I-*0wE!I^JhkhRM2&rhWd?8sU-s1E!qe)H4mD_RzwIKdueaq$e( ztZv>Ifqbz%FUb6Z=<|H^E!#f%>D2rD-lw%n<`rjn6@&6GA}}f(mo6n%fvUK1)M^n` zzxHm0oQp!`q{<)|1F3mFBuO#eEzbs0)anNiq#Q(L9RUEb`C`bva%G7Yqpk2EUBIB1 z*@jv(A>}CoeFWTn_Uy;RoPc%q%OhTt}haTW%zN zU{}seC4<03Qhry?Nmc(y(%xhIv!Lb)XNJGAoY$kwgl6iKOllo?*D2k3 zG{Tkv-K~RZ__a9XK$FMaP1O;WYwW9Fw#X4Py`f#pBsU)?j0-~`I*iJ zKDCykPF1M-wU^SfO)mTW3TjTuNUC{0BuO#elg@Z6mZ{YbAQ*7r&A(iH4{v<{$ewKs znYqy*X}A$BM*G+^JoKv!ML-cy1QdZW0^br#280~-eT-FFPNTJ$S&DIrwI&~JxVrUCX^JR!l89+258Ob^r+RhzKu2Rm@HIjml*`HFO)Udp<{$*j+cV74a{Y&egMIQg`E`u z5SuP8bJ_4_(r|}pvv!G3lf}@`nUSrXsk;9p1axS-2407@{yv!RgloW5LJ=qt__aKI z$0K{CG`?d38q?b&P&SX2@#a>Fq~WH~G88TQGY2}1XEDl;H><7_eQPwp>!#`#;n$A6 z^f*;V{D`4#&rL&PMy_E^2u-w)J;M{v%2EUr0YyL&7$H#Ay}C?|)Jl4-<;bpX{r%cY z>Dh**M}Ei>CshW)21w2GA^Gu)@y;BQXRxDIzk~-V2T@sdXbV7e`Kb|bxmA8!9Q2#E zZ+mKfl)%2FL}Wn7;oQfS1RJfz%uBfh?d$% znL*TKONs8*!5%a%4)vS19*B!)n9%7)5qKN|_Hm{zTH5;jU$m*>ia-y6e&ssCiS{^4K$cLRq(pfFhs>C<40(V7~dFk=_T~ zavFOBp+7vO7^G&4Skiyfc7~GwB`tJ59Hc+?49}e__eBW&VxuE-r1tf{#O)V(&?AJ| zT5CBrsef}(&!SWNvx$c=?)ILBM3v*8Y4Pusc9lU8`-jN({T_^0-J{3vl$_%QcNXPDNezLlv6C<2OrA}~Y%_w@M0$DO2DF;BGq zw$ZXDx&A{a7&j-u#r7OdrG3sITFIlL`WJ?xrdzmb*duHVBv}@ZBati^Vd(>K5*Tfz zTzbA6$@J)Wc4x^uv#JwiytQMNa$b&rZ@-Lp8X6{la#L>?J}$nwb$;1;HCi@) zQp2amH)z%`p>Yc|-)fzVhYl7Opyw@K{|I~+-VmB-ml*_s-%NA zP+cq|Y!H6*1{0Fe0)T}>u%q8#39wzzI{mr0+u0iEfhI75JzpYXa}njf5&?OJ;;Vvx zeaWu>Z1R4wYqZd%1vNa%_?wG1LNy967{BmP#6`XIR%(|S1PPnO!h6^6Dc&qO*^RJ4 z_!2;{0MZhGi8r!h#g0b;8(FhWiZ(VHQB1-cWihiwUT9nN^)3j=EjLyNl&KioUoS*> zqb#&?b%+InxBd?ZHexg|-oTO#irTWZSEHJIcO4V6F0J?T1>Mhiy0CRi3ma6MJ6^V&mx*5hR>?J|R4%Y?W1vRF&MIbN{m zi%IOP)ej&@xg_c@UwQQb5bkvS6S=$%kuu&Gu&7<)(_}HWbmq|7nW+0uLcrm4j7EC- z<2MQLMqW8j_2iwQt)cpC^NgXbn>i$Jgw3}kArOWmkhl&2a7lCVUJq?AY2C!Qgg46K z;u#jRy1p|4ueizP`~RzvFt2t9fA{&lPivLpE6(sL2IXHwpllu;wXa-Cjh3aEvOhcU z5vlq{O3ya1^nVv^cQnD4(!gTr*MYjZR2}gsfMCsrw||`*`aS?bZ25v;FL&k2YNCDY z8D2)M0*Zhlpa>`eEdo{DYsyrs(V;Y2tPa(!{~@KvAcC@j+EZNY6dZ_^U&edV8E-9E z)G{EH0YsuCF6-do84S!9OE$vi@oXbnjP|i-c;;Gpihv@Z2q*#r1k7O~XE4%p1GSR; zn;gnK^}7)4VdJ(xJjIA}tCrX#^?R7GxM;JQnIeP0GORRxzl=Bk@E9!)-UiqlRRBRd zlK#(ed>2!F0QUUWL)$$qM9VSjL(VX*NnW~sE&}Olz{M*wRv*&dXC%eWo>a78)N}hC z8jQQ7zV&XiRHa>J5X1~+Eq1t$p_${Q;A~?OGi&t&2vRPI`pZ{deE@_zUD;?KybVp| z6VpJ3+9f_s78@qL2(9gjtJG5wa5x>Kk=~Z`8>Q|V+ERPEdB)Io>X6J4Hs6wjKp2id z;yM`G()4sw4{fKyWY*D2cr{(VuuR3-<~Cz0PZ3ZA6ahtGg+SRnI*R93ilpJD(XtdR z`!ngZs=krZv(2jOMBf@su%$Gxh?W9=9jKd2)e(>S{$S0*q^!-?j;^$tIiowY93t_5 z_$Tc~Sx|1aaWkg!6ahs*5l{qH2vl{iE>m`;ANjSG6jeUfaxl}cy;Pq$%caLatgN8+ zq|8pifmr#aLkgaho2>WK^%UXhYEh>S@4`jNYG!)R z(01yP%n>$K06|_dS^z-P(@j0JoeGnAacE1u=|+dPQ+Qs_#MNMu=iG*+p44syRBQQ9 zue|ylTKRNjs{uPjQfiAcBQ6iziNdi35iX#~c)5XCe=&)ih5G>nDVIbgCV$igAe(}G zcVVNAhe~@|2DYgEh%=mj>gh(R#MdI=aB@c@y{%8mjWORfw6#>9ZJsi;jC!?x z4_-bsVT(O;V>7eV7H1|4`e7Z50$M@P-Qek_SMT9#(Y{!BWps&Az9Yy(R=w4H(Ec~$?e zL)!&j%2osv0Y%^y2vl{C&xTBL?zUp6wWO#vxBhC5J@_;9b>7S#~@I)kL)h-V8d=XskK%!%j&7gRs(j51ihj| zY-I+4Xu#2L+6Ev>eCl&$iPdz|H2+g+Wj+}J2m3g;a(3kLV?N2VIBG31>UF?^9SbYC zP}B7%MDPa7DUw3_a8N)7;V5tWei<(}u+d)z*i<*4s9W7pJgp1BmS4kYY}##UN%GWo zNm=OGNP_W%D+GIs=@FIoSqOYdpFM{U|96Q)ej`zir)#72Rm7_n9DmeAjN>2p5aH=+ zaIJ;{YNKTTp9cx7FZ^hty{-H*-e_m_HpHe3Aexbk767bVM!w?(b>(ltNVM{Ias2s> zw-TWIPkt+^AKL0m5qKs7)i=EO#kg-*oYq>7)$V_jnGaYiztWe*Hk`qdmqciy zU1bnVHD7is{T_^W!|!q2AVsZy06|J(lJz+H0KnpWxsi?Vc|6;Q7Nf23A^pBHJaetQ zmm%Qb2^|x!H*~k`)20E{T4K~I^*gkpb+%L6!aPM%Xdey|r=BlwtBw(xjF%hn(p?AG z=+L%{mJ*+jz(YoQ-z83a*tq>F1ap|U?GI07#3|CV)!>RdybBuz%bBSRB?C)`w&CZ0 z+-x3lhG{J#uWyRLH3W2Mdkrs@{t*$dND8Iw3v)#G$P!0JXVYl0pLLMNjo;u9#vzu~ z!R{?C6H9Fi#wk)EjUGAEVHSju?lQur>c4}oBrfaWV6guumMRnaM0^11uzAgEAf;zPQ zJnVlG&x?_s-GZSW1Ugo`{><`QvMOS^j!wKiWoXNvKqrom8PI(?7!8a!EIl%9G>|Pbh(wTdXdBQd z@v#x0@P?DX5=Kcn3?l{i_}t!EcUt?Khjt zT4ng|WCYK;PNY5nCzavWkYl;q*wjCOIOzOGXV`2wR*{z>@Q{(-cL`UAwz%7U6-3No z;!clsUkbtO_Xtihv@Z2s8-vE7$p%PNUKgEGbP*DR1!(f{hprj5jPj^0>)Bw#*ORMu5T_P6Cf-8#`kvPZ3xk@cV-Q4s89V?K_->A36pd+AdG;4H6t&Rx{^2 zzG=Jk83b;W(m#((D0CAMaKHf_6T8dv1D+*RwU!w5iv13)Y@L_(g8-lL@Yz!}AU*Yb zd0Ra+g5MnPmg^BVRRFr#(Vz}?}Z z%y*HrhmG6v?=zoC$5)XxhlyJq+6p4NDgugtBJdL;V3Bjvw4${GeU1zoLoZY|gn86j z^=+kCR-d?WnOACCFiw#QiO)(6WS~ihSr7u9V1U36H?$4KhGWzZWc`wV)7Dothsq}F=&QzqlTngyJk+5rq0mi4;7{pU!{1yy zvg|~Ev5~O#)@T`gdVPy%qJ=LjKEUtBEl$+=%T!?ZT_txQEg5l{pafe`{0j96#QNs1No zMC)%Gt<$u?L8bo`hYwx)hR@VR z4RMM92gYE*8D&Am*@o6;Ldts$0-^m1A2i=ES-+&-E__^kb8Gyv^=h>K9o538#5ZW+ zeEY`D`NjH+=wv)}u;+`>ON?K!?=^vs(4bvq5CmNOypR3nc!TuvHNvI}AlQ+NRsbx0 z27!NsH|PHs*uwGhCD9)E1+EI8ocpCSEY_CpRp1o}^!`DuK)YRW{?{OU*7{2z{N4Zm zEo}T}4;N=3`PVJJU;Be%(b7jyyoERaicXqGK7kXHy7|q(FXIiu%hv}asC5IO3?LFg zO0kUrfPwk)L5qNGE)H(e;=l3L;L~KWWi@JTNvhCG5Rhjm>A6KLQ_*j@N$2ks7C%J#(%Mqy7OkTP^DdF5X3^A#jEQ#$17sWaQwG|mEc2nGr;{*DCO>4jQZut;P zjguSHrOx?7A+h9Cei<)R7t076)WGa5&z)EvKVZ8AVBrvKW`yuBX)(uJX^r&z&hTCg zDy0Z00*ZhlP$1xNgs#z$nVUS4hMPt!_o(=hwtC(Q<5_HIIy3T5w+x zLI#=!hnvd?8-(vpW+Wq7>+eZ5fFhs>ED=b*X>nNpUwD0u@BYoO zPzhzSHd_BJ!qp$UNxx}9;}?F@;`oA!lS3>2z>8!MJpU%{-QnW4^2>NdZn}zPY6&)F z0MUkIv;bi0Pneed1;Q7`bd_lFn--yMip_!0n=Gc*gh^{c(Dic>z}0}h@6QZ|pBYld zn?{S5*a246p~1Krn`}6zUarzEGYE=E#_#%mbG(h49$|!yfpE_DXi0qldTwf(CBbpG zu|c$!q9r~#_bX>OTccUsd>#TfxE>8APoKzfkj)@)F|%~A3bA~Vja_j3`_Q4SnK;a> z5jOV^Z7=!d@0nfF;yJk?kx>@c&M=JW^4190S45ZZ|F7_N_OW%tI4eA8f1ls`v=$-T z1z*{3h=4;(Rom%*5%EH>hO%Wt=*eY&W+B*!(ZG0S+W*^*KrML-cy1QdY*0{zOxGBwaD z$&QEU;w%Z(t^X0FM;3D z6_YpL2VlpqrI6!pV}s-^MN52|EGReIWNR}i<-G`j8~lt$dRt*|K3vOlvBY{Y0_ zyn!VzP-;7c4|EY2;-c0kGwn8QCpy2-VTL0bO9+vTe4c zR7ep}1QY>9V1PisaQmcWZA}r=8A*rAM9*SqPOGL?TGXVIWib zb)d3t^SHZdifWZ5y&Z>z0a^K6&wznIPAXt@mW=%!T8;+cYm`OyLXCElt+hO*C<2Or zBA^H?5m=1$mikfPtB4ttx5dm-#4z;~?dhuDw4K63rbWf)nDrrNnAYe=H=l|?**@mx zE%l^Z9n|UB20B?7^@;U6w4!x(Tlt?NDYWZnKEc@b&^D(#ivi}ca6f=x!obb~fNTo# zy~UE~(r!yjlF!9KoPitfP-+= z^|80zvSlcRJ9jRhWq)QN*oe`zm2d#mhNOI zlJuLlCq#7n83^FAd#daFgXmM;bc~x0?G>c^{NAUv%I6hlcol>4FCx&dTr5+$Y)Xl7Z8Wp&!=Y;rLzwWWfdBSlip^C4(vhZO8MB&jK?{Q!czg_5iz0IvA;CUIq5 z(Q=4{9mXh&Gj7zWH`!Xv(PKqG5l{pafei#6GSd4hj?7`=_IX3wUqb~=PRcL3T2{IX z-?Wvur>j_QvMd9LHa5R$JM||_%l<&{>Mi1v2BV$; zgH?wHF%x5O@qP7niloqH2Z;=VoxJV)WtQAby$`U#-Gc!H8wQ3J0BrfSu*D~ATUwHQ z)`eT?8DcRoltlwyRVV4GHMta^F?BH@TQrPRb0TE=b2=V5;=%K;`o@9(OlQQSAp1bS(_XN)HAM1d@{h zy|*+i%M~q0izPmpjw}oXC!4G_5mJ^Spa>`eiogf~9omkNA>E>eeie#A5!a!uAfoH5 z5h&Y7G*mu_)R5&qZ5CIpb-<|C0jugW(e0UN)W!GJ+bNPln=@1Ne8EoM_Wd$mZl>O0 zE(`Yq2sR81Eda=-Am3Xoi7xH7v?Teg{fIN1t))=({c{m8aG%btWiT%7wmvD1mPyL~ zU0ATwy^2m3B=y=&j>LgEzIYZFjTP(M2%*0Yu#sOZF(<7mrU3x-XntVxP5_h;g`$6hAidNcH z20`q*$Vz)#`py5qhsaIW5jGP3>DLa0v;tu2Pnd=m)Rn&lBhjLP4_#Bdl?c5)SK@8H z(%M{1xr#s!0mqMWkNX}pKeW}CBJfNEx=pKhXyG(>o0BNe7-lVATc$LFB5Xm07)vwA z-NleEghpmIa{9KoPitfQ4{VIJWM=P#zVx<8Y9`E#Ba;EIlC37nj+kwgrRr zE!TW`7=9SYKr_b+`g|E-Q zZ9JQ)L)&K~{L|Y3@0&4LOss)O8J45=17Xjd5oW^TIs ze(5j^!e(!AAX3YMPzDf*lDMp>aP{v@U-HYR)0eauEwmhhCfz22(7_%o)Ee-W{8k8< zS44wr>lLmlAD{JUywC4_T2;#Rp{WUa{Qd}7gxD00E0y&M z*jKc8PAs$@bcVNLP$5O2K;YNn=q(TIl{?;BW}rd6I|7T59`D(+JU+;*#+jp;Whv&U zKHEHHXv=yw^W2O<%kU3C7);z?N7fMlSN!^x1^0m~S|5nyknl!XTs*@xtDDb6z`%L> zWLSpc(r)XM(rB5a?B9h2JNS$^@Kfiw^})#xxki2GsmA4P*RKS{=n&3m8DP^+Xmw~i zf>7xXMW7ma-Z#>#wRC99Urp$L)p+X^8r*Wi-v;4!sVT!*j#(dahG}i-Uj-BaML-cy z1X={TO{*8PNz|of@s5Y2)XKHNKodIKMw%|*QvX;48(D_-dKvbv@;}F?8*+! zfy!q*IG!!+7)O2QsjJW1u3tOz)8UP<=`_9#Nqm)obeyy#j*w1I*jlNEg5;@fATi3K zG0-E>T92u;S0nI{k)951aoQYiDXXdV)>$^ZQR&cj3osRWR|FhC%I_NCap*T~-}l`7 zAd%s5qeD7q@s7h@$*K6#+#+5l{qxfW=x?E>A>t0DHcSid$2t z4D9?zrAI>R|GHK1VBx0urGEI$@ltTM8DUce5KPE(8(9wr!>CpUhg(Ziv9D+`M+>b{ z7F$MXZA)5(6oC?fU(3UHJhE5rc<-2i#`N|GJa(klOk?|h9k>zOfJuk88z6ZR9op{U z^v9Mm2tQQ_%VZpP>y4#|OFKh?#jfno9H>{GbFgC^^_{00m$zNN5)`6XE+cF@jc-E| zUu7UmmqCDy_UQ@Rh9Z)uwt>zliw%?KShmDf=(z~!&~}NhIZTvkM$@=|0Ky=nL)(ay zz9|BVfFhs>lnCGfp#v2y9v{UDy;Q1?YORC)tbu6Rw^>jjMs<+8iy_rwS9YC_{0l?d zt;eHcnPFPEDg%f_NnBRcX+D-m<9f+28`Mi$jP|i-7^&-`2s{)4eq0}Fb;Fq3kWmpu z;1LK|7-Xh1~Cf>vl7uLlZ_xG(%FQ7iS0R6=bXA#x2kU4ufO-+*WKqf{Z-xb z|NQQsbMCG8z1JNn+B5$7PY$n@Mb{WJ#TpZIR0I?OML-c)hX7SoAGGA>YM^9|o0(~) z%Gg-{VB=C27oD*N3i6z^vkZ`L@q@Pf9hnQ%NxUr99et_gNIVZ95F=?305Z@WD0Gxr z6R{_w5<`a1#F8Vyp+T$-NvqI>B7p4|o@mf_;=%oJa0aIfHn)=l+>c?VbsOb9{Kp0j zk2f@E76xp!CdQ$IbwC~3T(}%CBo2+Viww}14d;8?uf#j#xrt2?02r!TIsl2^p4r4A z*b<>LqiC_giCd0O%AF5F$5vvAwM5d{l_5~CT&YYA1xEMtq$Sm%xb@$P<~C$i#0I>O zC6Fw%iww||)R9a6}-# zmieA1-LZvDQNqy%mqi}S@9Mee$j4#fQ!;W<&@aeGb{Q>em2`$ty!5Qw9#eUWfFhs> zC<03e&|jyBKWSmSJi@H_NsGCblRJ3v%WlF?TENPETnlo>Erpl(cV${==NSa47g^RC z8>YG6lqJh`#}+mmJ_Ud_n6v~y*B>*_q`#o>nb93NTH{G9$0y~!>IjRqu5V>t76OhO z#rDxBw{p%TQfoHTaw5qrx{fU|$hh1jM7}*C3n-9lJJN|6gq<|4`t_tSI<&AUI&d^M zBYARC1VYsAkQ!~$_sD&Q|K>BCxQe=Z2z@CA|%aFRWP>V(B95 zcsmzfp*jibNH<01Pd2B4&uJS8u&a1Q}+5#V;Z!jn94@Nf8 z8WC2Rt4825ZnFOBk{r5WTtIlc`Q1%xA^giY!V4iNdo2Q%6!Nyy7{A7lQ~}nKe%6s0 zI^pOPnTe59Z*Y-$FNIcgos*v4Mp^i*`;~Y_t~+UAQv`rE0_l2Myfuz2=YbG$VUUbg zU0G$cmb{d7zu-M%uS6`<)g47Z5l{pa0Z$Oj3I|n(A%v_*&1y=1i+3bA6B7gNiIkp3 z1*HtofEO!NBpeaQuND5#q=ikRr&M*#zVuz$uND)v3 z6aht`fxyC&-q0h>Y$4D|0>qcZX`s9;fF zHAYPb|IAA;E&wp*SEOjsR`x4F3W=jNo=7=9vtuP$iG|97M;eH7-W3tlpz(l5L$g_%pgdoY1OYMlcPfm8w%e|?951>m_;BHmF6@x z+O{cEVNmj-?MSATMa9INB-Z9ErCdG&3rl)q0m+iyhU6F4EN5Z^Zq7xf&@M7SF`ek0b(?qAr_Oza|@Lby-XL zSx08_zHKH(QoX?m)6=ZzIww8771_F9iC5&hlNL5b0BC~~=g~N_oCiY0g+Ve})u5Kq zTJloT{et(5y%MoZS9cTvML-cy1Ux}7D;!iEq-yk_vcjCzl>8R&NH7;m>SCudk$xb3=((H%&$*(09lLVPk8(Y{E0iY_EMIIY3&wS0zj3ybm$nrCZ8ljAqwMsg} zC|+vDm}YsRqavUPC<2PWE(k0v=?$5jEd(yDSr)6FLr(6BRH2<`5TssY*`-BWmg|nZ z3@VRz^#IU@gMVR^5>{We4nj*G`c2yft-R`u(VgPRYZiysYa=3lFwHRZ`g7RZ?2)M(of;+PgE zFWN3BGbj@yD~_-<|71&tt3{w#@+=o7CkMF`XQ?G?myI>c4cVfl&B+DXc5*JPLc7QS z#bgC#&QoMm2FV^zd0AQ70`KIkEEs3_kN9dcFmXE{2r)Vw6DO(Xx z1QY>9poV}YV%~P9)~=>AqscR$Czg~?M+9nGsa(v&NUAru$h?1b{{YNxx~^$5Xi%jexso2WUS%h+c-bsgIS{?^N}n=DYdbO=}@gx4>8S z0V3cjrdi>jONr?H$gQyR;s)frP&pFJ#Vk?#16cy0T-%e{BvK~L-Vc$cB^8qdnNk~D z*c7b;s`A4pj|~8P&CQG^8M(;vGl?3ZjFz=ZI>RVlYQ~smd7`5tpa>`eioh-iB9SJg;4}eaS3-({{|S^cVW;k%s_#f`lC98rw&o zGLPqsTz`o%pUt$K$S{lSSYl+YGZTr|7$%Wq+QyLrHNd!+rd7Y5G>lA`P#+uE=%Q^M zE~Q>L0t-ueWBz4HZ$t76YnC&y0XOF&Q)m|%pqMP9E-l)M&E8~7%vP4-4dgg+9vh3c zJ$J&}%1pm$D^Tb}5l{pafkzSnOHt=-XIdE@N=lX`Jc&y`>xe*2E4^NwiIG%qaFKa0 zg;s5UgOrW3@LBgO@rqn`(!!<)0Br=4F4}hCRHh=J2q*$i9s-_Ho)r!%Q$uyh3T}CE z19D!d90}%POeJPxAWOi_wLQsG2Drzh#YI~Vk4!X%7B)refZ9Zou?0X%rr{IGl93~! zHCmQ*1dLV|D~~Xn)lm^p1QY>9Uy9mKEZy2BKX%BZB>=kqnE6GX ztm;rXTH{DP$0y~!>IjQ9j!8#FU>t#aVoh1?%Rt1qTpML-cy1QdZP0l=ft%CEsH6RAlH&XB)CX#zm}c zS~zS82)Xu_MC2QF#xO~KL+OTONHfJt^#0JohQi-Yv^gUl4ToI-Fi~kwC8JGSX3i<2 z-I7R2XBg)eDwLIoRV*lJuL$Jr7wl}sHx5h1gK70QlTeNc@@j_zQt0@i+J9jai>-EjiN4UmB~WaY3xKt zioYWw6@P9r#i0mJlxI^*6wxZepBV8Z%42KMcA`QWmB9*)!e6B&(UKNh6FOzVba7Ul zh*p)W!~;VhT`U(Dn7cUBOO~(dY~0Q7ZdwZ%T*eVz2tnCv5oi?-x5kiE0oIZyTT5o> zgsa!yAy;gv^o3@J(s(>P(2wWKgr>Tp$vKZ8{d@0ou7P7!VT^!TTlIYjr0>>1 zAXR|1hl$t1X7@$gWV<&bzp`lClTExb+AXn4IZe*@??#AEjCV_9U>t#>?n&Wr<0jh0ZC0rA zcOzz(BGRg$eiASjRb8|NQ1*L-Cn)Pw5g0{4ziB&)l*&E62y7{}JuT_!qHV-ee?9W! zd&wL`W_jD1x=Xtvx|!DK+aq~vvh2(!5ld6j&ND!sBZ2gWD1R%H;uXQ(gv=!^OVW7& zfjA?PmM0Z?2%-JnkRBn{XgM+|+BrV+EP5dbPpk<=Cs&AoF4``FuZy;DA9RZ_semG& z2q*%IKofzyd7LfU+NR=^A+2uF5VqDV3o%ij+AQazZ8z#kOXj%W3t~PEHUXs5l{pa0YzXOfh~zXHjB0% z65^yT_ix%_RpZ549$UX38bp^jIwtx}+hwSpG>NnL4$9MSG``LGyYyCvN$qi_^&HDu z`r*Z+*r}cRz+mIYmgSa5EAK=K?IHuT^tza<`;~Y_t~Y67L*Y{Z!31Zt06@>3@VvCS z1eC<3bxpnJLvO7bd6e*ApI)=Wz(V{84R zcug|kgfxO=p`B%b0+Tm5E-1+FDvg?xc!}K~Y+z5c>H(mX529%qO@eWeLEQ)KbO+Wz zp^5LV4l*rC$U(^PnOK@aN;>U9thGgyb6E&L`{ltGHcWVMLvQC`g3ayZ00X77&9t6E zVGIAUL4)IsjT>G{&}umt*f?~s!)MOxpcl{HLc7QSr9O-w9lsK9kX!m_Vng9m0Kp7r zv;e@8%fNR5{|RhkT683#Tem@>z(;at7>BHiwIOL0x?lu6TvNE+io*tnK$Ev2kygnwunqv!$(t zO%VW^AyOQ-NT~yWoW(8pMT^@-(TTt`S|so92v3~o^r{hn`zUVly@d<&@Nw$Xd|~Di zKWf=TIEhTWwc`fW2sbjm=B3D_^cUJ$2Ejbti(p>$>w?huM++Mcp8`OGM6$_v9e~7d z&nBHd!Pb_YaEdoj#$@=oB)Q@UhjuAx>g^YR}oMI6aht`iU9Rtj+oMj+NyMeIMb3IHFm_|ofqojJ1^L5_>|ujLwo&!EP;?E zL2^=LfJ|vFJ&6{6C0=6p2S;qtvP8%O2t*ln7WNl!e3RblPhSt>T97XW~XT>w4`K^@jOCcEa>DD=Mhew^WYd zT}+fM{E9X#e8~8UpR_RMt>Q1&E;2wVFSUVxkxcG4 z#Va;@lNL4_Tu(Bho#SJPZ3IRk^d@4hC#1Z~LSSJ@FI|6~fV^B$ z#d>OM%`zAB9n*<*OQyMY?Z>TT8FfQStwme9$i#GYavrJ8EXCXSqU{>L;GM!>qm`oF z?-8ydq{IV5;4*Hq_R4bhSLAs&zq@HIrFa=fcqsa=f@` zOO_Uf7B)oyXoVB!(Kxc513<)uK{6uP7Q~5NMr#{%PxPTdj_{DQ3Mm4Lz#$WPcR8y|9RE$IzC(pZt=^;9{yBa60UwInXudT_-~;?MdP8DKWUi?%N0zVy+;rnPAM zHdwsv12E?IE(hjJP#DwVXpN2P1wON5CC4s`*FP;=tFx7Q*$Cuqs}=W7X3G;RA}-F- zg~%*AjazR=#6Wu@7eYLTL6AjBzPcovN<70_!1V$nBCTxwzo~-gN9D#);y&?ZzuBc)?b!^dg$j9W@RuoS1 z41zIPM%|F@)}rl@>+>kp%u>9KFWRp03$pr6+abVIND)v3DhQmNr9P^{R?;OQ&}v%k z8voQ7rWd$Uee?dzP>03FMQp%XI$a9wA_FufZ#_Nk!B+T{cq4b=(-B{^EDC`YYeU8mR@>Lp{mzjQE!+JWG75dv!a4Z zeM>dJ_0CEhS~1$2w6G}xKodlg(Ks@k17L~TA0#7!ZI#w6$5s~Nr5B7?>j^1O5l{pU z5rLzlp{x85Lw}rN^2UdBc&U$yf~<@VE#&G%BUTQVy3kfE&6`!h6wrMDT|3yQL9WYayZPNss|$d<7+8=Zwl3O^;dIebmK>CY z!{>C`YYb9uSWBvdBMmy?>a|zY8|DL9p4vM61D9 zvLc`e94rF5XnPQc#v32v;H5rk!&d$B+*0e}7HvJa%9nhL3^1GFZ`y{`7e89q?EX#L zMVCR~E{i$ic)C1tv|MEid~A8FmMwyWWotvyDs9WhOFtLt>Ap6lZ7R{q1e1!QN@>F^_#Z* z1>p?=xx;s6L30PKbWHYpgojQD6;cEgfkQ$d^-+fu)sq%WwP^(q>>42CX^FL@`sV!^ zcUm*C0cT|CP6~~j6d9l?X}UcbrVh{2uEb0G{lS%5mI!$OfrumrAHyKoK}B1l(bT^MpoYDetmyc%l#8Wn0A!3QumPUVDey zF17@3iOFVBL8ZQ>a=f@`n~ajp>d?Zb2mp1tEb`a@z*YT}M9GK%TBRk&#FE)o7VD01 z8Kdqi0*Zhlpa={g;EfMbywoSRUR|^m^jg^HqOCxrlS@V*Z(FT+cX1|tnlLI8D>N5p zsq1A{-l370F4{)88lTc=(;GI%vLQ}nPorq>;|NRh-}kLtML-cy1QY>9KoL*`6ahs* z5l{pU0fF>Px>GdtKI9KoL*`6oD&2K$Zq~_wL73<5TmUny~zU$n<9#Yl1t`);_1hw+LLtk^H1#g;$b% zNzi>oKoL*`6ahs*5l{pa0YyL&Py`f#i$h@O=au*8e!q*h`-^L82^Veq+nT4`z9r=< z0=ptGc_Fl`iNn?l@1$-Xc8nUGBA^H;0*ZhlaF7VtrKomoW~VDg(>eKD^t%+7@)dzc z34!XO?O`PVi?+Hc0#}K^^{aHgi|?0qQQC{nKA-PHk*`$gy#%U86ahs*5l{pU2!ZkH z;T|e#yQIDA^JUAfZ!u1j z5&EmTf3fmL;Hma3ak z=7dm^PE6rwsFPt_VCf2XFyLUA?28eHi5hUBAFDT89N`Wh(-TfFhs>C<6OIU{*z^1qtRw zb9KoL*`6ahs*5l{pa0YyL&Py`eKML-cy1QY>9KoL*`6ahs*5l{pa z0YyL&Py`eKML-cy1QY>9KoNK{5%7;d+H1aT@Cc-%Au0ljfFhs>C<2OrBA^H;0*Zhl zpa|?2fk)u0`eihv@Z2q*%Iz$1l#{(9s`>TqeW`$gdG<}2rH@duwj;y)6{Bpnq2MZlP! zt%C6TRqDeKe|M_ve{s6UbN6wc?Q3+uIkmL?ndu(Sx1Z$MzDD~>Vd+`(98f-Gw(mE$ zjQMr*>K%aH8*|UyH0FKg{2Fl2ZyEn9@K?T0wbY%Yd{rLID*++l#W&CT@vwtUl4s3r0e+uQn2}*9a_?d4WHisXwA^-Rl zV?P3S-oFpRk)#F*EEEI5RXrjtR;%LJIupunxc{I@4>ynx5!!tm8A>VmJR z&B;5y@a6yh!Ph?dM<2Lz_NwuJ>A!Gf{^|RF`p#!=m{-l|@$t95`rTK)@}EEc?6=#v)CIDxVWH6M!Rm$1s4r{DbTmqGBf`VaV6%yBz~EzYK&NX<86?i+h#+;?u6FJ0S$ z(-Zr}V>rB^eDklMh+Z@AMg!k4<`wY&s`-ey7w(8}4$5Qcht}nPM&*rh=Xu^=#=LJo zeSg1sKY#81`RV-!4=_3yp8fg@_hEMCAmx0tv>(RE-T0#$2L3+}k{14-m{S{6r=xMe z0eTqCt@ADHngHDiOs?I6XUk&)M;Aq=W3+e{Et?z9Z-6aZbb1tI-uK#ZF!xP!B?vTEDOHiVDbi5>=YlytBn(CwsFevia3E&ypf{QgcHP=&RRZudBhBG!$Xt~ z&Pkw_IN=%eK>>pYz-$B(Y$@cBhX>NXeeaL|_CG%LwSULQ3jcRz`#WX>?+?Cv zeab)p@!I?0TVQAG^0oYCs0DvB(z&X-c2@fGj0l!p2DUakr2~9gBqtS^Hnzl&s z_>q)Qicf|6&%)03L&*2|kw+4g9MaK;D8UqLSS0N^{1{2}G!lM{B!uTNoOR)!-+1$5 zXXfNN2d5;ZS|7o3HBpOB5sJnbxg~nx#v0(}8$>zI4p{(OZWtjJ`xEiTN+pNxp4knf z&BAoxkov|rJq*S{V}oZ2#IORV{{vWH^YA|upeG8acw_ZHhuJTj9(XKI@U%U%@Zmh3 z!{zBv?zc`4?h;!g*asgWq{%sX9H@VA<9aw^uV056GI$noTPWuqCJPC*P7`nq+;o+O zd*l_I9xZ&BerPyd)n&wZv_{3r!r2_2M#44J!O4T5Il{AFF7~Ut?)ZE%*Peoawm<2J z&=@1PxOT_V2J`dVP3z%{=~!uC^V~nh8wNjwy^1{Z&0~33mA;OjC)#B%-molK?%kGS zwM%!%AB86}xJN(#x!?HC@BPh>KlvBme&*)qt=Zh!e9UbB@H6lFv)7Kig@FBgf8hiF z^4EXz^)G+=A2-f;cYNA9BbW|>z!nAIH>cjdoY3RmmMA{d894T!B;7a&J0sN z4O(OQ5EApaywhWX6GGX1Qan_g-epd2dx$%1m$C*3ZvfHRg9i`p|L>9iCG+fSxQ|a; z<>dwML|Qkh^ui4~tI4~#OK%L}`omMRd0olZ-H$)-Jt2@f)`2jwkWaaKOZyaE0;}w82sa&}K)Y z+?VHsQ*nB}=IDS6b_#3J{G^>P3)6CEAE#p7rG*dE<;mB={Q+-pYjNV`^Y*eZ;}&n6 z#R)Zeo~oX`d^Yo0T;lX>TtLIy_KNnt+4*Cv0D`osubhx>-{f33no1ZeL@P^L81r6J$!;hH0$N$#LZ^xKw l|3K diff --git a/examples/hdl4se_riscv/de1/de1_riscv.sta.rpt b/examples/hdl4se_riscv/de1/de1_riscv.sta.rpt index 5819dd3..30b67aa 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.sta.rpt +++ b/examples/hdl4se_riscv/de1/de1_riscv.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for de1_riscv -Fri Aug 27 17:24:01 2021 +Sat Aug 28 10:56:45 2021 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -22,55 +22,63 @@ Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version 14. Hold Times 15. Clock to Output Times 16. Minimum Clock to Output Times - 17. Slow 1100mV 85C Model Metastability Report - 18. Slow 1100mV 0C Model Fmax Summary - 19. Slow 1100mV 0C Model Setup Summary - 20. Slow 1100mV 0C Model Hold Summary - 21. Slow 1100mV 0C Model Recovery Summary - 22. Slow 1100mV 0C Model Removal Summary - 23. Slow 1100mV 0C Model Minimum Pulse Width Summary - 24. Setup Times - 25. Hold Times - 26. Clock to Output Times - 27. Minimum Clock to Output Times - 28. Slow 1100mV 0C Model Metastability Report - 29. Fast 1100mV 85C Model Setup Summary - 30. Fast 1100mV 85C Model Hold Summary - 31. Fast 1100mV 85C Model Recovery Summary - 32. Fast 1100mV 85C Model Removal Summary - 33. Fast 1100mV 85C Model Minimum Pulse Width Summary - 34. Setup Times - 35. Hold Times - 36. Clock to Output Times - 37. Minimum Clock to Output Times - 38. Fast 1100mV 85C Model Metastability Report - 39. Fast 1100mV 0C Model Setup Summary - 40. Fast 1100mV 0C Model Hold Summary - 41. Fast 1100mV 0C Model Recovery Summary - 42. Fast 1100mV 0C Model Removal Summary - 43. Fast 1100mV 0C Model Minimum Pulse Width Summary - 44. Setup Times - 45. Hold Times - 46. Clock to Output Times - 47. Minimum Clock to Output Times - 48. Fast 1100mV 0C Model Metastability Report - 49. Multicorner Timing Analysis Summary + 17. MTBF Summary + 18. Synchronizer Summary + 19. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years + 20. Slow 1100mV 0C Model Fmax Summary + 21. Slow 1100mV 0C Model Setup Summary + 22. Slow 1100mV 0C Model Hold Summary + 23. Slow 1100mV 0C Model Recovery Summary + 24. Slow 1100mV 0C Model Removal Summary + 25. Slow 1100mV 0C Model Minimum Pulse Width Summary + 26. Setup Times + 27. Hold Times + 28. Clock to Output Times + 29. Minimum Clock to Output Times + 30. MTBF Summary + 31. Synchronizer Summary + 32. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years + 33. Fast 1100mV 85C Model Setup Summary + 34. Fast 1100mV 85C Model Hold Summary + 35. Fast 1100mV 85C Model Recovery Summary + 36. Fast 1100mV 85C Model Removal Summary + 37. Fast 1100mV 85C Model Minimum Pulse Width Summary + 38. Setup Times + 39. Hold Times + 40. Clock to Output Times + 41. Minimum Clock to Output Times + 42. MTBF Summary + 43. Synchronizer Summary + 44. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years + 45. Fast 1100mV 0C Model Setup Summary + 46. Fast 1100mV 0C Model Hold Summary + 47. Fast 1100mV 0C Model Recovery Summary + 48. Fast 1100mV 0C Model Removal Summary + 49. Fast 1100mV 0C Model Minimum Pulse Width Summary 50. Setup Times 51. Hold Times 52. Clock to Output Times 53. Minimum Clock to Output Times - 54. Board Trace Model Assignments - 55. Input Transition Times - 56. Signal Integrity Metrics (Slow 1100mv 0c Model) - 57. Signal Integrity Metrics (Slow 1100mv 85c Model) - 58. Signal Integrity Metrics (Fast 1100mv 0c Model) - 59. Signal Integrity Metrics (Fast 1100mv 85c Model) - 60. Setup Transfers - 61. Hold Transfers - 62. Report TCCS - 63. Report RSKM - 64. Unconstrained Paths - 65. TimeQuest Timing Analyzer Messages + 54. MTBF Summary + 55. Synchronizer Summary + 56. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years + 57. Multicorner Timing Analysis Summary + 58. Setup Times + 59. Hold Times + 60. Clock to Output Times + 61. Minimum Clock to Output Times + 62. Board Trace Model Assignments + 63. Input Transition Times + 64. Signal Integrity Metrics (Slow 1100mv 0c Model) + 65. Signal Integrity Metrics (Slow 1100mv 85c Model) + 66. Signal Integrity Metrics (Fast 1100mv 0c Model) + 67. Signal Integrity Metrics (Fast 1100mv 85c Model) + 68. Setup Transfers + 69. Hold Transfers + 70. Report TCCS + 71. Report RSKM + 72. Unconstrained Paths + 73. TimeQuest Timing Analyzer Messages @@ -114,12 +122,12 @@ applicable agreement for further details. ; Number detected on machine ; 4 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.33 ; +; Average used ; 1.37 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 33.3% ; +; Processor 2 ; 36.7% ; ; Processors 3-4 ; 0.0% ; +----------------------------+-------------+ @@ -129,7 +137,7 @@ applicable agreement for further details. +---------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +---------------+--------+--------------------------+ -; de1_riscv.SDC ; OK ; Fri Aug 27 17:23:34 2021 ; +; de1_riscv.SDC ; OK ; Sat Aug 28 10:56:17 2021 ; +---------------+--------+--------------------------+ @@ -157,7 +165,7 @@ applicable agreement for further details. +-----------+-----------------+----------------------------------------------------------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +-----------+-----------------+----------------------------------------------------------------------------+------+ -; 85.26 MHz ; 85.26 MHz ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; +; 89.31 MHz ; 89.31 MHz ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; +-----------+-----------------+----------------------------------------------------------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -173,7 +181,7 @@ HTML report is unavailable in plain text report export. +----------------------------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+--------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.729 ; -126.223 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.197 ; -95.783 ; +----------------------------------------------------------------------------+--------+---------------+ @@ -182,7 +190,7 @@ HTML report is unavailable in plain text report export. +----------------------------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.281 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.266 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ @@ -209,28 +217,28 @@ No paths to report. +----------------------------------------------------------------------------+-------+---------------+ -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 0.848 ; 1.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 0.848 ; 1.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 0.800 ; 1.535 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 0.537 ; 1.036 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 0.698 ; 1.590 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 2.301 ; 3.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; -0.438 ; 0.353 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.707 ; 1.571 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; -0.197 ; 0.867 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 0.380 ; 1.376 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 0.163 ; 0.850 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; -0.322 ; 0.217 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 1.129 ; 2.049 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 2.286 ; 3.285 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 1.216 ; 2.080 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 2.301 ; 3.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 1.172 ; 2.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 0.834 ; 1.942 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 1.172 ; 2.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; -0.187 ; 0.869 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; -0.416 ; 0.790 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 2.873 ; 4.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.534 ; 0.859 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; -0.605 ; 0.090 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; -0.912 ; 0.016 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; -0.577 ; 0.402 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 0.128 ; 1.022 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; -1.518 ; -1.025 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 0.963 ; 1.365 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 2.873 ; 4.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 1.752 ; 2.499 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 1.529 ; 2.464 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------+ @@ -238,22 +246,22 @@ No paths to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 4.072 ; 3.504 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 3.249 ; 2.498 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 3.192 ; 2.501 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 3.722 ; 3.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 4.072 ; 3.504 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 3.232 ; 2.671 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; 2.271 ; 1.612 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 1.286 ; 0.605 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; 2.758 ; 2.185 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 2.390 ; 1.679 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 2.878 ; 2.400 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; 2.565 ; 1.980 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 2.732 ; 2.097 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 2.977 ; 2.395 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 2.888 ; 2.392 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 3.232 ; 2.671 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[*] ; CLOCK_50 ; 4.302 ; 3.725 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 3.367 ; 2.664 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 3.157 ; 2.342 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; 3.591 ; 2.859 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; 4.302 ; 3.725 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 3.581 ; 3.092 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 1.571 ; 1.170 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; 2.354 ; 1.795 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; 3.058 ; 2.482 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; 3.291 ; 2.737 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 2.945 ; 2.456 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; 3.581 ; 3.092 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 2.675 ; 2.107 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 3.114 ; 2.543 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 3.218 ; 2.673 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 3.468 ; 2.939 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ @@ -262,54 +270,57 @@ No paths to report. +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 14.397 ; 13.497 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 14.397 ; 13.497 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 12.554 ; 12.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 13.186 ; 12.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 13.466 ; 12.968 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 13.073 ; 12.669 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 13.697 ; 13.039 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 13.855 ; 13.136 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 14.821 ; 13.777 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 14.821 ; 13.777 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 14.193 ; 13.450 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 14.321 ; 13.382 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 13.918 ; 13.105 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 12.323 ; 12.183 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 13.546 ; 12.997 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 14.493 ; 13.554 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 14.577 ; 13.594 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 14.577 ; 13.594 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 13.334 ; 12.689 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 13.293 ; 12.654 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 13.415 ; 12.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 13.271 ; 12.652 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 12.836 ; 12.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 13.395 ; 12.746 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 15.528 ; 14.283 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 13.620 ; 12.915 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 12.933 ; 12.507 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 12.936 ; 12.659 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 15.528 ; 14.283 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 13.518 ; 12.824 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 13.765 ; 13.151 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 13.270 ; 12.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 14.396 ; 13.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 12.762 ; 12.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 13.611 ; 12.890 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 14.396 ; 13.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 14.278 ; 13.400 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 12.923 ; 12.634 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 13.863 ; 13.090 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 12.517 ; 12.337 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 13.665 ; 13.063 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 13.665 ; 12.913 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 12.819 ; 12.431 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 11.916 ; 11.815 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 12.759 ; 12.363 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 12.719 ; 12.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 12.148 ; 11.955 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 13.601 ; 13.063 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 14.191 ; 13.318 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 14.002 ; 13.202 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 13.120 ; 12.618 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 13.313 ; 12.753 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 13.693 ; 13.119 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 13.759 ; 12.974 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 12.800 ; 12.470 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 14.191 ; 13.318 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 14.089 ; 13.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 14.089 ; 13.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 12.430 ; 12.213 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 11.957 ; 11.913 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 12.990 ; 12.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 13.273 ; 12.643 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 13.295 ; 12.675 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 12.618 ; 12.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 14.089 ; 13.234 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 13.457 ; 12.840 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 13.921 ; 13.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 12.588 ; 12.366 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 12.623 ; 12.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 13.284 ; 12.846 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 13.455 ; 12.789 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 14.089 ; 13.234 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 13.619 ; 12.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 12.868 ; 12.384 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 13.020 ; 12.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 13.619 ; 12.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 13.452 ; 12.942 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 13.575 ; 12.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 13.547 ; 12.847 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 12.700 ; 12.379 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 13.903 ; 13.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 13.197 ; 12.664 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 13.581 ; 12.835 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 13.297 ; 12.673 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 13.903 ; 13.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 12.741 ; 12.370 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 12.477 ; 12.232 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 12.414 ; 12.191 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 13.948 ; 13.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 13.425 ; 12.769 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 13.810 ; 13.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 13.826 ; 13.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 12.646 ; 12.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 13.948 ; 13.129 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 13.937 ; 13.102 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 12.793 ; 12.471 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 12.801 ; 12.941 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 12.801 ; 12.941 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 12.782 ; 12.899 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ @@ -318,61 +329,123 @@ No paths to report. +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 11.271 ; 11.120 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 12.710 ; 12.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 11.271 ; 11.120 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 11.831 ; 11.508 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 12.124 ; 11.715 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 11.734 ; 11.427 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 12.073 ; 11.665 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 12.216 ; 11.763 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 11.082 ; 10.992 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 13.083 ; 12.344 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 12.665 ; 12.095 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 12.648 ; 11.993 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 12.266 ; 11.734 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 11.082 ; 10.992 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 12.033 ; 11.668 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 12.754 ; 12.116 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 11.423 ; 11.199 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 12.885 ; 12.185 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 11.738 ; 11.349 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 11.700 ; 11.316 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 11.826 ; 11.425 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 11.702 ; 11.324 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 11.423 ; 11.199 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 11.815 ; 11.417 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 11.516 ; 11.240 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 12.012 ; 11.562 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 11.516 ; 11.240 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 11.582 ; 11.397 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 13.726 ; 12.803 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 11.907 ; 11.481 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 12.228 ; 11.807 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 11.891 ; 11.566 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 11.250 ; 11.122 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 11.420 ; 11.229 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 11.974 ; 11.528 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 12.712 ; 12.064 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 12.595 ; 12.000 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 11.579 ; 11.379 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 12.208 ; 11.706 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 11.250 ; 11.122 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 10.700 ; 10.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 12.062 ; 11.566 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 11.406 ; 11.171 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 10.700 ; 10.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 11.342 ; 11.109 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 11.418 ; 11.250 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 10.895 ; 10.767 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 12.182 ; 11.779 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 11.448 ; 11.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 12.320 ; 11.814 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 11.662 ; 11.334 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 11.854 ; 11.468 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 12.274 ; 11.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 12.093 ; 11.596 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 11.448 ; 11.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 12.491 ; 11.917 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 10.744 ; 10.741 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 12.415 ; 11.868 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 11.163 ; 11.018 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 10.744 ; 10.741 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 11.442 ; 11.163 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 11.689 ; 11.310 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 11.714 ; 11.343 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 11.320 ; 11.228 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 11.310 ; 11.149 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 11.931 ; 11.522 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 12.275 ; 11.755 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 11.312 ; 11.150 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 11.310 ; 11.149 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 11.867 ; 11.558 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 11.854 ; 11.450 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 12.395 ; 11.835 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 11.333 ; 11.073 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 11.333 ; 11.073 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 11.451 ; 11.144 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 12.096 ; 11.657 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 12.042 ; 11.656 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 11.982 ; 11.544 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 11.955 ; 11.506 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 11.390 ; 11.162 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 11.118 ; 10.978 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 11.716 ; 11.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 11.932 ; 11.473 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 11.706 ; 11.327 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 12.243 ; 11.717 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 11.302 ; 11.098 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 11.152 ; 10.999 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 11.118 ; 10.978 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 11.339 ; 11.229 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 11.817 ; 11.427 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 12.120 ; 11.626 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 12.178 ; 11.750 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 11.339 ; 11.229 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 12.302 ; 11.761 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 12.258 ; 11.718 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 11.474 ; 11.243 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 10.599 ; 10.683 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 10.623 ; 10.733 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 10.599 ; 10.683 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ----------------------------------------------- -; Slow 1100mV 85C Model Metastability Report ; ----------------------------------------------- -No synchronizer chains to report. +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 1 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 17.536 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 79.4 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 + + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; GPIO[7] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Source Node ; GPIO[7] ; +; Synchronization Node ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 17.536 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; GPIO[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.080 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 8.456 ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + +-----------------------------------------------------------------------------------------------------------------+ @@ -380,7 +453,7 @@ No synchronizer chains to report. +-----------+-----------------+----------------------------------------------------------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +-----------+-----------------+----------------------------------------------------------------------------+------+ -; 84.14 MHz ; 84.14 MHz ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; +; 88.09 MHz ; 88.09 MHz ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; +-----------+-----------------+----------------------------------------------------------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -390,7 +463,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+--------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.885 ; -158.135 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.352 ; -121.670 ; +----------------------------------------------------------------------------+--------+---------------+ @@ -399,7 +472,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.260 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.247 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ @@ -421,33 +494,33 @@ No paths to report. ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; 1.666 ; 0.000 ; -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.753 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.758 ; 0.000 ; ; CLOCK_50 ; 9.673 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 0.702 ; 1.518 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 0.702 ; 1.518 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 0.585 ; 1.367 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 0.356 ; 0.888 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 0.490 ; 1.433 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 2.173 ; 3.235 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; -0.723 ; 0.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.534 ; 1.480 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; -0.425 ; 0.751 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 0.230 ; 1.305 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; -0.112 ; 0.686 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; -0.534 ; 0.092 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 0.847 ; 1.887 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 2.173 ; 3.235 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 0.950 ; 1.919 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 2.109 ; 3.221 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 0.981 ; 2.410 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 0.699 ; 1.824 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 0.981 ; 2.410 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; -0.379 ; 0.805 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; -0.703 ; 0.621 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 2.585 ; 4.241 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.417 ; 0.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; -0.805 ; -0.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; -1.104 ; -0.076 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; -0.767 ; 0.312 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; -0.065 ; 0.911 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; -1.669 ; -1.138 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 0.758 ; 1.223 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 2.585 ; 4.241 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 1.516 ; 2.359 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 1.239 ; 2.310 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------+ @@ -455,22 +528,22 @@ No paths to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 4.197 ; 3.624 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 3.311 ; 2.588 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 3.283 ; 2.577 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 3.831 ; 3.218 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 4.197 ; 3.624 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 3.341 ; 2.720 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; 2.465 ; 1.724 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 1.393 ; 0.663 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; 2.898 ; 2.280 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 2.472 ; 1.701 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 3.051 ; 2.517 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; 2.728 ; 2.072 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 2.934 ; 2.245 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 3.061 ; 2.427 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 3.081 ; 2.497 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 3.341 ; 2.720 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[*] ; CLOCK_50 ; 4.379 ; 3.793 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 3.381 ; 2.697 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 3.217 ; 2.374 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; 3.644 ; 2.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; 4.379 ; 3.793 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 3.685 ; 3.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 1.617 ; 1.188 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; 2.455 ; 1.832 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; 3.152 ; 2.520 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; 3.415 ; 2.830 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 3.069 ; 2.508 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; 3.685 ; 3.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 2.788 ; 2.146 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 3.171 ; 2.538 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 3.327 ; 2.721 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 3.589 ; 2.995 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ @@ -479,54 +552,57 @@ No paths to report. +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 14.181 ; 13.254 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 14.181 ; 13.254 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 12.223 ; 11.986 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 12.906 ; 12.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 13.182 ; 12.652 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 12.782 ; 12.350 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 13.425 ; 12.752 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 13.532 ; 12.811 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 14.619 ; 13.557 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 14.619 ; 13.557 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 13.960 ; 13.199 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 14.121 ; 13.171 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 13.698 ; 12.875 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 11.994 ; 11.831 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 13.287 ; 12.707 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 14.228 ; 13.261 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 14.369 ; 13.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 14.369 ; 13.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 13.096 ; 12.446 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 13.044 ; 12.404 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 13.160 ; 12.508 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 13.022 ; 12.394 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 12.544 ; 12.150 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 13.151 ; 12.492 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 15.365 ; 14.099 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 13.360 ; 12.645 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 12.661 ; 12.205 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 12.572 ; 12.267 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 15.365 ; 14.099 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 13.289 ; 12.592 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 13.513 ; 12.858 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 12.949 ; 12.487 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 14.189 ; 13.246 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 12.442 ; 12.133 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 13.320 ; 12.599 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 14.189 ; 13.246 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 14.055 ; 13.150 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 12.632 ; 12.297 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 13.604 ; 12.815 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 12.182 ; 11.978 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 13.429 ; 12.737 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 13.429 ; 12.671 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 12.530 ; 12.125 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 11.609 ; 11.493 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 12.474 ; 12.059 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 12.348 ; 12.086 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 11.845 ; 11.640 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 13.305 ; 12.737 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 13.992 ; 13.085 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 13.779 ; 12.963 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 12.857 ; 12.333 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 13.056 ; 12.486 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 13.462 ; 12.860 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 13.546 ; 12.751 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 12.535 ; 12.172 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 13.992 ; 13.085 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 13.862 ; 13.007 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 13.862 ; 13.007 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 12.110 ; 11.866 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 11.676 ; 11.611 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 12.760 ; 12.241 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 13.042 ; 12.404 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 13.041 ; 12.409 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 12.305 ; 12.109 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 13.878 ; 12.987 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 13.237 ; 12.601 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 13.715 ; 12.900 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 12.278 ; 12.022 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 12.364 ; 12.091 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 13.022 ; 12.549 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 13.230 ; 12.555 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 13.878 ; 12.987 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 13.372 ; 12.708 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 12.627 ; 12.136 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 12.790 ; 12.216 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 13.372 ; 12.708 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 13.222 ; 12.682 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 13.327 ; 12.629 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 13.321 ; 12.598 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 12.410 ; 12.059 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 13.696 ; 12.872 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 12.951 ; 12.392 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 13.367 ; 12.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 13.056 ; 12.408 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 13.696 ; 12.872 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 12.463 ; 12.069 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 12.210 ; 11.946 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 12.148 ; 11.895 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 13.741 ; 12.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 13.199 ; 12.528 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 13.591 ; 12.769 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 13.591 ; 12.868 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 12.339 ; 12.122 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 13.741 ; 12.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 13.734 ; 12.882 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 12.540 ; 12.184 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 12.502 ; 12.619 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 12.502 ; 12.619 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 12.467 ; 12.583 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ @@ -535,61 +611,123 @@ No paths to report. +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 11.043 ; 10.875 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 12.584 ; 11.944 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 11.043 ; 10.875 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 11.654 ; 11.295 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 11.937 ; 11.501 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 11.548 ; 11.212 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 11.903 ; 11.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 11.989 ; 11.538 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 10.855 ; 10.749 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 12.965 ; 12.214 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 12.519 ; 11.939 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 12.535 ; 11.872 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 12.139 ; 11.596 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 10.855 ; 10.749 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 11.894 ; 11.480 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 12.595 ; 11.926 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 11.251 ; 10.993 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 12.772 ; 12.051 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 11.604 ; 11.202 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 11.558 ; 11.164 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 11.681 ; 11.261 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 11.569 ; 11.167 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 11.251 ; 10.993 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 11.682 ; 11.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 11.313 ; 11.040 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 11.867 ; 11.390 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 11.353 ; 11.040 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 11.313 ; 11.115 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 13.632 ; 12.704 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 11.777 ; 11.342 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 12.078 ; 11.613 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 11.673 ; 11.328 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 11.020 ; 10.872 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 11.200 ; 10.986 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 11.790 ; 11.336 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 12.588 ; 11.934 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 12.462 ; 11.843 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 11.400 ; 11.148 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 12.062 ; 11.531 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 11.020 ; 10.872 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 10.504 ; 10.433 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 11.932 ; 11.417 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 11.236 ; 10.969 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 10.504 ; 10.433 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 11.180 ; 10.906 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 11.145 ; 10.970 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 10.699 ; 10.558 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 11.979 ; 11.554 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 11.294 ; 11.028 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 12.204 ; 11.668 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 11.509 ; 11.150 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 11.711 ; 11.299 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 12.135 ; 11.666 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 11.979 ; 11.466 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 11.294 ; 11.028 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 12.384 ; 11.777 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 10.569 ; 10.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 12.299 ; 11.713 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 10.953 ; 10.778 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 10.569 ; 10.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 11.316 ; 11.019 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 11.563 ; 11.168 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 11.584 ; 11.176 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 11.106 ; 10.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 11.106 ; 10.914 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 11.803 ; 11.374 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 12.160 ; 11.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 11.106 ; 10.914 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 11.149 ; 10.969 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 11.705 ; 11.364 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 11.725 ; 11.308 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 12.281 ; 11.684 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 11.198 ; 10.920 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 11.198 ; 10.920 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 11.328 ; 10.990 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 11.962 ; 11.483 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 11.900 ; 11.492 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 11.854 ; 11.381 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 11.833 ; 11.351 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 11.224 ; 10.947 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 10.953 ; 10.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 11.582 ; 11.195 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 11.814 ; 11.348 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 11.568 ; 11.160 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 12.126 ; 11.585 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 11.139 ; 10.898 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 10.989 ; 10.814 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 10.953 ; 10.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 11.126 ; 10.988 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 11.686 ; 11.277 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 12.006 ; 11.473 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 12.050 ; 11.575 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 11.126 ; 10.988 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 12.183 ; 11.635 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 12.145 ; 11.586 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 11.318 ; 11.058 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 10.411 ; 10.495 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 10.448 ; 10.545 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 10.411 ; 10.495 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ---------------------------------------------- -; Slow 1100mV 0C Model Metastability Report ; ---------------------------------------------- -No synchronizer chains to report. +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 1 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 17.571 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 5.2 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 + + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; GPIO[7] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Source Node ; GPIO[7] ; +; Synchronization Node ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 17.571 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; GPIO[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.075 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 8.496 ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + +----------------------------------------------------------------------------------------------------+ @@ -597,7 +735,7 @@ No synchronizer chains to report. +----------------------------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.113 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.503 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ @@ -606,7 +744,7 @@ No synchronizer chains to report. +----------------------------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.163 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.154 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ @@ -628,113 +766,116 @@ No paths to report. ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; 1.666 ; 0.000 ; -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.889 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.888 ; 0.000 ; ; CLOCK_50 ; 9.336 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 0.528 ; 1.635 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 0.528 ; 1.626 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 0.435 ; 1.520 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 0.395 ; 1.178 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 0.439 ; 1.635 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 1.507 ; 2.852 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; -0.329 ; 0.796 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.338 ; 1.504 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; -0.119 ; 1.213 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 0.200 ; 1.570 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 0.058 ; 1.178 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; -0.306 ; 0.687 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 0.505 ; 1.707 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 1.180 ; 2.554 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 0.581 ; 1.871 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 1.507 ; 2.852 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Hold Times ; -+-----------+------------+-------+--------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+-------+--------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 2.296 ; 1.408 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 1.836 ; 0.812 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 1.807 ; 0.808 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 2.095 ; 1.189 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 2.296 ; 1.408 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 1.854 ; 0.915 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; 1.250 ; 0.246 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.712 ; -0.327 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; 1.529 ; 0.579 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 1.267 ; 0.183 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 1.586 ; 0.679 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; 1.451 ; 0.471 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 1.505 ; 0.527 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 1.694 ; 0.736 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 1.639 ; 0.710 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 1.854 ; 0.915 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+-------+--------+------------+----------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Clock to Output Times ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 9.066 ; 8.241 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 9.066 ; 8.241 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 7.579 ; 7.326 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 8.077 ; 7.640 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 8.313 ; 7.803 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 8.021 ; 7.593 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 8.475 ; 7.871 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 8.569 ; 7.932 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 9.398 ; 8.457 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 9.398 ; 8.457 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 8.901 ; 8.199 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 9.008 ; 8.156 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 8.746 ; 8.001 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 7.379 ; 7.191 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 8.397 ; 7.855 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 9.069 ; 8.225 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 9.268 ; 8.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 9.268 ; 8.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 8.269 ; 7.674 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 8.248 ; 7.661 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 8.306 ; 7.712 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 8.201 ; 7.630 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 7.861 ; 7.475 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 8.320 ; 7.718 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 10.029 ; 8.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 8.507 ; 7.852 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 7.987 ; 7.570 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 7.846 ; 7.543 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 10.029 ; 8.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 8.417 ; 7.779 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 8.566 ; 7.972 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 8.144 ; 7.689 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 9.134 ; 8.285 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 7.753 ; 7.435 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 8.425 ; 7.786 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 9.134 ; 8.285 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 9.022 ; 8.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 7.926 ; 7.591 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 8.681 ; 7.968 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 7.564 ; 7.339 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 8.532 ; 7.853 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 8.532 ; 7.853 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 7.856 ; 7.463 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 7.175 ; 7.022 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 7.805 ; 7.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 7.679 ; 7.414 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 7.338 ; 7.104 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 8.370 ; 7.827 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 0.692 ; 2.270 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 0.464 ; 1.837 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 0.692 ; 2.270 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; -0.037 ; 1.200 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; -0.145 ; 1.240 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 1.719 ; 3.429 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.339 ; 1.060 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; -0.452 ; 0.600 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; -0.605 ; 0.598 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; -0.373 ; 0.897 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; -0.021 ; 1.245 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; -1.060 ; -0.170 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 0.487 ; 1.358 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 1.719 ; 3.429 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 0.986 ; 2.118 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 0.864 ; 2.176 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 2.443 ; 1.566 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 1.878 ; 0.901 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 1.722 ; 0.631 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; 2.001 ; 1.020 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; 2.443 ; 1.566 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 2.083 ; 1.225 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.781 ; 0.016 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; 1.352 ; 0.408 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; 1.693 ; 0.753 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; 1.821 ; 0.909 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 1.684 ; 0.801 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; 2.083 ; 1.225 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 1.499 ; 0.536 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 1.689 ; 0.744 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 1.846 ; 0.908 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 1.921 ; 0.974 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +; HEX0[*] ; CLOCK_50 ; 8.963 ; 8.164 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 8.774 ; 8.038 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 8.038 ; 7.547 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 8.213 ; 7.680 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 8.510 ; 7.943 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 8.604 ; 7.891 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 7.795 ; 7.441 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 8.963 ; 8.164 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 8.830 ; 8.062 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 8.830 ; 8.062 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 7.520 ; 7.281 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 7.183 ; 7.067 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 8.034 ; 7.547 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 8.211 ; 7.628 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 8.222 ; 7.645 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 7.666 ; 7.468 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 8.818 ; 8.043 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 8.414 ; 7.834 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 8.726 ; 7.989 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 7.631 ; 7.371 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 7.716 ; 7.434 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 8.192 ; 7.738 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 8.385 ; 7.763 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 8.818 ; 8.043 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 8.516 ; 7.906 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 7.959 ; 7.496 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 8.090 ; 7.575 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 8.516 ; 7.906 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 8.404 ; 7.901 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 8.423 ; 7.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 8.452 ; 7.804 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 7.795 ; 7.442 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 8.761 ; 8.020 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 8.176 ; 7.663 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 8.521 ; 7.847 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 8.253 ; 7.670 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 8.761 ; 8.020 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 7.808 ; 7.429 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 7.635 ; 7.364 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 7.586 ; 7.331 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 8.793 ; 8.026 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 8.388 ; 7.773 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 8.657 ; 7.930 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 8.658 ; 8.001 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 7.697 ; 7.485 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 8.776 ; 8.019 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 8.793 ; 8.026 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 7.831 ; 7.486 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 7.522 ; 7.658 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 7.522 ; 7.658 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 7.508 ; 7.634 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------+ @@ -742,61 +883,123 @@ No paths to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 6.913 ; 6.715 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 8.097 ; 7.500 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 6.913 ; 6.715 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 7.368 ; 7.005 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 7.606 ; 7.170 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 7.316 ; 6.968 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 7.554 ; 7.151 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 7.645 ; 7.214 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 6.751 ; 6.603 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 8.391 ; 7.694 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 8.055 ; 7.493 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 8.052 ; 7.425 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 7.799 ; 7.278 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 6.751 ; 6.603 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 7.560 ; 7.168 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 8.075 ; 7.469 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 7.095 ; 6.832 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 8.296 ; 7.623 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 7.361 ; 6.971 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 7.344 ; 6.961 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 7.407 ; 7.005 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 7.315 ; 6.937 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 7.095 ; 6.832 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 7.427 ; 7.024 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 7.137 ; 6.909 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 7.596 ; 7.146 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 7.216 ; 6.920 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 7.137 ; 6.909 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 8.976 ; 8.098 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 7.500 ; 7.076 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 7.717 ; 7.277 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 7.419 ; 7.057 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 6.912 ; 6.734 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 7.049 ; 6.805 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 7.505 ; 7.079 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 8.168 ; 7.545 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 8.058 ; 7.481 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 7.216 ; 6.956 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 7.740 ; 7.243 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 6.912 ; 6.734 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 6.557 ; 6.447 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 7.625 ; 7.149 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 7.091 ; 6.822 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 6.557 ; 6.447 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 7.041 ; 6.776 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 7.009 ; 6.801 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 6.694 ; 6.515 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 7.610 ; 7.178 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 7.076 ; 6.808 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 7.807 ; 7.305 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 7.246 ; 6.893 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 7.419 ; 7.024 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 7.744 ; 7.282 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 7.644 ; 7.162 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 7.076 ; 6.808 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 7.979 ; 7.421 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 6.562 ; 6.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 7.870 ; 7.329 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 6.868 ; 6.686 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 6.562 ; 6.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 7.159 ; 6.860 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 7.314 ; 6.932 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 7.332 ; 6.952 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 6.982 ; 6.841 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 6.969 ; 6.761 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 7.558 ; 7.146 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 7.784 ; 7.269 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 6.969 ; 6.761 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 7.018 ; 6.813 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 7.422 ; 7.075 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 7.475 ; 7.063 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 7.849 ; 7.308 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 7.095 ; 6.812 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 7.095 ; 6.812 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 7.198 ; 6.883 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 7.669 ; 7.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 7.634 ; 7.235 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 7.524 ; 7.079 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 7.550 ; 7.102 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 7.108 ; 6.833 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 6.901 ; 6.717 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 7.360 ; 6.996 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 7.572 ; 7.128 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 7.355 ; 6.969 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 7.809 ; 7.295 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 7.024 ; 6.779 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 6.925 ; 6.734 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 6.901 ; 6.717 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 7.009 ; 6.856 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 7.473 ; 7.071 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 7.678 ; 7.189 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 7.718 ; 7.270 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 7.009 ; 6.856 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 7.835 ; 7.301 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 7.822 ; 7.292 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 7.132 ; 6.865 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 6.378 ; 6.474 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 6.396 ; 6.507 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 6.378 ; 6.474 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ----------------------------------------------- -; Fast 1100mV 85C Model Metastability Report ; ----------------------------------------------- -No synchronizer chains to report. +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 1 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 18.511 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 79.4 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 + + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; GPIO[7] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Source Node ; GPIO[7] ; +; Synchronization Node ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 18.511 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; GPIO[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.479 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 9.032 ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + +----------------------------------------------------------------------------------------------------+ @@ -804,7 +1007,7 @@ No synchronizer chains to report. +----------------------------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.512 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.812 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ @@ -813,7 +1016,7 @@ No synchronizer chains to report. +----------------------------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.147 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.141 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ @@ -835,57 +1038,57 @@ No paths to report. ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; 1.666 ; 0.000 ; -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.889 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.888 ; 0.000 ; ; CLOCK_50 ; 9.286 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 0.358 ; 1.486 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 0.358 ; 1.486 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 0.224 ; 1.352 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 0.218 ; 1.080 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 0.232 ; 1.452 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 1.251 ; 2.616 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; -0.493 ; 0.677 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.158 ; 1.348 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; -0.236 ; 1.107 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 0.096 ; 1.456 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; -0.124 ; 1.046 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; -0.447 ; 0.600 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 0.313 ; 1.552 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 0.958 ; 2.351 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 0.364 ; 1.670 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 1.251 ; 2.616 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Hold Times ; -+-----------+------------+-------+--------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+-------+--------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 2.324 ; 1.403 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 1.863 ; 0.839 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 1.856 ; 0.833 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 2.119 ; 1.175 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 2.324 ; 1.403 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 1.903 ; 0.919 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; 1.368 ; 0.328 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.814 ; -0.244 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; 1.581 ; 0.596 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 1.300 ; 0.199 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 1.670 ; 0.717 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; 1.545 ; 0.529 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 1.590 ; 0.571 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 1.737 ; 0.742 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 1.746 ; 0.758 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 1.903 ; 0.919 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+-------+--------+------------+----------------------------------------------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 0.539 ; 2.077 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 0.338 ; 1.679 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 0.539 ; 2.077 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; -0.167 ; 1.103 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; -0.291 ; 1.104 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 1.447 ; 3.120 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.193 ; 0.984 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; -0.563 ; 0.520 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; -0.671 ; 0.548 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; -0.456 ; 0.823 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; -0.154 ; 1.118 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; -1.126 ; -0.193 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 0.332 ; 1.250 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 1.447 ; 3.120 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 0.755 ; 1.924 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 0.643 ; 1.975 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 2.428 ; 1.516 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 1.868 ; 0.876 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 1.733 ; 0.631 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; 1.997 ; 0.997 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; 2.428 ; 1.516 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 2.105 ; 1.207 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.858 ; 0.041 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; 1.411 ; 0.433 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; 1.696 ; 0.721 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; 1.844 ; 0.898 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 1.735 ; 0.799 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; 2.105 ; 1.207 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 1.529 ; 0.529 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 1.691 ; 0.712 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 1.898 ; 0.913 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 1.951 ; 0.959 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------+ @@ -893,54 +1096,57 @@ No paths to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 8.559 ; 7.863 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 8.559 ; 7.863 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 7.125 ; 6.894 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 7.596 ; 7.215 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 7.830 ; 7.392 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 7.543 ; 7.173 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 7.987 ; 7.473 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 8.029 ; 7.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 8.872 ; 8.078 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 8.872 ; 8.078 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 8.387 ; 7.796 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 8.503 ; 7.787 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 8.251 ; 7.625 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 6.941 ; 6.762 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 7.908 ; 7.450 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 8.520 ; 7.800 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 8.728 ; 7.969 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 8.728 ; 7.969 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 7.812 ; 7.313 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 7.778 ; 7.289 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 7.840 ; 7.340 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 7.743 ; 7.268 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 7.401 ; 7.070 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 7.848 ; 7.346 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 9.456 ; 8.495 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 8.000 ; 7.450 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 7.513 ; 7.153 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 7.334 ; 7.050 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 9.456 ; 8.495 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 7.957 ; 7.420 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 8.055 ; 7.547 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 7.620 ; 7.223 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 8.610 ; 7.891 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 7.267 ; 6.980 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 7.903 ; 7.363 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 8.610 ; 7.891 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 8.497 ; 7.816 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 7.453 ; 7.154 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 8.167 ; 7.563 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 7.087 ; 6.880 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 8.033 ; 7.466 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 8.033 ; 7.466 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 7.398 ; 7.062 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 6.748 ; 6.610 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 7.334 ; 7.001 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 7.183 ; 6.936 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 6.895 ; 6.690 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 7.868 ; 7.392 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 8.459 ; 7.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 8.289 ; 7.667 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 7.574 ; 7.154 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 7.728 ; 7.276 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 8.034 ; 7.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 8.116 ; 7.518 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 7.353 ; 7.044 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 8.459 ; 7.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 8.329 ; 7.683 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 8.329 ; 7.683 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 7.063 ; 6.844 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 6.786 ; 6.678 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 7.590 ; 7.183 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 7.757 ; 7.268 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 7.747 ; 7.262 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 7.206 ; 7.013 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 8.305 ; 7.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 7.930 ; 7.432 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 8.242 ; 7.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 7.166 ; 6.926 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 7.294 ; 7.042 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 7.730 ; 7.328 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 7.911 ; 7.394 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 8.305 ; 7.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 8.007 ; 7.492 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 7.502 ; 7.117 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 7.631 ; 7.194 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 8.007 ; 7.492 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 7.921 ; 7.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 7.944 ; 7.405 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 7.954 ; 7.411 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 7.324 ; 7.014 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 8.258 ; 7.636 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 7.697 ; 7.257 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 8.037 ; 7.469 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 7.772 ; 7.278 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 8.258 ; 7.636 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 7.344 ; 7.017 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 7.193 ; 6.953 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 7.145 ; 6.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 8.289 ; 7.647 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 7.905 ; 7.387 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 8.167 ; 7.552 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 8.153 ; 7.592 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 7.224 ; 7.022 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 8.278 ; 7.643 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 8.289 ; 7.647 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 7.393 ; 7.091 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 7.159 ; 7.266 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 7.159 ; 7.266 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 7.141 ; 7.244 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ @@ -949,61 +1155,123 @@ No paths to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 6.503 ; 6.327 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 7.656 ; 7.159 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 6.503 ; 6.327 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 6.938 ; 6.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 7.170 ; 6.798 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 6.891 ; 6.589 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 7.131 ; 6.795 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 7.170 ; 6.810 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 6.355 ; 6.216 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 7.931 ; 7.354 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 7.592 ; 7.129 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 7.613 ; 7.095 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 7.371 ; 6.940 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 6.355 ; 6.216 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 7.142 ; 6.804 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 7.601 ; 7.088 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 6.700 ; 6.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 7.825 ; 7.261 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 6.974 ; 6.650 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 6.945 ; 6.628 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 7.011 ; 6.676 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 6.930 ; 6.615 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 6.700 ; 6.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 7.027 ; 6.690 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 6.669 ; 6.462 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 7.166 ; 6.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 6.803 ; 6.544 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 6.669 ; 6.462 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 8.464 ; 7.738 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 7.108 ; 6.755 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 7.266 ; 6.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 6.949 ; 6.633 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 6.480 ; 6.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 6.610 ; 6.394 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 7.056 ; 6.697 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 7.708 ; 7.188 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 7.598 ; 7.116 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 6.796 ; 6.560 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 7.301 ; 6.879 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 6.480 ; 6.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 6.175 ; 6.074 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 7.197 ; 6.799 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 6.698 ; 6.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 6.175 ; 6.074 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 6.639 ; 6.405 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 6.555 ; 6.370 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 6.298 ; 6.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 7.160 ; 6.785 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 6.692 ; 6.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 7.398 ; 6.973 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 6.848 ; 6.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 7.003 ; 6.660 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 7.320 ; 6.923 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 7.230 ; 6.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 6.692 ; 6.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 7.543 ; 7.077 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 6.210 ; 6.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 7.449 ; 6.992 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 6.460 ; 6.290 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 6.210 ; 6.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 6.782 ; 6.534 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 6.930 ; 6.612 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 6.938 ; 6.611 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 6.566 ; 6.430 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 6.550 ; 6.360 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 7.134 ; 6.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 7.369 ; 6.940 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 6.550 ; 6.360 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 6.644 ; 6.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 7.014 ; 6.709 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 7.070 ; 6.731 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 7.408 ; 6.955 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 6.699 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 6.706 ; 6.472 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 6.807 ; 6.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 7.230 ; 6.845 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 7.198 ; 6.857 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 7.123 ; 6.744 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 7.125 ; 6.749 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 6.699 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 6.508 ; 6.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 6.949 ; 6.629 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 7.158 ; 6.787 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 6.943 ; 6.617 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 7.374 ; 6.948 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 6.627 ; 6.409 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 6.533 ; 6.364 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 6.508 ; 6.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 6.580 ; 6.437 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 7.059 ; 6.723 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 7.263 ; 6.853 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 7.287 ; 6.903 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 6.580 ; 6.437 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 7.404 ; 6.962 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 7.388 ; 6.951 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 6.741 ; 6.509 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 6.046 ; 6.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 6.068 ; 6.158 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 6.046 ; 6.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ---------------------------------------------- -; Fast 1100mV 0C Model Metastability Report ; ---------------------------------------------- -No synchronizer chains to report. +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 1 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 18.610 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 5.2 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 + + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; GPIO[7] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Source Node ; GPIO[7] ; +; Synchronization Node ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 18.610 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; GPIO[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.504 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 9.106 ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + +-------------------------------------------------------------------------------------------------------------------------------------------+ @@ -1011,39 +1279,39 @@ No synchronizer chains to report. +-----------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+ ; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; +-----------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+ -; Worst-case Slack ; -1.885 ; 0.147 ; N/A ; N/A ; 1.666 ; +; Worst-case Slack ; -1.352 ; 0.141 ; N/A ; N/A ; 1.666 ; ; CLOCK_50 ; N/A ; N/A ; N/A ; N/A ; 9.286 ; ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 1.666 ; -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.885 ; 0.147 ; N/A ; N/A ; 3.753 ; -; Design-wide TNS ; -158.135 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.352 ; 0.141 ; N/A ; N/A ; 3.758 ; +; Design-wide TNS ; -121.67 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ; CLOCK_50 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -158.135 ; 0.000 ; N/A ; N/A ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -121.670 ; 0.000 ; N/A ; N/A ; 0.000 ; +-----------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+ -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 0.848 ; 1.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 0.848 ; 1.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 0.800 ; 1.535 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 0.537 ; 1.178 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 0.698 ; 1.635 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 2.301 ; 3.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; -0.329 ; 0.796 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.707 ; 1.571 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; -0.119 ; 1.213 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 0.380 ; 1.570 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 0.163 ; 1.178 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; -0.306 ; 0.687 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 1.129 ; 2.049 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 2.286 ; 3.285 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 1.216 ; 2.080 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 2.301 ; 3.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 1.172 ; 2.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 0.834 ; 1.942 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 1.172 ; 2.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; -0.037 ; 1.200 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; -0.145 ; 1.240 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 2.873 ; 4.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.534 ; 1.060 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; -0.452 ; 0.600 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; -0.605 ; 0.598 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; -0.373 ; 0.897 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 0.128 ; 1.245 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; -1.060 ; -0.170 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 0.963 ; 1.365 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 2.873 ; 4.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 1.752 ; 2.499 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 1.529 ; 2.464 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------+ @@ -1051,22 +1319,22 @@ No synchronizer chains to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 4.197 ; 3.624 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 3.311 ; 2.588 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 3.283 ; 2.577 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 3.831 ; 3.218 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 4.197 ; 3.624 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 3.341 ; 2.720 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; 2.465 ; 1.724 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 1.393 ; 0.663 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; 2.898 ; 2.280 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 2.472 ; 1.701 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 3.051 ; 2.517 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; 2.728 ; 2.072 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 2.934 ; 2.245 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 3.061 ; 2.427 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 3.081 ; 2.497 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 3.341 ; 2.720 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[*] ; CLOCK_50 ; 4.379 ; 3.793 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 3.381 ; 2.697 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 3.217 ; 2.374 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; 3.644 ; 2.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; 4.379 ; 3.793 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 3.685 ; 3.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 1.617 ; 1.188 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; 2.455 ; 1.832 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; 3.152 ; 2.520 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; 3.415 ; 2.830 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 3.069 ; 2.508 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; 3.685 ; 3.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 2.788 ; 2.146 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 3.171 ; 2.543 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 3.327 ; 2.721 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 3.589 ; 2.995 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ @@ -1075,54 +1343,57 @@ No synchronizer chains to report. +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 14.397 ; 13.497 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 14.397 ; 13.497 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 12.554 ; 12.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 13.186 ; 12.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 13.466 ; 12.968 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 13.073 ; 12.669 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 13.697 ; 13.039 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 13.855 ; 13.136 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 14.821 ; 13.777 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 14.821 ; 13.777 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 14.193 ; 13.450 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 14.321 ; 13.382 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 13.918 ; 13.105 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 12.323 ; 12.183 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 13.546 ; 12.997 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 14.493 ; 13.554 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 14.577 ; 13.594 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 14.577 ; 13.594 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 13.334 ; 12.689 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 13.293 ; 12.654 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 13.415 ; 12.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 13.271 ; 12.652 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 12.836 ; 12.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 13.395 ; 12.746 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 15.528 ; 14.283 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 13.620 ; 12.915 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 12.933 ; 12.507 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 12.936 ; 12.659 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 15.528 ; 14.283 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 13.518 ; 12.824 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 13.765 ; 13.151 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 13.270 ; 12.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 14.396 ; 13.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 12.762 ; 12.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 13.611 ; 12.890 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 14.396 ; 13.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 14.278 ; 13.400 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 12.923 ; 12.634 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 13.863 ; 13.090 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 12.517 ; 12.337 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 13.665 ; 13.063 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 13.665 ; 12.913 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 12.819 ; 12.431 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 11.916 ; 11.815 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 12.759 ; 12.363 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 12.719 ; 12.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 12.148 ; 11.955 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 13.601 ; 13.063 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 14.191 ; 13.318 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 14.002 ; 13.202 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 13.120 ; 12.618 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 13.313 ; 12.753 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 13.693 ; 13.119 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 13.759 ; 12.974 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 12.800 ; 12.470 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 14.191 ; 13.318 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 14.089 ; 13.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 14.089 ; 13.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 12.430 ; 12.213 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 11.957 ; 11.913 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 12.990 ; 12.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 13.273 ; 12.643 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 13.295 ; 12.675 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 12.618 ; 12.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 14.089 ; 13.234 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 13.457 ; 12.840 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 13.921 ; 13.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 12.588 ; 12.366 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 12.623 ; 12.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 13.284 ; 12.846 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 13.455 ; 12.789 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 14.089 ; 13.234 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 13.619 ; 12.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 12.868 ; 12.384 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 13.020 ; 12.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 13.619 ; 12.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 13.452 ; 12.942 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 13.575 ; 12.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 13.547 ; 12.847 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 12.700 ; 12.379 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 13.903 ; 13.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 13.197 ; 12.664 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 13.581 ; 12.835 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 13.297 ; 12.673 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 13.903 ; 13.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 12.741 ; 12.370 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 12.477 ; 12.232 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 12.414 ; 12.191 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 13.948 ; 13.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 13.425 ; 12.769 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 13.810 ; 13.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 13.826 ; 13.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 12.646 ; 12.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 13.948 ; 13.129 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 13.937 ; 13.102 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 12.793 ; 12.471 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 12.801 ; 12.941 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 12.801 ; 12.941 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 12.782 ; 12.899 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ @@ -1131,54 +1402,57 @@ No synchronizer chains to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 6.503 ; 6.327 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 7.656 ; 7.159 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 6.503 ; 6.327 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 6.938 ; 6.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 7.170 ; 6.798 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 6.891 ; 6.589 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 7.131 ; 6.795 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 7.170 ; 6.810 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 6.355 ; 6.216 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 7.931 ; 7.354 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 7.592 ; 7.129 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 7.613 ; 7.095 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 7.371 ; 6.940 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 6.355 ; 6.216 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 7.142 ; 6.804 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 7.601 ; 7.088 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 6.700 ; 6.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 7.825 ; 7.261 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 6.974 ; 6.650 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 6.945 ; 6.628 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 7.011 ; 6.676 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 6.930 ; 6.615 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 6.700 ; 6.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 7.027 ; 6.690 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 6.669 ; 6.462 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 7.166 ; 6.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 6.803 ; 6.544 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 6.669 ; 6.462 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 8.464 ; 7.738 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 7.108 ; 6.755 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 7.266 ; 6.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 6.949 ; 6.633 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 6.480 ; 6.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 6.610 ; 6.394 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 7.056 ; 6.697 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 7.708 ; 7.188 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 7.598 ; 7.116 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 6.796 ; 6.560 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 7.301 ; 6.879 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 6.480 ; 6.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 6.175 ; 6.074 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 7.197 ; 6.799 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 6.698 ; 6.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 6.175 ; 6.074 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 6.639 ; 6.405 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 6.555 ; 6.370 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 6.298 ; 6.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 7.160 ; 6.785 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 6.692 ; 6.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 7.398 ; 6.973 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 6.848 ; 6.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 7.003 ; 6.660 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 7.320 ; 6.923 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 7.230 ; 6.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 6.692 ; 6.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 7.543 ; 7.077 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 6.210 ; 6.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 7.449 ; 6.992 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 6.460 ; 6.290 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 6.210 ; 6.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 6.782 ; 6.534 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 6.930 ; 6.612 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 6.938 ; 6.611 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 6.566 ; 6.430 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 6.550 ; 6.360 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 7.134 ; 6.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 7.369 ; 6.940 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 6.550 ; 6.360 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 6.644 ; 6.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 7.014 ; 6.709 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 7.070 ; 6.731 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 7.408 ; 6.955 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 6.699 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 6.706 ; 6.472 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 6.807 ; 6.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 7.230 ; 6.845 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 7.198 ; 6.857 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 7.123 ; 6.744 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 7.125 ; 6.749 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 6.699 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 6.508 ; 6.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 6.949 ; 6.629 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 7.158 ; 6.787 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 6.943 ; 6.617 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 7.374 ; 6.948 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 6.627 ; 6.409 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 6.533 ; 6.364 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 6.508 ; 6.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 6.580 ; 6.437 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 7.059 ; 6.723 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 7.263 ; 6.853 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 7.287 ; 6.903 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 6.580 ; 6.437 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 7.404 ; 6.962 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 7.388 ; 6.951 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 6.741 ; 6.509 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 6.046 ; 6.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 6.068 ; 6.158 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 6.046 ; 6.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ @@ -1328,9 +1602,7 @@ No synchronizer chains to report. ; GPIO[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; GPIO[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; GPIO[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; @@ -1359,6 +1631,8 @@ No synchronizer chains to report. ; GPIO[33] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[34] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[35] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ @@ -1413,9 +1687,7 @@ No synchronizer chains to report. ; GPIO[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; GPIO[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; GPIO[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; @@ -1444,6 +1716,8 @@ No synchronizer chains to report. ; GPIO[33] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[34] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[35] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; KEY[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; @@ -1608,9 +1882,7 @@ No synchronizer chains to report. ; GPIO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; ; GPIO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; ; GPIO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; -; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; ; GPIO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; -; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; ; GPIO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; ; GPIO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; ; GPIO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; @@ -1639,6 +1911,8 @@ No synchronizer chains to report. ; GPIO[33] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; ; GPIO[34] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; ; GPIO[35] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; +; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -1788,9 +2062,7 @@ No synchronizer chains to report. ; GPIO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; ; GPIO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; ; GPIO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; -; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; ; GPIO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; -; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; ; GPIO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; ; GPIO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; ; GPIO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; @@ -1819,6 +2091,8 @@ No synchronizer chains to report. ; GPIO[33] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; ; GPIO[34] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; ; GPIO[35] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; +; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -1968,9 +2242,7 @@ No synchronizer chains to report. ; GPIO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; ; GPIO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; ; GPIO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; -; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; ; GPIO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; -; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; ; GPIO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; ; GPIO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; ; GPIO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; @@ -1999,6 +2271,8 @@ No synchronizer chains to report. ; GPIO[33] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; ; GPIO[34] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; ; GPIO[35] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; +; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -2148,9 +2422,7 @@ No synchronizer chains to report. ; GPIO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; ; GPIO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; ; GPIO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; -; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; ; GPIO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; -; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; ; GPIO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; ; GPIO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; ; GPIO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; @@ -2179,6 +2451,8 @@ No synchronizer chains to report. ; GPIO[33] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; ; GPIO[34] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; ; GPIO[35] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; +; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -2187,7 +2461,7 @@ No synchronizer chains to report. +----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 49532597 ; 0 ; 0 ; 0 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 47863402 ; 0 ; 0 ; 0 ; +----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -2197,7 +2471,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 49532597 ; 0 ; 0 ; 0 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 47863402 ; 0 ; 0 ; 0 ; +----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -2222,9 +2496,9 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 14 ; 14 ; -; Unconstrained Input Port Paths ; 323 ; 323 ; -; Unconstrained Output Ports ; 42 ; 42 ; -; Unconstrained Output Port Paths ; 42 ; 42 ; +; Unconstrained Input Port Paths ; 351 ; 351 ; +; Unconstrained Output Ports ; 44 ; 44 ; +; Unconstrained Output Port Paths ; 44 ; 44 ; +---------------------------------+-------+------+ @@ -2238,12 +2512,15 @@ Warning (125092): Tcl Script File alu/add_sub_s.qip not found Info: ******************************************************************* Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version - Info: Processing started: Fri Aug 27 17:23:29 2021 + Info: Processing started: Sat Aug 28 10:56:13 2021 Info: Command: quartus_sta de1_riscv -c de1_riscv Info: qsta_default_script.tcl version: #1 Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead. Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity altera_std_synchronizer + Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332104): Reading SDC File: 'de1_riscv.SDC' Warning (332049): Ignored create_clock at de1_riscv.sdc(20): Time value "1.536 MH" is not valid Info (332050): create_clock -period "1.536 MH" -name clk_audbck [get_ports AUD_BCLK] @@ -2386,14 +2663,14 @@ Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1100mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -1.729 +Info (332146): Worst-case setup slack is -1.197 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -1.729 -126.223 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk -Info (332146): Worst-case hold slack is 0.281 + Info (332119): -1.197 -95.783 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk +Info (332146): Worst-case hold slack is 0.266 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.281 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 0.266 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 1.666 @@ -2402,6 +2679,19 @@ Info (332146): Worst-case minimum pulse width slack is 1.666 Info (332119): 1.666 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] Info (332119): 3.775 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 9.670 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 1 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 1 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 17.536 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 79.4 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 Info: Analyzing Slow 1100mV 0C Model Info (334003): Started post-fitting delay annotation Warning (334000): Timing characteristics of device 5CSEMA5F31C6 are preliminary @@ -2517,22 +2807,35 @@ Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQue Warning (332061): Virtual clock clk_core is never referenced in any input or output delay assignment. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -1.885 +Info (332146): Worst-case setup slack is -1.352 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -1.885 -158.135 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk -Info (332146): Worst-case hold slack is 0.260 + Info (332119): -1.352 -121.670 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk +Info (332146): Worst-case hold slack is 0.247 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.260 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 0.247 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 1.666 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.666 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] - Info (332119): 3.753 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 3.758 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 9.673 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 1 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 1 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 17.571 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 5.2 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 Info: Analyzing Fast 1100mV 85C Model Info (334003): Started post-fitting delay annotation Warning (334000): Timing characteristics of device 5CSEMA5F31C6 are preliminary @@ -2646,22 +2949,35 @@ Info (332097): The following timing edges are non-unate. TimeQuest will assume Info (332098): From: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0CLKMUX_0 to: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0MEMORYREGOUT Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Warning (332061): Virtual clock clk_core is never referenced in any input or output delay assignment. -Info (332146): Worst-case setup slack is 3.113 +Info (332146): Worst-case setup slack is 3.503 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 3.113 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk -Info (332146): Worst-case hold slack is 0.163 + Info (332119): 3.503 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk +Info (332146): Worst-case hold slack is 0.154 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.163 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 0.154 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 1.666 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.666 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] - Info (332119): 3.889 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 3.888 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 9.336 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 1 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 1 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 18.511 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 79.4 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 Info: Analyzing Fast 1100mV 0C Model Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL from: refclkin to: fbclk @@ -2772,27 +3088,40 @@ Info (332097): The following timing edges are non-unate. TimeQuest will assume Info (332098): From: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0CLKMUX_0 to: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0MEMORYREGOUT Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Warning (332061): Virtual clock clk_core is never referenced in any input or output delay assignment. -Info (332146): Worst-case setup slack is 3.512 +Info (332146): Worst-case setup slack is 3.812 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 3.512 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk -Info (332146): Worst-case hold slack is 0.147 + Info (332119): 3.812 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk +Info (332146): Worst-case hold slack is 0.141 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.147 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 0.141 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 1.666 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.666 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] - Info (332119): 3.889 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 3.888 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 9.286 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 1 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 1 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 18.610 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 5.2 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 27 warnings - Info: Peak virtual memory: 1135 megabytes - Info: Processing ended: Fri Aug 27 17:24:01 2021 + Info: Peak virtual memory: 1136 megabytes + Info: Processing ended: Sat Aug 28 10:56:45 2021 Info: Elapsed time: 00:00:32 Info: Total CPU time (on all processors): 00:00:42 diff --git a/examples/hdl4se_riscv/de1/de1_riscv.sta.summary b/examples/hdl4se_riscv/de1/de1_riscv.sta.summary index b3f81d6..f5e166b 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.sta.summary +++ b/examples/hdl4se_riscv/de1/de1_riscv.sta.summary @@ -3,11 +3,11 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : -1.729 -TNS : -126.223 +Slack : -1.197 +TNS : -95.783 Type : Slow 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 0.281 +Slack : 0.266 TNS : 0.000 Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]' @@ -23,11 +23,11 @@ Slack : 9.670 TNS : 0.000 Type : Slow 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : -1.885 -TNS : -158.135 +Slack : -1.352 +TNS : -121.670 Type : Slow 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 0.260 +Slack : 0.247 TNS : 0.000 Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]' @@ -35,7 +35,7 @@ Slack : 1.666 TNS : 0.000 Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 3.753 +Slack : 3.758 TNS : 0.000 Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50' @@ -43,11 +43,11 @@ Slack : 9.673 TNS : 0.000 Type : Fast 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 3.113 +Slack : 3.503 TNS : 0.000 Type : Fast 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 0.163 +Slack : 0.154 TNS : 0.000 Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]' @@ -55,7 +55,7 @@ Slack : 1.666 TNS : 0.000 Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 3.889 +Slack : 3.888 TNS : 0.000 Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50' @@ -63,11 +63,11 @@ Slack : 9.336 TNS : 0.000 Type : Fast 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 3.512 +Slack : 3.812 TNS : 0.000 Type : Fast 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 0.147 +Slack : 0.141 TNS : 0.000 Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]' @@ -75,7 +75,7 @@ Slack : 1.666 TNS : 0.000 Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 3.889 +Slack : 3.888 TNS : 0.000 Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50' diff --git a/examples/hdl4se_riscv/de1/de1_riscv_v2.v b/examples/hdl4se_riscv/de1/de1_riscv_v2.v new file mode 100644 index 0000000..901b54b --- /dev/null +++ b/examples/hdl4se_riscv/de1/de1_riscv_v2.v @@ -0,0 +1,235 @@ + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +`define USECLOCK50_1 + +module de1_riscv( + + //////////// ADC ////////// + output ADC_CONVST, + output ADC_DIN, + input ADC_DOUT, + output ADC_SCLK, + + //////////// Audio ////////// + input AUD_ADCDAT, + inout AUD_ADCLRCK, + inout AUD_BCLK, + output AUD_DACDAT, + inout AUD_DACLRCK, + output AUD_XCK, + + //////////// CLOCK ////////// + input CLOCK2_50, + input CLOCK3_50, + input CLOCK4_50, + input CLOCK_50, + + //////////// SDRAM ////////// + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [15:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N, + + //////////// I2C for Audio and Video-In ////////// + output FPGA_I2C_SCLK, + inout FPGA_I2C_SDAT, + + //////////// SEG7 ////////// + output [6:0] HEX0, + output [6:0] HEX1, + output [6:0] HEX2, + output [6:0] HEX3, + output [6:0] HEX4, + output [6:0] HEX5, + + //////////// IR ////////// + input IRDA_RXD, + output IRDA_TXD, + + //////////// KEY ////////// + input [3:0] KEY, + + //////////// LED ////////// + output [9:0] LEDR, + + //////////// PS2 ////////// + inout PS2_CLK, + inout PS2_CLK2, + inout PS2_DAT, + inout PS2_DAT2, + + //////////// SW ////////// + input [9:0] SW, + + //////////// Video-In ////////// + input TD_CLK27, + input [7:0] TD_DATA, + input TD_HS, + output TD_RESET_N, + input TD_VS, + + //////////// VGA ////////// + output VGA_BLANK_N, + output [7:0] VGA_B, + output VGA_CLK, + output [7:0] VGA_G, + output VGA_HS, + output [7:0] VGA_R, + output VGA_SYNC_N, + output VGA_VS, + + //////////// GPIO_0, GPIO_0 connect to GPIO Default ////////// + inout [35:0] GPIO +); + + wire uart_tx; + wire uart_rx; + assign GPIO[5] = uart_tx; + assign GPIO[7] = 1'bz; + assign uart_rx = GPIO[7]; + +`ifdef USECLOCK50 + wire wClk = CLOCK_50; +`else + wire clk100MHz, clk75MHz, clklocked; + clk100M clk100(.refclk(CLOCK_50), + .rst(~KEY[3]), + .outclk_0(clk100MHz), + .outclk_1(clk75MHz), + .locked(clklocked)); + + wire wClk = clk100MHz; +`endif + wire nwReset = KEY[3]; + + wire wWrite, wRead; + wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey, bReadDataUart; + wire [3:0] bWriteMask; + + assign bReadDataKey = {18'b0, KEY, SW}; + + reg readcmd; + reg [31:0] readaddr; + + wire wRead_out = readcmd; + wire [31:0] bReadAddr_out = readaddr; + + + always @(posedge wClk) begin + if (!nwReset) begin + readcmd <= 1'b0; + readaddr <= 32'b0; + end else begin + readcmd <= wRead; + readaddr <= bReadAddr; + end + end + + assign bReadData = + ((bReadAddr_out & 32'hffffff00) == 32'hf0000000) ? bReadDataKey : ( + ((bReadAddr_out & 32'hffffc000) == 32'h00000000) ? bReadDataRam : ( + ((bReadAddr_out & 32'hffffff00) == 32'h00000100) ? bReadDataUart : (0) + ) + ); + + wire [10:0] ramaddr; + assign ramaddr = wWrite?bWriteAddr[12:2]:bReadAddr[12:2]; + + wire [4:0] regno; + wire [3:0] regena; + wire [31:0] regwrdata; + wire regwren; + wire [31:0] regrddata; + wire [2:0] uartaddr; + assign uartaddr = wWrite?bWriteAddr[4:2]:bReadAddr[4:2]; + altera_uart uart( + // inputs: + .address(uartaddr), + .begintransfer(SW[0]), + .chipselect((uartaddr & 32'hffffff00)==32'hf0000100), + .clk(wClk), + .read_n(~wRead), + .reset_n(nwReset), + .rxd(uart_rx), + .write_n(~wWrite), + .writedata(bWriteData), + + // outputs: + .dataavailable(LEDR[0]), + .irq(LEDR[1]), + .readdata(bReadDataUart), + .readyfordata(LEDR[2]), + .txd(uart_tx) + ); + + regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata); + ram8kb ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hffffc000) == 0)?wWrite:1'b0, bReadDataRam); + riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData, + regno, regena, regwrdata, regwren, regrddata); + + reg [6:0] led0; + reg [6:0] led1; + reg [6:0] led2; + reg [6:0] led3; + reg [6:0] led4; + reg [6:0] led5; + assign HEX0 = ~led0; + assign HEX1 = ~led1; + assign HEX2 = ~led2; + assign HEX3 = ~led3; + assign HEX4 = ~led4; + assign HEX5 = ~led5; + + + + always @(posedge wClk) begin + if (!nwReset) begin + led0 <= 8'h3f; + led1 <= 8'h3f; + led2 <= 8'h3f; + led3 <= 8'h3f; + led4 <= 8'h3f; + led5 <= 8'h3f; + end else begin + if (SW[8]) begin + led0 <= 8'h06; + led1 <= 8'h06; + led2 <= 8'h06; + led3 <= 8'h07; + led4 <= 8'h07; + led5 <= 8'h07; + end + else if (SW[9]) begin + led0 <= 8'h3f; + led1 <= 8'h06; + led2 <= 8'h5b; + led3 <= 8'h4f; + led4 <= 8'h66; + led5 <= 8'h6d; + end + else if (wWrite && ((bWriteAddr & 32'hffffff00) == 32'hf0000000)) begin + if (bWriteAddr[7:0] == 8'h10) begin + led0 <= bWriteData[6:0]; + led1 <= bWriteData[14:8]; + led2 <= bWriteData[22:16]; + led3 <= bWriteData[30:24]; + end else if (bWriteAddr[7:0] == 8'h14) begin + led4 <= bWriteData[6:0]; + led5 <= bWriteData[14:8]; + end + end + end + end + +endmodule + diff --git a/examples/hdl4se_riscv/de1/qsys/.qsys_edit/i-qsys.xml b/examples/hdl4se_riscv/de1/qsys/.qsys_edit/i-qsys.xml new file mode 100644 index 0000000..42540c8 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/.qsys_edit/i-qsys.xml @@ -0,0 +1,1848 @@ + + + + + + + + + + + + + ccontrol center + true + + false + + + + + + + + + + + + + + + + + + + + + + + + + dock.CContentArea.center + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Library + + true + + id + index + placeholder + + 0 + 0 + dock.single.Library + + + + + + + + + Library + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Hierarchy + + true + + id + index + placeholder + + 0 + 0 + dock.single.Hierarchy + + + + + + + + + Hierarchy + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.System\ Contents + + true + + id + index + placeholder + + 0 + 0 + dock.single.System\ Contents + + + + dock.single.Address\ Map + + true + + id + index + placeholder + + 1 + 1 + dock.single.Address\ Map + + + + dock.single.Instrumentation + + true + + id + index + placeholder + + 2 + 2 + dock.single.Instrumentation + + + + dock.single.Clock\ Settings + + true + + id + index + placeholder + + 3 + 3 + dock.single.Clock\ Settings + + + + dock.single.Instance\ Parameters + + true + + id + index + placeholder + + 4 + 4 + dock.single.Instance\ Parameters + + + + dock.single.Project\ Settings + + true + + id + index + placeholder + + 5 + 5 + dock.single.Project\ Settings + + + + dock.single.HDL\ Example + + true + + id + index + placeholder + + 6 + 6 + dock.single.HDL\ Example + + + + dock.single.Generation + + true + + id + index + placeholder + + 7 + 7 + dock.single.Generation + + + + dock.single.Connections + + true + + id + index + placeholder + + 8 + 8 + dock.single.Connections + + + + dock.single.Data\ Path + + true + + id + index + placeholder + + 9 + 9 + dock.single.Data\ Path + + + + dock.single.Domains + + true + + id + index + placeholder + + 10 + 10 + dock.single.Domains + + + + + + + + + System Contents + + + + + + + + + + Address Map + + + + + + + + + + Instrumentation + + + + + + + + + + Clock Settings + + + + + + + + + + Instance Parameters + + + + + + + + + + Project Settings + + + + + + + + + + HDL Example + + + + + + + + + + Generation + + + + + + + + + + Connections + + + + + + + + + + Data Path + + + + + + + + + + Domains + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Parameter\ Editor + + true + + id + index + placeholder + + 0 + 0 + dock.single.Parameter\ Editor + + + + + + + + + Parameter Editor + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Block\ Symbol + + true + + id + index + placeholder + + 0 + 0 + dock.single.Block\ Symbol + + + + dock.single.Element\ Docs + + true + + id + index + placeholder + + 1 + 1 + dock.single.Element\ Docs + + + + + + + + + Block Symbol + + + + + + + + + + Element Docs + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Presets + + true + + id + index + placeholder + + 0 + 0 + dock.single.Presets + + + + + + + + + Presets + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Messages + + true + + id + index + placeholder + + 0 + 0 + dock.single.Messages + + + + + + + + + Messages + + + + + + + + + + + + + + ccontrol south + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + ccontrol north + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + external + true + + + 0 + dock.PlaceholderList + + + + + + + dock.CExternalizeArea + + + + + + + + + ccontrol east + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + ccontrol west + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ccontrol center + true + + false + + + + + dock.single.Library + + + 0 + dock.PlaceholderList + + + + + dock.single.Hierarchy + + + + + + + + + dock.single.Clocks + dock.single.Project\ Settings + dock.single.Generation + dock.single.Instrumentation\ \-\ Beta + dock.single.Connections + dock.single.Parameters + dock.single.Connections\ \-\ Beta + dock.single.Clock\ Settings + dock.single.Address\ Map + dock.single.System\ Contents + dock.single.Interconnect\ Requirements + dock.single.Instance\ Parameters + dock.single.Clock\ Domains\ \-\ Beta + dock.single.Data\ Path + dock.single.Data\ Path\ \-\ Beta + dock.single.Instrumentation + dock.single.Domains + dock.single.HDL\ Example + + + 0 + dock.PlaceholderList + + + + + dock.single.Parameter\ Editor + + + + + + + dock.single.Element\ Docs + dock.single.Block\ Symbol + + + + + dock.single.Presets + + + + + + + dock.single.Messages + + + 0 + dock.PlaceholderList + + + + + + + + + + dock.CContentArea.center + + + + + + + + Library + + + + + + + + + + Hierarchy + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.System\ Contents + + true + + id + index + placeholder + + 0 + 0 + dock.single.System\ Contents + + + + dock.single.Address\ Map + + true + + id + index + placeholder + + 1 + 1 + dock.single.Address\ Map + + + + dock.single.Instrumentation\ \-\ Beta + + + + + dock.single.Instance\ Parameters + + + + + dock.single.Project\ Settings + + true + + id + index + placeholder + + 2 + 2 + dock.single.Project\ Settings + + + + dock.single.Clocks + + + + + dock.single.Clock\ Domains\ \-\ Beta + + + + + dock.single.Connections\ \-\ Beta + + + + + dock.single.Interconnect\ Requirements + + + + + dock.single.Data\ Path\ \-\ Beta + + + + + dock.single.Parameters + + + + + + + + + + System Contents + + + + + + + + + + Address Map + + + + + + + + + + Project Settings + + + + + + + + + + + + Messages + + + + + + + + + + + + true + + + 0 + dock.PlaceholderList + + + + + + + dock.CExternalizeArea + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + dock.single.Hierarchy + + + + + + + + + dock.CContentArea.minimize + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + + + + 6 + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + Clock Domains - Beta + + + + + + + + + + dock.single.Instance\ Parameters + + + + + + + + + + 3 + dock.single.Instance\ Parameters + + + + + + + Instance Parameters + + + + + + + + + + dock.single.Clocks + + + + + + + + + + 5 + dock.single.Clocks + + + + + + + Clocks + + + + + + + + + + dock.single.Connections\ \-\ Beta + + + + + + + + + + 7 + dock.single.Connections\ \-\ Beta + + + + + + + Connections - Beta + + + + + + + + + + dock.single.Parameters + + + + + + + + + + 10 + dock.single.Parameters + + + + + + + Parameters + + + + + + + + + + dock.single.Presets + + + + + + + + + + + + + + Presets + + + + + + + + + + dock.single.Instrumentation\ \-\ Beta + + + + + + + + + + 2 + dock.single.Instrumentation\ \-\ Beta + + + + + + + Instrumentation - Beta + + + + + + + + + + dock.single.Interconnect\ Requirements + + + + + + + + + + 8 + dock.single.Interconnect\ Requirements + + + + + + + Interconnect Requirements + + + + + + + + + + dock.single.Block\ Symbol + + + + + + + + + + + + + + Block Symbol + + + + + + + + + + dock.single.Data\ Path\ \-\ Beta + + + + + + + + + + 9 + dock.single.Data\ Path\ \-\ Beta + + + + + + + Data Path - Beta + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Project\ Settings + + + + + + + + + + + 5 + dock.single.Project\ Settings + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Library + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.System\ Contents + + + + + + + + + + + 0 + dock.single.System\ Contents + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + + + + + 9 + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Instance\ Parameters + + + + + + + + + + + 4 + dock.single.Instance\ Parameters + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Address\ Map + + + + + + + + + + + 1 + dock.single.Address\ Map + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Clocks + + + + + + + + + + + 3 + dock.single.Clocks + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Connections\ \-\ Beta + + + + + + + + + + + 7 + dock.single.Connections\ \-\ Beta + + + + + + + + dock.mode.minimized + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Parameters + + + + + + + + + + 1 + dock.single.Parameters + + + + + dock.mode.minimized + ccontrol west + + + 0 + false + 400 + dock.single.Parameters + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Presets + + + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Messages + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Instrumentation\ \-\ Beta + + + + + + + + + + + 2 + dock.single.Instrumentation\ \-\ Beta + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Interconnect\ Requirements + + + + + + + + + + + 8 + dock.single.Interconnect\ Requirements + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Block\ Symbol + + + + + + + + + + 0 + dock.single.Block\ Symbol + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Data\ Path\ \-\ Beta + + + + + + + + + + + 8 + dock.single.Data\ Path\ \-\ Beta + + + + + + + + dock.mode.minimized + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Hierarchy + + + + + + + + + + dock.mode.minimized + ccontrol north + + + 0 + false + 400 + dock.single.Hierarchy + + + + + + + + + + + + + + + + eclipse + + \ No newline at end of file diff --git a/examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml b/examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml index 48fdb7a..67f4549 100644 --- a/examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml +++ b/examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml @@ -14,7 +14,7 @@ - + + expandedCategories="Library/Window Bridge,Library/Peripherals/Microcontroller Peripherals,Library/Peripherals,Library/Verification,Library,Project" /> diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys.bsf b/examples/hdl4se_riscv/de1/qsys/i-qsys.bsf new file mode 100644 index 0000000..025cf1e --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys.bsf @@ -0,0 +1,143 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 496 328) + (text "i-qsys" (rect 231 -1 254 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 312 20 324)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) + (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 192 72)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) + (text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 192 112)(line_width 1)) + ) + (port + (pt 0 152) + (input) + (text "vic_0_clk_clk" (rect 0 0 55 12)(font "Arial" (font_size 8))) + (text "vic_0_clk_clk" (rect 4 141 82 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 192 152)(line_width 1)) + ) + (port + (pt 0 192) + (input) + (text "vic_0_clk_reset_reset" (rect 0 0 90 12)(font "Arial" (font_size 8))) + (text "vic_0_clk_reset_reset" (rect 4 181 130 192)(font "Arial" (font_size 8))) + (line (pt 0 192)(pt 192 192)(line_width 1)) + ) + (port + (pt 0 232) + (input) + (text "vic_0_csr_access_read" (rect 0 0 99 12)(font "Arial" (font_size 8))) + (text "vic_0_csr_access_read" (rect 4 221 130 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 192 232)(line_width 1)) + ) + (port + (pt 0 248) + (input) + (text "vic_0_csr_access_write" (rect 0 0 99 12)(font "Arial" (font_size 8))) + (text "vic_0_csr_access_write" (rect 4 237 136 248)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 192 248)(line_width 1)) + ) + (port + (pt 0 264) + (input) + (text "vic_0_csr_access_address[7..0]" (rect 0 0 133 12)(font "Arial" (font_size 8))) + (text "vic_0_csr_access_address[7..0]" (rect 4 253 184 264)(font "Arial" (font_size 8))) + (line (pt 0 264)(pt 192 264)(line_width 3)) + ) + (port + (pt 0 280) + (input) + (text "vic_0_csr_access_writedata[31..0]" (rect 0 0 139 12)(font "Arial" (font_size 8))) + (text "vic_0_csr_access_writedata[31..0]" (rect 4 269 202 280)(font "Arial" (font_size 8))) + (line (pt 0 280)(pt 192 280)(line_width 3)) + ) + (port + (pt 0 296) + (output) + (text "vic_0_csr_access_readdata[31..0]" (rect 0 0 139 12)(font "Arial" (font_size 8))) + (text "vic_0_csr_access_readdata[31..0]" (rect 4 285 196 296)(font "Arial" (font_size 8))) + (line (pt 0 296)(pt 192 296)(line_width 3)) + ) + (port + (pt 496 72) + (output) + (text "vic_0_interrupt_controller_out_valid" (rect 0 0 142 12)(font "Arial" (font_size 8))) + (text "vic_0_interrupt_controller_out_valid" (rect 317 61 533 72)(font "Arial" (font_size 8))) + (line (pt 496 72)(pt 272 72)(line_width 1)) + ) + (port + (pt 496 88) + (output) + (text "vic_0_interrupt_controller_out_data[44..0]" (rect 0 0 168 12)(font "Arial" (font_size 8))) + (text "vic_0_interrupt_controller_out_data[44..0]" (rect 288 77 540 88)(font "Arial" (font_size 8))) + (line (pt 496 88)(pt 272 88)(line_width 3)) + ) + (drawing + (text "clk" (rect 177 43 372 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 197 67 412 144)(font "Arial" (color 0 0 0))) + (text "reset" (rect 163 83 356 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset_n" (rect 197 107 436 224)(font "Arial" (color 0 0 0))) + (text "vic_0_clk" (rect 139 123 332 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 197 147 412 304)(font "Arial" (color 0 0 0))) + (text "vic_0_clk_reset" (rect 101 163 292 339)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset" (rect 197 187 424 384)(font "Arial" (color 0 0 0))) + (text "vic_0_csr_access" (rect 89 203 274 419)(font "Arial" (color 128 0 0)(font_size 9))) + (text "read" (rect 197 227 418 464)(font "Arial" (color 0 0 0))) + (text "write" (rect 197 243 424 496)(font "Arial" (color 0 0 0))) + (text "address" (rect 197 259 436 528)(font "Arial" (color 0 0 0))) + (text "writedata" (rect 197 275 448 560)(font "Arial" (color 0 0 0))) + (text "readdata" (rect 197 291 442 592)(font "Arial" (color 0 0 0))) + (text "vic_0_interrupt_controller_out" (rect 273 43 726 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "valid" (rect 249 67 528 144)(font "Arial" (color 0 0 0))) + (text "data" (rect 251 83 526 176)(font "Arial" (color 0 0 0))) + (text " i-qsys " (rect 467 312 982 634)(font "Arial" )) + (line (pt 193 52)(pt 193 76)(line_width 1)) + (line (pt 194 52)(pt 194 76)(line_width 1)) + (line (pt 193 92)(pt 193 116)(line_width 1)) + (line (pt 194 92)(pt 194 116)(line_width 1)) + (line (pt 193 132)(pt 193 156)(line_width 1)) + (line (pt 194 132)(pt 194 156)(line_width 1)) + (line (pt 193 172)(pt 193 196)(line_width 1)) + (line (pt 194 172)(pt 194 196)(line_width 1)) + (line (pt 193 212)(pt 193 300)(line_width 1)) + (line (pt 194 212)(pt 194 300)(line_width 1)) + (line (pt 271 52)(pt 271 92)(line_width 1)) + (line (pt 270 52)(pt 270 92)(line_width 1)) + (line (pt 192 32)(pt 272 32)(line_width 1)) + (line (pt 272 32)(pt 272 312)(line_width 1)) + (line (pt 192 312)(pt 272 312)(line_width 1)) + (line (pt 192 32)(pt 192 312)(line_width 1)) + (line (pt 0 0)(pt 496 0)(line_width 1)) + (line (pt 496 0)(pt 496 328)(line_width 1)) + (line (pt 0 328)(pt 496 328)(line_width 1)) + (line (pt 0 0)(pt 0 328)(line_width 1)) + ) +) diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys.cmp b/examples/hdl4se_riscv/de1/qsys/i-qsys.cmp new file mode 100644 index 0000000..e69de29 diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys.html b/examples/hdl4se_riscv/de1/qsys/i-qsys.html new file mode 100644 index 0000000..e69a543 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys.html @@ -0,0 +1,231 @@ + + + + + datasheet for i-qsys + + + + + + + + +
i-qsys +
+
+
+ + + + + +
2021.08.28.08:45:04Datasheet
+

+
Overview
+
+
+ + + + + + + + +
  clk_0 i-qsys
+
+ +
+
+
Memory Map
+ + + + + + + + + + +
  + vic_0 + +
csr_access 
+ +
+
+

clk_0

clock_source v13.1 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + +
clockFrequency50000000
clockFrequencyKnowntrue
inputClockFrequency0
resetSynchronousEdgesNONE
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ +
+
+

vic_0

altera_vic v13.1 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NUMBER_OF_INT_PORTS8
RIL_WIDTH4
DAISY_CHAIN_ENABLE0
AUTO_DEVICE_FAMILYCYCLONEV
AUTO_DEVICE5CSEMA5F31C6
deviceFamilyCyclone V
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + + + + + + + + + +
DAISY_CHAIN_ENABLE0
NUMBER_OF_INT_PORTS8
RIL_WIDTH4
+
+
+ + + + + +
generation took 0.01 secondsrendering took 0.02 seconds
+ + diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys.qsys b/examples/hdl4se_riscv/de1/qsys/i-qsys.qsys new file mode 100644 index 0000000..1d1e574 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys.qsys @@ -0,0 +1,80 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys.sopcinfo b/examples/hdl4se_riscv/de1/qsys/i-qsys.sopcinfo new file mode 100644 index 0000000..497e476 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys.sopcinfo @@ -0,0 +1,1206 @@ + + + + + + + java.lang.Integer + 1630111504 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + 5CSEMA5F31C6 + false + true + false + true + + + java.lang.Long + -1 + false + true + false + true + + + java.lang.Integer + -1 + false + true + false + true + + + java.lang.Integer + -1 + false + true + false + true + + + java.lang.Long + -1 + false + true + false + true + + + java.lang.Integer + -1 + false + true + false + true + + + java.lang.Integer + -1 + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + boolean + false + false + true + true + true + + + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + embeddedsw.CMacro.DAISY_CHAIN_ENABLE + 0 + + + embeddedsw.CMacro.NUMBER_OF_INT_PORTS + 8 + + + embeddedsw.CMacro.RIL_WIDTH + 4 + + + int + 8 + false + true + true + true + + + int + 4 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + 5CSEMA5F31C6 + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk_clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + clk_reset_reset + Input + 1 + reset + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + clk_reset + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + INDIVIDUAL_REQUESTS + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + true + + irq_input_irq + Input + 8 + irq + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 1024 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + clk_reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 4 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + csr_access_read + Input + 1 + read + + + csr_access_write + Input + 1 + write + + + csr_access_address + Input + 8 + address + + + csr_access_writedata + Input + 32 + writedata + + + csr_access_readdata + Output + 32 + readdata + + + + + + embeddedsw.configuration.isInterruptControllerSender + 1 + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + clk_reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 45 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + interrupt_controller_out_valid + Output + 1 + valid + + + interrupt_controller_out_data + Output + 45 + data + + + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 13.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 13.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 13.1 + + + 1 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 13.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 13.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 13.1 + + + 1 + altera_vic + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Vectored Interrupt Controller + 13.1 + + + 1 + avalon_streaming_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Source + 13.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 13.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 13.1 + + + 1 + interrupt_receiver + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Receiver + 13.1 + + 13.1 162 + + diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.debuginfo b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.debuginfo new file mode 100644 index 0000000..ff9638d --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.debuginfo @@ -0,0 +1,1503 @@ + + + + + + + com.altera.sopcmodel.ensemble.EClockAdapter + HANDSHAKE + false + true + true + true + + + java.lang.String + 5CSEMA5F31C6 + false + true + true + true + + + java.lang.String + CYCLONEV + false + true + true + true + + + java.lang.String + 6 + false + true + false + true + + + com.altera.sopcmodel.ensemble.Ensemble$EFabricMode + QSYS + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1630111504 + false + true + true + true + + + boolean + false + false + true + false + true + + + com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage + VERILOG + false + false + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + long + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + embeddedsw.CMacro.DAISY_CHAIN_ENABLE + 0 + + + embeddedsw.CMacro.NUMBER_OF_INT_PORTS + 8 + + + embeddedsw.CMacro.RIL_WIDTH + 4 + + + int + 8 + false + true + true + true + + + int + 4 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + 5CSEMA5F31C6 + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk_clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + clk_reset_reset + Input + 1 + reset + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + clk_reset + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + INDIVIDUAL_REQUESTS + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + true + + irq_input_irq + Input + 8 + irq + + + false + irq_mapper + sender + irq_mapper.sender + 0 + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 1024 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + clk_reset + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 4 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + csr_access_read + Input + 1 + read + + + csr_access_write + Input + 1 + write + + + csr_access_address + Input + 8 + address + + + csr_access_writedata + Input + 32 + writedata + + + csr_access_readdata + Output + 32 + readdata + + + + + + embeddedsw.configuration.isInterruptControllerSender + 1 + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + clk_reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 45 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + interrupt_controller_out_valid + Output + 1 + valid + + + interrupt_controller_out_data + Output + 45 + data + + + + + + + int + 0 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + clk_reset + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + sender_irq + Output + 8 + irq + + + + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + vic_0 + irq_input + irq_mapper + sender + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 13.1 + + + 1 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 13.1 + + + 2 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 13.1 + + + 1 + avalon_streaming_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Source + 13.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 13.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 13.1 + + + 1 + altera_irq_mapper + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Merlin IRQ Mapper + 13.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 13.1 + + + 2 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 13.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 13.1 + + + 1 + interrupt + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Interrupt Connection + 13.1 + + + 1 + altera_vic + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Vectored Interrupt Controller + 13.1 + + + 1 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender + 13.1 + + + 1 + interrupt_receiver + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Receiver + 13.1 + + 13.1 162 + 00000000000000E00000017B8A3798AD + diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.qip b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.qip new file mode 100644 index 0000000..38653ac --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.qip @@ -0,0 +1,34 @@ +set_global_assignment -entity "i-qsys" -library "i-qsys" -name IP_TOOL_NAME "Qsys" +set_global_assignment -entity "i-qsys" -library "i-qsys" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "i-qsys" -library "i-qsys" -name IP_TOOL_ENV "Qsys" +set_global_assignment -library "i-qsys" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../i-qsys.sopcinfo"] +set_global_assignment -entity "i-qsys" -library "i-qsys" -name SLD_INFO "QSYS_NAME i-qsys HAS_SOPCINFO 1 GENERATION_ID 1630111504" +set_global_assignment -library "i-qsys" -name MISC_FILE [file join $::quartus(qip_path) "../../i-qsys.cmp"] +set_global_assignment -library "i-qsys" -name SLD_FILE [file join $::quartus(qip_path) "i-qsys.debuginfo"] +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -library "i-qsys" -name MISC_FILE [file join $::quartus(qip_path) "../../i-qsys.qsys"] + +set_global_assignment -library "i-qsys" -name VERILOG_FILE [file join $::quartus(qip_path) "i-qsys.v"] +set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/i-qsys_irq_mapper.sv"] +set_global_assignment -library "i-qsys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/i-qsys_vic_0.v"] +set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_vector.sv"] +set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_priority.sv"] +set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_compare2.sv"] +set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_compare4.sv"] +set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_csr.sv"] + +set_global_assignment -entity "i-qsys_irq_mapper" -library "i-qsys" -name IP_TOOL_NAME "altera_irq_mapper" +set_global_assignment -entity "i-qsys_irq_mapper" -library "i-qsys" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "i-qsys_irq_mapper" -library "i-qsys" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "i-qsys_vic_0" -library "i-qsys" -name IP_TOOL_NAME "altera_vic" +set_global_assignment -entity "i-qsys_vic_0" -library "i-qsys" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "i-qsys_vic_0" -library "i-qsys" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_vic_vector" -library "i-qsys" -name IP_TOOL_NAME "altera_vic_vector" +set_global_assignment -entity "altera_vic_vector" -library "i-qsys" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "altera_vic_vector" -library "i-qsys" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_vic_priority" -library "i-qsys" -name IP_TOOL_NAME "altera_vic_priority" +set_global_assignment -entity "altera_vic_priority" -library "i-qsys" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "altera_vic_priority" -library "i-qsys" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_vic_csr" -library "i-qsys" -name IP_TOOL_NAME "altera_vic_csr" +set_global_assignment -entity "altera_vic_csr" -library "i-qsys" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "altera_vic_csr" -library "i-qsys" -name IP_TOOL_ENV "Qsys" diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.v b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.v new file mode 100644 index 0000000..efe9eaa --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.v @@ -0,0 +1,41 @@ +// i-qsys.v + +// Generated using ACDS version 13.1 162 at 2021.08.28.08:45:04 + +`timescale 1 ps / 1 ps +module i-qsys ( + input wire clk_clk, // clk.clk + input wire reset_reset_n, // reset.reset_n + input wire vic_0_clk_clk, // vic_0_clk.clk + input wire vic_0_clk_reset_reset, // vic_0_clk_reset.reset + input wire vic_0_csr_access_read, // vic_0_csr_access.read + input wire vic_0_csr_access_write, // .write + input wire [7:0] vic_0_csr_access_address, // .address + input wire [31:0] vic_0_csr_access_writedata, // .writedata + output wire [31:0] vic_0_csr_access_readdata, // .readdata + output wire vic_0_interrupt_controller_out_valid, // vic_0_interrupt_controller_out.valid + output wire [44:0] vic_0_interrupt_controller_out_data // .data + ); + + wire [7:0] vic_0_irq_input_irq; // irq_mapper:sender_irq -> vic_0:irq_input_irq + + i-qsys_vic_0 vic_0 ( + .clk_clk (vic_0_clk_clk), // clk.clk + .clk_reset_reset (vic_0_clk_reset_reset), // clk_reset.reset + .irq_input_irq (vic_0_irq_input_irq), // irq_input.irq + .csr_access_read (vic_0_csr_access_read), // csr_access.read + .csr_access_write (vic_0_csr_access_write), // .write + .csr_access_address (vic_0_csr_access_address), // .address + .csr_access_writedata (vic_0_csr_access_writedata), // .writedata + .csr_access_readdata (vic_0_csr_access_readdata), // .readdata + .interrupt_controller_out_valid (vic_0_interrupt_controller_out_valid), // interrupt_controller_out.valid + .interrupt_controller_out_data (vic_0_interrupt_controller_out_data) // .data + ); + + i-qsys_irq_mapper irq_mapper ( + .clk (), // clk.clk + .reset (), // clk_reset.reset + .sender_irq (vic_0_irq_input_irq) // sender.irq + ); + +endmodule diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare2.sv b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare2.sv new file mode 100644 index 0000000..9e6cebb --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare2.sv @@ -0,0 +1,65 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ns / 1ns + +module altera_vic_compare2 #(parameter PRIORITY_WIDTH = 6, + parameter DATA_WIDTH = 20) +( + input wire int_validA, + input wire [DATA_WIDTH-1:0] int_dataA, + + input wire int_validB, + input wire [DATA_WIDTH-1:0] int_dataB, + + output reg int_validZ, + output reg [DATA_WIDTH-1:0] int_dataZ, + + input wire clk +); + + +// ******************************************************************** +// Module Wiring + +wire [PRIORITY_WIDTH:0] LevelA; +wire [PRIORITY_WIDTH:0] LevelB; + +reg [PRIORITY_WIDTH+1:0] LevelDiffZ; + + +// ******************************************************************** +// Module Logic - 1st compare stage clocked + +assign LevelA = {int_validA, int_dataA[PRIORITY_WIDTH-1:0]}; +assign LevelB = {int_validB, int_dataB[PRIORITY_WIDTH-1:0]}; + + +always @(LevelA, LevelB) begin + LevelDiffZ = (LevelA - LevelB); +end + + +always @(posedge clk) begin + if (LevelDiffZ[PRIORITY_WIDTH+1]) begin + int_validZ <= int_validB; + int_dataZ <= int_dataB; + end + else begin + int_validZ <= int_validA; + int_dataZ <= int_dataA; + end +end + + +endmodule diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare4.sv b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare4.sv new file mode 100644 index 0000000..fc66769 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare4.sv @@ -0,0 +1,128 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ns / 1ns + +module altera_vic_compare4 #(parameter PRIORITY_WIDTH = 6, + parameter DATA_WIDTH = 20) +( + input wire int_validA, + input wire [DATA_WIDTH-1:0] int_dataA, + + input wire int_validB, + input wire [DATA_WIDTH-1:0] int_dataB, + + input wire int_validC, + input wire [DATA_WIDTH-1:0] int_dataC, + + input wire int_validD, + input wire [DATA_WIDTH-1:0] int_dataD, + + output reg int_validZ, + output reg [DATA_WIDTH-1:0] int_dataZ, + + input wire clk +); + + +// ******************************************************************** +// Module Wiring + +wire [PRIORITY_WIDTH:0] LevelA; +wire [PRIORITY_WIDTH:0] LevelB; +wire [PRIORITY_WIDTH:0] LevelC; +wire [PRIORITY_WIDTH:0] LevelD; + +wire [PRIORITY_WIDTH:0] LevelX; +wire [PRIORITY_WIDTH:0] LevelY; + +reg [PRIORITY_WIDTH+1:0] LevelDiffX; +reg [PRIORITY_WIDTH+1:0] LevelDiffY; +reg [PRIORITY_WIDTH+1:0] LevelDiffZ; + +reg int_validX; +reg [DATA_WIDTH-1:0] int_dataX; + +reg int_validY; +reg [DATA_WIDTH-1:0] int_dataY; + + +// ******************************************************************** +// Module Logic - 1st and 2nd compare stages combinational + +assign LevelA = {int_validA, int_dataA[PRIORITY_WIDTH-1:0]}; +assign LevelB = {int_validB, int_dataB[PRIORITY_WIDTH-1:0]}; +assign LevelC = {int_validC, int_dataC[PRIORITY_WIDTH-1:0]}; +assign LevelD = {int_validD, int_dataD[PRIORITY_WIDTH-1:0]}; + + +always @(LevelA, LevelB) begin + LevelDiffX = (LevelA - LevelB); +end + + +always @(LevelDiffX, int_validA, int_dataA, int_validB, int_dataB) begin + if (LevelDiffX[PRIORITY_WIDTH+1]) begin + int_validX <= int_validB; + int_dataX <= int_dataB; + end + else begin + int_validX <= int_validA; + int_dataX <= int_dataA; + end +end + + +always @(LevelC, LevelD) begin + LevelDiffY = (LevelC - LevelD); +end + + +always @(LevelDiffY, int_validC, int_dataC, int_validD, int_dataD) begin + if (LevelDiffY[PRIORITY_WIDTH+1]) begin + int_validY <= int_validD; + int_dataY <= int_dataD; + end + else begin + int_validY <= int_validC; + int_dataY <= int_dataC; + end +end + + + +// ******************************************************************** +// Module Logic - 3rd compare stage clocked + +assign LevelX = {int_validX, int_dataX[PRIORITY_WIDTH-1:0]}; +assign LevelY = {int_validY, int_dataY[PRIORITY_WIDTH-1:0]}; + + +always @(LevelX, LevelY) begin + LevelDiffZ = (LevelX - LevelY); +end + + +always @(posedge clk) begin + if (LevelDiffZ[PRIORITY_WIDTH+1]) begin + int_validZ <= int_validY; + int_dataZ <= int_dataY; + end + else begin + int_validZ <= int_validX; + int_dataZ <= int_dataX; + end +end + + +endmodule diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_csr.sv b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_csr.sv new file mode 100644 index 0000000..45a478f --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_csr.sv @@ -0,0 +1,800 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ns / 1ns + +module altera_vic_csr #(parameter NUMBER_OF_INT_PORTS = 32, + parameter RRS_WIDTH = 6, + parameter RIL_WIDTH = 6, + parameter DAISY_CHAIN_ENABLE = 0) +( + input wire [NUMBER_OF_INT_PORTS-1:0] inr_i1_irq, + + input wire [7:0] avs_s1_address, + input wire avs_s1_read, + input wire avs_s1_write, + input wire [31:0] avs_s1_writedata, + output reg [31:0] avs_s1_readdata, + + input wire dc_in_valid, + input wire [44:0] dc_in_data, + + output reg dc_out_valid, + output reg [31:0] dc_out_data, + + output wire out0_valid, + output wire [18:0] out0_data, + + output wire out1_valid, + output wire [18:0] out1_data, + + output wire out2_valid, + output wire [18:0] out2_data, + + output wire out3_valid, + output wire [18:0] out3_data, + + output wire out4_valid, + output wire [18:0] out4_data, + + output wire out5_valid, + output wire [18:0] out5_data, + + output wire out6_valid, + output wire [18:0] out6_data, + + output wire out7_valid, + output wire [18:0] out7_data, + + output wire out8_valid, + output wire [18:0] out8_data, + + output wire out9_valid, + output wire [18:0] out9_data, + + output wire out10_valid, + output wire [18:0] out10_data, + + output wire out11_valid, + output wire [18:0] out11_data, + + output wire out12_valid, + output wire [18:0] out12_data, + + output wire out13_valid, + output wire [18:0] out13_data, + + output wire out14_valid, + output wire [18:0] out14_data, + + output wire out15_valid, + output wire [18:0] out15_data, + + output wire out16_valid, + output wire [18:0] out16_data, + + output wire out17_valid, + output wire [18:0] out17_data, + + output wire out18_valid, + output wire [18:0] out18_data, + + output wire out19_valid, + output wire [18:0] out19_data, + + output wire out20_valid, + output wire [18:0] out20_data, + + output wire out21_valid, + output wire [18:0] out21_data, + + output wire out22_valid, + output wire [18:0] out22_data, + + output wire out23_valid, + output wire [18:0] out23_data, + + output wire out24_valid, + output wire [18:0] out24_data, + + output wire out25_valid, + output wire [18:0] out25_data, + + output wire out26_valid, + output wire [18:0] out26_data, + + output wire out27_valid, + output wire [18:0] out27_data, + + output wire out28_valid, + output wire [18:0] out28_data, + + output wire out29_valid, + output wire [18:0] out29_data, + + output wire out30_valid, + output wire [18:0] out30_data, + + output wire out31_valid, + output wire [18:0] out31_data, + + output wire out32_valid, + output wire [18:0] out32_data, + + output reg control_valid, + output reg [34:0] control_data, + + input wire status_valid, + input wire [37:0] status_data, + + input wire reset_n, + input wire clk +); + + +// ******************************************************************** +// Module Wiring + +reg Reset; + +reg [NUMBER_OF_INT_PORTS-1:0] IntInput; + +reg DcInValid; +reg [44:0] DcInData; + +wire DcOutValid; +wire [31:0] DcOutData; + +reg [5:0] DcRrsValue; +reg DcNmiValue; +reg [5:0] DcRilValue; +reg [5:0] DcRilAdjust; +wire [5:0] RilMaxValue; + +reg [7:0] AvsAddr; +reg AvsRead; +reg AvsWrite; +reg [31:0] AvsWrData; +reg [31:0] AvsRdData; + +reg ConfRegRead; +reg ConfRegWrite; +reg [31:0] ConfRegSelect; +reg [12:0] ConfRegWrData; +wire [12:0] ConfRegRdData [31:0]; +reg ConfRegReset; +reg [12:0] ConfRegRdMux; + +reg CtrlRegRead; +reg CtrlRegWrite; +reg [11:0] CtrlRegSelect; +reg [31:0] CtrlRegWrData; +reg CtrlRegReset; +reg [31:0] CtrlRegRdMux; +reg ControlValid; + +wire [NUMBER_OF_INT_PORTS-1:0] IntEnableRdData; + +reg [NUMBER_OF_INT_PORTS-1:0] IntPendingWrData; +wire [NUMBER_OF_INT_PORTS-1:0] IntPendingRdData; + +reg [NUMBER_OF_INT_PORTS-1:0] IntRawStatusWrData; +wire [NUMBER_OF_INT_PORTS-1:0] IntRawStatusRdData; + +wire [NUMBER_OF_INT_PORTS-1:0] SwTriggerRdData; + +wire [DAISY_CHAIN_ENABLE+2:0] VicConfigRdData; + +reg [31:0] VicStatusWrData; +wire [31:0] VicStatusRdData; + +wire [31:0] VecTableBaseRdData; + +reg [31:0] VecTableAddrWrData; +wire [31:0] VecTableAddrRdData; + +wire [32:0] IntOutputValid; +wire [18:0] IntOutputData [32:0]; +wire [5:0] IntPortId [32:0]; + +genvar i, j, k, l; + + +// ******************************************************************** +// Module Logic + +always @(posedge clk) begin + Reset <= ~reset_n; + ConfRegReset <= Reset; + CtrlRegReset <= Reset; +end + + +always @(posedge clk) begin + IntInput <= inr_i1_irq; + + DcInValid <= dc_in_valid; + DcInData <= dc_in_data; + DcRrsValue <= dc_in_data[12:7]; + DcNmiValue <= dc_in_data[6]; + DcRilValue <= dc_in_data[5:0]; + + AvsAddr <= avs_s1_address; + AvsRead <= avs_s1_read; + AvsWrite <= avs_s1_write; + AvsWrData <= avs_s1_writedata; + + avs_s1_readdata <= AvsRdData; + + dc_out_valid <= DcOutValid; + dc_out_data <= DcOutData; +end + + +generate + case (RIL_WIDTH) + 1: begin assign RilMaxValue = 6'b000001; end + 2: begin assign RilMaxValue = 6'b000011; end + 3: begin assign RilMaxValue = 6'b000111; end + 4: begin assign RilMaxValue = 6'b001111; end + 5: begin assign RilMaxValue = 6'b011111; end + default: begin assign RilMaxValue = 6'b111111; end + endcase +endgenerate + + +always @(DcRilValue, RilMaxValue) begin + if (DcRilValue > RilMaxValue) + DcRilAdjust <= RilMaxValue; + else + DcRilAdjust <= DcRilValue; +end + + +always @(posedge clk) begin + if (AvsAddr[7:5] == 3'b000) begin + ConfRegRead <= AvsRead; + ConfRegWrite <= AvsWrite; + CtrlRegRead <= 1'b0; + CtrlRegWrite <= 1'b0; + end + + else begin + ConfRegRead <= 1'b0; + ConfRegWrite <= 1'b0; + CtrlRegRead <= AvsRead; + CtrlRegWrite <= AvsWrite; + end +end + + +always @(posedge clk) begin + case (AvsAddr[4:0]) + 5'h00: ConfRegSelect <= 32'h00000001; + 5'h01: ConfRegSelect <= 32'h00000002; + 5'h02: ConfRegSelect <= 32'h00000004; + 5'h03: ConfRegSelect <= 32'h00000008; + 5'h04: ConfRegSelect <= 32'h00000010; + 5'h05: ConfRegSelect <= 32'h00000020; + 5'h06: ConfRegSelect <= 32'h00000040; + 5'h07: ConfRegSelect <= 32'h00000080; + 5'h08: ConfRegSelect <= 32'h00000100; + 5'h09: ConfRegSelect <= 32'h00000200; + 5'h0A: ConfRegSelect <= 32'h00000400; + 5'h0B: ConfRegSelect <= 32'h00000800; + 5'h0C: ConfRegSelect <= 32'h00001000; + 5'h0D: ConfRegSelect <= 32'h00002000; + 5'h0E: ConfRegSelect <= 32'h00004000; + 5'h0F: ConfRegSelect <= 32'h00008000; + 5'h10: ConfRegSelect <= 32'h00010000; + 5'h11: ConfRegSelect <= 32'h00020000; + 5'h12: ConfRegSelect <= 32'h00040000; + 5'h13: ConfRegSelect <= 32'h00080000; + 5'h14: ConfRegSelect <= 32'h00100000; + 5'h15: ConfRegSelect <= 32'h00200000; + 5'h16: ConfRegSelect <= 32'h00400000; + 5'h17: ConfRegSelect <= 32'h00800000; + 5'h18: ConfRegSelect <= 32'h01000000; + 5'h19: ConfRegSelect <= 32'h02000000; + 5'h1A: ConfRegSelect <= 32'h04000000; + 5'h1B: ConfRegSelect <= 32'h08000000; + 5'h1C: ConfRegSelect <= 32'h10000000; + 5'h1D: ConfRegSelect <= 32'h20000000; + 5'h1E: ConfRegSelect <= 32'h40000000; + 5'h1F: ConfRegSelect <= 32'h80000000; + endcase +end + + +always @(posedge clk) begin + case (AvsAddr[4:0]) + 5'h00: CtrlRegSelect <= 12'h001; + 5'h01: CtrlRegSelect <= 12'h002; + 5'h02: CtrlRegSelect <= 12'h004; + 5'h03: CtrlRegSelect <= 12'h008; + 5'h04: CtrlRegSelect <= 12'h010; + 5'h05: CtrlRegSelect <= 12'h020; + 5'h06: CtrlRegSelect <= 12'h040; + 5'h07: CtrlRegSelect <= 12'h080; + 5'h08: CtrlRegSelect <= 12'h100; + 5'h09: CtrlRegSelect <= 12'h200; + 5'h0A: CtrlRegSelect <= 12'h400; + 5'h0B: CtrlRegSelect <= 12'h800; + default: CtrlRegSelect <= 12'h000; + endcase +end + + +always @(posedge clk) begin + case (AvsAddr[4:0]) + 5'h00: ConfRegRdMux <= ConfRegRdData[0]; + 5'h01: ConfRegRdMux <= ConfRegRdData[1]; + 5'h02: ConfRegRdMux <= ConfRegRdData[2]; + 5'h03: ConfRegRdMux <= ConfRegRdData[3]; + 5'h04: ConfRegRdMux <= ConfRegRdData[4]; + 5'h05: ConfRegRdMux <= ConfRegRdData[5]; + 5'h06: ConfRegRdMux <= ConfRegRdData[6]; + 5'h07: ConfRegRdMux <= ConfRegRdData[7]; + 5'h08: ConfRegRdMux <= ConfRegRdData[8]; + 5'h09: ConfRegRdMux <= ConfRegRdData[9]; + 5'h0A: ConfRegRdMux <= ConfRegRdData[10]; + 5'h0B: ConfRegRdMux <= ConfRegRdData[11]; + 5'h0C: ConfRegRdMux <= ConfRegRdData[12]; + 5'h0D: ConfRegRdMux <= ConfRegRdData[13]; + 5'h0E: ConfRegRdMux <= ConfRegRdData[14]; + 5'h0F: ConfRegRdMux <= ConfRegRdData[15]; + 5'h10: ConfRegRdMux <= ConfRegRdData[16]; + 5'h11: ConfRegRdMux <= ConfRegRdData[17]; + 5'h12: ConfRegRdMux <= ConfRegRdData[18]; + 5'h13: ConfRegRdMux <= ConfRegRdData[19]; + 5'h14: ConfRegRdMux <= ConfRegRdData[20]; + 5'h15: ConfRegRdMux <= ConfRegRdData[21]; + 5'h16: ConfRegRdMux <= ConfRegRdData[22]; + 5'h17: ConfRegRdMux <= ConfRegRdData[23]; + 5'h18: ConfRegRdMux <= ConfRegRdData[24]; + 5'h19: ConfRegRdMux <= ConfRegRdData[25]; + 5'h1A: ConfRegRdMux <= ConfRegRdData[26]; + 5'h1B: ConfRegRdMux <= ConfRegRdData[27]; + 5'h1C: ConfRegRdMux <= ConfRegRdData[28]; + 5'h1D: ConfRegRdMux <= ConfRegRdData[29]; + 5'h1E: ConfRegRdMux <= ConfRegRdData[30]; + 5'h1F: ConfRegRdMux <= ConfRegRdData[31]; + endcase +end + + +always @(posedge clk) begin + case (AvsAddr[4:0]) + 5'h00: CtrlRegRdMux <= IntEnableRdData; + + 5'h03: CtrlRegRdMux <= IntPendingRdData; + 5'h04: CtrlRegRdMux <= IntRawStatusRdData; + 5'h05: CtrlRegRdMux <= SwTriggerRdData; + + 5'h08: CtrlRegRdMux <= VicConfigRdData; + 5'h09: CtrlRegRdMux <= VicStatusRdData; + 5'h0A: CtrlRegRdMux <= VecTableBaseRdData; + 5'h0B: CtrlRegRdMux <= VecTableAddrRdData; + + default: CtrlRegRdMux <= 32'h00000000; + endcase +end + + +always @(posedge clk) begin + if (ConfRegRead) + AvsRdData <= {19'h0, ConfRegRdMux}; + + else if (CtrlRegRead) + AvsRdData <= CtrlRegRdMux; + + else + AvsRdData <= 32'h00000000; +end + + +always @(posedge clk) begin + ConfRegWrData <= AvsWrData[12:0]; + CtrlRegWrData <= AvsWrData; +end + + +always @(posedge clk) begin + IntPendingWrData <= IntEnableRdData & (IntInput | SwTriggerRdData); + IntRawStatusWrData <= IntInput; + + ControlValid <= (CtrlRegSelect[8] | CtrlRegSelect[10]) & CtrlRegWrite; + control_valid <= ControlValid; + control_data <= {VicConfigRdData[2:0], VecTableBaseRdData}; +end + + +always @(posedge clk) begin + if (status_valid) begin + VicStatusWrData[31] <= status_valid; + VicStatusWrData[30:DAISY_CHAIN_ENABLE+5] <= 0; + VicStatusWrData[DAISY_CHAIN_ENABLE+4:0] <= status_data[DAISY_CHAIN_ENABLE+36:32]; + VecTableAddrWrData <= status_data[31:0]; + end + else begin + VicStatusWrData <= 0; + VecTableAddrWrData <= 0; + end +end + + +assign IntPortId[0] = 6'h00; +assign IntPortId[1] = 6'h01; +assign IntPortId[2] = 6'h02; +assign IntPortId[3] = 6'h03; +assign IntPortId[4] = 6'h04; +assign IntPortId[5] = 6'h05; +assign IntPortId[6] = 6'h06; +assign IntPortId[7] = 6'h07; +assign IntPortId[8] = 6'h08; +assign IntPortId[9] = 6'h09; +assign IntPortId[10] = 6'h0A; +assign IntPortId[11] = 6'h0B; +assign IntPortId[12] = 6'h0C; +assign IntPortId[13] = 6'h0D; +assign IntPortId[14] = 6'h0E; +assign IntPortId[15] = 6'h0F; +assign IntPortId[16] = 6'h10; +assign IntPortId[17] = 6'h11; +assign IntPortId[18] = 6'h12; +assign IntPortId[19] = 6'h13; +assign IntPortId[20] = 6'h14; +assign IntPortId[21] = 6'h15; +assign IntPortId[22] = 6'h16; +assign IntPortId[23] = 6'h17; +assign IntPortId[24] = 6'h18; +assign IntPortId[25] = 6'h19; +assign IntPortId[26] = 6'h1A; +assign IntPortId[27] = 6'h1B; +assign IntPortId[28] = 6'h1C; +assign IntPortId[29] = 6'h1D; +assign IntPortId[30] = 6'h1E; +assign IntPortId[31] = 6'h1F; +assign IntPortId[32] = 6'h20; + + +generate + for (i=0; i < NUMBER_OF_INT_PORTS; i=i+1) begin : INT_OUT + altera_vic_output_reg U (IntPendingWrData[i], + IntPortId[i], ConfRegRdData[i], + IntOutputValid[i], + IntOutputData[i], + clk); + end +endgenerate + + +generate + if (DAISY_CHAIN_ENABLE) begin : INT_DC + altera_vic_output_reg D ((|DcRilAdjust & VicConfigRdData[3]), + 6'h20, {DcRrsValue, DcNmiValue, DcRilAdjust}, + IntOutputValid[NUMBER_OF_INT_PORTS], + IntOutputData[NUMBER_OF_INT_PORTS], + clk); + end +endgenerate + + +generate + for (j=NUMBER_OF_INT_PORTS+DAISY_CHAIN_ENABLE; j < 33; j=j+1) begin : INT_NULL + assign IntOutputValid[j] = 1'b0; + assign IntOutputData[j] = 19'h00000; + end +endgenerate + + +generate + if (DAISY_CHAIN_ENABLE) begin : OUT_DC + assign DcOutValid = DcInValid; + assign DcOutData = DcInData[44:13]; + end + else begin + assign DcOutValid = 1'b0; + assign DcOutData = 32'h00000000; + end +endgenerate + + +assign out0_valid = IntOutputValid[0]; +assign out0_data = IntOutputData[0]; + +assign out1_valid = IntOutputValid[1]; +assign out1_data = IntOutputData[1]; + +assign out2_valid = IntOutputValid[2]; +assign out2_data = IntOutputData[2]; + +assign out3_valid = IntOutputValid[3]; +assign out3_data = IntOutputData[3]; + +assign out4_valid = IntOutputValid[4]; +assign out4_data = IntOutputData[4]; + +assign out5_valid = IntOutputValid[5]; +assign out5_data = IntOutputData[5]; + +assign out6_valid = IntOutputValid[6]; +assign out6_data = IntOutputData[6]; + +assign out7_valid = IntOutputValid[7]; +assign out7_data = IntOutputData[7]; + +assign out8_valid = IntOutputValid[8]; +assign out8_data = IntOutputData[8]; + +assign out9_valid = IntOutputValid[9]; +assign out9_data = IntOutputData[9]; + +assign out10_valid = IntOutputValid[10]; +assign out10_data = IntOutputData[10]; + +assign out11_valid = IntOutputValid[11]; +assign out11_data = IntOutputData[11]; + +assign out12_valid = IntOutputValid[12]; +assign out12_data = IntOutputData[12]; + +assign out13_valid = IntOutputValid[13]; +assign out13_data = IntOutputData[13]; + +assign out14_valid = IntOutputValid[14]; +assign out14_data = IntOutputData[14]; + +assign out15_valid = IntOutputValid[15]; +assign out15_data = IntOutputData[15]; + +assign out16_valid = IntOutputValid[16]; +assign out16_data = IntOutputData[16]; + +assign out17_valid = IntOutputValid[17]; +assign out17_data = IntOutputData[17]; + +assign out18_valid = IntOutputValid[18]; +assign out18_data = IntOutputData[18]; + +assign out19_valid = IntOutputValid[19]; +assign out19_data = IntOutputData[19]; + +assign out20_valid = IntOutputValid[20]; +assign out20_data = IntOutputData[20]; + +assign out21_valid = IntOutputValid[21]; +assign out21_data = IntOutputData[21]; + +assign out22_valid = IntOutputValid[22]; +assign out22_data = IntOutputData[22]; + +assign out23_valid = IntOutputValid[23]; +assign out23_data = IntOutputData[23]; + +assign out24_valid = IntOutputValid[24]; +assign out24_data = IntOutputData[24]; + +assign out25_valid = IntOutputValid[25]; +assign out25_data = IntOutputData[25]; + +assign out26_valid = IntOutputValid[26]; +assign out26_data = IntOutputData[26]; + +assign out27_valid = IntOutputValid[27]; +assign out27_data = IntOutputData[27]; + +assign out28_valid = IntOutputValid[28]; +assign out28_data = IntOutputData[28]; + +assign out29_valid = IntOutputValid[29]; +assign out29_data = IntOutputData[29]; + +assign out30_valid = IntOutputValid[30]; +assign out30_data = IntOutputData[30]; + +assign out31_valid = IntOutputValid[31]; +assign out31_data = IntOutputData[31]; + +assign out32_valid = IntOutputValid[32]; +assign out32_data = IntOutputData[32]; + + +// ******************************************************************** +// Instantiation of CSRs + +generate + for (k=0; k < NUMBER_OF_INT_PORTS; k=k+1) begin : REG_CONFIG + altera_vic_config_reg #(RRS_WIDTH, RIL_WIDTH) U + (ConfRegSelect[k], ConfRegWrite, ConfRegWrData, ConfRegRdData[k], ConfRegReset, clk); + end +endgenerate + + +generate + for (l=NUMBER_OF_INT_PORTS; l <32; l=l+1) begin : REG_NULL + assign ConfRegRdData[l] = 13'h0000; + end +endgenerate + + +// Set Clear +altera_vic_reg_set_clear #(NUMBER_OF_INT_PORTS) INT_ENABLE + (CtrlRegSelect[2:0], CtrlRegWrite, CtrlRegWrData[NUMBER_OF_INT_PORTS-1:0], IntEnableRdData, CtrlRegReset, clk); + +// Read only +altera_vic_reg_ro #(NUMBER_OF_INT_PORTS) INT_PENDING + (IntPendingWrData, IntPendingRdData, CtrlRegReset, clk); + +// Read only +altera_vic_reg_ro #(NUMBER_OF_INT_PORTS) INT_RAW_STATUS + (IntRawStatusWrData, IntRawStatusRdData, CtrlRegReset, clk); + +// Set Clear +altera_vic_reg_set_clear #(NUMBER_OF_INT_PORTS) SW_TRIGGER + (CtrlRegSelect[7:5], CtrlRegWrite, CtrlRegWrData[NUMBER_OF_INT_PORTS-1:0], SwTriggerRdData, CtrlRegReset, clk); + +// Reg +altera_vic_reg #(DAISY_CHAIN_ENABLE+3) VIC_CONFIG + (CtrlRegSelect[8], CtrlRegWrite, CtrlRegWrData[DAISY_CHAIN_ENABLE+2:0], VicConfigRdData, CtrlRegReset, clk); + +// Read only +altera_vic_reg_ro #(32) VIC_STATUS + (VicStatusWrData, VicStatusRdData, CtrlRegReset, clk); + +// Reg +altera_vic_reg #(32) VEC_TABLE_BASE + (CtrlRegSelect[10], CtrlRegWrite, CtrlRegWrData, VecTableBaseRdData, CtrlRegReset, clk); + +// Read only +altera_vic_reg_ro #(32) VEC_TABLE_ADDR + (VecTableAddrWrData, VecTableAddrRdData, CtrlRegReset, clk); + +endmodule + + +module altera_vic_output_reg +( + input wire reg_write, + input wire [5:0] reg_portid, + input wire [12:0] reg_configdata, + output reg reg_outputvalid, + output reg [18:0] reg_outputdata, + input wire clk +); +always @(posedge clk) begin + if (reg_write) begin + reg_outputvalid <= 1'b1; + reg_outputdata <= {reg_portid, reg_configdata}; + end + else begin + reg_outputvalid <= 1'b0; + reg_outputdata <= 19'h00000; + end +end +endmodule + + +module altera_vic_config_reg #(parameter RRS_WIDTH = 6, RIL_WIDTH = 6) +( + input wire reg_select, + input wire reg_write, + input wire [12:0] reg_writedata, + output reg [12:0] reg_readdata, + input wire reg_reset, + input wire clk +); + +localparam RRS_ZEROS = 6 - RRS_WIDTH; +localparam RIL_ZEROS = 6 - RIL_WIDTH; +wire [5:0] wr_data_lsb; +wire [12:7] wr_data_msb; + +generate + if (RIL_ZEROS > 0) begin + assign wr_data_lsb = {{RIL_ZEROS{1'b0}}, reg_writedata[RIL_WIDTH-1:0]}; + end + else begin + assign wr_data_lsb = reg_writedata[RIL_WIDTH-1:0]; + end +endgenerate + +generate + if (RRS_ZEROS > 0) begin + assign wr_data_msb = {{RRS_ZEROS{1'b0}}, reg_writedata[RRS_WIDTH+6:7]}; + end + else begin + assign wr_data_msb = reg_writedata[RRS_WIDTH+6:7]; + end +endgenerate + + +always @(posedge clk) begin + if (reg_reset) + reg_readdata <= 0; + else if (reg_select && reg_write) begin + reg_readdata[12:7] <= wr_data_msb; + reg_readdata[6] <= reg_writedata[6]; + reg_readdata[5:0] <= wr_data_lsb; + end +end + +endmodule + + + +module altera_vic_reg #(parameter WIDTH = 32) +( + input wire reg_select, + input wire reg_write, + input wire [WIDTH-1:0] reg_writedata, + output reg [WIDTH-1:0] reg_readdata, + input wire reg_reset, + input wire clk +); + +always @(posedge clk) begin + if (reg_reset) + reg_readdata <= 0; + else if (reg_select && reg_write) + reg_readdata <= reg_writedata; +end + +endmodule + + + +module altera_vic_reg_ro #(parameter WIDTH = 32) +( + input wire [WIDTH-1:0] reg_writedata, + output reg [WIDTH-1:0] reg_readdata, + input wire reg_reset, + input wire clk +); + + +always @(posedge clk) begin + if (reg_reset) + reg_readdata <= 0; + else + reg_readdata <= reg_writedata; +end + +endmodule + + + +module altera_vic_reg_set_clear #(parameter WIDTH = 32) +( + input wire [2:0] reg_select, + input wire reg_write, + input wire [WIDTH-1:0] reg_writedata, + output reg [WIDTH-1:0] reg_readdata, + input wire reg_reset, + input wire clk +); + + +always @(posedge clk) begin + if (reg_reset) + reg_readdata <= 0; + else if (reg_select[0] && reg_write) + reg_readdata <= reg_writedata; + else if (reg_select[1] && reg_write) // Write 1 to Set + reg_readdata <= reg_readdata | reg_writedata; + else if (reg_select[2] && reg_write) // Write 1 to Clear + reg_readdata <= reg_readdata & ~reg_writedata; +end + +endmodule + diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_priority.sv b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_priority.sv new file mode 100644 index 0000000..30eada6 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_priority.sv @@ -0,0 +1,351 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ns / 1ns + +module altera_vic_priority #(parameter NUMBER_OF_INT_PORTS = 32, + parameter PRIORITY_WIDTH = 6, + parameter DATA_WIDTH = 19) +( + input wire in0_valid, + input wire [DATA_WIDTH-1:0] in0_data, + + input wire in1_valid, + input wire [DATA_WIDTH-1:0] in1_data, + + input wire in2_valid, + input wire [DATA_WIDTH-1:0] in2_data, + + input wire in3_valid, + input wire [DATA_WIDTH-1:0] in3_data, + + input wire in4_valid, + input wire [DATA_WIDTH-1:0] in4_data, + + input wire in5_valid, + input wire [DATA_WIDTH-1:0] in5_data, + + input wire in6_valid, + input wire [DATA_WIDTH-1:0] in6_data, + + input wire in7_valid, + input wire [DATA_WIDTH-1:0] in7_data, + + input wire in8_valid, + input wire [DATA_WIDTH-1:0] in8_data, + + input wire in9_valid, + input wire [DATA_WIDTH-1:0] in9_data, + + input wire in10_valid, + input wire [DATA_WIDTH-1:0] in10_data, + + input wire in11_valid, + input wire [DATA_WIDTH-1:0] in11_data, + + input wire in12_valid, + input wire [DATA_WIDTH-1:0] in12_data, + + input wire in13_valid, + input wire [DATA_WIDTH-1:0] in13_data, + + input wire in14_valid, + input wire [DATA_WIDTH-1:0] in14_data, + + input wire in15_valid, + input wire [DATA_WIDTH-1:0] in15_data, + + input wire in16_valid, + input wire [DATA_WIDTH-1:0] in16_data, + + input wire in17_valid, + input wire [DATA_WIDTH-1:0] in17_data, + + input wire in18_valid, + input wire [DATA_WIDTH-1:0] in18_data, + + input wire in19_valid, + input wire [DATA_WIDTH-1:0] in19_data, + + input wire in20_valid, + input wire [DATA_WIDTH-1:0] in20_data, + + input wire in21_valid, + input wire [DATA_WIDTH-1:0] in21_data, + + input wire in22_valid, + input wire [DATA_WIDTH-1:0] in22_data, + + input wire in23_valid, + input wire [DATA_WIDTH-1:0] in23_data, + + input wire in24_valid, + input wire [DATA_WIDTH-1:0] in24_data, + + input wire in25_valid, + input wire [DATA_WIDTH-1:0] in25_data, + + input wire in26_valid, + input wire [DATA_WIDTH-1:0] in26_data, + + input wire in27_valid, + input wire [DATA_WIDTH-1:0] in27_data, + + input wire in28_valid, + input wire [DATA_WIDTH-1:0] in28_data, + + input wire in29_valid, + input wire [DATA_WIDTH-1:0] in29_data, + + input wire in30_valid, + input wire [DATA_WIDTH-1:0] in30_data, + + input wire in31_valid, + input wire [DATA_WIDTH-1:0] in31_data, + + input wire in32_valid, + input wire [DATA_WIDTH-1:0] in32_data, + + output wire pri_valid, + output wire [DATA_WIDTH-1:0] pri_data, + + input wire reset_n, + input wire clk +); + + +// ******************************************************************** +// Module Wiring + +wire cmp_valid_A0; +wire [DATA_WIDTH-1:0] cmp_data_A0; + +wire cmp_valid_A1; +wire [DATA_WIDTH-1:0] cmp_data_A1; + +wire cmp_valid_A2; +wire [DATA_WIDTH-1:0] cmp_data_A2; + +wire cmp_valid_A3; +wire [DATA_WIDTH-1:0] cmp_data_A3; + +wire cmp_valid_A4; +wire [DATA_WIDTH-1:0] cmp_data_A4; + +wire cmp_valid_A5; +wire [DATA_WIDTH-1:0] cmp_data_A5; + +wire cmp_valid_A6; +wire [DATA_WIDTH-1:0] cmp_data_A6; + +wire cmp_valid_A7; +wire [DATA_WIDTH-1:0] cmp_data_A7; + +wire cmp_valid_A8; +wire [DATA_WIDTH-1:0] cmp_data_A8; + +wire cmp_valid_B0; +wire [DATA_WIDTH-1:0] cmp_data_B0; + +wire cmp_valid_B1; +wire [DATA_WIDTH-1:0] cmp_data_B1; + +wire cmp_valid_B2; +wire [DATA_WIDTH-1:0] cmp_data_B2; + + +// ******************************************************************** +// Module Logic + +generate + case (NUMBER_OF_INT_PORTS) + 1: begin : port1 + assign pri_valid = in0_valid; + assign pri_data = in0_data; + end + + 2, 3, 4: begin : port2_4 + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0 + (in0_valid, in0_data, in1_valid, in1_data, + in2_valid, in2_data, in3_valid, in3_data, + pri_valid, pri_data, clk); + end + + 5, 6, 7, 8: begin : port5_8 + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0 + (in0_valid, in0_data, in1_valid, in1_data, + in2_valid, in2_data, in3_valid, in3_data, + cmp_valid_A0, cmp_data_A0, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A1 + (in4_valid, in4_data, in5_valid, in5_data, + in6_valid, in6_data, in7_valid, in7_data, + cmp_valid_A1, cmp_data_A1, clk); + + altera_vic_compare2 #(PRIORITY_WIDTH, DATA_WIDTH) B0 + (cmp_valid_A0, cmp_data_A0, cmp_valid_A1, cmp_data_A1, + pri_valid, pri_data, clk); + end + + 9, 10, 11, 12, 13, 14, 15, 16: begin : port9_16 + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0 + (in0_valid, in0_data, in1_valid, in1_data, + in2_valid, in2_data, in3_valid, in3_data, + cmp_valid_A0, cmp_data_A0, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A1 + (in4_valid, in4_data, in5_valid, in5_data, + in6_valid, in6_data, in7_valid, in7_data, + cmp_valid_A1, cmp_data_A1, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A2 + (in8_valid, in8_data, in9_valid, in9_data, + in10_valid, in10_data, in11_valid, in11_data, + cmp_valid_A2, cmp_data_A2, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A3 + (in12_valid, in12_data, in13_valid, in13_data, + in14_valid, in14_data, in15_valid, in15_data, + cmp_valid_A3, cmp_data_A3, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B0 + (cmp_valid_A0, cmp_data_A0, cmp_valid_A1, cmp_data_A1, + cmp_valid_A2, cmp_data_A2, cmp_valid_A3, cmp_data_A3, + pri_valid, pri_data, clk); + end + + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32: begin : port17_32 + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0 + (in0_valid, in0_data, in1_valid, in1_data, + in2_valid, in2_data, in3_valid, in3_data, + cmp_valid_A0, cmp_data_A0, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A1 + (in4_valid, in4_data, in5_valid, in5_data, + in6_valid, in6_data, in7_valid, in7_data, + cmp_valid_A1, cmp_data_A1, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A2 + (in8_valid, in8_data, in9_valid, in9_data, + in10_valid, in10_data, in11_valid, in11_data, + cmp_valid_A2, cmp_data_A2, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A3 + (in12_valid, in12_data, in13_valid, in13_data, + in14_valid, in14_data, in15_valid, in15_data, + cmp_valid_A3, cmp_data_A3, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A4 + (in16_valid, in16_data, in17_valid, in17_data, + in18_valid, in18_data, in19_valid, in19_data, + cmp_valid_A4, cmp_data_A4, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A5 + (in20_valid, in20_data, in21_valid, in21_data, + in22_valid, in22_data, in23_valid, in23_data, + cmp_valid_A5, cmp_data_A5, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A6 + (in24_valid, in24_data, in25_valid, in25_data, + in26_valid, in26_data, in27_valid, in27_data, + cmp_valid_A6, cmp_data_A6, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A7 + (in28_valid, in28_data, in29_valid, in29_data, + in30_valid, in30_data, in31_valid, in31_data, + cmp_valid_A7, cmp_data_A7, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B0 + (cmp_valid_A0, cmp_data_A0, cmp_valid_A1, cmp_data_A1, + cmp_valid_A2, cmp_data_A2, cmp_valid_A3, cmp_data_A3, + cmp_valid_B0, cmp_data_B0, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B1 + (cmp_valid_A4, cmp_data_A4, cmp_valid_A5, cmp_data_A5, + cmp_valid_A6, cmp_data_A6, cmp_valid_A7, cmp_data_A7, + cmp_valid_B1, cmp_data_B1, clk); + + altera_vic_compare2 #(PRIORITY_WIDTH, DATA_WIDTH) C0 + (cmp_valid_B0, cmp_data_B0, cmp_valid_B1, cmp_data_B1, + pri_valid, pri_data, clk); + end + + default: begin : port33 + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0 + (in0_valid, in0_data, in1_valid, in1_data, + in2_valid, in2_data, in3_valid, in3_data, + cmp_valid_A0, cmp_data_A0, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A1 + (in4_valid, in4_data, in5_valid, in5_data, + in6_valid, in6_data, in7_valid, in7_data, + cmp_valid_A1, cmp_data_A1, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A2 + (in8_valid, in8_data, in9_valid, in9_data, + in10_valid, in10_data, in11_valid, in11_data, + cmp_valid_A2, cmp_data_A2, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A3 + (in12_valid, in12_data, in13_valid, in13_data, + in14_valid, in14_data, in15_valid, in15_data, + cmp_valid_A3, cmp_data_A3, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A4 + (in16_valid, in16_data, in17_valid, in17_data, + in18_valid, in18_data, in19_valid, in19_data, + cmp_valid_A4, cmp_data_A4, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A5 + (in20_valid, in20_data, in21_valid, in21_data, + in22_valid, in22_data, in23_valid, in23_data, + cmp_valid_A5, cmp_data_A5, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A6 + (in24_valid, in24_data, in25_valid, in25_data, + in26_valid, in26_data, in27_valid, in27_data, + cmp_valid_A6, cmp_data_A6, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A7 + (in28_valid, in28_data, in29_valid, in29_data, + in30_valid, in30_data, in31_valid, in31_data, + cmp_valid_A7, cmp_data_A7, clk); + + altera_vic_compare2 #(PRIORITY_WIDTH, DATA_WIDTH) A8 + (in32_valid, in32_data, 1'b0, {DATA_WIDTH{1'b0}}, + cmp_valid_A8, cmp_data_A8, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B0 + (cmp_valid_A0, cmp_data_A0, cmp_valid_A1, cmp_data_A1, + cmp_valid_A2, cmp_data_A2, cmp_valid_A3, cmp_data_A3, + cmp_valid_B0, cmp_data_B0, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B1 + (cmp_valid_A4, cmp_data_A4, cmp_valid_A5, cmp_data_A5, + cmp_valid_A6, cmp_data_A6, cmp_valid_A7, cmp_data_A7, + cmp_valid_B1, cmp_data_B1, clk); + + altera_vic_compare2 #(PRIORITY_WIDTH, DATA_WIDTH) B2 + (cmp_valid_A8, cmp_data_A8, 1'b0, {DATA_WIDTH{1'b0}}, + cmp_valid_B2, cmp_data_B2, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) C0 + (cmp_valid_B0, cmp_data_B0, cmp_valid_B1, cmp_data_B1, + cmp_valid_B2, cmp_data_B2, 1'b0, {DATA_WIDTH{1'b0}}, + pri_valid, pri_data, clk); + end + endcase +endgenerate + + +endmodule diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_vector.sv b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_vector.sv new file mode 100644 index 0000000..7d2f571 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_vector.sv @@ -0,0 +1,136 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ns / 1ns + +module altera_vic_vector #(parameter DAISY_CHAIN_ENABLE = 0) +( + output reg out_valid, + output reg [44:0] out_data, + + output reg status_valid, + output reg [37:0] status_data, + + input wire control_valid, + input wire [34:0] control_data, + + input wire dc_valid, + input wire [31:0] dc_data, + + input wire in_valid, + input wire [18:0] in_data, + + input wire reset_n, + input wire clk +); + + +// ******************************************************************** +// Module Wiring + +wire InValid; +wire [5:0] InPortId; +wire [12:0] InConfig; + +wire OutValid; +reg [5:0] OutPortId; +reg [12:0] OutConfig; + +reg [2:0] VecSize; +reg [31:0] VecBaseAddr; + +reg [13:0] VecOffset; +reg [31:0] VecHandAddr; + +reg [31:0] DcRhaValue; + + +// ******************************************************************** +// Module Logic + +assign InValid = in_valid; +assign InPortId = in_data[18:13]; +assign InConfig = in_data[12:0]; + +assign OutValid = InValid; + + +always @(posedge clk) begin + if (control_valid) begin + VecSize <= control_data[34:32]; + VecBaseAddr <= control_data[31:0]; + end +end + + +always @(posedge clk) begin + status_valid <= OutValid; + status_data <= {OutPortId, VecHandAddr}; +end + + +always @(VecSize, InPortId) begin + case (VecSize) + 3'b000: VecOffset <= {7'b0, InPortId[4:0], 2'b0}; + 3'b001: VecOffset <= {6'b0, InPortId[4:0], 3'b0}; + 3'b010: VecOffset <= {5'b0, InPortId[4:0], 4'b0}; + 3'b011: VecOffset <= {4'b0, InPortId[4:0], 5'b0}; + 3'b100: VecOffset <= {3'b0, InPortId[4:0], 6'b0}; + 3'b101: VecOffset <= {2'b0, InPortId[4:0], 7'b0}; + 3'b110: VecOffset <= {1'b0, InPortId[4:0], 8'b0}; + 3'b111: VecOffset <= {InPortId[4:0], 9'b0}; + endcase +end + + +always @(dc_valid, dc_data) begin + if (dc_valid) + DcRhaValue <= dc_data; + else + DcRhaValue <= 32'h00000000; +end + + +always @(InValid, InPortId, DcRhaValue, VecBaseAddr, VecOffset) begin + if (InValid & InPortId[5]) + VecHandAddr <= DcRhaValue; + else if (InValid & ~InPortId[5]) + VecHandAddr <= VecBaseAddr + VecOffset; + else + VecHandAddr <= 32'h00000000; +end + + +always @(InValid, InPortId) begin + if (InValid) + OutPortId <= InPortId; + else + OutPortId <= 6'h00; +end + + +always @(InValid, InConfig) begin + if (InValid) + OutConfig <= InConfig; + else + OutConfig <= 13'h0000; +end + + +always @(posedge clk) begin + out_valid <= 1'b1; + out_data <= {VecHandAddr, OutConfig}; +end + + +endmodule diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_irq_mapper.sv b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_irq_mapper.sv new file mode 100644 index 0000000..4a7d913 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_irq_mapper.sv @@ -0,0 +1,58 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/08/11 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Altera IRQ Mapper +// +// Parameters +// NUM_RCVRS : 0 +// SENDER_IRW_WIDTH : 8 +// IRQ_MAP : +// +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module i-qsys_irq_mapper +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // IRQ Receivers + // ------------------- + + // ------------------- + // Command Source (Output) + // ------------------- + output reg [7 : 0] sender_irq +); + + initial sender_irq = 0; + + always @* begin + sender_irq = 0; + + end + +endmodule + + diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_vic_0.v b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_vic_0.v new file mode 100644 index 0000000..35053b1 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_vic_0.v @@ -0,0 +1,229 @@ +// i-qsys_vic_0.v + +// This file was auto-generated from altera_vic_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 13.1 162 at 2021.08.28.08:45:04 + +`timescale 1 ps / 1 ps +module i-qsys_vic_0 ( + input wire clk_clk, // clk.clk + input wire clk_reset_reset, // clk_reset.reset + input wire [7:0] irq_input_irq, // irq_input.irq + input wire csr_access_read, // csr_access.read + input wire csr_access_write, // .write + input wire [7:0] csr_access_address, // .address + input wire [31:0] csr_access_writedata, // .writedata + output wire [31:0] csr_access_readdata, // .readdata + output wire interrupt_controller_out_valid, // interrupt_controller_out.valid + output wire [44:0] interrupt_controller_out_data // .data + ); + + wire vic_csr_out0_valid; // vic_csr:out0_valid -> vic_priority:in0_valid + wire [18:0] vic_csr_out0_data; // vic_csr:out0_data -> vic_priority:in0_data + wire vic_csr_out1_valid; // vic_csr:out1_valid -> vic_priority:in1_valid + wire [18:0] vic_csr_out1_data; // vic_csr:out1_data -> vic_priority:in1_data + wire vic_csr_out2_valid; // vic_csr:out2_valid -> vic_priority:in2_valid + wire [18:0] vic_csr_out2_data; // vic_csr:out2_data -> vic_priority:in2_data + wire vic_csr_out3_valid; // vic_csr:out3_valid -> vic_priority:in3_valid + wire [18:0] vic_csr_out3_data; // vic_csr:out3_data -> vic_priority:in3_data + wire vic_csr_out4_valid; // vic_csr:out4_valid -> vic_priority:in4_valid + wire [18:0] vic_csr_out4_data; // vic_csr:out4_data -> vic_priority:in4_data + wire vic_csr_out5_valid; // vic_csr:out5_valid -> vic_priority:in5_valid + wire [18:0] vic_csr_out5_data; // vic_csr:out5_data -> vic_priority:in5_data + wire vic_csr_out6_valid; // vic_csr:out6_valid -> vic_priority:in6_valid + wire [18:0] vic_csr_out6_data; // vic_csr:out6_data -> vic_priority:in6_data + wire vic_csr_out7_valid; // vic_csr:out7_valid -> vic_priority:in7_valid + wire [18:0] vic_csr_out7_data; // vic_csr:out7_data -> vic_priority:in7_data + wire vic_priority_out_valid; // vic_priority:pri_valid -> vic_vector:in_valid + wire [18:0] vic_priority_out_data; // vic_priority:pri_data -> vic_vector:in_data + wire vic_csr_control_valid; // vic_csr:control_valid -> vic_vector:control_valid + wire [34:0] vic_csr_control_data; // vic_csr:control_data -> vic_vector:control_data + wire vic_vector_status_valid; // vic_vector:status_valid -> vic_csr:status_valid + wire [37:0] vic_vector_status_data; // vic_vector:status_data -> vic_csr:status_data + + altera_vic_csr #( + .NUMBER_OF_INT_PORTS (8), + .RRS_WIDTH (6), + .RIL_WIDTH (4), + .DAISY_CHAIN_ENABLE (0) + ) vic_csr ( + .inr_i1_irq (irq_input_irq), // i1.irq + .avs_s1_read (csr_access_read), // s1.read + .avs_s1_write (csr_access_write), // .write + .avs_s1_address (csr_access_address), // .address + .avs_s1_writedata (csr_access_writedata), // .writedata + .avs_s1_readdata (csr_access_readdata), // .readdata + .out0_valid (vic_csr_out0_valid), // out0.valid + .out0_data (vic_csr_out0_data), // .data + .out1_valid (vic_csr_out1_valid), // out1.valid + .out1_data (vic_csr_out1_data), // .data + .out2_valid (vic_csr_out2_valid), // out2.valid + .out2_data (vic_csr_out2_data), // .data + .out3_valid (vic_csr_out3_valid), // out3.valid + .out3_data (vic_csr_out3_data), // .data + .out4_valid (vic_csr_out4_valid), // out4.valid + .out4_data (vic_csr_out4_data), // .data + .out5_valid (vic_csr_out5_valid), // out5.valid + .out5_data (vic_csr_out5_data), // .data + .out6_valid (vic_csr_out6_valid), // out6.valid + .out6_data (vic_csr_out6_data), // .data + .out7_valid (vic_csr_out7_valid), // out7.valid + .out7_data (vic_csr_out7_data), // .data + .control_valid (vic_csr_control_valid), // control.valid + .control_data (vic_csr_control_data), // .data + .status_valid (vic_vector_status_valid), // status.valid + .status_data (vic_vector_status_data), // .data + .clk (clk_clk), // clk.clk + .reset_n (~clk_reset_reset), // clk_reset.reset_n + .dc_in_valid (1'b0), // (terminated) + .dc_in_data (45'b000000000000000000000000000000000000000000000), // (terminated) + .dc_out_valid (), // (terminated) + .dc_out_data (), // (terminated) + .out8_valid (), // (terminated) + .out8_data (), // (terminated) + .out9_valid (), // (terminated) + .out9_data (), // (terminated) + .out10_valid (), // (terminated) + .out10_data (), // (terminated) + .out11_valid (), // (terminated) + .out11_data (), // (terminated) + .out12_valid (), // (terminated) + .out12_data (), // (terminated) + .out13_valid (), // (terminated) + .out13_data (), // (terminated) + .out14_valid (), // (terminated) + .out14_data (), // (terminated) + .out15_valid (), // (terminated) + .out15_data (), // (terminated) + .out16_valid (), // (terminated) + .out16_data (), // (terminated) + .out17_valid (), // (terminated) + .out17_data (), // (terminated) + .out18_valid (), // (terminated) + .out18_data (), // (terminated) + .out19_valid (), // (terminated) + .out19_data (), // (terminated) + .out20_valid (), // (terminated) + .out20_data (), // (terminated) + .out21_valid (), // (terminated) + .out21_data (), // (terminated) + .out22_valid (), // (terminated) + .out22_data (), // (terminated) + .out23_valid (), // (terminated) + .out23_data (), // (terminated) + .out24_valid (), // (terminated) + .out24_data (), // (terminated) + .out25_valid (), // (terminated) + .out25_data (), // (terminated) + .out26_valid (), // (terminated) + .out26_data (), // (terminated) + .out27_valid (), // (terminated) + .out27_data (), // (terminated) + .out28_valid (), // (terminated) + .out28_data (), // (terminated) + .out29_valid (), // (terminated) + .out29_data (), // (terminated) + .out30_valid (), // (terminated) + .out30_data (), // (terminated) + .out31_valid (), // (terminated) + .out31_data (), // (terminated) + .out32_valid (), // (terminated) + .out32_data () // (terminated) + ); + + altera_vic_priority #( + .NUMBER_OF_INT_PORTS (8), + .PRIORITY_WIDTH (4), + .DATA_WIDTH (19) + ) vic_priority ( + .clk (clk_clk), // clk.clk + .reset_n (~clk_reset_reset), // clk_reset.reset_n + .in0_valid (vic_csr_out0_valid), // in0.valid + .in0_data (vic_csr_out0_data), // .data + .in1_valid (vic_csr_out1_valid), // in1.valid + .in1_data (vic_csr_out1_data), // .data + .in2_valid (vic_csr_out2_valid), // in2.valid + .in2_data (vic_csr_out2_data), // .data + .in3_valid (vic_csr_out3_valid), // in3.valid + .in3_data (vic_csr_out3_data), // .data + .in4_valid (vic_csr_out4_valid), // in4.valid + .in4_data (vic_csr_out4_data), // .data + .in5_valid (vic_csr_out5_valid), // in5.valid + .in5_data (vic_csr_out5_data), // .data + .in6_valid (vic_csr_out6_valid), // in6.valid + .in6_data (vic_csr_out6_data), // .data + .in7_valid (vic_csr_out7_valid), // in7.valid + .in7_data (vic_csr_out7_data), // .data + .pri_valid (vic_priority_out_valid), // out.valid + .pri_data (vic_priority_out_data), // .data + .in8_valid (1'b0), // (terminated) + .in8_data (19'b0000000000000000000), // (terminated) + .in9_valid (1'b0), // (terminated) + .in9_data (19'b0000000000000000000), // (terminated) + .in10_valid (1'b0), // (terminated) + .in10_data (19'b0000000000000000000), // (terminated) + .in11_valid (1'b0), // (terminated) + .in11_data (19'b0000000000000000000), // (terminated) + .in12_valid (1'b0), // (terminated) + .in12_data (19'b0000000000000000000), // (terminated) + .in13_valid (1'b0), // (terminated) + .in13_data (19'b0000000000000000000), // (terminated) + .in14_valid (1'b0), // (terminated) + .in14_data (19'b0000000000000000000), // (terminated) + .in15_valid (1'b0), // (terminated) + .in15_data (19'b0000000000000000000), // (terminated) + .in16_valid (1'b0), // (terminated) + .in16_data (19'b0000000000000000000), // (terminated) + .in17_valid (1'b0), // (terminated) + .in17_data (19'b0000000000000000000), // (terminated) + .in18_valid (1'b0), // (terminated) + .in18_data (19'b0000000000000000000), // (terminated) + .in19_valid (1'b0), // (terminated) + .in19_data (19'b0000000000000000000), // (terminated) + .in20_valid (1'b0), // (terminated) + .in20_data (19'b0000000000000000000), // (terminated) + .in21_valid (1'b0), // (terminated) + .in21_data (19'b0000000000000000000), // (terminated) + .in22_valid (1'b0), // (terminated) + .in22_data (19'b0000000000000000000), // (terminated) + .in23_valid (1'b0), // (terminated) + .in23_data (19'b0000000000000000000), // (terminated) + .in24_valid (1'b0), // (terminated) + .in24_data (19'b0000000000000000000), // (terminated) + .in25_valid (1'b0), // (terminated) + .in25_data (19'b0000000000000000000), // (terminated) + .in26_valid (1'b0), // (terminated) + .in26_data (19'b0000000000000000000), // (terminated) + .in27_valid (1'b0), // (terminated) + .in27_data (19'b0000000000000000000), // (terminated) + .in28_valid (1'b0), // (terminated) + .in28_data (19'b0000000000000000000), // (terminated) + .in29_valid (1'b0), // (terminated) + .in29_data (19'b0000000000000000000), // (terminated) + .in30_valid (1'b0), // (terminated) + .in30_data (19'b0000000000000000000), // (terminated) + .in31_valid (1'b0), // (terminated) + .in31_data (19'b0000000000000000000), // (terminated) + .in32_valid (1'b0), // (terminated) + .in32_data (19'b0000000000000000000) // (terminated) + ); + + altera_vic_vector #( + .DAISY_CHAIN_ENABLE (0) + ) vic_vector ( + .clk (clk_clk), // clk.clk + .reset_n (~clk_reset_reset), // clk_reset.reset_n + .in_valid (vic_priority_out_valid), // in.valid + .in_data (vic_priority_out_data), // .data + .control_valid (vic_csr_control_valid), // control.valid + .control_data (vic_csr_control_data), // .data + .status_valid (vic_vector_status_valid), // status.valid + .status_data (vic_vector_status_data), // .data + .out_valid (interrupt_controller_out_valid), // out.valid + .out_data (interrupt_controller_out_data), // .data + .dc_valid (1'b0), // (terminated) + .dc_data (32'b00000000000000000000000000000000) // (terminated) + ); + +endmodule diff --git a/examples/hdl4se_riscv/de1/vsim.wlf b/examples/hdl4se_riscv/de1/vsim.wlf index d6cae735293234edc55d2febd5aea57de9c160b3..e15c9dba1a27ab8d59a6f7782ae232c7d21fbc76 100644 GIT binary patch delta 69 zcmV~$ISqh7006;o{6FX*Ss6&8K8mdg3Q$3R8c@VcOnXdwSdKev*>xhB1j(h4QYxvX SkybkCWsp%OnPqudzvl?!~ESpy$lnb diff --git a/examples/hdl4se_riscv/test_code/main_v2.c b/examples/hdl4se_riscv/test_code/main_v2.c new file mode 100644 index 0000000..f6f7bff --- /dev/null +++ b/examples/hdl4se_riscv/test_code/main_v2.c @@ -0,0 +1,74 @@ + + +const unsigned int segcode[10] = +{ + 0x3F, + 0x06, + 0x5B,// 8'b01011011, + 0x4F,// 8'b01001111, + 0x66,// 8'b01100110, + 0x6d,// 8'b01101101, + 0x7d,// 8'b01111101, + 0x07,// 8'b00000111, + 0x7f,// 8'b01111111, + 0x6f,// 8'b01101111, +}; + +unsigned int num2seg(unsigned int num) +{ + return segcode[num % 10]; +} + +int main(int argc, char* argv[]) +{ + unsigned long long count, ctemp; + int countit = 1; + unsigned int* ledkey = (unsigned int*)0xF0000000; + unsigned int* leddata = (unsigned int*)0xf0000010; + unsigned int* uart = (unsigned int*)0xf0000100; + + count = 0; + leddata[0] = 0x6f7f077d; + leddata[1] = 0x6d664f5b; + uart[4] = 100000000 / 115200;/* set baudrate to 115200 */ + uart[1] = 'H'; + uart[1] = '\n'; + do { + unsigned int key; + unsigned int uartstate; + uartstate = uart[2]; + if (uartstate & 0x80) { /*rrdy*/ + uart[1] = uart[0]; /* writeback */ + continue; + } + key = *ledkey; + if (key & 1) { + count = 0; + } + else if (key & 2) { + countit = 0; + } + else if (key & 4) { + countit = 1; + } + if (countit) + count++; + + ctemp = count; + leddata[0] = num2seg(ctemp) | + ((num2seg(ctemp / 10ll)) << 8) | + ((num2seg(ctemp / 100ll)) << 16) | + ((num2seg(ctemp / 1000ll)) << 24); + ctemp /= 10000ll; + leddata[1] = num2seg(ctemp) | + ((num2seg(ctemp / 10ll)) << 8) | + ((num2seg(ctemp / 100ll)) << 16) | + ((num2seg(ctemp / 1000ll)) << 24); + ctemp /= 10000ll; + leddata[2] = num2seg(ctemp) | + ((num2seg(ctemp / 10ll)) << 8); + + + } while (1); + return 1; +} -- GitLab